1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_rxtx.h" 7 #include "axgbe_ethdev.h" 8 #include "axgbe_common.h" 9 #include "axgbe_phy.h" 10 11 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); 12 static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev); 13 static int axgbe_dev_configure(struct rte_eth_dev *dev); 14 static int axgbe_dev_start(struct rte_eth_dev *dev); 15 static void axgbe_dev_stop(struct rte_eth_dev *dev); 16 static void axgbe_dev_interrupt_handler(void *param); 17 static void axgbe_dev_close(struct rte_eth_dev *dev); 18 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 19 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 20 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 21 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 22 static int axgbe_dev_link_update(struct rte_eth_dev *dev, 23 int wait_to_complete); 24 static int axgbe_dev_stats_get(struct rte_eth_dev *dev, 25 struct rte_eth_stats *stats); 26 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev); 27 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev, 28 struct rte_eth_xstat *stats, 29 unsigned int n); 30 static int 31 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 32 struct rte_eth_xstat_name *xstats_names, 33 unsigned int size); 34 static int 35 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 36 const uint64_t *ids, 37 uint64_t *values, 38 unsigned int n); 39 static int 40 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 41 struct rte_eth_xstat_name *xstats_names, 42 const uint64_t *ids, 43 unsigned int size); 44 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev); 45 static int axgbe_dev_info_get(struct rte_eth_dev *dev, 46 struct rte_eth_dev_info *dev_info); 47 48 struct axgbe_xstats { 49 char name[RTE_ETH_XSTATS_NAME_SIZE]; 50 int offset; 51 }; 52 53 #define AXGMAC_MMC_STAT(_string, _var) \ 54 { _string, \ 55 offsetof(struct axgbe_mmc_stats, _var), \ 56 } 57 58 static const struct axgbe_xstats axgbe_xstats_strings[] = { 59 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb), 60 AXGMAC_MMC_STAT("tx_packets", txframecount_gb), 61 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb), 62 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb), 63 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb), 64 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g), 65 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb), 66 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb), 67 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb), 68 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb), 69 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb), 70 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb), 71 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror), 72 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes), 73 74 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb), 75 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb), 76 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g), 77 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g), 78 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g), 79 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb), 80 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb), 81 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb), 82 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb), 83 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb), 84 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb), 85 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb), 86 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g), 87 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g), 88 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror), 89 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror), 90 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror), 91 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror), 92 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype), 93 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow), 94 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror), 95 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes), 96 }; 97 98 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings) 99 100 /* The set of PCI devices this driver supports */ 101 #define AMD_PCI_VENDOR_ID 0x1022 102 #define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0 103 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 104 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459 105 106 int axgbe_logtype_init; 107 int axgbe_logtype_driver; 108 109 static const struct rte_pci_id pci_id_axgbe_map[] = { 110 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)}, 111 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)}, 112 { .vendor_id = 0, }, 113 }; 114 115 static struct axgbe_version_data axgbe_v2a = { 116 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 117 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 118 .mmc_64bit = 1, 119 .tx_max_fifo_size = 229376, 120 .rx_max_fifo_size = 229376, 121 .tx_tstamp_workaround = 1, 122 .ecc_support = 1, 123 .i2c_support = 1, 124 .an_cdr_workaround = 1, 125 }; 126 127 static struct axgbe_version_data axgbe_v2b = { 128 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 129 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 130 .mmc_64bit = 1, 131 .tx_max_fifo_size = 65536, 132 .rx_max_fifo_size = 65536, 133 .tx_tstamp_workaround = 1, 134 .ecc_support = 1, 135 .i2c_support = 1, 136 .an_cdr_workaround = 1, 137 }; 138 139 static const struct rte_eth_desc_lim rx_desc_lim = { 140 .nb_max = AXGBE_MAX_RING_DESC, 141 .nb_min = AXGBE_MIN_RING_DESC, 142 .nb_align = 8, 143 }; 144 145 static const struct rte_eth_desc_lim tx_desc_lim = { 146 .nb_max = AXGBE_MAX_RING_DESC, 147 .nb_min = AXGBE_MIN_RING_DESC, 148 .nb_align = 8, 149 }; 150 151 static const struct eth_dev_ops axgbe_eth_dev_ops = { 152 .dev_configure = axgbe_dev_configure, 153 .dev_start = axgbe_dev_start, 154 .dev_stop = axgbe_dev_stop, 155 .dev_close = axgbe_dev_close, 156 .promiscuous_enable = axgbe_dev_promiscuous_enable, 157 .promiscuous_disable = axgbe_dev_promiscuous_disable, 158 .allmulticast_enable = axgbe_dev_allmulticast_enable, 159 .allmulticast_disable = axgbe_dev_allmulticast_disable, 160 .link_update = axgbe_dev_link_update, 161 .stats_get = axgbe_dev_stats_get, 162 .stats_reset = axgbe_dev_stats_reset, 163 .xstats_get = axgbe_dev_xstats_get, 164 .xstats_reset = axgbe_dev_xstats_reset, 165 .xstats_get_names = axgbe_dev_xstats_get_names, 166 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id, 167 .xstats_get_by_id = axgbe_dev_xstats_get_by_id, 168 .dev_infos_get = axgbe_dev_info_get, 169 .rx_queue_setup = axgbe_dev_rx_queue_setup, 170 .rx_queue_release = axgbe_dev_rx_queue_release, 171 .tx_queue_setup = axgbe_dev_tx_queue_setup, 172 .tx_queue_release = axgbe_dev_tx_queue_release, 173 }; 174 175 static int axgbe_phy_reset(struct axgbe_port *pdata) 176 { 177 pdata->phy_link = -1; 178 pdata->phy_speed = SPEED_UNKNOWN; 179 return pdata->phy_if.phy_reset(pdata); 180 } 181 182 /* 183 * Interrupt handler triggered by NIC for handling 184 * specific interrupt. 185 * 186 * @param handle 187 * Pointer to interrupt handle. 188 * @param param 189 * The address of parameter (struct rte_eth_dev *) regsitered before. 190 * 191 * @return 192 * void 193 */ 194 static void 195 axgbe_dev_interrupt_handler(void *param) 196 { 197 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 198 struct axgbe_port *pdata = dev->data->dev_private; 199 unsigned int dma_isr, dma_ch_isr; 200 201 pdata->phy_if.an_isr(pdata); 202 /*DMA related interrupts*/ 203 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR); 204 if (dma_isr) { 205 if (dma_isr & 1) { 206 dma_ch_isr = 207 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *) 208 pdata->rx_queues[0], 209 DMA_CH_SR); 210 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *) 211 pdata->rx_queues[0], 212 DMA_CH_SR, dma_ch_isr); 213 } 214 } 215 /* Unmask interrupts since disabled after generation */ 216 rte_intr_ack(&pdata->pci_dev->intr_handle); 217 } 218 219 /* 220 * Configure device link speed and setup link. 221 * It returns 0 on success. 222 */ 223 static int 224 axgbe_dev_configure(struct rte_eth_dev *dev) 225 { 226 struct axgbe_port *pdata = dev->data->dev_private; 227 /* Checksum offload to hardware */ 228 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads & 229 DEV_RX_OFFLOAD_CHECKSUM; 230 return 0; 231 } 232 233 static int 234 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev) 235 { 236 struct axgbe_port *pdata = dev->data->dev_private; 237 238 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 239 pdata->rss_enable = 1; 240 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE) 241 pdata->rss_enable = 0; 242 else 243 return -1; 244 return 0; 245 } 246 247 static int 248 axgbe_dev_start(struct rte_eth_dev *dev) 249 { 250 struct axgbe_port *pdata = dev->data->dev_private; 251 int ret; 252 253 PMD_INIT_FUNC_TRACE(); 254 255 /* Multiqueue RSS */ 256 ret = axgbe_dev_rx_mq_config(dev); 257 if (ret) { 258 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n"); 259 return ret; 260 } 261 ret = axgbe_phy_reset(pdata); 262 if (ret) { 263 PMD_DRV_LOG(ERR, "phy reset failed\n"); 264 return ret; 265 } 266 ret = pdata->hw_if.init(pdata); 267 if (ret) { 268 PMD_DRV_LOG(ERR, "dev_init failed\n"); 269 return ret; 270 } 271 272 /* enable uio/vfio intr/eventfd mapping */ 273 rte_intr_enable(&pdata->pci_dev->intr_handle); 274 275 /* phy start*/ 276 pdata->phy_if.phy_start(pdata); 277 axgbe_dev_enable_tx(dev); 278 axgbe_dev_enable_rx(dev); 279 280 axgbe_clear_bit(AXGBE_STOPPED, &pdata->dev_state); 281 axgbe_clear_bit(AXGBE_DOWN, &pdata->dev_state); 282 return 0; 283 } 284 285 /* Stop device: disable rx and tx functions to allow for reconfiguring. */ 286 static void 287 axgbe_dev_stop(struct rte_eth_dev *dev) 288 { 289 struct axgbe_port *pdata = dev->data->dev_private; 290 291 PMD_INIT_FUNC_TRACE(); 292 293 rte_intr_disable(&pdata->pci_dev->intr_handle); 294 295 if (axgbe_test_bit(AXGBE_STOPPED, &pdata->dev_state)) 296 return; 297 298 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state); 299 axgbe_dev_disable_tx(dev); 300 axgbe_dev_disable_rx(dev); 301 302 pdata->phy_if.phy_stop(pdata); 303 pdata->hw_if.exit(pdata); 304 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); 305 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state); 306 } 307 308 /* Clear all resources like TX/RX queues. */ 309 static void 310 axgbe_dev_close(struct rte_eth_dev *dev) 311 { 312 axgbe_dev_clear_queues(dev); 313 } 314 315 static int 316 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 317 { 318 struct axgbe_port *pdata = dev->data->dev_private; 319 320 PMD_INIT_FUNC_TRACE(); 321 322 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); 323 324 return 0; 325 } 326 327 static int 328 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 329 { 330 struct axgbe_port *pdata = dev->data->dev_private; 331 332 PMD_INIT_FUNC_TRACE(); 333 334 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); 335 336 return 0; 337 } 338 339 static int 340 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 341 { 342 struct axgbe_port *pdata = dev->data->dev_private; 343 344 PMD_INIT_FUNC_TRACE(); 345 346 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 347 return 0; 348 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1); 349 350 return 0; 351 } 352 353 static int 354 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 355 { 356 struct axgbe_port *pdata = dev->data->dev_private; 357 358 PMD_INIT_FUNC_TRACE(); 359 360 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 361 return 0; 362 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0); 363 364 return 0; 365 } 366 367 /* return 0 means link status changed, -1 means not changed */ 368 static int 369 axgbe_dev_link_update(struct rte_eth_dev *dev, 370 int wait_to_complete __rte_unused) 371 { 372 struct axgbe_port *pdata = dev->data->dev_private; 373 struct rte_eth_link link; 374 int ret = 0; 375 376 PMD_INIT_FUNC_TRACE(); 377 rte_delay_ms(800); 378 379 pdata->phy_if.phy_status(pdata); 380 381 memset(&link, 0, sizeof(struct rte_eth_link)); 382 link.link_duplex = pdata->phy.duplex; 383 link.link_status = pdata->phy_link; 384 link.link_speed = pdata->phy_speed; 385 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 386 ETH_LINK_SPEED_FIXED); 387 ret = rte_eth_linkstatus_set(dev, &link); 388 if (ret == -1) 389 PMD_DRV_LOG(ERR, "No change in link status\n"); 390 391 return ret; 392 } 393 394 static void axgbe_read_mmc_stats(struct axgbe_port *pdata) 395 { 396 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 397 398 /* Freeze counters */ 399 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 400 401 /* Tx counters */ 402 stats->txoctetcount_gb += 403 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO); 404 stats->txoctetcount_gb += 405 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32); 406 407 stats->txframecount_gb += 408 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO); 409 stats->txframecount_gb += 410 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32); 411 412 stats->txbroadcastframes_g += 413 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO); 414 stats->txbroadcastframes_g += 415 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32); 416 417 stats->txmulticastframes_g += 418 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO); 419 stats->txmulticastframes_g += 420 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32); 421 422 stats->tx64octets_gb += 423 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO); 424 stats->tx64octets_gb += 425 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32); 426 427 stats->tx65to127octets_gb += 428 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO); 429 stats->tx65to127octets_gb += 430 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32); 431 432 stats->tx128to255octets_gb += 433 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO); 434 stats->tx128to255octets_gb += 435 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32); 436 437 stats->tx256to511octets_gb += 438 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO); 439 stats->tx256to511octets_gb += 440 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32); 441 442 stats->tx512to1023octets_gb += 443 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO); 444 stats->tx512to1023octets_gb += 445 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32); 446 447 stats->tx1024tomaxoctets_gb += 448 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 449 stats->tx1024tomaxoctets_gb += 450 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32); 451 452 stats->txunicastframes_gb += 453 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO); 454 stats->txunicastframes_gb += 455 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32); 456 457 stats->txmulticastframes_gb += 458 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 459 stats->txmulticastframes_gb += 460 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32); 461 462 stats->txbroadcastframes_g += 463 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 464 stats->txbroadcastframes_g += 465 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32); 466 467 stats->txunderflowerror += 468 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO); 469 stats->txunderflowerror += 470 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32); 471 472 stats->txoctetcount_g += 473 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO); 474 stats->txoctetcount_g += 475 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32); 476 477 stats->txframecount_g += 478 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO); 479 stats->txframecount_g += 480 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32); 481 482 stats->txpauseframes += 483 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO); 484 stats->txpauseframes += 485 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32); 486 487 stats->txvlanframes_g += 488 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO); 489 stats->txvlanframes_g += 490 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32); 491 492 /* Rx counters */ 493 stats->rxframecount_gb += 494 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO); 495 stats->rxframecount_gb += 496 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32); 497 498 stats->rxoctetcount_gb += 499 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO); 500 stats->rxoctetcount_gb += 501 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32); 502 503 stats->rxoctetcount_g += 504 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO); 505 stats->rxoctetcount_g += 506 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32); 507 508 stats->rxbroadcastframes_g += 509 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO); 510 stats->rxbroadcastframes_g += 511 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32); 512 513 stats->rxmulticastframes_g += 514 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO); 515 stats->rxmulticastframes_g += 516 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32); 517 518 stats->rxcrcerror += 519 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO); 520 stats->rxcrcerror += 521 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32); 522 523 stats->rxrunterror += 524 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR); 525 526 stats->rxjabbererror += 527 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR); 528 529 stats->rxundersize_g += 530 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G); 531 532 stats->rxoversize_g += 533 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G); 534 535 stats->rx64octets_gb += 536 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO); 537 stats->rx64octets_gb += 538 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32); 539 540 stats->rx65to127octets_gb += 541 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO); 542 stats->rx65to127octets_gb += 543 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32); 544 545 stats->rx128to255octets_gb += 546 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO); 547 stats->rx128to255octets_gb += 548 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32); 549 550 stats->rx256to511octets_gb += 551 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO); 552 stats->rx256to511octets_gb += 553 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32); 554 555 stats->rx512to1023octets_gb += 556 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO); 557 stats->rx512to1023octets_gb += 558 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32); 559 560 stats->rx1024tomaxoctets_gb += 561 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 562 stats->rx1024tomaxoctets_gb += 563 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32); 564 565 stats->rxunicastframes_g += 566 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO); 567 stats->rxunicastframes_g += 568 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32); 569 570 stats->rxlengtherror += 571 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO); 572 stats->rxlengtherror += 573 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32); 574 575 stats->rxoutofrangetype += 576 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO); 577 stats->rxoutofrangetype += 578 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32); 579 580 stats->rxpauseframes += 581 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO); 582 stats->rxpauseframes += 583 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32); 584 585 stats->rxfifooverflow += 586 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO); 587 stats->rxfifooverflow += 588 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32); 589 590 stats->rxvlanframes_gb += 591 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO); 592 stats->rxvlanframes_gb += 593 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32); 594 595 stats->rxwatchdogerror += 596 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR); 597 598 /* Un-freeze counters */ 599 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 600 } 601 602 static int 603 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 604 unsigned int n) 605 { 606 struct axgbe_port *pdata = dev->data->dev_private; 607 unsigned int i; 608 609 if (!stats) 610 return 0; 611 612 axgbe_read_mmc_stats(pdata); 613 614 for (i = 0; i < n && i < AXGBE_XSTATS_COUNT; i++) { 615 stats[i].id = i; 616 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats + 617 axgbe_xstats_strings[i].offset); 618 } 619 620 return i; 621 } 622 623 static int 624 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 625 struct rte_eth_xstat_name *xstats_names, 626 unsigned int n) 627 { 628 unsigned int i; 629 630 if (n >= AXGBE_XSTATS_COUNT && xstats_names) { 631 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) { 632 snprintf(xstats_names[i].name, 633 RTE_ETH_XSTATS_NAME_SIZE, "%s", 634 axgbe_xstats_strings[i].name); 635 } 636 } 637 638 return AXGBE_XSTATS_COUNT; 639 } 640 641 static int 642 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 643 uint64_t *values, unsigned int n) 644 { 645 unsigned int i; 646 uint64_t values_copy[AXGBE_XSTATS_COUNT]; 647 648 if (!ids) { 649 struct axgbe_port *pdata = dev->data->dev_private; 650 651 if (n < AXGBE_XSTATS_COUNT) 652 return AXGBE_XSTATS_COUNT; 653 654 axgbe_read_mmc_stats(pdata); 655 656 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 657 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats + 658 axgbe_xstats_strings[i].offset); 659 } 660 661 return i; 662 } 663 664 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT); 665 666 for (i = 0; i < n; i++) { 667 if (ids[i] >= AXGBE_XSTATS_COUNT) { 668 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 669 return -1; 670 } 671 values[i] = values_copy[ids[i]]; 672 } 673 return n; 674 } 675 676 static int 677 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 678 struct rte_eth_xstat_name *xstats_names, 679 const uint64_t *ids, 680 unsigned int size) 681 { 682 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT]; 683 unsigned int i; 684 685 if (!ids) 686 return axgbe_dev_xstats_get_names(dev, xstats_names, size); 687 688 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size); 689 690 for (i = 0; i < size; i++) { 691 if (ids[i] >= AXGBE_XSTATS_COUNT) { 692 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 693 return -1; 694 } 695 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 696 } 697 return size; 698 } 699 700 static int 701 axgbe_dev_xstats_reset(struct rte_eth_dev *dev) 702 { 703 struct axgbe_port *pdata = dev->data->dev_private; 704 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 705 706 /* MMC registers are configured for reset on read */ 707 axgbe_read_mmc_stats(pdata); 708 709 /* Reset stats */ 710 memset(stats, 0, sizeof(*stats)); 711 712 return 0; 713 } 714 715 static int 716 axgbe_dev_stats_get(struct rte_eth_dev *dev, 717 struct rte_eth_stats *stats) 718 { 719 struct axgbe_rx_queue *rxq; 720 struct axgbe_tx_queue *txq; 721 struct axgbe_port *pdata = dev->data->dev_private; 722 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats; 723 unsigned int i; 724 725 axgbe_read_mmc_stats(pdata); 726 727 stats->imissed = mmc_stats->rxfifooverflow; 728 729 for (i = 0; i < dev->data->nb_rx_queues; i++) { 730 rxq = dev->data->rx_queues[i]; 731 stats->q_ipackets[i] = rxq->pkts; 732 stats->ipackets += rxq->pkts; 733 stats->q_ibytes[i] = rxq->bytes; 734 stats->ibytes += rxq->bytes; 735 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed; 736 stats->q_errors[i] = rxq->errors + rxq->rx_mbuf_alloc_failed; 737 stats->ierrors += rxq->errors; 738 } 739 740 for (i = 0; i < dev->data->nb_tx_queues; i++) { 741 txq = dev->data->tx_queues[i]; 742 stats->q_opackets[i] = txq->pkts; 743 stats->opackets += txq->pkts; 744 stats->q_obytes[i] = txq->bytes; 745 stats->obytes += txq->bytes; 746 stats->oerrors += txq->errors; 747 } 748 749 return 0; 750 } 751 752 static int 753 axgbe_dev_stats_reset(struct rte_eth_dev *dev) 754 { 755 struct axgbe_rx_queue *rxq; 756 struct axgbe_tx_queue *txq; 757 unsigned int i; 758 759 for (i = 0; i < dev->data->nb_rx_queues; i++) { 760 rxq = dev->data->rx_queues[i]; 761 rxq->pkts = 0; 762 rxq->bytes = 0; 763 rxq->errors = 0; 764 rxq->rx_mbuf_alloc_failed = 0; 765 } 766 for (i = 0; i < dev->data->nb_tx_queues; i++) { 767 txq = dev->data->tx_queues[i]; 768 txq->pkts = 0; 769 txq->bytes = 0; 770 txq->errors = 0; 771 } 772 773 return 0; 774 } 775 776 static int 777 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 778 { 779 struct axgbe_port *pdata = dev->data->dev_private; 780 781 dev_info->max_rx_queues = pdata->rx_ring_count; 782 dev_info->max_tx_queues = pdata->tx_ring_count; 783 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE; 784 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE; 785 dev_info->max_mac_addrs = AXGBE_MAX_MAC_ADDRS; 786 dev_info->speed_capa = ETH_LINK_SPEED_10G; 787 788 dev_info->rx_offload_capa = 789 DEV_RX_OFFLOAD_IPV4_CKSUM | 790 DEV_RX_OFFLOAD_UDP_CKSUM | 791 DEV_RX_OFFLOAD_TCP_CKSUM | 792 DEV_RX_OFFLOAD_KEEP_CRC; 793 794 dev_info->tx_offload_capa = 795 DEV_TX_OFFLOAD_IPV4_CKSUM | 796 DEV_TX_OFFLOAD_UDP_CKSUM | 797 DEV_TX_OFFLOAD_TCP_CKSUM; 798 799 if (pdata->hw_feat.rss) { 800 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD; 801 dev_info->reta_size = pdata->hw_feat.hash_table_size; 802 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE; 803 } 804 805 dev_info->rx_desc_lim = rx_desc_lim; 806 dev_info->tx_desc_lim = tx_desc_lim; 807 808 dev_info->default_rxconf = (struct rte_eth_rxconf) { 809 .rx_free_thresh = AXGBE_RX_FREE_THRESH, 810 }; 811 812 dev_info->default_txconf = (struct rte_eth_txconf) { 813 .tx_free_thresh = AXGBE_TX_FREE_THRESH, 814 }; 815 816 return 0; 817 } 818 819 static void axgbe_get_all_hw_features(struct axgbe_port *pdata) 820 { 821 unsigned int mac_hfr0, mac_hfr1, mac_hfr2; 822 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 823 824 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R); 825 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R); 826 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R); 827 828 memset(hw_feat, 0, sizeof(*hw_feat)); 829 830 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR); 831 832 /* Hardware feature register 0 */ 833 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 834 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 835 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 836 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 837 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 838 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 839 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 840 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 841 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 842 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 843 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 844 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 845 ADDMACADRSEL); 846 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 847 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 848 849 /* Hardware feature register 1 */ 850 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 851 RXFIFOSIZE); 852 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 853 TXFIFOSIZE); 854 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1, 855 MAC_HWF1R, ADVTHWORD); 856 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 857 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 858 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 859 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 860 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 861 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 862 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 863 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 864 HASHTBLSZ); 865 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 866 L3L4FNUM); 867 868 /* Hardware feature register 2 */ 869 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 870 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 871 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 872 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 873 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 874 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, 875 AUXSNAPNUM); 876 877 /* Translate the Hash Table size into actual number */ 878 switch (hw_feat->hash_table_size) { 879 case 0: 880 break; 881 case 1: 882 hw_feat->hash_table_size = 64; 883 break; 884 case 2: 885 hw_feat->hash_table_size = 128; 886 break; 887 case 3: 888 hw_feat->hash_table_size = 256; 889 break; 890 } 891 892 /* Translate the address width setting into actual number */ 893 switch (hw_feat->dma_width) { 894 case 0: 895 hw_feat->dma_width = 32; 896 break; 897 case 1: 898 hw_feat->dma_width = 40; 899 break; 900 case 2: 901 hw_feat->dma_width = 48; 902 break; 903 default: 904 hw_feat->dma_width = 32; 905 } 906 907 /* The Queue, Channel and TC counts are zero based so increment them 908 * to get the actual number 909 */ 910 hw_feat->rx_q_cnt++; 911 hw_feat->tx_q_cnt++; 912 hw_feat->rx_ch_cnt++; 913 hw_feat->tx_ch_cnt++; 914 hw_feat->tc_cnt++; 915 916 /* Translate the fifo sizes into actual numbers */ 917 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 918 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 919 } 920 921 static void axgbe_init_all_fptrs(struct axgbe_port *pdata) 922 { 923 axgbe_init_function_ptrs_dev(&pdata->hw_if); 924 axgbe_init_function_ptrs_phy(&pdata->phy_if); 925 axgbe_init_function_ptrs_i2c(&pdata->i2c_if); 926 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 927 } 928 929 static void axgbe_set_counts(struct axgbe_port *pdata) 930 { 931 /* Set all the function pointers */ 932 axgbe_init_all_fptrs(pdata); 933 934 /* Populate the hardware features */ 935 axgbe_get_all_hw_features(pdata); 936 937 /* Set default max values if not provided */ 938 if (!pdata->tx_max_channel_count) 939 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 940 if (!pdata->rx_max_channel_count) 941 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 942 943 if (!pdata->tx_max_q_count) 944 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 945 if (!pdata->rx_max_q_count) 946 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 947 948 /* Calculate the number of Tx and Rx rings to be created 949 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 950 * the number of Tx queues to the number of Tx channels 951 * enabled 952 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 953 * number of Rx queues or maximum allowed 954 */ 955 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt, 956 pdata->tx_max_channel_count); 957 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count, 958 pdata->tx_max_q_count); 959 960 pdata->tx_q_count = pdata->tx_ring_count; 961 962 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt, 963 pdata->rx_max_channel_count); 964 965 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt, 966 pdata->rx_max_q_count); 967 } 968 969 static void axgbe_default_config(struct axgbe_port *pdata) 970 { 971 pdata->pblx8 = DMA_PBL_X8_ENABLE; 972 pdata->tx_sf_mode = MTL_TSF_ENABLE; 973 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 974 pdata->tx_pbl = DMA_PBL_32; 975 pdata->tx_osp_mode = DMA_OSP_ENABLE; 976 pdata->rx_sf_mode = MTL_RSF_ENABLE; 977 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 978 pdata->rx_pbl = DMA_PBL_32; 979 pdata->pause_autoneg = 1; 980 pdata->tx_pause = 0; 981 pdata->rx_pause = 0; 982 pdata->phy_speed = SPEED_UNKNOWN; 983 pdata->power_down = 0; 984 } 985 986 static int 987 pci_device_cmp(const struct rte_device *dev, const void *_pci_id) 988 { 989 const struct rte_pci_device *pdev = RTE_DEV_TO_PCI_CONST(dev); 990 const struct rte_pci_id *pcid = _pci_id; 991 992 if (pdev->id.vendor_id == AMD_PCI_VENDOR_ID && 993 pdev->id.device_id == pcid->device_id) 994 return 0; 995 return 1; 996 } 997 998 static bool 999 pci_search_device(int device_id) 1000 { 1001 struct rte_bus *pci_bus; 1002 struct rte_pci_id dev_id; 1003 1004 dev_id.device_id = device_id; 1005 pci_bus = rte_bus_find_by_name("pci"); 1006 return (pci_bus != NULL) && 1007 (pci_bus->find_device(NULL, pci_device_cmp, &dev_id) != NULL); 1008 } 1009 1010 /* 1011 * It returns 0 on success. 1012 */ 1013 static int 1014 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) 1015 { 1016 PMD_INIT_FUNC_TRACE(); 1017 struct axgbe_port *pdata; 1018 struct rte_pci_device *pci_dev; 1019 uint32_t reg, mac_lo, mac_hi; 1020 int ret; 1021 1022 eth_dev->dev_ops = &axgbe_eth_dev_ops; 1023 eth_dev->rx_pkt_burst = &axgbe_recv_pkts; 1024 1025 /* 1026 * For secondary processes, we don't initialise any further as primary 1027 * has already done this work. 1028 */ 1029 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1030 return 0; 1031 1032 pdata = eth_dev->data->dev_private; 1033 /* initial state */ 1034 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state); 1035 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state); 1036 pdata->eth_dev = eth_dev; 1037 1038 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 1039 pdata->pci_dev = pci_dev; 1040 1041 /* 1042 * Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE 1043 */ 1044 if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) { 1045 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; 1046 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; 1047 } else { 1048 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 1049 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 1050 } 1051 1052 pdata->xgmac_regs = 1053 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; 1054 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs 1055 + AXGBE_MAC_PROP_OFFSET); 1056 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs 1057 + AXGBE_I2C_CTRL_OFFSET); 1058 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; 1059 1060 /* version specific driver data*/ 1061 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A) 1062 pdata->vdata = &axgbe_v2a; 1063 else 1064 pdata->vdata = &axgbe_v2b; 1065 1066 /* Configure the PCS indirect addressing support */ 1067 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); 1068 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 1069 pdata->xpcs_window <<= 6; 1070 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 1071 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 1072 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 1073 1074 PMD_INIT_LOG(DEBUG, 1075 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, 1076 pdata->xpcs_window_size, pdata->xpcs_window_mask); 1077 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 1078 1079 /* Retrieve the MAC address */ 1080 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 1081 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 1082 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff; 1083 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff; 1084 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff; 1085 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff; 1086 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff; 1087 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff; 1088 1089 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", 1090 RTE_ETHER_ADDR_LEN, 0); 1091 if (!eth_dev->data->mac_addrs) { 1092 PMD_INIT_LOG(ERR, 1093 "Failed to alloc %u bytes needed to store MAC addr tbl", 1094 RTE_ETHER_ADDR_LEN); 1095 return -ENOMEM; 1096 } 1097 1098 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr)) 1099 rte_eth_random_addr(pdata->mac_addr.addr_bytes); 1100 1101 /* Copy the permanent MAC address */ 1102 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]); 1103 1104 /* Clock settings */ 1105 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ; 1106 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 1107 1108 /* Set the DMA coherency values */ 1109 pdata->coherent = 1; 1110 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN; 1111 pdata->arcache = AXGBE_DMA_OS_ARCACHE; 1112 pdata->awcache = AXGBE_DMA_OS_AWCACHE; 1113 1114 /* Set the maximum channels and queues */ 1115 reg = XP_IOREAD(pdata, XP_PROP_1); 1116 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA); 1117 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA); 1118 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES); 1119 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES); 1120 1121 /* Set the hardware channel and queue counts */ 1122 axgbe_set_counts(pdata); 1123 1124 /* Set the maximum fifo amounts */ 1125 reg = XP_IOREAD(pdata, XP_PROP_2); 1126 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE); 1127 pdata->tx_max_fifo_size *= 16384; 1128 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size, 1129 pdata->vdata->tx_max_fifo_size); 1130 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE); 1131 pdata->rx_max_fifo_size *= 16384; 1132 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size, 1133 pdata->vdata->rx_max_fifo_size); 1134 /* Issue software reset to DMA */ 1135 ret = pdata->hw_if.exit(pdata); 1136 if (ret) 1137 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n"); 1138 1139 /* Set default configuration data */ 1140 axgbe_default_config(pdata); 1141 1142 /* Set default max values if not provided */ 1143 if (!pdata->tx_max_fifo_size) 1144 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 1145 if (!pdata->rx_max_fifo_size) 1146 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 1147 1148 pdata->tx_desc_count = AXGBE_MAX_RING_DESC; 1149 pdata->rx_desc_count = AXGBE_MAX_RING_DESC; 1150 pthread_mutex_init(&pdata->xpcs_mutex, NULL); 1151 pthread_mutex_init(&pdata->i2c_mutex, NULL); 1152 pthread_mutex_init(&pdata->an_mutex, NULL); 1153 pthread_mutex_init(&pdata->phy_mutex, NULL); 1154 1155 ret = pdata->phy_if.phy_init(pdata); 1156 if (ret) { 1157 rte_free(eth_dev->data->mac_addrs); 1158 eth_dev->data->mac_addrs = NULL; 1159 return ret; 1160 } 1161 1162 rte_intr_callback_register(&pci_dev->intr_handle, 1163 axgbe_dev_interrupt_handler, 1164 (void *)eth_dev); 1165 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 1166 eth_dev->data->port_id, pci_dev->id.vendor_id, 1167 pci_dev->id.device_id); 1168 1169 return 0; 1170 } 1171 1172 static int 1173 eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1174 { 1175 struct rte_pci_device *pci_dev; 1176 1177 PMD_INIT_FUNC_TRACE(); 1178 1179 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1180 return 0; 1181 1182 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 1183 eth_dev->dev_ops = NULL; 1184 eth_dev->rx_pkt_burst = NULL; 1185 eth_dev->tx_pkt_burst = NULL; 1186 axgbe_dev_clear_queues(eth_dev); 1187 1188 /* disable uio intr before callback unregister */ 1189 rte_intr_disable(&pci_dev->intr_handle); 1190 rte_intr_callback_unregister(&pci_dev->intr_handle, 1191 axgbe_dev_interrupt_handler, 1192 (void *)eth_dev); 1193 1194 return 0; 1195 } 1196 1197 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1198 struct rte_pci_device *pci_dev) 1199 { 1200 return rte_eth_dev_pci_generic_probe(pci_dev, 1201 sizeof(struct axgbe_port), eth_axgbe_dev_init); 1202 } 1203 1204 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev) 1205 { 1206 return rte_eth_dev_pci_generic_remove(pci_dev, eth_axgbe_dev_uninit); 1207 } 1208 1209 static struct rte_pci_driver rte_axgbe_pmd = { 1210 .id_table = pci_id_axgbe_map, 1211 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1212 .probe = eth_axgbe_pci_probe, 1213 .remove = eth_axgbe_pci_remove, 1214 }; 1215 1216 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd); 1217 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map); 1218 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1219 1220 RTE_INIT(axgbe_init_log) 1221 { 1222 axgbe_logtype_init = rte_log_register("pmd.net.axgbe.init"); 1223 if (axgbe_logtype_init >= 0) 1224 rte_log_set_level(axgbe_logtype_init, RTE_LOG_NOTICE); 1225 axgbe_logtype_driver = rte_log_register("pmd.net.axgbe.driver"); 1226 if (axgbe_logtype_driver >= 0) 1227 rte_log_set_level(axgbe_logtype_driver, RTE_LOG_NOTICE); 1228 } 1229