1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_rxtx.h" 7 #include "axgbe_ethdev.h" 8 #include "axgbe_common.h" 9 #include "axgbe_phy.h" 10 #include "axgbe_regs.h" 11 #include "rte_time.h" 12 13 #include "eal_filesystem.h" 14 15 #include <rte_vect.h> 16 17 #ifdef RTE_ARCH_X86 18 #include <cpuid.h> 19 #else 20 #define __cpuid(n, a, b, c, d) 21 #endif 22 23 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); 24 static int axgbe_dev_configure(struct rte_eth_dev *dev); 25 static int axgbe_dev_start(struct rte_eth_dev *dev); 26 static int axgbe_dev_stop(struct rte_eth_dev *dev); 27 static void axgbe_dev_interrupt_handler(void *param); 28 static int axgbe_dev_close(struct rte_eth_dev *dev); 29 static int axgbe_dev_reset(struct rte_eth_dev *dev); 30 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 31 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 32 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 33 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 34 static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, 35 struct rte_ether_addr *mac_addr); 36 static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, 37 struct rte_ether_addr *mac_addr, 38 uint32_t index, 39 uint32_t vmdq); 40 static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 41 static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 42 struct rte_ether_addr *mc_addr_set, 43 uint32_t nb_mc_addr); 44 static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 45 struct rte_ether_addr *mac_addr, 46 uint8_t add); 47 static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, 48 uint8_t add); 49 static int axgbe_dev_link_update(struct rte_eth_dev *dev, 50 int wait_to_complete); 51 static int axgbe_dev_get_regs(struct rte_eth_dev *dev, 52 struct rte_dev_reg_info *regs); 53 static int axgbe_dev_stats_get(struct rte_eth_dev *dev, 54 struct rte_eth_stats *stats); 55 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev); 56 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev, 57 struct rte_eth_xstat *stats, 58 unsigned int n); 59 static int 60 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 61 struct rte_eth_xstat_name *xstats_names, 62 unsigned int size); 63 static int 64 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 65 const uint64_t *ids, 66 uint64_t *values, 67 unsigned int n); 68 static int 69 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 70 const uint64_t *ids, 71 struct rte_eth_xstat_name *xstats_names, 72 unsigned int size); 73 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev); 74 static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 75 struct rte_eth_rss_reta_entry64 *reta_conf, 76 uint16_t reta_size); 77 static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 78 struct rte_eth_rss_reta_entry64 *reta_conf, 79 uint16_t reta_size); 80 static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 81 struct rte_eth_rss_conf *rss_conf); 82 static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 83 struct rte_eth_rss_conf *rss_conf); 84 static int axgbe_dev_info_get(struct rte_eth_dev *dev, 85 struct rte_eth_dev_info *dev_info); 86 static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, 87 struct rte_eth_fc_conf *fc_conf); 88 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, 89 struct rte_eth_fc_conf *fc_conf); 90 static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 91 struct rte_eth_pfc_conf *pfc_conf); 92 static void axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 93 struct rte_eth_rxq_info *qinfo); 94 static void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 95 struct rte_eth_txq_info *qinfo); 96 const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev, 97 size_t *no_of_elements); 98 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 99 100 static int 101 axgbe_timesync_enable(struct rte_eth_dev *dev); 102 static int 103 axgbe_timesync_disable(struct rte_eth_dev *dev); 104 static int 105 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 106 struct timespec *timestamp, uint32_t flags); 107 static int 108 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 109 struct timespec *timestamp); 110 static int 111 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 112 static int 113 axgbe_timesync_read_time(struct rte_eth_dev *dev, 114 struct timespec *timestamp); 115 static int 116 axgbe_timesync_write_time(struct rte_eth_dev *dev, 117 const struct timespec *timestamp); 118 static void 119 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 120 unsigned int nsec); 121 static void 122 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 123 unsigned int addend); 124 static int 125 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on); 126 static int axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 127 enum rte_vlan_type vlan_type, uint16_t tpid); 128 static int axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 129 130 struct axgbe_xstats { 131 char name[RTE_ETH_XSTATS_NAME_SIZE]; 132 int offset; 133 }; 134 135 #define AXGMAC_MMC_STAT(_string, _var) \ 136 { _string, \ 137 offsetof(struct axgbe_mmc_stats, _var), \ 138 } 139 140 static const struct axgbe_xstats axgbe_xstats_strings[] = { 141 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb), 142 AXGMAC_MMC_STAT("tx_packets", txframecount_gb), 143 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb), 144 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb), 145 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb), 146 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g), 147 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb), 148 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb), 149 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb), 150 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb), 151 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb), 152 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb), 153 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror), 154 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes), 155 156 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb), 157 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb), 158 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g), 159 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g), 160 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g), 161 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb), 162 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb), 163 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb), 164 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb), 165 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb), 166 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb), 167 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb), 168 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g), 169 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g), 170 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror), 171 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror), 172 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror), 173 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror), 174 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype), 175 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow), 176 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror), 177 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes), 178 }; 179 180 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings) 181 182 /* The set of PCI devices this driver supports */ 183 #define AMD_PCI_VENDOR_ID 0x1022 184 185 #define Fam17h 0x17 186 #define Fam19h 0x19 187 188 #define CPUID_VENDOR_AuthenticAMD_ebx 0x68747541 189 #define CPUID_VENDOR_AuthenticAMD_ecx 0x444d4163 190 #define CPUID_VENDOR_AuthenticAMD_edx 0x69746e65 191 192 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 193 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459 194 195 static const struct rte_pci_id pci_id_axgbe_map[] = { 196 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)}, 197 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)}, 198 { .vendor_id = 0, }, 199 }; 200 201 static struct axgbe_version_data axgbe_v2a = { 202 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 203 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 204 .mmc_64bit = 1, 205 .tx_max_fifo_size = 229376, 206 .rx_max_fifo_size = 229376, 207 .tx_tstamp_workaround = 1, 208 .ecc_support = 1, 209 .i2c_support = 1, 210 .an_cdr_workaround = 1, 211 .enable_rrc = 1, 212 }; 213 214 static struct axgbe_version_data axgbe_v2b = { 215 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 216 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 217 .mmc_64bit = 1, 218 .tx_max_fifo_size = 65536, 219 .rx_max_fifo_size = 65536, 220 .tx_tstamp_workaround = 1, 221 .ecc_support = 1, 222 .i2c_support = 1, 223 .an_cdr_workaround = 1, 224 .enable_rrc = 1, 225 }; 226 227 static const struct rte_eth_desc_lim rx_desc_lim = { 228 .nb_max = AXGBE_MAX_RING_DESC, 229 .nb_min = AXGBE_MIN_RING_DESC, 230 .nb_align = 8, 231 }; 232 233 static const struct rte_eth_desc_lim tx_desc_lim = { 234 .nb_max = AXGBE_MAX_RING_DESC, 235 .nb_min = AXGBE_MIN_RING_DESC, 236 .nb_align = 8, 237 }; 238 239 static const struct eth_dev_ops axgbe_eth_dev_ops = { 240 .dev_configure = axgbe_dev_configure, 241 .dev_start = axgbe_dev_start, 242 .dev_stop = axgbe_dev_stop, 243 .dev_close = axgbe_dev_close, 244 .dev_reset = axgbe_dev_reset, 245 .promiscuous_enable = axgbe_dev_promiscuous_enable, 246 .promiscuous_disable = axgbe_dev_promiscuous_disable, 247 .allmulticast_enable = axgbe_dev_allmulticast_enable, 248 .allmulticast_disable = axgbe_dev_allmulticast_disable, 249 .mac_addr_set = axgbe_dev_mac_addr_set, 250 .mac_addr_add = axgbe_dev_mac_addr_add, 251 .mac_addr_remove = axgbe_dev_mac_addr_remove, 252 .set_mc_addr_list = axgbe_dev_set_mc_addr_list, 253 .uc_hash_table_set = axgbe_dev_uc_hash_table_set, 254 .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set, 255 .link_update = axgbe_dev_link_update, 256 .get_reg = axgbe_dev_get_regs, 257 .stats_get = axgbe_dev_stats_get, 258 .stats_reset = axgbe_dev_stats_reset, 259 .xstats_get = axgbe_dev_xstats_get, 260 .xstats_reset = axgbe_dev_xstats_reset, 261 .xstats_get_names = axgbe_dev_xstats_get_names, 262 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id, 263 .xstats_get_by_id = axgbe_dev_xstats_get_by_id, 264 .reta_update = axgbe_dev_rss_reta_update, 265 .reta_query = axgbe_dev_rss_reta_query, 266 .rss_hash_update = axgbe_dev_rss_hash_update, 267 .rss_hash_conf_get = axgbe_dev_rss_hash_conf_get, 268 .dev_infos_get = axgbe_dev_info_get, 269 .rx_queue_setup = axgbe_dev_rx_queue_setup, 270 .rx_queue_release = axgbe_dev_rx_queue_release, 271 .tx_queue_setup = axgbe_dev_tx_queue_setup, 272 .tx_queue_release = axgbe_dev_tx_queue_release, 273 .flow_ctrl_get = axgbe_flow_ctrl_get, 274 .flow_ctrl_set = axgbe_flow_ctrl_set, 275 .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set, 276 .rxq_info_get = axgbe_rxq_info_get, 277 .txq_info_get = axgbe_txq_info_get, 278 .dev_supported_ptypes_get = axgbe_dev_supported_ptypes_get, 279 .mtu_set = axgb_mtu_set, 280 .vlan_filter_set = axgbe_vlan_filter_set, 281 .vlan_tpid_set = axgbe_vlan_tpid_set, 282 .vlan_offload_set = axgbe_vlan_offload_set, 283 .timesync_enable = axgbe_timesync_enable, 284 .timesync_disable = axgbe_timesync_disable, 285 .timesync_read_rx_timestamp = axgbe_timesync_read_rx_timestamp, 286 .timesync_read_tx_timestamp = axgbe_timesync_read_tx_timestamp, 287 .timesync_adjust_time = axgbe_timesync_adjust_time, 288 .timesync_read_time = axgbe_timesync_read_time, 289 .timesync_write_time = axgbe_timesync_write_time, 290 .fw_version_get = axgbe_dev_fw_version_get, 291 }; 292 293 static int axgbe_phy_reset(struct axgbe_port *pdata) 294 { 295 pdata->phy_link = -1; 296 pdata->phy_speed = SPEED_UNKNOWN; 297 return pdata->phy_if.phy_reset(pdata); 298 } 299 300 /* 301 * Interrupt handler triggered by NIC for handling 302 * specific interrupt. 303 * 304 * @param handle 305 * Pointer to interrupt handle. 306 * @param param 307 * The address of parameter (struct rte_eth_dev *) registered before. 308 * 309 * @return 310 * void 311 */ 312 static void 313 axgbe_dev_interrupt_handler(void *param) 314 { 315 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 316 struct axgbe_port *pdata = dev->data->dev_private; 317 unsigned int dma_isr, dma_ch_isr; 318 319 pdata->phy_if.an_isr(pdata); 320 /*DMA related interrupts*/ 321 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR); 322 PMD_DRV_LOG_LINE(DEBUG, "DMA_ISR=%#010x", dma_isr); 323 if (dma_isr) { 324 if (dma_isr & 1) { 325 dma_ch_isr = 326 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *) 327 pdata->rx_queues[0], 328 DMA_CH_SR); 329 PMD_DRV_LOG_LINE(DEBUG, "DMA_CH0_ISR=%#010x", dma_ch_isr); 330 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *) 331 pdata->rx_queues[0], 332 DMA_CH_SR, dma_ch_isr); 333 } 334 } 335 /* Unmask interrupts since disabled after generation */ 336 rte_intr_ack(pdata->pci_dev->intr_handle); 337 } 338 339 /* 340 * Configure device link speed and setup link. 341 * It returns 0 on success. 342 */ 343 static int 344 axgbe_dev_configure(struct rte_eth_dev *dev) 345 { 346 struct axgbe_port *pdata = dev->data->dev_private; 347 /* Checksum offload to hardware */ 348 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads & 349 RTE_ETH_RX_OFFLOAD_CHECKSUM; 350 return 0; 351 } 352 353 static int 354 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev) 355 { 356 struct axgbe_port *pdata = dev->data->dev_private; 357 358 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) 359 pdata->rss_enable = 1; 360 else if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_NONE) 361 pdata->rss_enable = 0; 362 else 363 return -1; 364 return 0; 365 } 366 367 static int 368 axgbe_dev_start(struct rte_eth_dev *dev) 369 { 370 struct axgbe_port *pdata = dev->data->dev_private; 371 uint16_t i; 372 int ret; 373 374 dev->dev_ops = &axgbe_eth_dev_ops; 375 376 PMD_INIT_FUNC_TRACE(); 377 378 /* Multiqueue RSS */ 379 ret = axgbe_dev_rx_mq_config(dev); 380 if (ret) { 381 PMD_DRV_LOG_LINE(ERR, "Unable to config RX MQ"); 382 return ret; 383 } 384 ret = axgbe_phy_reset(pdata); 385 if (ret) { 386 PMD_DRV_LOG_LINE(ERR, "phy reset failed"); 387 return ret; 388 } 389 ret = pdata->hw_if.init(pdata); 390 if (ret) { 391 PMD_DRV_LOG_LINE(ERR, "dev_init failed"); 392 return ret; 393 } 394 395 /* enable uio/vfio intr/eventfd mapping */ 396 rte_intr_enable(pdata->pci_dev->intr_handle); 397 398 /* phy start*/ 399 pdata->phy_if.phy_start(pdata); 400 axgbe_dev_enable_tx(dev); 401 axgbe_dev_enable_rx(dev); 402 403 rte_bit_relaxed_clear32(AXGBE_STOPPED, &pdata->dev_state); 404 rte_bit_relaxed_clear32(AXGBE_DOWN, &pdata->dev_state); 405 406 axgbe_set_rx_function(dev); 407 axgbe_set_tx_function(dev); 408 409 for (i = 0; i < dev->data->nb_rx_queues; i++) 410 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 411 for (i = 0; i < dev->data->nb_tx_queues; i++) 412 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 413 414 return 0; 415 } 416 417 /* Stop device: disable rx and tx functions to allow for reconfiguring. */ 418 static int 419 axgbe_dev_stop(struct rte_eth_dev *dev) 420 { 421 struct axgbe_port *pdata = dev->data->dev_private; 422 423 PMD_INIT_FUNC_TRACE(); 424 425 rte_intr_disable(pdata->pci_dev->intr_handle); 426 427 if (rte_bit_relaxed_get32(AXGBE_STOPPED, &pdata->dev_state)) 428 return 0; 429 430 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 431 axgbe_dev_disable_tx(dev); 432 axgbe_dev_disable_rx(dev); 433 434 pdata->phy_if.phy_stop(pdata); 435 pdata->hw_if.exit(pdata); 436 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); 437 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 438 439 return 0; 440 } 441 442 static int 443 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 444 { 445 struct axgbe_port *pdata = dev->data->dev_private; 446 447 PMD_INIT_FUNC_TRACE(); 448 449 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); 450 451 return 0; 452 } 453 454 static int 455 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 456 { 457 struct axgbe_port *pdata = dev->data->dev_private; 458 459 PMD_INIT_FUNC_TRACE(); 460 461 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); 462 463 return 0; 464 } 465 466 static int 467 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 468 { 469 struct axgbe_port *pdata = dev->data->dev_private; 470 471 PMD_INIT_FUNC_TRACE(); 472 473 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 474 return 0; 475 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1); 476 477 return 0; 478 } 479 480 static int 481 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 482 { 483 struct axgbe_port *pdata = dev->data->dev_private; 484 485 PMD_INIT_FUNC_TRACE(); 486 487 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 488 return 0; 489 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0); 490 491 return 0; 492 } 493 494 static int 495 axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 496 { 497 struct axgbe_port *pdata = dev->data->dev_private; 498 499 /* Set Default MAC Addr */ 500 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0); 501 502 return 0; 503 } 504 505 static int 506 axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 507 uint32_t index, uint32_t pool __rte_unused) 508 { 509 struct axgbe_port *pdata = dev->data->dev_private; 510 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 511 512 if (index > hw_feat->addn_mac) { 513 PMD_DRV_LOG_LINE(ERR, "Invalid Index %d", index); 514 return -EINVAL; 515 } 516 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index); 517 return 0; 518 } 519 520 static int 521 axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 522 struct rte_eth_rss_reta_entry64 *reta_conf, 523 uint16_t reta_size) 524 { 525 struct axgbe_port *pdata = dev->data->dev_private; 526 unsigned int i, idx, shift; 527 int ret; 528 529 if (!pdata->rss_enable) { 530 PMD_DRV_LOG_LINE(ERR, "RSS not enabled"); 531 return -ENOTSUP; 532 } 533 534 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 535 PMD_DRV_LOG_LINE(ERR, "reta_size %d is not supported", reta_size); 536 return -EINVAL; 537 } 538 539 for (i = 0; i < reta_size; i++) { 540 idx = i / RTE_ETH_RETA_GROUP_SIZE; 541 shift = i % RTE_ETH_RETA_GROUP_SIZE; 542 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 543 continue; 544 pdata->rss_table[i] = reta_conf[idx].reta[shift]; 545 } 546 547 /* Program the lookup table */ 548 ret = axgbe_write_rss_lookup_table(pdata); 549 return ret; 550 } 551 552 static int 553 axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 554 struct rte_eth_rss_reta_entry64 *reta_conf, 555 uint16_t reta_size) 556 { 557 struct axgbe_port *pdata = dev->data->dev_private; 558 unsigned int i, idx, shift; 559 560 if (!pdata->rss_enable) { 561 PMD_DRV_LOG_LINE(ERR, "RSS not enabled"); 562 return -ENOTSUP; 563 } 564 565 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 566 PMD_DRV_LOG_LINE(ERR, "reta_size %d is not supported", reta_size); 567 return -EINVAL; 568 } 569 570 for (i = 0; i < reta_size; i++) { 571 idx = i / RTE_ETH_RETA_GROUP_SIZE; 572 shift = i % RTE_ETH_RETA_GROUP_SIZE; 573 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 574 continue; 575 reta_conf[idx].reta[shift] = pdata->rss_table[i]; 576 } 577 return 0; 578 } 579 580 static int 581 axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 582 struct rte_eth_rss_conf *rss_conf) 583 { 584 struct axgbe_port *pdata = dev->data->dev_private; 585 int ret; 586 587 if (!pdata->rss_enable) { 588 PMD_DRV_LOG_LINE(ERR, "RSS not enabled"); 589 return -ENOTSUP; 590 } 591 592 if (rss_conf == NULL) { 593 PMD_DRV_LOG_LINE(ERR, "rss_conf value isn't valid"); 594 return -EINVAL; 595 } 596 597 if (rss_conf->rss_key != NULL && 598 rss_conf->rss_key_len == AXGBE_RSS_HASH_KEY_SIZE) { 599 rte_memcpy(pdata->rss_key, rss_conf->rss_key, 600 AXGBE_RSS_HASH_KEY_SIZE); 601 /* Program the hash key */ 602 ret = axgbe_write_rss_hash_key(pdata); 603 if (ret != 0) 604 return ret; 605 } 606 607 pdata->rss_hf = rss_conf->rss_hf & AXGBE_RSS_OFFLOAD; 608 609 if (pdata->rss_hf & (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6)) 610 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); 611 if (pdata->rss_hf & 612 (RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV6_TCP)) 613 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); 614 if (pdata->rss_hf & 615 (RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV6_UDP)) 616 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); 617 618 /* Set the RSS options */ 619 AXGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 620 621 return 0; 622 } 623 624 static int 625 axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 626 struct rte_eth_rss_conf *rss_conf) 627 { 628 struct axgbe_port *pdata = dev->data->dev_private; 629 630 if (!pdata->rss_enable) { 631 PMD_DRV_LOG_LINE(ERR, "RSS not enabled"); 632 return -ENOTSUP; 633 } 634 635 if (rss_conf == NULL) { 636 PMD_DRV_LOG_LINE(ERR, "rss_conf value isn't valid"); 637 return -EINVAL; 638 } 639 640 if (rss_conf->rss_key != NULL && 641 rss_conf->rss_key_len >= AXGBE_RSS_HASH_KEY_SIZE) { 642 rte_memcpy(rss_conf->rss_key, pdata->rss_key, 643 AXGBE_RSS_HASH_KEY_SIZE); 644 } 645 rss_conf->rss_key_len = AXGBE_RSS_HASH_KEY_SIZE; 646 rss_conf->rss_hf = pdata->rss_hf; 647 return 0; 648 } 649 650 static int 651 axgbe_dev_reset(struct rte_eth_dev *dev) 652 { 653 int ret = 0; 654 655 ret = axgbe_dev_close(dev); 656 if (ret) 657 return ret; 658 659 ret = eth_axgbe_dev_init(dev); 660 661 return ret; 662 } 663 664 static void 665 axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 666 { 667 struct axgbe_port *pdata = dev->data->dev_private; 668 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 669 670 if (index > hw_feat->addn_mac) { 671 PMD_DRV_LOG_LINE(ERR, "Invalid Index %d", index); 672 return; 673 } 674 axgbe_set_mac_addn_addr(pdata, NULL, index); 675 } 676 677 static int 678 axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 679 struct rte_ether_addr *mc_addr_set, 680 uint32_t nb_mc_addr) 681 { 682 struct axgbe_port *pdata = dev->data->dev_private; 683 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 684 uint32_t index = 1; /* 0 is always default mac */ 685 uint32_t i; 686 687 if (nb_mc_addr > hw_feat->addn_mac) { 688 PMD_DRV_LOG_LINE(ERR, "Invalid Index %d", nb_mc_addr); 689 return -EINVAL; 690 } 691 692 /* clear unicast addresses */ 693 for (i = 1; i < hw_feat->addn_mac; i++) { 694 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i])) 695 continue; 696 memset(&dev->data->mac_addrs[i], 0, 697 sizeof(struct rte_ether_addr)); 698 } 699 700 while (nb_mc_addr--) 701 axgbe_set_mac_addn_addr(pdata, (u8 *)mc_addr_set++, index++); 702 703 return 0; 704 } 705 706 static int 707 axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 708 struct rte_ether_addr *mac_addr, uint8_t add) 709 { 710 struct axgbe_port *pdata = dev->data->dev_private; 711 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 712 713 if (!hw_feat->hash_table_size) { 714 PMD_DRV_LOG_LINE(ERR, "MAC Hash Table not supported"); 715 return -ENOTSUP; 716 } 717 718 axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add); 719 720 if (pdata->uc_hash_mac_addr > 0) { 721 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 722 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 723 } else { 724 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 725 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 726 } 727 return 0; 728 } 729 730 static int 731 axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add) 732 { 733 struct axgbe_port *pdata = dev->data->dev_private; 734 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 735 uint32_t index; 736 737 if (!hw_feat->hash_table_size) { 738 PMD_DRV_LOG_LINE(ERR, "MAC Hash Table not supported"); 739 return -ENOTSUP; 740 } 741 742 for (index = 0; index < pdata->hash_table_count; index++) { 743 if (add) 744 pdata->uc_hash_table[index] = ~0; 745 else 746 pdata->uc_hash_table[index] = 0; 747 748 PMD_DRV_LOG_LINE(DEBUG, "%s MAC hash table at Index %#x", 749 add ? "set" : "clear", index); 750 751 AXGMAC_IOWRITE(pdata, MAC_HTR(index), 752 pdata->uc_hash_table[index]); 753 } 754 755 if (add) { 756 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 757 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 758 } else { 759 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 760 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 761 } 762 return 0; 763 } 764 765 /* return 0 means link status changed, -1 means not changed */ 766 static int 767 axgbe_dev_link_update(struct rte_eth_dev *dev, 768 int wait_to_complete __rte_unused) 769 { 770 struct axgbe_port *pdata = dev->data->dev_private; 771 struct rte_eth_link link; 772 int ret = 0; 773 774 PMD_INIT_FUNC_TRACE(); 775 rte_delay_ms(800); 776 777 pdata->phy_if.phy_status(pdata); 778 779 memset(&link, 0, sizeof(struct rte_eth_link)); 780 link.link_duplex = pdata->phy.duplex; 781 link.link_status = pdata->phy_link; 782 link.link_speed = pdata->phy_speed; 783 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 784 RTE_ETH_LINK_SPEED_FIXED); 785 ret = rte_eth_linkstatus_set(dev, &link); 786 if (ret == 0) 787 PMD_DRV_LOG_LINE(ERR, "Link status changed"); 788 789 return ret; 790 } 791 792 static int 793 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 794 { 795 struct axgbe_port *pdata = dev->data->dev_private; 796 797 if (regs->data == NULL) { 798 regs->length = axgbe_regs_get_count(pdata); 799 regs->width = sizeof(uint32_t); 800 return 0; 801 } 802 803 /* Only full register dump is supported */ 804 if (regs->length && 805 regs->length != (uint32_t)axgbe_regs_get_count(pdata)) 806 return -ENOTSUP; 807 808 regs->version = pdata->pci_dev->id.vendor_id << 16 | 809 pdata->pci_dev->id.device_id; 810 axgbe_regs_dump(pdata, regs->data); 811 return 0; 812 } 813 static void axgbe_read_mmc_stats(struct axgbe_port *pdata) 814 { 815 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 816 817 /* Freeze counters */ 818 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 819 820 /* Tx counters */ 821 stats->txoctetcount_gb += 822 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO); 823 stats->txoctetcount_gb += 824 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32); 825 826 stats->txframecount_gb += 827 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO); 828 stats->txframecount_gb += 829 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32); 830 831 stats->txbroadcastframes_g += 832 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO); 833 stats->txbroadcastframes_g += 834 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32); 835 836 stats->txmulticastframes_g += 837 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO); 838 stats->txmulticastframes_g += 839 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32); 840 841 stats->tx64octets_gb += 842 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO); 843 stats->tx64octets_gb += 844 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32); 845 846 stats->tx65to127octets_gb += 847 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO); 848 stats->tx65to127octets_gb += 849 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32); 850 851 stats->tx128to255octets_gb += 852 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO); 853 stats->tx128to255octets_gb += 854 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32); 855 856 stats->tx256to511octets_gb += 857 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO); 858 stats->tx256to511octets_gb += 859 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32); 860 861 stats->tx512to1023octets_gb += 862 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO); 863 stats->tx512to1023octets_gb += 864 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32); 865 866 stats->tx1024tomaxoctets_gb += 867 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 868 stats->tx1024tomaxoctets_gb += 869 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32); 870 871 stats->txunicastframes_gb += 872 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO); 873 stats->txunicastframes_gb += 874 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32); 875 876 stats->txmulticastframes_gb += 877 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 878 stats->txmulticastframes_gb += 879 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32); 880 881 stats->txbroadcastframes_g += 882 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 883 stats->txbroadcastframes_g += 884 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32); 885 886 stats->txunderflowerror += 887 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO); 888 stats->txunderflowerror += 889 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32); 890 891 stats->txoctetcount_g += 892 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO); 893 stats->txoctetcount_g += 894 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32); 895 896 stats->txframecount_g += 897 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO); 898 stats->txframecount_g += 899 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32); 900 901 stats->txpauseframes += 902 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO); 903 stats->txpauseframes += 904 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32); 905 906 stats->txvlanframes_g += 907 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO); 908 stats->txvlanframes_g += 909 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32); 910 911 /* Rx counters */ 912 stats->rxframecount_gb += 913 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO); 914 stats->rxframecount_gb += 915 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32); 916 917 stats->rxoctetcount_gb += 918 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO); 919 stats->rxoctetcount_gb += 920 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32); 921 922 stats->rxoctetcount_g += 923 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO); 924 stats->rxoctetcount_g += 925 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32); 926 927 stats->rxbroadcastframes_g += 928 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO); 929 stats->rxbroadcastframes_g += 930 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32); 931 932 stats->rxmulticastframes_g += 933 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO); 934 stats->rxmulticastframes_g += 935 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32); 936 937 stats->rxcrcerror += 938 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO); 939 stats->rxcrcerror += 940 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32); 941 942 stats->rxrunterror += 943 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR); 944 945 stats->rxjabbererror += 946 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR); 947 948 stats->rxundersize_g += 949 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G); 950 951 stats->rxoversize_g += 952 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G); 953 954 stats->rx64octets_gb += 955 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO); 956 stats->rx64octets_gb += 957 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32); 958 959 stats->rx65to127octets_gb += 960 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO); 961 stats->rx65to127octets_gb += 962 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32); 963 964 stats->rx128to255octets_gb += 965 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO); 966 stats->rx128to255octets_gb += 967 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32); 968 969 stats->rx256to511octets_gb += 970 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO); 971 stats->rx256to511octets_gb += 972 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32); 973 974 stats->rx512to1023octets_gb += 975 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO); 976 stats->rx512to1023octets_gb += 977 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32); 978 979 stats->rx1024tomaxoctets_gb += 980 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 981 stats->rx1024tomaxoctets_gb += 982 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32); 983 984 stats->rxunicastframes_g += 985 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO); 986 stats->rxunicastframes_g += 987 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32); 988 989 stats->rxlengtherror += 990 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO); 991 stats->rxlengtherror += 992 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32); 993 994 stats->rxoutofrangetype += 995 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO); 996 stats->rxoutofrangetype += 997 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32); 998 999 stats->rxpauseframes += 1000 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO); 1001 stats->rxpauseframes += 1002 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32); 1003 1004 stats->rxfifooverflow += 1005 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO); 1006 stats->rxfifooverflow += 1007 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32); 1008 1009 stats->rxvlanframes_gb += 1010 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO); 1011 stats->rxvlanframes_gb += 1012 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32); 1013 1014 stats->rxwatchdogerror += 1015 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR); 1016 1017 /* Un-freeze counters */ 1018 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 1019 } 1020 1021 static int 1022 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1023 unsigned int n) 1024 { 1025 struct axgbe_port *pdata = dev->data->dev_private; 1026 unsigned int i; 1027 1028 if (n < AXGBE_XSTATS_COUNT) 1029 return AXGBE_XSTATS_COUNT; 1030 1031 axgbe_read_mmc_stats(pdata); 1032 1033 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1034 stats[i].id = i; 1035 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1036 axgbe_xstats_strings[i].offset); 1037 } 1038 1039 return AXGBE_XSTATS_COUNT; 1040 } 1041 1042 static int 1043 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1044 struct rte_eth_xstat_name *xstats_names, 1045 unsigned int n) 1046 { 1047 unsigned int i; 1048 1049 if (n >= AXGBE_XSTATS_COUNT && xstats_names) { 1050 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) { 1051 snprintf(xstats_names[i].name, 1052 RTE_ETH_XSTATS_NAME_SIZE, "%s", 1053 axgbe_xstats_strings[i].name); 1054 } 1055 } 1056 1057 return AXGBE_XSTATS_COUNT; 1058 } 1059 1060 static int 1061 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1062 uint64_t *values, unsigned int n) 1063 { 1064 unsigned int i; 1065 uint64_t values_copy[AXGBE_XSTATS_COUNT]; 1066 1067 if (!ids) { 1068 struct axgbe_port *pdata = dev->data->dev_private; 1069 1070 if (n < AXGBE_XSTATS_COUNT) 1071 return AXGBE_XSTATS_COUNT; 1072 1073 axgbe_read_mmc_stats(pdata); 1074 1075 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1076 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1077 axgbe_xstats_strings[i].offset); 1078 } 1079 1080 return i; 1081 } 1082 1083 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT); 1084 1085 for (i = 0; i < n; i++) { 1086 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1087 PMD_DRV_LOG_LINE(ERR, "id value isn't valid"); 1088 return -1; 1089 } 1090 values[i] = values_copy[ids[i]]; 1091 } 1092 return n; 1093 } 1094 1095 static int 1096 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 1097 const uint64_t *ids, 1098 struct rte_eth_xstat_name *xstats_names, 1099 unsigned int size) 1100 { 1101 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT]; 1102 unsigned int i; 1103 1104 if (!ids) 1105 return axgbe_dev_xstats_get_names(dev, xstats_names, size); 1106 1107 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size); 1108 1109 for (i = 0; i < size; i++) { 1110 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1111 PMD_DRV_LOG_LINE(ERR, "id value isn't valid"); 1112 return -1; 1113 } 1114 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1115 } 1116 return size; 1117 } 1118 1119 static int 1120 axgbe_dev_xstats_reset(struct rte_eth_dev *dev) 1121 { 1122 struct axgbe_port *pdata = dev->data->dev_private; 1123 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 1124 1125 /* MMC registers are configured for reset on read */ 1126 axgbe_read_mmc_stats(pdata); 1127 1128 /* Reset stats */ 1129 memset(stats, 0, sizeof(*stats)); 1130 1131 return 0; 1132 } 1133 1134 static int 1135 axgbe_dev_stats_get(struct rte_eth_dev *dev, 1136 struct rte_eth_stats *stats) 1137 { 1138 struct axgbe_rx_queue *rxq; 1139 struct axgbe_tx_queue *txq; 1140 struct axgbe_port *pdata = dev->data->dev_private; 1141 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats; 1142 unsigned int i; 1143 1144 axgbe_read_mmc_stats(pdata); 1145 1146 stats->imissed = mmc_stats->rxfifooverflow; 1147 1148 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1149 rxq = dev->data->rx_queues[i]; 1150 if (rxq) { 1151 stats->q_ipackets[i] = rxq->pkts; 1152 stats->ipackets += rxq->pkts; 1153 stats->q_ibytes[i] = rxq->bytes; 1154 stats->ibytes += rxq->bytes; 1155 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed; 1156 stats->q_errors[i] = rxq->errors 1157 + rxq->rx_mbuf_alloc_failed; 1158 stats->ierrors += rxq->errors; 1159 } else { 1160 PMD_DRV_LOG_LINE(DEBUG, "Rx queue not setup for port %d", 1161 dev->data->port_id); 1162 } 1163 } 1164 1165 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1166 txq = dev->data->tx_queues[i]; 1167 if (txq) { 1168 stats->q_opackets[i] = txq->pkts; 1169 stats->opackets += txq->pkts; 1170 stats->q_obytes[i] = txq->bytes; 1171 stats->obytes += txq->bytes; 1172 stats->oerrors += txq->errors; 1173 } else { 1174 PMD_DRV_LOG_LINE(DEBUG, "Tx queue not setup for port %d", 1175 dev->data->port_id); 1176 } 1177 } 1178 1179 return 0; 1180 } 1181 1182 static int 1183 axgbe_dev_stats_reset(struct rte_eth_dev *dev) 1184 { 1185 struct axgbe_rx_queue *rxq; 1186 struct axgbe_tx_queue *txq; 1187 unsigned int i; 1188 1189 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1190 rxq = dev->data->rx_queues[i]; 1191 if (rxq) { 1192 rxq->pkts = 0; 1193 rxq->bytes = 0; 1194 rxq->errors = 0; 1195 rxq->rx_mbuf_alloc_failed = 0; 1196 } else { 1197 PMD_DRV_LOG_LINE(DEBUG, "Rx queue not setup for port %d", 1198 dev->data->port_id); 1199 } 1200 } 1201 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1202 txq = dev->data->tx_queues[i]; 1203 if (txq) { 1204 txq->pkts = 0; 1205 txq->bytes = 0; 1206 txq->errors = 0; 1207 } else { 1208 PMD_DRV_LOG_LINE(DEBUG, "Tx queue not setup for port %d", 1209 dev->data->port_id); 1210 } 1211 } 1212 1213 return 0; 1214 } 1215 1216 static int 1217 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1218 { 1219 struct axgbe_port *pdata = dev->data->dev_private; 1220 1221 dev_info->max_rx_queues = pdata->rx_ring_count; 1222 dev_info->max_tx_queues = pdata->tx_ring_count; 1223 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE; 1224 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE; 1225 dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1; 1226 dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size; 1227 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10G; 1228 1229 dev_info->rx_offload_capa = 1230 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 1231 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 1232 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | 1233 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 1234 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 1235 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 1236 RTE_ETH_RX_OFFLOAD_SCATTER | 1237 RTE_ETH_RX_OFFLOAD_KEEP_CRC; 1238 1239 dev_info->tx_offload_capa = 1240 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 1241 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | 1242 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 1243 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | 1244 RTE_ETH_TX_OFFLOAD_TCP_TSO | 1245 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 1246 RTE_ETH_TX_OFFLOAD_TCP_CKSUM; 1247 1248 if (pdata->hw_feat.rss) { 1249 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD; 1250 dev_info->reta_size = pdata->hw_feat.hash_table_size; 1251 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE; 1252 } 1253 1254 dev_info->rx_desc_lim = rx_desc_lim; 1255 dev_info->tx_desc_lim = tx_desc_lim; 1256 1257 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1258 .rx_free_thresh = AXGBE_RX_FREE_THRESH, 1259 }; 1260 1261 dev_info->default_txconf = (struct rte_eth_txconf) { 1262 .tx_free_thresh = AXGBE_TX_FREE_THRESH, 1263 }; 1264 1265 return 0; 1266 } 1267 1268 static int 1269 axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1270 { 1271 struct axgbe_port *pdata = dev->data->dev_private; 1272 struct xgbe_fc_info fc = pdata->fc; 1273 unsigned int reg, reg_val = 0; 1274 1275 reg = MAC_Q0TFCR; 1276 reg_val = AXGMAC_IOREAD(pdata, reg); 1277 fc.low_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA); 1278 fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD); 1279 fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT); 1280 fc.autoneg = pdata->pause_autoneg; 1281 1282 if (pdata->rx_pause && pdata->tx_pause) 1283 fc.mode = RTE_ETH_FC_FULL; 1284 else if (pdata->rx_pause) 1285 fc.mode = RTE_ETH_FC_RX_PAUSE; 1286 else if (pdata->tx_pause) 1287 fc.mode = RTE_ETH_FC_TX_PAUSE; 1288 else 1289 fc.mode = RTE_ETH_FC_NONE; 1290 1291 fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024; 1292 fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024; 1293 fc_conf->pause_time = fc.pause_time[0]; 1294 fc_conf->send_xon = fc.send_xon; 1295 fc_conf->mode = fc.mode; 1296 1297 return 0; 1298 } 1299 1300 static int 1301 axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1302 { 1303 struct axgbe_port *pdata = dev->data->dev_private; 1304 struct xgbe_fc_info fc = pdata->fc; 1305 unsigned int reg, reg_val = 0; 1306 reg = MAC_Q0TFCR; 1307 1308 pdata->pause_autoneg = fc_conf->autoneg; 1309 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1310 fc.send_xon = fc_conf->send_xon; 1311 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA, 1312 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water)); 1313 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD, 1314 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water)); 1315 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time); 1316 AXGMAC_IOWRITE(pdata, reg, reg_val); 1317 fc.mode = fc_conf->mode; 1318 1319 if (fc.mode == RTE_ETH_FC_FULL) { 1320 pdata->tx_pause = 1; 1321 pdata->rx_pause = 1; 1322 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) { 1323 pdata->tx_pause = 0; 1324 pdata->rx_pause = 1; 1325 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) { 1326 pdata->tx_pause = 1; 1327 pdata->rx_pause = 0; 1328 } else { 1329 pdata->tx_pause = 0; 1330 pdata->rx_pause = 0; 1331 } 1332 1333 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1334 pdata->hw_if.config_tx_flow_control(pdata); 1335 1336 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1337 pdata->hw_if.config_rx_flow_control(pdata); 1338 1339 pdata->hw_if.config_flow_control(pdata); 1340 pdata->phy.tx_pause = pdata->tx_pause; 1341 pdata->phy.rx_pause = pdata->rx_pause; 1342 1343 return 0; 1344 } 1345 1346 static int 1347 axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 1348 struct rte_eth_pfc_conf *pfc_conf) 1349 { 1350 struct axgbe_port *pdata = dev->data->dev_private; 1351 struct xgbe_fc_info fc = pdata->fc; 1352 uint8_t tc_num; 1353 1354 tc_num = pdata->pfc_map[pfc_conf->priority]; 1355 1356 if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) { 1357 PMD_INIT_LOG(ERR, "Max supported traffic class: %d", 1358 pdata->hw_feat.tc_cnt); 1359 return -EINVAL; 1360 } 1361 1362 pdata->pause_autoneg = pfc_conf->fc.autoneg; 1363 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1364 fc.send_xon = pfc_conf->fc.send_xon; 1365 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA, 1366 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water)); 1367 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD, 1368 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water)); 1369 1370 switch (tc_num) { 1371 case 0: 1372 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1373 PSTC0, pfc_conf->fc.pause_time); 1374 break; 1375 case 1: 1376 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1377 PSTC1, pfc_conf->fc.pause_time); 1378 break; 1379 case 2: 1380 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1381 PSTC2, pfc_conf->fc.pause_time); 1382 break; 1383 case 3: 1384 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1385 PSTC3, pfc_conf->fc.pause_time); 1386 break; 1387 case 4: 1388 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1389 PSTC4, pfc_conf->fc.pause_time); 1390 break; 1391 case 5: 1392 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1393 PSTC5, pfc_conf->fc.pause_time); 1394 break; 1395 case 7: 1396 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1397 PSTC6, pfc_conf->fc.pause_time); 1398 break; 1399 case 6: 1400 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1401 PSTC7, pfc_conf->fc.pause_time); 1402 break; 1403 } 1404 1405 fc.mode = pfc_conf->fc.mode; 1406 1407 if (fc.mode == RTE_ETH_FC_FULL) { 1408 pdata->tx_pause = 1; 1409 pdata->rx_pause = 1; 1410 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1411 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) { 1412 pdata->tx_pause = 0; 1413 pdata->rx_pause = 1; 1414 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1415 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) { 1416 pdata->tx_pause = 1; 1417 pdata->rx_pause = 0; 1418 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1419 } else { 1420 pdata->tx_pause = 0; 1421 pdata->rx_pause = 0; 1422 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1423 } 1424 1425 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1426 pdata->hw_if.config_tx_flow_control(pdata); 1427 1428 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1429 pdata->hw_if.config_rx_flow_control(pdata); 1430 pdata->hw_if.config_flow_control(pdata); 1431 pdata->phy.tx_pause = pdata->tx_pause; 1432 pdata->phy.rx_pause = pdata->rx_pause; 1433 1434 return 0; 1435 } 1436 1437 void 1438 axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1439 struct rte_eth_rxq_info *qinfo) 1440 { 1441 struct axgbe_rx_queue *rxq; 1442 1443 rxq = dev->data->rx_queues[queue_id]; 1444 qinfo->mp = rxq->mb_pool; 1445 qinfo->scattered_rx = dev->data->scattered_rx; 1446 qinfo->nb_desc = rxq->nb_desc; 1447 qinfo->conf.rx_free_thresh = rxq->free_thresh; 1448 } 1449 1450 void 1451 axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1452 struct rte_eth_txq_info *qinfo) 1453 { 1454 struct axgbe_tx_queue *txq; 1455 1456 txq = dev->data->tx_queues[queue_id]; 1457 qinfo->nb_desc = txq->nb_desc; 1458 qinfo->conf.tx_free_thresh = txq->free_thresh; 1459 } 1460 const uint32_t * 1461 axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 1462 { 1463 static const uint32_t ptypes[] = { 1464 RTE_PTYPE_L2_ETHER, 1465 RTE_PTYPE_L2_ETHER_TIMESYNC, 1466 RTE_PTYPE_L2_ETHER_LLDP, 1467 RTE_PTYPE_L2_ETHER_ARP, 1468 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1469 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 1470 RTE_PTYPE_L4_FRAG, 1471 RTE_PTYPE_L4_ICMP, 1472 RTE_PTYPE_L4_NONFRAG, 1473 RTE_PTYPE_L4_SCTP, 1474 RTE_PTYPE_L4_TCP, 1475 RTE_PTYPE_L4_UDP, 1476 RTE_PTYPE_TUNNEL_GRENAT, 1477 RTE_PTYPE_TUNNEL_IP, 1478 RTE_PTYPE_INNER_L2_ETHER, 1479 RTE_PTYPE_INNER_L2_ETHER_VLAN, 1480 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 1481 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 1482 RTE_PTYPE_INNER_L4_FRAG, 1483 RTE_PTYPE_INNER_L4_ICMP, 1484 RTE_PTYPE_INNER_L4_NONFRAG, 1485 RTE_PTYPE_INNER_L4_SCTP, 1486 RTE_PTYPE_INNER_L4_TCP, 1487 RTE_PTYPE_INNER_L4_UDP, 1488 }; 1489 1490 if (dev->rx_pkt_burst == axgbe_recv_pkts) { 1491 *no_of_elements = RTE_DIM(ptypes); 1492 return ptypes; 1493 } 1494 return NULL; 1495 } 1496 1497 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1498 { 1499 struct axgbe_port *pdata = dev->data->dev_private; 1500 unsigned int val; 1501 1502 /* mtu setting is forbidden if port is start */ 1503 if (dev->data->dev_started) { 1504 PMD_DRV_LOG_LINE(ERR, "port %d must be stopped before configuration", 1505 dev->data->port_id); 1506 return -EBUSY; 1507 } 1508 val = mtu > RTE_ETHER_MTU ? 1 : 0; 1509 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 1510 1511 return 0; 1512 } 1513 1514 static void 1515 axgbe_update_tstamp_time(struct axgbe_port *pdata, 1516 unsigned int sec, unsigned int nsec, int addsub) 1517 { 1518 unsigned int count = 100; 1519 uint32_t sub_val = 0; 1520 uint32_t sub_val_sec = 0xFFFFFFFF; 1521 uint32_t sub_val_nsec = 0x3B9ACA00; 1522 1523 if (addsub) { 1524 if (sec) 1525 sub_val = sub_val_sec - (sec - 1); 1526 else 1527 sub_val = sec; 1528 1529 AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val); 1530 sub_val = sub_val_nsec - nsec; 1531 AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val); 1532 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1); 1533 } else { 1534 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1535 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0); 1536 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1537 } 1538 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1539 /* Wait for time update to complete */ 1540 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1541 rte_delay_ms(1); 1542 } 1543 1544 static inline uint64_t 1545 div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) 1546 { 1547 *remainder = dividend % divisor; 1548 return dividend / divisor; 1549 } 1550 1551 static inline uint64_t 1552 div_u64(uint64_t dividend, uint32_t divisor) 1553 { 1554 uint32_t remainder; 1555 return div_u64_rem(dividend, divisor, &remainder); 1556 } 1557 1558 static int 1559 axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta) 1560 { 1561 uint64_t adjust; 1562 uint32_t addend, diff; 1563 unsigned int neg_adjust = 0; 1564 1565 if (delta < 0) { 1566 neg_adjust = 1; 1567 delta = -delta; 1568 } 1569 adjust = (uint64_t)pdata->tstamp_addend; 1570 adjust *= delta; 1571 diff = (uint32_t)div_u64(adjust, 1000000000UL); 1572 addend = (neg_adjust) ? pdata->tstamp_addend - diff : 1573 pdata->tstamp_addend + diff; 1574 pdata->tstamp_addend = addend; 1575 axgbe_update_tstamp_addend(pdata, addend); 1576 return 0; 1577 } 1578 1579 static int 1580 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 1581 { 1582 struct axgbe_port *pdata = dev->data->dev_private; 1583 struct timespec timestamp_delta; 1584 1585 axgbe_adjfreq(pdata, delta); 1586 pdata->systime_tc.nsec += delta; 1587 1588 if (delta < 0) { 1589 delta = -delta; 1590 timestamp_delta = rte_ns_to_timespec(delta); 1591 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1592 timestamp_delta.tv_nsec, 1); 1593 } else { 1594 timestamp_delta = rte_ns_to_timespec(delta); 1595 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1596 timestamp_delta.tv_nsec, 0); 1597 } 1598 return 0; 1599 } 1600 1601 static int 1602 axgbe_timesync_read_time(struct rte_eth_dev *dev, 1603 struct timespec *timestamp) 1604 { 1605 uint64_t nsec; 1606 struct axgbe_port *pdata = dev->data->dev_private; 1607 1608 nsec = AXGMAC_IOREAD(pdata, MAC_STSR); 1609 nsec *= NSEC_PER_SEC; 1610 nsec += AXGMAC_IOREAD(pdata, MAC_STNR); 1611 *timestamp = rte_ns_to_timespec(nsec); 1612 return 0; 1613 } 1614 static int 1615 axgbe_timesync_write_time(struct rte_eth_dev *dev, 1616 const struct timespec *timestamp) 1617 { 1618 unsigned int count = 100; 1619 struct axgbe_port *pdata = dev->data->dev_private; 1620 1621 AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec); 1622 AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec); 1623 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1624 /* Wait for time update to complete */ 1625 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1626 rte_delay_ms(1); 1627 if (!count) 1628 PMD_DRV_LOG_LINE(ERR, "Timed out update timestamp"); 1629 return 0; 1630 } 1631 1632 static void 1633 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 1634 uint32_t addend) 1635 { 1636 unsigned int count = 100; 1637 1638 AXGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1639 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1640 1641 /* Wait for addend update to complete */ 1642 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1643 rte_delay_ms(1); 1644 if (!count) 1645 PMD_DRV_LOG_LINE(ERR, "Timed out updating timestamp addend register"); 1646 } 1647 1648 static void 1649 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 1650 unsigned int nsec) 1651 { 1652 unsigned int count = 100; 1653 1654 /*System Time Sec Update*/ 1655 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1656 /*System Time nanoSec Update*/ 1657 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1658 /*Initialize Timestamp*/ 1659 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1660 1661 /* Wait for time update to complete */ 1662 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1663 rte_delay_ms(1); 1664 if (!count) 1665 PMD_DRV_LOG_LINE(ERR, "Timed out initializing timestamp"); 1666 } 1667 1668 static int 1669 axgbe_timesync_enable(struct rte_eth_dev *dev) 1670 { 1671 struct axgbe_port *pdata = dev->data->dev_private; 1672 unsigned int mac_tscr = 0; 1673 uint64_t dividend; 1674 struct timespec timestamp; 1675 uint64_t nsec; 1676 1677 /* Set one nano-second accuracy */ 1678 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1679 1680 /* Set fine timestamp update */ 1681 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1682 1683 /* Overwrite earlier timestamps */ 1684 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1685 1686 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1687 1688 /* Enabling processing of ptp over eth pkt */ 1689 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1690 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1691 /* Enable timestamp for all pkts*/ 1692 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 1693 1694 /* enabling timestamp */ 1695 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1696 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1697 1698 /* Exit if timestamping is not enabled */ 1699 if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) { 1700 PMD_DRV_LOG_LINE(ERR, "Exiting as timestamp is not enabled"); 1701 return 0; 1702 } 1703 1704 /* Sub-second Increment Value*/ 1705 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC); 1706 /* Sub-nanosecond Increment Value */ 1707 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC); 1708 1709 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 1710 dividend = 50000000; 1711 dividend <<= 32; 1712 pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate); 1713 1714 axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1715 axgbe_set_tstamp_time(pdata, 0, 0); 1716 1717 /* Initialize the timecounter */ 1718 memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter)); 1719 1720 pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK; 1721 pdata->systime_tc.cc_shift = 0; 1722 pdata->systime_tc.nsec_mask = 0; 1723 1724 PMD_DRV_LOG_LINE(DEBUG, "Initializing system time counter with realtime"); 1725 1726 /* Updating the counter once with clock real time */ 1727 clock_gettime(CLOCK_REALTIME, ×tamp); 1728 nsec = rte_timespec_to_ns(×tamp); 1729 nsec = rte_timecounter_update(&pdata->systime_tc, nsec); 1730 axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec); 1731 return 0; 1732 } 1733 1734 static int 1735 axgbe_timesync_disable(struct rte_eth_dev *dev) 1736 { 1737 struct axgbe_port *pdata = dev->data->dev_private; 1738 unsigned int mac_tscr = 0; 1739 1740 /*disable timestamp for all pkts*/ 1741 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0); 1742 /*disable the addened register*/ 1743 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0); 1744 /* disable timestamp update */ 1745 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0); 1746 /*disable time stamp*/ 1747 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0); 1748 return 0; 1749 } 1750 1751 static int 1752 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 1753 struct timespec *timestamp, uint32_t flags) 1754 { 1755 uint64_t nsec = 0; 1756 volatile union axgbe_rx_desc *desc; 1757 uint16_t idx, pmt; 1758 struct axgbe_rx_queue *rxq = *dev->data->rx_queues; 1759 1760 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 1761 desc = &rxq->desc[idx]; 1762 1763 while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 1764 rte_delay_ms(1); 1765 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) { 1766 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) && 1767 !AXGMAC_GET_BITS_LE(desc->write.desc3, 1768 RX_CONTEXT_DESC3, TSD)) { 1769 pmt = AXGMAC_GET_BITS_LE(desc->write.desc3, 1770 RX_CONTEXT_DESC3, PMT); 1771 nsec = rte_le_to_cpu_32(desc->write.desc1); 1772 nsec *= NSEC_PER_SEC; 1773 nsec += rte_le_to_cpu_32(desc->write.desc0); 1774 if (nsec != 0xffffffffffffffffULL) { 1775 if (pmt == 0x01) 1776 *timestamp = rte_ns_to_timespec(nsec); 1777 PMD_DRV_LOG_LINE(DEBUG, 1778 "flags = 0x%x nsec = %"PRIu64, 1779 flags, nsec); 1780 } 1781 } 1782 } 1783 1784 return 0; 1785 } 1786 1787 static int 1788 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 1789 struct timespec *timestamp) 1790 { 1791 uint64_t nsec; 1792 struct axgbe_port *pdata = dev->data->dev_private; 1793 unsigned int tx_snr, tx_ssr; 1794 1795 rte_delay_us(5); 1796 if (pdata->vdata->tx_tstamp_workaround) { 1797 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1798 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1799 1800 } else { 1801 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1802 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1803 } 1804 if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) { 1805 PMD_DRV_LOG_LINE(DEBUG, "Waiting for TXTSSTSMIS"); 1806 return 0; 1807 } 1808 nsec = tx_ssr; 1809 nsec *= NSEC_PER_SEC; 1810 nsec += tx_snr; 1811 PMD_DRV_LOG_LINE(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d", 1812 nsec, tx_ssr, tx_snr); 1813 *timestamp = rte_ns_to_timespec(nsec); 1814 return 0; 1815 } 1816 1817 static int 1818 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1819 { 1820 struct axgbe_port *pdata = dev->data->dev_private; 1821 unsigned long vid_bit, vid_idx; 1822 1823 vid_bit = VLAN_TABLE_BIT(vid); 1824 vid_idx = VLAN_TABLE_IDX(vid); 1825 1826 if (on) { 1827 PMD_DRV_LOG_LINE(DEBUG, "Set VLAN vid=%d for device = %s", 1828 vid, pdata->eth_dev->device->name); 1829 pdata->active_vlans[vid_idx] |= vid_bit; 1830 } else { 1831 PMD_DRV_LOG_LINE(DEBUG, "Reset VLAN vid=%d for device = %s", 1832 vid, pdata->eth_dev->device->name); 1833 pdata->active_vlans[vid_idx] &= ~vid_bit; 1834 } 1835 pdata->hw_if.update_vlan_hash_table(pdata); 1836 return 0; 1837 } 1838 1839 static int 1840 axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1841 enum rte_vlan_type vlan_type, 1842 uint16_t tpid) 1843 { 1844 struct axgbe_port *pdata = dev->data->dev_private; 1845 uint32_t reg = 0; 1846 uint32_t qinq = 0; 1847 1848 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1849 PMD_DRV_LOG_LINE(DEBUG, "EDVLP: qinq = 0x%x", qinq); 1850 1851 switch (vlan_type) { 1852 case RTE_ETH_VLAN_TYPE_INNER: 1853 PMD_DRV_LOG_LINE(DEBUG, "RTE_ETH_VLAN_TYPE_INNER"); 1854 if (qinq) { 1855 if (tpid != 0x8100 && tpid != 0x88a8) 1856 PMD_DRV_LOG_LINE(ERR, 1857 "tag supported 0x8100/0x88A8"); 1858 PMD_DRV_LOG_LINE(DEBUG, "qinq with inner tag"); 1859 1860 /*Enable Inner VLAN Tag */ 1861 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 1); 1862 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1863 PMD_DRV_LOG_LINE(DEBUG, "bit ERIVLT = 0x%x", reg); 1864 1865 } else { 1866 PMD_DRV_LOG_LINE(ERR, 1867 "Inner type not supported in single tag"); 1868 } 1869 break; 1870 case RTE_ETH_VLAN_TYPE_OUTER: 1871 PMD_DRV_LOG_LINE(DEBUG, "RTE_ETH_VLAN_TYPE_OUTER"); 1872 if (qinq) { 1873 PMD_DRV_LOG_LINE(DEBUG, "double tagging is enabled"); 1874 /*Enable outer VLAN tag*/ 1875 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 0); 1876 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1877 PMD_DRV_LOG_LINE(DEBUG, "bit ERIVLT = 0x%x", reg); 1878 1879 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 1); 1880 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANIR, CSVL); 1881 PMD_DRV_LOG_LINE(DEBUG, "bit CSVL = 0x%x", reg); 1882 } else { 1883 if (tpid != 0x8100 && tpid != 0x88a8) 1884 PMD_DRV_LOG_LINE(ERR, 1885 "tag supported 0x8100/0x88A8"); 1886 } 1887 break; 1888 case RTE_ETH_VLAN_TYPE_MAX: 1889 PMD_DRV_LOG_LINE(ERR, "RTE_ETH_VLAN_TYPE_MAX"); 1890 break; 1891 case RTE_ETH_VLAN_TYPE_UNKNOWN: 1892 PMD_DRV_LOG_LINE(ERR, "RTE_ETH_VLAN_TYPE_UNKNOWN"); 1893 break; 1894 } 1895 return 0; 1896 } 1897 1898 static void axgbe_vlan_extend_enable(struct axgbe_port *pdata) 1899 { 1900 int qinq = 0; 1901 1902 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 1); 1903 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1904 PMD_DRV_LOG_LINE(DEBUG, "vlan double tag enabled EDVLP:qinq=0x%x", qinq); 1905 } 1906 1907 static void axgbe_vlan_extend_disable(struct axgbe_port *pdata) 1908 { 1909 int qinq = 0; 1910 1911 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 0); 1912 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1913 PMD_DRV_LOG_LINE(DEBUG, "vlan double tag disable EDVLP:qinq=0x%x", qinq); 1914 } 1915 1916 static int 1917 axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1918 { 1919 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1920 struct axgbe_port *pdata = dev->data->dev_private; 1921 1922 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 1923 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 1924 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 1925 1926 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 1927 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { 1928 PMD_DRV_LOG_LINE(DEBUG, "Strip ON for device = %s", 1929 pdata->eth_dev->device->name); 1930 pdata->hw_if.enable_rx_vlan_stripping(pdata); 1931 } else { 1932 PMD_DRV_LOG_LINE(DEBUG, "Strip OFF for device = %s", 1933 pdata->eth_dev->device->name); 1934 pdata->hw_if.disable_rx_vlan_stripping(pdata); 1935 } 1936 } 1937 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 1938 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 1939 PMD_DRV_LOG_LINE(DEBUG, "Filter ON for device = %s", 1940 pdata->eth_dev->device->name); 1941 pdata->hw_if.enable_rx_vlan_filtering(pdata); 1942 } else { 1943 PMD_DRV_LOG_LINE(DEBUG, "Filter OFF for device = %s", 1944 pdata->eth_dev->device->name); 1945 pdata->hw_if.disable_rx_vlan_filtering(pdata); 1946 } 1947 } 1948 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 1949 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) { 1950 PMD_DRV_LOG_LINE(DEBUG, "enabling vlan extended mode"); 1951 axgbe_vlan_extend_enable(pdata); 1952 /* Set global registers with default ethertype*/ 1953 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER, 1954 RTE_ETHER_TYPE_VLAN); 1955 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER, 1956 RTE_ETHER_TYPE_VLAN); 1957 } else { 1958 PMD_DRV_LOG_LINE(DEBUG, "disabling vlan extended mode"); 1959 axgbe_vlan_extend_disable(pdata); 1960 } 1961 } 1962 return 0; 1963 } 1964 1965 static void axgbe_get_all_hw_features(struct axgbe_port *pdata) 1966 { 1967 unsigned int mac_hfr0, mac_hfr1, mac_hfr2, mac_hfr3; 1968 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 1969 1970 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R); 1971 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R); 1972 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R); 1973 mac_hfr3 = AXGMAC_IOREAD(pdata, MAC_HWF3R); 1974 1975 memset(hw_feat, 0, sizeof(*hw_feat)); 1976 1977 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR); 1978 1979 /* Hardware feature register 0 */ 1980 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 1981 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 1982 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 1983 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 1984 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 1985 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 1986 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 1987 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 1988 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 1989 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 1990 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 1991 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 1992 ADDMACADRSEL); 1993 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 1994 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 1995 1996 /* Hardware feature register 1 */ 1997 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1998 RXFIFOSIZE); 1999 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 2000 TXFIFOSIZE); 2001 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1, 2002 MAC_HWF1R, ADVTHWORD); 2003 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 2004 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 2005 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 2006 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 2007 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 2008 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 2009 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 2010 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 2011 HASHTBLSZ); 2012 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 2013 L3L4FNUM); 2014 2015 /* Hardware feature register 2 */ 2016 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 2017 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 2018 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 2019 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 2020 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 2021 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, 2022 AUXSNAPNUM); 2023 2024 /* Hardware feature register 3 */ 2025 hw_feat->tx_q_vlan_tag_ins = AXGMAC_GET_BITS(mac_hfr3, 2026 MAC_HWF3R, CBTISEL); 2027 hw_feat->no_of_vlan_extn = AXGMAC_GET_BITS(mac_hfr3, 2028 MAC_HWF3R, NRVF); 2029 2030 /* Translate the Hash Table size into actual number */ 2031 switch (hw_feat->hash_table_size) { 2032 case 0: 2033 break; 2034 case 1: 2035 hw_feat->hash_table_size = 64; 2036 break; 2037 case 2: 2038 hw_feat->hash_table_size = 128; 2039 break; 2040 case 3: 2041 hw_feat->hash_table_size = 256; 2042 break; 2043 } 2044 2045 /* Translate the address width setting into actual number */ 2046 switch (hw_feat->dma_width) { 2047 case 0: 2048 hw_feat->dma_width = 32; 2049 break; 2050 case 1: 2051 hw_feat->dma_width = 40; 2052 break; 2053 case 2: 2054 hw_feat->dma_width = 48; 2055 break; 2056 default: 2057 hw_feat->dma_width = 32; 2058 } 2059 2060 /* The Queue, Channel and TC counts are zero based so increment them 2061 * to get the actual number 2062 */ 2063 hw_feat->rx_q_cnt++; 2064 hw_feat->tx_q_cnt++; 2065 hw_feat->rx_ch_cnt++; 2066 hw_feat->tx_ch_cnt++; 2067 hw_feat->tc_cnt++; 2068 2069 /* Translate the fifo sizes into actual numbers */ 2070 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 2071 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 2072 } 2073 2074 static void axgbe_init_all_fptrs(struct axgbe_port *pdata) 2075 { 2076 axgbe_init_function_ptrs_dev(&pdata->hw_if); 2077 axgbe_init_function_ptrs_phy(&pdata->phy_if); 2078 axgbe_init_function_ptrs_i2c(&pdata->i2c_if); 2079 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 2080 } 2081 2082 static void axgbe_set_counts(struct axgbe_port *pdata) 2083 { 2084 /* Set all the function pointers */ 2085 axgbe_init_all_fptrs(pdata); 2086 2087 /* Populate the hardware features */ 2088 axgbe_get_all_hw_features(pdata); 2089 2090 /* Set default max values if not provided */ 2091 if (!pdata->tx_max_channel_count) 2092 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 2093 if (!pdata->rx_max_channel_count) 2094 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 2095 2096 if (!pdata->tx_max_q_count) 2097 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 2098 if (!pdata->rx_max_q_count) 2099 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 2100 2101 /* Calculate the number of Tx and Rx rings to be created 2102 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 2103 * the number of Tx queues to the number of Tx channels 2104 * enabled 2105 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 2106 * number of Rx queues or maximum allowed 2107 */ 2108 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt, 2109 pdata->tx_max_channel_count); 2110 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count, 2111 pdata->tx_max_q_count); 2112 2113 pdata->tx_q_count = pdata->tx_ring_count; 2114 2115 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt, 2116 pdata->rx_max_channel_count); 2117 2118 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt, 2119 pdata->rx_max_q_count); 2120 } 2121 2122 static void axgbe_default_config(struct axgbe_port *pdata) 2123 { 2124 pdata->pblx8 = DMA_PBL_X8_ENABLE; 2125 pdata->tx_sf_mode = MTL_TSF_ENABLE; 2126 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 2127 pdata->tx_pbl = DMA_PBL_32; 2128 pdata->tx_osp_mode = DMA_OSP_ENABLE; 2129 pdata->rx_sf_mode = MTL_RSF_ENABLE; 2130 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 2131 pdata->rx_pbl = DMA_PBL_32; 2132 pdata->pause_autoneg = 1; 2133 pdata->tx_pause = 0; 2134 pdata->rx_pause = 0; 2135 pdata->phy_speed = SPEED_UNKNOWN; 2136 pdata->power_down = 0; 2137 } 2138 2139 /* Used in dev_start by primary process and then 2140 * in dev_init by secondary process when attaching to an existing ethdev. 2141 */ 2142 void 2143 axgbe_set_tx_function(struct rte_eth_dev *dev) 2144 { 2145 struct axgbe_port *pdata = dev->data->dev_private; 2146 2147 dev->tx_pkt_burst = &axgbe_xmit_pkts; 2148 2149 if (pdata->multi_segs_tx) 2150 dev->tx_pkt_burst = &axgbe_xmit_pkts_seg; 2151 #ifdef RTE_ARCH_X86 2152 struct axgbe_tx_queue *txq = dev->data->tx_queues[0]; 2153 if (!txq->vector_disable && 2154 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) 2155 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec; 2156 #endif 2157 } 2158 2159 void 2160 axgbe_set_rx_function(struct rte_eth_dev *dev) 2161 { 2162 struct rte_eth_dev_data *dev_data = dev->data; 2163 uint16_t max_pkt_len; 2164 struct axgbe_port *pdata; 2165 2166 pdata = dev->data->dev_private; 2167 max_pkt_len = dev_data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 2168 if ((dev_data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) || 2169 max_pkt_len > pdata->rx_buf_size) 2170 dev_data->scattered_rx = 1; 2171 /* Scatter Rx handling */ 2172 if (dev_data->scattered_rx) 2173 dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts; 2174 else 2175 dev->rx_pkt_burst = &axgbe_recv_pkts; 2176 } 2177 2178 /* 2179 * It returns 0 on success. 2180 */ 2181 static int 2182 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) 2183 { 2184 PMD_INIT_FUNC_TRACE(); 2185 struct axgbe_port *pdata; 2186 struct rte_pci_device *pci_dev; 2187 uint32_t reg, mac_lo, mac_hi; 2188 uint32_t len; 2189 int ret; 2190 2191 unsigned int eax = 0, ebx = 0, ecx = 0, edx = 0; 2192 unsigned char cpu_family = 0, cpu_model = 0; 2193 2194 eth_dev->dev_ops = &axgbe_eth_dev_ops; 2195 2196 eth_dev->rx_descriptor_status = axgbe_dev_rx_descriptor_status; 2197 eth_dev->tx_descriptor_status = axgbe_dev_tx_descriptor_status; 2198 2199 eth_dev->tx_pkt_burst = &axgbe_xmit_pkts; 2200 eth_dev->rx_pkt_burst = &axgbe_recv_pkts; 2201 2202 /* 2203 * For secondary processes, we don't initialise any further as primary 2204 * has already done this work. 2205 */ 2206 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2207 axgbe_set_tx_function(eth_dev); 2208 axgbe_set_rx_function(eth_dev); 2209 return 0; 2210 } 2211 2212 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2213 2214 pdata = eth_dev->data->dev_private; 2215 /* initial state */ 2216 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 2217 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 2218 pdata->eth_dev = eth_dev; 2219 2220 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2221 pdata->pci_dev = pci_dev; 2222 2223 pdata->xgmac_regs = 2224 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; 2225 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs 2226 + AXGBE_MAC_PROP_OFFSET); 2227 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs 2228 + AXGBE_I2C_CTRL_OFFSET); 2229 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; 2230 2231 /* version specific driver data*/ 2232 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A) 2233 pdata->vdata = &axgbe_v2a; 2234 else 2235 pdata->vdata = &axgbe_v2b; 2236 2237 /* 2238 * Use CPUID to get Family and model ID to identify the CPU 2239 */ 2240 __cpuid(0x0, eax, ebx, ecx, edx); 2241 2242 if (ebx == CPUID_VENDOR_AuthenticAMD_ebx && 2243 edx == CPUID_VENDOR_AuthenticAMD_edx && 2244 ecx == CPUID_VENDOR_AuthenticAMD_ecx) { 2245 int unknown_cpu = 0; 2246 eax = 0, ebx = 0, ecx = 0, edx = 0; 2247 2248 __cpuid(0x1, eax, ebx, ecx, edx); 2249 2250 cpu_family = ((GET_BITS(eax, 8, 4)) + (GET_BITS(eax, 20, 8))); 2251 cpu_model = ((GET_BITS(eax, 4, 4)) | (((GET_BITS(eax, 16, 4)) << 4) & 0xF0)); 2252 2253 switch (cpu_family) { 2254 case Fam17h: 2255 /* V1000/R1000 */ 2256 if (cpu_model >= 0x10 && cpu_model <= 0x1F) { 2257 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; 2258 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; 2259 /* EPYC 3000 */ 2260 } else if (cpu_model >= 0x01 && cpu_model <= 0x0F) { 2261 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 2262 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 2263 } else { 2264 unknown_cpu = 1; 2265 } 2266 break; 2267 case Fam19h: 2268 /* V3000 (Yellow Carp) */ 2269 if (cpu_model >= 0x44 && cpu_model <= 0x47) { 2270 pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF; 2271 pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT; 2272 2273 /* Yellow Carp devices do not need cdr workaround */ 2274 pdata->vdata->an_cdr_workaround = 0; 2275 2276 /* Yellow Carp devices do not need rrc */ 2277 pdata->vdata->enable_rrc = 0; 2278 } else { 2279 unknown_cpu = 1; 2280 } 2281 break; 2282 default: 2283 unknown_cpu = 1; 2284 break; 2285 } 2286 if (unknown_cpu) { 2287 PMD_DRV_LOG_LINE(ERR, "Unknown CPU family, no supported axgbe device found"); 2288 return -ENODEV; 2289 } 2290 } 2291 2292 /* Configure the PCS indirect addressing support */ 2293 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); 2294 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 2295 pdata->xpcs_window <<= 6; 2296 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 2297 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 2298 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 2299 2300 PMD_INIT_LOG(DEBUG, 2301 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, 2302 pdata->xpcs_window_size, pdata->xpcs_window_mask); 2303 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 2304 2305 /* Retrieve the MAC address */ 2306 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 2307 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 2308 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff; 2309 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff; 2310 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff; 2311 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff; 2312 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff; 2313 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff; 2314 2315 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_MAC_ADDRS; 2316 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", len, 0); 2317 2318 if (!eth_dev->data->mac_addrs) { 2319 PMD_INIT_LOG(ERR, 2320 "Failed to alloc %u bytes needed to " 2321 "store MAC addresses", len); 2322 return -ENOMEM; 2323 } 2324 2325 /* Allocate memory for storing hash filter MAC addresses */ 2326 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS; 2327 eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr", 2328 len, 0); 2329 2330 if (eth_dev->data->hash_mac_addrs == NULL) { 2331 PMD_INIT_LOG(ERR, 2332 "Failed to allocate %d bytes needed to " 2333 "store MAC addresses", len); 2334 return -ENOMEM; 2335 } 2336 2337 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr)) 2338 rte_eth_random_addr(pdata->mac_addr.addr_bytes); 2339 2340 /* Copy the permanent MAC address */ 2341 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]); 2342 2343 /* Clock settings */ 2344 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ; 2345 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 2346 2347 /* Set the DMA coherency values */ 2348 pdata->coherent = 1; 2349 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN; 2350 pdata->arcache = AXGBE_DMA_OS_ARCACHE; 2351 pdata->awcache = AXGBE_DMA_OS_AWCACHE; 2352 2353 /* Read the port property registers */ 2354 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0); 2355 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1); 2356 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2); 2357 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3); 2358 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4); 2359 2360 /* Set the maximum channels and queues */ 2361 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_TX_DMA); 2362 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_RX_DMA); 2363 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_TX_QUEUES); 2364 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_RX_QUEUES); 2365 2366 /* Set the hardware channel and queue counts */ 2367 axgbe_set_counts(pdata); 2368 2369 /* Set the maximum fifo amounts */ 2370 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2, TX_FIFO_SIZE); 2371 pdata->tx_max_fifo_size *= 16384; 2372 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size, 2373 pdata->vdata->tx_max_fifo_size); 2374 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2, RX_FIFO_SIZE); 2375 pdata->rx_max_fifo_size *= 16384; 2376 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size, 2377 pdata->vdata->rx_max_fifo_size); 2378 /* Issue software reset to DMA */ 2379 ret = pdata->hw_if.exit(pdata); 2380 if (ret) 2381 PMD_DRV_LOG_LINE(ERR, "hw_if->exit EBUSY error"); 2382 2383 /* Set default configuration data */ 2384 axgbe_default_config(pdata); 2385 2386 /* Set default max values if not provided */ 2387 if (!pdata->tx_max_fifo_size) 2388 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 2389 if (!pdata->rx_max_fifo_size) 2390 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 2391 2392 pdata->tx_desc_count = AXGBE_MAX_RING_DESC; 2393 pdata->rx_desc_count = AXGBE_MAX_RING_DESC; 2394 pthread_mutex_init(&pdata->xpcs_mutex, NULL); 2395 pthread_mutex_init(&pdata->i2c_mutex, NULL); 2396 pthread_mutex_init(&pdata->an_mutex, NULL); 2397 pthread_mutex_init(&pdata->phy_mutex, NULL); 2398 2399 ret = pdata->phy_if.phy_init(pdata); 2400 if (ret) { 2401 rte_free(eth_dev->data->mac_addrs); 2402 eth_dev->data->mac_addrs = NULL; 2403 return ret; 2404 } 2405 2406 rte_intr_callback_register(pci_dev->intr_handle, 2407 axgbe_dev_interrupt_handler, 2408 (void *)eth_dev); 2409 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 2410 eth_dev->data->port_id, pci_dev->id.vendor_id, 2411 pci_dev->id.device_id); 2412 2413 return 0; 2414 } 2415 2416 static int 2417 axgbe_dev_close(struct rte_eth_dev *eth_dev) 2418 { 2419 struct rte_pci_device *pci_dev; 2420 struct axgbe_port *pdata; 2421 2422 PMD_INIT_FUNC_TRACE(); 2423 2424 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2425 return 0; 2426 2427 pdata = eth_dev->data->dev_private; 2428 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2429 axgbe_dev_clear_queues(eth_dev); 2430 2431 /* disable uio intr before callback unregister */ 2432 rte_intr_disable(pci_dev->intr_handle); 2433 rte_intr_callback_unregister(pci_dev->intr_handle, 2434 axgbe_dev_interrupt_handler, 2435 (void *)eth_dev); 2436 2437 /* Disable all interrupts in the hardware */ 2438 XP_IOWRITE(pdata, XP_INT_EN, 0x0); 2439 2440 return 0; 2441 } 2442 2443 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2444 struct rte_pci_device *pci_dev) 2445 { 2446 return rte_eth_dev_pci_generic_probe(pci_dev, 2447 sizeof(struct axgbe_port), eth_axgbe_dev_init); 2448 } 2449 2450 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev) 2451 { 2452 return rte_eth_dev_pci_generic_remove(pci_dev, axgbe_dev_close); 2453 } 2454 2455 static struct rte_pci_driver rte_axgbe_pmd = { 2456 .id_table = pci_id_axgbe_map, 2457 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2458 .probe = eth_axgbe_pci_probe, 2459 .remove = eth_axgbe_pci_remove, 2460 }; 2461 2462 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd); 2463 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map); 2464 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 2465 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_init, init, NOTICE); 2466 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_driver, driver, NOTICE); 2467