1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_rxtx.h" 7 #include "axgbe_ethdev.h" 8 #include "axgbe_common.h" 9 #include "axgbe_phy.h" 10 #include "axgbe_regs.h" 11 #include "rte_time.h" 12 13 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); 14 static int axgbe_dev_configure(struct rte_eth_dev *dev); 15 static int axgbe_dev_start(struct rte_eth_dev *dev); 16 static void axgbe_dev_stop(struct rte_eth_dev *dev); 17 static void axgbe_dev_interrupt_handler(void *param); 18 static int axgbe_dev_close(struct rte_eth_dev *dev); 19 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 20 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 21 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 22 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 23 static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, 24 struct rte_ether_addr *mac_addr); 25 static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, 26 struct rte_ether_addr *mac_addr, 27 uint32_t index, 28 uint32_t vmdq); 29 static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 30 static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 31 struct rte_ether_addr *mc_addr_set, 32 uint32_t nb_mc_addr); 33 static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 34 struct rte_ether_addr *mac_addr, 35 uint8_t add); 36 static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, 37 uint8_t add); 38 static int axgbe_dev_link_update(struct rte_eth_dev *dev, 39 int wait_to_complete); 40 static int axgbe_dev_get_regs(struct rte_eth_dev *dev, 41 struct rte_dev_reg_info *regs); 42 static int axgbe_dev_stats_get(struct rte_eth_dev *dev, 43 struct rte_eth_stats *stats); 44 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev); 45 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev, 46 struct rte_eth_xstat *stats, 47 unsigned int n); 48 static int 49 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 50 struct rte_eth_xstat_name *xstats_names, 51 unsigned int size); 52 static int 53 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 54 const uint64_t *ids, 55 uint64_t *values, 56 unsigned int n); 57 static int 58 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 59 struct rte_eth_xstat_name *xstats_names, 60 const uint64_t *ids, 61 unsigned int size); 62 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev); 63 static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 64 struct rte_eth_rss_reta_entry64 *reta_conf, 65 uint16_t reta_size); 66 static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 67 struct rte_eth_rss_reta_entry64 *reta_conf, 68 uint16_t reta_size); 69 static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 70 struct rte_eth_rss_conf *rss_conf); 71 static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 72 struct rte_eth_rss_conf *rss_conf); 73 static int axgbe_dev_info_get(struct rte_eth_dev *dev, 74 struct rte_eth_dev_info *dev_info); 75 static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, 76 struct rte_eth_fc_conf *fc_conf); 77 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, 78 struct rte_eth_fc_conf *fc_conf); 79 static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 80 struct rte_eth_pfc_conf *pfc_conf); 81 static void axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 82 struct rte_eth_rxq_info *qinfo); 83 static void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 84 struct rte_eth_txq_info *qinfo); 85 const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 86 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 87 88 static int 89 axgbe_timesync_enable(struct rte_eth_dev *dev); 90 static int 91 axgbe_timesync_disable(struct rte_eth_dev *dev); 92 static int 93 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 94 struct timespec *timestamp, uint32_t flags); 95 static int 96 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 97 struct timespec *timestamp); 98 static int 99 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 100 static int 101 axgbe_timesync_read_time(struct rte_eth_dev *dev, 102 struct timespec *timestamp); 103 static int 104 axgbe_timesync_write_time(struct rte_eth_dev *dev, 105 const struct timespec *timestamp); 106 static void 107 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 108 unsigned int nsec); 109 static void 110 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 111 unsigned int addend); 112 113 struct axgbe_xstats { 114 char name[RTE_ETH_XSTATS_NAME_SIZE]; 115 int offset; 116 }; 117 118 #define AXGMAC_MMC_STAT(_string, _var) \ 119 { _string, \ 120 offsetof(struct axgbe_mmc_stats, _var), \ 121 } 122 123 static const struct axgbe_xstats axgbe_xstats_strings[] = { 124 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb), 125 AXGMAC_MMC_STAT("tx_packets", txframecount_gb), 126 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb), 127 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb), 128 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb), 129 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g), 130 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb), 131 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb), 132 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb), 133 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb), 134 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb), 135 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb), 136 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror), 137 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes), 138 139 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb), 140 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb), 141 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g), 142 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g), 143 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g), 144 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb), 145 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb), 146 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb), 147 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb), 148 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb), 149 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb), 150 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb), 151 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g), 152 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g), 153 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror), 154 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror), 155 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror), 156 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror), 157 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype), 158 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow), 159 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror), 160 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes), 161 }; 162 163 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings) 164 165 /* The set of PCI devices this driver supports */ 166 #define AMD_PCI_VENDOR_ID 0x1022 167 #define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0 168 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 169 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459 170 171 static const struct rte_pci_id pci_id_axgbe_map[] = { 172 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)}, 173 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)}, 174 { .vendor_id = 0, }, 175 }; 176 177 static struct axgbe_version_data axgbe_v2a = { 178 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 179 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 180 .mmc_64bit = 1, 181 .tx_max_fifo_size = 229376, 182 .rx_max_fifo_size = 229376, 183 .tx_tstamp_workaround = 1, 184 .ecc_support = 1, 185 .i2c_support = 1, 186 .an_cdr_workaround = 1, 187 }; 188 189 static struct axgbe_version_data axgbe_v2b = { 190 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 191 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 192 .mmc_64bit = 1, 193 .tx_max_fifo_size = 65536, 194 .rx_max_fifo_size = 65536, 195 .tx_tstamp_workaround = 1, 196 .ecc_support = 1, 197 .i2c_support = 1, 198 .an_cdr_workaround = 1, 199 }; 200 201 static const struct rte_eth_desc_lim rx_desc_lim = { 202 .nb_max = AXGBE_MAX_RING_DESC, 203 .nb_min = AXGBE_MIN_RING_DESC, 204 .nb_align = 8, 205 }; 206 207 static const struct rte_eth_desc_lim tx_desc_lim = { 208 .nb_max = AXGBE_MAX_RING_DESC, 209 .nb_min = AXGBE_MIN_RING_DESC, 210 .nb_align = 8, 211 }; 212 213 static const struct eth_dev_ops axgbe_eth_dev_ops = { 214 .dev_configure = axgbe_dev_configure, 215 .dev_start = axgbe_dev_start, 216 .dev_stop = axgbe_dev_stop, 217 .dev_close = axgbe_dev_close, 218 .promiscuous_enable = axgbe_dev_promiscuous_enable, 219 .promiscuous_disable = axgbe_dev_promiscuous_disable, 220 .allmulticast_enable = axgbe_dev_allmulticast_enable, 221 .allmulticast_disable = axgbe_dev_allmulticast_disable, 222 .mac_addr_set = axgbe_dev_mac_addr_set, 223 .mac_addr_add = axgbe_dev_mac_addr_add, 224 .mac_addr_remove = axgbe_dev_mac_addr_remove, 225 .set_mc_addr_list = axgbe_dev_set_mc_addr_list, 226 .uc_hash_table_set = axgbe_dev_uc_hash_table_set, 227 .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set, 228 .link_update = axgbe_dev_link_update, 229 .get_reg = axgbe_dev_get_regs, 230 .stats_get = axgbe_dev_stats_get, 231 .stats_reset = axgbe_dev_stats_reset, 232 .xstats_get = axgbe_dev_xstats_get, 233 .xstats_reset = axgbe_dev_xstats_reset, 234 .xstats_get_names = axgbe_dev_xstats_get_names, 235 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id, 236 .xstats_get_by_id = axgbe_dev_xstats_get_by_id, 237 .reta_update = axgbe_dev_rss_reta_update, 238 .reta_query = axgbe_dev_rss_reta_query, 239 .rss_hash_update = axgbe_dev_rss_hash_update, 240 .rss_hash_conf_get = axgbe_dev_rss_hash_conf_get, 241 .dev_infos_get = axgbe_dev_info_get, 242 .rx_queue_setup = axgbe_dev_rx_queue_setup, 243 .rx_queue_release = axgbe_dev_rx_queue_release, 244 .tx_queue_setup = axgbe_dev_tx_queue_setup, 245 .tx_queue_release = axgbe_dev_tx_queue_release, 246 .flow_ctrl_get = axgbe_flow_ctrl_get, 247 .flow_ctrl_set = axgbe_flow_ctrl_set, 248 .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set, 249 .rxq_info_get = axgbe_rxq_info_get, 250 .txq_info_get = axgbe_txq_info_get, 251 .dev_supported_ptypes_get = axgbe_dev_supported_ptypes_get, 252 .mtu_set = axgb_mtu_set, 253 .timesync_enable = axgbe_timesync_enable, 254 .timesync_disable = axgbe_timesync_disable, 255 .timesync_read_rx_timestamp = axgbe_timesync_read_rx_timestamp, 256 .timesync_read_tx_timestamp = axgbe_timesync_read_tx_timestamp, 257 .timesync_adjust_time = axgbe_timesync_adjust_time, 258 .timesync_read_time = axgbe_timesync_read_time, 259 .timesync_write_time = axgbe_timesync_write_time, 260 }; 261 262 static int axgbe_phy_reset(struct axgbe_port *pdata) 263 { 264 pdata->phy_link = -1; 265 pdata->phy_speed = SPEED_UNKNOWN; 266 return pdata->phy_if.phy_reset(pdata); 267 } 268 269 /* 270 * Interrupt handler triggered by NIC for handling 271 * specific interrupt. 272 * 273 * @param handle 274 * Pointer to interrupt handle. 275 * @param param 276 * The address of parameter (struct rte_eth_dev *) regsitered before. 277 * 278 * @return 279 * void 280 */ 281 static void 282 axgbe_dev_interrupt_handler(void *param) 283 { 284 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 285 struct axgbe_port *pdata = dev->data->dev_private; 286 unsigned int dma_isr, dma_ch_isr; 287 288 pdata->phy_if.an_isr(pdata); 289 /*DMA related interrupts*/ 290 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR); 291 PMD_DRV_LOG(DEBUG, "DMA_ISR=%#010x\n", dma_isr); 292 if (dma_isr) { 293 if (dma_isr & 1) { 294 dma_ch_isr = 295 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *) 296 pdata->rx_queues[0], 297 DMA_CH_SR); 298 PMD_DRV_LOG(DEBUG, "DMA_CH0_ISR=%#010x\n", dma_ch_isr); 299 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *) 300 pdata->rx_queues[0], 301 DMA_CH_SR, dma_ch_isr); 302 } 303 } 304 /* Unmask interrupts since disabled after generation */ 305 rte_intr_ack(&pdata->pci_dev->intr_handle); 306 } 307 308 /* 309 * Configure device link speed and setup link. 310 * It returns 0 on success. 311 */ 312 static int 313 axgbe_dev_configure(struct rte_eth_dev *dev) 314 { 315 struct axgbe_port *pdata = dev->data->dev_private; 316 /* Checksum offload to hardware */ 317 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads & 318 DEV_RX_OFFLOAD_CHECKSUM; 319 return 0; 320 } 321 322 static int 323 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev) 324 { 325 struct axgbe_port *pdata = dev->data->dev_private; 326 327 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 328 pdata->rss_enable = 1; 329 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE) 330 pdata->rss_enable = 0; 331 else 332 return -1; 333 return 0; 334 } 335 336 static int 337 axgbe_dev_start(struct rte_eth_dev *dev) 338 { 339 struct axgbe_port *pdata = dev->data->dev_private; 340 int ret; 341 struct rte_eth_dev_data *dev_data = dev->data; 342 uint16_t max_pkt_len = dev_data->dev_conf.rxmode.max_rx_pkt_len; 343 344 dev->dev_ops = &axgbe_eth_dev_ops; 345 346 PMD_INIT_FUNC_TRACE(); 347 348 /* Multiqueue RSS */ 349 ret = axgbe_dev_rx_mq_config(dev); 350 if (ret) { 351 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n"); 352 return ret; 353 } 354 ret = axgbe_phy_reset(pdata); 355 if (ret) { 356 PMD_DRV_LOG(ERR, "phy reset failed\n"); 357 return ret; 358 } 359 ret = pdata->hw_if.init(pdata); 360 if (ret) { 361 PMD_DRV_LOG(ERR, "dev_init failed\n"); 362 return ret; 363 } 364 365 /* enable uio/vfio intr/eventfd mapping */ 366 rte_intr_enable(&pdata->pci_dev->intr_handle); 367 368 /* phy start*/ 369 pdata->phy_if.phy_start(pdata); 370 axgbe_dev_enable_tx(dev); 371 axgbe_dev_enable_rx(dev); 372 373 rte_bit_relaxed_clear32(AXGBE_STOPPED, &pdata->dev_state); 374 rte_bit_relaxed_clear32(AXGBE_DOWN, &pdata->dev_state); 375 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) || 376 max_pkt_len > pdata->rx_buf_size) 377 dev_data->scattered_rx = 1; 378 379 /* Scatter Rx handling */ 380 if (dev_data->scattered_rx) 381 dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts; 382 else 383 dev->rx_pkt_burst = &axgbe_recv_pkts; 384 385 return 0; 386 } 387 388 /* Stop device: disable rx and tx functions to allow for reconfiguring. */ 389 static void 390 axgbe_dev_stop(struct rte_eth_dev *dev) 391 { 392 struct axgbe_port *pdata = dev->data->dev_private; 393 394 PMD_INIT_FUNC_TRACE(); 395 396 rte_intr_disable(&pdata->pci_dev->intr_handle); 397 398 if (rte_bit_relaxed_get32(AXGBE_STOPPED, &pdata->dev_state)) 399 return; 400 401 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 402 axgbe_dev_disable_tx(dev); 403 axgbe_dev_disable_rx(dev); 404 405 pdata->phy_if.phy_stop(pdata); 406 pdata->hw_if.exit(pdata); 407 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); 408 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 409 } 410 411 static int 412 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 413 { 414 struct axgbe_port *pdata = dev->data->dev_private; 415 416 PMD_INIT_FUNC_TRACE(); 417 418 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); 419 420 return 0; 421 } 422 423 static int 424 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 425 { 426 struct axgbe_port *pdata = dev->data->dev_private; 427 428 PMD_INIT_FUNC_TRACE(); 429 430 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); 431 432 return 0; 433 } 434 435 static int 436 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 437 { 438 struct axgbe_port *pdata = dev->data->dev_private; 439 440 PMD_INIT_FUNC_TRACE(); 441 442 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 443 return 0; 444 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1); 445 446 return 0; 447 } 448 449 static int 450 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 451 { 452 struct axgbe_port *pdata = dev->data->dev_private; 453 454 PMD_INIT_FUNC_TRACE(); 455 456 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 457 return 0; 458 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0); 459 460 return 0; 461 } 462 463 static int 464 axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 465 { 466 struct axgbe_port *pdata = dev->data->dev_private; 467 468 /* Set Default MAC Addr */ 469 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0); 470 471 return 0; 472 } 473 474 static int 475 axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 476 uint32_t index, uint32_t pool __rte_unused) 477 { 478 struct axgbe_port *pdata = dev->data->dev_private; 479 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 480 481 if (index > hw_feat->addn_mac) { 482 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index); 483 return -EINVAL; 484 } 485 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index); 486 return 0; 487 } 488 489 static int 490 axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 491 struct rte_eth_rss_reta_entry64 *reta_conf, 492 uint16_t reta_size) 493 { 494 struct axgbe_port *pdata = dev->data->dev_private; 495 unsigned int i, idx, shift; 496 int ret; 497 498 if (!pdata->rss_enable) { 499 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 500 return -ENOTSUP; 501 } 502 503 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 504 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size); 505 return -EINVAL; 506 } 507 508 for (i = 0; i < reta_size; i++) { 509 idx = i / RTE_RETA_GROUP_SIZE; 510 shift = i % RTE_RETA_GROUP_SIZE; 511 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 512 continue; 513 pdata->rss_table[i] = reta_conf[idx].reta[shift]; 514 } 515 516 /* Program the lookup table */ 517 ret = axgbe_write_rss_lookup_table(pdata); 518 return ret; 519 } 520 521 static int 522 axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 523 struct rte_eth_rss_reta_entry64 *reta_conf, 524 uint16_t reta_size) 525 { 526 struct axgbe_port *pdata = dev->data->dev_private; 527 unsigned int i, idx, shift; 528 529 if (!pdata->rss_enable) { 530 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 531 return -ENOTSUP; 532 } 533 534 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 535 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size); 536 return -EINVAL; 537 } 538 539 for (i = 0; i < reta_size; i++) { 540 idx = i / RTE_RETA_GROUP_SIZE; 541 shift = i % RTE_RETA_GROUP_SIZE; 542 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 543 continue; 544 reta_conf[idx].reta[shift] = pdata->rss_table[i]; 545 } 546 return 0; 547 } 548 549 static int 550 axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 551 struct rte_eth_rss_conf *rss_conf) 552 { 553 struct axgbe_port *pdata = dev->data->dev_private; 554 int ret; 555 556 if (!pdata->rss_enable) { 557 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 558 return -ENOTSUP; 559 } 560 561 if (rss_conf == NULL) { 562 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n"); 563 return -EINVAL; 564 } 565 566 if (rss_conf->rss_key != NULL && 567 rss_conf->rss_key_len == AXGBE_RSS_HASH_KEY_SIZE) { 568 rte_memcpy(pdata->rss_key, rss_conf->rss_key, 569 AXGBE_RSS_HASH_KEY_SIZE); 570 /* Program the hash key */ 571 ret = axgbe_write_rss_hash_key(pdata); 572 if (ret != 0) 573 return ret; 574 } 575 576 pdata->rss_hf = rss_conf->rss_hf & AXGBE_RSS_OFFLOAD; 577 578 if (pdata->rss_hf & (ETH_RSS_IPV4 | ETH_RSS_IPV6)) 579 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); 580 if (pdata->rss_hf & 581 (ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV6_TCP)) 582 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); 583 if (pdata->rss_hf & 584 (ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP)) 585 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); 586 587 /* Set the RSS options */ 588 AXGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 589 590 return 0; 591 } 592 593 static int 594 axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 595 struct rte_eth_rss_conf *rss_conf) 596 { 597 struct axgbe_port *pdata = dev->data->dev_private; 598 599 if (!pdata->rss_enable) { 600 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 601 return -ENOTSUP; 602 } 603 604 if (rss_conf == NULL) { 605 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n"); 606 return -EINVAL; 607 } 608 609 if (rss_conf->rss_key != NULL && 610 rss_conf->rss_key_len >= AXGBE_RSS_HASH_KEY_SIZE) { 611 rte_memcpy(rss_conf->rss_key, pdata->rss_key, 612 AXGBE_RSS_HASH_KEY_SIZE); 613 } 614 rss_conf->rss_key_len = AXGBE_RSS_HASH_KEY_SIZE; 615 rss_conf->rss_hf = pdata->rss_hf; 616 return 0; 617 } 618 619 static void 620 axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 621 { 622 struct axgbe_port *pdata = dev->data->dev_private; 623 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 624 625 if (index > hw_feat->addn_mac) { 626 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index); 627 return; 628 } 629 axgbe_set_mac_addn_addr(pdata, NULL, index); 630 } 631 632 static int 633 axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 634 struct rte_ether_addr *mc_addr_set, 635 uint32_t nb_mc_addr) 636 { 637 struct axgbe_port *pdata = dev->data->dev_private; 638 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 639 uint32_t index = 1; /* 0 is always default mac */ 640 uint32_t i; 641 642 if (nb_mc_addr > hw_feat->addn_mac) { 643 PMD_DRV_LOG(ERR, "Invalid Index %d\n", nb_mc_addr); 644 return -EINVAL; 645 } 646 647 /* clear unicast addresses */ 648 for (i = 1; i < hw_feat->addn_mac; i++) { 649 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i])) 650 continue; 651 memset(&dev->data->mac_addrs[i], 0, 652 sizeof(struct rte_ether_addr)); 653 } 654 655 while (nb_mc_addr--) 656 axgbe_set_mac_addn_addr(pdata, (u8 *)mc_addr_set++, index++); 657 658 return 0; 659 } 660 661 static int 662 axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 663 struct rte_ether_addr *mac_addr, uint8_t add) 664 { 665 struct axgbe_port *pdata = dev->data->dev_private; 666 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 667 668 if (!hw_feat->hash_table_size) { 669 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); 670 return -ENOTSUP; 671 } 672 673 axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add); 674 675 if (pdata->uc_hash_mac_addr > 0) { 676 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 677 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 678 } else { 679 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 680 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 681 } 682 return 0; 683 } 684 685 static int 686 axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add) 687 { 688 struct axgbe_port *pdata = dev->data->dev_private; 689 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 690 uint32_t index; 691 692 if (!hw_feat->hash_table_size) { 693 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); 694 return -ENOTSUP; 695 } 696 697 for (index = 0; index < pdata->hash_table_count; index++) { 698 if (add) 699 pdata->uc_hash_table[index] = ~0; 700 else 701 pdata->uc_hash_table[index] = 0; 702 703 PMD_DRV_LOG(DEBUG, "%s MAC hash table at Index %#x\n", 704 add ? "set" : "clear", index); 705 706 AXGMAC_IOWRITE(pdata, MAC_HTR(index), 707 pdata->uc_hash_table[index]); 708 } 709 710 if (add) { 711 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 712 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 713 } else { 714 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 715 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 716 } 717 return 0; 718 } 719 720 /* return 0 means link status changed, -1 means not changed */ 721 static int 722 axgbe_dev_link_update(struct rte_eth_dev *dev, 723 int wait_to_complete __rte_unused) 724 { 725 struct axgbe_port *pdata = dev->data->dev_private; 726 struct rte_eth_link link; 727 int ret = 0; 728 729 PMD_INIT_FUNC_TRACE(); 730 rte_delay_ms(800); 731 732 pdata->phy_if.phy_status(pdata); 733 734 memset(&link, 0, sizeof(struct rte_eth_link)); 735 link.link_duplex = pdata->phy.duplex; 736 link.link_status = pdata->phy_link; 737 link.link_speed = pdata->phy_speed; 738 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 739 ETH_LINK_SPEED_FIXED); 740 ret = rte_eth_linkstatus_set(dev, &link); 741 if (ret == -1) 742 PMD_DRV_LOG(ERR, "No change in link status\n"); 743 744 return ret; 745 } 746 747 static int 748 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 749 { 750 struct axgbe_port *pdata = dev->data->dev_private; 751 752 if (regs->data == NULL) { 753 regs->length = axgbe_regs_get_count(pdata); 754 regs->width = sizeof(uint32_t); 755 return 0; 756 } 757 758 /* Only full register dump is supported */ 759 if (regs->length && 760 regs->length != (uint32_t)axgbe_regs_get_count(pdata)) 761 return -ENOTSUP; 762 763 regs->version = pdata->pci_dev->id.vendor_id << 16 | 764 pdata->pci_dev->id.device_id; 765 axgbe_regs_dump(pdata, regs->data); 766 return 0; 767 } 768 static void axgbe_read_mmc_stats(struct axgbe_port *pdata) 769 { 770 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 771 772 /* Freeze counters */ 773 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 774 775 /* Tx counters */ 776 stats->txoctetcount_gb += 777 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO); 778 stats->txoctetcount_gb += 779 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32); 780 781 stats->txframecount_gb += 782 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO); 783 stats->txframecount_gb += 784 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32); 785 786 stats->txbroadcastframes_g += 787 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO); 788 stats->txbroadcastframes_g += 789 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32); 790 791 stats->txmulticastframes_g += 792 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO); 793 stats->txmulticastframes_g += 794 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32); 795 796 stats->tx64octets_gb += 797 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO); 798 stats->tx64octets_gb += 799 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32); 800 801 stats->tx65to127octets_gb += 802 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO); 803 stats->tx65to127octets_gb += 804 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32); 805 806 stats->tx128to255octets_gb += 807 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO); 808 stats->tx128to255octets_gb += 809 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32); 810 811 stats->tx256to511octets_gb += 812 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO); 813 stats->tx256to511octets_gb += 814 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32); 815 816 stats->tx512to1023octets_gb += 817 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO); 818 stats->tx512to1023octets_gb += 819 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32); 820 821 stats->tx1024tomaxoctets_gb += 822 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 823 stats->tx1024tomaxoctets_gb += 824 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32); 825 826 stats->txunicastframes_gb += 827 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO); 828 stats->txunicastframes_gb += 829 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32); 830 831 stats->txmulticastframes_gb += 832 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 833 stats->txmulticastframes_gb += 834 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32); 835 836 stats->txbroadcastframes_g += 837 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 838 stats->txbroadcastframes_g += 839 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32); 840 841 stats->txunderflowerror += 842 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO); 843 stats->txunderflowerror += 844 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32); 845 846 stats->txoctetcount_g += 847 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO); 848 stats->txoctetcount_g += 849 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32); 850 851 stats->txframecount_g += 852 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO); 853 stats->txframecount_g += 854 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32); 855 856 stats->txpauseframes += 857 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO); 858 stats->txpauseframes += 859 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32); 860 861 stats->txvlanframes_g += 862 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO); 863 stats->txvlanframes_g += 864 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32); 865 866 /* Rx counters */ 867 stats->rxframecount_gb += 868 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO); 869 stats->rxframecount_gb += 870 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32); 871 872 stats->rxoctetcount_gb += 873 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO); 874 stats->rxoctetcount_gb += 875 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32); 876 877 stats->rxoctetcount_g += 878 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO); 879 stats->rxoctetcount_g += 880 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32); 881 882 stats->rxbroadcastframes_g += 883 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO); 884 stats->rxbroadcastframes_g += 885 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32); 886 887 stats->rxmulticastframes_g += 888 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO); 889 stats->rxmulticastframes_g += 890 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32); 891 892 stats->rxcrcerror += 893 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO); 894 stats->rxcrcerror += 895 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32); 896 897 stats->rxrunterror += 898 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR); 899 900 stats->rxjabbererror += 901 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR); 902 903 stats->rxundersize_g += 904 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G); 905 906 stats->rxoversize_g += 907 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G); 908 909 stats->rx64octets_gb += 910 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO); 911 stats->rx64octets_gb += 912 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32); 913 914 stats->rx65to127octets_gb += 915 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO); 916 stats->rx65to127octets_gb += 917 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32); 918 919 stats->rx128to255octets_gb += 920 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO); 921 stats->rx128to255octets_gb += 922 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32); 923 924 stats->rx256to511octets_gb += 925 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO); 926 stats->rx256to511octets_gb += 927 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32); 928 929 stats->rx512to1023octets_gb += 930 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO); 931 stats->rx512to1023octets_gb += 932 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32); 933 934 stats->rx1024tomaxoctets_gb += 935 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 936 stats->rx1024tomaxoctets_gb += 937 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32); 938 939 stats->rxunicastframes_g += 940 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO); 941 stats->rxunicastframes_g += 942 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32); 943 944 stats->rxlengtherror += 945 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO); 946 stats->rxlengtherror += 947 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32); 948 949 stats->rxoutofrangetype += 950 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO); 951 stats->rxoutofrangetype += 952 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32); 953 954 stats->rxpauseframes += 955 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO); 956 stats->rxpauseframes += 957 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32); 958 959 stats->rxfifooverflow += 960 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO); 961 stats->rxfifooverflow += 962 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32); 963 964 stats->rxvlanframes_gb += 965 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO); 966 stats->rxvlanframes_gb += 967 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32); 968 969 stats->rxwatchdogerror += 970 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR); 971 972 /* Un-freeze counters */ 973 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 974 } 975 976 static int 977 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 978 unsigned int n) 979 { 980 struct axgbe_port *pdata = dev->data->dev_private; 981 unsigned int i; 982 983 if (!stats) 984 return 0; 985 986 axgbe_read_mmc_stats(pdata); 987 988 for (i = 0; i < n && i < AXGBE_XSTATS_COUNT; i++) { 989 stats[i].id = i; 990 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats + 991 axgbe_xstats_strings[i].offset); 992 } 993 994 return i; 995 } 996 997 static int 998 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 999 struct rte_eth_xstat_name *xstats_names, 1000 unsigned int n) 1001 { 1002 unsigned int i; 1003 1004 if (n >= AXGBE_XSTATS_COUNT && xstats_names) { 1005 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) { 1006 snprintf(xstats_names[i].name, 1007 RTE_ETH_XSTATS_NAME_SIZE, "%s", 1008 axgbe_xstats_strings[i].name); 1009 } 1010 } 1011 1012 return AXGBE_XSTATS_COUNT; 1013 } 1014 1015 static int 1016 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1017 uint64_t *values, unsigned int n) 1018 { 1019 unsigned int i; 1020 uint64_t values_copy[AXGBE_XSTATS_COUNT]; 1021 1022 if (!ids) { 1023 struct axgbe_port *pdata = dev->data->dev_private; 1024 1025 if (n < AXGBE_XSTATS_COUNT) 1026 return AXGBE_XSTATS_COUNT; 1027 1028 axgbe_read_mmc_stats(pdata); 1029 1030 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1031 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1032 axgbe_xstats_strings[i].offset); 1033 } 1034 1035 return i; 1036 } 1037 1038 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT); 1039 1040 for (i = 0; i < n; i++) { 1041 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1042 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 1043 return -1; 1044 } 1045 values[i] = values_copy[ids[i]]; 1046 } 1047 return n; 1048 } 1049 1050 static int 1051 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 1052 struct rte_eth_xstat_name *xstats_names, 1053 const uint64_t *ids, 1054 unsigned int size) 1055 { 1056 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT]; 1057 unsigned int i; 1058 1059 if (!ids) 1060 return axgbe_dev_xstats_get_names(dev, xstats_names, size); 1061 1062 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size); 1063 1064 for (i = 0; i < size; i++) { 1065 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1066 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 1067 return -1; 1068 } 1069 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1070 } 1071 return size; 1072 } 1073 1074 static int 1075 axgbe_dev_xstats_reset(struct rte_eth_dev *dev) 1076 { 1077 struct axgbe_port *pdata = dev->data->dev_private; 1078 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 1079 1080 /* MMC registers are configured for reset on read */ 1081 axgbe_read_mmc_stats(pdata); 1082 1083 /* Reset stats */ 1084 memset(stats, 0, sizeof(*stats)); 1085 1086 return 0; 1087 } 1088 1089 static int 1090 axgbe_dev_stats_get(struct rte_eth_dev *dev, 1091 struct rte_eth_stats *stats) 1092 { 1093 struct axgbe_rx_queue *rxq; 1094 struct axgbe_tx_queue *txq; 1095 struct axgbe_port *pdata = dev->data->dev_private; 1096 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats; 1097 unsigned int i; 1098 1099 axgbe_read_mmc_stats(pdata); 1100 1101 stats->imissed = mmc_stats->rxfifooverflow; 1102 1103 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1104 rxq = dev->data->rx_queues[i]; 1105 stats->q_ipackets[i] = rxq->pkts; 1106 stats->ipackets += rxq->pkts; 1107 stats->q_ibytes[i] = rxq->bytes; 1108 stats->ibytes += rxq->bytes; 1109 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed; 1110 stats->q_errors[i] = rxq->errors + rxq->rx_mbuf_alloc_failed; 1111 stats->ierrors += rxq->errors; 1112 } 1113 1114 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1115 txq = dev->data->tx_queues[i]; 1116 stats->q_opackets[i] = txq->pkts; 1117 stats->opackets += txq->pkts; 1118 stats->q_obytes[i] = txq->bytes; 1119 stats->obytes += txq->bytes; 1120 stats->oerrors += txq->errors; 1121 } 1122 1123 return 0; 1124 } 1125 1126 static int 1127 axgbe_dev_stats_reset(struct rte_eth_dev *dev) 1128 { 1129 struct axgbe_rx_queue *rxq; 1130 struct axgbe_tx_queue *txq; 1131 unsigned int i; 1132 1133 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1134 rxq = dev->data->rx_queues[i]; 1135 rxq->pkts = 0; 1136 rxq->bytes = 0; 1137 rxq->errors = 0; 1138 rxq->rx_mbuf_alloc_failed = 0; 1139 } 1140 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1141 txq = dev->data->tx_queues[i]; 1142 txq->pkts = 0; 1143 txq->bytes = 0; 1144 txq->errors = 0; 1145 } 1146 1147 return 0; 1148 } 1149 1150 static int 1151 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1152 { 1153 struct axgbe_port *pdata = dev->data->dev_private; 1154 1155 dev_info->max_rx_queues = pdata->rx_ring_count; 1156 dev_info->max_tx_queues = pdata->tx_ring_count; 1157 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE; 1158 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE; 1159 dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1; 1160 dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size; 1161 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1162 1163 dev_info->rx_offload_capa = 1164 DEV_RX_OFFLOAD_IPV4_CKSUM | 1165 DEV_RX_OFFLOAD_UDP_CKSUM | 1166 DEV_RX_OFFLOAD_TCP_CKSUM | 1167 DEV_RX_OFFLOAD_JUMBO_FRAME | 1168 DEV_RX_OFFLOAD_SCATTER | 1169 DEV_RX_OFFLOAD_KEEP_CRC; 1170 1171 dev_info->tx_offload_capa = 1172 DEV_TX_OFFLOAD_IPV4_CKSUM | 1173 DEV_TX_OFFLOAD_UDP_CKSUM | 1174 DEV_TX_OFFLOAD_TCP_CKSUM; 1175 1176 if (pdata->hw_feat.rss) { 1177 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD; 1178 dev_info->reta_size = pdata->hw_feat.hash_table_size; 1179 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE; 1180 } 1181 1182 dev_info->rx_desc_lim = rx_desc_lim; 1183 dev_info->tx_desc_lim = tx_desc_lim; 1184 1185 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1186 .rx_free_thresh = AXGBE_RX_FREE_THRESH, 1187 }; 1188 1189 dev_info->default_txconf = (struct rte_eth_txconf) { 1190 .tx_free_thresh = AXGBE_TX_FREE_THRESH, 1191 }; 1192 1193 return 0; 1194 } 1195 1196 static int 1197 axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1198 { 1199 struct axgbe_port *pdata = dev->data->dev_private; 1200 struct xgbe_fc_info fc = pdata->fc; 1201 unsigned int reg, reg_val = 0; 1202 1203 reg = MAC_Q0TFCR; 1204 reg_val = AXGMAC_IOREAD(pdata, reg); 1205 fc.low_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA); 1206 fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD); 1207 fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT); 1208 fc.autoneg = pdata->pause_autoneg; 1209 1210 if (pdata->rx_pause && pdata->tx_pause) 1211 fc.mode = RTE_FC_FULL; 1212 else if (pdata->rx_pause) 1213 fc.mode = RTE_FC_RX_PAUSE; 1214 else if (pdata->tx_pause) 1215 fc.mode = RTE_FC_TX_PAUSE; 1216 else 1217 fc.mode = RTE_FC_NONE; 1218 1219 fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024; 1220 fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024; 1221 fc_conf->pause_time = fc.pause_time[0]; 1222 fc_conf->send_xon = fc.send_xon; 1223 fc_conf->mode = fc.mode; 1224 1225 return 0; 1226 } 1227 1228 static int 1229 axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1230 { 1231 struct axgbe_port *pdata = dev->data->dev_private; 1232 struct xgbe_fc_info fc = pdata->fc; 1233 unsigned int reg, reg_val = 0; 1234 reg = MAC_Q0TFCR; 1235 1236 pdata->pause_autoneg = fc_conf->autoneg; 1237 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1238 fc.send_xon = fc_conf->send_xon; 1239 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA, 1240 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water)); 1241 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD, 1242 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water)); 1243 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time); 1244 AXGMAC_IOWRITE(pdata, reg, reg_val); 1245 fc.mode = fc_conf->mode; 1246 1247 if (fc.mode == RTE_FC_FULL) { 1248 pdata->tx_pause = 1; 1249 pdata->rx_pause = 1; 1250 } else if (fc.mode == RTE_FC_RX_PAUSE) { 1251 pdata->tx_pause = 0; 1252 pdata->rx_pause = 1; 1253 } else if (fc.mode == RTE_FC_TX_PAUSE) { 1254 pdata->tx_pause = 1; 1255 pdata->rx_pause = 0; 1256 } else { 1257 pdata->tx_pause = 0; 1258 pdata->rx_pause = 0; 1259 } 1260 1261 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1262 pdata->hw_if.config_tx_flow_control(pdata); 1263 1264 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1265 pdata->hw_if.config_rx_flow_control(pdata); 1266 1267 pdata->hw_if.config_flow_control(pdata); 1268 pdata->phy.tx_pause = pdata->tx_pause; 1269 pdata->phy.rx_pause = pdata->rx_pause; 1270 1271 return 0; 1272 } 1273 1274 static int 1275 axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 1276 struct rte_eth_pfc_conf *pfc_conf) 1277 { 1278 struct axgbe_port *pdata = dev->data->dev_private; 1279 struct xgbe_fc_info fc = pdata->fc; 1280 uint8_t tc_num; 1281 1282 tc_num = pdata->pfc_map[pfc_conf->priority]; 1283 1284 if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) { 1285 PMD_INIT_LOG(ERR, "Max supported traffic class: %d\n", 1286 pdata->hw_feat.tc_cnt); 1287 return -EINVAL; 1288 } 1289 1290 pdata->pause_autoneg = pfc_conf->fc.autoneg; 1291 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1292 fc.send_xon = pfc_conf->fc.send_xon; 1293 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA, 1294 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water)); 1295 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD, 1296 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water)); 1297 1298 switch (tc_num) { 1299 case 0: 1300 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1301 PSTC0, pfc_conf->fc.pause_time); 1302 break; 1303 case 1: 1304 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1305 PSTC1, pfc_conf->fc.pause_time); 1306 break; 1307 case 2: 1308 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1309 PSTC2, pfc_conf->fc.pause_time); 1310 break; 1311 case 3: 1312 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1313 PSTC3, pfc_conf->fc.pause_time); 1314 break; 1315 case 4: 1316 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1317 PSTC4, pfc_conf->fc.pause_time); 1318 break; 1319 case 5: 1320 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1321 PSTC5, pfc_conf->fc.pause_time); 1322 break; 1323 case 7: 1324 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1325 PSTC6, pfc_conf->fc.pause_time); 1326 break; 1327 case 6: 1328 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1329 PSTC7, pfc_conf->fc.pause_time); 1330 break; 1331 } 1332 1333 fc.mode = pfc_conf->fc.mode; 1334 1335 if (fc.mode == RTE_FC_FULL) { 1336 pdata->tx_pause = 1; 1337 pdata->rx_pause = 1; 1338 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1339 } else if (fc.mode == RTE_FC_RX_PAUSE) { 1340 pdata->tx_pause = 0; 1341 pdata->rx_pause = 1; 1342 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1343 } else if (fc.mode == RTE_FC_TX_PAUSE) { 1344 pdata->tx_pause = 1; 1345 pdata->rx_pause = 0; 1346 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1347 } else { 1348 pdata->tx_pause = 0; 1349 pdata->rx_pause = 0; 1350 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1351 } 1352 1353 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1354 pdata->hw_if.config_tx_flow_control(pdata); 1355 1356 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1357 pdata->hw_if.config_rx_flow_control(pdata); 1358 pdata->hw_if.config_flow_control(pdata); 1359 pdata->phy.tx_pause = pdata->tx_pause; 1360 pdata->phy.rx_pause = pdata->rx_pause; 1361 1362 return 0; 1363 } 1364 1365 void 1366 axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1367 struct rte_eth_rxq_info *qinfo) 1368 { 1369 struct axgbe_rx_queue *rxq; 1370 1371 rxq = dev->data->rx_queues[queue_id]; 1372 qinfo->mp = rxq->mb_pool; 1373 qinfo->scattered_rx = dev->data->scattered_rx; 1374 qinfo->nb_desc = rxq->nb_desc; 1375 qinfo->conf.rx_free_thresh = rxq->free_thresh; 1376 } 1377 1378 void 1379 axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1380 struct rte_eth_txq_info *qinfo) 1381 { 1382 struct axgbe_tx_queue *txq; 1383 1384 txq = dev->data->tx_queues[queue_id]; 1385 qinfo->nb_desc = txq->nb_desc; 1386 qinfo->conf.tx_free_thresh = txq->free_thresh; 1387 } 1388 const uint32_t * 1389 axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1390 { 1391 static const uint32_t ptypes[] = { 1392 RTE_PTYPE_L2_ETHER, 1393 RTE_PTYPE_L2_ETHER_TIMESYNC, 1394 RTE_PTYPE_L2_ETHER_LLDP, 1395 RTE_PTYPE_L2_ETHER_ARP, 1396 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1397 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 1398 RTE_PTYPE_L4_FRAG, 1399 RTE_PTYPE_L4_ICMP, 1400 RTE_PTYPE_L4_NONFRAG, 1401 RTE_PTYPE_L4_SCTP, 1402 RTE_PTYPE_L4_TCP, 1403 RTE_PTYPE_L4_UDP, 1404 RTE_PTYPE_TUNNEL_GRENAT, 1405 RTE_PTYPE_TUNNEL_IP, 1406 RTE_PTYPE_INNER_L2_ETHER, 1407 RTE_PTYPE_INNER_L2_ETHER_VLAN, 1408 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 1409 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 1410 RTE_PTYPE_INNER_L4_FRAG, 1411 RTE_PTYPE_INNER_L4_ICMP, 1412 RTE_PTYPE_INNER_L4_NONFRAG, 1413 RTE_PTYPE_INNER_L4_SCTP, 1414 RTE_PTYPE_INNER_L4_TCP, 1415 RTE_PTYPE_INNER_L4_UDP, 1416 RTE_PTYPE_UNKNOWN 1417 }; 1418 1419 if (dev->rx_pkt_burst == axgbe_recv_pkts) 1420 return ptypes; 1421 return NULL; 1422 } 1423 1424 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1425 { 1426 struct rte_eth_dev_info dev_info; 1427 struct axgbe_port *pdata = dev->data->dev_private; 1428 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 1429 unsigned int val = 0; 1430 axgbe_dev_info_get(dev, &dev_info); 1431 /* check that mtu is within the allowed range */ 1432 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 1433 return -EINVAL; 1434 /* mtu setting is forbidden if port is start */ 1435 if (dev->data->dev_started) { 1436 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", 1437 dev->data->port_id); 1438 return -EBUSY; 1439 } 1440 if (frame_size > RTE_ETHER_MAX_LEN) { 1441 dev->data->dev_conf.rxmode.offloads |= 1442 DEV_RX_OFFLOAD_JUMBO_FRAME; 1443 val = 1; 1444 } else { 1445 dev->data->dev_conf.rxmode.offloads &= 1446 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1447 val = 0; 1448 } 1449 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 1450 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1451 return 0; 1452 } 1453 1454 static void 1455 axgbe_update_tstamp_time(struct axgbe_port *pdata, 1456 unsigned int sec, unsigned int nsec, int addsub) 1457 { 1458 unsigned int count = 100; 1459 uint32_t sub_val = 0; 1460 uint32_t sub_val_sec = 0xFFFFFFFF; 1461 uint32_t sub_val_nsec = 0x3B9ACA00; 1462 1463 if (addsub) { 1464 if (sec) 1465 sub_val = sub_val_sec - (sec - 1); 1466 else 1467 sub_val = sec; 1468 1469 AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val); 1470 sub_val = sub_val_nsec - nsec; 1471 AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val); 1472 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1); 1473 } else { 1474 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1475 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0); 1476 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1477 } 1478 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1479 /* Wait for time update to complete */ 1480 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1481 rte_delay_ms(1); 1482 } 1483 1484 static inline uint64_t 1485 div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) 1486 { 1487 *remainder = dividend % divisor; 1488 return dividend / divisor; 1489 } 1490 1491 static inline uint64_t 1492 div_u64(uint64_t dividend, uint32_t divisor) 1493 { 1494 uint32_t remainder; 1495 return div_u64_rem(dividend, divisor, &remainder); 1496 } 1497 1498 static int 1499 axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta) 1500 { 1501 uint64_t adjust; 1502 uint32_t addend, diff; 1503 unsigned int neg_adjust = 0; 1504 1505 if (delta < 0) { 1506 neg_adjust = 1; 1507 delta = -delta; 1508 } 1509 adjust = (uint64_t)pdata->tstamp_addend; 1510 adjust *= delta; 1511 diff = (uint32_t)div_u64(adjust, 1000000000UL); 1512 addend = (neg_adjust) ? pdata->tstamp_addend - diff : 1513 pdata->tstamp_addend + diff; 1514 pdata->tstamp_addend = addend; 1515 axgbe_update_tstamp_addend(pdata, addend); 1516 return 0; 1517 } 1518 1519 static int 1520 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 1521 { 1522 struct axgbe_port *pdata = dev->data->dev_private; 1523 struct timespec timestamp_delta; 1524 1525 axgbe_adjfreq(pdata, delta); 1526 pdata->systime_tc.nsec += delta; 1527 1528 if (delta < 0) { 1529 delta = -delta; 1530 timestamp_delta = rte_ns_to_timespec(delta); 1531 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1532 timestamp_delta.tv_nsec, 1); 1533 } else { 1534 timestamp_delta = rte_ns_to_timespec(delta); 1535 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1536 timestamp_delta.tv_nsec, 0); 1537 } 1538 return 0; 1539 } 1540 1541 static int 1542 axgbe_timesync_read_time(struct rte_eth_dev *dev, 1543 struct timespec *timestamp) 1544 { 1545 uint64_t nsec; 1546 struct axgbe_port *pdata = dev->data->dev_private; 1547 1548 nsec = AXGMAC_IOREAD(pdata, MAC_STSR); 1549 nsec *= NSEC_PER_SEC; 1550 nsec += AXGMAC_IOREAD(pdata, MAC_STNR); 1551 *timestamp = rte_ns_to_timespec(nsec); 1552 return 0; 1553 } 1554 static int 1555 axgbe_timesync_write_time(struct rte_eth_dev *dev, 1556 const struct timespec *timestamp) 1557 { 1558 unsigned int count = 100; 1559 struct axgbe_port *pdata = dev->data->dev_private; 1560 1561 AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec); 1562 AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec); 1563 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1564 /* Wait for time update to complete */ 1565 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1566 rte_delay_ms(1); 1567 if (!count) 1568 PMD_DRV_LOG(ERR, "Timed out update timestamp\n"); 1569 return 0; 1570 } 1571 1572 static void 1573 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 1574 uint32_t addend) 1575 { 1576 unsigned int count = 100; 1577 1578 AXGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1579 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1580 1581 /* Wait for addend update to complete */ 1582 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1583 rte_delay_ms(1); 1584 if (!count) 1585 PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n"); 1586 } 1587 1588 static void 1589 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 1590 unsigned int nsec) 1591 { 1592 unsigned int count = 100; 1593 1594 /*System Time Sec Update*/ 1595 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1596 /*System Time nanoSec Update*/ 1597 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1598 /*Initialize Timestamp*/ 1599 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1600 1601 /* Wait for time update to complete */ 1602 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1603 rte_delay_ms(1); 1604 if (!count) 1605 PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n"); 1606 } 1607 1608 static int 1609 axgbe_timesync_enable(struct rte_eth_dev *dev) 1610 { 1611 struct axgbe_port *pdata = dev->data->dev_private; 1612 unsigned int mac_tscr = 0; 1613 uint64_t dividend; 1614 struct timespec timestamp; 1615 uint64_t nsec; 1616 1617 /* Set one nano-second accuracy */ 1618 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1619 1620 /* Set fine timestamp update */ 1621 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1622 1623 /* Overwrite earlier timestamps */ 1624 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1625 1626 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1627 1628 /* Enabling processing of ptp over eth pkt */ 1629 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1630 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1631 /* Enable timestamp for all pkts*/ 1632 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 1633 1634 /* enabling timestamp */ 1635 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1636 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1637 1638 /* Exit if timestamping is not enabled */ 1639 if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) { 1640 PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n"); 1641 return 0; 1642 } 1643 1644 /* Sub-second Increment Value*/ 1645 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC); 1646 /* Sub-nanosecond Increment Value */ 1647 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC); 1648 1649 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 1650 dividend = 50000000; 1651 dividend <<= 32; 1652 pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate); 1653 1654 axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1655 axgbe_set_tstamp_time(pdata, 0, 0); 1656 1657 /* Initialize the timecounter */ 1658 memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter)); 1659 1660 pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK; 1661 pdata->systime_tc.cc_shift = 0; 1662 pdata->systime_tc.nsec_mask = 0; 1663 1664 PMD_DRV_LOG(DEBUG, "Initializing system time counter with realtime\n"); 1665 1666 /* Updating the counter once with clock real time */ 1667 clock_gettime(CLOCK_REALTIME, ×tamp); 1668 nsec = rte_timespec_to_ns(×tamp); 1669 nsec = rte_timecounter_update(&pdata->systime_tc, nsec); 1670 axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec); 1671 return 0; 1672 } 1673 1674 static int 1675 axgbe_timesync_disable(struct rte_eth_dev *dev) 1676 { 1677 struct axgbe_port *pdata = dev->data->dev_private; 1678 unsigned int mac_tscr = 0; 1679 1680 /*disable timestamp for all pkts*/ 1681 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0); 1682 /*disable the addened register*/ 1683 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0); 1684 /* disable timestamp update */ 1685 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0); 1686 /*disable time stamp*/ 1687 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0); 1688 return 0; 1689 } 1690 1691 static int 1692 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 1693 struct timespec *timestamp, uint32_t flags) 1694 { 1695 uint64_t nsec = 0; 1696 volatile union axgbe_rx_desc *desc; 1697 uint16_t idx, pmt; 1698 struct axgbe_rx_queue *rxq = *dev->data->rx_queues; 1699 1700 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 1701 desc = &rxq->desc[idx]; 1702 1703 while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 1704 rte_delay_ms(1); 1705 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) { 1706 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) && 1707 !AXGMAC_GET_BITS_LE(desc->write.desc3, 1708 RX_CONTEXT_DESC3, TSD)) { 1709 pmt = AXGMAC_GET_BITS_LE(desc->write.desc3, 1710 RX_CONTEXT_DESC3, PMT); 1711 nsec = rte_le_to_cpu_32(desc->write.desc1); 1712 nsec *= NSEC_PER_SEC; 1713 nsec += rte_le_to_cpu_32(desc->write.desc0); 1714 if (nsec != 0xffffffffffffffffULL) { 1715 if (pmt == 0x01) 1716 *timestamp = rte_ns_to_timespec(nsec); 1717 PMD_DRV_LOG(DEBUG, 1718 "flags = 0x%x nsec = %"PRIu64"\n", 1719 flags, nsec); 1720 } 1721 } 1722 } 1723 1724 return 0; 1725 } 1726 1727 static int 1728 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 1729 struct timespec *timestamp) 1730 { 1731 uint64_t nsec; 1732 struct axgbe_port *pdata = dev->data->dev_private; 1733 unsigned int tx_snr, tx_ssr; 1734 1735 rte_delay_us(5); 1736 if (pdata->vdata->tx_tstamp_workaround) { 1737 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1738 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1739 1740 } else { 1741 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1742 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1743 } 1744 if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) { 1745 PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n"); 1746 return 0; 1747 } 1748 nsec = tx_ssr; 1749 nsec *= NSEC_PER_SEC; 1750 nsec += tx_snr; 1751 PMD_DRV_LOG(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d\n", 1752 nsec, tx_ssr, tx_snr); 1753 *timestamp = rte_ns_to_timespec(nsec); 1754 return 0; 1755 } 1756 1757 static void axgbe_get_all_hw_features(struct axgbe_port *pdata) 1758 { 1759 unsigned int mac_hfr0, mac_hfr1, mac_hfr2; 1760 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 1761 1762 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R); 1763 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R); 1764 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R); 1765 1766 memset(hw_feat, 0, sizeof(*hw_feat)); 1767 1768 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR); 1769 1770 /* Hardware feature register 0 */ 1771 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 1772 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 1773 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 1774 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 1775 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 1776 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 1777 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 1778 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 1779 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 1780 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 1781 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 1782 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 1783 ADDMACADRSEL); 1784 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 1785 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 1786 1787 /* Hardware feature register 1 */ 1788 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1789 RXFIFOSIZE); 1790 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1791 TXFIFOSIZE); 1792 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1, 1793 MAC_HWF1R, ADVTHWORD); 1794 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 1795 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 1796 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 1797 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 1798 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 1799 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 1800 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 1801 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1802 HASHTBLSZ); 1803 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1804 L3L4FNUM); 1805 1806 /* Hardware feature register 2 */ 1807 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 1808 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 1809 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 1810 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 1811 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 1812 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, 1813 AUXSNAPNUM); 1814 1815 /* Translate the Hash Table size into actual number */ 1816 switch (hw_feat->hash_table_size) { 1817 case 0: 1818 break; 1819 case 1: 1820 hw_feat->hash_table_size = 64; 1821 break; 1822 case 2: 1823 hw_feat->hash_table_size = 128; 1824 break; 1825 case 3: 1826 hw_feat->hash_table_size = 256; 1827 break; 1828 } 1829 1830 /* Translate the address width setting into actual number */ 1831 switch (hw_feat->dma_width) { 1832 case 0: 1833 hw_feat->dma_width = 32; 1834 break; 1835 case 1: 1836 hw_feat->dma_width = 40; 1837 break; 1838 case 2: 1839 hw_feat->dma_width = 48; 1840 break; 1841 default: 1842 hw_feat->dma_width = 32; 1843 } 1844 1845 /* The Queue, Channel and TC counts are zero based so increment them 1846 * to get the actual number 1847 */ 1848 hw_feat->rx_q_cnt++; 1849 hw_feat->tx_q_cnt++; 1850 hw_feat->rx_ch_cnt++; 1851 hw_feat->tx_ch_cnt++; 1852 hw_feat->tc_cnt++; 1853 1854 /* Translate the fifo sizes into actual numbers */ 1855 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 1856 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 1857 } 1858 1859 static void axgbe_init_all_fptrs(struct axgbe_port *pdata) 1860 { 1861 axgbe_init_function_ptrs_dev(&pdata->hw_if); 1862 axgbe_init_function_ptrs_phy(&pdata->phy_if); 1863 axgbe_init_function_ptrs_i2c(&pdata->i2c_if); 1864 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 1865 } 1866 1867 static void axgbe_set_counts(struct axgbe_port *pdata) 1868 { 1869 /* Set all the function pointers */ 1870 axgbe_init_all_fptrs(pdata); 1871 1872 /* Populate the hardware features */ 1873 axgbe_get_all_hw_features(pdata); 1874 1875 /* Set default max values if not provided */ 1876 if (!pdata->tx_max_channel_count) 1877 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 1878 if (!pdata->rx_max_channel_count) 1879 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 1880 1881 if (!pdata->tx_max_q_count) 1882 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 1883 if (!pdata->rx_max_q_count) 1884 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 1885 1886 /* Calculate the number of Tx and Rx rings to be created 1887 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 1888 * the number of Tx queues to the number of Tx channels 1889 * enabled 1890 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 1891 * number of Rx queues or maximum allowed 1892 */ 1893 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt, 1894 pdata->tx_max_channel_count); 1895 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count, 1896 pdata->tx_max_q_count); 1897 1898 pdata->tx_q_count = pdata->tx_ring_count; 1899 1900 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt, 1901 pdata->rx_max_channel_count); 1902 1903 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt, 1904 pdata->rx_max_q_count); 1905 } 1906 1907 static void axgbe_default_config(struct axgbe_port *pdata) 1908 { 1909 pdata->pblx8 = DMA_PBL_X8_ENABLE; 1910 pdata->tx_sf_mode = MTL_TSF_ENABLE; 1911 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 1912 pdata->tx_pbl = DMA_PBL_32; 1913 pdata->tx_osp_mode = DMA_OSP_ENABLE; 1914 pdata->rx_sf_mode = MTL_RSF_ENABLE; 1915 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 1916 pdata->rx_pbl = DMA_PBL_32; 1917 pdata->pause_autoneg = 1; 1918 pdata->tx_pause = 0; 1919 pdata->rx_pause = 0; 1920 pdata->phy_speed = SPEED_UNKNOWN; 1921 pdata->power_down = 0; 1922 } 1923 1924 static int 1925 pci_device_cmp(const struct rte_device *dev, const void *_pci_id) 1926 { 1927 const struct rte_pci_device *pdev = RTE_DEV_TO_PCI_CONST(dev); 1928 const struct rte_pci_id *pcid = _pci_id; 1929 1930 if (pdev->id.vendor_id == AMD_PCI_VENDOR_ID && 1931 pdev->id.device_id == pcid->device_id) 1932 return 0; 1933 return 1; 1934 } 1935 1936 static bool 1937 pci_search_device(int device_id) 1938 { 1939 struct rte_bus *pci_bus; 1940 struct rte_pci_id dev_id; 1941 1942 dev_id.device_id = device_id; 1943 pci_bus = rte_bus_find_by_name("pci"); 1944 return (pci_bus != NULL) && 1945 (pci_bus->find_device(NULL, pci_device_cmp, &dev_id) != NULL); 1946 } 1947 1948 /* 1949 * It returns 0 on success. 1950 */ 1951 static int 1952 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) 1953 { 1954 PMD_INIT_FUNC_TRACE(); 1955 struct axgbe_port *pdata; 1956 struct rte_pci_device *pci_dev; 1957 uint32_t reg, mac_lo, mac_hi; 1958 uint32_t len; 1959 int ret; 1960 1961 eth_dev->dev_ops = &axgbe_eth_dev_ops; 1962 1963 eth_dev->rx_descriptor_status = axgbe_dev_rx_descriptor_status; 1964 eth_dev->tx_descriptor_status = axgbe_dev_tx_descriptor_status; 1965 1966 /* 1967 * For secondary processes, we don't initialise any further as primary 1968 * has already done this work. 1969 */ 1970 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1971 return 0; 1972 1973 pdata = eth_dev->data->dev_private; 1974 /* initial state */ 1975 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 1976 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 1977 pdata->eth_dev = eth_dev; 1978 1979 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 1980 pdata->pci_dev = pci_dev; 1981 1982 /* 1983 * Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE 1984 */ 1985 if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) { 1986 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; 1987 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; 1988 } else { 1989 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 1990 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 1991 } 1992 1993 pdata->xgmac_regs = 1994 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; 1995 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs 1996 + AXGBE_MAC_PROP_OFFSET); 1997 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs 1998 + AXGBE_I2C_CTRL_OFFSET); 1999 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; 2000 2001 /* version specific driver data*/ 2002 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A) 2003 pdata->vdata = &axgbe_v2a; 2004 else 2005 pdata->vdata = &axgbe_v2b; 2006 2007 /* Configure the PCS indirect addressing support */ 2008 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); 2009 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 2010 pdata->xpcs_window <<= 6; 2011 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 2012 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 2013 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 2014 2015 PMD_INIT_LOG(DEBUG, 2016 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, 2017 pdata->xpcs_window_size, pdata->xpcs_window_mask); 2018 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 2019 2020 /* Retrieve the MAC address */ 2021 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 2022 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 2023 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff; 2024 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff; 2025 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff; 2026 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff; 2027 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff; 2028 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff; 2029 2030 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_MAC_ADDRS; 2031 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", len, 0); 2032 2033 if (!eth_dev->data->mac_addrs) { 2034 PMD_INIT_LOG(ERR, 2035 "Failed to alloc %u bytes needed to " 2036 "store MAC addresses", len); 2037 return -ENOMEM; 2038 } 2039 2040 /* Allocate memory for storing hash filter MAC addresses */ 2041 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS; 2042 eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr", 2043 len, 0); 2044 2045 if (eth_dev->data->hash_mac_addrs == NULL) { 2046 PMD_INIT_LOG(ERR, 2047 "Failed to allocate %d bytes needed to " 2048 "store MAC addresses", len); 2049 return -ENOMEM; 2050 } 2051 2052 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr)) 2053 rte_eth_random_addr(pdata->mac_addr.addr_bytes); 2054 2055 /* Copy the permanent MAC address */ 2056 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]); 2057 2058 /* Clock settings */ 2059 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ; 2060 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 2061 2062 /* Set the DMA coherency values */ 2063 pdata->coherent = 1; 2064 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN; 2065 pdata->arcache = AXGBE_DMA_OS_ARCACHE; 2066 pdata->awcache = AXGBE_DMA_OS_AWCACHE; 2067 2068 /* Set the maximum channels and queues */ 2069 reg = XP_IOREAD(pdata, XP_PROP_1); 2070 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA); 2071 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA); 2072 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES); 2073 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES); 2074 2075 /* Set the hardware channel and queue counts */ 2076 axgbe_set_counts(pdata); 2077 2078 /* Set the maximum fifo amounts */ 2079 reg = XP_IOREAD(pdata, XP_PROP_2); 2080 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE); 2081 pdata->tx_max_fifo_size *= 16384; 2082 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size, 2083 pdata->vdata->tx_max_fifo_size); 2084 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE); 2085 pdata->rx_max_fifo_size *= 16384; 2086 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size, 2087 pdata->vdata->rx_max_fifo_size); 2088 /* Issue software reset to DMA */ 2089 ret = pdata->hw_if.exit(pdata); 2090 if (ret) 2091 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n"); 2092 2093 /* Set default configuration data */ 2094 axgbe_default_config(pdata); 2095 2096 /* Set default max values if not provided */ 2097 if (!pdata->tx_max_fifo_size) 2098 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 2099 if (!pdata->rx_max_fifo_size) 2100 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 2101 2102 pdata->tx_desc_count = AXGBE_MAX_RING_DESC; 2103 pdata->rx_desc_count = AXGBE_MAX_RING_DESC; 2104 pthread_mutex_init(&pdata->xpcs_mutex, NULL); 2105 pthread_mutex_init(&pdata->i2c_mutex, NULL); 2106 pthread_mutex_init(&pdata->an_mutex, NULL); 2107 pthread_mutex_init(&pdata->phy_mutex, NULL); 2108 2109 ret = pdata->phy_if.phy_init(pdata); 2110 if (ret) { 2111 rte_free(eth_dev->data->mac_addrs); 2112 eth_dev->data->mac_addrs = NULL; 2113 return ret; 2114 } 2115 2116 rte_intr_callback_register(&pci_dev->intr_handle, 2117 axgbe_dev_interrupt_handler, 2118 (void *)eth_dev); 2119 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 2120 eth_dev->data->port_id, pci_dev->id.vendor_id, 2121 pci_dev->id.device_id); 2122 2123 return 0; 2124 } 2125 2126 static int 2127 axgbe_dev_close(struct rte_eth_dev *eth_dev) 2128 { 2129 struct rte_pci_device *pci_dev; 2130 2131 PMD_INIT_FUNC_TRACE(); 2132 2133 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2134 return 0; 2135 2136 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2137 eth_dev->dev_ops = NULL; 2138 eth_dev->rx_pkt_burst = NULL; 2139 eth_dev->tx_pkt_burst = NULL; 2140 axgbe_dev_clear_queues(eth_dev); 2141 2142 /* disable uio intr before callback unregister */ 2143 rte_intr_disable(&pci_dev->intr_handle); 2144 rte_intr_callback_unregister(&pci_dev->intr_handle, 2145 axgbe_dev_interrupt_handler, 2146 (void *)eth_dev); 2147 2148 return 0; 2149 } 2150 2151 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2152 struct rte_pci_device *pci_dev) 2153 { 2154 return rte_eth_dev_pci_generic_probe(pci_dev, 2155 sizeof(struct axgbe_port), eth_axgbe_dev_init); 2156 } 2157 2158 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev) 2159 { 2160 return rte_eth_dev_pci_generic_remove(pci_dev, axgbe_dev_close); 2161 } 2162 2163 static struct rte_pci_driver rte_axgbe_pmd = { 2164 .id_table = pci_id_axgbe_map, 2165 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2166 .probe = eth_axgbe_pci_probe, 2167 .remove = eth_axgbe_pci_remove, 2168 }; 2169 2170 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd); 2171 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map); 2172 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 2173 RTE_LOG_REGISTER(axgbe_logtype_init, pmd.net.axgbe.init, NOTICE); 2174 RTE_LOG_REGISTER(axgbe_logtype_driver, pmd.net.axgbe.driver, NOTICE); 2175