1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_rxtx.h" 7 #include "axgbe_ethdev.h" 8 #include "axgbe_common.h" 9 #include "axgbe_phy.h" 10 #include "axgbe_regs.h" 11 #include "rte_time.h" 12 13 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); 14 static int axgbe_dev_configure(struct rte_eth_dev *dev); 15 static int axgbe_dev_start(struct rte_eth_dev *dev); 16 static int axgbe_dev_stop(struct rte_eth_dev *dev); 17 static void axgbe_dev_interrupt_handler(void *param); 18 static int axgbe_dev_close(struct rte_eth_dev *dev); 19 static int axgbe_dev_reset(struct rte_eth_dev *dev); 20 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 21 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 22 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 23 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 24 static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, 25 struct rte_ether_addr *mac_addr); 26 static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, 27 struct rte_ether_addr *mac_addr, 28 uint32_t index, 29 uint32_t vmdq); 30 static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 31 static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 32 struct rte_ether_addr *mc_addr_set, 33 uint32_t nb_mc_addr); 34 static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 35 struct rte_ether_addr *mac_addr, 36 uint8_t add); 37 static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, 38 uint8_t add); 39 static int axgbe_dev_link_update(struct rte_eth_dev *dev, 40 int wait_to_complete); 41 static int axgbe_dev_get_regs(struct rte_eth_dev *dev, 42 struct rte_dev_reg_info *regs); 43 static int axgbe_dev_stats_get(struct rte_eth_dev *dev, 44 struct rte_eth_stats *stats); 45 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev); 46 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev, 47 struct rte_eth_xstat *stats, 48 unsigned int n); 49 static int 50 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 51 struct rte_eth_xstat_name *xstats_names, 52 unsigned int size); 53 static int 54 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 55 const uint64_t *ids, 56 uint64_t *values, 57 unsigned int n); 58 static int 59 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 60 const uint64_t *ids, 61 struct rte_eth_xstat_name *xstats_names, 62 unsigned int size); 63 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev); 64 static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 65 struct rte_eth_rss_reta_entry64 *reta_conf, 66 uint16_t reta_size); 67 static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 68 struct rte_eth_rss_reta_entry64 *reta_conf, 69 uint16_t reta_size); 70 static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 71 struct rte_eth_rss_conf *rss_conf); 72 static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 73 struct rte_eth_rss_conf *rss_conf); 74 static int axgbe_dev_info_get(struct rte_eth_dev *dev, 75 struct rte_eth_dev_info *dev_info); 76 static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, 77 struct rte_eth_fc_conf *fc_conf); 78 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, 79 struct rte_eth_fc_conf *fc_conf); 80 static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 81 struct rte_eth_pfc_conf *pfc_conf); 82 static void axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 83 struct rte_eth_rxq_info *qinfo); 84 static void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 85 struct rte_eth_txq_info *qinfo); 86 const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 87 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 88 89 static int 90 axgbe_timesync_enable(struct rte_eth_dev *dev); 91 static int 92 axgbe_timesync_disable(struct rte_eth_dev *dev); 93 static int 94 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 95 struct timespec *timestamp, uint32_t flags); 96 static int 97 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 98 struct timespec *timestamp); 99 static int 100 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 101 static int 102 axgbe_timesync_read_time(struct rte_eth_dev *dev, 103 struct timespec *timestamp); 104 static int 105 axgbe_timesync_write_time(struct rte_eth_dev *dev, 106 const struct timespec *timestamp); 107 static void 108 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 109 unsigned int nsec); 110 static void 111 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 112 unsigned int addend); 113 static int 114 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on); 115 static int axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 116 enum rte_vlan_type vlan_type, uint16_t tpid); 117 static int axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 118 119 struct axgbe_xstats { 120 char name[RTE_ETH_XSTATS_NAME_SIZE]; 121 int offset; 122 }; 123 124 #define AXGMAC_MMC_STAT(_string, _var) \ 125 { _string, \ 126 offsetof(struct axgbe_mmc_stats, _var), \ 127 } 128 129 static const struct axgbe_xstats axgbe_xstats_strings[] = { 130 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb), 131 AXGMAC_MMC_STAT("tx_packets", txframecount_gb), 132 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb), 133 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb), 134 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb), 135 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g), 136 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb), 137 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb), 138 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb), 139 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb), 140 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb), 141 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb), 142 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror), 143 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes), 144 145 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb), 146 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb), 147 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g), 148 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g), 149 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g), 150 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb), 151 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb), 152 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb), 153 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb), 154 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb), 155 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb), 156 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb), 157 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g), 158 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g), 159 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror), 160 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror), 161 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror), 162 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror), 163 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype), 164 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow), 165 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror), 166 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes), 167 }; 168 169 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings) 170 171 /* The set of PCI devices this driver supports */ 172 #define AMD_PCI_VENDOR_ID 0x1022 173 #define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0 174 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 175 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459 176 177 static const struct rte_pci_id pci_id_axgbe_map[] = { 178 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)}, 179 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)}, 180 { .vendor_id = 0, }, 181 }; 182 183 static struct axgbe_version_data axgbe_v2a = { 184 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 185 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 186 .mmc_64bit = 1, 187 .tx_max_fifo_size = 229376, 188 .rx_max_fifo_size = 229376, 189 .tx_tstamp_workaround = 1, 190 .ecc_support = 1, 191 .i2c_support = 1, 192 .an_cdr_workaround = 1, 193 }; 194 195 static struct axgbe_version_data axgbe_v2b = { 196 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 197 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 198 .mmc_64bit = 1, 199 .tx_max_fifo_size = 65536, 200 .rx_max_fifo_size = 65536, 201 .tx_tstamp_workaround = 1, 202 .ecc_support = 1, 203 .i2c_support = 1, 204 .an_cdr_workaround = 1, 205 }; 206 207 static const struct rte_eth_desc_lim rx_desc_lim = { 208 .nb_max = AXGBE_MAX_RING_DESC, 209 .nb_min = AXGBE_MIN_RING_DESC, 210 .nb_align = 8, 211 }; 212 213 static const struct rte_eth_desc_lim tx_desc_lim = { 214 .nb_max = AXGBE_MAX_RING_DESC, 215 .nb_min = AXGBE_MIN_RING_DESC, 216 .nb_align = 8, 217 }; 218 219 static const struct eth_dev_ops axgbe_eth_dev_ops = { 220 .dev_configure = axgbe_dev_configure, 221 .dev_start = axgbe_dev_start, 222 .dev_stop = axgbe_dev_stop, 223 .dev_close = axgbe_dev_close, 224 .dev_reset = axgbe_dev_reset, 225 .promiscuous_enable = axgbe_dev_promiscuous_enable, 226 .promiscuous_disable = axgbe_dev_promiscuous_disable, 227 .allmulticast_enable = axgbe_dev_allmulticast_enable, 228 .allmulticast_disable = axgbe_dev_allmulticast_disable, 229 .mac_addr_set = axgbe_dev_mac_addr_set, 230 .mac_addr_add = axgbe_dev_mac_addr_add, 231 .mac_addr_remove = axgbe_dev_mac_addr_remove, 232 .set_mc_addr_list = axgbe_dev_set_mc_addr_list, 233 .uc_hash_table_set = axgbe_dev_uc_hash_table_set, 234 .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set, 235 .link_update = axgbe_dev_link_update, 236 .get_reg = axgbe_dev_get_regs, 237 .stats_get = axgbe_dev_stats_get, 238 .stats_reset = axgbe_dev_stats_reset, 239 .xstats_get = axgbe_dev_xstats_get, 240 .xstats_reset = axgbe_dev_xstats_reset, 241 .xstats_get_names = axgbe_dev_xstats_get_names, 242 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id, 243 .xstats_get_by_id = axgbe_dev_xstats_get_by_id, 244 .reta_update = axgbe_dev_rss_reta_update, 245 .reta_query = axgbe_dev_rss_reta_query, 246 .rss_hash_update = axgbe_dev_rss_hash_update, 247 .rss_hash_conf_get = axgbe_dev_rss_hash_conf_get, 248 .dev_infos_get = axgbe_dev_info_get, 249 .rx_queue_setup = axgbe_dev_rx_queue_setup, 250 .rx_queue_release = axgbe_dev_rx_queue_release, 251 .tx_queue_setup = axgbe_dev_tx_queue_setup, 252 .tx_queue_release = axgbe_dev_tx_queue_release, 253 .flow_ctrl_get = axgbe_flow_ctrl_get, 254 .flow_ctrl_set = axgbe_flow_ctrl_set, 255 .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set, 256 .rxq_info_get = axgbe_rxq_info_get, 257 .txq_info_get = axgbe_txq_info_get, 258 .dev_supported_ptypes_get = axgbe_dev_supported_ptypes_get, 259 .mtu_set = axgb_mtu_set, 260 .vlan_filter_set = axgbe_vlan_filter_set, 261 .vlan_tpid_set = axgbe_vlan_tpid_set, 262 .vlan_offload_set = axgbe_vlan_offload_set, 263 .timesync_enable = axgbe_timesync_enable, 264 .timesync_disable = axgbe_timesync_disable, 265 .timesync_read_rx_timestamp = axgbe_timesync_read_rx_timestamp, 266 .timesync_read_tx_timestamp = axgbe_timesync_read_tx_timestamp, 267 .timesync_adjust_time = axgbe_timesync_adjust_time, 268 .timesync_read_time = axgbe_timesync_read_time, 269 .timesync_write_time = axgbe_timesync_write_time, 270 .fw_version_get = axgbe_dev_fw_version_get, 271 }; 272 273 static int axgbe_phy_reset(struct axgbe_port *pdata) 274 { 275 pdata->phy_link = -1; 276 pdata->phy_speed = SPEED_UNKNOWN; 277 return pdata->phy_if.phy_reset(pdata); 278 } 279 280 /* 281 * Interrupt handler triggered by NIC for handling 282 * specific interrupt. 283 * 284 * @param handle 285 * Pointer to interrupt handle. 286 * @param param 287 * The address of parameter (struct rte_eth_dev *) regsitered before. 288 * 289 * @return 290 * void 291 */ 292 static void 293 axgbe_dev_interrupt_handler(void *param) 294 { 295 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 296 struct axgbe_port *pdata = dev->data->dev_private; 297 unsigned int dma_isr, dma_ch_isr; 298 299 pdata->phy_if.an_isr(pdata); 300 /*DMA related interrupts*/ 301 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR); 302 PMD_DRV_LOG(DEBUG, "DMA_ISR=%#010x\n", dma_isr); 303 if (dma_isr) { 304 if (dma_isr & 1) { 305 dma_ch_isr = 306 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *) 307 pdata->rx_queues[0], 308 DMA_CH_SR); 309 PMD_DRV_LOG(DEBUG, "DMA_CH0_ISR=%#010x\n", dma_ch_isr); 310 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *) 311 pdata->rx_queues[0], 312 DMA_CH_SR, dma_ch_isr); 313 } 314 } 315 /* Unmask interrupts since disabled after generation */ 316 rte_intr_ack(&pdata->pci_dev->intr_handle); 317 } 318 319 /* 320 * Configure device link speed and setup link. 321 * It returns 0 on success. 322 */ 323 static int 324 axgbe_dev_configure(struct rte_eth_dev *dev) 325 { 326 struct axgbe_port *pdata = dev->data->dev_private; 327 /* Checksum offload to hardware */ 328 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads & 329 DEV_RX_OFFLOAD_CHECKSUM; 330 return 0; 331 } 332 333 static int 334 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev) 335 { 336 struct axgbe_port *pdata = dev->data->dev_private; 337 338 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 339 pdata->rss_enable = 1; 340 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE) 341 pdata->rss_enable = 0; 342 else 343 return -1; 344 return 0; 345 } 346 347 static int 348 axgbe_dev_start(struct rte_eth_dev *dev) 349 { 350 struct axgbe_port *pdata = dev->data->dev_private; 351 int ret; 352 struct rte_eth_dev_data *dev_data = dev->data; 353 uint16_t max_pkt_len; 354 355 dev->dev_ops = &axgbe_eth_dev_ops; 356 357 PMD_INIT_FUNC_TRACE(); 358 359 /* Multiqueue RSS */ 360 ret = axgbe_dev_rx_mq_config(dev); 361 if (ret) { 362 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n"); 363 return ret; 364 } 365 ret = axgbe_phy_reset(pdata); 366 if (ret) { 367 PMD_DRV_LOG(ERR, "phy reset failed\n"); 368 return ret; 369 } 370 ret = pdata->hw_if.init(pdata); 371 if (ret) { 372 PMD_DRV_LOG(ERR, "dev_init failed\n"); 373 return ret; 374 } 375 376 /* enable uio/vfio intr/eventfd mapping */ 377 rte_intr_enable(&pdata->pci_dev->intr_handle); 378 379 /* phy start*/ 380 pdata->phy_if.phy_start(pdata); 381 axgbe_dev_enable_tx(dev); 382 axgbe_dev_enable_rx(dev); 383 384 rte_bit_relaxed_clear32(AXGBE_STOPPED, &pdata->dev_state); 385 rte_bit_relaxed_clear32(AXGBE_DOWN, &pdata->dev_state); 386 387 max_pkt_len = dev_data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 388 if ((dev_data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) || 389 max_pkt_len > pdata->rx_buf_size) 390 dev_data->scattered_rx = 1; 391 392 /* Scatter Rx handling */ 393 if (dev_data->scattered_rx) 394 dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts; 395 else 396 dev->rx_pkt_burst = &axgbe_recv_pkts; 397 398 return 0; 399 } 400 401 /* Stop device: disable rx and tx functions to allow for reconfiguring. */ 402 static int 403 axgbe_dev_stop(struct rte_eth_dev *dev) 404 { 405 struct axgbe_port *pdata = dev->data->dev_private; 406 407 PMD_INIT_FUNC_TRACE(); 408 409 rte_intr_disable(&pdata->pci_dev->intr_handle); 410 411 if (rte_bit_relaxed_get32(AXGBE_STOPPED, &pdata->dev_state)) 412 return 0; 413 414 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 415 axgbe_dev_disable_tx(dev); 416 axgbe_dev_disable_rx(dev); 417 418 pdata->phy_if.phy_stop(pdata); 419 pdata->hw_if.exit(pdata); 420 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); 421 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 422 423 return 0; 424 } 425 426 static int 427 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 428 { 429 struct axgbe_port *pdata = dev->data->dev_private; 430 431 PMD_INIT_FUNC_TRACE(); 432 433 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); 434 435 return 0; 436 } 437 438 static int 439 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 440 { 441 struct axgbe_port *pdata = dev->data->dev_private; 442 443 PMD_INIT_FUNC_TRACE(); 444 445 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); 446 447 return 0; 448 } 449 450 static int 451 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 452 { 453 struct axgbe_port *pdata = dev->data->dev_private; 454 455 PMD_INIT_FUNC_TRACE(); 456 457 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 458 return 0; 459 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1); 460 461 return 0; 462 } 463 464 static int 465 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 466 { 467 struct axgbe_port *pdata = dev->data->dev_private; 468 469 PMD_INIT_FUNC_TRACE(); 470 471 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 472 return 0; 473 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0); 474 475 return 0; 476 } 477 478 static int 479 axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 480 { 481 struct axgbe_port *pdata = dev->data->dev_private; 482 483 /* Set Default MAC Addr */ 484 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0); 485 486 return 0; 487 } 488 489 static int 490 axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 491 uint32_t index, uint32_t pool __rte_unused) 492 { 493 struct axgbe_port *pdata = dev->data->dev_private; 494 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 495 496 if (index > hw_feat->addn_mac) { 497 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index); 498 return -EINVAL; 499 } 500 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index); 501 return 0; 502 } 503 504 static int 505 axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 506 struct rte_eth_rss_reta_entry64 *reta_conf, 507 uint16_t reta_size) 508 { 509 struct axgbe_port *pdata = dev->data->dev_private; 510 unsigned int i, idx, shift; 511 int ret; 512 513 if (!pdata->rss_enable) { 514 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 515 return -ENOTSUP; 516 } 517 518 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 519 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size); 520 return -EINVAL; 521 } 522 523 for (i = 0; i < reta_size; i++) { 524 idx = i / RTE_RETA_GROUP_SIZE; 525 shift = i % RTE_RETA_GROUP_SIZE; 526 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 527 continue; 528 pdata->rss_table[i] = reta_conf[idx].reta[shift]; 529 } 530 531 /* Program the lookup table */ 532 ret = axgbe_write_rss_lookup_table(pdata); 533 return ret; 534 } 535 536 static int 537 axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 538 struct rte_eth_rss_reta_entry64 *reta_conf, 539 uint16_t reta_size) 540 { 541 struct axgbe_port *pdata = dev->data->dev_private; 542 unsigned int i, idx, shift; 543 544 if (!pdata->rss_enable) { 545 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 546 return -ENOTSUP; 547 } 548 549 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 550 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size); 551 return -EINVAL; 552 } 553 554 for (i = 0; i < reta_size; i++) { 555 idx = i / RTE_RETA_GROUP_SIZE; 556 shift = i % RTE_RETA_GROUP_SIZE; 557 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 558 continue; 559 reta_conf[idx].reta[shift] = pdata->rss_table[i]; 560 } 561 return 0; 562 } 563 564 static int 565 axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 566 struct rte_eth_rss_conf *rss_conf) 567 { 568 struct axgbe_port *pdata = dev->data->dev_private; 569 int ret; 570 571 if (!pdata->rss_enable) { 572 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 573 return -ENOTSUP; 574 } 575 576 if (rss_conf == NULL) { 577 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n"); 578 return -EINVAL; 579 } 580 581 if (rss_conf->rss_key != NULL && 582 rss_conf->rss_key_len == AXGBE_RSS_HASH_KEY_SIZE) { 583 rte_memcpy(pdata->rss_key, rss_conf->rss_key, 584 AXGBE_RSS_HASH_KEY_SIZE); 585 /* Program the hash key */ 586 ret = axgbe_write_rss_hash_key(pdata); 587 if (ret != 0) 588 return ret; 589 } 590 591 pdata->rss_hf = rss_conf->rss_hf & AXGBE_RSS_OFFLOAD; 592 593 if (pdata->rss_hf & (ETH_RSS_IPV4 | ETH_RSS_IPV6)) 594 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); 595 if (pdata->rss_hf & 596 (ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV6_TCP)) 597 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); 598 if (pdata->rss_hf & 599 (ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_NONFRAG_IPV6_UDP)) 600 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); 601 602 /* Set the RSS options */ 603 AXGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 604 605 return 0; 606 } 607 608 static int 609 axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 610 struct rte_eth_rss_conf *rss_conf) 611 { 612 struct axgbe_port *pdata = dev->data->dev_private; 613 614 if (!pdata->rss_enable) { 615 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 616 return -ENOTSUP; 617 } 618 619 if (rss_conf == NULL) { 620 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n"); 621 return -EINVAL; 622 } 623 624 if (rss_conf->rss_key != NULL && 625 rss_conf->rss_key_len >= AXGBE_RSS_HASH_KEY_SIZE) { 626 rte_memcpy(rss_conf->rss_key, pdata->rss_key, 627 AXGBE_RSS_HASH_KEY_SIZE); 628 } 629 rss_conf->rss_key_len = AXGBE_RSS_HASH_KEY_SIZE; 630 rss_conf->rss_hf = pdata->rss_hf; 631 return 0; 632 } 633 634 static int 635 axgbe_dev_reset(struct rte_eth_dev *dev) 636 { 637 int ret = 0; 638 639 ret = axgbe_dev_close(dev); 640 if (ret) 641 return ret; 642 643 ret = eth_axgbe_dev_init(dev); 644 645 return ret; 646 } 647 648 static void 649 axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 650 { 651 struct axgbe_port *pdata = dev->data->dev_private; 652 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 653 654 if (index > hw_feat->addn_mac) { 655 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index); 656 return; 657 } 658 axgbe_set_mac_addn_addr(pdata, NULL, index); 659 } 660 661 static int 662 axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 663 struct rte_ether_addr *mc_addr_set, 664 uint32_t nb_mc_addr) 665 { 666 struct axgbe_port *pdata = dev->data->dev_private; 667 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 668 uint32_t index = 1; /* 0 is always default mac */ 669 uint32_t i; 670 671 if (nb_mc_addr > hw_feat->addn_mac) { 672 PMD_DRV_LOG(ERR, "Invalid Index %d\n", nb_mc_addr); 673 return -EINVAL; 674 } 675 676 /* clear unicast addresses */ 677 for (i = 1; i < hw_feat->addn_mac; i++) { 678 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i])) 679 continue; 680 memset(&dev->data->mac_addrs[i], 0, 681 sizeof(struct rte_ether_addr)); 682 } 683 684 while (nb_mc_addr--) 685 axgbe_set_mac_addn_addr(pdata, (u8 *)mc_addr_set++, index++); 686 687 return 0; 688 } 689 690 static int 691 axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 692 struct rte_ether_addr *mac_addr, uint8_t add) 693 { 694 struct axgbe_port *pdata = dev->data->dev_private; 695 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 696 697 if (!hw_feat->hash_table_size) { 698 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); 699 return -ENOTSUP; 700 } 701 702 axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add); 703 704 if (pdata->uc_hash_mac_addr > 0) { 705 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 706 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 707 } else { 708 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 709 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 710 } 711 return 0; 712 } 713 714 static int 715 axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add) 716 { 717 struct axgbe_port *pdata = dev->data->dev_private; 718 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 719 uint32_t index; 720 721 if (!hw_feat->hash_table_size) { 722 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); 723 return -ENOTSUP; 724 } 725 726 for (index = 0; index < pdata->hash_table_count; index++) { 727 if (add) 728 pdata->uc_hash_table[index] = ~0; 729 else 730 pdata->uc_hash_table[index] = 0; 731 732 PMD_DRV_LOG(DEBUG, "%s MAC hash table at Index %#x\n", 733 add ? "set" : "clear", index); 734 735 AXGMAC_IOWRITE(pdata, MAC_HTR(index), 736 pdata->uc_hash_table[index]); 737 } 738 739 if (add) { 740 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 741 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 742 } else { 743 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 744 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 745 } 746 return 0; 747 } 748 749 /* return 0 means link status changed, -1 means not changed */ 750 static int 751 axgbe_dev_link_update(struct rte_eth_dev *dev, 752 int wait_to_complete __rte_unused) 753 { 754 struct axgbe_port *pdata = dev->data->dev_private; 755 struct rte_eth_link link; 756 int ret = 0; 757 758 PMD_INIT_FUNC_TRACE(); 759 rte_delay_ms(800); 760 761 pdata->phy_if.phy_status(pdata); 762 763 memset(&link, 0, sizeof(struct rte_eth_link)); 764 link.link_duplex = pdata->phy.duplex; 765 link.link_status = pdata->phy_link; 766 link.link_speed = pdata->phy_speed; 767 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 768 ETH_LINK_SPEED_FIXED); 769 ret = rte_eth_linkstatus_set(dev, &link); 770 if (ret == -1) 771 PMD_DRV_LOG(ERR, "No change in link status\n"); 772 773 return ret; 774 } 775 776 static int 777 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 778 { 779 struct axgbe_port *pdata = dev->data->dev_private; 780 781 if (regs->data == NULL) { 782 regs->length = axgbe_regs_get_count(pdata); 783 regs->width = sizeof(uint32_t); 784 return 0; 785 } 786 787 /* Only full register dump is supported */ 788 if (regs->length && 789 regs->length != (uint32_t)axgbe_regs_get_count(pdata)) 790 return -ENOTSUP; 791 792 regs->version = pdata->pci_dev->id.vendor_id << 16 | 793 pdata->pci_dev->id.device_id; 794 axgbe_regs_dump(pdata, regs->data); 795 return 0; 796 } 797 static void axgbe_read_mmc_stats(struct axgbe_port *pdata) 798 { 799 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 800 801 /* Freeze counters */ 802 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 803 804 /* Tx counters */ 805 stats->txoctetcount_gb += 806 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO); 807 stats->txoctetcount_gb += 808 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32); 809 810 stats->txframecount_gb += 811 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO); 812 stats->txframecount_gb += 813 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32); 814 815 stats->txbroadcastframes_g += 816 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO); 817 stats->txbroadcastframes_g += 818 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32); 819 820 stats->txmulticastframes_g += 821 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO); 822 stats->txmulticastframes_g += 823 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32); 824 825 stats->tx64octets_gb += 826 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO); 827 stats->tx64octets_gb += 828 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32); 829 830 stats->tx65to127octets_gb += 831 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO); 832 stats->tx65to127octets_gb += 833 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32); 834 835 stats->tx128to255octets_gb += 836 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO); 837 stats->tx128to255octets_gb += 838 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32); 839 840 stats->tx256to511octets_gb += 841 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO); 842 stats->tx256to511octets_gb += 843 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32); 844 845 stats->tx512to1023octets_gb += 846 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO); 847 stats->tx512to1023octets_gb += 848 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32); 849 850 stats->tx1024tomaxoctets_gb += 851 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 852 stats->tx1024tomaxoctets_gb += 853 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32); 854 855 stats->txunicastframes_gb += 856 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO); 857 stats->txunicastframes_gb += 858 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32); 859 860 stats->txmulticastframes_gb += 861 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 862 stats->txmulticastframes_gb += 863 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32); 864 865 stats->txbroadcastframes_g += 866 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 867 stats->txbroadcastframes_g += 868 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32); 869 870 stats->txunderflowerror += 871 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO); 872 stats->txunderflowerror += 873 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32); 874 875 stats->txoctetcount_g += 876 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO); 877 stats->txoctetcount_g += 878 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32); 879 880 stats->txframecount_g += 881 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO); 882 stats->txframecount_g += 883 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32); 884 885 stats->txpauseframes += 886 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO); 887 stats->txpauseframes += 888 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32); 889 890 stats->txvlanframes_g += 891 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO); 892 stats->txvlanframes_g += 893 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32); 894 895 /* Rx counters */ 896 stats->rxframecount_gb += 897 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO); 898 stats->rxframecount_gb += 899 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32); 900 901 stats->rxoctetcount_gb += 902 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO); 903 stats->rxoctetcount_gb += 904 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32); 905 906 stats->rxoctetcount_g += 907 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO); 908 stats->rxoctetcount_g += 909 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32); 910 911 stats->rxbroadcastframes_g += 912 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO); 913 stats->rxbroadcastframes_g += 914 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32); 915 916 stats->rxmulticastframes_g += 917 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO); 918 stats->rxmulticastframes_g += 919 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32); 920 921 stats->rxcrcerror += 922 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO); 923 stats->rxcrcerror += 924 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32); 925 926 stats->rxrunterror += 927 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR); 928 929 stats->rxjabbererror += 930 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR); 931 932 stats->rxundersize_g += 933 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G); 934 935 stats->rxoversize_g += 936 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G); 937 938 stats->rx64octets_gb += 939 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO); 940 stats->rx64octets_gb += 941 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32); 942 943 stats->rx65to127octets_gb += 944 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO); 945 stats->rx65to127octets_gb += 946 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32); 947 948 stats->rx128to255octets_gb += 949 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO); 950 stats->rx128to255octets_gb += 951 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32); 952 953 stats->rx256to511octets_gb += 954 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO); 955 stats->rx256to511octets_gb += 956 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32); 957 958 stats->rx512to1023octets_gb += 959 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO); 960 stats->rx512to1023octets_gb += 961 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32); 962 963 stats->rx1024tomaxoctets_gb += 964 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 965 stats->rx1024tomaxoctets_gb += 966 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32); 967 968 stats->rxunicastframes_g += 969 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO); 970 stats->rxunicastframes_g += 971 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32); 972 973 stats->rxlengtherror += 974 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO); 975 stats->rxlengtherror += 976 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32); 977 978 stats->rxoutofrangetype += 979 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO); 980 stats->rxoutofrangetype += 981 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32); 982 983 stats->rxpauseframes += 984 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO); 985 stats->rxpauseframes += 986 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32); 987 988 stats->rxfifooverflow += 989 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO); 990 stats->rxfifooverflow += 991 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32); 992 993 stats->rxvlanframes_gb += 994 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO); 995 stats->rxvlanframes_gb += 996 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32); 997 998 stats->rxwatchdogerror += 999 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR); 1000 1001 /* Un-freeze counters */ 1002 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 1003 } 1004 1005 static int 1006 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1007 unsigned int n) 1008 { 1009 struct axgbe_port *pdata = dev->data->dev_private; 1010 unsigned int i; 1011 1012 if (!stats) 1013 return 0; 1014 1015 axgbe_read_mmc_stats(pdata); 1016 1017 for (i = 0; i < n && i < AXGBE_XSTATS_COUNT; i++) { 1018 stats[i].id = i; 1019 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1020 axgbe_xstats_strings[i].offset); 1021 } 1022 1023 return i; 1024 } 1025 1026 static int 1027 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1028 struct rte_eth_xstat_name *xstats_names, 1029 unsigned int n) 1030 { 1031 unsigned int i; 1032 1033 if (n >= AXGBE_XSTATS_COUNT && xstats_names) { 1034 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) { 1035 snprintf(xstats_names[i].name, 1036 RTE_ETH_XSTATS_NAME_SIZE, "%s", 1037 axgbe_xstats_strings[i].name); 1038 } 1039 } 1040 1041 return AXGBE_XSTATS_COUNT; 1042 } 1043 1044 static int 1045 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1046 uint64_t *values, unsigned int n) 1047 { 1048 unsigned int i; 1049 uint64_t values_copy[AXGBE_XSTATS_COUNT]; 1050 1051 if (!ids) { 1052 struct axgbe_port *pdata = dev->data->dev_private; 1053 1054 if (n < AXGBE_XSTATS_COUNT) 1055 return AXGBE_XSTATS_COUNT; 1056 1057 axgbe_read_mmc_stats(pdata); 1058 1059 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1060 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1061 axgbe_xstats_strings[i].offset); 1062 } 1063 1064 return i; 1065 } 1066 1067 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT); 1068 1069 for (i = 0; i < n; i++) { 1070 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1071 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 1072 return -1; 1073 } 1074 values[i] = values_copy[ids[i]]; 1075 } 1076 return n; 1077 } 1078 1079 static int 1080 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 1081 const uint64_t *ids, 1082 struct rte_eth_xstat_name *xstats_names, 1083 unsigned int size) 1084 { 1085 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT]; 1086 unsigned int i; 1087 1088 if (!ids) 1089 return axgbe_dev_xstats_get_names(dev, xstats_names, size); 1090 1091 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size); 1092 1093 for (i = 0; i < size; i++) { 1094 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1095 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 1096 return -1; 1097 } 1098 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1099 } 1100 return size; 1101 } 1102 1103 static int 1104 axgbe_dev_xstats_reset(struct rte_eth_dev *dev) 1105 { 1106 struct axgbe_port *pdata = dev->data->dev_private; 1107 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 1108 1109 /* MMC registers are configured for reset on read */ 1110 axgbe_read_mmc_stats(pdata); 1111 1112 /* Reset stats */ 1113 memset(stats, 0, sizeof(*stats)); 1114 1115 return 0; 1116 } 1117 1118 static int 1119 axgbe_dev_stats_get(struct rte_eth_dev *dev, 1120 struct rte_eth_stats *stats) 1121 { 1122 struct axgbe_rx_queue *rxq; 1123 struct axgbe_tx_queue *txq; 1124 struct axgbe_port *pdata = dev->data->dev_private; 1125 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats; 1126 unsigned int i; 1127 1128 axgbe_read_mmc_stats(pdata); 1129 1130 stats->imissed = mmc_stats->rxfifooverflow; 1131 1132 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1133 rxq = dev->data->rx_queues[i]; 1134 if (rxq) { 1135 stats->q_ipackets[i] = rxq->pkts; 1136 stats->ipackets += rxq->pkts; 1137 stats->q_ibytes[i] = rxq->bytes; 1138 stats->ibytes += rxq->bytes; 1139 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed; 1140 stats->q_errors[i] = rxq->errors 1141 + rxq->rx_mbuf_alloc_failed; 1142 stats->ierrors += rxq->errors; 1143 } else { 1144 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n", 1145 dev->data->port_id); 1146 } 1147 } 1148 1149 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1150 txq = dev->data->tx_queues[i]; 1151 if (txq) { 1152 stats->q_opackets[i] = txq->pkts; 1153 stats->opackets += txq->pkts; 1154 stats->q_obytes[i] = txq->bytes; 1155 stats->obytes += txq->bytes; 1156 stats->oerrors += txq->errors; 1157 } else { 1158 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n", 1159 dev->data->port_id); 1160 } 1161 } 1162 1163 return 0; 1164 } 1165 1166 static int 1167 axgbe_dev_stats_reset(struct rte_eth_dev *dev) 1168 { 1169 struct axgbe_rx_queue *rxq; 1170 struct axgbe_tx_queue *txq; 1171 unsigned int i; 1172 1173 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1174 rxq = dev->data->rx_queues[i]; 1175 if (rxq) { 1176 rxq->pkts = 0; 1177 rxq->bytes = 0; 1178 rxq->errors = 0; 1179 rxq->rx_mbuf_alloc_failed = 0; 1180 } else { 1181 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n", 1182 dev->data->port_id); 1183 } 1184 } 1185 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1186 txq = dev->data->tx_queues[i]; 1187 if (txq) { 1188 txq->pkts = 0; 1189 txq->bytes = 0; 1190 txq->errors = 0; 1191 } else { 1192 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n", 1193 dev->data->port_id); 1194 } 1195 } 1196 1197 return 0; 1198 } 1199 1200 static int 1201 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1202 { 1203 struct axgbe_port *pdata = dev->data->dev_private; 1204 1205 dev_info->max_rx_queues = pdata->rx_ring_count; 1206 dev_info->max_tx_queues = pdata->tx_ring_count; 1207 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE; 1208 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE; 1209 dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1; 1210 dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size; 1211 dev_info->speed_capa = ETH_LINK_SPEED_10G; 1212 1213 dev_info->rx_offload_capa = 1214 DEV_RX_OFFLOAD_VLAN_STRIP | 1215 DEV_RX_OFFLOAD_VLAN_FILTER | 1216 DEV_RX_OFFLOAD_VLAN_EXTEND | 1217 DEV_RX_OFFLOAD_IPV4_CKSUM | 1218 DEV_RX_OFFLOAD_UDP_CKSUM | 1219 DEV_RX_OFFLOAD_TCP_CKSUM | 1220 DEV_RX_OFFLOAD_JUMBO_FRAME | 1221 DEV_RX_OFFLOAD_SCATTER | 1222 DEV_RX_OFFLOAD_KEEP_CRC; 1223 1224 dev_info->tx_offload_capa = 1225 DEV_TX_OFFLOAD_VLAN_INSERT | 1226 DEV_TX_OFFLOAD_QINQ_INSERT | 1227 DEV_TX_OFFLOAD_IPV4_CKSUM | 1228 DEV_TX_OFFLOAD_UDP_CKSUM | 1229 DEV_TX_OFFLOAD_TCP_CKSUM; 1230 1231 if (pdata->hw_feat.rss) { 1232 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD; 1233 dev_info->reta_size = pdata->hw_feat.hash_table_size; 1234 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE; 1235 } 1236 1237 dev_info->rx_desc_lim = rx_desc_lim; 1238 dev_info->tx_desc_lim = tx_desc_lim; 1239 1240 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1241 .rx_free_thresh = AXGBE_RX_FREE_THRESH, 1242 }; 1243 1244 dev_info->default_txconf = (struct rte_eth_txconf) { 1245 .tx_free_thresh = AXGBE_TX_FREE_THRESH, 1246 }; 1247 1248 return 0; 1249 } 1250 1251 static int 1252 axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1253 { 1254 struct axgbe_port *pdata = dev->data->dev_private; 1255 struct xgbe_fc_info fc = pdata->fc; 1256 unsigned int reg, reg_val = 0; 1257 1258 reg = MAC_Q0TFCR; 1259 reg_val = AXGMAC_IOREAD(pdata, reg); 1260 fc.low_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA); 1261 fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD); 1262 fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT); 1263 fc.autoneg = pdata->pause_autoneg; 1264 1265 if (pdata->rx_pause && pdata->tx_pause) 1266 fc.mode = RTE_FC_FULL; 1267 else if (pdata->rx_pause) 1268 fc.mode = RTE_FC_RX_PAUSE; 1269 else if (pdata->tx_pause) 1270 fc.mode = RTE_FC_TX_PAUSE; 1271 else 1272 fc.mode = RTE_FC_NONE; 1273 1274 fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024; 1275 fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024; 1276 fc_conf->pause_time = fc.pause_time[0]; 1277 fc_conf->send_xon = fc.send_xon; 1278 fc_conf->mode = fc.mode; 1279 1280 return 0; 1281 } 1282 1283 static int 1284 axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1285 { 1286 struct axgbe_port *pdata = dev->data->dev_private; 1287 struct xgbe_fc_info fc = pdata->fc; 1288 unsigned int reg, reg_val = 0; 1289 reg = MAC_Q0TFCR; 1290 1291 pdata->pause_autoneg = fc_conf->autoneg; 1292 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1293 fc.send_xon = fc_conf->send_xon; 1294 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA, 1295 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water)); 1296 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD, 1297 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water)); 1298 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time); 1299 AXGMAC_IOWRITE(pdata, reg, reg_val); 1300 fc.mode = fc_conf->mode; 1301 1302 if (fc.mode == RTE_FC_FULL) { 1303 pdata->tx_pause = 1; 1304 pdata->rx_pause = 1; 1305 } else if (fc.mode == RTE_FC_RX_PAUSE) { 1306 pdata->tx_pause = 0; 1307 pdata->rx_pause = 1; 1308 } else if (fc.mode == RTE_FC_TX_PAUSE) { 1309 pdata->tx_pause = 1; 1310 pdata->rx_pause = 0; 1311 } else { 1312 pdata->tx_pause = 0; 1313 pdata->rx_pause = 0; 1314 } 1315 1316 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1317 pdata->hw_if.config_tx_flow_control(pdata); 1318 1319 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1320 pdata->hw_if.config_rx_flow_control(pdata); 1321 1322 pdata->hw_if.config_flow_control(pdata); 1323 pdata->phy.tx_pause = pdata->tx_pause; 1324 pdata->phy.rx_pause = pdata->rx_pause; 1325 1326 return 0; 1327 } 1328 1329 static int 1330 axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 1331 struct rte_eth_pfc_conf *pfc_conf) 1332 { 1333 struct axgbe_port *pdata = dev->data->dev_private; 1334 struct xgbe_fc_info fc = pdata->fc; 1335 uint8_t tc_num; 1336 1337 tc_num = pdata->pfc_map[pfc_conf->priority]; 1338 1339 if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) { 1340 PMD_INIT_LOG(ERR, "Max supported traffic class: %d\n", 1341 pdata->hw_feat.tc_cnt); 1342 return -EINVAL; 1343 } 1344 1345 pdata->pause_autoneg = pfc_conf->fc.autoneg; 1346 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1347 fc.send_xon = pfc_conf->fc.send_xon; 1348 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA, 1349 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water)); 1350 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD, 1351 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water)); 1352 1353 switch (tc_num) { 1354 case 0: 1355 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1356 PSTC0, pfc_conf->fc.pause_time); 1357 break; 1358 case 1: 1359 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1360 PSTC1, pfc_conf->fc.pause_time); 1361 break; 1362 case 2: 1363 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1364 PSTC2, pfc_conf->fc.pause_time); 1365 break; 1366 case 3: 1367 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1368 PSTC3, pfc_conf->fc.pause_time); 1369 break; 1370 case 4: 1371 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1372 PSTC4, pfc_conf->fc.pause_time); 1373 break; 1374 case 5: 1375 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1376 PSTC5, pfc_conf->fc.pause_time); 1377 break; 1378 case 7: 1379 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1380 PSTC6, pfc_conf->fc.pause_time); 1381 break; 1382 case 6: 1383 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1384 PSTC7, pfc_conf->fc.pause_time); 1385 break; 1386 } 1387 1388 fc.mode = pfc_conf->fc.mode; 1389 1390 if (fc.mode == RTE_FC_FULL) { 1391 pdata->tx_pause = 1; 1392 pdata->rx_pause = 1; 1393 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1394 } else if (fc.mode == RTE_FC_RX_PAUSE) { 1395 pdata->tx_pause = 0; 1396 pdata->rx_pause = 1; 1397 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1398 } else if (fc.mode == RTE_FC_TX_PAUSE) { 1399 pdata->tx_pause = 1; 1400 pdata->rx_pause = 0; 1401 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1402 } else { 1403 pdata->tx_pause = 0; 1404 pdata->rx_pause = 0; 1405 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1406 } 1407 1408 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1409 pdata->hw_if.config_tx_flow_control(pdata); 1410 1411 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1412 pdata->hw_if.config_rx_flow_control(pdata); 1413 pdata->hw_if.config_flow_control(pdata); 1414 pdata->phy.tx_pause = pdata->tx_pause; 1415 pdata->phy.rx_pause = pdata->rx_pause; 1416 1417 return 0; 1418 } 1419 1420 void 1421 axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1422 struct rte_eth_rxq_info *qinfo) 1423 { 1424 struct axgbe_rx_queue *rxq; 1425 1426 rxq = dev->data->rx_queues[queue_id]; 1427 qinfo->mp = rxq->mb_pool; 1428 qinfo->scattered_rx = dev->data->scattered_rx; 1429 qinfo->nb_desc = rxq->nb_desc; 1430 qinfo->conf.rx_free_thresh = rxq->free_thresh; 1431 } 1432 1433 void 1434 axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1435 struct rte_eth_txq_info *qinfo) 1436 { 1437 struct axgbe_tx_queue *txq; 1438 1439 txq = dev->data->tx_queues[queue_id]; 1440 qinfo->nb_desc = txq->nb_desc; 1441 qinfo->conf.tx_free_thresh = txq->free_thresh; 1442 } 1443 const uint32_t * 1444 axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1445 { 1446 static const uint32_t ptypes[] = { 1447 RTE_PTYPE_L2_ETHER, 1448 RTE_PTYPE_L2_ETHER_TIMESYNC, 1449 RTE_PTYPE_L2_ETHER_LLDP, 1450 RTE_PTYPE_L2_ETHER_ARP, 1451 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1452 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 1453 RTE_PTYPE_L4_FRAG, 1454 RTE_PTYPE_L4_ICMP, 1455 RTE_PTYPE_L4_NONFRAG, 1456 RTE_PTYPE_L4_SCTP, 1457 RTE_PTYPE_L4_TCP, 1458 RTE_PTYPE_L4_UDP, 1459 RTE_PTYPE_TUNNEL_GRENAT, 1460 RTE_PTYPE_TUNNEL_IP, 1461 RTE_PTYPE_INNER_L2_ETHER, 1462 RTE_PTYPE_INNER_L2_ETHER_VLAN, 1463 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 1464 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 1465 RTE_PTYPE_INNER_L4_FRAG, 1466 RTE_PTYPE_INNER_L4_ICMP, 1467 RTE_PTYPE_INNER_L4_NONFRAG, 1468 RTE_PTYPE_INNER_L4_SCTP, 1469 RTE_PTYPE_INNER_L4_TCP, 1470 RTE_PTYPE_INNER_L4_UDP, 1471 RTE_PTYPE_UNKNOWN 1472 }; 1473 1474 if (dev->rx_pkt_burst == axgbe_recv_pkts) 1475 return ptypes; 1476 return NULL; 1477 } 1478 1479 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1480 { 1481 struct rte_eth_dev_info dev_info; 1482 struct axgbe_port *pdata = dev->data->dev_private; 1483 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 1484 unsigned int val = 0; 1485 axgbe_dev_info_get(dev, &dev_info); 1486 /* check that mtu is within the allowed range */ 1487 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) 1488 return -EINVAL; 1489 /* mtu setting is forbidden if port is start */ 1490 if (dev->data->dev_started) { 1491 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", 1492 dev->data->port_id); 1493 return -EBUSY; 1494 } 1495 if (mtu > RTE_ETHER_MTU) 1496 val = 1; 1497 else 1498 val = 0; 1499 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 1500 return 0; 1501 } 1502 1503 static void 1504 axgbe_update_tstamp_time(struct axgbe_port *pdata, 1505 unsigned int sec, unsigned int nsec, int addsub) 1506 { 1507 unsigned int count = 100; 1508 uint32_t sub_val = 0; 1509 uint32_t sub_val_sec = 0xFFFFFFFF; 1510 uint32_t sub_val_nsec = 0x3B9ACA00; 1511 1512 if (addsub) { 1513 if (sec) 1514 sub_val = sub_val_sec - (sec - 1); 1515 else 1516 sub_val = sec; 1517 1518 AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val); 1519 sub_val = sub_val_nsec - nsec; 1520 AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val); 1521 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1); 1522 } else { 1523 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1524 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0); 1525 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1526 } 1527 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1528 /* Wait for time update to complete */ 1529 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1530 rte_delay_ms(1); 1531 } 1532 1533 static inline uint64_t 1534 div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) 1535 { 1536 *remainder = dividend % divisor; 1537 return dividend / divisor; 1538 } 1539 1540 static inline uint64_t 1541 div_u64(uint64_t dividend, uint32_t divisor) 1542 { 1543 uint32_t remainder; 1544 return div_u64_rem(dividend, divisor, &remainder); 1545 } 1546 1547 static int 1548 axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta) 1549 { 1550 uint64_t adjust; 1551 uint32_t addend, diff; 1552 unsigned int neg_adjust = 0; 1553 1554 if (delta < 0) { 1555 neg_adjust = 1; 1556 delta = -delta; 1557 } 1558 adjust = (uint64_t)pdata->tstamp_addend; 1559 adjust *= delta; 1560 diff = (uint32_t)div_u64(adjust, 1000000000UL); 1561 addend = (neg_adjust) ? pdata->tstamp_addend - diff : 1562 pdata->tstamp_addend + diff; 1563 pdata->tstamp_addend = addend; 1564 axgbe_update_tstamp_addend(pdata, addend); 1565 return 0; 1566 } 1567 1568 static int 1569 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 1570 { 1571 struct axgbe_port *pdata = dev->data->dev_private; 1572 struct timespec timestamp_delta; 1573 1574 axgbe_adjfreq(pdata, delta); 1575 pdata->systime_tc.nsec += delta; 1576 1577 if (delta < 0) { 1578 delta = -delta; 1579 timestamp_delta = rte_ns_to_timespec(delta); 1580 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1581 timestamp_delta.tv_nsec, 1); 1582 } else { 1583 timestamp_delta = rte_ns_to_timespec(delta); 1584 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1585 timestamp_delta.tv_nsec, 0); 1586 } 1587 return 0; 1588 } 1589 1590 static int 1591 axgbe_timesync_read_time(struct rte_eth_dev *dev, 1592 struct timespec *timestamp) 1593 { 1594 uint64_t nsec; 1595 struct axgbe_port *pdata = dev->data->dev_private; 1596 1597 nsec = AXGMAC_IOREAD(pdata, MAC_STSR); 1598 nsec *= NSEC_PER_SEC; 1599 nsec += AXGMAC_IOREAD(pdata, MAC_STNR); 1600 *timestamp = rte_ns_to_timespec(nsec); 1601 return 0; 1602 } 1603 static int 1604 axgbe_timesync_write_time(struct rte_eth_dev *dev, 1605 const struct timespec *timestamp) 1606 { 1607 unsigned int count = 100; 1608 struct axgbe_port *pdata = dev->data->dev_private; 1609 1610 AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec); 1611 AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec); 1612 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1613 /* Wait for time update to complete */ 1614 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1615 rte_delay_ms(1); 1616 if (!count) 1617 PMD_DRV_LOG(ERR, "Timed out update timestamp\n"); 1618 return 0; 1619 } 1620 1621 static void 1622 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 1623 uint32_t addend) 1624 { 1625 unsigned int count = 100; 1626 1627 AXGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1628 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1629 1630 /* Wait for addend update to complete */ 1631 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1632 rte_delay_ms(1); 1633 if (!count) 1634 PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n"); 1635 } 1636 1637 static void 1638 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 1639 unsigned int nsec) 1640 { 1641 unsigned int count = 100; 1642 1643 /*System Time Sec Update*/ 1644 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1645 /*System Time nanoSec Update*/ 1646 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1647 /*Initialize Timestamp*/ 1648 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1649 1650 /* Wait for time update to complete */ 1651 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1652 rte_delay_ms(1); 1653 if (!count) 1654 PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n"); 1655 } 1656 1657 static int 1658 axgbe_timesync_enable(struct rte_eth_dev *dev) 1659 { 1660 struct axgbe_port *pdata = dev->data->dev_private; 1661 unsigned int mac_tscr = 0; 1662 uint64_t dividend; 1663 struct timespec timestamp; 1664 uint64_t nsec; 1665 1666 /* Set one nano-second accuracy */ 1667 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1668 1669 /* Set fine timestamp update */ 1670 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1671 1672 /* Overwrite earlier timestamps */ 1673 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1674 1675 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1676 1677 /* Enabling processing of ptp over eth pkt */ 1678 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1679 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1680 /* Enable timestamp for all pkts*/ 1681 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 1682 1683 /* enabling timestamp */ 1684 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1685 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1686 1687 /* Exit if timestamping is not enabled */ 1688 if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) { 1689 PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n"); 1690 return 0; 1691 } 1692 1693 /* Sub-second Increment Value*/ 1694 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC); 1695 /* Sub-nanosecond Increment Value */ 1696 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC); 1697 1698 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 1699 dividend = 50000000; 1700 dividend <<= 32; 1701 pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate); 1702 1703 axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1704 axgbe_set_tstamp_time(pdata, 0, 0); 1705 1706 /* Initialize the timecounter */ 1707 memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter)); 1708 1709 pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK; 1710 pdata->systime_tc.cc_shift = 0; 1711 pdata->systime_tc.nsec_mask = 0; 1712 1713 PMD_DRV_LOG(DEBUG, "Initializing system time counter with realtime\n"); 1714 1715 /* Updating the counter once with clock real time */ 1716 clock_gettime(CLOCK_REALTIME, ×tamp); 1717 nsec = rte_timespec_to_ns(×tamp); 1718 nsec = rte_timecounter_update(&pdata->systime_tc, nsec); 1719 axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec); 1720 return 0; 1721 } 1722 1723 static int 1724 axgbe_timesync_disable(struct rte_eth_dev *dev) 1725 { 1726 struct axgbe_port *pdata = dev->data->dev_private; 1727 unsigned int mac_tscr = 0; 1728 1729 /*disable timestamp for all pkts*/ 1730 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0); 1731 /*disable the addened register*/ 1732 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0); 1733 /* disable timestamp update */ 1734 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0); 1735 /*disable time stamp*/ 1736 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0); 1737 return 0; 1738 } 1739 1740 static int 1741 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 1742 struct timespec *timestamp, uint32_t flags) 1743 { 1744 uint64_t nsec = 0; 1745 volatile union axgbe_rx_desc *desc; 1746 uint16_t idx, pmt; 1747 struct axgbe_rx_queue *rxq = *dev->data->rx_queues; 1748 1749 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 1750 desc = &rxq->desc[idx]; 1751 1752 while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 1753 rte_delay_ms(1); 1754 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) { 1755 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) && 1756 !AXGMAC_GET_BITS_LE(desc->write.desc3, 1757 RX_CONTEXT_DESC3, TSD)) { 1758 pmt = AXGMAC_GET_BITS_LE(desc->write.desc3, 1759 RX_CONTEXT_DESC3, PMT); 1760 nsec = rte_le_to_cpu_32(desc->write.desc1); 1761 nsec *= NSEC_PER_SEC; 1762 nsec += rte_le_to_cpu_32(desc->write.desc0); 1763 if (nsec != 0xffffffffffffffffULL) { 1764 if (pmt == 0x01) 1765 *timestamp = rte_ns_to_timespec(nsec); 1766 PMD_DRV_LOG(DEBUG, 1767 "flags = 0x%x nsec = %"PRIu64"\n", 1768 flags, nsec); 1769 } 1770 } 1771 } 1772 1773 return 0; 1774 } 1775 1776 static int 1777 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 1778 struct timespec *timestamp) 1779 { 1780 uint64_t nsec; 1781 struct axgbe_port *pdata = dev->data->dev_private; 1782 unsigned int tx_snr, tx_ssr; 1783 1784 rte_delay_us(5); 1785 if (pdata->vdata->tx_tstamp_workaround) { 1786 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1787 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1788 1789 } else { 1790 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1791 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1792 } 1793 if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) { 1794 PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n"); 1795 return 0; 1796 } 1797 nsec = tx_ssr; 1798 nsec *= NSEC_PER_SEC; 1799 nsec += tx_snr; 1800 PMD_DRV_LOG(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d\n", 1801 nsec, tx_ssr, tx_snr); 1802 *timestamp = rte_ns_to_timespec(nsec); 1803 return 0; 1804 } 1805 1806 static int 1807 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1808 { 1809 struct axgbe_port *pdata = dev->data->dev_private; 1810 unsigned long vid_bit, vid_idx; 1811 1812 vid_bit = VLAN_TABLE_BIT(vid); 1813 vid_idx = VLAN_TABLE_IDX(vid); 1814 1815 if (on) { 1816 PMD_DRV_LOG(DEBUG, "Set VLAN vid=%d for device = %s\n", 1817 vid, pdata->eth_dev->device->name); 1818 pdata->active_vlans[vid_idx] |= vid_bit; 1819 } else { 1820 PMD_DRV_LOG(DEBUG, "Reset VLAN vid=%d for device = %s\n", 1821 vid, pdata->eth_dev->device->name); 1822 pdata->active_vlans[vid_idx] &= ~vid_bit; 1823 } 1824 pdata->hw_if.update_vlan_hash_table(pdata); 1825 return 0; 1826 } 1827 1828 static int 1829 axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1830 enum rte_vlan_type vlan_type, 1831 uint16_t tpid) 1832 { 1833 struct axgbe_port *pdata = dev->data->dev_private; 1834 uint32_t reg = 0; 1835 uint32_t qinq = 0; 1836 1837 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1838 PMD_DRV_LOG(DEBUG, "EDVLP: qinq = 0x%x\n", qinq); 1839 1840 switch (vlan_type) { 1841 case ETH_VLAN_TYPE_INNER: 1842 PMD_DRV_LOG(DEBUG, "ETH_VLAN_TYPE_INNER\n"); 1843 if (qinq) { 1844 if (tpid != 0x8100 && tpid != 0x88a8) 1845 PMD_DRV_LOG(ERR, 1846 "tag supported 0x8100/0x88A8\n"); 1847 PMD_DRV_LOG(DEBUG, "qinq with inner tag\n"); 1848 1849 /*Enable Inner VLAN Tag */ 1850 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 1); 1851 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1852 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg); 1853 1854 } else { 1855 PMD_DRV_LOG(ERR, 1856 "Inner type not supported in single tag\n"); 1857 } 1858 break; 1859 case ETH_VLAN_TYPE_OUTER: 1860 PMD_DRV_LOG(DEBUG, "ETH_VLAN_TYPE_OUTER\n"); 1861 if (qinq) { 1862 PMD_DRV_LOG(DEBUG, "double tagging is enabled\n"); 1863 /*Enable outer VLAN tag*/ 1864 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 0); 1865 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1866 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg); 1867 1868 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 1); 1869 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANIR, CSVL); 1870 PMD_DRV_LOG(DEBUG, "bit CSVL = 0x%x\n", reg); 1871 } else { 1872 if (tpid != 0x8100 && tpid != 0x88a8) 1873 PMD_DRV_LOG(ERR, 1874 "tag supported 0x8100/0x88A8\n"); 1875 } 1876 break; 1877 case ETH_VLAN_TYPE_MAX: 1878 PMD_DRV_LOG(ERR, "ETH_VLAN_TYPE_MAX\n"); 1879 break; 1880 case ETH_VLAN_TYPE_UNKNOWN: 1881 PMD_DRV_LOG(ERR, "ETH_VLAN_TYPE_UNKNOWN\n"); 1882 break; 1883 } 1884 return 0; 1885 } 1886 1887 static void axgbe_vlan_extend_enable(struct axgbe_port *pdata) 1888 { 1889 int qinq = 0; 1890 1891 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 1); 1892 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1893 PMD_DRV_LOG(DEBUG, "vlan double tag enabled EDVLP:qinq=0x%x\n", qinq); 1894 } 1895 1896 static void axgbe_vlan_extend_disable(struct axgbe_port *pdata) 1897 { 1898 int qinq = 0; 1899 1900 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 0); 1901 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1902 PMD_DRV_LOG(DEBUG, "vlan double tag disable EDVLP:qinq=0x%x\n", qinq); 1903 } 1904 1905 static int 1906 axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1907 { 1908 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1909 struct axgbe_port *pdata = dev->data->dev_private; 1910 1911 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 1912 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 1913 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 1914 1915 if (mask & ETH_VLAN_STRIP_MASK) { 1916 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 1917 PMD_DRV_LOG(DEBUG, "Strip ON for device = %s\n", 1918 pdata->eth_dev->device->name); 1919 pdata->hw_if.enable_rx_vlan_stripping(pdata); 1920 } else { 1921 PMD_DRV_LOG(DEBUG, "Strip OFF for device = %s\n", 1922 pdata->eth_dev->device->name); 1923 pdata->hw_if.disable_rx_vlan_stripping(pdata); 1924 } 1925 } 1926 if (mask & ETH_VLAN_FILTER_MASK) { 1927 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 1928 PMD_DRV_LOG(DEBUG, "Filter ON for device = %s\n", 1929 pdata->eth_dev->device->name); 1930 pdata->hw_if.enable_rx_vlan_filtering(pdata); 1931 } else { 1932 PMD_DRV_LOG(DEBUG, "Filter OFF for device = %s\n", 1933 pdata->eth_dev->device->name); 1934 pdata->hw_if.disable_rx_vlan_filtering(pdata); 1935 } 1936 } 1937 if (mask & ETH_VLAN_EXTEND_MASK) { 1938 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) { 1939 PMD_DRV_LOG(DEBUG, "enabling vlan extended mode\n"); 1940 axgbe_vlan_extend_enable(pdata); 1941 /* Set global registers with default ethertype*/ 1942 axgbe_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, 1943 RTE_ETHER_TYPE_VLAN); 1944 axgbe_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, 1945 RTE_ETHER_TYPE_VLAN); 1946 } else { 1947 PMD_DRV_LOG(DEBUG, "disabling vlan extended mode\n"); 1948 axgbe_vlan_extend_disable(pdata); 1949 } 1950 } 1951 return 0; 1952 } 1953 1954 static void axgbe_get_all_hw_features(struct axgbe_port *pdata) 1955 { 1956 unsigned int mac_hfr0, mac_hfr1, mac_hfr2, mac_hfr3; 1957 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 1958 1959 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R); 1960 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R); 1961 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R); 1962 mac_hfr3 = AXGMAC_IOREAD(pdata, MAC_HWF3R); 1963 1964 memset(hw_feat, 0, sizeof(*hw_feat)); 1965 1966 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR); 1967 1968 /* Hardware feature register 0 */ 1969 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 1970 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 1971 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 1972 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 1973 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 1974 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 1975 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 1976 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 1977 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 1978 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 1979 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 1980 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 1981 ADDMACADRSEL); 1982 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 1983 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 1984 1985 /* Hardware feature register 1 */ 1986 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1987 RXFIFOSIZE); 1988 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1989 TXFIFOSIZE); 1990 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1, 1991 MAC_HWF1R, ADVTHWORD); 1992 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 1993 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 1994 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 1995 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 1996 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 1997 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 1998 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 1999 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 2000 HASHTBLSZ); 2001 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 2002 L3L4FNUM); 2003 2004 /* Hardware feature register 2 */ 2005 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 2006 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 2007 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 2008 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 2009 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 2010 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, 2011 AUXSNAPNUM); 2012 2013 /* Hardware feature register 3 */ 2014 hw_feat->tx_q_vlan_tag_ins = AXGMAC_GET_BITS(mac_hfr3, 2015 MAC_HWF3R, CBTISEL); 2016 hw_feat->no_of_vlan_extn = AXGMAC_GET_BITS(mac_hfr3, 2017 MAC_HWF3R, NRVF); 2018 2019 /* Translate the Hash Table size into actual number */ 2020 switch (hw_feat->hash_table_size) { 2021 case 0: 2022 break; 2023 case 1: 2024 hw_feat->hash_table_size = 64; 2025 break; 2026 case 2: 2027 hw_feat->hash_table_size = 128; 2028 break; 2029 case 3: 2030 hw_feat->hash_table_size = 256; 2031 break; 2032 } 2033 2034 /* Translate the address width setting into actual number */ 2035 switch (hw_feat->dma_width) { 2036 case 0: 2037 hw_feat->dma_width = 32; 2038 break; 2039 case 1: 2040 hw_feat->dma_width = 40; 2041 break; 2042 case 2: 2043 hw_feat->dma_width = 48; 2044 break; 2045 default: 2046 hw_feat->dma_width = 32; 2047 } 2048 2049 /* The Queue, Channel and TC counts are zero based so increment them 2050 * to get the actual number 2051 */ 2052 hw_feat->rx_q_cnt++; 2053 hw_feat->tx_q_cnt++; 2054 hw_feat->rx_ch_cnt++; 2055 hw_feat->tx_ch_cnt++; 2056 hw_feat->tc_cnt++; 2057 2058 /* Translate the fifo sizes into actual numbers */ 2059 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 2060 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 2061 } 2062 2063 static void axgbe_init_all_fptrs(struct axgbe_port *pdata) 2064 { 2065 axgbe_init_function_ptrs_dev(&pdata->hw_if); 2066 axgbe_init_function_ptrs_phy(&pdata->phy_if); 2067 axgbe_init_function_ptrs_i2c(&pdata->i2c_if); 2068 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 2069 } 2070 2071 static void axgbe_set_counts(struct axgbe_port *pdata) 2072 { 2073 /* Set all the function pointers */ 2074 axgbe_init_all_fptrs(pdata); 2075 2076 /* Populate the hardware features */ 2077 axgbe_get_all_hw_features(pdata); 2078 2079 /* Set default max values if not provided */ 2080 if (!pdata->tx_max_channel_count) 2081 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 2082 if (!pdata->rx_max_channel_count) 2083 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 2084 2085 if (!pdata->tx_max_q_count) 2086 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 2087 if (!pdata->rx_max_q_count) 2088 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 2089 2090 /* Calculate the number of Tx and Rx rings to be created 2091 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 2092 * the number of Tx queues to the number of Tx channels 2093 * enabled 2094 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 2095 * number of Rx queues or maximum allowed 2096 */ 2097 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt, 2098 pdata->tx_max_channel_count); 2099 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count, 2100 pdata->tx_max_q_count); 2101 2102 pdata->tx_q_count = pdata->tx_ring_count; 2103 2104 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt, 2105 pdata->rx_max_channel_count); 2106 2107 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt, 2108 pdata->rx_max_q_count); 2109 } 2110 2111 static void axgbe_default_config(struct axgbe_port *pdata) 2112 { 2113 pdata->pblx8 = DMA_PBL_X8_ENABLE; 2114 pdata->tx_sf_mode = MTL_TSF_ENABLE; 2115 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 2116 pdata->tx_pbl = DMA_PBL_32; 2117 pdata->tx_osp_mode = DMA_OSP_ENABLE; 2118 pdata->rx_sf_mode = MTL_RSF_ENABLE; 2119 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 2120 pdata->rx_pbl = DMA_PBL_32; 2121 pdata->pause_autoneg = 1; 2122 pdata->tx_pause = 0; 2123 pdata->rx_pause = 0; 2124 pdata->phy_speed = SPEED_UNKNOWN; 2125 pdata->power_down = 0; 2126 } 2127 2128 static int 2129 pci_device_cmp(const struct rte_device *dev, const void *_pci_id) 2130 { 2131 const struct rte_pci_device *pdev = RTE_DEV_TO_PCI_CONST(dev); 2132 const struct rte_pci_id *pcid = _pci_id; 2133 2134 if (pdev->id.vendor_id == AMD_PCI_VENDOR_ID && 2135 pdev->id.device_id == pcid->device_id) 2136 return 0; 2137 return 1; 2138 } 2139 2140 static bool 2141 pci_search_device(int device_id) 2142 { 2143 struct rte_bus *pci_bus; 2144 struct rte_pci_id dev_id; 2145 2146 dev_id.device_id = device_id; 2147 pci_bus = rte_bus_find_by_name("pci"); 2148 return (pci_bus != NULL) && 2149 (pci_bus->find_device(NULL, pci_device_cmp, &dev_id) != NULL); 2150 } 2151 2152 /* 2153 * It returns 0 on success. 2154 */ 2155 static int 2156 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) 2157 { 2158 PMD_INIT_FUNC_TRACE(); 2159 struct axgbe_port *pdata; 2160 struct rte_pci_device *pci_dev; 2161 uint32_t reg, mac_lo, mac_hi; 2162 uint32_t len; 2163 int ret; 2164 2165 eth_dev->dev_ops = &axgbe_eth_dev_ops; 2166 2167 eth_dev->rx_descriptor_status = axgbe_dev_rx_descriptor_status; 2168 eth_dev->tx_descriptor_status = axgbe_dev_tx_descriptor_status; 2169 2170 /* 2171 * For secondary processes, we don't initialise any further as primary 2172 * has already done this work. 2173 */ 2174 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2175 return 0; 2176 2177 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2178 2179 pdata = eth_dev->data->dev_private; 2180 /* initial state */ 2181 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 2182 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 2183 pdata->eth_dev = eth_dev; 2184 2185 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2186 pdata->pci_dev = pci_dev; 2187 2188 /* 2189 * Use root complex device ID to differentiate RV AXGBE vs SNOWY AXGBE 2190 */ 2191 if (pci_search_device(AMD_PCI_RV_ROOT_COMPLEX_ID)) { 2192 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; 2193 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; 2194 } else { 2195 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 2196 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 2197 } 2198 2199 pdata->xgmac_regs = 2200 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; 2201 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs 2202 + AXGBE_MAC_PROP_OFFSET); 2203 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs 2204 + AXGBE_I2C_CTRL_OFFSET); 2205 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; 2206 2207 /* version specific driver data*/ 2208 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A) 2209 pdata->vdata = &axgbe_v2a; 2210 else 2211 pdata->vdata = &axgbe_v2b; 2212 2213 /* Configure the PCS indirect addressing support */ 2214 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); 2215 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 2216 pdata->xpcs_window <<= 6; 2217 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 2218 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 2219 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 2220 2221 PMD_INIT_LOG(DEBUG, 2222 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, 2223 pdata->xpcs_window_size, pdata->xpcs_window_mask); 2224 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 2225 2226 /* Retrieve the MAC address */ 2227 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 2228 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 2229 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff; 2230 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff; 2231 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff; 2232 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff; 2233 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff; 2234 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff; 2235 2236 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_MAC_ADDRS; 2237 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", len, 0); 2238 2239 if (!eth_dev->data->mac_addrs) { 2240 PMD_INIT_LOG(ERR, 2241 "Failed to alloc %u bytes needed to " 2242 "store MAC addresses", len); 2243 return -ENOMEM; 2244 } 2245 2246 /* Allocate memory for storing hash filter MAC addresses */ 2247 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS; 2248 eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr", 2249 len, 0); 2250 2251 if (eth_dev->data->hash_mac_addrs == NULL) { 2252 PMD_INIT_LOG(ERR, 2253 "Failed to allocate %d bytes needed to " 2254 "store MAC addresses", len); 2255 return -ENOMEM; 2256 } 2257 2258 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr)) 2259 rte_eth_random_addr(pdata->mac_addr.addr_bytes); 2260 2261 /* Copy the permanent MAC address */ 2262 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]); 2263 2264 /* Clock settings */ 2265 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ; 2266 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 2267 2268 /* Set the DMA coherency values */ 2269 pdata->coherent = 1; 2270 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN; 2271 pdata->arcache = AXGBE_DMA_OS_ARCACHE; 2272 pdata->awcache = AXGBE_DMA_OS_AWCACHE; 2273 2274 /* Set the maximum channels and queues */ 2275 reg = XP_IOREAD(pdata, XP_PROP_1); 2276 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA); 2277 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA); 2278 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES); 2279 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES); 2280 2281 /* Set the hardware channel and queue counts */ 2282 axgbe_set_counts(pdata); 2283 2284 /* Set the maximum fifo amounts */ 2285 reg = XP_IOREAD(pdata, XP_PROP_2); 2286 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE); 2287 pdata->tx_max_fifo_size *= 16384; 2288 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size, 2289 pdata->vdata->tx_max_fifo_size); 2290 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE); 2291 pdata->rx_max_fifo_size *= 16384; 2292 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size, 2293 pdata->vdata->rx_max_fifo_size); 2294 /* Issue software reset to DMA */ 2295 ret = pdata->hw_if.exit(pdata); 2296 if (ret) 2297 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n"); 2298 2299 /* Set default configuration data */ 2300 axgbe_default_config(pdata); 2301 2302 /* Set default max values if not provided */ 2303 if (!pdata->tx_max_fifo_size) 2304 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 2305 if (!pdata->rx_max_fifo_size) 2306 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 2307 2308 pdata->tx_desc_count = AXGBE_MAX_RING_DESC; 2309 pdata->rx_desc_count = AXGBE_MAX_RING_DESC; 2310 pthread_mutex_init(&pdata->xpcs_mutex, NULL); 2311 pthread_mutex_init(&pdata->i2c_mutex, NULL); 2312 pthread_mutex_init(&pdata->an_mutex, NULL); 2313 pthread_mutex_init(&pdata->phy_mutex, NULL); 2314 2315 ret = pdata->phy_if.phy_init(pdata); 2316 if (ret) { 2317 rte_free(eth_dev->data->mac_addrs); 2318 eth_dev->data->mac_addrs = NULL; 2319 return ret; 2320 } 2321 2322 rte_intr_callback_register(&pci_dev->intr_handle, 2323 axgbe_dev_interrupt_handler, 2324 (void *)eth_dev); 2325 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 2326 eth_dev->data->port_id, pci_dev->id.vendor_id, 2327 pci_dev->id.device_id); 2328 2329 return 0; 2330 } 2331 2332 static int 2333 axgbe_dev_close(struct rte_eth_dev *eth_dev) 2334 { 2335 struct rte_pci_device *pci_dev; 2336 2337 PMD_INIT_FUNC_TRACE(); 2338 2339 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2340 return 0; 2341 2342 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2343 axgbe_dev_clear_queues(eth_dev); 2344 2345 /* disable uio intr before callback unregister */ 2346 rte_intr_disable(&pci_dev->intr_handle); 2347 rte_intr_callback_unregister(&pci_dev->intr_handle, 2348 axgbe_dev_interrupt_handler, 2349 (void *)eth_dev); 2350 2351 return 0; 2352 } 2353 2354 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2355 struct rte_pci_device *pci_dev) 2356 { 2357 return rte_eth_dev_pci_generic_probe(pci_dev, 2358 sizeof(struct axgbe_port), eth_axgbe_dev_init); 2359 } 2360 2361 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev) 2362 { 2363 return rte_eth_dev_pci_generic_remove(pci_dev, axgbe_dev_close); 2364 } 2365 2366 static struct rte_pci_driver rte_axgbe_pmd = { 2367 .id_table = pci_id_axgbe_map, 2368 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2369 .probe = eth_axgbe_pci_probe, 2370 .remove = eth_axgbe_pci_remove, 2371 }; 2372 2373 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd); 2374 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map); 2375 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 2376 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_init, init, NOTICE); 2377 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_driver, driver, NOTICE); 2378