1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_rxtx.h" 7 #include "axgbe_ethdev.h" 8 #include "axgbe_common.h" 9 #include "axgbe_phy.h" 10 #include "axgbe_regs.h" 11 #include "rte_time.h" 12 13 #include "eal_filesystem.h" 14 15 #ifdef RTE_ARCH_X86 16 #include <cpuid.h> 17 #else 18 #define __cpuid(n, a, b, c, d) 19 #endif 20 21 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); 22 static int axgbe_dev_configure(struct rte_eth_dev *dev); 23 static int axgbe_dev_start(struct rte_eth_dev *dev); 24 static int axgbe_dev_stop(struct rte_eth_dev *dev); 25 static void axgbe_dev_interrupt_handler(void *param); 26 static int axgbe_dev_close(struct rte_eth_dev *dev); 27 static int axgbe_dev_reset(struct rte_eth_dev *dev); 28 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 29 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 30 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 31 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 32 static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, 33 struct rte_ether_addr *mac_addr); 34 static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, 35 struct rte_ether_addr *mac_addr, 36 uint32_t index, 37 uint32_t vmdq); 38 static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 39 static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 40 struct rte_ether_addr *mc_addr_set, 41 uint32_t nb_mc_addr); 42 static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 43 struct rte_ether_addr *mac_addr, 44 uint8_t add); 45 static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, 46 uint8_t add); 47 static int axgbe_dev_link_update(struct rte_eth_dev *dev, 48 int wait_to_complete); 49 static int axgbe_dev_get_regs(struct rte_eth_dev *dev, 50 struct rte_dev_reg_info *regs); 51 static int axgbe_dev_stats_get(struct rte_eth_dev *dev, 52 struct rte_eth_stats *stats); 53 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev); 54 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev, 55 struct rte_eth_xstat *stats, 56 unsigned int n); 57 static int 58 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 59 struct rte_eth_xstat_name *xstats_names, 60 unsigned int size); 61 static int 62 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 63 const uint64_t *ids, 64 uint64_t *values, 65 unsigned int n); 66 static int 67 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 68 const uint64_t *ids, 69 struct rte_eth_xstat_name *xstats_names, 70 unsigned int size); 71 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev); 72 static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 73 struct rte_eth_rss_reta_entry64 *reta_conf, 74 uint16_t reta_size); 75 static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 76 struct rte_eth_rss_reta_entry64 *reta_conf, 77 uint16_t reta_size); 78 static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 79 struct rte_eth_rss_conf *rss_conf); 80 static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 81 struct rte_eth_rss_conf *rss_conf); 82 static int axgbe_dev_info_get(struct rte_eth_dev *dev, 83 struct rte_eth_dev_info *dev_info); 84 static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, 85 struct rte_eth_fc_conf *fc_conf); 86 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, 87 struct rte_eth_fc_conf *fc_conf); 88 static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 89 struct rte_eth_pfc_conf *pfc_conf); 90 static void axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 91 struct rte_eth_rxq_info *qinfo); 92 static void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 93 struct rte_eth_txq_info *qinfo); 94 const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 95 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 96 97 static int 98 axgbe_timesync_enable(struct rte_eth_dev *dev); 99 static int 100 axgbe_timesync_disable(struct rte_eth_dev *dev); 101 static int 102 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 103 struct timespec *timestamp, uint32_t flags); 104 static int 105 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 106 struct timespec *timestamp); 107 static int 108 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 109 static int 110 axgbe_timesync_read_time(struct rte_eth_dev *dev, 111 struct timespec *timestamp); 112 static int 113 axgbe_timesync_write_time(struct rte_eth_dev *dev, 114 const struct timespec *timestamp); 115 static void 116 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 117 unsigned int nsec); 118 static void 119 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 120 unsigned int addend); 121 static int 122 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on); 123 static int axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 124 enum rte_vlan_type vlan_type, uint16_t tpid); 125 static int axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 126 127 struct axgbe_xstats { 128 char name[RTE_ETH_XSTATS_NAME_SIZE]; 129 int offset; 130 }; 131 132 #define AXGMAC_MMC_STAT(_string, _var) \ 133 { _string, \ 134 offsetof(struct axgbe_mmc_stats, _var), \ 135 } 136 137 static const struct axgbe_xstats axgbe_xstats_strings[] = { 138 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb), 139 AXGMAC_MMC_STAT("tx_packets", txframecount_gb), 140 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb), 141 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb), 142 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb), 143 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g), 144 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb), 145 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb), 146 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb), 147 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb), 148 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb), 149 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb), 150 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror), 151 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes), 152 153 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb), 154 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb), 155 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g), 156 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g), 157 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g), 158 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb), 159 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb), 160 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb), 161 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb), 162 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb), 163 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb), 164 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb), 165 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g), 166 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g), 167 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror), 168 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror), 169 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror), 170 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror), 171 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype), 172 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow), 173 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror), 174 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes), 175 }; 176 177 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings) 178 179 /* The set of PCI devices this driver supports */ 180 #define AMD_PCI_VENDOR_ID 0x1022 181 182 #define Fam17h 0x17 183 #define Fam19h 0x19 184 185 #define CPUID_VENDOR_AuthenticAMD_ebx 0x68747541 186 #define CPUID_VENDOR_AuthenticAMD_ecx 0x444d4163 187 #define CPUID_VENDOR_AuthenticAMD_edx 0x69746e65 188 189 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 190 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459 191 192 static const struct rte_pci_id pci_id_axgbe_map[] = { 193 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)}, 194 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)}, 195 { .vendor_id = 0, }, 196 }; 197 198 static struct axgbe_version_data axgbe_v2a = { 199 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 200 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 201 .mmc_64bit = 1, 202 .tx_max_fifo_size = 229376, 203 .rx_max_fifo_size = 229376, 204 .tx_tstamp_workaround = 1, 205 .ecc_support = 1, 206 .i2c_support = 1, 207 .an_cdr_workaround = 1, 208 }; 209 210 static struct axgbe_version_data axgbe_v2b = { 211 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 212 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 213 .mmc_64bit = 1, 214 .tx_max_fifo_size = 65536, 215 .rx_max_fifo_size = 65536, 216 .tx_tstamp_workaround = 1, 217 .ecc_support = 1, 218 .i2c_support = 1, 219 .an_cdr_workaround = 1, 220 }; 221 222 static const struct rte_eth_desc_lim rx_desc_lim = { 223 .nb_max = AXGBE_MAX_RING_DESC, 224 .nb_min = AXGBE_MIN_RING_DESC, 225 .nb_align = 8, 226 }; 227 228 static const struct rte_eth_desc_lim tx_desc_lim = { 229 .nb_max = AXGBE_MAX_RING_DESC, 230 .nb_min = AXGBE_MIN_RING_DESC, 231 .nb_align = 8, 232 }; 233 234 static const struct eth_dev_ops axgbe_eth_dev_ops = { 235 .dev_configure = axgbe_dev_configure, 236 .dev_start = axgbe_dev_start, 237 .dev_stop = axgbe_dev_stop, 238 .dev_close = axgbe_dev_close, 239 .dev_reset = axgbe_dev_reset, 240 .promiscuous_enable = axgbe_dev_promiscuous_enable, 241 .promiscuous_disable = axgbe_dev_promiscuous_disable, 242 .allmulticast_enable = axgbe_dev_allmulticast_enable, 243 .allmulticast_disable = axgbe_dev_allmulticast_disable, 244 .mac_addr_set = axgbe_dev_mac_addr_set, 245 .mac_addr_add = axgbe_dev_mac_addr_add, 246 .mac_addr_remove = axgbe_dev_mac_addr_remove, 247 .set_mc_addr_list = axgbe_dev_set_mc_addr_list, 248 .uc_hash_table_set = axgbe_dev_uc_hash_table_set, 249 .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set, 250 .link_update = axgbe_dev_link_update, 251 .get_reg = axgbe_dev_get_regs, 252 .stats_get = axgbe_dev_stats_get, 253 .stats_reset = axgbe_dev_stats_reset, 254 .xstats_get = axgbe_dev_xstats_get, 255 .xstats_reset = axgbe_dev_xstats_reset, 256 .xstats_get_names = axgbe_dev_xstats_get_names, 257 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id, 258 .xstats_get_by_id = axgbe_dev_xstats_get_by_id, 259 .reta_update = axgbe_dev_rss_reta_update, 260 .reta_query = axgbe_dev_rss_reta_query, 261 .rss_hash_update = axgbe_dev_rss_hash_update, 262 .rss_hash_conf_get = axgbe_dev_rss_hash_conf_get, 263 .dev_infos_get = axgbe_dev_info_get, 264 .rx_queue_setup = axgbe_dev_rx_queue_setup, 265 .rx_queue_release = axgbe_dev_rx_queue_release, 266 .tx_queue_setup = axgbe_dev_tx_queue_setup, 267 .tx_queue_release = axgbe_dev_tx_queue_release, 268 .flow_ctrl_get = axgbe_flow_ctrl_get, 269 .flow_ctrl_set = axgbe_flow_ctrl_set, 270 .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set, 271 .rxq_info_get = axgbe_rxq_info_get, 272 .txq_info_get = axgbe_txq_info_get, 273 .dev_supported_ptypes_get = axgbe_dev_supported_ptypes_get, 274 .mtu_set = axgb_mtu_set, 275 .vlan_filter_set = axgbe_vlan_filter_set, 276 .vlan_tpid_set = axgbe_vlan_tpid_set, 277 .vlan_offload_set = axgbe_vlan_offload_set, 278 .timesync_enable = axgbe_timesync_enable, 279 .timesync_disable = axgbe_timesync_disable, 280 .timesync_read_rx_timestamp = axgbe_timesync_read_rx_timestamp, 281 .timesync_read_tx_timestamp = axgbe_timesync_read_tx_timestamp, 282 .timesync_adjust_time = axgbe_timesync_adjust_time, 283 .timesync_read_time = axgbe_timesync_read_time, 284 .timesync_write_time = axgbe_timesync_write_time, 285 .fw_version_get = axgbe_dev_fw_version_get, 286 }; 287 288 static int axgbe_phy_reset(struct axgbe_port *pdata) 289 { 290 pdata->phy_link = -1; 291 pdata->phy_speed = SPEED_UNKNOWN; 292 return pdata->phy_if.phy_reset(pdata); 293 } 294 295 /* 296 * Interrupt handler triggered by NIC for handling 297 * specific interrupt. 298 * 299 * @param handle 300 * Pointer to interrupt handle. 301 * @param param 302 * The address of parameter (struct rte_eth_dev *) registered before. 303 * 304 * @return 305 * void 306 */ 307 static void 308 axgbe_dev_interrupt_handler(void *param) 309 { 310 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 311 struct axgbe_port *pdata = dev->data->dev_private; 312 unsigned int dma_isr, dma_ch_isr; 313 314 pdata->phy_if.an_isr(pdata); 315 /*DMA related interrupts*/ 316 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR); 317 PMD_DRV_LOG(DEBUG, "DMA_ISR=%#010x\n", dma_isr); 318 if (dma_isr) { 319 if (dma_isr & 1) { 320 dma_ch_isr = 321 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *) 322 pdata->rx_queues[0], 323 DMA_CH_SR); 324 PMD_DRV_LOG(DEBUG, "DMA_CH0_ISR=%#010x\n", dma_ch_isr); 325 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *) 326 pdata->rx_queues[0], 327 DMA_CH_SR, dma_ch_isr); 328 } 329 } 330 /* Unmask interrupts since disabled after generation */ 331 rte_intr_ack(pdata->pci_dev->intr_handle); 332 } 333 334 /* 335 * Configure device link speed and setup link. 336 * It returns 0 on success. 337 */ 338 static int 339 axgbe_dev_configure(struct rte_eth_dev *dev) 340 { 341 struct axgbe_port *pdata = dev->data->dev_private; 342 /* Checksum offload to hardware */ 343 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads & 344 RTE_ETH_RX_OFFLOAD_CHECKSUM; 345 return 0; 346 } 347 348 static int 349 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev) 350 { 351 struct axgbe_port *pdata = dev->data->dev_private; 352 353 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) 354 pdata->rss_enable = 1; 355 else if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_NONE) 356 pdata->rss_enable = 0; 357 else 358 return -1; 359 return 0; 360 } 361 362 static int 363 axgbe_dev_start(struct rte_eth_dev *dev) 364 { 365 struct axgbe_port *pdata = dev->data->dev_private; 366 uint16_t i; 367 int ret; 368 369 dev->dev_ops = &axgbe_eth_dev_ops; 370 371 PMD_INIT_FUNC_TRACE(); 372 373 /* Multiqueue RSS */ 374 ret = axgbe_dev_rx_mq_config(dev); 375 if (ret) { 376 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n"); 377 return ret; 378 } 379 ret = axgbe_phy_reset(pdata); 380 if (ret) { 381 PMD_DRV_LOG(ERR, "phy reset failed\n"); 382 return ret; 383 } 384 ret = pdata->hw_if.init(pdata); 385 if (ret) { 386 PMD_DRV_LOG(ERR, "dev_init failed\n"); 387 return ret; 388 } 389 390 /* enable uio/vfio intr/eventfd mapping */ 391 rte_intr_enable(pdata->pci_dev->intr_handle); 392 393 /* phy start*/ 394 pdata->phy_if.phy_start(pdata); 395 axgbe_dev_enable_tx(dev); 396 axgbe_dev_enable_rx(dev); 397 398 rte_bit_relaxed_clear32(AXGBE_STOPPED, &pdata->dev_state); 399 rte_bit_relaxed_clear32(AXGBE_DOWN, &pdata->dev_state); 400 401 axgbe_set_rx_function(dev); 402 axgbe_set_tx_function(dev); 403 404 for (i = 0; i < dev->data->nb_rx_queues; i++) 405 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 406 for (i = 0; i < dev->data->nb_tx_queues; i++) 407 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 408 409 return 0; 410 } 411 412 /* Stop device: disable rx and tx functions to allow for reconfiguring. */ 413 static int 414 axgbe_dev_stop(struct rte_eth_dev *dev) 415 { 416 struct axgbe_port *pdata = dev->data->dev_private; 417 418 PMD_INIT_FUNC_TRACE(); 419 420 rte_intr_disable(pdata->pci_dev->intr_handle); 421 422 if (rte_bit_relaxed_get32(AXGBE_STOPPED, &pdata->dev_state)) 423 return 0; 424 425 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 426 axgbe_dev_disable_tx(dev); 427 axgbe_dev_disable_rx(dev); 428 429 pdata->phy_if.phy_stop(pdata); 430 pdata->hw_if.exit(pdata); 431 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); 432 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 433 434 return 0; 435 } 436 437 static int 438 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 439 { 440 struct axgbe_port *pdata = dev->data->dev_private; 441 442 PMD_INIT_FUNC_TRACE(); 443 444 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); 445 446 return 0; 447 } 448 449 static int 450 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 451 { 452 struct axgbe_port *pdata = dev->data->dev_private; 453 454 PMD_INIT_FUNC_TRACE(); 455 456 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); 457 458 return 0; 459 } 460 461 static int 462 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 463 { 464 struct axgbe_port *pdata = dev->data->dev_private; 465 466 PMD_INIT_FUNC_TRACE(); 467 468 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 469 return 0; 470 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1); 471 472 return 0; 473 } 474 475 static int 476 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 477 { 478 struct axgbe_port *pdata = dev->data->dev_private; 479 480 PMD_INIT_FUNC_TRACE(); 481 482 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 483 return 0; 484 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0); 485 486 return 0; 487 } 488 489 static int 490 axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 491 { 492 struct axgbe_port *pdata = dev->data->dev_private; 493 494 /* Set Default MAC Addr */ 495 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0); 496 497 return 0; 498 } 499 500 static int 501 axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 502 uint32_t index, uint32_t pool __rte_unused) 503 { 504 struct axgbe_port *pdata = dev->data->dev_private; 505 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 506 507 if (index > hw_feat->addn_mac) { 508 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index); 509 return -EINVAL; 510 } 511 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index); 512 return 0; 513 } 514 515 static int 516 axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 517 struct rte_eth_rss_reta_entry64 *reta_conf, 518 uint16_t reta_size) 519 { 520 struct axgbe_port *pdata = dev->data->dev_private; 521 unsigned int i, idx, shift; 522 int ret; 523 524 if (!pdata->rss_enable) { 525 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 526 return -ENOTSUP; 527 } 528 529 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 530 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size); 531 return -EINVAL; 532 } 533 534 for (i = 0; i < reta_size; i++) { 535 idx = i / RTE_ETH_RETA_GROUP_SIZE; 536 shift = i % RTE_ETH_RETA_GROUP_SIZE; 537 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 538 continue; 539 pdata->rss_table[i] = reta_conf[idx].reta[shift]; 540 } 541 542 /* Program the lookup table */ 543 ret = axgbe_write_rss_lookup_table(pdata); 544 return ret; 545 } 546 547 static int 548 axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 549 struct rte_eth_rss_reta_entry64 *reta_conf, 550 uint16_t reta_size) 551 { 552 struct axgbe_port *pdata = dev->data->dev_private; 553 unsigned int i, idx, shift; 554 555 if (!pdata->rss_enable) { 556 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 557 return -ENOTSUP; 558 } 559 560 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 561 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size); 562 return -EINVAL; 563 } 564 565 for (i = 0; i < reta_size; i++) { 566 idx = i / RTE_ETH_RETA_GROUP_SIZE; 567 shift = i % RTE_ETH_RETA_GROUP_SIZE; 568 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 569 continue; 570 reta_conf[idx].reta[shift] = pdata->rss_table[i]; 571 } 572 return 0; 573 } 574 575 static int 576 axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 577 struct rte_eth_rss_conf *rss_conf) 578 { 579 struct axgbe_port *pdata = dev->data->dev_private; 580 int ret; 581 582 if (!pdata->rss_enable) { 583 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 584 return -ENOTSUP; 585 } 586 587 if (rss_conf == NULL) { 588 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n"); 589 return -EINVAL; 590 } 591 592 if (rss_conf->rss_key != NULL && 593 rss_conf->rss_key_len == AXGBE_RSS_HASH_KEY_SIZE) { 594 rte_memcpy(pdata->rss_key, rss_conf->rss_key, 595 AXGBE_RSS_HASH_KEY_SIZE); 596 /* Program the hash key */ 597 ret = axgbe_write_rss_hash_key(pdata); 598 if (ret != 0) 599 return ret; 600 } 601 602 pdata->rss_hf = rss_conf->rss_hf & AXGBE_RSS_OFFLOAD; 603 604 if (pdata->rss_hf & (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6)) 605 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); 606 if (pdata->rss_hf & 607 (RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV6_TCP)) 608 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); 609 if (pdata->rss_hf & 610 (RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV6_UDP)) 611 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); 612 613 /* Set the RSS options */ 614 AXGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 615 616 return 0; 617 } 618 619 static int 620 axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 621 struct rte_eth_rss_conf *rss_conf) 622 { 623 struct axgbe_port *pdata = dev->data->dev_private; 624 625 if (!pdata->rss_enable) { 626 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 627 return -ENOTSUP; 628 } 629 630 if (rss_conf == NULL) { 631 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n"); 632 return -EINVAL; 633 } 634 635 if (rss_conf->rss_key != NULL && 636 rss_conf->rss_key_len >= AXGBE_RSS_HASH_KEY_SIZE) { 637 rte_memcpy(rss_conf->rss_key, pdata->rss_key, 638 AXGBE_RSS_HASH_KEY_SIZE); 639 } 640 rss_conf->rss_key_len = AXGBE_RSS_HASH_KEY_SIZE; 641 rss_conf->rss_hf = pdata->rss_hf; 642 return 0; 643 } 644 645 static int 646 axgbe_dev_reset(struct rte_eth_dev *dev) 647 { 648 int ret = 0; 649 650 ret = axgbe_dev_close(dev); 651 if (ret) 652 return ret; 653 654 ret = eth_axgbe_dev_init(dev); 655 656 return ret; 657 } 658 659 static void 660 axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 661 { 662 struct axgbe_port *pdata = dev->data->dev_private; 663 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 664 665 if (index > hw_feat->addn_mac) { 666 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index); 667 return; 668 } 669 axgbe_set_mac_addn_addr(pdata, NULL, index); 670 } 671 672 static int 673 axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 674 struct rte_ether_addr *mc_addr_set, 675 uint32_t nb_mc_addr) 676 { 677 struct axgbe_port *pdata = dev->data->dev_private; 678 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 679 uint32_t index = 1; /* 0 is always default mac */ 680 uint32_t i; 681 682 if (nb_mc_addr > hw_feat->addn_mac) { 683 PMD_DRV_LOG(ERR, "Invalid Index %d\n", nb_mc_addr); 684 return -EINVAL; 685 } 686 687 /* clear unicast addresses */ 688 for (i = 1; i < hw_feat->addn_mac; i++) { 689 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i])) 690 continue; 691 memset(&dev->data->mac_addrs[i], 0, 692 sizeof(struct rte_ether_addr)); 693 } 694 695 while (nb_mc_addr--) 696 axgbe_set_mac_addn_addr(pdata, (u8 *)mc_addr_set++, index++); 697 698 return 0; 699 } 700 701 static int 702 axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 703 struct rte_ether_addr *mac_addr, uint8_t add) 704 { 705 struct axgbe_port *pdata = dev->data->dev_private; 706 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 707 708 if (!hw_feat->hash_table_size) { 709 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); 710 return -ENOTSUP; 711 } 712 713 axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add); 714 715 if (pdata->uc_hash_mac_addr > 0) { 716 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 717 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 718 } else { 719 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 720 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 721 } 722 return 0; 723 } 724 725 static int 726 axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add) 727 { 728 struct axgbe_port *pdata = dev->data->dev_private; 729 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 730 uint32_t index; 731 732 if (!hw_feat->hash_table_size) { 733 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); 734 return -ENOTSUP; 735 } 736 737 for (index = 0; index < pdata->hash_table_count; index++) { 738 if (add) 739 pdata->uc_hash_table[index] = ~0; 740 else 741 pdata->uc_hash_table[index] = 0; 742 743 PMD_DRV_LOG(DEBUG, "%s MAC hash table at Index %#x\n", 744 add ? "set" : "clear", index); 745 746 AXGMAC_IOWRITE(pdata, MAC_HTR(index), 747 pdata->uc_hash_table[index]); 748 } 749 750 if (add) { 751 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 752 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 753 } else { 754 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 755 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 756 } 757 return 0; 758 } 759 760 /* return 0 means link status changed, -1 means not changed */ 761 static int 762 axgbe_dev_link_update(struct rte_eth_dev *dev, 763 int wait_to_complete __rte_unused) 764 { 765 struct axgbe_port *pdata = dev->data->dev_private; 766 struct rte_eth_link link; 767 int ret = 0; 768 769 PMD_INIT_FUNC_TRACE(); 770 rte_delay_ms(800); 771 772 pdata->phy_if.phy_status(pdata); 773 774 memset(&link, 0, sizeof(struct rte_eth_link)); 775 link.link_duplex = pdata->phy.duplex; 776 link.link_status = pdata->phy_link; 777 link.link_speed = pdata->phy_speed; 778 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 779 RTE_ETH_LINK_SPEED_FIXED); 780 ret = rte_eth_linkstatus_set(dev, &link); 781 if (ret == -1) 782 PMD_DRV_LOG(ERR, "No change in link status\n"); 783 784 return ret; 785 } 786 787 static int 788 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 789 { 790 struct axgbe_port *pdata = dev->data->dev_private; 791 792 if (regs->data == NULL) { 793 regs->length = axgbe_regs_get_count(pdata); 794 regs->width = sizeof(uint32_t); 795 return 0; 796 } 797 798 /* Only full register dump is supported */ 799 if (regs->length && 800 regs->length != (uint32_t)axgbe_regs_get_count(pdata)) 801 return -ENOTSUP; 802 803 regs->version = pdata->pci_dev->id.vendor_id << 16 | 804 pdata->pci_dev->id.device_id; 805 axgbe_regs_dump(pdata, regs->data); 806 return 0; 807 } 808 static void axgbe_read_mmc_stats(struct axgbe_port *pdata) 809 { 810 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 811 812 /* Freeze counters */ 813 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 814 815 /* Tx counters */ 816 stats->txoctetcount_gb += 817 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO); 818 stats->txoctetcount_gb += 819 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32); 820 821 stats->txframecount_gb += 822 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO); 823 stats->txframecount_gb += 824 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32); 825 826 stats->txbroadcastframes_g += 827 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO); 828 stats->txbroadcastframes_g += 829 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32); 830 831 stats->txmulticastframes_g += 832 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO); 833 stats->txmulticastframes_g += 834 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32); 835 836 stats->tx64octets_gb += 837 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO); 838 stats->tx64octets_gb += 839 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32); 840 841 stats->tx65to127octets_gb += 842 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO); 843 stats->tx65to127octets_gb += 844 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32); 845 846 stats->tx128to255octets_gb += 847 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO); 848 stats->tx128to255octets_gb += 849 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32); 850 851 stats->tx256to511octets_gb += 852 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO); 853 stats->tx256to511octets_gb += 854 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32); 855 856 stats->tx512to1023octets_gb += 857 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO); 858 stats->tx512to1023octets_gb += 859 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32); 860 861 stats->tx1024tomaxoctets_gb += 862 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 863 stats->tx1024tomaxoctets_gb += 864 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32); 865 866 stats->txunicastframes_gb += 867 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO); 868 stats->txunicastframes_gb += 869 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32); 870 871 stats->txmulticastframes_gb += 872 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 873 stats->txmulticastframes_gb += 874 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32); 875 876 stats->txbroadcastframes_g += 877 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 878 stats->txbroadcastframes_g += 879 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32); 880 881 stats->txunderflowerror += 882 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO); 883 stats->txunderflowerror += 884 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32); 885 886 stats->txoctetcount_g += 887 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO); 888 stats->txoctetcount_g += 889 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32); 890 891 stats->txframecount_g += 892 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO); 893 stats->txframecount_g += 894 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32); 895 896 stats->txpauseframes += 897 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO); 898 stats->txpauseframes += 899 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32); 900 901 stats->txvlanframes_g += 902 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO); 903 stats->txvlanframes_g += 904 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32); 905 906 /* Rx counters */ 907 stats->rxframecount_gb += 908 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO); 909 stats->rxframecount_gb += 910 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32); 911 912 stats->rxoctetcount_gb += 913 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO); 914 stats->rxoctetcount_gb += 915 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32); 916 917 stats->rxoctetcount_g += 918 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO); 919 stats->rxoctetcount_g += 920 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32); 921 922 stats->rxbroadcastframes_g += 923 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO); 924 stats->rxbroadcastframes_g += 925 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32); 926 927 stats->rxmulticastframes_g += 928 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO); 929 stats->rxmulticastframes_g += 930 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32); 931 932 stats->rxcrcerror += 933 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO); 934 stats->rxcrcerror += 935 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32); 936 937 stats->rxrunterror += 938 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR); 939 940 stats->rxjabbererror += 941 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR); 942 943 stats->rxundersize_g += 944 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G); 945 946 stats->rxoversize_g += 947 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G); 948 949 stats->rx64octets_gb += 950 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO); 951 stats->rx64octets_gb += 952 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32); 953 954 stats->rx65to127octets_gb += 955 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO); 956 stats->rx65to127octets_gb += 957 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32); 958 959 stats->rx128to255octets_gb += 960 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO); 961 stats->rx128to255octets_gb += 962 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32); 963 964 stats->rx256to511octets_gb += 965 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO); 966 stats->rx256to511octets_gb += 967 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32); 968 969 stats->rx512to1023octets_gb += 970 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO); 971 stats->rx512to1023octets_gb += 972 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32); 973 974 stats->rx1024tomaxoctets_gb += 975 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 976 stats->rx1024tomaxoctets_gb += 977 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32); 978 979 stats->rxunicastframes_g += 980 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO); 981 stats->rxunicastframes_g += 982 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32); 983 984 stats->rxlengtherror += 985 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO); 986 stats->rxlengtherror += 987 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32); 988 989 stats->rxoutofrangetype += 990 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO); 991 stats->rxoutofrangetype += 992 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32); 993 994 stats->rxpauseframes += 995 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO); 996 stats->rxpauseframes += 997 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32); 998 999 stats->rxfifooverflow += 1000 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO); 1001 stats->rxfifooverflow += 1002 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32); 1003 1004 stats->rxvlanframes_gb += 1005 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO); 1006 stats->rxvlanframes_gb += 1007 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32); 1008 1009 stats->rxwatchdogerror += 1010 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR); 1011 1012 /* Un-freeze counters */ 1013 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 1014 } 1015 1016 static int 1017 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1018 unsigned int n) 1019 { 1020 struct axgbe_port *pdata = dev->data->dev_private; 1021 unsigned int i; 1022 1023 if (n < AXGBE_XSTATS_COUNT) 1024 return AXGBE_XSTATS_COUNT; 1025 1026 axgbe_read_mmc_stats(pdata); 1027 1028 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1029 stats[i].id = i; 1030 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1031 axgbe_xstats_strings[i].offset); 1032 } 1033 1034 return AXGBE_XSTATS_COUNT; 1035 } 1036 1037 static int 1038 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1039 struct rte_eth_xstat_name *xstats_names, 1040 unsigned int n) 1041 { 1042 unsigned int i; 1043 1044 if (n >= AXGBE_XSTATS_COUNT && xstats_names) { 1045 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) { 1046 snprintf(xstats_names[i].name, 1047 RTE_ETH_XSTATS_NAME_SIZE, "%s", 1048 axgbe_xstats_strings[i].name); 1049 } 1050 } 1051 1052 return AXGBE_XSTATS_COUNT; 1053 } 1054 1055 static int 1056 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1057 uint64_t *values, unsigned int n) 1058 { 1059 unsigned int i; 1060 uint64_t values_copy[AXGBE_XSTATS_COUNT]; 1061 1062 if (!ids) { 1063 struct axgbe_port *pdata = dev->data->dev_private; 1064 1065 if (n < AXGBE_XSTATS_COUNT) 1066 return AXGBE_XSTATS_COUNT; 1067 1068 axgbe_read_mmc_stats(pdata); 1069 1070 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1071 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1072 axgbe_xstats_strings[i].offset); 1073 } 1074 1075 return i; 1076 } 1077 1078 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT); 1079 1080 for (i = 0; i < n; i++) { 1081 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1082 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 1083 return -1; 1084 } 1085 values[i] = values_copy[ids[i]]; 1086 } 1087 return n; 1088 } 1089 1090 static int 1091 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 1092 const uint64_t *ids, 1093 struct rte_eth_xstat_name *xstats_names, 1094 unsigned int size) 1095 { 1096 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT]; 1097 unsigned int i; 1098 1099 if (!ids) 1100 return axgbe_dev_xstats_get_names(dev, xstats_names, size); 1101 1102 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size); 1103 1104 for (i = 0; i < size; i++) { 1105 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1106 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 1107 return -1; 1108 } 1109 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1110 } 1111 return size; 1112 } 1113 1114 static int 1115 axgbe_dev_xstats_reset(struct rte_eth_dev *dev) 1116 { 1117 struct axgbe_port *pdata = dev->data->dev_private; 1118 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 1119 1120 /* MMC registers are configured for reset on read */ 1121 axgbe_read_mmc_stats(pdata); 1122 1123 /* Reset stats */ 1124 memset(stats, 0, sizeof(*stats)); 1125 1126 return 0; 1127 } 1128 1129 static int 1130 axgbe_dev_stats_get(struct rte_eth_dev *dev, 1131 struct rte_eth_stats *stats) 1132 { 1133 struct axgbe_rx_queue *rxq; 1134 struct axgbe_tx_queue *txq; 1135 struct axgbe_port *pdata = dev->data->dev_private; 1136 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats; 1137 unsigned int i; 1138 1139 axgbe_read_mmc_stats(pdata); 1140 1141 stats->imissed = mmc_stats->rxfifooverflow; 1142 1143 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1144 rxq = dev->data->rx_queues[i]; 1145 if (rxq) { 1146 stats->q_ipackets[i] = rxq->pkts; 1147 stats->ipackets += rxq->pkts; 1148 stats->q_ibytes[i] = rxq->bytes; 1149 stats->ibytes += rxq->bytes; 1150 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed; 1151 stats->q_errors[i] = rxq->errors 1152 + rxq->rx_mbuf_alloc_failed; 1153 stats->ierrors += rxq->errors; 1154 } else { 1155 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n", 1156 dev->data->port_id); 1157 } 1158 } 1159 1160 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1161 txq = dev->data->tx_queues[i]; 1162 if (txq) { 1163 stats->q_opackets[i] = txq->pkts; 1164 stats->opackets += txq->pkts; 1165 stats->q_obytes[i] = txq->bytes; 1166 stats->obytes += txq->bytes; 1167 stats->oerrors += txq->errors; 1168 } else { 1169 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n", 1170 dev->data->port_id); 1171 } 1172 } 1173 1174 return 0; 1175 } 1176 1177 static int 1178 axgbe_dev_stats_reset(struct rte_eth_dev *dev) 1179 { 1180 struct axgbe_rx_queue *rxq; 1181 struct axgbe_tx_queue *txq; 1182 unsigned int i; 1183 1184 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1185 rxq = dev->data->rx_queues[i]; 1186 if (rxq) { 1187 rxq->pkts = 0; 1188 rxq->bytes = 0; 1189 rxq->errors = 0; 1190 rxq->rx_mbuf_alloc_failed = 0; 1191 } else { 1192 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n", 1193 dev->data->port_id); 1194 } 1195 } 1196 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1197 txq = dev->data->tx_queues[i]; 1198 if (txq) { 1199 txq->pkts = 0; 1200 txq->bytes = 0; 1201 txq->errors = 0; 1202 } else { 1203 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n", 1204 dev->data->port_id); 1205 } 1206 } 1207 1208 return 0; 1209 } 1210 1211 static int 1212 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1213 { 1214 struct axgbe_port *pdata = dev->data->dev_private; 1215 1216 dev_info->max_rx_queues = pdata->rx_ring_count; 1217 dev_info->max_tx_queues = pdata->tx_ring_count; 1218 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE; 1219 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE; 1220 dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1; 1221 dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size; 1222 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10G; 1223 1224 dev_info->rx_offload_capa = 1225 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 1226 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 1227 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | 1228 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 1229 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 1230 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 1231 RTE_ETH_RX_OFFLOAD_SCATTER | 1232 RTE_ETH_RX_OFFLOAD_KEEP_CRC; 1233 1234 dev_info->tx_offload_capa = 1235 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 1236 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | 1237 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 1238 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | 1239 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 1240 RTE_ETH_TX_OFFLOAD_TCP_CKSUM; 1241 1242 if (pdata->hw_feat.rss) { 1243 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD; 1244 dev_info->reta_size = pdata->hw_feat.hash_table_size; 1245 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE; 1246 } 1247 1248 dev_info->rx_desc_lim = rx_desc_lim; 1249 dev_info->tx_desc_lim = tx_desc_lim; 1250 1251 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1252 .rx_free_thresh = AXGBE_RX_FREE_THRESH, 1253 }; 1254 1255 dev_info->default_txconf = (struct rte_eth_txconf) { 1256 .tx_free_thresh = AXGBE_TX_FREE_THRESH, 1257 }; 1258 1259 return 0; 1260 } 1261 1262 static int 1263 axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1264 { 1265 struct axgbe_port *pdata = dev->data->dev_private; 1266 struct xgbe_fc_info fc = pdata->fc; 1267 unsigned int reg, reg_val = 0; 1268 1269 reg = MAC_Q0TFCR; 1270 reg_val = AXGMAC_IOREAD(pdata, reg); 1271 fc.low_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA); 1272 fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD); 1273 fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT); 1274 fc.autoneg = pdata->pause_autoneg; 1275 1276 if (pdata->rx_pause && pdata->tx_pause) 1277 fc.mode = RTE_ETH_FC_FULL; 1278 else if (pdata->rx_pause) 1279 fc.mode = RTE_ETH_FC_RX_PAUSE; 1280 else if (pdata->tx_pause) 1281 fc.mode = RTE_ETH_FC_TX_PAUSE; 1282 else 1283 fc.mode = RTE_ETH_FC_NONE; 1284 1285 fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024; 1286 fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024; 1287 fc_conf->pause_time = fc.pause_time[0]; 1288 fc_conf->send_xon = fc.send_xon; 1289 fc_conf->mode = fc.mode; 1290 1291 return 0; 1292 } 1293 1294 static int 1295 axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1296 { 1297 struct axgbe_port *pdata = dev->data->dev_private; 1298 struct xgbe_fc_info fc = pdata->fc; 1299 unsigned int reg, reg_val = 0; 1300 reg = MAC_Q0TFCR; 1301 1302 pdata->pause_autoneg = fc_conf->autoneg; 1303 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1304 fc.send_xon = fc_conf->send_xon; 1305 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA, 1306 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water)); 1307 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD, 1308 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water)); 1309 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time); 1310 AXGMAC_IOWRITE(pdata, reg, reg_val); 1311 fc.mode = fc_conf->mode; 1312 1313 if (fc.mode == RTE_ETH_FC_FULL) { 1314 pdata->tx_pause = 1; 1315 pdata->rx_pause = 1; 1316 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) { 1317 pdata->tx_pause = 0; 1318 pdata->rx_pause = 1; 1319 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) { 1320 pdata->tx_pause = 1; 1321 pdata->rx_pause = 0; 1322 } else { 1323 pdata->tx_pause = 0; 1324 pdata->rx_pause = 0; 1325 } 1326 1327 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1328 pdata->hw_if.config_tx_flow_control(pdata); 1329 1330 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1331 pdata->hw_if.config_rx_flow_control(pdata); 1332 1333 pdata->hw_if.config_flow_control(pdata); 1334 pdata->phy.tx_pause = pdata->tx_pause; 1335 pdata->phy.rx_pause = pdata->rx_pause; 1336 1337 return 0; 1338 } 1339 1340 static int 1341 axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 1342 struct rte_eth_pfc_conf *pfc_conf) 1343 { 1344 struct axgbe_port *pdata = dev->data->dev_private; 1345 struct xgbe_fc_info fc = pdata->fc; 1346 uint8_t tc_num; 1347 1348 tc_num = pdata->pfc_map[pfc_conf->priority]; 1349 1350 if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) { 1351 PMD_INIT_LOG(ERR, "Max supported traffic class: %d\n", 1352 pdata->hw_feat.tc_cnt); 1353 return -EINVAL; 1354 } 1355 1356 pdata->pause_autoneg = pfc_conf->fc.autoneg; 1357 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1358 fc.send_xon = pfc_conf->fc.send_xon; 1359 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA, 1360 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water)); 1361 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD, 1362 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water)); 1363 1364 switch (tc_num) { 1365 case 0: 1366 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1367 PSTC0, pfc_conf->fc.pause_time); 1368 break; 1369 case 1: 1370 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1371 PSTC1, pfc_conf->fc.pause_time); 1372 break; 1373 case 2: 1374 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1375 PSTC2, pfc_conf->fc.pause_time); 1376 break; 1377 case 3: 1378 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1379 PSTC3, pfc_conf->fc.pause_time); 1380 break; 1381 case 4: 1382 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1383 PSTC4, pfc_conf->fc.pause_time); 1384 break; 1385 case 5: 1386 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1387 PSTC5, pfc_conf->fc.pause_time); 1388 break; 1389 case 7: 1390 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1391 PSTC6, pfc_conf->fc.pause_time); 1392 break; 1393 case 6: 1394 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1395 PSTC7, pfc_conf->fc.pause_time); 1396 break; 1397 } 1398 1399 fc.mode = pfc_conf->fc.mode; 1400 1401 if (fc.mode == RTE_ETH_FC_FULL) { 1402 pdata->tx_pause = 1; 1403 pdata->rx_pause = 1; 1404 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1405 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) { 1406 pdata->tx_pause = 0; 1407 pdata->rx_pause = 1; 1408 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1409 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) { 1410 pdata->tx_pause = 1; 1411 pdata->rx_pause = 0; 1412 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1413 } else { 1414 pdata->tx_pause = 0; 1415 pdata->rx_pause = 0; 1416 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1417 } 1418 1419 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1420 pdata->hw_if.config_tx_flow_control(pdata); 1421 1422 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1423 pdata->hw_if.config_rx_flow_control(pdata); 1424 pdata->hw_if.config_flow_control(pdata); 1425 pdata->phy.tx_pause = pdata->tx_pause; 1426 pdata->phy.rx_pause = pdata->rx_pause; 1427 1428 return 0; 1429 } 1430 1431 void 1432 axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1433 struct rte_eth_rxq_info *qinfo) 1434 { 1435 struct axgbe_rx_queue *rxq; 1436 1437 rxq = dev->data->rx_queues[queue_id]; 1438 qinfo->mp = rxq->mb_pool; 1439 qinfo->scattered_rx = dev->data->scattered_rx; 1440 qinfo->nb_desc = rxq->nb_desc; 1441 qinfo->conf.rx_free_thresh = rxq->free_thresh; 1442 } 1443 1444 void 1445 axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1446 struct rte_eth_txq_info *qinfo) 1447 { 1448 struct axgbe_tx_queue *txq; 1449 1450 txq = dev->data->tx_queues[queue_id]; 1451 qinfo->nb_desc = txq->nb_desc; 1452 qinfo->conf.tx_free_thresh = txq->free_thresh; 1453 } 1454 const uint32_t * 1455 axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1456 { 1457 static const uint32_t ptypes[] = { 1458 RTE_PTYPE_L2_ETHER, 1459 RTE_PTYPE_L2_ETHER_TIMESYNC, 1460 RTE_PTYPE_L2_ETHER_LLDP, 1461 RTE_PTYPE_L2_ETHER_ARP, 1462 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1463 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 1464 RTE_PTYPE_L4_FRAG, 1465 RTE_PTYPE_L4_ICMP, 1466 RTE_PTYPE_L4_NONFRAG, 1467 RTE_PTYPE_L4_SCTP, 1468 RTE_PTYPE_L4_TCP, 1469 RTE_PTYPE_L4_UDP, 1470 RTE_PTYPE_TUNNEL_GRENAT, 1471 RTE_PTYPE_TUNNEL_IP, 1472 RTE_PTYPE_INNER_L2_ETHER, 1473 RTE_PTYPE_INNER_L2_ETHER_VLAN, 1474 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 1475 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 1476 RTE_PTYPE_INNER_L4_FRAG, 1477 RTE_PTYPE_INNER_L4_ICMP, 1478 RTE_PTYPE_INNER_L4_NONFRAG, 1479 RTE_PTYPE_INNER_L4_SCTP, 1480 RTE_PTYPE_INNER_L4_TCP, 1481 RTE_PTYPE_INNER_L4_UDP, 1482 RTE_PTYPE_UNKNOWN 1483 }; 1484 1485 if (dev->rx_pkt_burst == axgbe_recv_pkts) 1486 return ptypes; 1487 return NULL; 1488 } 1489 1490 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1491 { 1492 struct axgbe_port *pdata = dev->data->dev_private; 1493 unsigned int val; 1494 1495 /* mtu setting is forbidden if port is start */ 1496 if (dev->data->dev_started) { 1497 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", 1498 dev->data->port_id); 1499 return -EBUSY; 1500 } 1501 val = mtu > RTE_ETHER_MTU ? 1 : 0; 1502 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 1503 1504 return 0; 1505 } 1506 1507 static void 1508 axgbe_update_tstamp_time(struct axgbe_port *pdata, 1509 unsigned int sec, unsigned int nsec, int addsub) 1510 { 1511 unsigned int count = 100; 1512 uint32_t sub_val = 0; 1513 uint32_t sub_val_sec = 0xFFFFFFFF; 1514 uint32_t sub_val_nsec = 0x3B9ACA00; 1515 1516 if (addsub) { 1517 if (sec) 1518 sub_val = sub_val_sec - (sec - 1); 1519 else 1520 sub_val = sec; 1521 1522 AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val); 1523 sub_val = sub_val_nsec - nsec; 1524 AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val); 1525 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1); 1526 } else { 1527 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1528 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0); 1529 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1530 } 1531 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1532 /* Wait for time update to complete */ 1533 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1534 rte_delay_ms(1); 1535 } 1536 1537 static inline uint64_t 1538 div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) 1539 { 1540 *remainder = dividend % divisor; 1541 return dividend / divisor; 1542 } 1543 1544 static inline uint64_t 1545 div_u64(uint64_t dividend, uint32_t divisor) 1546 { 1547 uint32_t remainder; 1548 return div_u64_rem(dividend, divisor, &remainder); 1549 } 1550 1551 static int 1552 axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta) 1553 { 1554 uint64_t adjust; 1555 uint32_t addend, diff; 1556 unsigned int neg_adjust = 0; 1557 1558 if (delta < 0) { 1559 neg_adjust = 1; 1560 delta = -delta; 1561 } 1562 adjust = (uint64_t)pdata->tstamp_addend; 1563 adjust *= delta; 1564 diff = (uint32_t)div_u64(adjust, 1000000000UL); 1565 addend = (neg_adjust) ? pdata->tstamp_addend - diff : 1566 pdata->tstamp_addend + diff; 1567 pdata->tstamp_addend = addend; 1568 axgbe_update_tstamp_addend(pdata, addend); 1569 return 0; 1570 } 1571 1572 static int 1573 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 1574 { 1575 struct axgbe_port *pdata = dev->data->dev_private; 1576 struct timespec timestamp_delta; 1577 1578 axgbe_adjfreq(pdata, delta); 1579 pdata->systime_tc.nsec += delta; 1580 1581 if (delta < 0) { 1582 delta = -delta; 1583 timestamp_delta = rte_ns_to_timespec(delta); 1584 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1585 timestamp_delta.tv_nsec, 1); 1586 } else { 1587 timestamp_delta = rte_ns_to_timespec(delta); 1588 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1589 timestamp_delta.tv_nsec, 0); 1590 } 1591 return 0; 1592 } 1593 1594 static int 1595 axgbe_timesync_read_time(struct rte_eth_dev *dev, 1596 struct timespec *timestamp) 1597 { 1598 uint64_t nsec; 1599 struct axgbe_port *pdata = dev->data->dev_private; 1600 1601 nsec = AXGMAC_IOREAD(pdata, MAC_STSR); 1602 nsec *= NSEC_PER_SEC; 1603 nsec += AXGMAC_IOREAD(pdata, MAC_STNR); 1604 *timestamp = rte_ns_to_timespec(nsec); 1605 return 0; 1606 } 1607 static int 1608 axgbe_timesync_write_time(struct rte_eth_dev *dev, 1609 const struct timespec *timestamp) 1610 { 1611 unsigned int count = 100; 1612 struct axgbe_port *pdata = dev->data->dev_private; 1613 1614 AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec); 1615 AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec); 1616 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1617 /* Wait for time update to complete */ 1618 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1619 rte_delay_ms(1); 1620 if (!count) 1621 PMD_DRV_LOG(ERR, "Timed out update timestamp\n"); 1622 return 0; 1623 } 1624 1625 static void 1626 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 1627 uint32_t addend) 1628 { 1629 unsigned int count = 100; 1630 1631 AXGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1632 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1633 1634 /* Wait for addend update to complete */ 1635 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1636 rte_delay_ms(1); 1637 if (!count) 1638 PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n"); 1639 } 1640 1641 static void 1642 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 1643 unsigned int nsec) 1644 { 1645 unsigned int count = 100; 1646 1647 /*System Time Sec Update*/ 1648 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1649 /*System Time nanoSec Update*/ 1650 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1651 /*Initialize Timestamp*/ 1652 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1653 1654 /* Wait for time update to complete */ 1655 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1656 rte_delay_ms(1); 1657 if (!count) 1658 PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n"); 1659 } 1660 1661 static int 1662 axgbe_timesync_enable(struct rte_eth_dev *dev) 1663 { 1664 struct axgbe_port *pdata = dev->data->dev_private; 1665 unsigned int mac_tscr = 0; 1666 uint64_t dividend; 1667 struct timespec timestamp; 1668 uint64_t nsec; 1669 1670 /* Set one nano-second accuracy */ 1671 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1672 1673 /* Set fine timestamp update */ 1674 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1675 1676 /* Overwrite earlier timestamps */ 1677 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1678 1679 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1680 1681 /* Enabling processing of ptp over eth pkt */ 1682 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1683 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1684 /* Enable timestamp for all pkts*/ 1685 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 1686 1687 /* enabling timestamp */ 1688 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1689 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1690 1691 /* Exit if timestamping is not enabled */ 1692 if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) { 1693 PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n"); 1694 return 0; 1695 } 1696 1697 /* Sub-second Increment Value*/ 1698 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC); 1699 /* Sub-nanosecond Increment Value */ 1700 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC); 1701 1702 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 1703 dividend = 50000000; 1704 dividend <<= 32; 1705 pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate); 1706 1707 axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1708 axgbe_set_tstamp_time(pdata, 0, 0); 1709 1710 /* Initialize the timecounter */ 1711 memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter)); 1712 1713 pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK; 1714 pdata->systime_tc.cc_shift = 0; 1715 pdata->systime_tc.nsec_mask = 0; 1716 1717 PMD_DRV_LOG(DEBUG, "Initializing system time counter with realtime\n"); 1718 1719 /* Updating the counter once with clock real time */ 1720 clock_gettime(CLOCK_REALTIME, ×tamp); 1721 nsec = rte_timespec_to_ns(×tamp); 1722 nsec = rte_timecounter_update(&pdata->systime_tc, nsec); 1723 axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec); 1724 return 0; 1725 } 1726 1727 static int 1728 axgbe_timesync_disable(struct rte_eth_dev *dev) 1729 { 1730 struct axgbe_port *pdata = dev->data->dev_private; 1731 unsigned int mac_tscr = 0; 1732 1733 /*disable timestamp for all pkts*/ 1734 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0); 1735 /*disable the addened register*/ 1736 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0); 1737 /* disable timestamp update */ 1738 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0); 1739 /*disable time stamp*/ 1740 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0); 1741 return 0; 1742 } 1743 1744 static int 1745 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 1746 struct timespec *timestamp, uint32_t flags) 1747 { 1748 uint64_t nsec = 0; 1749 volatile union axgbe_rx_desc *desc; 1750 uint16_t idx, pmt; 1751 struct axgbe_rx_queue *rxq = *dev->data->rx_queues; 1752 1753 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 1754 desc = &rxq->desc[idx]; 1755 1756 while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 1757 rte_delay_ms(1); 1758 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) { 1759 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) && 1760 !AXGMAC_GET_BITS_LE(desc->write.desc3, 1761 RX_CONTEXT_DESC3, TSD)) { 1762 pmt = AXGMAC_GET_BITS_LE(desc->write.desc3, 1763 RX_CONTEXT_DESC3, PMT); 1764 nsec = rte_le_to_cpu_32(desc->write.desc1); 1765 nsec *= NSEC_PER_SEC; 1766 nsec += rte_le_to_cpu_32(desc->write.desc0); 1767 if (nsec != 0xffffffffffffffffULL) { 1768 if (pmt == 0x01) 1769 *timestamp = rte_ns_to_timespec(nsec); 1770 PMD_DRV_LOG(DEBUG, 1771 "flags = 0x%x nsec = %"PRIu64"\n", 1772 flags, nsec); 1773 } 1774 } 1775 } 1776 1777 return 0; 1778 } 1779 1780 static int 1781 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 1782 struct timespec *timestamp) 1783 { 1784 uint64_t nsec; 1785 struct axgbe_port *pdata = dev->data->dev_private; 1786 unsigned int tx_snr, tx_ssr; 1787 1788 rte_delay_us(5); 1789 if (pdata->vdata->tx_tstamp_workaround) { 1790 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1791 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1792 1793 } else { 1794 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1795 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1796 } 1797 if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) { 1798 PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n"); 1799 return 0; 1800 } 1801 nsec = tx_ssr; 1802 nsec *= NSEC_PER_SEC; 1803 nsec += tx_snr; 1804 PMD_DRV_LOG(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d\n", 1805 nsec, tx_ssr, tx_snr); 1806 *timestamp = rte_ns_to_timespec(nsec); 1807 return 0; 1808 } 1809 1810 static int 1811 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1812 { 1813 struct axgbe_port *pdata = dev->data->dev_private; 1814 unsigned long vid_bit, vid_idx; 1815 1816 vid_bit = VLAN_TABLE_BIT(vid); 1817 vid_idx = VLAN_TABLE_IDX(vid); 1818 1819 if (on) { 1820 PMD_DRV_LOG(DEBUG, "Set VLAN vid=%d for device = %s\n", 1821 vid, pdata->eth_dev->device->name); 1822 pdata->active_vlans[vid_idx] |= vid_bit; 1823 } else { 1824 PMD_DRV_LOG(DEBUG, "Reset VLAN vid=%d for device = %s\n", 1825 vid, pdata->eth_dev->device->name); 1826 pdata->active_vlans[vid_idx] &= ~vid_bit; 1827 } 1828 pdata->hw_if.update_vlan_hash_table(pdata); 1829 return 0; 1830 } 1831 1832 static int 1833 axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1834 enum rte_vlan_type vlan_type, 1835 uint16_t tpid) 1836 { 1837 struct axgbe_port *pdata = dev->data->dev_private; 1838 uint32_t reg = 0; 1839 uint32_t qinq = 0; 1840 1841 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1842 PMD_DRV_LOG(DEBUG, "EDVLP: qinq = 0x%x\n", qinq); 1843 1844 switch (vlan_type) { 1845 case RTE_ETH_VLAN_TYPE_INNER: 1846 PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_INNER\n"); 1847 if (qinq) { 1848 if (tpid != 0x8100 && tpid != 0x88a8) 1849 PMD_DRV_LOG(ERR, 1850 "tag supported 0x8100/0x88A8\n"); 1851 PMD_DRV_LOG(DEBUG, "qinq with inner tag\n"); 1852 1853 /*Enable Inner VLAN Tag */ 1854 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 1); 1855 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1856 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg); 1857 1858 } else { 1859 PMD_DRV_LOG(ERR, 1860 "Inner type not supported in single tag\n"); 1861 } 1862 break; 1863 case RTE_ETH_VLAN_TYPE_OUTER: 1864 PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_OUTER\n"); 1865 if (qinq) { 1866 PMD_DRV_LOG(DEBUG, "double tagging is enabled\n"); 1867 /*Enable outer VLAN tag*/ 1868 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 0); 1869 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1870 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg); 1871 1872 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 1); 1873 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANIR, CSVL); 1874 PMD_DRV_LOG(DEBUG, "bit CSVL = 0x%x\n", reg); 1875 } else { 1876 if (tpid != 0x8100 && tpid != 0x88a8) 1877 PMD_DRV_LOG(ERR, 1878 "tag supported 0x8100/0x88A8\n"); 1879 } 1880 break; 1881 case RTE_ETH_VLAN_TYPE_MAX: 1882 PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_MAX\n"); 1883 break; 1884 case RTE_ETH_VLAN_TYPE_UNKNOWN: 1885 PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_UNKNOWN\n"); 1886 break; 1887 } 1888 return 0; 1889 } 1890 1891 static void axgbe_vlan_extend_enable(struct axgbe_port *pdata) 1892 { 1893 int qinq = 0; 1894 1895 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 1); 1896 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1897 PMD_DRV_LOG(DEBUG, "vlan double tag enabled EDVLP:qinq=0x%x\n", qinq); 1898 } 1899 1900 static void axgbe_vlan_extend_disable(struct axgbe_port *pdata) 1901 { 1902 int qinq = 0; 1903 1904 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 0); 1905 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1906 PMD_DRV_LOG(DEBUG, "vlan double tag disable EDVLP:qinq=0x%x\n", qinq); 1907 } 1908 1909 static int 1910 axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1911 { 1912 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1913 struct axgbe_port *pdata = dev->data->dev_private; 1914 1915 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 1916 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 1917 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 1918 1919 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 1920 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { 1921 PMD_DRV_LOG(DEBUG, "Strip ON for device = %s\n", 1922 pdata->eth_dev->device->name); 1923 pdata->hw_if.enable_rx_vlan_stripping(pdata); 1924 } else { 1925 PMD_DRV_LOG(DEBUG, "Strip OFF for device = %s\n", 1926 pdata->eth_dev->device->name); 1927 pdata->hw_if.disable_rx_vlan_stripping(pdata); 1928 } 1929 } 1930 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 1931 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 1932 PMD_DRV_LOG(DEBUG, "Filter ON for device = %s\n", 1933 pdata->eth_dev->device->name); 1934 pdata->hw_if.enable_rx_vlan_filtering(pdata); 1935 } else { 1936 PMD_DRV_LOG(DEBUG, "Filter OFF for device = %s\n", 1937 pdata->eth_dev->device->name); 1938 pdata->hw_if.disable_rx_vlan_filtering(pdata); 1939 } 1940 } 1941 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 1942 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) { 1943 PMD_DRV_LOG(DEBUG, "enabling vlan extended mode\n"); 1944 axgbe_vlan_extend_enable(pdata); 1945 /* Set global registers with default ethertype*/ 1946 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER, 1947 RTE_ETHER_TYPE_VLAN); 1948 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER, 1949 RTE_ETHER_TYPE_VLAN); 1950 } else { 1951 PMD_DRV_LOG(DEBUG, "disabling vlan extended mode\n"); 1952 axgbe_vlan_extend_disable(pdata); 1953 } 1954 } 1955 return 0; 1956 } 1957 1958 static void axgbe_get_all_hw_features(struct axgbe_port *pdata) 1959 { 1960 unsigned int mac_hfr0, mac_hfr1, mac_hfr2, mac_hfr3; 1961 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 1962 1963 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R); 1964 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R); 1965 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R); 1966 mac_hfr3 = AXGMAC_IOREAD(pdata, MAC_HWF3R); 1967 1968 memset(hw_feat, 0, sizeof(*hw_feat)); 1969 1970 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR); 1971 1972 /* Hardware feature register 0 */ 1973 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 1974 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 1975 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 1976 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 1977 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 1978 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 1979 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 1980 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 1981 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 1982 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 1983 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 1984 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 1985 ADDMACADRSEL); 1986 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 1987 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 1988 1989 /* Hardware feature register 1 */ 1990 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1991 RXFIFOSIZE); 1992 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1993 TXFIFOSIZE); 1994 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1, 1995 MAC_HWF1R, ADVTHWORD); 1996 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 1997 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 1998 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 1999 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 2000 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 2001 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 2002 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 2003 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 2004 HASHTBLSZ); 2005 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 2006 L3L4FNUM); 2007 2008 /* Hardware feature register 2 */ 2009 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 2010 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 2011 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 2012 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 2013 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 2014 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, 2015 AUXSNAPNUM); 2016 2017 /* Hardware feature register 3 */ 2018 hw_feat->tx_q_vlan_tag_ins = AXGMAC_GET_BITS(mac_hfr3, 2019 MAC_HWF3R, CBTISEL); 2020 hw_feat->no_of_vlan_extn = AXGMAC_GET_BITS(mac_hfr3, 2021 MAC_HWF3R, NRVF); 2022 2023 /* Translate the Hash Table size into actual number */ 2024 switch (hw_feat->hash_table_size) { 2025 case 0: 2026 break; 2027 case 1: 2028 hw_feat->hash_table_size = 64; 2029 break; 2030 case 2: 2031 hw_feat->hash_table_size = 128; 2032 break; 2033 case 3: 2034 hw_feat->hash_table_size = 256; 2035 break; 2036 } 2037 2038 /* Translate the address width setting into actual number */ 2039 switch (hw_feat->dma_width) { 2040 case 0: 2041 hw_feat->dma_width = 32; 2042 break; 2043 case 1: 2044 hw_feat->dma_width = 40; 2045 break; 2046 case 2: 2047 hw_feat->dma_width = 48; 2048 break; 2049 default: 2050 hw_feat->dma_width = 32; 2051 } 2052 2053 /* The Queue, Channel and TC counts are zero based so increment them 2054 * to get the actual number 2055 */ 2056 hw_feat->rx_q_cnt++; 2057 hw_feat->tx_q_cnt++; 2058 hw_feat->rx_ch_cnt++; 2059 hw_feat->tx_ch_cnt++; 2060 hw_feat->tc_cnt++; 2061 2062 /* Translate the fifo sizes into actual numbers */ 2063 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 2064 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 2065 } 2066 2067 static void axgbe_init_all_fptrs(struct axgbe_port *pdata) 2068 { 2069 axgbe_init_function_ptrs_dev(&pdata->hw_if); 2070 axgbe_init_function_ptrs_phy(&pdata->phy_if); 2071 axgbe_init_function_ptrs_i2c(&pdata->i2c_if); 2072 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 2073 } 2074 2075 static void axgbe_set_counts(struct axgbe_port *pdata) 2076 { 2077 /* Set all the function pointers */ 2078 axgbe_init_all_fptrs(pdata); 2079 2080 /* Populate the hardware features */ 2081 axgbe_get_all_hw_features(pdata); 2082 2083 /* Set default max values if not provided */ 2084 if (!pdata->tx_max_channel_count) 2085 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 2086 if (!pdata->rx_max_channel_count) 2087 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 2088 2089 if (!pdata->tx_max_q_count) 2090 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 2091 if (!pdata->rx_max_q_count) 2092 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 2093 2094 /* Calculate the number of Tx and Rx rings to be created 2095 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 2096 * the number of Tx queues to the number of Tx channels 2097 * enabled 2098 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 2099 * number of Rx queues or maximum allowed 2100 */ 2101 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt, 2102 pdata->tx_max_channel_count); 2103 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count, 2104 pdata->tx_max_q_count); 2105 2106 pdata->tx_q_count = pdata->tx_ring_count; 2107 2108 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt, 2109 pdata->rx_max_channel_count); 2110 2111 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt, 2112 pdata->rx_max_q_count); 2113 } 2114 2115 static void axgbe_default_config(struct axgbe_port *pdata) 2116 { 2117 pdata->pblx8 = DMA_PBL_X8_ENABLE; 2118 pdata->tx_sf_mode = MTL_TSF_ENABLE; 2119 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 2120 pdata->tx_pbl = DMA_PBL_32; 2121 pdata->tx_osp_mode = DMA_OSP_ENABLE; 2122 pdata->rx_sf_mode = MTL_RSF_ENABLE; 2123 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 2124 pdata->rx_pbl = DMA_PBL_32; 2125 pdata->pause_autoneg = 1; 2126 pdata->tx_pause = 0; 2127 pdata->rx_pause = 0; 2128 pdata->phy_speed = SPEED_UNKNOWN; 2129 pdata->power_down = 0; 2130 } 2131 2132 /* Used in dev_start by primary process and then 2133 * in dev_init by secondary process when attaching to an existing ethdev. 2134 */ 2135 void 2136 axgbe_set_tx_function(struct rte_eth_dev *dev) 2137 { 2138 struct axgbe_port *pdata = dev->data->dev_private; 2139 2140 if (pdata->multi_segs_tx) 2141 dev->tx_pkt_burst = &axgbe_xmit_pkts_seg; 2142 #ifdef RTE_ARCH_X86 2143 struct axgbe_tx_queue *txq = dev->data->tx_queues[0]; 2144 if (!txq->vector_disable && 2145 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) 2146 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec; 2147 #else 2148 dev->tx_pkt_burst = &axgbe_xmit_pkts; 2149 #endif 2150 } 2151 2152 void 2153 axgbe_set_rx_function(struct rte_eth_dev *dev) 2154 { 2155 struct rte_eth_dev_data *dev_data = dev->data; 2156 uint16_t max_pkt_len; 2157 struct axgbe_port *pdata; 2158 2159 pdata = dev->data->dev_private; 2160 max_pkt_len = dev_data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 2161 if ((dev_data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) || 2162 max_pkt_len > pdata->rx_buf_size) 2163 dev_data->scattered_rx = 1; 2164 /* Scatter Rx handling */ 2165 if (dev_data->scattered_rx) 2166 dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts; 2167 else 2168 dev->rx_pkt_burst = &axgbe_recv_pkts; 2169 } 2170 2171 /* 2172 * It returns 0 on success. 2173 */ 2174 static int 2175 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) 2176 { 2177 PMD_INIT_FUNC_TRACE(); 2178 struct axgbe_port *pdata; 2179 struct rte_pci_device *pci_dev; 2180 uint32_t reg, mac_lo, mac_hi; 2181 uint32_t len; 2182 int ret; 2183 2184 unsigned int eax = 0, ebx = 0, ecx = 0, edx = 0; 2185 unsigned char cpu_family = 0, cpu_model = 0; 2186 2187 eth_dev->dev_ops = &axgbe_eth_dev_ops; 2188 2189 eth_dev->rx_descriptor_status = axgbe_dev_rx_descriptor_status; 2190 eth_dev->tx_descriptor_status = axgbe_dev_tx_descriptor_status; 2191 2192 eth_dev->tx_pkt_burst = &axgbe_xmit_pkts; 2193 eth_dev->rx_pkt_burst = &axgbe_recv_pkts; 2194 2195 /* 2196 * For secondary processes, we don't initialise any further as primary 2197 * has already done this work. 2198 */ 2199 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2200 axgbe_set_tx_function(eth_dev); 2201 axgbe_set_rx_function(eth_dev); 2202 return 0; 2203 } 2204 2205 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2206 2207 pdata = eth_dev->data->dev_private; 2208 /* initial state */ 2209 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 2210 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 2211 pdata->eth_dev = eth_dev; 2212 2213 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2214 pdata->pci_dev = pci_dev; 2215 2216 pdata->xgmac_regs = 2217 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; 2218 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs 2219 + AXGBE_MAC_PROP_OFFSET); 2220 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs 2221 + AXGBE_I2C_CTRL_OFFSET); 2222 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; 2223 2224 /* version specific driver data*/ 2225 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A) 2226 pdata->vdata = &axgbe_v2a; 2227 else 2228 pdata->vdata = &axgbe_v2b; 2229 2230 /* 2231 * Use CPUID to get Family and model ID to identify the CPU 2232 */ 2233 __cpuid(0x0, eax, ebx, ecx, edx); 2234 2235 if (ebx == CPUID_VENDOR_AuthenticAMD_ebx && 2236 edx == CPUID_VENDOR_AuthenticAMD_edx && 2237 ecx == CPUID_VENDOR_AuthenticAMD_ecx) { 2238 int unknown_cpu = 0; 2239 eax = 0, ebx = 0, ecx = 0, edx = 0; 2240 2241 __cpuid(0x1, eax, ebx, ecx, edx); 2242 2243 cpu_family = ((GET_BITS(eax, 8, 4)) + (GET_BITS(eax, 20, 8))); 2244 cpu_model = ((GET_BITS(eax, 4, 4)) | (((GET_BITS(eax, 16, 4)) << 4) & 0xF0)); 2245 2246 switch (cpu_family) { 2247 case Fam17h: 2248 /* V1000/R1000 */ 2249 if (cpu_model >= 0x10 && cpu_model <= 0x1F) { 2250 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; 2251 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; 2252 /* EPYC 3000 */ 2253 } else if (cpu_model >= 0x01 && cpu_model <= 0x0F) { 2254 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 2255 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 2256 } else { 2257 unknown_cpu = 1; 2258 } 2259 break; 2260 case Fam19h: 2261 /* V3000 (Yellow Carp) */ 2262 if (cpu_model >= 0x44 && cpu_model <= 0x47) { 2263 pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF; 2264 pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT; 2265 2266 /* Yellow Carp devices do not need cdr workaround */ 2267 pdata->vdata->an_cdr_workaround = 0; 2268 } else { 2269 unknown_cpu = 1; 2270 } 2271 break; 2272 default: 2273 unknown_cpu = 1; 2274 break; 2275 } 2276 if (unknown_cpu) { 2277 PMD_DRV_LOG(ERR, "Unknown CPU family, no supported axgbe device found\n"); 2278 return -ENODEV; 2279 } 2280 } 2281 2282 /* Configure the PCS indirect addressing support */ 2283 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); 2284 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 2285 pdata->xpcs_window <<= 6; 2286 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 2287 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 2288 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 2289 2290 PMD_INIT_LOG(DEBUG, 2291 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, 2292 pdata->xpcs_window_size, pdata->xpcs_window_mask); 2293 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 2294 2295 /* Retrieve the MAC address */ 2296 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 2297 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 2298 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff; 2299 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff; 2300 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff; 2301 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff; 2302 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff; 2303 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff; 2304 2305 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_MAC_ADDRS; 2306 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", len, 0); 2307 2308 if (!eth_dev->data->mac_addrs) { 2309 PMD_INIT_LOG(ERR, 2310 "Failed to alloc %u bytes needed to " 2311 "store MAC addresses", len); 2312 return -ENOMEM; 2313 } 2314 2315 /* Allocate memory for storing hash filter MAC addresses */ 2316 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS; 2317 eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr", 2318 len, 0); 2319 2320 if (eth_dev->data->hash_mac_addrs == NULL) { 2321 PMD_INIT_LOG(ERR, 2322 "Failed to allocate %d bytes needed to " 2323 "store MAC addresses", len); 2324 return -ENOMEM; 2325 } 2326 2327 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr)) 2328 rte_eth_random_addr(pdata->mac_addr.addr_bytes); 2329 2330 /* Copy the permanent MAC address */ 2331 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]); 2332 2333 /* Clock settings */ 2334 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ; 2335 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 2336 2337 /* Set the DMA coherency values */ 2338 pdata->coherent = 1; 2339 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN; 2340 pdata->arcache = AXGBE_DMA_OS_ARCACHE; 2341 pdata->awcache = AXGBE_DMA_OS_AWCACHE; 2342 2343 /* Set the maximum channels and queues */ 2344 reg = XP_IOREAD(pdata, XP_PROP_1); 2345 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA); 2346 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA); 2347 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES); 2348 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES); 2349 2350 /* Set the hardware channel and queue counts */ 2351 axgbe_set_counts(pdata); 2352 2353 /* Set the maximum fifo amounts */ 2354 reg = XP_IOREAD(pdata, XP_PROP_2); 2355 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE); 2356 pdata->tx_max_fifo_size *= 16384; 2357 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size, 2358 pdata->vdata->tx_max_fifo_size); 2359 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE); 2360 pdata->rx_max_fifo_size *= 16384; 2361 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size, 2362 pdata->vdata->rx_max_fifo_size); 2363 /* Issue software reset to DMA */ 2364 ret = pdata->hw_if.exit(pdata); 2365 if (ret) 2366 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n"); 2367 2368 /* Set default configuration data */ 2369 axgbe_default_config(pdata); 2370 2371 /* Set default max values if not provided */ 2372 if (!pdata->tx_max_fifo_size) 2373 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 2374 if (!pdata->rx_max_fifo_size) 2375 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 2376 2377 pdata->tx_desc_count = AXGBE_MAX_RING_DESC; 2378 pdata->rx_desc_count = AXGBE_MAX_RING_DESC; 2379 pthread_mutex_init(&pdata->xpcs_mutex, NULL); 2380 pthread_mutex_init(&pdata->i2c_mutex, NULL); 2381 pthread_mutex_init(&pdata->an_mutex, NULL); 2382 pthread_mutex_init(&pdata->phy_mutex, NULL); 2383 2384 ret = pdata->phy_if.phy_init(pdata); 2385 if (ret) { 2386 rte_free(eth_dev->data->mac_addrs); 2387 eth_dev->data->mac_addrs = NULL; 2388 return ret; 2389 } 2390 2391 rte_intr_callback_register(pci_dev->intr_handle, 2392 axgbe_dev_interrupt_handler, 2393 (void *)eth_dev); 2394 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 2395 eth_dev->data->port_id, pci_dev->id.vendor_id, 2396 pci_dev->id.device_id); 2397 2398 return 0; 2399 } 2400 2401 static int 2402 axgbe_dev_close(struct rte_eth_dev *eth_dev) 2403 { 2404 struct rte_pci_device *pci_dev; 2405 2406 PMD_INIT_FUNC_TRACE(); 2407 2408 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2409 return 0; 2410 2411 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2412 axgbe_dev_clear_queues(eth_dev); 2413 2414 /* disable uio intr before callback unregister */ 2415 rte_intr_disable(pci_dev->intr_handle); 2416 rte_intr_callback_unregister(pci_dev->intr_handle, 2417 axgbe_dev_interrupt_handler, 2418 (void *)eth_dev); 2419 2420 return 0; 2421 } 2422 2423 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2424 struct rte_pci_device *pci_dev) 2425 { 2426 return rte_eth_dev_pci_generic_probe(pci_dev, 2427 sizeof(struct axgbe_port), eth_axgbe_dev_init); 2428 } 2429 2430 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev) 2431 { 2432 return rte_eth_dev_pci_generic_remove(pci_dev, axgbe_dev_close); 2433 } 2434 2435 static struct rte_pci_driver rte_axgbe_pmd = { 2436 .id_table = pci_id_axgbe_map, 2437 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2438 .probe = eth_axgbe_pci_probe, 2439 .remove = eth_axgbe_pci_remove, 2440 }; 2441 2442 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd); 2443 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map); 2444 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 2445 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_init, init, NOTICE); 2446 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_driver, driver, NOTICE); 2447