1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_rxtx.h" 7 #include "axgbe_ethdev.h" 8 #include "axgbe_common.h" 9 #include "axgbe_phy.h" 10 #include "axgbe_regs.h" 11 #include "rte_time.h" 12 13 #include "eal_filesystem.h" 14 15 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); 16 static int axgbe_dev_configure(struct rte_eth_dev *dev); 17 static int axgbe_dev_start(struct rte_eth_dev *dev); 18 static int axgbe_dev_stop(struct rte_eth_dev *dev); 19 static void axgbe_dev_interrupt_handler(void *param); 20 static int axgbe_dev_close(struct rte_eth_dev *dev); 21 static int axgbe_dev_reset(struct rte_eth_dev *dev); 22 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 23 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 24 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 25 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 26 static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, 27 struct rte_ether_addr *mac_addr); 28 static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, 29 struct rte_ether_addr *mac_addr, 30 uint32_t index, 31 uint32_t vmdq); 32 static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 33 static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 34 struct rte_ether_addr *mc_addr_set, 35 uint32_t nb_mc_addr); 36 static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 37 struct rte_ether_addr *mac_addr, 38 uint8_t add); 39 static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, 40 uint8_t add); 41 static int axgbe_dev_link_update(struct rte_eth_dev *dev, 42 int wait_to_complete); 43 static int axgbe_dev_get_regs(struct rte_eth_dev *dev, 44 struct rte_dev_reg_info *regs); 45 static int axgbe_dev_stats_get(struct rte_eth_dev *dev, 46 struct rte_eth_stats *stats); 47 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev); 48 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev, 49 struct rte_eth_xstat *stats, 50 unsigned int n); 51 static int 52 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 53 struct rte_eth_xstat_name *xstats_names, 54 unsigned int size); 55 static int 56 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 57 const uint64_t *ids, 58 uint64_t *values, 59 unsigned int n); 60 static int 61 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 62 const uint64_t *ids, 63 struct rte_eth_xstat_name *xstats_names, 64 unsigned int size); 65 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev); 66 static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 67 struct rte_eth_rss_reta_entry64 *reta_conf, 68 uint16_t reta_size); 69 static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 70 struct rte_eth_rss_reta_entry64 *reta_conf, 71 uint16_t reta_size); 72 static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 73 struct rte_eth_rss_conf *rss_conf); 74 static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 75 struct rte_eth_rss_conf *rss_conf); 76 static int axgbe_dev_info_get(struct rte_eth_dev *dev, 77 struct rte_eth_dev_info *dev_info); 78 static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, 79 struct rte_eth_fc_conf *fc_conf); 80 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, 81 struct rte_eth_fc_conf *fc_conf); 82 static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 83 struct rte_eth_pfc_conf *pfc_conf); 84 static void axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 85 struct rte_eth_rxq_info *qinfo); 86 static void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 87 struct rte_eth_txq_info *qinfo); 88 const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 89 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 90 91 static int 92 axgbe_timesync_enable(struct rte_eth_dev *dev); 93 static int 94 axgbe_timesync_disable(struct rte_eth_dev *dev); 95 static int 96 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 97 struct timespec *timestamp, uint32_t flags); 98 static int 99 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 100 struct timespec *timestamp); 101 static int 102 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 103 static int 104 axgbe_timesync_read_time(struct rte_eth_dev *dev, 105 struct timespec *timestamp); 106 static int 107 axgbe_timesync_write_time(struct rte_eth_dev *dev, 108 const struct timespec *timestamp); 109 static void 110 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 111 unsigned int nsec); 112 static void 113 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 114 unsigned int addend); 115 static int 116 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on); 117 static int axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 118 enum rte_vlan_type vlan_type, uint16_t tpid); 119 static int axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 120 121 struct axgbe_xstats { 122 char name[RTE_ETH_XSTATS_NAME_SIZE]; 123 int offset; 124 }; 125 126 #define AXGMAC_MMC_STAT(_string, _var) \ 127 { _string, \ 128 offsetof(struct axgbe_mmc_stats, _var), \ 129 } 130 131 static const struct axgbe_xstats axgbe_xstats_strings[] = { 132 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb), 133 AXGMAC_MMC_STAT("tx_packets", txframecount_gb), 134 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb), 135 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb), 136 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb), 137 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g), 138 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb), 139 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb), 140 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb), 141 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb), 142 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb), 143 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb), 144 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror), 145 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes), 146 147 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb), 148 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb), 149 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g), 150 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g), 151 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g), 152 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb), 153 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb), 154 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb), 155 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb), 156 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb), 157 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb), 158 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb), 159 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g), 160 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g), 161 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror), 162 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror), 163 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror), 164 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror), 165 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype), 166 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow), 167 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror), 168 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes), 169 }; 170 171 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings) 172 173 /* The set of PCI devices this driver supports */ 174 #define AMD_PCI_VENDOR_ID 0x1022 175 #define AMD_PCI_RV_ROOT_COMPLEX_ID 0x15d0 176 #define AMD_PCI_YC_ROOT_COMPLEX_ID 0x14b5 177 #define AMD_PCI_SNOWY_ROOT_COMPLEX_ID 0x1450 178 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 179 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459 180 181 static const struct rte_pci_id pci_id_axgbe_map[] = { 182 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)}, 183 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)}, 184 { .vendor_id = 0, }, 185 }; 186 187 static struct axgbe_version_data axgbe_v2a = { 188 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 189 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 190 .mmc_64bit = 1, 191 .tx_max_fifo_size = 229376, 192 .rx_max_fifo_size = 229376, 193 .tx_tstamp_workaround = 1, 194 .ecc_support = 1, 195 .i2c_support = 1, 196 .an_cdr_workaround = 1, 197 }; 198 199 static struct axgbe_version_data axgbe_v2b = { 200 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 201 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 202 .mmc_64bit = 1, 203 .tx_max_fifo_size = 65536, 204 .rx_max_fifo_size = 65536, 205 .tx_tstamp_workaround = 1, 206 .ecc_support = 1, 207 .i2c_support = 1, 208 .an_cdr_workaround = 1, 209 }; 210 211 static const struct rte_eth_desc_lim rx_desc_lim = { 212 .nb_max = AXGBE_MAX_RING_DESC, 213 .nb_min = AXGBE_MIN_RING_DESC, 214 .nb_align = 8, 215 }; 216 217 static const struct rte_eth_desc_lim tx_desc_lim = { 218 .nb_max = AXGBE_MAX_RING_DESC, 219 .nb_min = AXGBE_MIN_RING_DESC, 220 .nb_align = 8, 221 }; 222 223 static const struct eth_dev_ops axgbe_eth_dev_ops = { 224 .dev_configure = axgbe_dev_configure, 225 .dev_start = axgbe_dev_start, 226 .dev_stop = axgbe_dev_stop, 227 .dev_close = axgbe_dev_close, 228 .dev_reset = axgbe_dev_reset, 229 .promiscuous_enable = axgbe_dev_promiscuous_enable, 230 .promiscuous_disable = axgbe_dev_promiscuous_disable, 231 .allmulticast_enable = axgbe_dev_allmulticast_enable, 232 .allmulticast_disable = axgbe_dev_allmulticast_disable, 233 .mac_addr_set = axgbe_dev_mac_addr_set, 234 .mac_addr_add = axgbe_dev_mac_addr_add, 235 .mac_addr_remove = axgbe_dev_mac_addr_remove, 236 .set_mc_addr_list = axgbe_dev_set_mc_addr_list, 237 .uc_hash_table_set = axgbe_dev_uc_hash_table_set, 238 .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set, 239 .link_update = axgbe_dev_link_update, 240 .get_reg = axgbe_dev_get_regs, 241 .stats_get = axgbe_dev_stats_get, 242 .stats_reset = axgbe_dev_stats_reset, 243 .xstats_get = axgbe_dev_xstats_get, 244 .xstats_reset = axgbe_dev_xstats_reset, 245 .xstats_get_names = axgbe_dev_xstats_get_names, 246 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id, 247 .xstats_get_by_id = axgbe_dev_xstats_get_by_id, 248 .reta_update = axgbe_dev_rss_reta_update, 249 .reta_query = axgbe_dev_rss_reta_query, 250 .rss_hash_update = axgbe_dev_rss_hash_update, 251 .rss_hash_conf_get = axgbe_dev_rss_hash_conf_get, 252 .dev_infos_get = axgbe_dev_info_get, 253 .rx_queue_setup = axgbe_dev_rx_queue_setup, 254 .rx_queue_release = axgbe_dev_rx_queue_release, 255 .tx_queue_setup = axgbe_dev_tx_queue_setup, 256 .tx_queue_release = axgbe_dev_tx_queue_release, 257 .flow_ctrl_get = axgbe_flow_ctrl_get, 258 .flow_ctrl_set = axgbe_flow_ctrl_set, 259 .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set, 260 .rxq_info_get = axgbe_rxq_info_get, 261 .txq_info_get = axgbe_txq_info_get, 262 .dev_supported_ptypes_get = axgbe_dev_supported_ptypes_get, 263 .mtu_set = axgb_mtu_set, 264 .vlan_filter_set = axgbe_vlan_filter_set, 265 .vlan_tpid_set = axgbe_vlan_tpid_set, 266 .vlan_offload_set = axgbe_vlan_offload_set, 267 .timesync_enable = axgbe_timesync_enable, 268 .timesync_disable = axgbe_timesync_disable, 269 .timesync_read_rx_timestamp = axgbe_timesync_read_rx_timestamp, 270 .timesync_read_tx_timestamp = axgbe_timesync_read_tx_timestamp, 271 .timesync_adjust_time = axgbe_timesync_adjust_time, 272 .timesync_read_time = axgbe_timesync_read_time, 273 .timesync_write_time = axgbe_timesync_write_time, 274 .fw_version_get = axgbe_dev_fw_version_get, 275 }; 276 277 static int axgbe_phy_reset(struct axgbe_port *pdata) 278 { 279 pdata->phy_link = -1; 280 pdata->phy_speed = SPEED_UNKNOWN; 281 return pdata->phy_if.phy_reset(pdata); 282 } 283 284 /* 285 * Interrupt handler triggered by NIC for handling 286 * specific interrupt. 287 * 288 * @param handle 289 * Pointer to interrupt handle. 290 * @param param 291 * The address of parameter (struct rte_eth_dev *) registered before. 292 * 293 * @return 294 * void 295 */ 296 static void 297 axgbe_dev_interrupt_handler(void *param) 298 { 299 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 300 struct axgbe_port *pdata = dev->data->dev_private; 301 unsigned int dma_isr, dma_ch_isr; 302 303 pdata->phy_if.an_isr(pdata); 304 /*DMA related interrupts*/ 305 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR); 306 PMD_DRV_LOG(DEBUG, "DMA_ISR=%#010x\n", dma_isr); 307 if (dma_isr) { 308 if (dma_isr & 1) { 309 dma_ch_isr = 310 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *) 311 pdata->rx_queues[0], 312 DMA_CH_SR); 313 PMD_DRV_LOG(DEBUG, "DMA_CH0_ISR=%#010x\n", dma_ch_isr); 314 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *) 315 pdata->rx_queues[0], 316 DMA_CH_SR, dma_ch_isr); 317 } 318 } 319 /* Unmask interrupts since disabled after generation */ 320 rte_intr_ack(pdata->pci_dev->intr_handle); 321 } 322 323 /* 324 * Configure device link speed and setup link. 325 * It returns 0 on success. 326 */ 327 static int 328 axgbe_dev_configure(struct rte_eth_dev *dev) 329 { 330 struct axgbe_port *pdata = dev->data->dev_private; 331 /* Checksum offload to hardware */ 332 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads & 333 RTE_ETH_RX_OFFLOAD_CHECKSUM; 334 return 0; 335 } 336 337 static int 338 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev) 339 { 340 struct axgbe_port *pdata = dev->data->dev_private; 341 342 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) 343 pdata->rss_enable = 1; 344 else if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_NONE) 345 pdata->rss_enable = 0; 346 else 347 return -1; 348 return 0; 349 } 350 351 static int 352 axgbe_dev_start(struct rte_eth_dev *dev) 353 { 354 struct axgbe_port *pdata = dev->data->dev_private; 355 int ret; 356 357 dev->dev_ops = &axgbe_eth_dev_ops; 358 359 PMD_INIT_FUNC_TRACE(); 360 361 /* Multiqueue RSS */ 362 ret = axgbe_dev_rx_mq_config(dev); 363 if (ret) { 364 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n"); 365 return ret; 366 } 367 ret = axgbe_phy_reset(pdata); 368 if (ret) { 369 PMD_DRV_LOG(ERR, "phy reset failed\n"); 370 return ret; 371 } 372 ret = pdata->hw_if.init(pdata); 373 if (ret) { 374 PMD_DRV_LOG(ERR, "dev_init failed\n"); 375 return ret; 376 } 377 378 /* enable uio/vfio intr/eventfd mapping */ 379 rte_intr_enable(pdata->pci_dev->intr_handle); 380 381 /* phy start*/ 382 pdata->phy_if.phy_start(pdata); 383 axgbe_dev_enable_tx(dev); 384 axgbe_dev_enable_rx(dev); 385 386 rte_bit_relaxed_clear32(AXGBE_STOPPED, &pdata->dev_state); 387 rte_bit_relaxed_clear32(AXGBE_DOWN, &pdata->dev_state); 388 389 axgbe_set_rx_function(dev); 390 axgbe_set_tx_function(dev); 391 return 0; 392 } 393 394 /* Stop device: disable rx and tx functions to allow for reconfiguring. */ 395 static int 396 axgbe_dev_stop(struct rte_eth_dev *dev) 397 { 398 struct axgbe_port *pdata = dev->data->dev_private; 399 400 PMD_INIT_FUNC_TRACE(); 401 402 rte_intr_disable(pdata->pci_dev->intr_handle); 403 404 if (rte_bit_relaxed_get32(AXGBE_STOPPED, &pdata->dev_state)) 405 return 0; 406 407 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 408 axgbe_dev_disable_tx(dev); 409 axgbe_dev_disable_rx(dev); 410 411 pdata->phy_if.phy_stop(pdata); 412 pdata->hw_if.exit(pdata); 413 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); 414 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 415 416 return 0; 417 } 418 419 static int 420 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 421 { 422 struct axgbe_port *pdata = dev->data->dev_private; 423 424 PMD_INIT_FUNC_TRACE(); 425 426 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); 427 428 return 0; 429 } 430 431 static int 432 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 433 { 434 struct axgbe_port *pdata = dev->data->dev_private; 435 436 PMD_INIT_FUNC_TRACE(); 437 438 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); 439 440 return 0; 441 } 442 443 static int 444 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 445 { 446 struct axgbe_port *pdata = dev->data->dev_private; 447 448 PMD_INIT_FUNC_TRACE(); 449 450 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 451 return 0; 452 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1); 453 454 return 0; 455 } 456 457 static int 458 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 459 { 460 struct axgbe_port *pdata = dev->data->dev_private; 461 462 PMD_INIT_FUNC_TRACE(); 463 464 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 465 return 0; 466 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0); 467 468 return 0; 469 } 470 471 static int 472 axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 473 { 474 struct axgbe_port *pdata = dev->data->dev_private; 475 476 /* Set Default MAC Addr */ 477 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0); 478 479 return 0; 480 } 481 482 static int 483 axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 484 uint32_t index, uint32_t pool __rte_unused) 485 { 486 struct axgbe_port *pdata = dev->data->dev_private; 487 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 488 489 if (index > hw_feat->addn_mac) { 490 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index); 491 return -EINVAL; 492 } 493 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index); 494 return 0; 495 } 496 497 static int 498 axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 499 struct rte_eth_rss_reta_entry64 *reta_conf, 500 uint16_t reta_size) 501 { 502 struct axgbe_port *pdata = dev->data->dev_private; 503 unsigned int i, idx, shift; 504 int ret; 505 506 if (!pdata->rss_enable) { 507 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 508 return -ENOTSUP; 509 } 510 511 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 512 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size); 513 return -EINVAL; 514 } 515 516 for (i = 0; i < reta_size; i++) { 517 idx = i / RTE_ETH_RETA_GROUP_SIZE; 518 shift = i % RTE_ETH_RETA_GROUP_SIZE; 519 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 520 continue; 521 pdata->rss_table[i] = reta_conf[idx].reta[shift]; 522 } 523 524 /* Program the lookup table */ 525 ret = axgbe_write_rss_lookup_table(pdata); 526 return ret; 527 } 528 529 static int 530 axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 531 struct rte_eth_rss_reta_entry64 *reta_conf, 532 uint16_t reta_size) 533 { 534 struct axgbe_port *pdata = dev->data->dev_private; 535 unsigned int i, idx, shift; 536 537 if (!pdata->rss_enable) { 538 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 539 return -ENOTSUP; 540 } 541 542 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 543 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size); 544 return -EINVAL; 545 } 546 547 for (i = 0; i < reta_size; i++) { 548 idx = i / RTE_ETH_RETA_GROUP_SIZE; 549 shift = i % RTE_ETH_RETA_GROUP_SIZE; 550 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 551 continue; 552 reta_conf[idx].reta[shift] = pdata->rss_table[i]; 553 } 554 return 0; 555 } 556 557 static int 558 axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 559 struct rte_eth_rss_conf *rss_conf) 560 { 561 struct axgbe_port *pdata = dev->data->dev_private; 562 int ret; 563 564 if (!pdata->rss_enable) { 565 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 566 return -ENOTSUP; 567 } 568 569 if (rss_conf == NULL) { 570 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n"); 571 return -EINVAL; 572 } 573 574 if (rss_conf->rss_key != NULL && 575 rss_conf->rss_key_len == AXGBE_RSS_HASH_KEY_SIZE) { 576 rte_memcpy(pdata->rss_key, rss_conf->rss_key, 577 AXGBE_RSS_HASH_KEY_SIZE); 578 /* Program the hash key */ 579 ret = axgbe_write_rss_hash_key(pdata); 580 if (ret != 0) 581 return ret; 582 } 583 584 pdata->rss_hf = rss_conf->rss_hf & AXGBE_RSS_OFFLOAD; 585 586 if (pdata->rss_hf & (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6)) 587 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); 588 if (pdata->rss_hf & 589 (RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV6_TCP)) 590 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); 591 if (pdata->rss_hf & 592 (RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV6_UDP)) 593 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); 594 595 /* Set the RSS options */ 596 AXGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 597 598 return 0; 599 } 600 601 static int 602 axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 603 struct rte_eth_rss_conf *rss_conf) 604 { 605 struct axgbe_port *pdata = dev->data->dev_private; 606 607 if (!pdata->rss_enable) { 608 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 609 return -ENOTSUP; 610 } 611 612 if (rss_conf == NULL) { 613 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n"); 614 return -EINVAL; 615 } 616 617 if (rss_conf->rss_key != NULL && 618 rss_conf->rss_key_len >= AXGBE_RSS_HASH_KEY_SIZE) { 619 rte_memcpy(rss_conf->rss_key, pdata->rss_key, 620 AXGBE_RSS_HASH_KEY_SIZE); 621 } 622 rss_conf->rss_key_len = AXGBE_RSS_HASH_KEY_SIZE; 623 rss_conf->rss_hf = pdata->rss_hf; 624 return 0; 625 } 626 627 static int 628 axgbe_dev_reset(struct rte_eth_dev *dev) 629 { 630 int ret = 0; 631 632 ret = axgbe_dev_close(dev); 633 if (ret) 634 return ret; 635 636 ret = eth_axgbe_dev_init(dev); 637 638 return ret; 639 } 640 641 static void 642 axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 643 { 644 struct axgbe_port *pdata = dev->data->dev_private; 645 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 646 647 if (index > hw_feat->addn_mac) { 648 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index); 649 return; 650 } 651 axgbe_set_mac_addn_addr(pdata, NULL, index); 652 } 653 654 static int 655 axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 656 struct rte_ether_addr *mc_addr_set, 657 uint32_t nb_mc_addr) 658 { 659 struct axgbe_port *pdata = dev->data->dev_private; 660 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 661 uint32_t index = 1; /* 0 is always default mac */ 662 uint32_t i; 663 664 if (nb_mc_addr > hw_feat->addn_mac) { 665 PMD_DRV_LOG(ERR, "Invalid Index %d\n", nb_mc_addr); 666 return -EINVAL; 667 } 668 669 /* clear unicast addresses */ 670 for (i = 1; i < hw_feat->addn_mac; i++) { 671 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i])) 672 continue; 673 memset(&dev->data->mac_addrs[i], 0, 674 sizeof(struct rte_ether_addr)); 675 } 676 677 while (nb_mc_addr--) 678 axgbe_set_mac_addn_addr(pdata, (u8 *)mc_addr_set++, index++); 679 680 return 0; 681 } 682 683 static int 684 axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 685 struct rte_ether_addr *mac_addr, uint8_t add) 686 { 687 struct axgbe_port *pdata = dev->data->dev_private; 688 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 689 690 if (!hw_feat->hash_table_size) { 691 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); 692 return -ENOTSUP; 693 } 694 695 axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add); 696 697 if (pdata->uc_hash_mac_addr > 0) { 698 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 699 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 700 } else { 701 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 702 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 703 } 704 return 0; 705 } 706 707 static int 708 axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add) 709 { 710 struct axgbe_port *pdata = dev->data->dev_private; 711 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 712 uint32_t index; 713 714 if (!hw_feat->hash_table_size) { 715 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); 716 return -ENOTSUP; 717 } 718 719 for (index = 0; index < pdata->hash_table_count; index++) { 720 if (add) 721 pdata->uc_hash_table[index] = ~0; 722 else 723 pdata->uc_hash_table[index] = 0; 724 725 PMD_DRV_LOG(DEBUG, "%s MAC hash table at Index %#x\n", 726 add ? "set" : "clear", index); 727 728 AXGMAC_IOWRITE(pdata, MAC_HTR(index), 729 pdata->uc_hash_table[index]); 730 } 731 732 if (add) { 733 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 734 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 735 } else { 736 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 737 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 738 } 739 return 0; 740 } 741 742 /* return 0 means link status changed, -1 means not changed */ 743 static int 744 axgbe_dev_link_update(struct rte_eth_dev *dev, 745 int wait_to_complete __rte_unused) 746 { 747 struct axgbe_port *pdata = dev->data->dev_private; 748 struct rte_eth_link link; 749 int ret = 0; 750 751 PMD_INIT_FUNC_TRACE(); 752 rte_delay_ms(800); 753 754 pdata->phy_if.phy_status(pdata); 755 756 memset(&link, 0, sizeof(struct rte_eth_link)); 757 link.link_duplex = pdata->phy.duplex; 758 link.link_status = pdata->phy_link; 759 link.link_speed = pdata->phy_speed; 760 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 761 RTE_ETH_LINK_SPEED_FIXED); 762 ret = rte_eth_linkstatus_set(dev, &link); 763 if (ret == -1) 764 PMD_DRV_LOG(ERR, "No change in link status\n"); 765 766 return ret; 767 } 768 769 static int 770 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 771 { 772 struct axgbe_port *pdata = dev->data->dev_private; 773 774 if (regs->data == NULL) { 775 regs->length = axgbe_regs_get_count(pdata); 776 regs->width = sizeof(uint32_t); 777 return 0; 778 } 779 780 /* Only full register dump is supported */ 781 if (regs->length && 782 regs->length != (uint32_t)axgbe_regs_get_count(pdata)) 783 return -ENOTSUP; 784 785 regs->version = pdata->pci_dev->id.vendor_id << 16 | 786 pdata->pci_dev->id.device_id; 787 axgbe_regs_dump(pdata, regs->data); 788 return 0; 789 } 790 static void axgbe_read_mmc_stats(struct axgbe_port *pdata) 791 { 792 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 793 794 /* Freeze counters */ 795 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 796 797 /* Tx counters */ 798 stats->txoctetcount_gb += 799 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO); 800 stats->txoctetcount_gb += 801 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32); 802 803 stats->txframecount_gb += 804 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO); 805 stats->txframecount_gb += 806 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32); 807 808 stats->txbroadcastframes_g += 809 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO); 810 stats->txbroadcastframes_g += 811 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32); 812 813 stats->txmulticastframes_g += 814 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO); 815 stats->txmulticastframes_g += 816 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32); 817 818 stats->tx64octets_gb += 819 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO); 820 stats->tx64octets_gb += 821 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32); 822 823 stats->tx65to127octets_gb += 824 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO); 825 stats->tx65to127octets_gb += 826 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32); 827 828 stats->tx128to255octets_gb += 829 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO); 830 stats->tx128to255octets_gb += 831 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32); 832 833 stats->tx256to511octets_gb += 834 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO); 835 stats->tx256to511octets_gb += 836 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32); 837 838 stats->tx512to1023octets_gb += 839 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO); 840 stats->tx512to1023octets_gb += 841 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32); 842 843 stats->tx1024tomaxoctets_gb += 844 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 845 stats->tx1024tomaxoctets_gb += 846 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32); 847 848 stats->txunicastframes_gb += 849 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO); 850 stats->txunicastframes_gb += 851 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32); 852 853 stats->txmulticastframes_gb += 854 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 855 stats->txmulticastframes_gb += 856 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32); 857 858 stats->txbroadcastframes_g += 859 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 860 stats->txbroadcastframes_g += 861 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32); 862 863 stats->txunderflowerror += 864 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO); 865 stats->txunderflowerror += 866 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32); 867 868 stats->txoctetcount_g += 869 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO); 870 stats->txoctetcount_g += 871 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32); 872 873 stats->txframecount_g += 874 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO); 875 stats->txframecount_g += 876 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32); 877 878 stats->txpauseframes += 879 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO); 880 stats->txpauseframes += 881 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32); 882 883 stats->txvlanframes_g += 884 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO); 885 stats->txvlanframes_g += 886 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32); 887 888 /* Rx counters */ 889 stats->rxframecount_gb += 890 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO); 891 stats->rxframecount_gb += 892 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32); 893 894 stats->rxoctetcount_gb += 895 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO); 896 stats->rxoctetcount_gb += 897 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32); 898 899 stats->rxoctetcount_g += 900 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO); 901 stats->rxoctetcount_g += 902 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32); 903 904 stats->rxbroadcastframes_g += 905 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO); 906 stats->rxbroadcastframes_g += 907 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32); 908 909 stats->rxmulticastframes_g += 910 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO); 911 stats->rxmulticastframes_g += 912 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32); 913 914 stats->rxcrcerror += 915 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO); 916 stats->rxcrcerror += 917 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32); 918 919 stats->rxrunterror += 920 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR); 921 922 stats->rxjabbererror += 923 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR); 924 925 stats->rxundersize_g += 926 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G); 927 928 stats->rxoversize_g += 929 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G); 930 931 stats->rx64octets_gb += 932 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO); 933 stats->rx64octets_gb += 934 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32); 935 936 stats->rx65to127octets_gb += 937 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO); 938 stats->rx65to127octets_gb += 939 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32); 940 941 stats->rx128to255octets_gb += 942 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO); 943 stats->rx128to255octets_gb += 944 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32); 945 946 stats->rx256to511octets_gb += 947 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO); 948 stats->rx256to511octets_gb += 949 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32); 950 951 stats->rx512to1023octets_gb += 952 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO); 953 stats->rx512to1023octets_gb += 954 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32); 955 956 stats->rx1024tomaxoctets_gb += 957 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 958 stats->rx1024tomaxoctets_gb += 959 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32); 960 961 stats->rxunicastframes_g += 962 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO); 963 stats->rxunicastframes_g += 964 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32); 965 966 stats->rxlengtherror += 967 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO); 968 stats->rxlengtherror += 969 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32); 970 971 stats->rxoutofrangetype += 972 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO); 973 stats->rxoutofrangetype += 974 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32); 975 976 stats->rxpauseframes += 977 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO); 978 stats->rxpauseframes += 979 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32); 980 981 stats->rxfifooverflow += 982 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO); 983 stats->rxfifooverflow += 984 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32); 985 986 stats->rxvlanframes_gb += 987 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO); 988 stats->rxvlanframes_gb += 989 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32); 990 991 stats->rxwatchdogerror += 992 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR); 993 994 /* Un-freeze counters */ 995 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 996 } 997 998 static int 999 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1000 unsigned int n) 1001 { 1002 struct axgbe_port *pdata = dev->data->dev_private; 1003 unsigned int i; 1004 1005 if (n < AXGBE_XSTATS_COUNT) 1006 return AXGBE_XSTATS_COUNT; 1007 1008 axgbe_read_mmc_stats(pdata); 1009 1010 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1011 stats[i].id = i; 1012 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1013 axgbe_xstats_strings[i].offset); 1014 } 1015 1016 return AXGBE_XSTATS_COUNT; 1017 } 1018 1019 static int 1020 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1021 struct rte_eth_xstat_name *xstats_names, 1022 unsigned int n) 1023 { 1024 unsigned int i; 1025 1026 if (n >= AXGBE_XSTATS_COUNT && xstats_names) { 1027 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) { 1028 snprintf(xstats_names[i].name, 1029 RTE_ETH_XSTATS_NAME_SIZE, "%s", 1030 axgbe_xstats_strings[i].name); 1031 } 1032 } 1033 1034 return AXGBE_XSTATS_COUNT; 1035 } 1036 1037 static int 1038 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1039 uint64_t *values, unsigned int n) 1040 { 1041 unsigned int i; 1042 uint64_t values_copy[AXGBE_XSTATS_COUNT]; 1043 1044 if (!ids) { 1045 struct axgbe_port *pdata = dev->data->dev_private; 1046 1047 if (n < AXGBE_XSTATS_COUNT) 1048 return AXGBE_XSTATS_COUNT; 1049 1050 axgbe_read_mmc_stats(pdata); 1051 1052 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1053 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1054 axgbe_xstats_strings[i].offset); 1055 } 1056 1057 return i; 1058 } 1059 1060 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT); 1061 1062 for (i = 0; i < n; i++) { 1063 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1064 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 1065 return -1; 1066 } 1067 values[i] = values_copy[ids[i]]; 1068 } 1069 return n; 1070 } 1071 1072 static int 1073 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 1074 const uint64_t *ids, 1075 struct rte_eth_xstat_name *xstats_names, 1076 unsigned int size) 1077 { 1078 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT]; 1079 unsigned int i; 1080 1081 if (!ids) 1082 return axgbe_dev_xstats_get_names(dev, xstats_names, size); 1083 1084 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size); 1085 1086 for (i = 0; i < size; i++) { 1087 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1088 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 1089 return -1; 1090 } 1091 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1092 } 1093 return size; 1094 } 1095 1096 static int 1097 axgbe_dev_xstats_reset(struct rte_eth_dev *dev) 1098 { 1099 struct axgbe_port *pdata = dev->data->dev_private; 1100 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 1101 1102 /* MMC registers are configured for reset on read */ 1103 axgbe_read_mmc_stats(pdata); 1104 1105 /* Reset stats */ 1106 memset(stats, 0, sizeof(*stats)); 1107 1108 return 0; 1109 } 1110 1111 static int 1112 axgbe_dev_stats_get(struct rte_eth_dev *dev, 1113 struct rte_eth_stats *stats) 1114 { 1115 struct axgbe_rx_queue *rxq; 1116 struct axgbe_tx_queue *txq; 1117 struct axgbe_port *pdata = dev->data->dev_private; 1118 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats; 1119 unsigned int i; 1120 1121 axgbe_read_mmc_stats(pdata); 1122 1123 stats->imissed = mmc_stats->rxfifooverflow; 1124 1125 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1126 rxq = dev->data->rx_queues[i]; 1127 if (rxq) { 1128 stats->q_ipackets[i] = rxq->pkts; 1129 stats->ipackets += rxq->pkts; 1130 stats->q_ibytes[i] = rxq->bytes; 1131 stats->ibytes += rxq->bytes; 1132 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed; 1133 stats->q_errors[i] = rxq->errors 1134 + rxq->rx_mbuf_alloc_failed; 1135 stats->ierrors += rxq->errors; 1136 } else { 1137 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n", 1138 dev->data->port_id); 1139 } 1140 } 1141 1142 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1143 txq = dev->data->tx_queues[i]; 1144 if (txq) { 1145 stats->q_opackets[i] = txq->pkts; 1146 stats->opackets += txq->pkts; 1147 stats->q_obytes[i] = txq->bytes; 1148 stats->obytes += txq->bytes; 1149 stats->oerrors += txq->errors; 1150 } else { 1151 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n", 1152 dev->data->port_id); 1153 } 1154 } 1155 1156 return 0; 1157 } 1158 1159 static int 1160 axgbe_dev_stats_reset(struct rte_eth_dev *dev) 1161 { 1162 struct axgbe_rx_queue *rxq; 1163 struct axgbe_tx_queue *txq; 1164 unsigned int i; 1165 1166 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1167 rxq = dev->data->rx_queues[i]; 1168 if (rxq) { 1169 rxq->pkts = 0; 1170 rxq->bytes = 0; 1171 rxq->errors = 0; 1172 rxq->rx_mbuf_alloc_failed = 0; 1173 } else { 1174 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n", 1175 dev->data->port_id); 1176 } 1177 } 1178 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1179 txq = dev->data->tx_queues[i]; 1180 if (txq) { 1181 txq->pkts = 0; 1182 txq->bytes = 0; 1183 txq->errors = 0; 1184 } else { 1185 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n", 1186 dev->data->port_id); 1187 } 1188 } 1189 1190 return 0; 1191 } 1192 1193 static int 1194 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1195 { 1196 struct axgbe_port *pdata = dev->data->dev_private; 1197 1198 dev_info->max_rx_queues = pdata->rx_ring_count; 1199 dev_info->max_tx_queues = pdata->tx_ring_count; 1200 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE; 1201 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE; 1202 dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1; 1203 dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size; 1204 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10G; 1205 1206 dev_info->rx_offload_capa = 1207 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 1208 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 1209 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | 1210 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 1211 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 1212 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 1213 RTE_ETH_RX_OFFLOAD_SCATTER | 1214 RTE_ETH_RX_OFFLOAD_KEEP_CRC; 1215 1216 dev_info->tx_offload_capa = 1217 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 1218 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | 1219 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 1220 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | 1221 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 1222 RTE_ETH_TX_OFFLOAD_TCP_CKSUM; 1223 1224 if (pdata->hw_feat.rss) { 1225 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD; 1226 dev_info->reta_size = pdata->hw_feat.hash_table_size; 1227 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE; 1228 } 1229 1230 dev_info->rx_desc_lim = rx_desc_lim; 1231 dev_info->tx_desc_lim = tx_desc_lim; 1232 1233 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1234 .rx_free_thresh = AXGBE_RX_FREE_THRESH, 1235 }; 1236 1237 dev_info->default_txconf = (struct rte_eth_txconf) { 1238 .tx_free_thresh = AXGBE_TX_FREE_THRESH, 1239 }; 1240 1241 return 0; 1242 } 1243 1244 static int 1245 axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1246 { 1247 struct axgbe_port *pdata = dev->data->dev_private; 1248 struct xgbe_fc_info fc = pdata->fc; 1249 unsigned int reg, reg_val = 0; 1250 1251 reg = MAC_Q0TFCR; 1252 reg_val = AXGMAC_IOREAD(pdata, reg); 1253 fc.low_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA); 1254 fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD); 1255 fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT); 1256 fc.autoneg = pdata->pause_autoneg; 1257 1258 if (pdata->rx_pause && pdata->tx_pause) 1259 fc.mode = RTE_ETH_FC_FULL; 1260 else if (pdata->rx_pause) 1261 fc.mode = RTE_ETH_FC_RX_PAUSE; 1262 else if (pdata->tx_pause) 1263 fc.mode = RTE_ETH_FC_TX_PAUSE; 1264 else 1265 fc.mode = RTE_ETH_FC_NONE; 1266 1267 fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024; 1268 fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024; 1269 fc_conf->pause_time = fc.pause_time[0]; 1270 fc_conf->send_xon = fc.send_xon; 1271 fc_conf->mode = fc.mode; 1272 1273 return 0; 1274 } 1275 1276 static int 1277 axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1278 { 1279 struct axgbe_port *pdata = dev->data->dev_private; 1280 struct xgbe_fc_info fc = pdata->fc; 1281 unsigned int reg, reg_val = 0; 1282 reg = MAC_Q0TFCR; 1283 1284 pdata->pause_autoneg = fc_conf->autoneg; 1285 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1286 fc.send_xon = fc_conf->send_xon; 1287 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA, 1288 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water)); 1289 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD, 1290 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water)); 1291 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time); 1292 AXGMAC_IOWRITE(pdata, reg, reg_val); 1293 fc.mode = fc_conf->mode; 1294 1295 if (fc.mode == RTE_ETH_FC_FULL) { 1296 pdata->tx_pause = 1; 1297 pdata->rx_pause = 1; 1298 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) { 1299 pdata->tx_pause = 0; 1300 pdata->rx_pause = 1; 1301 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) { 1302 pdata->tx_pause = 1; 1303 pdata->rx_pause = 0; 1304 } else { 1305 pdata->tx_pause = 0; 1306 pdata->rx_pause = 0; 1307 } 1308 1309 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1310 pdata->hw_if.config_tx_flow_control(pdata); 1311 1312 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1313 pdata->hw_if.config_rx_flow_control(pdata); 1314 1315 pdata->hw_if.config_flow_control(pdata); 1316 pdata->phy.tx_pause = pdata->tx_pause; 1317 pdata->phy.rx_pause = pdata->rx_pause; 1318 1319 return 0; 1320 } 1321 1322 static int 1323 axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 1324 struct rte_eth_pfc_conf *pfc_conf) 1325 { 1326 struct axgbe_port *pdata = dev->data->dev_private; 1327 struct xgbe_fc_info fc = pdata->fc; 1328 uint8_t tc_num; 1329 1330 tc_num = pdata->pfc_map[pfc_conf->priority]; 1331 1332 if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) { 1333 PMD_INIT_LOG(ERR, "Max supported traffic class: %d\n", 1334 pdata->hw_feat.tc_cnt); 1335 return -EINVAL; 1336 } 1337 1338 pdata->pause_autoneg = pfc_conf->fc.autoneg; 1339 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1340 fc.send_xon = pfc_conf->fc.send_xon; 1341 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA, 1342 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water)); 1343 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD, 1344 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water)); 1345 1346 switch (tc_num) { 1347 case 0: 1348 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1349 PSTC0, pfc_conf->fc.pause_time); 1350 break; 1351 case 1: 1352 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1353 PSTC1, pfc_conf->fc.pause_time); 1354 break; 1355 case 2: 1356 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1357 PSTC2, pfc_conf->fc.pause_time); 1358 break; 1359 case 3: 1360 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1361 PSTC3, pfc_conf->fc.pause_time); 1362 break; 1363 case 4: 1364 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1365 PSTC4, pfc_conf->fc.pause_time); 1366 break; 1367 case 5: 1368 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1369 PSTC5, pfc_conf->fc.pause_time); 1370 break; 1371 case 7: 1372 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1373 PSTC6, pfc_conf->fc.pause_time); 1374 break; 1375 case 6: 1376 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1377 PSTC7, pfc_conf->fc.pause_time); 1378 break; 1379 } 1380 1381 fc.mode = pfc_conf->fc.mode; 1382 1383 if (fc.mode == RTE_ETH_FC_FULL) { 1384 pdata->tx_pause = 1; 1385 pdata->rx_pause = 1; 1386 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1387 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) { 1388 pdata->tx_pause = 0; 1389 pdata->rx_pause = 1; 1390 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1391 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) { 1392 pdata->tx_pause = 1; 1393 pdata->rx_pause = 0; 1394 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1395 } else { 1396 pdata->tx_pause = 0; 1397 pdata->rx_pause = 0; 1398 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1399 } 1400 1401 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1402 pdata->hw_if.config_tx_flow_control(pdata); 1403 1404 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1405 pdata->hw_if.config_rx_flow_control(pdata); 1406 pdata->hw_if.config_flow_control(pdata); 1407 pdata->phy.tx_pause = pdata->tx_pause; 1408 pdata->phy.rx_pause = pdata->rx_pause; 1409 1410 return 0; 1411 } 1412 1413 void 1414 axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1415 struct rte_eth_rxq_info *qinfo) 1416 { 1417 struct axgbe_rx_queue *rxq; 1418 1419 rxq = dev->data->rx_queues[queue_id]; 1420 qinfo->mp = rxq->mb_pool; 1421 qinfo->scattered_rx = dev->data->scattered_rx; 1422 qinfo->nb_desc = rxq->nb_desc; 1423 qinfo->conf.rx_free_thresh = rxq->free_thresh; 1424 } 1425 1426 void 1427 axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1428 struct rte_eth_txq_info *qinfo) 1429 { 1430 struct axgbe_tx_queue *txq; 1431 1432 txq = dev->data->tx_queues[queue_id]; 1433 qinfo->nb_desc = txq->nb_desc; 1434 qinfo->conf.tx_free_thresh = txq->free_thresh; 1435 } 1436 const uint32_t * 1437 axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1438 { 1439 static const uint32_t ptypes[] = { 1440 RTE_PTYPE_L2_ETHER, 1441 RTE_PTYPE_L2_ETHER_TIMESYNC, 1442 RTE_PTYPE_L2_ETHER_LLDP, 1443 RTE_PTYPE_L2_ETHER_ARP, 1444 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1445 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 1446 RTE_PTYPE_L4_FRAG, 1447 RTE_PTYPE_L4_ICMP, 1448 RTE_PTYPE_L4_NONFRAG, 1449 RTE_PTYPE_L4_SCTP, 1450 RTE_PTYPE_L4_TCP, 1451 RTE_PTYPE_L4_UDP, 1452 RTE_PTYPE_TUNNEL_GRENAT, 1453 RTE_PTYPE_TUNNEL_IP, 1454 RTE_PTYPE_INNER_L2_ETHER, 1455 RTE_PTYPE_INNER_L2_ETHER_VLAN, 1456 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 1457 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 1458 RTE_PTYPE_INNER_L4_FRAG, 1459 RTE_PTYPE_INNER_L4_ICMP, 1460 RTE_PTYPE_INNER_L4_NONFRAG, 1461 RTE_PTYPE_INNER_L4_SCTP, 1462 RTE_PTYPE_INNER_L4_TCP, 1463 RTE_PTYPE_INNER_L4_UDP, 1464 RTE_PTYPE_UNKNOWN 1465 }; 1466 1467 if (dev->rx_pkt_burst == axgbe_recv_pkts) 1468 return ptypes; 1469 return NULL; 1470 } 1471 1472 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1473 { 1474 struct axgbe_port *pdata = dev->data->dev_private; 1475 unsigned int val; 1476 1477 /* mtu setting is forbidden if port is start */ 1478 if (dev->data->dev_started) { 1479 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", 1480 dev->data->port_id); 1481 return -EBUSY; 1482 } 1483 val = mtu > RTE_ETHER_MTU ? 1 : 0; 1484 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 1485 1486 return 0; 1487 } 1488 1489 static void 1490 axgbe_update_tstamp_time(struct axgbe_port *pdata, 1491 unsigned int sec, unsigned int nsec, int addsub) 1492 { 1493 unsigned int count = 100; 1494 uint32_t sub_val = 0; 1495 uint32_t sub_val_sec = 0xFFFFFFFF; 1496 uint32_t sub_val_nsec = 0x3B9ACA00; 1497 1498 if (addsub) { 1499 if (sec) 1500 sub_val = sub_val_sec - (sec - 1); 1501 else 1502 sub_val = sec; 1503 1504 AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val); 1505 sub_val = sub_val_nsec - nsec; 1506 AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val); 1507 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1); 1508 } else { 1509 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1510 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0); 1511 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1512 } 1513 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1514 /* Wait for time update to complete */ 1515 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1516 rte_delay_ms(1); 1517 } 1518 1519 static inline uint64_t 1520 div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) 1521 { 1522 *remainder = dividend % divisor; 1523 return dividend / divisor; 1524 } 1525 1526 static inline uint64_t 1527 div_u64(uint64_t dividend, uint32_t divisor) 1528 { 1529 uint32_t remainder; 1530 return div_u64_rem(dividend, divisor, &remainder); 1531 } 1532 1533 static int 1534 axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta) 1535 { 1536 uint64_t adjust; 1537 uint32_t addend, diff; 1538 unsigned int neg_adjust = 0; 1539 1540 if (delta < 0) { 1541 neg_adjust = 1; 1542 delta = -delta; 1543 } 1544 adjust = (uint64_t)pdata->tstamp_addend; 1545 adjust *= delta; 1546 diff = (uint32_t)div_u64(adjust, 1000000000UL); 1547 addend = (neg_adjust) ? pdata->tstamp_addend - diff : 1548 pdata->tstamp_addend + diff; 1549 pdata->tstamp_addend = addend; 1550 axgbe_update_tstamp_addend(pdata, addend); 1551 return 0; 1552 } 1553 1554 static int 1555 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 1556 { 1557 struct axgbe_port *pdata = dev->data->dev_private; 1558 struct timespec timestamp_delta; 1559 1560 axgbe_adjfreq(pdata, delta); 1561 pdata->systime_tc.nsec += delta; 1562 1563 if (delta < 0) { 1564 delta = -delta; 1565 timestamp_delta = rte_ns_to_timespec(delta); 1566 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1567 timestamp_delta.tv_nsec, 1); 1568 } else { 1569 timestamp_delta = rte_ns_to_timespec(delta); 1570 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1571 timestamp_delta.tv_nsec, 0); 1572 } 1573 return 0; 1574 } 1575 1576 static int 1577 axgbe_timesync_read_time(struct rte_eth_dev *dev, 1578 struct timespec *timestamp) 1579 { 1580 uint64_t nsec; 1581 struct axgbe_port *pdata = dev->data->dev_private; 1582 1583 nsec = AXGMAC_IOREAD(pdata, MAC_STSR); 1584 nsec *= NSEC_PER_SEC; 1585 nsec += AXGMAC_IOREAD(pdata, MAC_STNR); 1586 *timestamp = rte_ns_to_timespec(nsec); 1587 return 0; 1588 } 1589 static int 1590 axgbe_timesync_write_time(struct rte_eth_dev *dev, 1591 const struct timespec *timestamp) 1592 { 1593 unsigned int count = 100; 1594 struct axgbe_port *pdata = dev->data->dev_private; 1595 1596 AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec); 1597 AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec); 1598 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1599 /* Wait for time update to complete */ 1600 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1601 rte_delay_ms(1); 1602 if (!count) 1603 PMD_DRV_LOG(ERR, "Timed out update timestamp\n"); 1604 return 0; 1605 } 1606 1607 static void 1608 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 1609 uint32_t addend) 1610 { 1611 unsigned int count = 100; 1612 1613 AXGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1614 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1615 1616 /* Wait for addend update to complete */ 1617 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1618 rte_delay_ms(1); 1619 if (!count) 1620 PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n"); 1621 } 1622 1623 static void 1624 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 1625 unsigned int nsec) 1626 { 1627 unsigned int count = 100; 1628 1629 /*System Time Sec Update*/ 1630 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1631 /*System Time nanoSec Update*/ 1632 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1633 /*Initialize Timestamp*/ 1634 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1635 1636 /* Wait for time update to complete */ 1637 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1638 rte_delay_ms(1); 1639 if (!count) 1640 PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n"); 1641 } 1642 1643 static int 1644 axgbe_timesync_enable(struct rte_eth_dev *dev) 1645 { 1646 struct axgbe_port *pdata = dev->data->dev_private; 1647 unsigned int mac_tscr = 0; 1648 uint64_t dividend; 1649 struct timespec timestamp; 1650 uint64_t nsec; 1651 1652 /* Set one nano-second accuracy */ 1653 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1654 1655 /* Set fine timestamp update */ 1656 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1657 1658 /* Overwrite earlier timestamps */ 1659 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1660 1661 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1662 1663 /* Enabling processing of ptp over eth pkt */ 1664 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1665 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1666 /* Enable timestamp for all pkts*/ 1667 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 1668 1669 /* enabling timestamp */ 1670 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1671 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1672 1673 /* Exit if timestamping is not enabled */ 1674 if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) { 1675 PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n"); 1676 return 0; 1677 } 1678 1679 /* Sub-second Increment Value*/ 1680 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC); 1681 /* Sub-nanosecond Increment Value */ 1682 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC); 1683 1684 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 1685 dividend = 50000000; 1686 dividend <<= 32; 1687 pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate); 1688 1689 axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1690 axgbe_set_tstamp_time(pdata, 0, 0); 1691 1692 /* Initialize the timecounter */ 1693 memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter)); 1694 1695 pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK; 1696 pdata->systime_tc.cc_shift = 0; 1697 pdata->systime_tc.nsec_mask = 0; 1698 1699 PMD_DRV_LOG(DEBUG, "Initializing system time counter with realtime\n"); 1700 1701 /* Updating the counter once with clock real time */ 1702 clock_gettime(CLOCK_REALTIME, ×tamp); 1703 nsec = rte_timespec_to_ns(×tamp); 1704 nsec = rte_timecounter_update(&pdata->systime_tc, nsec); 1705 axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec); 1706 return 0; 1707 } 1708 1709 static int 1710 axgbe_timesync_disable(struct rte_eth_dev *dev) 1711 { 1712 struct axgbe_port *pdata = dev->data->dev_private; 1713 unsigned int mac_tscr = 0; 1714 1715 /*disable timestamp for all pkts*/ 1716 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0); 1717 /*disable the addened register*/ 1718 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0); 1719 /* disable timestamp update */ 1720 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0); 1721 /*disable time stamp*/ 1722 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0); 1723 return 0; 1724 } 1725 1726 static int 1727 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 1728 struct timespec *timestamp, uint32_t flags) 1729 { 1730 uint64_t nsec = 0; 1731 volatile union axgbe_rx_desc *desc; 1732 uint16_t idx, pmt; 1733 struct axgbe_rx_queue *rxq = *dev->data->rx_queues; 1734 1735 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 1736 desc = &rxq->desc[idx]; 1737 1738 while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 1739 rte_delay_ms(1); 1740 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) { 1741 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) && 1742 !AXGMAC_GET_BITS_LE(desc->write.desc3, 1743 RX_CONTEXT_DESC3, TSD)) { 1744 pmt = AXGMAC_GET_BITS_LE(desc->write.desc3, 1745 RX_CONTEXT_DESC3, PMT); 1746 nsec = rte_le_to_cpu_32(desc->write.desc1); 1747 nsec *= NSEC_PER_SEC; 1748 nsec += rte_le_to_cpu_32(desc->write.desc0); 1749 if (nsec != 0xffffffffffffffffULL) { 1750 if (pmt == 0x01) 1751 *timestamp = rte_ns_to_timespec(nsec); 1752 PMD_DRV_LOG(DEBUG, 1753 "flags = 0x%x nsec = %"PRIu64"\n", 1754 flags, nsec); 1755 } 1756 } 1757 } 1758 1759 return 0; 1760 } 1761 1762 static int 1763 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 1764 struct timespec *timestamp) 1765 { 1766 uint64_t nsec; 1767 struct axgbe_port *pdata = dev->data->dev_private; 1768 unsigned int tx_snr, tx_ssr; 1769 1770 rte_delay_us(5); 1771 if (pdata->vdata->tx_tstamp_workaround) { 1772 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1773 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1774 1775 } else { 1776 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1777 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1778 } 1779 if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) { 1780 PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n"); 1781 return 0; 1782 } 1783 nsec = tx_ssr; 1784 nsec *= NSEC_PER_SEC; 1785 nsec += tx_snr; 1786 PMD_DRV_LOG(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d\n", 1787 nsec, tx_ssr, tx_snr); 1788 *timestamp = rte_ns_to_timespec(nsec); 1789 return 0; 1790 } 1791 1792 static int 1793 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1794 { 1795 struct axgbe_port *pdata = dev->data->dev_private; 1796 unsigned long vid_bit, vid_idx; 1797 1798 vid_bit = VLAN_TABLE_BIT(vid); 1799 vid_idx = VLAN_TABLE_IDX(vid); 1800 1801 if (on) { 1802 PMD_DRV_LOG(DEBUG, "Set VLAN vid=%d for device = %s\n", 1803 vid, pdata->eth_dev->device->name); 1804 pdata->active_vlans[vid_idx] |= vid_bit; 1805 } else { 1806 PMD_DRV_LOG(DEBUG, "Reset VLAN vid=%d for device = %s\n", 1807 vid, pdata->eth_dev->device->name); 1808 pdata->active_vlans[vid_idx] &= ~vid_bit; 1809 } 1810 pdata->hw_if.update_vlan_hash_table(pdata); 1811 return 0; 1812 } 1813 1814 static int 1815 axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1816 enum rte_vlan_type vlan_type, 1817 uint16_t tpid) 1818 { 1819 struct axgbe_port *pdata = dev->data->dev_private; 1820 uint32_t reg = 0; 1821 uint32_t qinq = 0; 1822 1823 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1824 PMD_DRV_LOG(DEBUG, "EDVLP: qinq = 0x%x\n", qinq); 1825 1826 switch (vlan_type) { 1827 case RTE_ETH_VLAN_TYPE_INNER: 1828 PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_INNER\n"); 1829 if (qinq) { 1830 if (tpid != 0x8100 && tpid != 0x88a8) 1831 PMD_DRV_LOG(ERR, 1832 "tag supported 0x8100/0x88A8\n"); 1833 PMD_DRV_LOG(DEBUG, "qinq with inner tag\n"); 1834 1835 /*Enable Inner VLAN Tag */ 1836 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 1); 1837 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1838 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg); 1839 1840 } else { 1841 PMD_DRV_LOG(ERR, 1842 "Inner type not supported in single tag\n"); 1843 } 1844 break; 1845 case RTE_ETH_VLAN_TYPE_OUTER: 1846 PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_OUTER\n"); 1847 if (qinq) { 1848 PMD_DRV_LOG(DEBUG, "double tagging is enabled\n"); 1849 /*Enable outer VLAN tag*/ 1850 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 0); 1851 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1852 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg); 1853 1854 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 1); 1855 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANIR, CSVL); 1856 PMD_DRV_LOG(DEBUG, "bit CSVL = 0x%x\n", reg); 1857 } else { 1858 if (tpid != 0x8100 && tpid != 0x88a8) 1859 PMD_DRV_LOG(ERR, 1860 "tag supported 0x8100/0x88A8\n"); 1861 } 1862 break; 1863 case RTE_ETH_VLAN_TYPE_MAX: 1864 PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_MAX\n"); 1865 break; 1866 case RTE_ETH_VLAN_TYPE_UNKNOWN: 1867 PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_UNKNOWN\n"); 1868 break; 1869 } 1870 return 0; 1871 } 1872 1873 static void axgbe_vlan_extend_enable(struct axgbe_port *pdata) 1874 { 1875 int qinq = 0; 1876 1877 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 1); 1878 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1879 PMD_DRV_LOG(DEBUG, "vlan double tag enabled EDVLP:qinq=0x%x\n", qinq); 1880 } 1881 1882 static void axgbe_vlan_extend_disable(struct axgbe_port *pdata) 1883 { 1884 int qinq = 0; 1885 1886 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 0); 1887 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1888 PMD_DRV_LOG(DEBUG, "vlan double tag disable EDVLP:qinq=0x%x\n", qinq); 1889 } 1890 1891 static int 1892 axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1893 { 1894 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1895 struct axgbe_port *pdata = dev->data->dev_private; 1896 1897 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 1898 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 1899 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 1900 1901 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 1902 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { 1903 PMD_DRV_LOG(DEBUG, "Strip ON for device = %s\n", 1904 pdata->eth_dev->device->name); 1905 pdata->hw_if.enable_rx_vlan_stripping(pdata); 1906 } else { 1907 PMD_DRV_LOG(DEBUG, "Strip OFF for device = %s\n", 1908 pdata->eth_dev->device->name); 1909 pdata->hw_if.disable_rx_vlan_stripping(pdata); 1910 } 1911 } 1912 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 1913 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 1914 PMD_DRV_LOG(DEBUG, "Filter ON for device = %s\n", 1915 pdata->eth_dev->device->name); 1916 pdata->hw_if.enable_rx_vlan_filtering(pdata); 1917 } else { 1918 PMD_DRV_LOG(DEBUG, "Filter OFF for device = %s\n", 1919 pdata->eth_dev->device->name); 1920 pdata->hw_if.disable_rx_vlan_filtering(pdata); 1921 } 1922 } 1923 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 1924 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) { 1925 PMD_DRV_LOG(DEBUG, "enabling vlan extended mode\n"); 1926 axgbe_vlan_extend_enable(pdata); 1927 /* Set global registers with default ethertype*/ 1928 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER, 1929 RTE_ETHER_TYPE_VLAN); 1930 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER, 1931 RTE_ETHER_TYPE_VLAN); 1932 } else { 1933 PMD_DRV_LOG(DEBUG, "disabling vlan extended mode\n"); 1934 axgbe_vlan_extend_disable(pdata); 1935 } 1936 } 1937 return 0; 1938 } 1939 1940 static void axgbe_get_all_hw_features(struct axgbe_port *pdata) 1941 { 1942 unsigned int mac_hfr0, mac_hfr1, mac_hfr2, mac_hfr3; 1943 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 1944 1945 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R); 1946 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R); 1947 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R); 1948 mac_hfr3 = AXGMAC_IOREAD(pdata, MAC_HWF3R); 1949 1950 memset(hw_feat, 0, sizeof(*hw_feat)); 1951 1952 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR); 1953 1954 /* Hardware feature register 0 */ 1955 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 1956 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 1957 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 1958 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 1959 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 1960 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 1961 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 1962 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 1963 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 1964 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 1965 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 1966 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 1967 ADDMACADRSEL); 1968 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 1969 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 1970 1971 /* Hardware feature register 1 */ 1972 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1973 RXFIFOSIZE); 1974 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1975 TXFIFOSIZE); 1976 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1, 1977 MAC_HWF1R, ADVTHWORD); 1978 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 1979 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 1980 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 1981 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 1982 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 1983 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 1984 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 1985 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1986 HASHTBLSZ); 1987 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1988 L3L4FNUM); 1989 1990 /* Hardware feature register 2 */ 1991 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 1992 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 1993 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 1994 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 1995 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 1996 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, 1997 AUXSNAPNUM); 1998 1999 /* Hardware feature register 3 */ 2000 hw_feat->tx_q_vlan_tag_ins = AXGMAC_GET_BITS(mac_hfr3, 2001 MAC_HWF3R, CBTISEL); 2002 hw_feat->no_of_vlan_extn = AXGMAC_GET_BITS(mac_hfr3, 2003 MAC_HWF3R, NRVF); 2004 2005 /* Translate the Hash Table size into actual number */ 2006 switch (hw_feat->hash_table_size) { 2007 case 0: 2008 break; 2009 case 1: 2010 hw_feat->hash_table_size = 64; 2011 break; 2012 case 2: 2013 hw_feat->hash_table_size = 128; 2014 break; 2015 case 3: 2016 hw_feat->hash_table_size = 256; 2017 break; 2018 } 2019 2020 /* Translate the address width setting into actual number */ 2021 switch (hw_feat->dma_width) { 2022 case 0: 2023 hw_feat->dma_width = 32; 2024 break; 2025 case 1: 2026 hw_feat->dma_width = 40; 2027 break; 2028 case 2: 2029 hw_feat->dma_width = 48; 2030 break; 2031 default: 2032 hw_feat->dma_width = 32; 2033 } 2034 2035 /* The Queue, Channel and TC counts are zero based so increment them 2036 * to get the actual number 2037 */ 2038 hw_feat->rx_q_cnt++; 2039 hw_feat->tx_q_cnt++; 2040 hw_feat->rx_ch_cnt++; 2041 hw_feat->tx_ch_cnt++; 2042 hw_feat->tc_cnt++; 2043 2044 /* Translate the fifo sizes into actual numbers */ 2045 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 2046 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 2047 } 2048 2049 static void axgbe_init_all_fptrs(struct axgbe_port *pdata) 2050 { 2051 axgbe_init_function_ptrs_dev(&pdata->hw_if); 2052 axgbe_init_function_ptrs_phy(&pdata->phy_if); 2053 axgbe_init_function_ptrs_i2c(&pdata->i2c_if); 2054 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 2055 } 2056 2057 static void axgbe_set_counts(struct axgbe_port *pdata) 2058 { 2059 /* Set all the function pointers */ 2060 axgbe_init_all_fptrs(pdata); 2061 2062 /* Populate the hardware features */ 2063 axgbe_get_all_hw_features(pdata); 2064 2065 /* Set default max values if not provided */ 2066 if (!pdata->tx_max_channel_count) 2067 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 2068 if (!pdata->rx_max_channel_count) 2069 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 2070 2071 if (!pdata->tx_max_q_count) 2072 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 2073 if (!pdata->rx_max_q_count) 2074 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 2075 2076 /* Calculate the number of Tx and Rx rings to be created 2077 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 2078 * the number of Tx queues to the number of Tx channels 2079 * enabled 2080 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 2081 * number of Rx queues or maximum allowed 2082 */ 2083 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt, 2084 pdata->tx_max_channel_count); 2085 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count, 2086 pdata->tx_max_q_count); 2087 2088 pdata->tx_q_count = pdata->tx_ring_count; 2089 2090 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt, 2091 pdata->rx_max_channel_count); 2092 2093 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt, 2094 pdata->rx_max_q_count); 2095 } 2096 2097 static void axgbe_default_config(struct axgbe_port *pdata) 2098 { 2099 pdata->pblx8 = DMA_PBL_X8_ENABLE; 2100 pdata->tx_sf_mode = MTL_TSF_ENABLE; 2101 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 2102 pdata->tx_pbl = DMA_PBL_32; 2103 pdata->tx_osp_mode = DMA_OSP_ENABLE; 2104 pdata->rx_sf_mode = MTL_RSF_ENABLE; 2105 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 2106 pdata->rx_pbl = DMA_PBL_32; 2107 pdata->pause_autoneg = 1; 2108 pdata->tx_pause = 0; 2109 pdata->rx_pause = 0; 2110 pdata->phy_speed = SPEED_UNKNOWN; 2111 pdata->power_down = 0; 2112 } 2113 2114 /* 2115 * Return PCI root complex device id on success else 0 2116 */ 2117 static uint16_t 2118 get_pci_rc_devid(void) 2119 { 2120 char pci_sysfs[PATH_MAX]; 2121 const struct rte_pci_addr pci_rc_addr = {0, 0, 0, 0}; 2122 unsigned long device_id; 2123 2124 snprintf(pci_sysfs, sizeof(pci_sysfs), "%s/" PCI_PRI_FMT "/device", 2125 rte_pci_get_sysfs_path(), pci_rc_addr.domain, 2126 pci_rc_addr.bus, pci_rc_addr.devid, pci_rc_addr.function); 2127 2128 /* get device id */ 2129 if (eal_parse_sysfs_value(pci_sysfs, &device_id) < 0) { 2130 PMD_INIT_LOG(ERR, "Error in reading PCI sysfs\n"); 2131 return 0; 2132 } 2133 2134 return (uint16_t)device_id; 2135 } 2136 2137 /* Used in dev_start by primary process and then 2138 * in dev_init by secondary process when attaching to an existing ethdev. 2139 */ 2140 void 2141 axgbe_set_tx_function(struct rte_eth_dev *dev) 2142 { 2143 struct axgbe_port *pdata = dev->data->dev_private; 2144 2145 if (pdata->multi_segs_tx) 2146 dev->tx_pkt_burst = &axgbe_xmit_pkts_seg; 2147 #ifdef RTE_ARCH_X86 2148 struct axgbe_tx_queue *txq = dev->data->tx_queues[0]; 2149 if (!txq->vector_disable && 2150 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) 2151 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec; 2152 #else 2153 dev->tx_pkt_burst = &axgbe_xmit_pkts; 2154 #endif 2155 } 2156 2157 void 2158 axgbe_set_rx_function(struct rte_eth_dev *dev) 2159 { 2160 struct rte_eth_dev_data *dev_data = dev->data; 2161 uint16_t max_pkt_len; 2162 struct axgbe_port *pdata; 2163 2164 pdata = dev->data->dev_private; 2165 max_pkt_len = dev_data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 2166 if ((dev_data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) || 2167 max_pkt_len > pdata->rx_buf_size) 2168 dev_data->scattered_rx = 1; 2169 /* Scatter Rx handling */ 2170 if (dev_data->scattered_rx) 2171 dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts; 2172 else 2173 dev->rx_pkt_burst = &axgbe_recv_pkts; 2174 } 2175 2176 /* 2177 * It returns 0 on success. 2178 */ 2179 static int 2180 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) 2181 { 2182 PMD_INIT_FUNC_TRACE(); 2183 struct axgbe_port *pdata; 2184 struct rte_pci_device *pci_dev; 2185 uint32_t reg, mac_lo, mac_hi; 2186 uint32_t len; 2187 int ret; 2188 2189 eth_dev->dev_ops = &axgbe_eth_dev_ops; 2190 2191 eth_dev->rx_descriptor_status = axgbe_dev_rx_descriptor_status; 2192 eth_dev->tx_descriptor_status = axgbe_dev_tx_descriptor_status; 2193 2194 eth_dev->tx_pkt_burst = &axgbe_xmit_pkts; 2195 eth_dev->rx_pkt_burst = &axgbe_recv_pkts; 2196 2197 /* 2198 * For secondary processes, we don't initialise any further as primary 2199 * has already done this work. 2200 */ 2201 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2202 axgbe_set_tx_function(eth_dev); 2203 axgbe_set_rx_function(eth_dev); 2204 return 0; 2205 } 2206 2207 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2208 2209 pdata = eth_dev->data->dev_private; 2210 /* initial state */ 2211 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 2212 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 2213 pdata->eth_dev = eth_dev; 2214 2215 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2216 pdata->pci_dev = pci_dev; 2217 2218 pdata->xgmac_regs = 2219 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; 2220 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs 2221 + AXGBE_MAC_PROP_OFFSET); 2222 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs 2223 + AXGBE_I2C_CTRL_OFFSET); 2224 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; 2225 2226 /* version specific driver data*/ 2227 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A) 2228 pdata->vdata = &axgbe_v2a; 2229 else 2230 pdata->vdata = &axgbe_v2b; 2231 2232 /* 2233 * Use PCI root complex device ID to identify the CPU 2234 */ 2235 switch (get_pci_rc_devid()) { 2236 case AMD_PCI_RV_ROOT_COMPLEX_ID: 2237 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; 2238 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; 2239 break; 2240 case AMD_PCI_YC_ROOT_COMPLEX_ID: 2241 pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF; 2242 pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT; 2243 /* Yellow Carp devices do not need cdr workaround */ 2244 pdata->vdata->an_cdr_workaround = 0; 2245 break; 2246 case AMD_PCI_SNOWY_ROOT_COMPLEX_ID: 2247 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 2248 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 2249 break; 2250 default: 2251 PMD_DRV_LOG(ERR, "No supported devices found\n"); 2252 return -ENODEV; 2253 } 2254 2255 /* Configure the PCS indirect addressing support */ 2256 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); 2257 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 2258 pdata->xpcs_window <<= 6; 2259 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 2260 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 2261 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 2262 2263 PMD_INIT_LOG(DEBUG, 2264 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, 2265 pdata->xpcs_window_size, pdata->xpcs_window_mask); 2266 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 2267 2268 /* Retrieve the MAC address */ 2269 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 2270 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 2271 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff; 2272 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff; 2273 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff; 2274 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff; 2275 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff; 2276 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff; 2277 2278 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_MAC_ADDRS; 2279 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", len, 0); 2280 2281 if (!eth_dev->data->mac_addrs) { 2282 PMD_INIT_LOG(ERR, 2283 "Failed to alloc %u bytes needed to " 2284 "store MAC addresses", len); 2285 return -ENOMEM; 2286 } 2287 2288 /* Allocate memory for storing hash filter MAC addresses */ 2289 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS; 2290 eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr", 2291 len, 0); 2292 2293 if (eth_dev->data->hash_mac_addrs == NULL) { 2294 PMD_INIT_LOG(ERR, 2295 "Failed to allocate %d bytes needed to " 2296 "store MAC addresses", len); 2297 return -ENOMEM; 2298 } 2299 2300 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr)) 2301 rte_eth_random_addr(pdata->mac_addr.addr_bytes); 2302 2303 /* Copy the permanent MAC address */ 2304 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]); 2305 2306 /* Clock settings */ 2307 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ; 2308 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 2309 2310 /* Set the DMA coherency values */ 2311 pdata->coherent = 1; 2312 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN; 2313 pdata->arcache = AXGBE_DMA_OS_ARCACHE; 2314 pdata->awcache = AXGBE_DMA_OS_AWCACHE; 2315 2316 /* Set the maximum channels and queues */ 2317 reg = XP_IOREAD(pdata, XP_PROP_1); 2318 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA); 2319 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA); 2320 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES); 2321 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES); 2322 2323 /* Set the hardware channel and queue counts */ 2324 axgbe_set_counts(pdata); 2325 2326 /* Set the maximum fifo amounts */ 2327 reg = XP_IOREAD(pdata, XP_PROP_2); 2328 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE); 2329 pdata->tx_max_fifo_size *= 16384; 2330 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size, 2331 pdata->vdata->tx_max_fifo_size); 2332 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE); 2333 pdata->rx_max_fifo_size *= 16384; 2334 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size, 2335 pdata->vdata->rx_max_fifo_size); 2336 /* Issue software reset to DMA */ 2337 ret = pdata->hw_if.exit(pdata); 2338 if (ret) 2339 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n"); 2340 2341 /* Set default configuration data */ 2342 axgbe_default_config(pdata); 2343 2344 /* Set default max values if not provided */ 2345 if (!pdata->tx_max_fifo_size) 2346 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 2347 if (!pdata->rx_max_fifo_size) 2348 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 2349 2350 pdata->tx_desc_count = AXGBE_MAX_RING_DESC; 2351 pdata->rx_desc_count = AXGBE_MAX_RING_DESC; 2352 pthread_mutex_init(&pdata->xpcs_mutex, NULL); 2353 pthread_mutex_init(&pdata->i2c_mutex, NULL); 2354 pthread_mutex_init(&pdata->an_mutex, NULL); 2355 pthread_mutex_init(&pdata->phy_mutex, NULL); 2356 2357 ret = pdata->phy_if.phy_init(pdata); 2358 if (ret) { 2359 rte_free(eth_dev->data->mac_addrs); 2360 eth_dev->data->mac_addrs = NULL; 2361 return ret; 2362 } 2363 2364 rte_intr_callback_register(pci_dev->intr_handle, 2365 axgbe_dev_interrupt_handler, 2366 (void *)eth_dev); 2367 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 2368 eth_dev->data->port_id, pci_dev->id.vendor_id, 2369 pci_dev->id.device_id); 2370 2371 return 0; 2372 } 2373 2374 static int 2375 axgbe_dev_close(struct rte_eth_dev *eth_dev) 2376 { 2377 struct rte_pci_device *pci_dev; 2378 2379 PMD_INIT_FUNC_TRACE(); 2380 2381 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2382 return 0; 2383 2384 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2385 axgbe_dev_clear_queues(eth_dev); 2386 2387 /* disable uio intr before callback unregister */ 2388 rte_intr_disable(pci_dev->intr_handle); 2389 rte_intr_callback_unregister(pci_dev->intr_handle, 2390 axgbe_dev_interrupt_handler, 2391 (void *)eth_dev); 2392 2393 return 0; 2394 } 2395 2396 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2397 struct rte_pci_device *pci_dev) 2398 { 2399 return rte_eth_dev_pci_generic_probe(pci_dev, 2400 sizeof(struct axgbe_port), eth_axgbe_dev_init); 2401 } 2402 2403 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev) 2404 { 2405 return rte_eth_dev_pci_generic_remove(pci_dev, axgbe_dev_close); 2406 } 2407 2408 static struct rte_pci_driver rte_axgbe_pmd = { 2409 .id_table = pci_id_axgbe_map, 2410 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2411 .probe = eth_axgbe_pci_probe, 2412 .remove = eth_axgbe_pci_remove, 2413 }; 2414 2415 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd); 2416 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map); 2417 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 2418 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_init, init, NOTICE); 2419 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_driver, driver, NOTICE); 2420