1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_rxtx.h" 7 #include "axgbe_ethdev.h" 8 #include "axgbe_common.h" 9 #include "axgbe_phy.h" 10 #include "axgbe_regs.h" 11 #include "rte_time.h" 12 13 #include "eal_filesystem.h" 14 15 #ifdef RTE_ARCH_X86 16 #include <cpuid.h> 17 #else 18 #define __cpuid(n, a, b, c, d) 19 #endif 20 21 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); 22 static int axgbe_dev_configure(struct rte_eth_dev *dev); 23 static int axgbe_dev_start(struct rte_eth_dev *dev); 24 static int axgbe_dev_stop(struct rte_eth_dev *dev); 25 static void axgbe_dev_interrupt_handler(void *param); 26 static int axgbe_dev_close(struct rte_eth_dev *dev); 27 static int axgbe_dev_reset(struct rte_eth_dev *dev); 28 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 29 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 30 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 31 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 32 static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, 33 struct rte_ether_addr *mac_addr); 34 static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, 35 struct rte_ether_addr *mac_addr, 36 uint32_t index, 37 uint32_t vmdq); 38 static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 39 static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 40 struct rte_ether_addr *mc_addr_set, 41 uint32_t nb_mc_addr); 42 static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 43 struct rte_ether_addr *mac_addr, 44 uint8_t add); 45 static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, 46 uint8_t add); 47 static int axgbe_dev_link_update(struct rte_eth_dev *dev, 48 int wait_to_complete); 49 static int axgbe_dev_get_regs(struct rte_eth_dev *dev, 50 struct rte_dev_reg_info *regs); 51 static int axgbe_dev_stats_get(struct rte_eth_dev *dev, 52 struct rte_eth_stats *stats); 53 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev); 54 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev, 55 struct rte_eth_xstat *stats, 56 unsigned int n); 57 static int 58 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 59 struct rte_eth_xstat_name *xstats_names, 60 unsigned int size); 61 static int 62 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 63 const uint64_t *ids, 64 uint64_t *values, 65 unsigned int n); 66 static int 67 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 68 const uint64_t *ids, 69 struct rte_eth_xstat_name *xstats_names, 70 unsigned int size); 71 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev); 72 static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 73 struct rte_eth_rss_reta_entry64 *reta_conf, 74 uint16_t reta_size); 75 static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 76 struct rte_eth_rss_reta_entry64 *reta_conf, 77 uint16_t reta_size); 78 static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 79 struct rte_eth_rss_conf *rss_conf); 80 static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 81 struct rte_eth_rss_conf *rss_conf); 82 static int axgbe_dev_info_get(struct rte_eth_dev *dev, 83 struct rte_eth_dev_info *dev_info); 84 static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, 85 struct rte_eth_fc_conf *fc_conf); 86 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, 87 struct rte_eth_fc_conf *fc_conf); 88 static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 89 struct rte_eth_pfc_conf *pfc_conf); 90 static void axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 91 struct rte_eth_rxq_info *qinfo); 92 static void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 93 struct rte_eth_txq_info *qinfo); 94 const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); 95 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 96 97 static int 98 axgbe_timesync_enable(struct rte_eth_dev *dev); 99 static int 100 axgbe_timesync_disable(struct rte_eth_dev *dev); 101 static int 102 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 103 struct timespec *timestamp, uint32_t flags); 104 static int 105 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 106 struct timespec *timestamp); 107 static int 108 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 109 static int 110 axgbe_timesync_read_time(struct rte_eth_dev *dev, 111 struct timespec *timestamp); 112 static int 113 axgbe_timesync_write_time(struct rte_eth_dev *dev, 114 const struct timespec *timestamp); 115 static void 116 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 117 unsigned int nsec); 118 static void 119 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 120 unsigned int addend); 121 static int 122 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on); 123 static int axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 124 enum rte_vlan_type vlan_type, uint16_t tpid); 125 static int axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 126 127 struct axgbe_xstats { 128 char name[RTE_ETH_XSTATS_NAME_SIZE]; 129 int offset; 130 }; 131 132 #define AXGMAC_MMC_STAT(_string, _var) \ 133 { _string, \ 134 offsetof(struct axgbe_mmc_stats, _var), \ 135 } 136 137 static const struct axgbe_xstats axgbe_xstats_strings[] = { 138 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb), 139 AXGMAC_MMC_STAT("tx_packets", txframecount_gb), 140 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb), 141 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb), 142 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb), 143 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g), 144 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb), 145 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb), 146 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb), 147 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb), 148 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb), 149 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb), 150 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror), 151 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes), 152 153 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb), 154 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb), 155 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g), 156 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g), 157 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g), 158 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb), 159 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb), 160 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb), 161 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb), 162 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb), 163 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb), 164 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb), 165 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g), 166 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g), 167 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror), 168 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror), 169 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror), 170 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror), 171 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype), 172 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow), 173 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror), 174 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes), 175 }; 176 177 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings) 178 179 /* The set of PCI devices this driver supports */ 180 #define AMD_PCI_VENDOR_ID 0x1022 181 182 #define Fam17h 0x17 183 #define Fam19h 0x19 184 185 #define CPUID_VENDOR_AuthenticAMD_ebx 0x68747541 186 #define CPUID_VENDOR_AuthenticAMD_ecx 0x444d4163 187 #define CPUID_VENDOR_AuthenticAMD_edx 0x69746e65 188 189 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 190 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459 191 192 static const struct rte_pci_id pci_id_axgbe_map[] = { 193 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)}, 194 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)}, 195 { .vendor_id = 0, }, 196 }; 197 198 static struct axgbe_version_data axgbe_v2a = { 199 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 200 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 201 .mmc_64bit = 1, 202 .tx_max_fifo_size = 229376, 203 .rx_max_fifo_size = 229376, 204 .tx_tstamp_workaround = 1, 205 .ecc_support = 1, 206 .i2c_support = 1, 207 .an_cdr_workaround = 1, 208 }; 209 210 static struct axgbe_version_data axgbe_v2b = { 211 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 212 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 213 .mmc_64bit = 1, 214 .tx_max_fifo_size = 65536, 215 .rx_max_fifo_size = 65536, 216 .tx_tstamp_workaround = 1, 217 .ecc_support = 1, 218 .i2c_support = 1, 219 .an_cdr_workaround = 1, 220 }; 221 222 static const struct rte_eth_desc_lim rx_desc_lim = { 223 .nb_max = AXGBE_MAX_RING_DESC, 224 .nb_min = AXGBE_MIN_RING_DESC, 225 .nb_align = 8, 226 }; 227 228 static const struct rte_eth_desc_lim tx_desc_lim = { 229 .nb_max = AXGBE_MAX_RING_DESC, 230 .nb_min = AXGBE_MIN_RING_DESC, 231 .nb_align = 8, 232 }; 233 234 static const struct eth_dev_ops axgbe_eth_dev_ops = { 235 .dev_configure = axgbe_dev_configure, 236 .dev_start = axgbe_dev_start, 237 .dev_stop = axgbe_dev_stop, 238 .dev_close = axgbe_dev_close, 239 .dev_reset = axgbe_dev_reset, 240 .promiscuous_enable = axgbe_dev_promiscuous_enable, 241 .promiscuous_disable = axgbe_dev_promiscuous_disable, 242 .allmulticast_enable = axgbe_dev_allmulticast_enable, 243 .allmulticast_disable = axgbe_dev_allmulticast_disable, 244 .mac_addr_set = axgbe_dev_mac_addr_set, 245 .mac_addr_add = axgbe_dev_mac_addr_add, 246 .mac_addr_remove = axgbe_dev_mac_addr_remove, 247 .set_mc_addr_list = axgbe_dev_set_mc_addr_list, 248 .uc_hash_table_set = axgbe_dev_uc_hash_table_set, 249 .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set, 250 .link_update = axgbe_dev_link_update, 251 .get_reg = axgbe_dev_get_regs, 252 .stats_get = axgbe_dev_stats_get, 253 .stats_reset = axgbe_dev_stats_reset, 254 .xstats_get = axgbe_dev_xstats_get, 255 .xstats_reset = axgbe_dev_xstats_reset, 256 .xstats_get_names = axgbe_dev_xstats_get_names, 257 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id, 258 .xstats_get_by_id = axgbe_dev_xstats_get_by_id, 259 .reta_update = axgbe_dev_rss_reta_update, 260 .reta_query = axgbe_dev_rss_reta_query, 261 .rss_hash_update = axgbe_dev_rss_hash_update, 262 .rss_hash_conf_get = axgbe_dev_rss_hash_conf_get, 263 .dev_infos_get = axgbe_dev_info_get, 264 .rx_queue_setup = axgbe_dev_rx_queue_setup, 265 .rx_queue_release = axgbe_dev_rx_queue_release, 266 .tx_queue_setup = axgbe_dev_tx_queue_setup, 267 .tx_queue_release = axgbe_dev_tx_queue_release, 268 .flow_ctrl_get = axgbe_flow_ctrl_get, 269 .flow_ctrl_set = axgbe_flow_ctrl_set, 270 .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set, 271 .rxq_info_get = axgbe_rxq_info_get, 272 .txq_info_get = axgbe_txq_info_get, 273 .dev_supported_ptypes_get = axgbe_dev_supported_ptypes_get, 274 .mtu_set = axgb_mtu_set, 275 .vlan_filter_set = axgbe_vlan_filter_set, 276 .vlan_tpid_set = axgbe_vlan_tpid_set, 277 .vlan_offload_set = axgbe_vlan_offload_set, 278 .timesync_enable = axgbe_timesync_enable, 279 .timesync_disable = axgbe_timesync_disable, 280 .timesync_read_rx_timestamp = axgbe_timesync_read_rx_timestamp, 281 .timesync_read_tx_timestamp = axgbe_timesync_read_tx_timestamp, 282 .timesync_adjust_time = axgbe_timesync_adjust_time, 283 .timesync_read_time = axgbe_timesync_read_time, 284 .timesync_write_time = axgbe_timesync_write_time, 285 .fw_version_get = axgbe_dev_fw_version_get, 286 }; 287 288 static int axgbe_phy_reset(struct axgbe_port *pdata) 289 { 290 pdata->phy_link = -1; 291 pdata->phy_speed = SPEED_UNKNOWN; 292 return pdata->phy_if.phy_reset(pdata); 293 } 294 295 /* 296 * Interrupt handler triggered by NIC for handling 297 * specific interrupt. 298 * 299 * @param handle 300 * Pointer to interrupt handle. 301 * @param param 302 * The address of parameter (struct rte_eth_dev *) registered before. 303 * 304 * @return 305 * void 306 */ 307 static void 308 axgbe_dev_interrupt_handler(void *param) 309 { 310 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 311 struct axgbe_port *pdata = dev->data->dev_private; 312 unsigned int dma_isr, dma_ch_isr; 313 314 pdata->phy_if.an_isr(pdata); 315 /*DMA related interrupts*/ 316 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR); 317 PMD_DRV_LOG(DEBUG, "DMA_ISR=%#010x\n", dma_isr); 318 if (dma_isr) { 319 if (dma_isr & 1) { 320 dma_ch_isr = 321 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *) 322 pdata->rx_queues[0], 323 DMA_CH_SR); 324 PMD_DRV_LOG(DEBUG, "DMA_CH0_ISR=%#010x\n", dma_ch_isr); 325 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *) 326 pdata->rx_queues[0], 327 DMA_CH_SR, dma_ch_isr); 328 } 329 } 330 /* Unmask interrupts since disabled after generation */ 331 rte_intr_ack(pdata->pci_dev->intr_handle); 332 } 333 334 /* 335 * Configure device link speed and setup link. 336 * It returns 0 on success. 337 */ 338 static int 339 axgbe_dev_configure(struct rte_eth_dev *dev) 340 { 341 struct axgbe_port *pdata = dev->data->dev_private; 342 /* Checksum offload to hardware */ 343 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads & 344 RTE_ETH_RX_OFFLOAD_CHECKSUM; 345 return 0; 346 } 347 348 static int 349 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev) 350 { 351 struct axgbe_port *pdata = dev->data->dev_private; 352 353 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) 354 pdata->rss_enable = 1; 355 else if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_NONE) 356 pdata->rss_enable = 0; 357 else 358 return -1; 359 return 0; 360 } 361 362 static int 363 axgbe_dev_start(struct rte_eth_dev *dev) 364 { 365 struct axgbe_port *pdata = dev->data->dev_private; 366 int ret; 367 368 dev->dev_ops = &axgbe_eth_dev_ops; 369 370 PMD_INIT_FUNC_TRACE(); 371 372 /* Multiqueue RSS */ 373 ret = axgbe_dev_rx_mq_config(dev); 374 if (ret) { 375 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n"); 376 return ret; 377 } 378 ret = axgbe_phy_reset(pdata); 379 if (ret) { 380 PMD_DRV_LOG(ERR, "phy reset failed\n"); 381 return ret; 382 } 383 ret = pdata->hw_if.init(pdata); 384 if (ret) { 385 PMD_DRV_LOG(ERR, "dev_init failed\n"); 386 return ret; 387 } 388 389 /* enable uio/vfio intr/eventfd mapping */ 390 rte_intr_enable(pdata->pci_dev->intr_handle); 391 392 /* phy start*/ 393 pdata->phy_if.phy_start(pdata); 394 axgbe_dev_enable_tx(dev); 395 axgbe_dev_enable_rx(dev); 396 397 rte_bit_relaxed_clear32(AXGBE_STOPPED, &pdata->dev_state); 398 rte_bit_relaxed_clear32(AXGBE_DOWN, &pdata->dev_state); 399 400 axgbe_set_rx_function(dev); 401 axgbe_set_tx_function(dev); 402 return 0; 403 } 404 405 /* Stop device: disable rx and tx functions to allow for reconfiguring. */ 406 static int 407 axgbe_dev_stop(struct rte_eth_dev *dev) 408 { 409 struct axgbe_port *pdata = dev->data->dev_private; 410 411 PMD_INIT_FUNC_TRACE(); 412 413 rte_intr_disable(pdata->pci_dev->intr_handle); 414 415 if (rte_bit_relaxed_get32(AXGBE_STOPPED, &pdata->dev_state)) 416 return 0; 417 418 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 419 axgbe_dev_disable_tx(dev); 420 axgbe_dev_disable_rx(dev); 421 422 pdata->phy_if.phy_stop(pdata); 423 pdata->hw_if.exit(pdata); 424 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); 425 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 426 427 return 0; 428 } 429 430 static int 431 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 432 { 433 struct axgbe_port *pdata = dev->data->dev_private; 434 435 PMD_INIT_FUNC_TRACE(); 436 437 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); 438 439 return 0; 440 } 441 442 static int 443 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 444 { 445 struct axgbe_port *pdata = dev->data->dev_private; 446 447 PMD_INIT_FUNC_TRACE(); 448 449 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); 450 451 return 0; 452 } 453 454 static int 455 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 456 { 457 struct axgbe_port *pdata = dev->data->dev_private; 458 459 PMD_INIT_FUNC_TRACE(); 460 461 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 462 return 0; 463 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1); 464 465 return 0; 466 } 467 468 static int 469 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 470 { 471 struct axgbe_port *pdata = dev->data->dev_private; 472 473 PMD_INIT_FUNC_TRACE(); 474 475 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 476 return 0; 477 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0); 478 479 return 0; 480 } 481 482 static int 483 axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 484 { 485 struct axgbe_port *pdata = dev->data->dev_private; 486 487 /* Set Default MAC Addr */ 488 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0); 489 490 return 0; 491 } 492 493 static int 494 axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 495 uint32_t index, uint32_t pool __rte_unused) 496 { 497 struct axgbe_port *pdata = dev->data->dev_private; 498 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 499 500 if (index > hw_feat->addn_mac) { 501 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index); 502 return -EINVAL; 503 } 504 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index); 505 return 0; 506 } 507 508 static int 509 axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 510 struct rte_eth_rss_reta_entry64 *reta_conf, 511 uint16_t reta_size) 512 { 513 struct axgbe_port *pdata = dev->data->dev_private; 514 unsigned int i, idx, shift; 515 int ret; 516 517 if (!pdata->rss_enable) { 518 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 519 return -ENOTSUP; 520 } 521 522 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 523 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size); 524 return -EINVAL; 525 } 526 527 for (i = 0; i < reta_size; i++) { 528 idx = i / RTE_ETH_RETA_GROUP_SIZE; 529 shift = i % RTE_ETH_RETA_GROUP_SIZE; 530 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 531 continue; 532 pdata->rss_table[i] = reta_conf[idx].reta[shift]; 533 } 534 535 /* Program the lookup table */ 536 ret = axgbe_write_rss_lookup_table(pdata); 537 return ret; 538 } 539 540 static int 541 axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 542 struct rte_eth_rss_reta_entry64 *reta_conf, 543 uint16_t reta_size) 544 { 545 struct axgbe_port *pdata = dev->data->dev_private; 546 unsigned int i, idx, shift; 547 548 if (!pdata->rss_enable) { 549 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 550 return -ENOTSUP; 551 } 552 553 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 554 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size); 555 return -EINVAL; 556 } 557 558 for (i = 0; i < reta_size; i++) { 559 idx = i / RTE_ETH_RETA_GROUP_SIZE; 560 shift = i % RTE_ETH_RETA_GROUP_SIZE; 561 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 562 continue; 563 reta_conf[idx].reta[shift] = pdata->rss_table[i]; 564 } 565 return 0; 566 } 567 568 static int 569 axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 570 struct rte_eth_rss_conf *rss_conf) 571 { 572 struct axgbe_port *pdata = dev->data->dev_private; 573 int ret; 574 575 if (!pdata->rss_enable) { 576 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 577 return -ENOTSUP; 578 } 579 580 if (rss_conf == NULL) { 581 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n"); 582 return -EINVAL; 583 } 584 585 if (rss_conf->rss_key != NULL && 586 rss_conf->rss_key_len == AXGBE_RSS_HASH_KEY_SIZE) { 587 rte_memcpy(pdata->rss_key, rss_conf->rss_key, 588 AXGBE_RSS_HASH_KEY_SIZE); 589 /* Program the hash key */ 590 ret = axgbe_write_rss_hash_key(pdata); 591 if (ret != 0) 592 return ret; 593 } 594 595 pdata->rss_hf = rss_conf->rss_hf & AXGBE_RSS_OFFLOAD; 596 597 if (pdata->rss_hf & (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6)) 598 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); 599 if (pdata->rss_hf & 600 (RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV6_TCP)) 601 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); 602 if (pdata->rss_hf & 603 (RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV6_UDP)) 604 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); 605 606 /* Set the RSS options */ 607 AXGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 608 609 return 0; 610 } 611 612 static int 613 axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 614 struct rte_eth_rss_conf *rss_conf) 615 { 616 struct axgbe_port *pdata = dev->data->dev_private; 617 618 if (!pdata->rss_enable) { 619 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 620 return -ENOTSUP; 621 } 622 623 if (rss_conf == NULL) { 624 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n"); 625 return -EINVAL; 626 } 627 628 if (rss_conf->rss_key != NULL && 629 rss_conf->rss_key_len >= AXGBE_RSS_HASH_KEY_SIZE) { 630 rte_memcpy(rss_conf->rss_key, pdata->rss_key, 631 AXGBE_RSS_HASH_KEY_SIZE); 632 } 633 rss_conf->rss_key_len = AXGBE_RSS_HASH_KEY_SIZE; 634 rss_conf->rss_hf = pdata->rss_hf; 635 return 0; 636 } 637 638 static int 639 axgbe_dev_reset(struct rte_eth_dev *dev) 640 { 641 int ret = 0; 642 643 ret = axgbe_dev_close(dev); 644 if (ret) 645 return ret; 646 647 ret = eth_axgbe_dev_init(dev); 648 649 return ret; 650 } 651 652 static void 653 axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 654 { 655 struct axgbe_port *pdata = dev->data->dev_private; 656 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 657 658 if (index > hw_feat->addn_mac) { 659 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index); 660 return; 661 } 662 axgbe_set_mac_addn_addr(pdata, NULL, index); 663 } 664 665 static int 666 axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 667 struct rte_ether_addr *mc_addr_set, 668 uint32_t nb_mc_addr) 669 { 670 struct axgbe_port *pdata = dev->data->dev_private; 671 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 672 uint32_t index = 1; /* 0 is always default mac */ 673 uint32_t i; 674 675 if (nb_mc_addr > hw_feat->addn_mac) { 676 PMD_DRV_LOG(ERR, "Invalid Index %d\n", nb_mc_addr); 677 return -EINVAL; 678 } 679 680 /* clear unicast addresses */ 681 for (i = 1; i < hw_feat->addn_mac; i++) { 682 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i])) 683 continue; 684 memset(&dev->data->mac_addrs[i], 0, 685 sizeof(struct rte_ether_addr)); 686 } 687 688 while (nb_mc_addr--) 689 axgbe_set_mac_addn_addr(pdata, (u8 *)mc_addr_set++, index++); 690 691 return 0; 692 } 693 694 static int 695 axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 696 struct rte_ether_addr *mac_addr, uint8_t add) 697 { 698 struct axgbe_port *pdata = dev->data->dev_private; 699 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 700 701 if (!hw_feat->hash_table_size) { 702 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); 703 return -ENOTSUP; 704 } 705 706 axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add); 707 708 if (pdata->uc_hash_mac_addr > 0) { 709 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 710 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 711 } else { 712 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 713 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 714 } 715 return 0; 716 } 717 718 static int 719 axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add) 720 { 721 struct axgbe_port *pdata = dev->data->dev_private; 722 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 723 uint32_t index; 724 725 if (!hw_feat->hash_table_size) { 726 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); 727 return -ENOTSUP; 728 } 729 730 for (index = 0; index < pdata->hash_table_count; index++) { 731 if (add) 732 pdata->uc_hash_table[index] = ~0; 733 else 734 pdata->uc_hash_table[index] = 0; 735 736 PMD_DRV_LOG(DEBUG, "%s MAC hash table at Index %#x\n", 737 add ? "set" : "clear", index); 738 739 AXGMAC_IOWRITE(pdata, MAC_HTR(index), 740 pdata->uc_hash_table[index]); 741 } 742 743 if (add) { 744 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 745 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 746 } else { 747 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 748 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 749 } 750 return 0; 751 } 752 753 /* return 0 means link status changed, -1 means not changed */ 754 static int 755 axgbe_dev_link_update(struct rte_eth_dev *dev, 756 int wait_to_complete __rte_unused) 757 { 758 struct axgbe_port *pdata = dev->data->dev_private; 759 struct rte_eth_link link; 760 int ret = 0; 761 762 PMD_INIT_FUNC_TRACE(); 763 rte_delay_ms(800); 764 765 pdata->phy_if.phy_status(pdata); 766 767 memset(&link, 0, sizeof(struct rte_eth_link)); 768 link.link_duplex = pdata->phy.duplex; 769 link.link_status = pdata->phy_link; 770 link.link_speed = pdata->phy_speed; 771 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 772 RTE_ETH_LINK_SPEED_FIXED); 773 ret = rte_eth_linkstatus_set(dev, &link); 774 if (ret == -1) 775 PMD_DRV_LOG(ERR, "No change in link status\n"); 776 777 return ret; 778 } 779 780 static int 781 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 782 { 783 struct axgbe_port *pdata = dev->data->dev_private; 784 785 if (regs->data == NULL) { 786 regs->length = axgbe_regs_get_count(pdata); 787 regs->width = sizeof(uint32_t); 788 return 0; 789 } 790 791 /* Only full register dump is supported */ 792 if (regs->length && 793 regs->length != (uint32_t)axgbe_regs_get_count(pdata)) 794 return -ENOTSUP; 795 796 regs->version = pdata->pci_dev->id.vendor_id << 16 | 797 pdata->pci_dev->id.device_id; 798 axgbe_regs_dump(pdata, regs->data); 799 return 0; 800 } 801 static void axgbe_read_mmc_stats(struct axgbe_port *pdata) 802 { 803 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 804 805 /* Freeze counters */ 806 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 807 808 /* Tx counters */ 809 stats->txoctetcount_gb += 810 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO); 811 stats->txoctetcount_gb += 812 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32); 813 814 stats->txframecount_gb += 815 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO); 816 stats->txframecount_gb += 817 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32); 818 819 stats->txbroadcastframes_g += 820 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO); 821 stats->txbroadcastframes_g += 822 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32); 823 824 stats->txmulticastframes_g += 825 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO); 826 stats->txmulticastframes_g += 827 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32); 828 829 stats->tx64octets_gb += 830 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO); 831 stats->tx64octets_gb += 832 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32); 833 834 stats->tx65to127octets_gb += 835 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO); 836 stats->tx65to127octets_gb += 837 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32); 838 839 stats->tx128to255octets_gb += 840 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO); 841 stats->tx128to255octets_gb += 842 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32); 843 844 stats->tx256to511octets_gb += 845 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO); 846 stats->tx256to511octets_gb += 847 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32); 848 849 stats->tx512to1023octets_gb += 850 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO); 851 stats->tx512to1023octets_gb += 852 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32); 853 854 stats->tx1024tomaxoctets_gb += 855 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 856 stats->tx1024tomaxoctets_gb += 857 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32); 858 859 stats->txunicastframes_gb += 860 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO); 861 stats->txunicastframes_gb += 862 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32); 863 864 stats->txmulticastframes_gb += 865 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 866 stats->txmulticastframes_gb += 867 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32); 868 869 stats->txbroadcastframes_g += 870 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 871 stats->txbroadcastframes_g += 872 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32); 873 874 stats->txunderflowerror += 875 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO); 876 stats->txunderflowerror += 877 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32); 878 879 stats->txoctetcount_g += 880 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO); 881 stats->txoctetcount_g += 882 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32); 883 884 stats->txframecount_g += 885 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO); 886 stats->txframecount_g += 887 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32); 888 889 stats->txpauseframes += 890 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO); 891 stats->txpauseframes += 892 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32); 893 894 stats->txvlanframes_g += 895 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO); 896 stats->txvlanframes_g += 897 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32); 898 899 /* Rx counters */ 900 stats->rxframecount_gb += 901 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO); 902 stats->rxframecount_gb += 903 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32); 904 905 stats->rxoctetcount_gb += 906 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO); 907 stats->rxoctetcount_gb += 908 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32); 909 910 stats->rxoctetcount_g += 911 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO); 912 stats->rxoctetcount_g += 913 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32); 914 915 stats->rxbroadcastframes_g += 916 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO); 917 stats->rxbroadcastframes_g += 918 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32); 919 920 stats->rxmulticastframes_g += 921 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO); 922 stats->rxmulticastframes_g += 923 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32); 924 925 stats->rxcrcerror += 926 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO); 927 stats->rxcrcerror += 928 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32); 929 930 stats->rxrunterror += 931 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR); 932 933 stats->rxjabbererror += 934 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR); 935 936 stats->rxundersize_g += 937 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G); 938 939 stats->rxoversize_g += 940 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G); 941 942 stats->rx64octets_gb += 943 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO); 944 stats->rx64octets_gb += 945 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32); 946 947 stats->rx65to127octets_gb += 948 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO); 949 stats->rx65to127octets_gb += 950 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32); 951 952 stats->rx128to255octets_gb += 953 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO); 954 stats->rx128to255octets_gb += 955 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32); 956 957 stats->rx256to511octets_gb += 958 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO); 959 stats->rx256to511octets_gb += 960 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32); 961 962 stats->rx512to1023octets_gb += 963 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO); 964 stats->rx512to1023octets_gb += 965 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32); 966 967 stats->rx1024tomaxoctets_gb += 968 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 969 stats->rx1024tomaxoctets_gb += 970 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32); 971 972 stats->rxunicastframes_g += 973 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO); 974 stats->rxunicastframes_g += 975 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32); 976 977 stats->rxlengtherror += 978 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO); 979 stats->rxlengtherror += 980 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32); 981 982 stats->rxoutofrangetype += 983 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO); 984 stats->rxoutofrangetype += 985 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32); 986 987 stats->rxpauseframes += 988 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO); 989 stats->rxpauseframes += 990 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32); 991 992 stats->rxfifooverflow += 993 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO); 994 stats->rxfifooverflow += 995 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32); 996 997 stats->rxvlanframes_gb += 998 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO); 999 stats->rxvlanframes_gb += 1000 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32); 1001 1002 stats->rxwatchdogerror += 1003 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR); 1004 1005 /* Un-freeze counters */ 1006 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 1007 } 1008 1009 static int 1010 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1011 unsigned int n) 1012 { 1013 struct axgbe_port *pdata = dev->data->dev_private; 1014 unsigned int i; 1015 1016 if (n < AXGBE_XSTATS_COUNT) 1017 return AXGBE_XSTATS_COUNT; 1018 1019 axgbe_read_mmc_stats(pdata); 1020 1021 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1022 stats[i].id = i; 1023 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1024 axgbe_xstats_strings[i].offset); 1025 } 1026 1027 return AXGBE_XSTATS_COUNT; 1028 } 1029 1030 static int 1031 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1032 struct rte_eth_xstat_name *xstats_names, 1033 unsigned int n) 1034 { 1035 unsigned int i; 1036 1037 if (n >= AXGBE_XSTATS_COUNT && xstats_names) { 1038 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) { 1039 snprintf(xstats_names[i].name, 1040 RTE_ETH_XSTATS_NAME_SIZE, "%s", 1041 axgbe_xstats_strings[i].name); 1042 } 1043 } 1044 1045 return AXGBE_XSTATS_COUNT; 1046 } 1047 1048 static int 1049 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1050 uint64_t *values, unsigned int n) 1051 { 1052 unsigned int i; 1053 uint64_t values_copy[AXGBE_XSTATS_COUNT]; 1054 1055 if (!ids) { 1056 struct axgbe_port *pdata = dev->data->dev_private; 1057 1058 if (n < AXGBE_XSTATS_COUNT) 1059 return AXGBE_XSTATS_COUNT; 1060 1061 axgbe_read_mmc_stats(pdata); 1062 1063 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1064 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1065 axgbe_xstats_strings[i].offset); 1066 } 1067 1068 return i; 1069 } 1070 1071 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT); 1072 1073 for (i = 0; i < n; i++) { 1074 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1075 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 1076 return -1; 1077 } 1078 values[i] = values_copy[ids[i]]; 1079 } 1080 return n; 1081 } 1082 1083 static int 1084 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 1085 const uint64_t *ids, 1086 struct rte_eth_xstat_name *xstats_names, 1087 unsigned int size) 1088 { 1089 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT]; 1090 unsigned int i; 1091 1092 if (!ids) 1093 return axgbe_dev_xstats_get_names(dev, xstats_names, size); 1094 1095 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size); 1096 1097 for (i = 0; i < size; i++) { 1098 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1099 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 1100 return -1; 1101 } 1102 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1103 } 1104 return size; 1105 } 1106 1107 static int 1108 axgbe_dev_xstats_reset(struct rte_eth_dev *dev) 1109 { 1110 struct axgbe_port *pdata = dev->data->dev_private; 1111 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 1112 1113 /* MMC registers are configured for reset on read */ 1114 axgbe_read_mmc_stats(pdata); 1115 1116 /* Reset stats */ 1117 memset(stats, 0, sizeof(*stats)); 1118 1119 return 0; 1120 } 1121 1122 static int 1123 axgbe_dev_stats_get(struct rte_eth_dev *dev, 1124 struct rte_eth_stats *stats) 1125 { 1126 struct axgbe_rx_queue *rxq; 1127 struct axgbe_tx_queue *txq; 1128 struct axgbe_port *pdata = dev->data->dev_private; 1129 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats; 1130 unsigned int i; 1131 1132 axgbe_read_mmc_stats(pdata); 1133 1134 stats->imissed = mmc_stats->rxfifooverflow; 1135 1136 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1137 rxq = dev->data->rx_queues[i]; 1138 if (rxq) { 1139 stats->q_ipackets[i] = rxq->pkts; 1140 stats->ipackets += rxq->pkts; 1141 stats->q_ibytes[i] = rxq->bytes; 1142 stats->ibytes += rxq->bytes; 1143 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed; 1144 stats->q_errors[i] = rxq->errors 1145 + rxq->rx_mbuf_alloc_failed; 1146 stats->ierrors += rxq->errors; 1147 } else { 1148 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n", 1149 dev->data->port_id); 1150 } 1151 } 1152 1153 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1154 txq = dev->data->tx_queues[i]; 1155 if (txq) { 1156 stats->q_opackets[i] = txq->pkts; 1157 stats->opackets += txq->pkts; 1158 stats->q_obytes[i] = txq->bytes; 1159 stats->obytes += txq->bytes; 1160 stats->oerrors += txq->errors; 1161 } else { 1162 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n", 1163 dev->data->port_id); 1164 } 1165 } 1166 1167 return 0; 1168 } 1169 1170 static int 1171 axgbe_dev_stats_reset(struct rte_eth_dev *dev) 1172 { 1173 struct axgbe_rx_queue *rxq; 1174 struct axgbe_tx_queue *txq; 1175 unsigned int i; 1176 1177 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1178 rxq = dev->data->rx_queues[i]; 1179 if (rxq) { 1180 rxq->pkts = 0; 1181 rxq->bytes = 0; 1182 rxq->errors = 0; 1183 rxq->rx_mbuf_alloc_failed = 0; 1184 } else { 1185 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n", 1186 dev->data->port_id); 1187 } 1188 } 1189 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1190 txq = dev->data->tx_queues[i]; 1191 if (txq) { 1192 txq->pkts = 0; 1193 txq->bytes = 0; 1194 txq->errors = 0; 1195 } else { 1196 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n", 1197 dev->data->port_id); 1198 } 1199 } 1200 1201 return 0; 1202 } 1203 1204 static int 1205 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1206 { 1207 struct axgbe_port *pdata = dev->data->dev_private; 1208 1209 dev_info->max_rx_queues = pdata->rx_ring_count; 1210 dev_info->max_tx_queues = pdata->tx_ring_count; 1211 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE; 1212 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE; 1213 dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1; 1214 dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size; 1215 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10G; 1216 1217 dev_info->rx_offload_capa = 1218 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 1219 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 1220 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | 1221 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 1222 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 1223 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 1224 RTE_ETH_RX_OFFLOAD_SCATTER | 1225 RTE_ETH_RX_OFFLOAD_KEEP_CRC; 1226 1227 dev_info->tx_offload_capa = 1228 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 1229 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | 1230 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 1231 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | 1232 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 1233 RTE_ETH_TX_OFFLOAD_TCP_CKSUM; 1234 1235 if (pdata->hw_feat.rss) { 1236 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD; 1237 dev_info->reta_size = pdata->hw_feat.hash_table_size; 1238 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE; 1239 } 1240 1241 dev_info->rx_desc_lim = rx_desc_lim; 1242 dev_info->tx_desc_lim = tx_desc_lim; 1243 1244 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1245 .rx_free_thresh = AXGBE_RX_FREE_THRESH, 1246 }; 1247 1248 dev_info->default_txconf = (struct rte_eth_txconf) { 1249 .tx_free_thresh = AXGBE_TX_FREE_THRESH, 1250 }; 1251 1252 return 0; 1253 } 1254 1255 static int 1256 axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1257 { 1258 struct axgbe_port *pdata = dev->data->dev_private; 1259 struct xgbe_fc_info fc = pdata->fc; 1260 unsigned int reg, reg_val = 0; 1261 1262 reg = MAC_Q0TFCR; 1263 reg_val = AXGMAC_IOREAD(pdata, reg); 1264 fc.low_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA); 1265 fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD); 1266 fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT); 1267 fc.autoneg = pdata->pause_autoneg; 1268 1269 if (pdata->rx_pause && pdata->tx_pause) 1270 fc.mode = RTE_ETH_FC_FULL; 1271 else if (pdata->rx_pause) 1272 fc.mode = RTE_ETH_FC_RX_PAUSE; 1273 else if (pdata->tx_pause) 1274 fc.mode = RTE_ETH_FC_TX_PAUSE; 1275 else 1276 fc.mode = RTE_ETH_FC_NONE; 1277 1278 fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024; 1279 fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024; 1280 fc_conf->pause_time = fc.pause_time[0]; 1281 fc_conf->send_xon = fc.send_xon; 1282 fc_conf->mode = fc.mode; 1283 1284 return 0; 1285 } 1286 1287 static int 1288 axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1289 { 1290 struct axgbe_port *pdata = dev->data->dev_private; 1291 struct xgbe_fc_info fc = pdata->fc; 1292 unsigned int reg, reg_val = 0; 1293 reg = MAC_Q0TFCR; 1294 1295 pdata->pause_autoneg = fc_conf->autoneg; 1296 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1297 fc.send_xon = fc_conf->send_xon; 1298 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA, 1299 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water)); 1300 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD, 1301 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water)); 1302 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time); 1303 AXGMAC_IOWRITE(pdata, reg, reg_val); 1304 fc.mode = fc_conf->mode; 1305 1306 if (fc.mode == RTE_ETH_FC_FULL) { 1307 pdata->tx_pause = 1; 1308 pdata->rx_pause = 1; 1309 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) { 1310 pdata->tx_pause = 0; 1311 pdata->rx_pause = 1; 1312 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) { 1313 pdata->tx_pause = 1; 1314 pdata->rx_pause = 0; 1315 } else { 1316 pdata->tx_pause = 0; 1317 pdata->rx_pause = 0; 1318 } 1319 1320 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1321 pdata->hw_if.config_tx_flow_control(pdata); 1322 1323 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1324 pdata->hw_if.config_rx_flow_control(pdata); 1325 1326 pdata->hw_if.config_flow_control(pdata); 1327 pdata->phy.tx_pause = pdata->tx_pause; 1328 pdata->phy.rx_pause = pdata->rx_pause; 1329 1330 return 0; 1331 } 1332 1333 static int 1334 axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 1335 struct rte_eth_pfc_conf *pfc_conf) 1336 { 1337 struct axgbe_port *pdata = dev->data->dev_private; 1338 struct xgbe_fc_info fc = pdata->fc; 1339 uint8_t tc_num; 1340 1341 tc_num = pdata->pfc_map[pfc_conf->priority]; 1342 1343 if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) { 1344 PMD_INIT_LOG(ERR, "Max supported traffic class: %d\n", 1345 pdata->hw_feat.tc_cnt); 1346 return -EINVAL; 1347 } 1348 1349 pdata->pause_autoneg = pfc_conf->fc.autoneg; 1350 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1351 fc.send_xon = pfc_conf->fc.send_xon; 1352 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA, 1353 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water)); 1354 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD, 1355 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water)); 1356 1357 switch (tc_num) { 1358 case 0: 1359 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1360 PSTC0, pfc_conf->fc.pause_time); 1361 break; 1362 case 1: 1363 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1364 PSTC1, pfc_conf->fc.pause_time); 1365 break; 1366 case 2: 1367 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1368 PSTC2, pfc_conf->fc.pause_time); 1369 break; 1370 case 3: 1371 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1372 PSTC3, pfc_conf->fc.pause_time); 1373 break; 1374 case 4: 1375 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1376 PSTC4, pfc_conf->fc.pause_time); 1377 break; 1378 case 5: 1379 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1380 PSTC5, pfc_conf->fc.pause_time); 1381 break; 1382 case 7: 1383 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1384 PSTC6, pfc_conf->fc.pause_time); 1385 break; 1386 case 6: 1387 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1388 PSTC7, pfc_conf->fc.pause_time); 1389 break; 1390 } 1391 1392 fc.mode = pfc_conf->fc.mode; 1393 1394 if (fc.mode == RTE_ETH_FC_FULL) { 1395 pdata->tx_pause = 1; 1396 pdata->rx_pause = 1; 1397 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1398 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) { 1399 pdata->tx_pause = 0; 1400 pdata->rx_pause = 1; 1401 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1402 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) { 1403 pdata->tx_pause = 1; 1404 pdata->rx_pause = 0; 1405 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1406 } else { 1407 pdata->tx_pause = 0; 1408 pdata->rx_pause = 0; 1409 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1410 } 1411 1412 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1413 pdata->hw_if.config_tx_flow_control(pdata); 1414 1415 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1416 pdata->hw_if.config_rx_flow_control(pdata); 1417 pdata->hw_if.config_flow_control(pdata); 1418 pdata->phy.tx_pause = pdata->tx_pause; 1419 pdata->phy.rx_pause = pdata->rx_pause; 1420 1421 return 0; 1422 } 1423 1424 void 1425 axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1426 struct rte_eth_rxq_info *qinfo) 1427 { 1428 struct axgbe_rx_queue *rxq; 1429 1430 rxq = dev->data->rx_queues[queue_id]; 1431 qinfo->mp = rxq->mb_pool; 1432 qinfo->scattered_rx = dev->data->scattered_rx; 1433 qinfo->nb_desc = rxq->nb_desc; 1434 qinfo->conf.rx_free_thresh = rxq->free_thresh; 1435 } 1436 1437 void 1438 axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1439 struct rte_eth_txq_info *qinfo) 1440 { 1441 struct axgbe_tx_queue *txq; 1442 1443 txq = dev->data->tx_queues[queue_id]; 1444 qinfo->nb_desc = txq->nb_desc; 1445 qinfo->conf.tx_free_thresh = txq->free_thresh; 1446 } 1447 const uint32_t * 1448 axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) 1449 { 1450 static const uint32_t ptypes[] = { 1451 RTE_PTYPE_L2_ETHER, 1452 RTE_PTYPE_L2_ETHER_TIMESYNC, 1453 RTE_PTYPE_L2_ETHER_LLDP, 1454 RTE_PTYPE_L2_ETHER_ARP, 1455 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1456 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 1457 RTE_PTYPE_L4_FRAG, 1458 RTE_PTYPE_L4_ICMP, 1459 RTE_PTYPE_L4_NONFRAG, 1460 RTE_PTYPE_L4_SCTP, 1461 RTE_PTYPE_L4_TCP, 1462 RTE_PTYPE_L4_UDP, 1463 RTE_PTYPE_TUNNEL_GRENAT, 1464 RTE_PTYPE_TUNNEL_IP, 1465 RTE_PTYPE_INNER_L2_ETHER, 1466 RTE_PTYPE_INNER_L2_ETHER_VLAN, 1467 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 1468 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 1469 RTE_PTYPE_INNER_L4_FRAG, 1470 RTE_PTYPE_INNER_L4_ICMP, 1471 RTE_PTYPE_INNER_L4_NONFRAG, 1472 RTE_PTYPE_INNER_L4_SCTP, 1473 RTE_PTYPE_INNER_L4_TCP, 1474 RTE_PTYPE_INNER_L4_UDP, 1475 RTE_PTYPE_UNKNOWN 1476 }; 1477 1478 if (dev->rx_pkt_burst == axgbe_recv_pkts) 1479 return ptypes; 1480 return NULL; 1481 } 1482 1483 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1484 { 1485 struct axgbe_port *pdata = dev->data->dev_private; 1486 unsigned int val; 1487 1488 /* mtu setting is forbidden if port is start */ 1489 if (dev->data->dev_started) { 1490 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", 1491 dev->data->port_id); 1492 return -EBUSY; 1493 } 1494 val = mtu > RTE_ETHER_MTU ? 1 : 0; 1495 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 1496 1497 return 0; 1498 } 1499 1500 static void 1501 axgbe_update_tstamp_time(struct axgbe_port *pdata, 1502 unsigned int sec, unsigned int nsec, int addsub) 1503 { 1504 unsigned int count = 100; 1505 uint32_t sub_val = 0; 1506 uint32_t sub_val_sec = 0xFFFFFFFF; 1507 uint32_t sub_val_nsec = 0x3B9ACA00; 1508 1509 if (addsub) { 1510 if (sec) 1511 sub_val = sub_val_sec - (sec - 1); 1512 else 1513 sub_val = sec; 1514 1515 AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val); 1516 sub_val = sub_val_nsec - nsec; 1517 AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val); 1518 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1); 1519 } else { 1520 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1521 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0); 1522 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1523 } 1524 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1525 /* Wait for time update to complete */ 1526 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1527 rte_delay_ms(1); 1528 } 1529 1530 static inline uint64_t 1531 div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) 1532 { 1533 *remainder = dividend % divisor; 1534 return dividend / divisor; 1535 } 1536 1537 static inline uint64_t 1538 div_u64(uint64_t dividend, uint32_t divisor) 1539 { 1540 uint32_t remainder; 1541 return div_u64_rem(dividend, divisor, &remainder); 1542 } 1543 1544 static int 1545 axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta) 1546 { 1547 uint64_t adjust; 1548 uint32_t addend, diff; 1549 unsigned int neg_adjust = 0; 1550 1551 if (delta < 0) { 1552 neg_adjust = 1; 1553 delta = -delta; 1554 } 1555 adjust = (uint64_t)pdata->tstamp_addend; 1556 adjust *= delta; 1557 diff = (uint32_t)div_u64(adjust, 1000000000UL); 1558 addend = (neg_adjust) ? pdata->tstamp_addend - diff : 1559 pdata->tstamp_addend + diff; 1560 pdata->tstamp_addend = addend; 1561 axgbe_update_tstamp_addend(pdata, addend); 1562 return 0; 1563 } 1564 1565 static int 1566 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 1567 { 1568 struct axgbe_port *pdata = dev->data->dev_private; 1569 struct timespec timestamp_delta; 1570 1571 axgbe_adjfreq(pdata, delta); 1572 pdata->systime_tc.nsec += delta; 1573 1574 if (delta < 0) { 1575 delta = -delta; 1576 timestamp_delta = rte_ns_to_timespec(delta); 1577 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1578 timestamp_delta.tv_nsec, 1); 1579 } else { 1580 timestamp_delta = rte_ns_to_timespec(delta); 1581 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1582 timestamp_delta.tv_nsec, 0); 1583 } 1584 return 0; 1585 } 1586 1587 static int 1588 axgbe_timesync_read_time(struct rte_eth_dev *dev, 1589 struct timespec *timestamp) 1590 { 1591 uint64_t nsec; 1592 struct axgbe_port *pdata = dev->data->dev_private; 1593 1594 nsec = AXGMAC_IOREAD(pdata, MAC_STSR); 1595 nsec *= NSEC_PER_SEC; 1596 nsec += AXGMAC_IOREAD(pdata, MAC_STNR); 1597 *timestamp = rte_ns_to_timespec(nsec); 1598 return 0; 1599 } 1600 static int 1601 axgbe_timesync_write_time(struct rte_eth_dev *dev, 1602 const struct timespec *timestamp) 1603 { 1604 unsigned int count = 100; 1605 struct axgbe_port *pdata = dev->data->dev_private; 1606 1607 AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec); 1608 AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec); 1609 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1610 /* Wait for time update to complete */ 1611 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1612 rte_delay_ms(1); 1613 if (!count) 1614 PMD_DRV_LOG(ERR, "Timed out update timestamp\n"); 1615 return 0; 1616 } 1617 1618 static void 1619 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 1620 uint32_t addend) 1621 { 1622 unsigned int count = 100; 1623 1624 AXGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1625 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1626 1627 /* Wait for addend update to complete */ 1628 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1629 rte_delay_ms(1); 1630 if (!count) 1631 PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n"); 1632 } 1633 1634 static void 1635 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 1636 unsigned int nsec) 1637 { 1638 unsigned int count = 100; 1639 1640 /*System Time Sec Update*/ 1641 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1642 /*System Time nanoSec Update*/ 1643 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1644 /*Initialize Timestamp*/ 1645 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1646 1647 /* Wait for time update to complete */ 1648 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1649 rte_delay_ms(1); 1650 if (!count) 1651 PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n"); 1652 } 1653 1654 static int 1655 axgbe_timesync_enable(struct rte_eth_dev *dev) 1656 { 1657 struct axgbe_port *pdata = dev->data->dev_private; 1658 unsigned int mac_tscr = 0; 1659 uint64_t dividend; 1660 struct timespec timestamp; 1661 uint64_t nsec; 1662 1663 /* Set one nano-second accuracy */ 1664 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1665 1666 /* Set fine timestamp update */ 1667 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1668 1669 /* Overwrite earlier timestamps */ 1670 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1671 1672 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1673 1674 /* Enabling processing of ptp over eth pkt */ 1675 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1676 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1677 /* Enable timestamp for all pkts*/ 1678 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 1679 1680 /* enabling timestamp */ 1681 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1682 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1683 1684 /* Exit if timestamping is not enabled */ 1685 if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) { 1686 PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n"); 1687 return 0; 1688 } 1689 1690 /* Sub-second Increment Value*/ 1691 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC); 1692 /* Sub-nanosecond Increment Value */ 1693 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC); 1694 1695 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 1696 dividend = 50000000; 1697 dividend <<= 32; 1698 pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate); 1699 1700 axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1701 axgbe_set_tstamp_time(pdata, 0, 0); 1702 1703 /* Initialize the timecounter */ 1704 memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter)); 1705 1706 pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK; 1707 pdata->systime_tc.cc_shift = 0; 1708 pdata->systime_tc.nsec_mask = 0; 1709 1710 PMD_DRV_LOG(DEBUG, "Initializing system time counter with realtime\n"); 1711 1712 /* Updating the counter once with clock real time */ 1713 clock_gettime(CLOCK_REALTIME, ×tamp); 1714 nsec = rte_timespec_to_ns(×tamp); 1715 nsec = rte_timecounter_update(&pdata->systime_tc, nsec); 1716 axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec); 1717 return 0; 1718 } 1719 1720 static int 1721 axgbe_timesync_disable(struct rte_eth_dev *dev) 1722 { 1723 struct axgbe_port *pdata = dev->data->dev_private; 1724 unsigned int mac_tscr = 0; 1725 1726 /*disable timestamp for all pkts*/ 1727 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0); 1728 /*disable the addened register*/ 1729 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0); 1730 /* disable timestamp update */ 1731 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0); 1732 /*disable time stamp*/ 1733 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0); 1734 return 0; 1735 } 1736 1737 static int 1738 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 1739 struct timespec *timestamp, uint32_t flags) 1740 { 1741 uint64_t nsec = 0; 1742 volatile union axgbe_rx_desc *desc; 1743 uint16_t idx, pmt; 1744 struct axgbe_rx_queue *rxq = *dev->data->rx_queues; 1745 1746 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 1747 desc = &rxq->desc[idx]; 1748 1749 while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 1750 rte_delay_ms(1); 1751 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) { 1752 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) && 1753 !AXGMAC_GET_BITS_LE(desc->write.desc3, 1754 RX_CONTEXT_DESC3, TSD)) { 1755 pmt = AXGMAC_GET_BITS_LE(desc->write.desc3, 1756 RX_CONTEXT_DESC3, PMT); 1757 nsec = rte_le_to_cpu_32(desc->write.desc1); 1758 nsec *= NSEC_PER_SEC; 1759 nsec += rte_le_to_cpu_32(desc->write.desc0); 1760 if (nsec != 0xffffffffffffffffULL) { 1761 if (pmt == 0x01) 1762 *timestamp = rte_ns_to_timespec(nsec); 1763 PMD_DRV_LOG(DEBUG, 1764 "flags = 0x%x nsec = %"PRIu64"\n", 1765 flags, nsec); 1766 } 1767 } 1768 } 1769 1770 return 0; 1771 } 1772 1773 static int 1774 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 1775 struct timespec *timestamp) 1776 { 1777 uint64_t nsec; 1778 struct axgbe_port *pdata = dev->data->dev_private; 1779 unsigned int tx_snr, tx_ssr; 1780 1781 rte_delay_us(5); 1782 if (pdata->vdata->tx_tstamp_workaround) { 1783 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1784 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1785 1786 } else { 1787 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1788 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1789 } 1790 if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) { 1791 PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n"); 1792 return 0; 1793 } 1794 nsec = tx_ssr; 1795 nsec *= NSEC_PER_SEC; 1796 nsec += tx_snr; 1797 PMD_DRV_LOG(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d\n", 1798 nsec, tx_ssr, tx_snr); 1799 *timestamp = rte_ns_to_timespec(nsec); 1800 return 0; 1801 } 1802 1803 static int 1804 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1805 { 1806 struct axgbe_port *pdata = dev->data->dev_private; 1807 unsigned long vid_bit, vid_idx; 1808 1809 vid_bit = VLAN_TABLE_BIT(vid); 1810 vid_idx = VLAN_TABLE_IDX(vid); 1811 1812 if (on) { 1813 PMD_DRV_LOG(DEBUG, "Set VLAN vid=%d for device = %s\n", 1814 vid, pdata->eth_dev->device->name); 1815 pdata->active_vlans[vid_idx] |= vid_bit; 1816 } else { 1817 PMD_DRV_LOG(DEBUG, "Reset VLAN vid=%d for device = %s\n", 1818 vid, pdata->eth_dev->device->name); 1819 pdata->active_vlans[vid_idx] &= ~vid_bit; 1820 } 1821 pdata->hw_if.update_vlan_hash_table(pdata); 1822 return 0; 1823 } 1824 1825 static int 1826 axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1827 enum rte_vlan_type vlan_type, 1828 uint16_t tpid) 1829 { 1830 struct axgbe_port *pdata = dev->data->dev_private; 1831 uint32_t reg = 0; 1832 uint32_t qinq = 0; 1833 1834 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1835 PMD_DRV_LOG(DEBUG, "EDVLP: qinq = 0x%x\n", qinq); 1836 1837 switch (vlan_type) { 1838 case RTE_ETH_VLAN_TYPE_INNER: 1839 PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_INNER\n"); 1840 if (qinq) { 1841 if (tpid != 0x8100 && tpid != 0x88a8) 1842 PMD_DRV_LOG(ERR, 1843 "tag supported 0x8100/0x88A8\n"); 1844 PMD_DRV_LOG(DEBUG, "qinq with inner tag\n"); 1845 1846 /*Enable Inner VLAN Tag */ 1847 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 1); 1848 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1849 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg); 1850 1851 } else { 1852 PMD_DRV_LOG(ERR, 1853 "Inner type not supported in single tag\n"); 1854 } 1855 break; 1856 case RTE_ETH_VLAN_TYPE_OUTER: 1857 PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_OUTER\n"); 1858 if (qinq) { 1859 PMD_DRV_LOG(DEBUG, "double tagging is enabled\n"); 1860 /*Enable outer VLAN tag*/ 1861 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 0); 1862 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1863 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg); 1864 1865 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 1); 1866 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANIR, CSVL); 1867 PMD_DRV_LOG(DEBUG, "bit CSVL = 0x%x\n", reg); 1868 } else { 1869 if (tpid != 0x8100 && tpid != 0x88a8) 1870 PMD_DRV_LOG(ERR, 1871 "tag supported 0x8100/0x88A8\n"); 1872 } 1873 break; 1874 case RTE_ETH_VLAN_TYPE_MAX: 1875 PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_MAX\n"); 1876 break; 1877 case RTE_ETH_VLAN_TYPE_UNKNOWN: 1878 PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_UNKNOWN\n"); 1879 break; 1880 } 1881 return 0; 1882 } 1883 1884 static void axgbe_vlan_extend_enable(struct axgbe_port *pdata) 1885 { 1886 int qinq = 0; 1887 1888 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 1); 1889 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1890 PMD_DRV_LOG(DEBUG, "vlan double tag enabled EDVLP:qinq=0x%x\n", qinq); 1891 } 1892 1893 static void axgbe_vlan_extend_disable(struct axgbe_port *pdata) 1894 { 1895 int qinq = 0; 1896 1897 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 0); 1898 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1899 PMD_DRV_LOG(DEBUG, "vlan double tag disable EDVLP:qinq=0x%x\n", qinq); 1900 } 1901 1902 static int 1903 axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1904 { 1905 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1906 struct axgbe_port *pdata = dev->data->dev_private; 1907 1908 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 1909 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 1910 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 1911 1912 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 1913 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { 1914 PMD_DRV_LOG(DEBUG, "Strip ON for device = %s\n", 1915 pdata->eth_dev->device->name); 1916 pdata->hw_if.enable_rx_vlan_stripping(pdata); 1917 } else { 1918 PMD_DRV_LOG(DEBUG, "Strip OFF for device = %s\n", 1919 pdata->eth_dev->device->name); 1920 pdata->hw_if.disable_rx_vlan_stripping(pdata); 1921 } 1922 } 1923 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 1924 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 1925 PMD_DRV_LOG(DEBUG, "Filter ON for device = %s\n", 1926 pdata->eth_dev->device->name); 1927 pdata->hw_if.enable_rx_vlan_filtering(pdata); 1928 } else { 1929 PMD_DRV_LOG(DEBUG, "Filter OFF for device = %s\n", 1930 pdata->eth_dev->device->name); 1931 pdata->hw_if.disable_rx_vlan_filtering(pdata); 1932 } 1933 } 1934 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 1935 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) { 1936 PMD_DRV_LOG(DEBUG, "enabling vlan extended mode\n"); 1937 axgbe_vlan_extend_enable(pdata); 1938 /* Set global registers with default ethertype*/ 1939 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER, 1940 RTE_ETHER_TYPE_VLAN); 1941 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER, 1942 RTE_ETHER_TYPE_VLAN); 1943 } else { 1944 PMD_DRV_LOG(DEBUG, "disabling vlan extended mode\n"); 1945 axgbe_vlan_extend_disable(pdata); 1946 } 1947 } 1948 return 0; 1949 } 1950 1951 static void axgbe_get_all_hw_features(struct axgbe_port *pdata) 1952 { 1953 unsigned int mac_hfr0, mac_hfr1, mac_hfr2, mac_hfr3; 1954 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 1955 1956 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R); 1957 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R); 1958 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R); 1959 mac_hfr3 = AXGMAC_IOREAD(pdata, MAC_HWF3R); 1960 1961 memset(hw_feat, 0, sizeof(*hw_feat)); 1962 1963 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR); 1964 1965 /* Hardware feature register 0 */ 1966 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 1967 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 1968 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 1969 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 1970 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 1971 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 1972 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 1973 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 1974 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 1975 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 1976 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 1977 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 1978 ADDMACADRSEL); 1979 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 1980 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 1981 1982 /* Hardware feature register 1 */ 1983 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1984 RXFIFOSIZE); 1985 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1986 TXFIFOSIZE); 1987 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1, 1988 MAC_HWF1R, ADVTHWORD); 1989 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 1990 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 1991 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 1992 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 1993 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 1994 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 1995 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 1996 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1997 HASHTBLSZ); 1998 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1999 L3L4FNUM); 2000 2001 /* Hardware feature register 2 */ 2002 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 2003 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 2004 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 2005 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 2006 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 2007 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, 2008 AUXSNAPNUM); 2009 2010 /* Hardware feature register 3 */ 2011 hw_feat->tx_q_vlan_tag_ins = AXGMAC_GET_BITS(mac_hfr3, 2012 MAC_HWF3R, CBTISEL); 2013 hw_feat->no_of_vlan_extn = AXGMAC_GET_BITS(mac_hfr3, 2014 MAC_HWF3R, NRVF); 2015 2016 /* Translate the Hash Table size into actual number */ 2017 switch (hw_feat->hash_table_size) { 2018 case 0: 2019 break; 2020 case 1: 2021 hw_feat->hash_table_size = 64; 2022 break; 2023 case 2: 2024 hw_feat->hash_table_size = 128; 2025 break; 2026 case 3: 2027 hw_feat->hash_table_size = 256; 2028 break; 2029 } 2030 2031 /* Translate the address width setting into actual number */ 2032 switch (hw_feat->dma_width) { 2033 case 0: 2034 hw_feat->dma_width = 32; 2035 break; 2036 case 1: 2037 hw_feat->dma_width = 40; 2038 break; 2039 case 2: 2040 hw_feat->dma_width = 48; 2041 break; 2042 default: 2043 hw_feat->dma_width = 32; 2044 } 2045 2046 /* The Queue, Channel and TC counts are zero based so increment them 2047 * to get the actual number 2048 */ 2049 hw_feat->rx_q_cnt++; 2050 hw_feat->tx_q_cnt++; 2051 hw_feat->rx_ch_cnt++; 2052 hw_feat->tx_ch_cnt++; 2053 hw_feat->tc_cnt++; 2054 2055 /* Translate the fifo sizes into actual numbers */ 2056 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 2057 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 2058 } 2059 2060 static void axgbe_init_all_fptrs(struct axgbe_port *pdata) 2061 { 2062 axgbe_init_function_ptrs_dev(&pdata->hw_if); 2063 axgbe_init_function_ptrs_phy(&pdata->phy_if); 2064 axgbe_init_function_ptrs_i2c(&pdata->i2c_if); 2065 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 2066 } 2067 2068 static void axgbe_set_counts(struct axgbe_port *pdata) 2069 { 2070 /* Set all the function pointers */ 2071 axgbe_init_all_fptrs(pdata); 2072 2073 /* Populate the hardware features */ 2074 axgbe_get_all_hw_features(pdata); 2075 2076 /* Set default max values if not provided */ 2077 if (!pdata->tx_max_channel_count) 2078 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 2079 if (!pdata->rx_max_channel_count) 2080 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 2081 2082 if (!pdata->tx_max_q_count) 2083 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 2084 if (!pdata->rx_max_q_count) 2085 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 2086 2087 /* Calculate the number of Tx and Rx rings to be created 2088 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 2089 * the number of Tx queues to the number of Tx channels 2090 * enabled 2091 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 2092 * number of Rx queues or maximum allowed 2093 */ 2094 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt, 2095 pdata->tx_max_channel_count); 2096 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count, 2097 pdata->tx_max_q_count); 2098 2099 pdata->tx_q_count = pdata->tx_ring_count; 2100 2101 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt, 2102 pdata->rx_max_channel_count); 2103 2104 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt, 2105 pdata->rx_max_q_count); 2106 } 2107 2108 static void axgbe_default_config(struct axgbe_port *pdata) 2109 { 2110 pdata->pblx8 = DMA_PBL_X8_ENABLE; 2111 pdata->tx_sf_mode = MTL_TSF_ENABLE; 2112 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 2113 pdata->tx_pbl = DMA_PBL_32; 2114 pdata->tx_osp_mode = DMA_OSP_ENABLE; 2115 pdata->rx_sf_mode = MTL_RSF_ENABLE; 2116 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 2117 pdata->rx_pbl = DMA_PBL_32; 2118 pdata->pause_autoneg = 1; 2119 pdata->tx_pause = 0; 2120 pdata->rx_pause = 0; 2121 pdata->phy_speed = SPEED_UNKNOWN; 2122 pdata->power_down = 0; 2123 } 2124 2125 /* Used in dev_start by primary process and then 2126 * in dev_init by secondary process when attaching to an existing ethdev. 2127 */ 2128 void 2129 axgbe_set_tx_function(struct rte_eth_dev *dev) 2130 { 2131 struct axgbe_port *pdata = dev->data->dev_private; 2132 2133 if (pdata->multi_segs_tx) 2134 dev->tx_pkt_burst = &axgbe_xmit_pkts_seg; 2135 #ifdef RTE_ARCH_X86 2136 struct axgbe_tx_queue *txq = dev->data->tx_queues[0]; 2137 if (!txq->vector_disable && 2138 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) 2139 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec; 2140 #else 2141 dev->tx_pkt_burst = &axgbe_xmit_pkts; 2142 #endif 2143 } 2144 2145 void 2146 axgbe_set_rx_function(struct rte_eth_dev *dev) 2147 { 2148 struct rte_eth_dev_data *dev_data = dev->data; 2149 uint16_t max_pkt_len; 2150 struct axgbe_port *pdata; 2151 2152 pdata = dev->data->dev_private; 2153 max_pkt_len = dev_data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 2154 if ((dev_data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) || 2155 max_pkt_len > pdata->rx_buf_size) 2156 dev_data->scattered_rx = 1; 2157 /* Scatter Rx handling */ 2158 if (dev_data->scattered_rx) 2159 dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts; 2160 else 2161 dev->rx_pkt_burst = &axgbe_recv_pkts; 2162 } 2163 2164 /* 2165 * It returns 0 on success. 2166 */ 2167 static int 2168 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) 2169 { 2170 PMD_INIT_FUNC_TRACE(); 2171 struct axgbe_port *pdata; 2172 struct rte_pci_device *pci_dev; 2173 uint32_t reg, mac_lo, mac_hi; 2174 uint32_t len; 2175 int ret; 2176 2177 unsigned int eax = 0, ebx = 0, ecx = 0, edx = 0; 2178 unsigned char cpu_family = 0, cpu_model = 0; 2179 2180 eth_dev->dev_ops = &axgbe_eth_dev_ops; 2181 2182 eth_dev->rx_descriptor_status = axgbe_dev_rx_descriptor_status; 2183 eth_dev->tx_descriptor_status = axgbe_dev_tx_descriptor_status; 2184 2185 eth_dev->tx_pkt_burst = &axgbe_xmit_pkts; 2186 eth_dev->rx_pkt_burst = &axgbe_recv_pkts; 2187 2188 /* 2189 * For secondary processes, we don't initialise any further as primary 2190 * has already done this work. 2191 */ 2192 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2193 axgbe_set_tx_function(eth_dev); 2194 axgbe_set_rx_function(eth_dev); 2195 return 0; 2196 } 2197 2198 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2199 2200 pdata = eth_dev->data->dev_private; 2201 /* initial state */ 2202 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 2203 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 2204 pdata->eth_dev = eth_dev; 2205 2206 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2207 pdata->pci_dev = pci_dev; 2208 2209 pdata->xgmac_regs = 2210 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; 2211 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs 2212 + AXGBE_MAC_PROP_OFFSET); 2213 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs 2214 + AXGBE_I2C_CTRL_OFFSET); 2215 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; 2216 2217 /* version specific driver data*/ 2218 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A) 2219 pdata->vdata = &axgbe_v2a; 2220 else 2221 pdata->vdata = &axgbe_v2b; 2222 2223 /* 2224 * Use CPUID to get Family and model ID to identify the CPU 2225 */ 2226 __cpuid(0x0, eax, ebx, ecx, edx); 2227 2228 if (ebx == CPUID_VENDOR_AuthenticAMD_ebx && 2229 edx == CPUID_VENDOR_AuthenticAMD_edx && 2230 ecx == CPUID_VENDOR_AuthenticAMD_ecx) { 2231 int unknown_cpu = 0; 2232 eax = 0, ebx = 0, ecx = 0, edx = 0; 2233 2234 __cpuid(0x1, eax, ebx, ecx, edx); 2235 2236 cpu_family = ((GET_BITS(eax, 8, 4)) + (GET_BITS(eax, 20, 8))); 2237 cpu_model = ((GET_BITS(eax, 4, 4)) | (((GET_BITS(eax, 16, 4)) << 4) & 0xF0)); 2238 2239 switch (cpu_family) { 2240 case Fam17h: 2241 /* V1000/R1000 */ 2242 if (cpu_model >= 0x10 && cpu_model <= 0x1F) { 2243 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; 2244 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; 2245 /* EPYC 3000 */ 2246 } else if (cpu_model >= 0x01 && cpu_model <= 0x0F) { 2247 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 2248 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 2249 } else { 2250 unknown_cpu = 1; 2251 } 2252 break; 2253 case Fam19h: 2254 /* V3000 (Yellow Carp) */ 2255 if (cpu_model >= 0x44 && cpu_model <= 0x47) { 2256 pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF; 2257 pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT; 2258 2259 /* Yellow Carp devices do not need cdr workaround */ 2260 pdata->vdata->an_cdr_workaround = 0; 2261 } else { 2262 unknown_cpu = 1; 2263 } 2264 break; 2265 default: 2266 unknown_cpu = 1; 2267 break; 2268 } 2269 if (unknown_cpu) { 2270 PMD_DRV_LOG(ERR, "Unknown CPU family, no supported axgbe device found\n"); 2271 return -ENODEV; 2272 } 2273 } 2274 2275 /* Configure the PCS indirect addressing support */ 2276 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); 2277 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 2278 pdata->xpcs_window <<= 6; 2279 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 2280 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 2281 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 2282 2283 PMD_INIT_LOG(DEBUG, 2284 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, 2285 pdata->xpcs_window_size, pdata->xpcs_window_mask); 2286 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 2287 2288 /* Retrieve the MAC address */ 2289 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 2290 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 2291 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff; 2292 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff; 2293 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff; 2294 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff; 2295 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff; 2296 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff; 2297 2298 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_MAC_ADDRS; 2299 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", len, 0); 2300 2301 if (!eth_dev->data->mac_addrs) { 2302 PMD_INIT_LOG(ERR, 2303 "Failed to alloc %u bytes needed to " 2304 "store MAC addresses", len); 2305 return -ENOMEM; 2306 } 2307 2308 /* Allocate memory for storing hash filter MAC addresses */ 2309 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS; 2310 eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr", 2311 len, 0); 2312 2313 if (eth_dev->data->hash_mac_addrs == NULL) { 2314 PMD_INIT_LOG(ERR, 2315 "Failed to allocate %d bytes needed to " 2316 "store MAC addresses", len); 2317 return -ENOMEM; 2318 } 2319 2320 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr)) 2321 rte_eth_random_addr(pdata->mac_addr.addr_bytes); 2322 2323 /* Copy the permanent MAC address */ 2324 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]); 2325 2326 /* Clock settings */ 2327 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ; 2328 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 2329 2330 /* Set the DMA coherency values */ 2331 pdata->coherent = 1; 2332 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN; 2333 pdata->arcache = AXGBE_DMA_OS_ARCACHE; 2334 pdata->awcache = AXGBE_DMA_OS_AWCACHE; 2335 2336 /* Set the maximum channels and queues */ 2337 reg = XP_IOREAD(pdata, XP_PROP_1); 2338 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA); 2339 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA); 2340 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES); 2341 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES); 2342 2343 /* Set the hardware channel and queue counts */ 2344 axgbe_set_counts(pdata); 2345 2346 /* Set the maximum fifo amounts */ 2347 reg = XP_IOREAD(pdata, XP_PROP_2); 2348 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE); 2349 pdata->tx_max_fifo_size *= 16384; 2350 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size, 2351 pdata->vdata->tx_max_fifo_size); 2352 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE); 2353 pdata->rx_max_fifo_size *= 16384; 2354 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size, 2355 pdata->vdata->rx_max_fifo_size); 2356 /* Issue software reset to DMA */ 2357 ret = pdata->hw_if.exit(pdata); 2358 if (ret) 2359 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n"); 2360 2361 /* Set default configuration data */ 2362 axgbe_default_config(pdata); 2363 2364 /* Set default max values if not provided */ 2365 if (!pdata->tx_max_fifo_size) 2366 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 2367 if (!pdata->rx_max_fifo_size) 2368 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 2369 2370 pdata->tx_desc_count = AXGBE_MAX_RING_DESC; 2371 pdata->rx_desc_count = AXGBE_MAX_RING_DESC; 2372 pthread_mutex_init(&pdata->xpcs_mutex, NULL); 2373 pthread_mutex_init(&pdata->i2c_mutex, NULL); 2374 pthread_mutex_init(&pdata->an_mutex, NULL); 2375 pthread_mutex_init(&pdata->phy_mutex, NULL); 2376 2377 ret = pdata->phy_if.phy_init(pdata); 2378 if (ret) { 2379 rte_free(eth_dev->data->mac_addrs); 2380 eth_dev->data->mac_addrs = NULL; 2381 return ret; 2382 } 2383 2384 rte_intr_callback_register(pci_dev->intr_handle, 2385 axgbe_dev_interrupt_handler, 2386 (void *)eth_dev); 2387 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 2388 eth_dev->data->port_id, pci_dev->id.vendor_id, 2389 pci_dev->id.device_id); 2390 2391 return 0; 2392 } 2393 2394 static int 2395 axgbe_dev_close(struct rte_eth_dev *eth_dev) 2396 { 2397 struct rte_pci_device *pci_dev; 2398 2399 PMD_INIT_FUNC_TRACE(); 2400 2401 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2402 return 0; 2403 2404 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2405 axgbe_dev_clear_queues(eth_dev); 2406 2407 /* disable uio intr before callback unregister */ 2408 rte_intr_disable(pci_dev->intr_handle); 2409 rte_intr_callback_unregister(pci_dev->intr_handle, 2410 axgbe_dev_interrupt_handler, 2411 (void *)eth_dev); 2412 2413 return 0; 2414 } 2415 2416 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2417 struct rte_pci_device *pci_dev) 2418 { 2419 return rte_eth_dev_pci_generic_probe(pci_dev, 2420 sizeof(struct axgbe_port), eth_axgbe_dev_init); 2421 } 2422 2423 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev) 2424 { 2425 return rte_eth_dev_pci_generic_remove(pci_dev, axgbe_dev_close); 2426 } 2427 2428 static struct rte_pci_driver rte_axgbe_pmd = { 2429 .id_table = pci_id_axgbe_map, 2430 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2431 .probe = eth_axgbe_pci_probe, 2432 .remove = eth_axgbe_pci_remove, 2433 }; 2434 2435 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd); 2436 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map); 2437 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 2438 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_init, init, NOTICE); 2439 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_driver, driver, NOTICE); 2440