1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_rxtx.h" 7 #include "axgbe_ethdev.h" 8 #include "axgbe_common.h" 9 #include "axgbe_phy.h" 10 #include "axgbe_regs.h" 11 #include "rte_time.h" 12 13 #include "eal_filesystem.h" 14 15 #include <rte_vect.h> 16 17 #ifdef RTE_ARCH_X86 18 #include <cpuid.h> 19 #else 20 #define __cpuid(n, a, b, c, d) 21 #endif 22 23 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); 24 static int axgbe_dev_configure(struct rte_eth_dev *dev); 25 static int axgbe_dev_start(struct rte_eth_dev *dev); 26 static int axgbe_dev_stop(struct rte_eth_dev *dev); 27 static void axgbe_dev_interrupt_handler(void *param); 28 static int axgbe_dev_close(struct rte_eth_dev *dev); 29 static int axgbe_dev_reset(struct rte_eth_dev *dev); 30 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 31 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 32 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 33 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 34 static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, 35 struct rte_ether_addr *mac_addr); 36 static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, 37 struct rte_ether_addr *mac_addr, 38 uint32_t index, 39 uint32_t vmdq); 40 static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 41 static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 42 struct rte_ether_addr *mc_addr_set, 43 uint32_t nb_mc_addr); 44 static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 45 struct rte_ether_addr *mac_addr, 46 uint8_t add); 47 static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, 48 uint8_t add); 49 static int axgbe_dev_link_update(struct rte_eth_dev *dev, 50 int wait_to_complete); 51 static int axgbe_dev_get_regs(struct rte_eth_dev *dev, 52 struct rte_dev_reg_info *regs); 53 static int axgbe_dev_stats_get(struct rte_eth_dev *dev, 54 struct rte_eth_stats *stats); 55 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev); 56 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev, 57 struct rte_eth_xstat *stats, 58 unsigned int n); 59 static int 60 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 61 struct rte_eth_xstat_name *xstats_names, 62 unsigned int size); 63 static int 64 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 65 const uint64_t *ids, 66 uint64_t *values, 67 unsigned int n); 68 static int 69 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 70 const uint64_t *ids, 71 struct rte_eth_xstat_name *xstats_names, 72 unsigned int size); 73 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev); 74 static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 75 struct rte_eth_rss_reta_entry64 *reta_conf, 76 uint16_t reta_size); 77 static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 78 struct rte_eth_rss_reta_entry64 *reta_conf, 79 uint16_t reta_size); 80 static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 81 struct rte_eth_rss_conf *rss_conf); 82 static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 83 struct rte_eth_rss_conf *rss_conf); 84 static int axgbe_dev_info_get(struct rte_eth_dev *dev, 85 struct rte_eth_dev_info *dev_info); 86 static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, 87 struct rte_eth_fc_conf *fc_conf); 88 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, 89 struct rte_eth_fc_conf *fc_conf); 90 static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 91 struct rte_eth_pfc_conf *pfc_conf); 92 static void axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 93 struct rte_eth_rxq_info *qinfo); 94 static void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 95 struct rte_eth_txq_info *qinfo); 96 const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev, 97 size_t *no_of_elements); 98 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 99 100 static int 101 axgbe_timesync_enable(struct rte_eth_dev *dev); 102 static int 103 axgbe_timesync_disable(struct rte_eth_dev *dev); 104 static int 105 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 106 struct timespec *timestamp, uint32_t flags); 107 static int 108 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 109 struct timespec *timestamp); 110 static int 111 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 112 static int 113 axgbe_timesync_read_time(struct rte_eth_dev *dev, 114 struct timespec *timestamp); 115 static int 116 axgbe_timesync_write_time(struct rte_eth_dev *dev, 117 const struct timespec *timestamp); 118 static void 119 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 120 unsigned int nsec); 121 static void 122 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 123 unsigned int addend); 124 static int 125 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on); 126 static int axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 127 enum rte_vlan_type vlan_type, uint16_t tpid); 128 static int axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 129 130 struct axgbe_xstats { 131 char name[RTE_ETH_XSTATS_NAME_SIZE]; 132 int offset; 133 }; 134 135 #define AXGMAC_MMC_STAT(_string, _var) \ 136 { _string, \ 137 offsetof(struct axgbe_mmc_stats, _var), \ 138 } 139 140 static const struct axgbe_xstats axgbe_xstats_strings[] = { 141 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb), 142 AXGMAC_MMC_STAT("tx_packets", txframecount_gb), 143 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb), 144 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb), 145 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb), 146 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g), 147 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb), 148 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb), 149 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb), 150 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb), 151 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb), 152 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb), 153 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror), 154 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes), 155 156 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb), 157 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb), 158 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g), 159 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g), 160 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g), 161 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb), 162 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb), 163 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb), 164 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb), 165 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb), 166 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb), 167 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb), 168 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g), 169 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g), 170 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror), 171 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror), 172 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror), 173 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror), 174 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype), 175 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow), 176 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror), 177 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes), 178 }; 179 180 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings) 181 182 /* The set of PCI devices this driver supports */ 183 #define AMD_PCI_VENDOR_ID 0x1022 184 185 #define Fam17h 0x17 186 #define Fam19h 0x19 187 188 #define CPUID_VENDOR_AuthenticAMD_ebx 0x68747541 189 #define CPUID_VENDOR_AuthenticAMD_ecx 0x444d4163 190 #define CPUID_VENDOR_AuthenticAMD_edx 0x69746e65 191 192 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 193 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459 194 195 static const struct rte_pci_id pci_id_axgbe_map[] = { 196 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)}, 197 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)}, 198 { .vendor_id = 0, }, 199 }; 200 201 static struct axgbe_version_data axgbe_v2a = { 202 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 203 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 204 .mmc_64bit = 1, 205 .tx_max_fifo_size = 229376, 206 .rx_max_fifo_size = 229376, 207 .tx_tstamp_workaround = 1, 208 .ecc_support = 1, 209 .i2c_support = 1, 210 .an_cdr_workaround = 1, 211 .enable_rrc = 1, 212 }; 213 214 static struct axgbe_version_data axgbe_v2b = { 215 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 216 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 217 .mmc_64bit = 1, 218 .tx_max_fifo_size = 65536, 219 .rx_max_fifo_size = 65536, 220 .tx_tstamp_workaround = 1, 221 .ecc_support = 1, 222 .i2c_support = 1, 223 .an_cdr_workaround = 1, 224 .enable_rrc = 1, 225 }; 226 227 static const struct rte_eth_desc_lim rx_desc_lim = { 228 .nb_max = AXGBE_MAX_RING_DESC, 229 .nb_min = AXGBE_MIN_RING_DESC, 230 .nb_align = 8, 231 }; 232 233 static const struct rte_eth_desc_lim tx_desc_lim = { 234 .nb_max = AXGBE_MAX_RING_DESC, 235 .nb_min = AXGBE_MIN_RING_DESC, 236 .nb_align = 8, 237 }; 238 239 static const struct eth_dev_ops axgbe_eth_dev_ops = { 240 .dev_configure = axgbe_dev_configure, 241 .dev_start = axgbe_dev_start, 242 .dev_stop = axgbe_dev_stop, 243 .dev_close = axgbe_dev_close, 244 .dev_reset = axgbe_dev_reset, 245 .promiscuous_enable = axgbe_dev_promiscuous_enable, 246 .promiscuous_disable = axgbe_dev_promiscuous_disable, 247 .allmulticast_enable = axgbe_dev_allmulticast_enable, 248 .allmulticast_disable = axgbe_dev_allmulticast_disable, 249 .mac_addr_set = axgbe_dev_mac_addr_set, 250 .mac_addr_add = axgbe_dev_mac_addr_add, 251 .mac_addr_remove = axgbe_dev_mac_addr_remove, 252 .set_mc_addr_list = axgbe_dev_set_mc_addr_list, 253 .uc_hash_table_set = axgbe_dev_uc_hash_table_set, 254 .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set, 255 .link_update = axgbe_dev_link_update, 256 .get_reg = axgbe_dev_get_regs, 257 .stats_get = axgbe_dev_stats_get, 258 .stats_reset = axgbe_dev_stats_reset, 259 .xstats_get = axgbe_dev_xstats_get, 260 .xstats_reset = axgbe_dev_xstats_reset, 261 .xstats_get_names = axgbe_dev_xstats_get_names, 262 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id, 263 .xstats_get_by_id = axgbe_dev_xstats_get_by_id, 264 .reta_update = axgbe_dev_rss_reta_update, 265 .reta_query = axgbe_dev_rss_reta_query, 266 .rss_hash_update = axgbe_dev_rss_hash_update, 267 .rss_hash_conf_get = axgbe_dev_rss_hash_conf_get, 268 .dev_infos_get = axgbe_dev_info_get, 269 .rx_queue_setup = axgbe_dev_rx_queue_setup, 270 .rx_queue_release = axgbe_dev_rx_queue_release, 271 .tx_queue_setup = axgbe_dev_tx_queue_setup, 272 .tx_queue_release = axgbe_dev_tx_queue_release, 273 .flow_ctrl_get = axgbe_flow_ctrl_get, 274 .flow_ctrl_set = axgbe_flow_ctrl_set, 275 .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set, 276 .rxq_info_get = axgbe_rxq_info_get, 277 .txq_info_get = axgbe_txq_info_get, 278 .dev_supported_ptypes_get = axgbe_dev_supported_ptypes_get, 279 .mtu_set = axgb_mtu_set, 280 .vlan_filter_set = axgbe_vlan_filter_set, 281 .vlan_tpid_set = axgbe_vlan_tpid_set, 282 .vlan_offload_set = axgbe_vlan_offload_set, 283 .timesync_enable = axgbe_timesync_enable, 284 .timesync_disable = axgbe_timesync_disable, 285 .timesync_read_rx_timestamp = axgbe_timesync_read_rx_timestamp, 286 .timesync_read_tx_timestamp = axgbe_timesync_read_tx_timestamp, 287 .timesync_adjust_time = axgbe_timesync_adjust_time, 288 .timesync_read_time = axgbe_timesync_read_time, 289 .timesync_write_time = axgbe_timesync_write_time, 290 .fw_version_get = axgbe_dev_fw_version_get, 291 }; 292 293 static int axgbe_phy_reset(struct axgbe_port *pdata) 294 { 295 pdata->phy_link = -1; 296 pdata->phy_speed = SPEED_UNKNOWN; 297 return pdata->phy_if.phy_reset(pdata); 298 } 299 300 /* 301 * Interrupt handler triggered by NIC for handling 302 * specific interrupt. 303 * 304 * @param handle 305 * Pointer to interrupt handle. 306 * @param param 307 * The address of parameter (struct rte_eth_dev *) registered before. 308 * 309 * @return 310 * void 311 */ 312 static void 313 axgbe_dev_interrupt_handler(void *param) 314 { 315 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 316 struct axgbe_port *pdata = dev->data->dev_private; 317 unsigned int dma_isr, dma_ch_isr; 318 319 pdata->phy_if.an_isr(pdata); 320 /*DMA related interrupts*/ 321 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR); 322 PMD_DRV_LOG_LINE(DEBUG, "DMA_ISR=%#010x", dma_isr); 323 if (dma_isr) { 324 if (dma_isr & 1) { 325 dma_ch_isr = 326 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *) 327 pdata->rx_queues[0], 328 DMA_CH_SR); 329 PMD_DRV_LOG_LINE(DEBUG, "DMA_CH0_ISR=%#010x", dma_ch_isr); 330 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *) 331 pdata->rx_queues[0], 332 DMA_CH_SR, dma_ch_isr); 333 } 334 } 335 /* Unmask interrupts since disabled after generation */ 336 rte_intr_ack(pdata->pci_dev->intr_handle); 337 } 338 339 /* 340 * Configure device link speed and setup link. 341 * It returns 0 on success. 342 */ 343 static int 344 axgbe_dev_configure(struct rte_eth_dev *dev) 345 { 346 struct axgbe_port *pdata = dev->data->dev_private; 347 /* Checksum offload to hardware */ 348 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads & 349 RTE_ETH_RX_OFFLOAD_CHECKSUM; 350 return 0; 351 } 352 353 static int 354 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev) 355 { 356 struct axgbe_port *pdata = dev->data->dev_private; 357 358 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) 359 pdata->rss_enable = 1; 360 else if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_NONE) 361 pdata->rss_enable = 0; 362 else 363 return -1; 364 return 0; 365 } 366 367 static int 368 axgbe_dev_start(struct rte_eth_dev *dev) 369 { 370 struct axgbe_port *pdata = dev->data->dev_private; 371 uint16_t i; 372 int ret; 373 374 dev->dev_ops = &axgbe_eth_dev_ops; 375 376 PMD_INIT_FUNC_TRACE(); 377 378 /* Multiqueue RSS */ 379 ret = axgbe_dev_rx_mq_config(dev); 380 if (ret) { 381 PMD_DRV_LOG_LINE(ERR, "Unable to config RX MQ"); 382 return ret; 383 } 384 ret = axgbe_phy_reset(pdata); 385 if (ret) { 386 PMD_DRV_LOG_LINE(ERR, "phy reset failed"); 387 return ret; 388 } 389 ret = pdata->hw_if.init(pdata); 390 if (ret) { 391 PMD_DRV_LOG_LINE(ERR, "dev_init failed"); 392 return ret; 393 } 394 395 /* enable uio/vfio intr/eventfd mapping */ 396 rte_intr_enable(pdata->pci_dev->intr_handle); 397 398 /* phy start*/ 399 pdata->phy_if.phy_start(pdata); 400 axgbe_dev_enable_tx(dev); 401 axgbe_dev_enable_rx(dev); 402 403 rte_bit_relaxed_clear32(AXGBE_STOPPED, &pdata->dev_state); 404 rte_bit_relaxed_clear32(AXGBE_DOWN, &pdata->dev_state); 405 406 axgbe_set_rx_function(dev); 407 axgbe_set_tx_function(dev); 408 409 for (i = 0; i < dev->data->nb_rx_queues; i++) 410 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 411 for (i = 0; i < dev->data->nb_tx_queues; i++) 412 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 413 414 return 0; 415 } 416 417 /* Stop device: disable rx and tx functions to allow for reconfiguring. */ 418 static int 419 axgbe_dev_stop(struct rte_eth_dev *dev) 420 { 421 struct axgbe_port *pdata = dev->data->dev_private; 422 423 PMD_INIT_FUNC_TRACE(); 424 425 rte_intr_disable(pdata->pci_dev->intr_handle); 426 427 if (rte_bit_relaxed_get32(AXGBE_STOPPED, &pdata->dev_state)) 428 return 0; 429 430 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 431 axgbe_dev_disable_tx(dev); 432 axgbe_dev_disable_rx(dev); 433 434 pdata->phy_if.phy_stop(pdata); 435 pdata->hw_if.exit(pdata); 436 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); 437 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 438 439 return 0; 440 } 441 442 static int 443 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 444 { 445 struct axgbe_port *pdata = dev->data->dev_private; 446 447 PMD_INIT_FUNC_TRACE(); 448 449 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); 450 451 return 0; 452 } 453 454 static int 455 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 456 { 457 struct axgbe_port *pdata = dev->data->dev_private; 458 459 PMD_INIT_FUNC_TRACE(); 460 461 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); 462 463 return 0; 464 } 465 466 static int 467 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 468 { 469 struct axgbe_port *pdata = dev->data->dev_private; 470 471 PMD_INIT_FUNC_TRACE(); 472 473 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 474 return 0; 475 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1); 476 477 return 0; 478 } 479 480 static int 481 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 482 { 483 struct axgbe_port *pdata = dev->data->dev_private; 484 485 PMD_INIT_FUNC_TRACE(); 486 487 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 488 return 0; 489 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0); 490 491 return 0; 492 } 493 494 static int 495 axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 496 { 497 struct axgbe_port *pdata = dev->data->dev_private; 498 499 /* Set Default MAC Addr */ 500 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0); 501 502 return 0; 503 } 504 505 static int 506 axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 507 uint32_t index, uint32_t pool __rte_unused) 508 { 509 struct axgbe_port *pdata = dev->data->dev_private; 510 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 511 512 if (index > hw_feat->addn_mac) { 513 PMD_DRV_LOG_LINE(ERR, "Invalid Index %d", index); 514 return -EINVAL; 515 } 516 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index); 517 return 0; 518 } 519 520 static int 521 axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 522 struct rte_eth_rss_reta_entry64 *reta_conf, 523 uint16_t reta_size) 524 { 525 struct axgbe_port *pdata = dev->data->dev_private; 526 unsigned int i, idx, shift; 527 int ret; 528 529 if (!pdata->rss_enable) { 530 PMD_DRV_LOG_LINE(ERR, "RSS not enabled"); 531 return -ENOTSUP; 532 } 533 534 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 535 PMD_DRV_LOG_LINE(ERR, "reta_size %d is not supported", reta_size); 536 return -EINVAL; 537 } 538 539 for (i = 0; i < reta_size; i++) { 540 idx = i / RTE_ETH_RETA_GROUP_SIZE; 541 shift = i % RTE_ETH_RETA_GROUP_SIZE; 542 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 543 continue; 544 pdata->rss_table[i] = reta_conf[idx].reta[shift]; 545 } 546 547 /* Program the lookup table */ 548 ret = axgbe_write_rss_lookup_table(pdata); 549 return ret; 550 } 551 552 static int 553 axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 554 struct rte_eth_rss_reta_entry64 *reta_conf, 555 uint16_t reta_size) 556 { 557 struct axgbe_port *pdata = dev->data->dev_private; 558 unsigned int i, idx, shift; 559 560 if (!pdata->rss_enable) { 561 PMD_DRV_LOG_LINE(ERR, "RSS not enabled"); 562 return -ENOTSUP; 563 } 564 565 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 566 PMD_DRV_LOG_LINE(ERR, "reta_size %d is not supported", reta_size); 567 return -EINVAL; 568 } 569 570 for (i = 0; i < reta_size; i++) { 571 idx = i / RTE_ETH_RETA_GROUP_SIZE; 572 shift = i % RTE_ETH_RETA_GROUP_SIZE; 573 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 574 continue; 575 reta_conf[idx].reta[shift] = pdata->rss_table[i]; 576 } 577 return 0; 578 } 579 580 static int 581 axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 582 struct rte_eth_rss_conf *rss_conf) 583 { 584 struct axgbe_port *pdata = dev->data->dev_private; 585 int ret; 586 587 if (!pdata->rss_enable) { 588 PMD_DRV_LOG_LINE(ERR, "RSS not enabled"); 589 return -ENOTSUP; 590 } 591 592 if (rss_conf == NULL) { 593 PMD_DRV_LOG_LINE(ERR, "rss_conf value isn't valid"); 594 return -EINVAL; 595 } 596 597 if (rss_conf->rss_key != NULL && 598 rss_conf->rss_key_len == AXGBE_RSS_HASH_KEY_SIZE) { 599 rte_memcpy(pdata->rss_key, rss_conf->rss_key, 600 AXGBE_RSS_HASH_KEY_SIZE); 601 /* Program the hash key */ 602 ret = axgbe_write_rss_hash_key(pdata); 603 if (ret != 0) 604 return ret; 605 } 606 607 pdata->rss_hf = rss_conf->rss_hf & AXGBE_RSS_OFFLOAD; 608 609 if (pdata->rss_hf & (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6)) 610 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); 611 if (pdata->rss_hf & 612 (RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV6_TCP)) 613 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); 614 if (pdata->rss_hf & 615 (RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV6_UDP)) 616 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); 617 618 /* Set the RSS options */ 619 AXGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 620 621 return 0; 622 } 623 624 static int 625 axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 626 struct rte_eth_rss_conf *rss_conf) 627 { 628 struct axgbe_port *pdata = dev->data->dev_private; 629 630 if (!pdata->rss_enable) { 631 PMD_DRV_LOG_LINE(ERR, "RSS not enabled"); 632 return -ENOTSUP; 633 } 634 635 if (rss_conf == NULL) { 636 PMD_DRV_LOG_LINE(ERR, "rss_conf value isn't valid"); 637 return -EINVAL; 638 } 639 640 if (rss_conf->rss_key != NULL && 641 rss_conf->rss_key_len >= AXGBE_RSS_HASH_KEY_SIZE) { 642 rte_memcpy(rss_conf->rss_key, pdata->rss_key, 643 AXGBE_RSS_HASH_KEY_SIZE); 644 } 645 rss_conf->rss_key_len = AXGBE_RSS_HASH_KEY_SIZE; 646 rss_conf->rss_hf = pdata->rss_hf; 647 return 0; 648 } 649 650 static int 651 axgbe_dev_reset(struct rte_eth_dev *dev) 652 { 653 int ret = 0; 654 655 ret = axgbe_dev_close(dev); 656 if (ret) 657 return ret; 658 659 ret = eth_axgbe_dev_init(dev); 660 661 return ret; 662 } 663 664 static void 665 axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 666 { 667 struct axgbe_port *pdata = dev->data->dev_private; 668 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 669 670 if (index > hw_feat->addn_mac) { 671 PMD_DRV_LOG_LINE(ERR, "Invalid Index %d", index); 672 return; 673 } 674 axgbe_set_mac_addn_addr(pdata, NULL, index); 675 } 676 677 static int 678 axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 679 struct rte_ether_addr *mc_addr_set, 680 uint32_t nb_mc_addr) 681 { 682 struct axgbe_port *pdata = dev->data->dev_private; 683 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 684 uint32_t index = 1; /* 0 is always default mac */ 685 uint32_t i; 686 687 if (nb_mc_addr > hw_feat->addn_mac) { 688 PMD_DRV_LOG_LINE(ERR, "Invalid Index %d", nb_mc_addr); 689 return -EINVAL; 690 } 691 692 /* clear unicast addresses */ 693 for (i = 1; i < hw_feat->addn_mac; i++) { 694 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i])) 695 continue; 696 memset(&dev->data->mac_addrs[i], 0, 697 sizeof(struct rte_ether_addr)); 698 } 699 700 while (nb_mc_addr--) 701 axgbe_set_mac_addn_addr(pdata, (u8 *)mc_addr_set++, index++); 702 703 return 0; 704 } 705 706 static int 707 axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 708 struct rte_ether_addr *mac_addr, uint8_t add) 709 { 710 struct axgbe_port *pdata = dev->data->dev_private; 711 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 712 713 if (!hw_feat->hash_table_size) { 714 PMD_DRV_LOG_LINE(ERR, "MAC Hash Table not supported"); 715 return -ENOTSUP; 716 } 717 718 axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add); 719 720 if (pdata->uc_hash_mac_addr > 0) { 721 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 722 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 723 } else { 724 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 725 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 726 } 727 return 0; 728 } 729 730 static int 731 axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add) 732 { 733 struct axgbe_port *pdata = dev->data->dev_private; 734 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 735 uint32_t index; 736 737 if (!hw_feat->hash_table_size) { 738 PMD_DRV_LOG_LINE(ERR, "MAC Hash Table not supported"); 739 return -ENOTSUP; 740 } 741 742 for (index = 0; index < pdata->hash_table_count; index++) { 743 if (add) 744 pdata->uc_hash_table[index] = ~0; 745 else 746 pdata->uc_hash_table[index] = 0; 747 748 PMD_DRV_LOG_LINE(DEBUG, "%s MAC hash table at Index %#x", 749 add ? "set" : "clear", index); 750 751 AXGMAC_IOWRITE(pdata, MAC_HTR(index), 752 pdata->uc_hash_table[index]); 753 } 754 755 if (add) { 756 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 757 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 758 } else { 759 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 760 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 761 } 762 return 0; 763 } 764 765 /* return 0 means link status changed, -1 means not changed */ 766 static int 767 axgbe_dev_link_update(struct rte_eth_dev *dev, 768 int wait_to_complete __rte_unused) 769 { 770 struct axgbe_port *pdata = dev->data->dev_private; 771 struct rte_eth_link link; 772 int ret = 0; 773 774 PMD_INIT_FUNC_TRACE(); 775 rte_delay_ms(800); 776 777 pdata->phy_if.phy_status(pdata); 778 779 memset(&link, 0, sizeof(struct rte_eth_link)); 780 link.link_duplex = pdata->phy.duplex; 781 link.link_status = pdata->phy_link; 782 link.link_speed = pdata->phy_speed; 783 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 784 RTE_ETH_LINK_SPEED_FIXED); 785 ret = rte_eth_linkstatus_set(dev, &link); 786 if (ret == 0) 787 PMD_DRV_LOG_LINE(ERR, "Link status changed"); 788 789 return ret; 790 } 791 792 static int 793 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 794 { 795 struct axgbe_port *pdata = dev->data->dev_private; 796 797 if (regs->data == NULL) { 798 regs->length = axgbe_regs_get_count(pdata); 799 regs->width = sizeof(uint32_t); 800 return 0; 801 } 802 803 /* Only full register dump is supported */ 804 if (regs->length && 805 regs->length != (uint32_t)axgbe_regs_get_count(pdata)) 806 return -ENOTSUP; 807 808 regs->version = pdata->pci_dev->id.vendor_id << 16 | 809 pdata->pci_dev->id.device_id; 810 axgbe_regs_dump(pdata, regs->data); 811 return 0; 812 } 813 static void axgbe_read_mmc_stats(struct axgbe_port *pdata) 814 { 815 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 816 817 /* Freeze counters */ 818 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 819 820 /* Tx counters */ 821 stats->txoctetcount_gb += 822 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO); 823 stats->txoctetcount_gb += 824 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32); 825 826 stats->txframecount_gb += 827 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO); 828 stats->txframecount_gb += 829 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32); 830 831 stats->txbroadcastframes_g += 832 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO); 833 stats->txbroadcastframes_g += 834 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32); 835 836 stats->txmulticastframes_g += 837 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO); 838 stats->txmulticastframes_g += 839 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32); 840 841 stats->tx64octets_gb += 842 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO); 843 stats->tx64octets_gb += 844 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32); 845 846 stats->tx65to127octets_gb += 847 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO); 848 stats->tx65to127octets_gb += 849 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32); 850 851 stats->tx128to255octets_gb += 852 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO); 853 stats->tx128to255octets_gb += 854 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32); 855 856 stats->tx256to511octets_gb += 857 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO); 858 stats->tx256to511octets_gb += 859 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32); 860 861 stats->tx512to1023octets_gb += 862 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO); 863 stats->tx512to1023octets_gb += 864 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32); 865 866 stats->tx1024tomaxoctets_gb += 867 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 868 stats->tx1024tomaxoctets_gb += 869 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32); 870 871 stats->txunicastframes_gb += 872 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO); 873 stats->txunicastframes_gb += 874 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32); 875 876 stats->txmulticastframes_gb += 877 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 878 stats->txmulticastframes_gb += 879 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32); 880 881 stats->txbroadcastframes_g += 882 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 883 stats->txbroadcastframes_g += 884 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32); 885 886 stats->txunderflowerror += 887 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO); 888 stats->txunderflowerror += 889 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32); 890 891 stats->txoctetcount_g += 892 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO); 893 stats->txoctetcount_g += 894 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32); 895 896 stats->txframecount_g += 897 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO); 898 stats->txframecount_g += 899 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32); 900 901 stats->txpauseframes += 902 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO); 903 stats->txpauseframes += 904 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32); 905 906 stats->txvlanframes_g += 907 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO); 908 stats->txvlanframes_g += 909 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32); 910 911 /* Rx counters */ 912 stats->rxframecount_gb += 913 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO); 914 stats->rxframecount_gb += 915 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32); 916 917 stats->rxoctetcount_gb += 918 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO); 919 stats->rxoctetcount_gb += 920 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32); 921 922 stats->rxoctetcount_g += 923 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO); 924 stats->rxoctetcount_g += 925 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32); 926 927 stats->rxbroadcastframes_g += 928 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO); 929 stats->rxbroadcastframes_g += 930 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32); 931 932 stats->rxmulticastframes_g += 933 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO); 934 stats->rxmulticastframes_g += 935 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32); 936 937 stats->rxcrcerror += 938 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO); 939 stats->rxcrcerror += 940 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32); 941 942 stats->rxrunterror += 943 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR); 944 945 stats->rxjabbererror += 946 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR); 947 948 stats->rxundersize_g += 949 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G); 950 951 stats->rxoversize_g += 952 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G); 953 954 stats->rx64octets_gb += 955 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO); 956 stats->rx64octets_gb += 957 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32); 958 959 stats->rx65to127octets_gb += 960 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO); 961 stats->rx65to127octets_gb += 962 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32); 963 964 stats->rx128to255octets_gb += 965 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO); 966 stats->rx128to255octets_gb += 967 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32); 968 969 stats->rx256to511octets_gb += 970 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO); 971 stats->rx256to511octets_gb += 972 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32); 973 974 stats->rx512to1023octets_gb += 975 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO); 976 stats->rx512to1023octets_gb += 977 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32); 978 979 stats->rx1024tomaxoctets_gb += 980 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 981 stats->rx1024tomaxoctets_gb += 982 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32); 983 984 stats->rxunicastframes_g += 985 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO); 986 stats->rxunicastframes_g += 987 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32); 988 989 stats->rxlengtherror += 990 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO); 991 stats->rxlengtherror += 992 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32); 993 994 stats->rxoutofrangetype += 995 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO); 996 stats->rxoutofrangetype += 997 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32); 998 999 stats->rxpauseframes += 1000 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO); 1001 stats->rxpauseframes += 1002 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32); 1003 1004 stats->rxfifooverflow += 1005 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO); 1006 stats->rxfifooverflow += 1007 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32); 1008 1009 stats->rxvlanframes_gb += 1010 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO); 1011 stats->rxvlanframes_gb += 1012 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32); 1013 1014 stats->rxwatchdogerror += 1015 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR); 1016 1017 /* Un-freeze counters */ 1018 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 1019 } 1020 1021 static int 1022 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1023 unsigned int n) 1024 { 1025 struct axgbe_port *pdata = dev->data->dev_private; 1026 unsigned int i; 1027 1028 if (n < AXGBE_XSTATS_COUNT) 1029 return AXGBE_XSTATS_COUNT; 1030 1031 axgbe_read_mmc_stats(pdata); 1032 1033 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1034 stats[i].id = i; 1035 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1036 axgbe_xstats_strings[i].offset); 1037 } 1038 1039 return AXGBE_XSTATS_COUNT; 1040 } 1041 1042 static int 1043 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1044 struct rte_eth_xstat_name *xstats_names, 1045 unsigned int n) 1046 { 1047 unsigned int i; 1048 1049 if (n >= AXGBE_XSTATS_COUNT && xstats_names) { 1050 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) { 1051 snprintf(xstats_names[i].name, 1052 RTE_ETH_XSTATS_NAME_SIZE, "%s", 1053 axgbe_xstats_strings[i].name); 1054 } 1055 } 1056 1057 return AXGBE_XSTATS_COUNT; 1058 } 1059 1060 static int 1061 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1062 uint64_t *values, unsigned int n) 1063 { 1064 unsigned int i; 1065 uint64_t values_copy[AXGBE_XSTATS_COUNT]; 1066 1067 if (!ids) { 1068 struct axgbe_port *pdata = dev->data->dev_private; 1069 1070 if (n < AXGBE_XSTATS_COUNT) 1071 return AXGBE_XSTATS_COUNT; 1072 1073 axgbe_read_mmc_stats(pdata); 1074 1075 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1076 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1077 axgbe_xstats_strings[i].offset); 1078 } 1079 1080 return i; 1081 } 1082 1083 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT); 1084 1085 for (i = 0; i < n; i++) { 1086 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1087 PMD_DRV_LOG_LINE(ERR, "id value isn't valid"); 1088 return -1; 1089 } 1090 values[i] = values_copy[ids[i]]; 1091 } 1092 return n; 1093 } 1094 1095 static int 1096 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 1097 const uint64_t *ids, 1098 struct rte_eth_xstat_name *xstats_names, 1099 unsigned int size) 1100 { 1101 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT]; 1102 unsigned int i; 1103 1104 if (!ids) 1105 return axgbe_dev_xstats_get_names(dev, xstats_names, size); 1106 1107 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size); 1108 1109 for (i = 0; i < size; i++) { 1110 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1111 PMD_DRV_LOG_LINE(ERR, "id value isn't valid"); 1112 return -1; 1113 } 1114 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1115 } 1116 return size; 1117 } 1118 1119 static int 1120 axgbe_dev_xstats_reset(struct rte_eth_dev *dev) 1121 { 1122 struct axgbe_port *pdata = dev->data->dev_private; 1123 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 1124 1125 /* MMC registers are configured for reset on read */ 1126 axgbe_read_mmc_stats(pdata); 1127 1128 /* Reset stats */ 1129 memset(stats, 0, sizeof(*stats)); 1130 1131 return 0; 1132 } 1133 1134 static int 1135 axgbe_dev_stats_get(struct rte_eth_dev *dev, 1136 struct rte_eth_stats *stats) 1137 { 1138 struct axgbe_rx_queue *rxq; 1139 struct axgbe_tx_queue *txq; 1140 struct axgbe_port *pdata = dev->data->dev_private; 1141 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats; 1142 unsigned int i; 1143 1144 axgbe_read_mmc_stats(pdata); 1145 1146 stats->imissed = mmc_stats->rxfifooverflow; 1147 1148 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1149 rxq = dev->data->rx_queues[i]; 1150 if (rxq) { 1151 stats->q_ipackets[i] = rxq->pkts; 1152 stats->ipackets += rxq->pkts; 1153 stats->q_ibytes[i] = rxq->bytes; 1154 stats->ibytes += rxq->bytes; 1155 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed; 1156 stats->q_errors[i] = rxq->errors 1157 + rxq->rx_mbuf_alloc_failed; 1158 stats->ierrors += rxq->errors; 1159 } else { 1160 PMD_DRV_LOG_LINE(DEBUG, "Rx queue not setup for port %d", 1161 dev->data->port_id); 1162 } 1163 } 1164 1165 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1166 txq = dev->data->tx_queues[i]; 1167 if (txq) { 1168 stats->q_opackets[i] = txq->pkts; 1169 stats->opackets += txq->pkts; 1170 stats->q_obytes[i] = txq->bytes; 1171 stats->obytes += txq->bytes; 1172 stats->oerrors += txq->errors; 1173 } else { 1174 PMD_DRV_LOG_LINE(DEBUG, "Tx queue not setup for port %d", 1175 dev->data->port_id); 1176 } 1177 } 1178 1179 return 0; 1180 } 1181 1182 static int 1183 axgbe_dev_stats_reset(struct rte_eth_dev *dev) 1184 { 1185 struct axgbe_rx_queue *rxq; 1186 struct axgbe_tx_queue *txq; 1187 unsigned int i; 1188 1189 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1190 rxq = dev->data->rx_queues[i]; 1191 if (rxq) { 1192 rxq->pkts = 0; 1193 rxq->bytes = 0; 1194 rxq->errors = 0; 1195 rxq->rx_mbuf_alloc_failed = 0; 1196 } else { 1197 PMD_DRV_LOG_LINE(DEBUG, "Rx queue not setup for port %d", 1198 dev->data->port_id); 1199 } 1200 } 1201 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1202 txq = dev->data->tx_queues[i]; 1203 if (txq) { 1204 txq->pkts = 0; 1205 txq->bytes = 0; 1206 txq->errors = 0; 1207 } else { 1208 PMD_DRV_LOG_LINE(DEBUG, "Tx queue not setup for port %d", 1209 dev->data->port_id); 1210 } 1211 } 1212 1213 return 0; 1214 } 1215 1216 static int 1217 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1218 { 1219 struct axgbe_port *pdata = dev->data->dev_private; 1220 1221 dev_info->max_rx_queues = pdata->rx_ring_count; 1222 dev_info->max_tx_queues = pdata->tx_ring_count; 1223 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE; 1224 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE; 1225 dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1; 1226 dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size; 1227 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10G; 1228 1229 dev_info->rx_offload_capa = 1230 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 1231 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 1232 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | 1233 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 1234 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 1235 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 1236 RTE_ETH_RX_OFFLOAD_SCATTER | 1237 RTE_ETH_RX_OFFLOAD_KEEP_CRC; 1238 1239 dev_info->tx_offload_capa = 1240 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 1241 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | 1242 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 1243 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | 1244 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 1245 RTE_ETH_TX_OFFLOAD_TCP_CKSUM; 1246 1247 if (pdata->hw_feat.rss) { 1248 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD; 1249 dev_info->reta_size = pdata->hw_feat.hash_table_size; 1250 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE; 1251 } 1252 1253 dev_info->rx_desc_lim = rx_desc_lim; 1254 dev_info->tx_desc_lim = tx_desc_lim; 1255 1256 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1257 .rx_free_thresh = AXGBE_RX_FREE_THRESH, 1258 }; 1259 1260 dev_info->default_txconf = (struct rte_eth_txconf) { 1261 .tx_free_thresh = AXGBE_TX_FREE_THRESH, 1262 }; 1263 1264 return 0; 1265 } 1266 1267 static int 1268 axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1269 { 1270 struct axgbe_port *pdata = dev->data->dev_private; 1271 struct xgbe_fc_info fc = pdata->fc; 1272 unsigned int reg, reg_val = 0; 1273 1274 reg = MAC_Q0TFCR; 1275 reg_val = AXGMAC_IOREAD(pdata, reg); 1276 fc.low_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA); 1277 fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD); 1278 fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT); 1279 fc.autoneg = pdata->pause_autoneg; 1280 1281 if (pdata->rx_pause && pdata->tx_pause) 1282 fc.mode = RTE_ETH_FC_FULL; 1283 else if (pdata->rx_pause) 1284 fc.mode = RTE_ETH_FC_RX_PAUSE; 1285 else if (pdata->tx_pause) 1286 fc.mode = RTE_ETH_FC_TX_PAUSE; 1287 else 1288 fc.mode = RTE_ETH_FC_NONE; 1289 1290 fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024; 1291 fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024; 1292 fc_conf->pause_time = fc.pause_time[0]; 1293 fc_conf->send_xon = fc.send_xon; 1294 fc_conf->mode = fc.mode; 1295 1296 return 0; 1297 } 1298 1299 static int 1300 axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1301 { 1302 struct axgbe_port *pdata = dev->data->dev_private; 1303 struct xgbe_fc_info fc = pdata->fc; 1304 unsigned int reg, reg_val = 0; 1305 reg = MAC_Q0TFCR; 1306 1307 pdata->pause_autoneg = fc_conf->autoneg; 1308 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1309 fc.send_xon = fc_conf->send_xon; 1310 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA, 1311 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water)); 1312 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD, 1313 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water)); 1314 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time); 1315 AXGMAC_IOWRITE(pdata, reg, reg_val); 1316 fc.mode = fc_conf->mode; 1317 1318 if (fc.mode == RTE_ETH_FC_FULL) { 1319 pdata->tx_pause = 1; 1320 pdata->rx_pause = 1; 1321 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) { 1322 pdata->tx_pause = 0; 1323 pdata->rx_pause = 1; 1324 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) { 1325 pdata->tx_pause = 1; 1326 pdata->rx_pause = 0; 1327 } else { 1328 pdata->tx_pause = 0; 1329 pdata->rx_pause = 0; 1330 } 1331 1332 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1333 pdata->hw_if.config_tx_flow_control(pdata); 1334 1335 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1336 pdata->hw_if.config_rx_flow_control(pdata); 1337 1338 pdata->hw_if.config_flow_control(pdata); 1339 pdata->phy.tx_pause = pdata->tx_pause; 1340 pdata->phy.rx_pause = pdata->rx_pause; 1341 1342 return 0; 1343 } 1344 1345 static int 1346 axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 1347 struct rte_eth_pfc_conf *pfc_conf) 1348 { 1349 struct axgbe_port *pdata = dev->data->dev_private; 1350 struct xgbe_fc_info fc = pdata->fc; 1351 uint8_t tc_num; 1352 1353 tc_num = pdata->pfc_map[pfc_conf->priority]; 1354 1355 if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) { 1356 PMD_INIT_LOG(ERR, "Max supported traffic class: %d", 1357 pdata->hw_feat.tc_cnt); 1358 return -EINVAL; 1359 } 1360 1361 pdata->pause_autoneg = pfc_conf->fc.autoneg; 1362 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1363 fc.send_xon = pfc_conf->fc.send_xon; 1364 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA, 1365 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water)); 1366 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD, 1367 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water)); 1368 1369 switch (tc_num) { 1370 case 0: 1371 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1372 PSTC0, pfc_conf->fc.pause_time); 1373 break; 1374 case 1: 1375 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1376 PSTC1, pfc_conf->fc.pause_time); 1377 break; 1378 case 2: 1379 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1380 PSTC2, pfc_conf->fc.pause_time); 1381 break; 1382 case 3: 1383 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1384 PSTC3, pfc_conf->fc.pause_time); 1385 break; 1386 case 4: 1387 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1388 PSTC4, pfc_conf->fc.pause_time); 1389 break; 1390 case 5: 1391 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1392 PSTC5, pfc_conf->fc.pause_time); 1393 break; 1394 case 7: 1395 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1396 PSTC6, pfc_conf->fc.pause_time); 1397 break; 1398 case 6: 1399 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1400 PSTC7, pfc_conf->fc.pause_time); 1401 break; 1402 } 1403 1404 fc.mode = pfc_conf->fc.mode; 1405 1406 if (fc.mode == RTE_ETH_FC_FULL) { 1407 pdata->tx_pause = 1; 1408 pdata->rx_pause = 1; 1409 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1410 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) { 1411 pdata->tx_pause = 0; 1412 pdata->rx_pause = 1; 1413 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1414 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) { 1415 pdata->tx_pause = 1; 1416 pdata->rx_pause = 0; 1417 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1418 } else { 1419 pdata->tx_pause = 0; 1420 pdata->rx_pause = 0; 1421 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1422 } 1423 1424 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1425 pdata->hw_if.config_tx_flow_control(pdata); 1426 1427 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1428 pdata->hw_if.config_rx_flow_control(pdata); 1429 pdata->hw_if.config_flow_control(pdata); 1430 pdata->phy.tx_pause = pdata->tx_pause; 1431 pdata->phy.rx_pause = pdata->rx_pause; 1432 1433 return 0; 1434 } 1435 1436 void 1437 axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1438 struct rte_eth_rxq_info *qinfo) 1439 { 1440 struct axgbe_rx_queue *rxq; 1441 1442 rxq = dev->data->rx_queues[queue_id]; 1443 qinfo->mp = rxq->mb_pool; 1444 qinfo->scattered_rx = dev->data->scattered_rx; 1445 qinfo->nb_desc = rxq->nb_desc; 1446 qinfo->conf.rx_free_thresh = rxq->free_thresh; 1447 } 1448 1449 void 1450 axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1451 struct rte_eth_txq_info *qinfo) 1452 { 1453 struct axgbe_tx_queue *txq; 1454 1455 txq = dev->data->tx_queues[queue_id]; 1456 qinfo->nb_desc = txq->nb_desc; 1457 qinfo->conf.tx_free_thresh = txq->free_thresh; 1458 } 1459 const uint32_t * 1460 axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 1461 { 1462 static const uint32_t ptypes[] = { 1463 RTE_PTYPE_L2_ETHER, 1464 RTE_PTYPE_L2_ETHER_TIMESYNC, 1465 RTE_PTYPE_L2_ETHER_LLDP, 1466 RTE_PTYPE_L2_ETHER_ARP, 1467 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1468 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 1469 RTE_PTYPE_L4_FRAG, 1470 RTE_PTYPE_L4_ICMP, 1471 RTE_PTYPE_L4_NONFRAG, 1472 RTE_PTYPE_L4_SCTP, 1473 RTE_PTYPE_L4_TCP, 1474 RTE_PTYPE_L4_UDP, 1475 RTE_PTYPE_TUNNEL_GRENAT, 1476 RTE_PTYPE_TUNNEL_IP, 1477 RTE_PTYPE_INNER_L2_ETHER, 1478 RTE_PTYPE_INNER_L2_ETHER_VLAN, 1479 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 1480 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 1481 RTE_PTYPE_INNER_L4_FRAG, 1482 RTE_PTYPE_INNER_L4_ICMP, 1483 RTE_PTYPE_INNER_L4_NONFRAG, 1484 RTE_PTYPE_INNER_L4_SCTP, 1485 RTE_PTYPE_INNER_L4_TCP, 1486 RTE_PTYPE_INNER_L4_UDP, 1487 }; 1488 1489 if (dev->rx_pkt_burst == axgbe_recv_pkts) { 1490 *no_of_elements = RTE_DIM(ptypes); 1491 return ptypes; 1492 } 1493 return NULL; 1494 } 1495 1496 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1497 { 1498 struct axgbe_port *pdata = dev->data->dev_private; 1499 unsigned int val; 1500 1501 /* mtu setting is forbidden if port is start */ 1502 if (dev->data->dev_started) { 1503 PMD_DRV_LOG_LINE(ERR, "port %d must be stopped before configuration", 1504 dev->data->port_id); 1505 return -EBUSY; 1506 } 1507 val = mtu > RTE_ETHER_MTU ? 1 : 0; 1508 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 1509 1510 return 0; 1511 } 1512 1513 static void 1514 axgbe_update_tstamp_time(struct axgbe_port *pdata, 1515 unsigned int sec, unsigned int nsec, int addsub) 1516 { 1517 unsigned int count = 100; 1518 uint32_t sub_val = 0; 1519 uint32_t sub_val_sec = 0xFFFFFFFF; 1520 uint32_t sub_val_nsec = 0x3B9ACA00; 1521 1522 if (addsub) { 1523 if (sec) 1524 sub_val = sub_val_sec - (sec - 1); 1525 else 1526 sub_val = sec; 1527 1528 AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val); 1529 sub_val = sub_val_nsec - nsec; 1530 AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val); 1531 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1); 1532 } else { 1533 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1534 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0); 1535 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1536 } 1537 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1538 /* Wait for time update to complete */ 1539 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1540 rte_delay_ms(1); 1541 } 1542 1543 static inline uint64_t 1544 div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) 1545 { 1546 *remainder = dividend % divisor; 1547 return dividend / divisor; 1548 } 1549 1550 static inline uint64_t 1551 div_u64(uint64_t dividend, uint32_t divisor) 1552 { 1553 uint32_t remainder; 1554 return div_u64_rem(dividend, divisor, &remainder); 1555 } 1556 1557 static int 1558 axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta) 1559 { 1560 uint64_t adjust; 1561 uint32_t addend, diff; 1562 unsigned int neg_adjust = 0; 1563 1564 if (delta < 0) { 1565 neg_adjust = 1; 1566 delta = -delta; 1567 } 1568 adjust = (uint64_t)pdata->tstamp_addend; 1569 adjust *= delta; 1570 diff = (uint32_t)div_u64(adjust, 1000000000UL); 1571 addend = (neg_adjust) ? pdata->tstamp_addend - diff : 1572 pdata->tstamp_addend + diff; 1573 pdata->tstamp_addend = addend; 1574 axgbe_update_tstamp_addend(pdata, addend); 1575 return 0; 1576 } 1577 1578 static int 1579 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 1580 { 1581 struct axgbe_port *pdata = dev->data->dev_private; 1582 struct timespec timestamp_delta; 1583 1584 axgbe_adjfreq(pdata, delta); 1585 pdata->systime_tc.nsec += delta; 1586 1587 if (delta < 0) { 1588 delta = -delta; 1589 timestamp_delta = rte_ns_to_timespec(delta); 1590 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1591 timestamp_delta.tv_nsec, 1); 1592 } else { 1593 timestamp_delta = rte_ns_to_timespec(delta); 1594 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1595 timestamp_delta.tv_nsec, 0); 1596 } 1597 return 0; 1598 } 1599 1600 static int 1601 axgbe_timesync_read_time(struct rte_eth_dev *dev, 1602 struct timespec *timestamp) 1603 { 1604 uint64_t nsec; 1605 struct axgbe_port *pdata = dev->data->dev_private; 1606 1607 nsec = AXGMAC_IOREAD(pdata, MAC_STSR); 1608 nsec *= NSEC_PER_SEC; 1609 nsec += AXGMAC_IOREAD(pdata, MAC_STNR); 1610 *timestamp = rte_ns_to_timespec(nsec); 1611 return 0; 1612 } 1613 static int 1614 axgbe_timesync_write_time(struct rte_eth_dev *dev, 1615 const struct timespec *timestamp) 1616 { 1617 unsigned int count = 100; 1618 struct axgbe_port *pdata = dev->data->dev_private; 1619 1620 AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec); 1621 AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec); 1622 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1623 /* Wait for time update to complete */ 1624 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1625 rte_delay_ms(1); 1626 if (!count) 1627 PMD_DRV_LOG_LINE(ERR, "Timed out update timestamp"); 1628 return 0; 1629 } 1630 1631 static void 1632 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 1633 uint32_t addend) 1634 { 1635 unsigned int count = 100; 1636 1637 AXGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1638 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1639 1640 /* Wait for addend update to complete */ 1641 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1642 rte_delay_ms(1); 1643 if (!count) 1644 PMD_DRV_LOG_LINE(ERR, "Timed out updating timestamp addend register"); 1645 } 1646 1647 static void 1648 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 1649 unsigned int nsec) 1650 { 1651 unsigned int count = 100; 1652 1653 /*System Time Sec Update*/ 1654 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1655 /*System Time nanoSec Update*/ 1656 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1657 /*Initialize Timestamp*/ 1658 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1659 1660 /* Wait for time update to complete */ 1661 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1662 rte_delay_ms(1); 1663 if (!count) 1664 PMD_DRV_LOG_LINE(ERR, "Timed out initializing timestamp"); 1665 } 1666 1667 static int 1668 axgbe_timesync_enable(struct rte_eth_dev *dev) 1669 { 1670 struct axgbe_port *pdata = dev->data->dev_private; 1671 unsigned int mac_tscr = 0; 1672 uint64_t dividend; 1673 struct timespec timestamp; 1674 uint64_t nsec; 1675 1676 /* Set one nano-second accuracy */ 1677 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1678 1679 /* Set fine timestamp update */ 1680 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1681 1682 /* Overwrite earlier timestamps */ 1683 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1684 1685 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1686 1687 /* Enabling processing of ptp over eth pkt */ 1688 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1689 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1690 /* Enable timestamp for all pkts*/ 1691 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 1692 1693 /* enabling timestamp */ 1694 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1695 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1696 1697 /* Exit if timestamping is not enabled */ 1698 if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) { 1699 PMD_DRV_LOG_LINE(ERR, "Exiting as timestamp is not enabled"); 1700 return 0; 1701 } 1702 1703 /* Sub-second Increment Value*/ 1704 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC); 1705 /* Sub-nanosecond Increment Value */ 1706 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC); 1707 1708 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 1709 dividend = 50000000; 1710 dividend <<= 32; 1711 pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate); 1712 1713 axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1714 axgbe_set_tstamp_time(pdata, 0, 0); 1715 1716 /* Initialize the timecounter */ 1717 memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter)); 1718 1719 pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK; 1720 pdata->systime_tc.cc_shift = 0; 1721 pdata->systime_tc.nsec_mask = 0; 1722 1723 PMD_DRV_LOG_LINE(DEBUG, "Initializing system time counter with realtime"); 1724 1725 /* Updating the counter once with clock real time */ 1726 clock_gettime(CLOCK_REALTIME, ×tamp); 1727 nsec = rte_timespec_to_ns(×tamp); 1728 nsec = rte_timecounter_update(&pdata->systime_tc, nsec); 1729 axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec); 1730 return 0; 1731 } 1732 1733 static int 1734 axgbe_timesync_disable(struct rte_eth_dev *dev) 1735 { 1736 struct axgbe_port *pdata = dev->data->dev_private; 1737 unsigned int mac_tscr = 0; 1738 1739 /*disable timestamp for all pkts*/ 1740 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0); 1741 /*disable the addened register*/ 1742 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0); 1743 /* disable timestamp update */ 1744 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0); 1745 /*disable time stamp*/ 1746 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0); 1747 return 0; 1748 } 1749 1750 static int 1751 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 1752 struct timespec *timestamp, uint32_t flags) 1753 { 1754 uint64_t nsec = 0; 1755 volatile union axgbe_rx_desc *desc; 1756 uint16_t idx, pmt; 1757 struct axgbe_rx_queue *rxq = *dev->data->rx_queues; 1758 1759 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 1760 desc = &rxq->desc[idx]; 1761 1762 while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 1763 rte_delay_ms(1); 1764 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) { 1765 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) && 1766 !AXGMAC_GET_BITS_LE(desc->write.desc3, 1767 RX_CONTEXT_DESC3, TSD)) { 1768 pmt = AXGMAC_GET_BITS_LE(desc->write.desc3, 1769 RX_CONTEXT_DESC3, PMT); 1770 nsec = rte_le_to_cpu_32(desc->write.desc1); 1771 nsec *= NSEC_PER_SEC; 1772 nsec += rte_le_to_cpu_32(desc->write.desc0); 1773 if (nsec != 0xffffffffffffffffULL) { 1774 if (pmt == 0x01) 1775 *timestamp = rte_ns_to_timespec(nsec); 1776 PMD_DRV_LOG_LINE(DEBUG, 1777 "flags = 0x%x nsec = %"PRIu64, 1778 flags, nsec); 1779 } 1780 } 1781 } 1782 1783 return 0; 1784 } 1785 1786 static int 1787 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 1788 struct timespec *timestamp) 1789 { 1790 uint64_t nsec; 1791 struct axgbe_port *pdata = dev->data->dev_private; 1792 unsigned int tx_snr, tx_ssr; 1793 1794 rte_delay_us(5); 1795 if (pdata->vdata->tx_tstamp_workaround) { 1796 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1797 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1798 1799 } else { 1800 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1801 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1802 } 1803 if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) { 1804 PMD_DRV_LOG_LINE(DEBUG, "Waiting for TXTSSTSMIS"); 1805 return 0; 1806 } 1807 nsec = tx_ssr; 1808 nsec *= NSEC_PER_SEC; 1809 nsec += tx_snr; 1810 PMD_DRV_LOG_LINE(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d", 1811 nsec, tx_ssr, tx_snr); 1812 *timestamp = rte_ns_to_timespec(nsec); 1813 return 0; 1814 } 1815 1816 static int 1817 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1818 { 1819 struct axgbe_port *pdata = dev->data->dev_private; 1820 unsigned long vid_bit, vid_idx; 1821 1822 vid_bit = VLAN_TABLE_BIT(vid); 1823 vid_idx = VLAN_TABLE_IDX(vid); 1824 1825 if (on) { 1826 PMD_DRV_LOG_LINE(DEBUG, "Set VLAN vid=%d for device = %s", 1827 vid, pdata->eth_dev->device->name); 1828 pdata->active_vlans[vid_idx] |= vid_bit; 1829 } else { 1830 PMD_DRV_LOG_LINE(DEBUG, "Reset VLAN vid=%d for device = %s", 1831 vid, pdata->eth_dev->device->name); 1832 pdata->active_vlans[vid_idx] &= ~vid_bit; 1833 } 1834 pdata->hw_if.update_vlan_hash_table(pdata); 1835 return 0; 1836 } 1837 1838 static int 1839 axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1840 enum rte_vlan_type vlan_type, 1841 uint16_t tpid) 1842 { 1843 struct axgbe_port *pdata = dev->data->dev_private; 1844 uint32_t reg = 0; 1845 uint32_t qinq = 0; 1846 1847 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1848 PMD_DRV_LOG_LINE(DEBUG, "EDVLP: qinq = 0x%x", qinq); 1849 1850 switch (vlan_type) { 1851 case RTE_ETH_VLAN_TYPE_INNER: 1852 PMD_DRV_LOG_LINE(DEBUG, "RTE_ETH_VLAN_TYPE_INNER"); 1853 if (qinq) { 1854 if (tpid != 0x8100 && tpid != 0x88a8) 1855 PMD_DRV_LOG_LINE(ERR, 1856 "tag supported 0x8100/0x88A8"); 1857 PMD_DRV_LOG_LINE(DEBUG, "qinq with inner tag"); 1858 1859 /*Enable Inner VLAN Tag */ 1860 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 1); 1861 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1862 PMD_DRV_LOG_LINE(DEBUG, "bit ERIVLT = 0x%x", reg); 1863 1864 } else { 1865 PMD_DRV_LOG_LINE(ERR, 1866 "Inner type not supported in single tag"); 1867 } 1868 break; 1869 case RTE_ETH_VLAN_TYPE_OUTER: 1870 PMD_DRV_LOG_LINE(DEBUG, "RTE_ETH_VLAN_TYPE_OUTER"); 1871 if (qinq) { 1872 PMD_DRV_LOG_LINE(DEBUG, "double tagging is enabled"); 1873 /*Enable outer VLAN tag*/ 1874 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 0); 1875 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1876 PMD_DRV_LOG_LINE(DEBUG, "bit ERIVLT = 0x%x", reg); 1877 1878 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 1); 1879 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANIR, CSVL); 1880 PMD_DRV_LOG_LINE(DEBUG, "bit CSVL = 0x%x", reg); 1881 } else { 1882 if (tpid != 0x8100 && tpid != 0x88a8) 1883 PMD_DRV_LOG_LINE(ERR, 1884 "tag supported 0x8100/0x88A8"); 1885 } 1886 break; 1887 case RTE_ETH_VLAN_TYPE_MAX: 1888 PMD_DRV_LOG_LINE(ERR, "RTE_ETH_VLAN_TYPE_MAX"); 1889 break; 1890 case RTE_ETH_VLAN_TYPE_UNKNOWN: 1891 PMD_DRV_LOG_LINE(ERR, "RTE_ETH_VLAN_TYPE_UNKNOWN"); 1892 break; 1893 } 1894 return 0; 1895 } 1896 1897 static void axgbe_vlan_extend_enable(struct axgbe_port *pdata) 1898 { 1899 int qinq = 0; 1900 1901 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 1); 1902 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1903 PMD_DRV_LOG_LINE(DEBUG, "vlan double tag enabled EDVLP:qinq=0x%x", qinq); 1904 } 1905 1906 static void axgbe_vlan_extend_disable(struct axgbe_port *pdata) 1907 { 1908 int qinq = 0; 1909 1910 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 0); 1911 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1912 PMD_DRV_LOG_LINE(DEBUG, "vlan double tag disable EDVLP:qinq=0x%x", qinq); 1913 } 1914 1915 static int 1916 axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1917 { 1918 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1919 struct axgbe_port *pdata = dev->data->dev_private; 1920 1921 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 1922 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 1923 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 1924 1925 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 1926 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { 1927 PMD_DRV_LOG_LINE(DEBUG, "Strip ON for device = %s", 1928 pdata->eth_dev->device->name); 1929 pdata->hw_if.enable_rx_vlan_stripping(pdata); 1930 } else { 1931 PMD_DRV_LOG_LINE(DEBUG, "Strip OFF for device = %s", 1932 pdata->eth_dev->device->name); 1933 pdata->hw_if.disable_rx_vlan_stripping(pdata); 1934 } 1935 } 1936 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 1937 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 1938 PMD_DRV_LOG_LINE(DEBUG, "Filter ON for device = %s", 1939 pdata->eth_dev->device->name); 1940 pdata->hw_if.enable_rx_vlan_filtering(pdata); 1941 } else { 1942 PMD_DRV_LOG_LINE(DEBUG, "Filter OFF for device = %s", 1943 pdata->eth_dev->device->name); 1944 pdata->hw_if.disable_rx_vlan_filtering(pdata); 1945 } 1946 } 1947 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 1948 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) { 1949 PMD_DRV_LOG_LINE(DEBUG, "enabling vlan extended mode"); 1950 axgbe_vlan_extend_enable(pdata); 1951 /* Set global registers with default ethertype*/ 1952 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER, 1953 RTE_ETHER_TYPE_VLAN); 1954 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER, 1955 RTE_ETHER_TYPE_VLAN); 1956 } else { 1957 PMD_DRV_LOG_LINE(DEBUG, "disabling vlan extended mode"); 1958 axgbe_vlan_extend_disable(pdata); 1959 } 1960 } 1961 return 0; 1962 } 1963 1964 static void axgbe_get_all_hw_features(struct axgbe_port *pdata) 1965 { 1966 unsigned int mac_hfr0, mac_hfr1, mac_hfr2, mac_hfr3; 1967 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 1968 1969 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R); 1970 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R); 1971 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R); 1972 mac_hfr3 = AXGMAC_IOREAD(pdata, MAC_HWF3R); 1973 1974 memset(hw_feat, 0, sizeof(*hw_feat)); 1975 1976 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR); 1977 1978 /* Hardware feature register 0 */ 1979 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 1980 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 1981 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 1982 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 1983 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 1984 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 1985 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 1986 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 1987 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 1988 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 1989 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 1990 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 1991 ADDMACADRSEL); 1992 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 1993 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 1994 1995 /* Hardware feature register 1 */ 1996 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1997 RXFIFOSIZE); 1998 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1999 TXFIFOSIZE); 2000 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1, 2001 MAC_HWF1R, ADVTHWORD); 2002 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 2003 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 2004 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 2005 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 2006 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 2007 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 2008 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 2009 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 2010 HASHTBLSZ); 2011 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 2012 L3L4FNUM); 2013 2014 /* Hardware feature register 2 */ 2015 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 2016 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 2017 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 2018 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 2019 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 2020 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, 2021 AUXSNAPNUM); 2022 2023 /* Hardware feature register 3 */ 2024 hw_feat->tx_q_vlan_tag_ins = AXGMAC_GET_BITS(mac_hfr3, 2025 MAC_HWF3R, CBTISEL); 2026 hw_feat->no_of_vlan_extn = AXGMAC_GET_BITS(mac_hfr3, 2027 MAC_HWF3R, NRVF); 2028 2029 /* Translate the Hash Table size into actual number */ 2030 switch (hw_feat->hash_table_size) { 2031 case 0: 2032 break; 2033 case 1: 2034 hw_feat->hash_table_size = 64; 2035 break; 2036 case 2: 2037 hw_feat->hash_table_size = 128; 2038 break; 2039 case 3: 2040 hw_feat->hash_table_size = 256; 2041 break; 2042 } 2043 2044 /* Translate the address width setting into actual number */ 2045 switch (hw_feat->dma_width) { 2046 case 0: 2047 hw_feat->dma_width = 32; 2048 break; 2049 case 1: 2050 hw_feat->dma_width = 40; 2051 break; 2052 case 2: 2053 hw_feat->dma_width = 48; 2054 break; 2055 default: 2056 hw_feat->dma_width = 32; 2057 } 2058 2059 /* The Queue, Channel and TC counts are zero based so increment them 2060 * to get the actual number 2061 */ 2062 hw_feat->rx_q_cnt++; 2063 hw_feat->tx_q_cnt++; 2064 hw_feat->rx_ch_cnt++; 2065 hw_feat->tx_ch_cnt++; 2066 hw_feat->tc_cnt++; 2067 2068 /* Translate the fifo sizes into actual numbers */ 2069 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 2070 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 2071 } 2072 2073 static void axgbe_init_all_fptrs(struct axgbe_port *pdata) 2074 { 2075 axgbe_init_function_ptrs_dev(&pdata->hw_if); 2076 axgbe_init_function_ptrs_phy(&pdata->phy_if); 2077 axgbe_init_function_ptrs_i2c(&pdata->i2c_if); 2078 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 2079 } 2080 2081 static void axgbe_set_counts(struct axgbe_port *pdata) 2082 { 2083 /* Set all the function pointers */ 2084 axgbe_init_all_fptrs(pdata); 2085 2086 /* Populate the hardware features */ 2087 axgbe_get_all_hw_features(pdata); 2088 2089 /* Set default max values if not provided */ 2090 if (!pdata->tx_max_channel_count) 2091 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 2092 if (!pdata->rx_max_channel_count) 2093 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 2094 2095 if (!pdata->tx_max_q_count) 2096 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 2097 if (!pdata->rx_max_q_count) 2098 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 2099 2100 /* Calculate the number of Tx and Rx rings to be created 2101 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 2102 * the number of Tx queues to the number of Tx channels 2103 * enabled 2104 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 2105 * number of Rx queues or maximum allowed 2106 */ 2107 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt, 2108 pdata->tx_max_channel_count); 2109 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count, 2110 pdata->tx_max_q_count); 2111 2112 pdata->tx_q_count = pdata->tx_ring_count; 2113 2114 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt, 2115 pdata->rx_max_channel_count); 2116 2117 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt, 2118 pdata->rx_max_q_count); 2119 } 2120 2121 static void axgbe_default_config(struct axgbe_port *pdata) 2122 { 2123 pdata->pblx8 = DMA_PBL_X8_ENABLE; 2124 pdata->tx_sf_mode = MTL_TSF_ENABLE; 2125 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 2126 pdata->tx_pbl = DMA_PBL_32; 2127 pdata->tx_osp_mode = DMA_OSP_ENABLE; 2128 pdata->rx_sf_mode = MTL_RSF_ENABLE; 2129 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 2130 pdata->rx_pbl = DMA_PBL_32; 2131 pdata->pause_autoneg = 1; 2132 pdata->tx_pause = 0; 2133 pdata->rx_pause = 0; 2134 pdata->phy_speed = SPEED_UNKNOWN; 2135 pdata->power_down = 0; 2136 } 2137 2138 /* Used in dev_start by primary process and then 2139 * in dev_init by secondary process when attaching to an existing ethdev. 2140 */ 2141 void 2142 axgbe_set_tx_function(struct rte_eth_dev *dev) 2143 { 2144 struct axgbe_port *pdata = dev->data->dev_private; 2145 2146 dev->tx_pkt_burst = &axgbe_xmit_pkts; 2147 2148 if (pdata->multi_segs_tx) 2149 dev->tx_pkt_burst = &axgbe_xmit_pkts_seg; 2150 #ifdef RTE_ARCH_X86 2151 struct axgbe_tx_queue *txq = dev->data->tx_queues[0]; 2152 if (!txq->vector_disable && 2153 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) 2154 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec; 2155 #endif 2156 } 2157 2158 void 2159 axgbe_set_rx_function(struct rte_eth_dev *dev) 2160 { 2161 struct rte_eth_dev_data *dev_data = dev->data; 2162 uint16_t max_pkt_len; 2163 struct axgbe_port *pdata; 2164 2165 pdata = dev->data->dev_private; 2166 max_pkt_len = dev_data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 2167 if ((dev_data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) || 2168 max_pkt_len > pdata->rx_buf_size) 2169 dev_data->scattered_rx = 1; 2170 /* Scatter Rx handling */ 2171 if (dev_data->scattered_rx) 2172 dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts; 2173 else 2174 dev->rx_pkt_burst = &axgbe_recv_pkts; 2175 } 2176 2177 /* 2178 * It returns 0 on success. 2179 */ 2180 static int 2181 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) 2182 { 2183 PMD_INIT_FUNC_TRACE(); 2184 struct axgbe_port *pdata; 2185 struct rte_pci_device *pci_dev; 2186 uint32_t reg, mac_lo, mac_hi; 2187 uint32_t len; 2188 int ret; 2189 2190 unsigned int eax = 0, ebx = 0, ecx = 0, edx = 0; 2191 unsigned char cpu_family = 0, cpu_model = 0; 2192 2193 eth_dev->dev_ops = &axgbe_eth_dev_ops; 2194 2195 eth_dev->rx_descriptor_status = axgbe_dev_rx_descriptor_status; 2196 eth_dev->tx_descriptor_status = axgbe_dev_tx_descriptor_status; 2197 2198 eth_dev->tx_pkt_burst = &axgbe_xmit_pkts; 2199 eth_dev->rx_pkt_burst = &axgbe_recv_pkts; 2200 2201 /* 2202 * For secondary processes, we don't initialise any further as primary 2203 * has already done this work. 2204 */ 2205 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2206 axgbe_set_tx_function(eth_dev); 2207 axgbe_set_rx_function(eth_dev); 2208 return 0; 2209 } 2210 2211 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2212 2213 pdata = eth_dev->data->dev_private; 2214 /* initial state */ 2215 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 2216 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 2217 pdata->eth_dev = eth_dev; 2218 2219 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2220 pdata->pci_dev = pci_dev; 2221 2222 pdata->xgmac_regs = 2223 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; 2224 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs 2225 + AXGBE_MAC_PROP_OFFSET); 2226 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs 2227 + AXGBE_I2C_CTRL_OFFSET); 2228 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; 2229 2230 /* version specific driver data*/ 2231 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A) 2232 pdata->vdata = &axgbe_v2a; 2233 else 2234 pdata->vdata = &axgbe_v2b; 2235 2236 /* 2237 * Use CPUID to get Family and model ID to identify the CPU 2238 */ 2239 __cpuid(0x0, eax, ebx, ecx, edx); 2240 2241 if (ebx == CPUID_VENDOR_AuthenticAMD_ebx && 2242 edx == CPUID_VENDOR_AuthenticAMD_edx && 2243 ecx == CPUID_VENDOR_AuthenticAMD_ecx) { 2244 int unknown_cpu = 0; 2245 eax = 0, ebx = 0, ecx = 0, edx = 0; 2246 2247 __cpuid(0x1, eax, ebx, ecx, edx); 2248 2249 cpu_family = ((GET_BITS(eax, 8, 4)) + (GET_BITS(eax, 20, 8))); 2250 cpu_model = ((GET_BITS(eax, 4, 4)) | (((GET_BITS(eax, 16, 4)) << 4) & 0xF0)); 2251 2252 switch (cpu_family) { 2253 case Fam17h: 2254 /* V1000/R1000 */ 2255 if (cpu_model >= 0x10 && cpu_model <= 0x1F) { 2256 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; 2257 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; 2258 /* EPYC 3000 */ 2259 } else if (cpu_model >= 0x01 && cpu_model <= 0x0F) { 2260 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 2261 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 2262 } else { 2263 unknown_cpu = 1; 2264 } 2265 break; 2266 case Fam19h: 2267 /* V3000 (Yellow Carp) */ 2268 if (cpu_model >= 0x44 && cpu_model <= 0x47) { 2269 pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF; 2270 pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT; 2271 2272 /* Yellow Carp devices do not need cdr workaround */ 2273 pdata->vdata->an_cdr_workaround = 0; 2274 2275 /* Yellow Carp devices do not need rrc */ 2276 pdata->vdata->enable_rrc = 0; 2277 } else { 2278 unknown_cpu = 1; 2279 } 2280 break; 2281 default: 2282 unknown_cpu = 1; 2283 break; 2284 } 2285 if (unknown_cpu) { 2286 PMD_DRV_LOG_LINE(ERR, "Unknown CPU family, no supported axgbe device found"); 2287 return -ENODEV; 2288 } 2289 } 2290 2291 /* Configure the PCS indirect addressing support */ 2292 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); 2293 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 2294 pdata->xpcs_window <<= 6; 2295 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 2296 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 2297 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 2298 2299 PMD_INIT_LOG(DEBUG, 2300 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, 2301 pdata->xpcs_window_size, pdata->xpcs_window_mask); 2302 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 2303 2304 /* Retrieve the MAC address */ 2305 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 2306 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 2307 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff; 2308 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff; 2309 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff; 2310 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff; 2311 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff; 2312 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff; 2313 2314 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_MAC_ADDRS; 2315 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", len, 0); 2316 2317 if (!eth_dev->data->mac_addrs) { 2318 PMD_INIT_LOG(ERR, 2319 "Failed to alloc %u bytes needed to " 2320 "store MAC addresses", len); 2321 return -ENOMEM; 2322 } 2323 2324 /* Allocate memory for storing hash filter MAC addresses */ 2325 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS; 2326 eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr", 2327 len, 0); 2328 2329 if (eth_dev->data->hash_mac_addrs == NULL) { 2330 PMD_INIT_LOG(ERR, 2331 "Failed to allocate %d bytes needed to " 2332 "store MAC addresses", len); 2333 return -ENOMEM; 2334 } 2335 2336 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr)) 2337 rte_eth_random_addr(pdata->mac_addr.addr_bytes); 2338 2339 /* Copy the permanent MAC address */ 2340 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]); 2341 2342 /* Clock settings */ 2343 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ; 2344 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 2345 2346 /* Set the DMA coherency values */ 2347 pdata->coherent = 1; 2348 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN; 2349 pdata->arcache = AXGBE_DMA_OS_ARCACHE; 2350 pdata->awcache = AXGBE_DMA_OS_AWCACHE; 2351 2352 /* Read the port property registers */ 2353 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0); 2354 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1); 2355 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2); 2356 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3); 2357 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4); 2358 2359 /* Set the maximum channels and queues */ 2360 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_TX_DMA); 2361 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_RX_DMA); 2362 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_TX_QUEUES); 2363 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_RX_QUEUES); 2364 2365 /* Set the hardware channel and queue counts */ 2366 axgbe_set_counts(pdata); 2367 2368 /* Set the maximum fifo amounts */ 2369 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2, TX_FIFO_SIZE); 2370 pdata->tx_max_fifo_size *= 16384; 2371 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size, 2372 pdata->vdata->tx_max_fifo_size); 2373 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2, RX_FIFO_SIZE); 2374 pdata->rx_max_fifo_size *= 16384; 2375 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size, 2376 pdata->vdata->rx_max_fifo_size); 2377 /* Issue software reset to DMA */ 2378 ret = pdata->hw_if.exit(pdata); 2379 if (ret) 2380 PMD_DRV_LOG_LINE(ERR, "hw_if->exit EBUSY error"); 2381 2382 /* Set default configuration data */ 2383 axgbe_default_config(pdata); 2384 2385 /* Set default max values if not provided */ 2386 if (!pdata->tx_max_fifo_size) 2387 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 2388 if (!pdata->rx_max_fifo_size) 2389 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 2390 2391 pdata->tx_desc_count = AXGBE_MAX_RING_DESC; 2392 pdata->rx_desc_count = AXGBE_MAX_RING_DESC; 2393 pthread_mutex_init(&pdata->xpcs_mutex, NULL); 2394 pthread_mutex_init(&pdata->i2c_mutex, NULL); 2395 pthread_mutex_init(&pdata->an_mutex, NULL); 2396 pthread_mutex_init(&pdata->phy_mutex, NULL); 2397 2398 ret = pdata->phy_if.phy_init(pdata); 2399 if (ret) { 2400 rte_free(eth_dev->data->mac_addrs); 2401 eth_dev->data->mac_addrs = NULL; 2402 return ret; 2403 } 2404 2405 rte_intr_callback_register(pci_dev->intr_handle, 2406 axgbe_dev_interrupt_handler, 2407 (void *)eth_dev); 2408 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 2409 eth_dev->data->port_id, pci_dev->id.vendor_id, 2410 pci_dev->id.device_id); 2411 2412 return 0; 2413 } 2414 2415 static int 2416 axgbe_dev_close(struct rte_eth_dev *eth_dev) 2417 { 2418 struct rte_pci_device *pci_dev; 2419 struct axgbe_port *pdata; 2420 2421 PMD_INIT_FUNC_TRACE(); 2422 2423 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2424 return 0; 2425 2426 pdata = eth_dev->data->dev_private; 2427 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2428 axgbe_dev_clear_queues(eth_dev); 2429 2430 /* disable uio intr before callback unregister */ 2431 rte_intr_disable(pci_dev->intr_handle); 2432 rte_intr_callback_unregister(pci_dev->intr_handle, 2433 axgbe_dev_interrupt_handler, 2434 (void *)eth_dev); 2435 2436 /* Disable all interrupts in the hardware */ 2437 XP_IOWRITE(pdata, XP_INT_EN, 0x0); 2438 2439 return 0; 2440 } 2441 2442 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2443 struct rte_pci_device *pci_dev) 2444 { 2445 return rte_eth_dev_pci_generic_probe(pci_dev, 2446 sizeof(struct axgbe_port), eth_axgbe_dev_init); 2447 } 2448 2449 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev) 2450 { 2451 return rte_eth_dev_pci_generic_remove(pci_dev, axgbe_dev_close); 2452 } 2453 2454 static struct rte_pci_driver rte_axgbe_pmd = { 2455 .id_table = pci_id_axgbe_map, 2456 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2457 .probe = eth_axgbe_pci_probe, 2458 .remove = eth_axgbe_pci_remove, 2459 }; 2460 2461 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd); 2462 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map); 2463 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 2464 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_init, init, NOTICE); 2465 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_driver, driver, NOTICE); 2466