1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_common.h" 8 #include "axgbe_phy.h" 9 10 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); 11 static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev); 12 13 /* The set of PCI devices this driver supports */ 14 #define AMD_PCI_VENDOR_ID 0x1022 15 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 16 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459 17 18 int axgbe_logtype_init; 19 int axgbe_logtype_driver; 20 21 static const struct rte_pci_id pci_id_axgbe_map[] = { 22 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)}, 23 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)}, 24 { .vendor_id = 0, }, 25 }; 26 27 static struct axgbe_version_data axgbe_v2a = { 28 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 29 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 30 .mmc_64bit = 1, 31 .tx_max_fifo_size = 229376, 32 .rx_max_fifo_size = 229376, 33 .tx_tstamp_workaround = 1, 34 .ecc_support = 1, 35 .i2c_support = 1, 36 }; 37 38 static struct axgbe_version_data axgbe_v2b = { 39 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 40 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 41 .mmc_64bit = 1, 42 .tx_max_fifo_size = 65536, 43 .rx_max_fifo_size = 65536, 44 .tx_tstamp_workaround = 1, 45 .ecc_support = 1, 46 .i2c_support = 1, 47 }; 48 49 static void axgbe_get_all_hw_features(struct axgbe_port *pdata) 50 { 51 unsigned int mac_hfr0, mac_hfr1, mac_hfr2; 52 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 53 54 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R); 55 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R); 56 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R); 57 58 memset(hw_feat, 0, sizeof(*hw_feat)); 59 60 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR); 61 62 /* Hardware feature register 0 */ 63 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 64 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 65 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 66 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 67 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 68 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 69 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 70 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 71 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 72 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 73 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 74 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 75 ADDMACADRSEL); 76 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 77 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 78 79 /* Hardware feature register 1 */ 80 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 81 RXFIFOSIZE); 82 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 83 TXFIFOSIZE); 84 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1, 85 MAC_HWF1R, ADVTHWORD); 86 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 87 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 88 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 89 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 90 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 91 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 92 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 93 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 94 HASHTBLSZ); 95 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 96 L3L4FNUM); 97 98 /* Hardware feature register 2 */ 99 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 100 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 101 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 102 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 103 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 104 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, 105 AUXSNAPNUM); 106 107 /* Translate the Hash Table size into actual number */ 108 switch (hw_feat->hash_table_size) { 109 case 0: 110 break; 111 case 1: 112 hw_feat->hash_table_size = 64; 113 break; 114 case 2: 115 hw_feat->hash_table_size = 128; 116 break; 117 case 3: 118 hw_feat->hash_table_size = 256; 119 break; 120 } 121 122 /* Translate the address width setting into actual number */ 123 switch (hw_feat->dma_width) { 124 case 0: 125 hw_feat->dma_width = 32; 126 break; 127 case 1: 128 hw_feat->dma_width = 40; 129 break; 130 case 2: 131 hw_feat->dma_width = 48; 132 break; 133 default: 134 hw_feat->dma_width = 32; 135 } 136 137 /* The Queue, Channel and TC counts are zero based so increment them 138 * to get the actual number 139 */ 140 hw_feat->rx_q_cnt++; 141 hw_feat->tx_q_cnt++; 142 hw_feat->rx_ch_cnt++; 143 hw_feat->tx_ch_cnt++; 144 hw_feat->tc_cnt++; 145 146 /* Translate the fifo sizes into actual numbers */ 147 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 148 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 149 } 150 151 static void axgbe_init_all_fptrs(struct axgbe_port *pdata) 152 { 153 axgbe_init_function_ptrs_dev(&pdata->hw_if); 154 axgbe_init_function_ptrs_phy(&pdata->phy_if); 155 axgbe_init_function_ptrs_i2c(&pdata->i2c_if); 156 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 157 } 158 159 static void axgbe_set_counts(struct axgbe_port *pdata) 160 { 161 /* Set all the function pointers */ 162 axgbe_init_all_fptrs(pdata); 163 164 /* Populate the hardware features */ 165 axgbe_get_all_hw_features(pdata); 166 167 /* Set default max values if not provided */ 168 if (!pdata->tx_max_channel_count) 169 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 170 if (!pdata->rx_max_channel_count) 171 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 172 173 if (!pdata->tx_max_q_count) 174 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 175 if (!pdata->rx_max_q_count) 176 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 177 178 /* Calculate the number of Tx and Rx rings to be created 179 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 180 * the number of Tx queues to the number of Tx channels 181 * enabled 182 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 183 * number of Rx queues or maximum allowed 184 */ 185 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt, 186 pdata->tx_max_channel_count); 187 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count, 188 pdata->tx_max_q_count); 189 190 pdata->tx_q_count = pdata->tx_ring_count; 191 192 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt, 193 pdata->rx_max_channel_count); 194 195 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt, 196 pdata->rx_max_q_count); 197 } 198 199 static void axgbe_default_config(struct axgbe_port *pdata) 200 { 201 pdata->pblx8 = DMA_PBL_X8_ENABLE; 202 pdata->tx_sf_mode = MTL_TSF_ENABLE; 203 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 204 pdata->tx_pbl = DMA_PBL_32; 205 pdata->tx_osp_mode = DMA_OSP_ENABLE; 206 pdata->rx_sf_mode = MTL_RSF_ENABLE; 207 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 208 pdata->rx_pbl = DMA_PBL_32; 209 pdata->pause_autoneg = 1; 210 pdata->tx_pause = 0; 211 pdata->rx_pause = 0; 212 pdata->phy_speed = SPEED_UNKNOWN; 213 pdata->power_down = 0; 214 } 215 216 /* 217 * It returns 0 on success. 218 */ 219 static int 220 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) 221 { 222 PMD_INIT_FUNC_TRACE(); 223 struct axgbe_port *pdata; 224 struct rte_pci_device *pci_dev; 225 uint32_t reg, mac_lo, mac_hi; 226 int ret; 227 228 /* 229 * For secondary processes, we don't initialise any further as primary 230 * has already done this work. 231 */ 232 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 233 return 0; 234 235 pdata = (struct axgbe_port *)eth_dev->data->dev_private; 236 /* initial state */ 237 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state); 238 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state); 239 pdata->eth_dev = eth_dev; 240 241 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 242 pdata->pci_dev = pci_dev; 243 244 pdata->xgmac_regs = 245 (uint64_t)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; 246 pdata->xprop_regs = pdata->xgmac_regs + AXGBE_MAC_PROP_OFFSET; 247 pdata->xi2c_regs = pdata->xgmac_regs + AXGBE_I2C_CTRL_OFFSET; 248 pdata->xpcs_regs = (uint64_t)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; 249 250 /* version specific driver data*/ 251 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A) 252 pdata->vdata = &axgbe_v2a; 253 else 254 pdata->vdata = &axgbe_v2b; 255 256 /* Configure the PCS indirect addressing support */ 257 reg = XPCS32_IOREAD(pdata, PCS_V2_WINDOW_DEF); 258 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 259 pdata->xpcs_window <<= 6; 260 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 261 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 262 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 263 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 264 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 265 PMD_INIT_LOG(DEBUG, 266 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, 267 pdata->xpcs_window_size, pdata->xpcs_window_mask); 268 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 269 270 /* Retrieve the MAC address */ 271 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 272 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 273 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff; 274 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff; 275 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff; 276 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff; 277 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff; 278 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff; 279 280 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", 281 ETHER_ADDR_LEN, 0); 282 if (!eth_dev->data->mac_addrs) { 283 PMD_INIT_LOG(ERR, 284 "Failed to alloc %u bytes needed to store MAC addr tbl", 285 ETHER_ADDR_LEN); 286 return -ENOMEM; 287 } 288 289 if (!is_valid_assigned_ether_addr(&pdata->mac_addr)) 290 eth_random_addr(pdata->mac_addr.addr_bytes); 291 292 /* Copy the permanent MAC address */ 293 ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]); 294 295 /* Clock settings */ 296 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ; 297 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 298 299 /* Set the DMA coherency values */ 300 pdata->coherent = 1; 301 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN; 302 pdata->arcache = AXGBE_DMA_OS_ARCACHE; 303 pdata->awcache = AXGBE_DMA_OS_AWCACHE; 304 305 /* Set the maximum channels and queues */ 306 reg = XP_IOREAD(pdata, XP_PROP_1); 307 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA); 308 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA); 309 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES); 310 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES); 311 312 /* Set the hardware channel and queue counts */ 313 axgbe_set_counts(pdata); 314 315 /* Set the maximum fifo amounts */ 316 reg = XP_IOREAD(pdata, XP_PROP_2); 317 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE); 318 pdata->tx_max_fifo_size *= 16384; 319 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size, 320 pdata->vdata->tx_max_fifo_size); 321 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE); 322 pdata->rx_max_fifo_size *= 16384; 323 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size, 324 pdata->vdata->rx_max_fifo_size); 325 /* Issue software reset to DMA */ 326 ret = pdata->hw_if.exit(pdata); 327 if (ret) 328 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n"); 329 330 /* Set default configuration data */ 331 axgbe_default_config(pdata); 332 333 /* Set default max values if not provided */ 334 if (!pdata->tx_max_fifo_size) 335 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 336 if (!pdata->rx_max_fifo_size) 337 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 338 339 pthread_mutex_init(&pdata->xpcs_mutex, NULL); 340 pthread_mutex_init(&pdata->i2c_mutex, NULL); 341 pthread_mutex_init(&pdata->an_mutex, NULL); 342 pthread_mutex_init(&pdata->phy_mutex, NULL); 343 344 ret = pdata->phy_if.phy_init(pdata); 345 if (ret) { 346 rte_free(eth_dev->data->mac_addrs); 347 return ret; 348 } 349 350 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 351 eth_dev->data->port_id, pci_dev->id.vendor_id, 352 pci_dev->id.device_id); 353 354 return 0; 355 } 356 357 static int 358 eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev) 359 { 360 PMD_INIT_FUNC_TRACE(); 361 362 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 363 return 0; 364 365 /*Free macaddres*/ 366 rte_free(eth_dev->data->mac_addrs); 367 eth_dev->data->mac_addrs = NULL; 368 369 return 0; 370 } 371 372 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 373 struct rte_pci_device *pci_dev) 374 { 375 return rte_eth_dev_pci_generic_probe(pci_dev, 376 sizeof(struct axgbe_port), eth_axgbe_dev_init); 377 } 378 379 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev) 380 { 381 return rte_eth_dev_pci_generic_remove(pci_dev, eth_axgbe_dev_uninit); 382 } 383 384 static struct rte_pci_driver rte_axgbe_pmd = { 385 .id_table = pci_id_axgbe_map, 386 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 387 .probe = eth_axgbe_pci_probe, 388 .remove = eth_axgbe_pci_remove, 389 }; 390 391 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd); 392 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map); 393 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 394 395 RTE_INIT(axgbe_init_log); 396 static void 397 axgbe_init_log(void) 398 { 399 axgbe_logtype_init = rte_log_register("pmd.net.axgbe.init"); 400 if (axgbe_logtype_init >= 0) 401 rte_log_set_level(axgbe_logtype_init, RTE_LOG_NOTICE); 402 axgbe_logtype_driver = rte_log_register("pmd.net.axgbe.driver"); 403 if (axgbe_logtype_driver >= 0) 404 rte_log_set_level(axgbe_logtype_driver, RTE_LOG_NOTICE); 405 } 406