1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_rxtx.h" 7 #include "axgbe_ethdev.h" 8 #include "axgbe_common.h" 9 #include "axgbe_phy.h" 10 #include "axgbe_regs.h" 11 #include "rte_time.h" 12 13 #include "eal_filesystem.h" 14 15 #include <rte_vect.h> 16 17 #ifdef RTE_ARCH_X86 18 #include <cpuid.h> 19 #else 20 #define __cpuid(n, a, b, c, d) 21 #endif 22 23 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); 24 static int axgbe_dev_configure(struct rte_eth_dev *dev); 25 static int axgbe_dev_start(struct rte_eth_dev *dev); 26 static int axgbe_dev_stop(struct rte_eth_dev *dev); 27 static void axgbe_dev_interrupt_handler(void *param); 28 static int axgbe_dev_close(struct rte_eth_dev *dev); 29 static int axgbe_dev_reset(struct rte_eth_dev *dev); 30 static int axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 31 static int axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 32 static int axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 33 static int axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 34 static int axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, 35 struct rte_ether_addr *mac_addr); 36 static int axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, 37 struct rte_ether_addr *mac_addr, 38 uint32_t index, 39 uint32_t vmdq); 40 static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 41 static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 42 struct rte_ether_addr *mc_addr_set, 43 uint32_t nb_mc_addr); 44 static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 45 struct rte_ether_addr *mac_addr, 46 uint8_t add); 47 static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, 48 uint8_t add); 49 static int axgbe_dev_link_update(struct rte_eth_dev *dev, 50 int wait_to_complete); 51 static int axgbe_dev_get_regs(struct rte_eth_dev *dev, 52 struct rte_dev_reg_info *regs); 53 static int axgbe_dev_stats_get(struct rte_eth_dev *dev, 54 struct rte_eth_stats *stats); 55 static int axgbe_dev_stats_reset(struct rte_eth_dev *dev); 56 static int axgbe_dev_xstats_get(struct rte_eth_dev *dev, 57 struct rte_eth_xstat *stats, 58 unsigned int n); 59 static int 60 axgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 61 struct rte_eth_xstat_name *xstats_names, 62 unsigned int size); 63 static int 64 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 65 const uint64_t *ids, 66 uint64_t *values, 67 unsigned int n); 68 static int 69 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 70 const uint64_t *ids, 71 struct rte_eth_xstat_name *xstats_names, 72 unsigned int size); 73 static int axgbe_dev_xstats_reset(struct rte_eth_dev *dev); 74 static int axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 75 struct rte_eth_rss_reta_entry64 *reta_conf, 76 uint16_t reta_size); 77 static int axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 78 struct rte_eth_rss_reta_entry64 *reta_conf, 79 uint16_t reta_size); 80 static int axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 81 struct rte_eth_rss_conf *rss_conf); 82 static int axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 83 struct rte_eth_rss_conf *rss_conf); 84 static int axgbe_dev_info_get(struct rte_eth_dev *dev, 85 struct rte_eth_dev_info *dev_info); 86 static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, 87 struct rte_eth_fc_conf *fc_conf); 88 static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, 89 struct rte_eth_fc_conf *fc_conf); 90 static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 91 struct rte_eth_pfc_conf *pfc_conf); 92 static void axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 93 struct rte_eth_rxq_info *qinfo); 94 static void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 95 struct rte_eth_txq_info *qinfo); 96 const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev, 97 size_t *no_of_elements); 98 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 99 100 static int 101 axgbe_timesync_enable(struct rte_eth_dev *dev); 102 static int 103 axgbe_timesync_disable(struct rte_eth_dev *dev); 104 static int 105 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 106 struct timespec *timestamp, uint32_t flags); 107 static int 108 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 109 struct timespec *timestamp); 110 static int 111 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 112 static int 113 axgbe_timesync_read_time(struct rte_eth_dev *dev, 114 struct timespec *timestamp); 115 static int 116 axgbe_timesync_write_time(struct rte_eth_dev *dev, 117 const struct timespec *timestamp); 118 static void 119 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 120 unsigned int nsec); 121 static void 122 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 123 unsigned int addend); 124 static int 125 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on); 126 static int axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 127 enum rte_vlan_type vlan_type, uint16_t tpid); 128 static int axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask); 129 130 struct axgbe_xstats { 131 char name[RTE_ETH_XSTATS_NAME_SIZE]; 132 int offset; 133 }; 134 135 #define AXGMAC_MMC_STAT(_string, _var) \ 136 { _string, \ 137 offsetof(struct axgbe_mmc_stats, _var), \ 138 } 139 140 static const struct axgbe_xstats axgbe_xstats_strings[] = { 141 AXGMAC_MMC_STAT("tx_bytes", txoctetcount_gb), 142 AXGMAC_MMC_STAT("tx_packets", txframecount_gb), 143 AXGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb), 144 AXGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb), 145 AXGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb), 146 AXGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g), 147 AXGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb), 148 AXGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb), 149 AXGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb), 150 AXGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb), 151 AXGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb), 152 AXGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb), 153 AXGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror), 154 AXGMAC_MMC_STAT("tx_pause_frames", txpauseframes), 155 156 AXGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb), 157 AXGMAC_MMC_STAT("rx_packets", rxframecount_gb), 158 AXGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g), 159 AXGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g), 160 AXGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g), 161 AXGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb), 162 AXGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb), 163 AXGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb), 164 AXGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb), 165 AXGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb), 166 AXGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb), 167 AXGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb), 168 AXGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g), 169 AXGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g), 170 AXGMAC_MMC_STAT("rx_crc_errors", rxcrcerror), 171 AXGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror), 172 AXGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror), 173 AXGMAC_MMC_STAT("rx_length_errors", rxlengtherror), 174 AXGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype), 175 AXGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow), 176 AXGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror), 177 AXGMAC_MMC_STAT("rx_pause_frames", rxpauseframes), 178 }; 179 180 #define AXGBE_XSTATS_COUNT ARRAY_SIZE(axgbe_xstats_strings) 181 182 /* The set of PCI devices this driver supports */ 183 #define AMD_PCI_VENDOR_ID 0x1022 184 185 #define Fam17h 0x17 186 #define Fam19h 0x19 187 188 #define CPUID_VENDOR_AuthenticAMD_ebx 0x68747541 189 #define CPUID_VENDOR_AuthenticAMD_ecx 0x444d4163 190 #define CPUID_VENDOR_AuthenticAMD_edx 0x69746e65 191 192 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 193 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459 194 195 static const struct rte_pci_id pci_id_axgbe_map[] = { 196 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)}, 197 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)}, 198 { .vendor_id = 0, }, 199 }; 200 201 static struct axgbe_version_data axgbe_v2a = { 202 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 203 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 204 .mmc_64bit = 1, 205 .tx_max_fifo_size = 229376, 206 .rx_max_fifo_size = 229376, 207 .tx_tstamp_workaround = 1, 208 .ecc_support = 1, 209 .i2c_support = 1, 210 .an_cdr_workaround = 1, 211 }; 212 213 static struct axgbe_version_data axgbe_v2b = { 214 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 215 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 216 .mmc_64bit = 1, 217 .tx_max_fifo_size = 65536, 218 .rx_max_fifo_size = 65536, 219 .tx_tstamp_workaround = 1, 220 .ecc_support = 1, 221 .i2c_support = 1, 222 .an_cdr_workaround = 1, 223 }; 224 225 static const struct rte_eth_desc_lim rx_desc_lim = { 226 .nb_max = AXGBE_MAX_RING_DESC, 227 .nb_min = AXGBE_MIN_RING_DESC, 228 .nb_align = 8, 229 }; 230 231 static const struct rte_eth_desc_lim tx_desc_lim = { 232 .nb_max = AXGBE_MAX_RING_DESC, 233 .nb_min = AXGBE_MIN_RING_DESC, 234 .nb_align = 8, 235 }; 236 237 static const struct eth_dev_ops axgbe_eth_dev_ops = { 238 .dev_configure = axgbe_dev_configure, 239 .dev_start = axgbe_dev_start, 240 .dev_stop = axgbe_dev_stop, 241 .dev_close = axgbe_dev_close, 242 .dev_reset = axgbe_dev_reset, 243 .promiscuous_enable = axgbe_dev_promiscuous_enable, 244 .promiscuous_disable = axgbe_dev_promiscuous_disable, 245 .allmulticast_enable = axgbe_dev_allmulticast_enable, 246 .allmulticast_disable = axgbe_dev_allmulticast_disable, 247 .mac_addr_set = axgbe_dev_mac_addr_set, 248 .mac_addr_add = axgbe_dev_mac_addr_add, 249 .mac_addr_remove = axgbe_dev_mac_addr_remove, 250 .set_mc_addr_list = axgbe_dev_set_mc_addr_list, 251 .uc_hash_table_set = axgbe_dev_uc_hash_table_set, 252 .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set, 253 .link_update = axgbe_dev_link_update, 254 .get_reg = axgbe_dev_get_regs, 255 .stats_get = axgbe_dev_stats_get, 256 .stats_reset = axgbe_dev_stats_reset, 257 .xstats_get = axgbe_dev_xstats_get, 258 .xstats_reset = axgbe_dev_xstats_reset, 259 .xstats_get_names = axgbe_dev_xstats_get_names, 260 .xstats_get_names_by_id = axgbe_dev_xstats_get_names_by_id, 261 .xstats_get_by_id = axgbe_dev_xstats_get_by_id, 262 .reta_update = axgbe_dev_rss_reta_update, 263 .reta_query = axgbe_dev_rss_reta_query, 264 .rss_hash_update = axgbe_dev_rss_hash_update, 265 .rss_hash_conf_get = axgbe_dev_rss_hash_conf_get, 266 .dev_infos_get = axgbe_dev_info_get, 267 .rx_queue_setup = axgbe_dev_rx_queue_setup, 268 .rx_queue_release = axgbe_dev_rx_queue_release, 269 .tx_queue_setup = axgbe_dev_tx_queue_setup, 270 .tx_queue_release = axgbe_dev_tx_queue_release, 271 .flow_ctrl_get = axgbe_flow_ctrl_get, 272 .flow_ctrl_set = axgbe_flow_ctrl_set, 273 .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set, 274 .rxq_info_get = axgbe_rxq_info_get, 275 .txq_info_get = axgbe_txq_info_get, 276 .dev_supported_ptypes_get = axgbe_dev_supported_ptypes_get, 277 .mtu_set = axgb_mtu_set, 278 .vlan_filter_set = axgbe_vlan_filter_set, 279 .vlan_tpid_set = axgbe_vlan_tpid_set, 280 .vlan_offload_set = axgbe_vlan_offload_set, 281 .timesync_enable = axgbe_timesync_enable, 282 .timesync_disable = axgbe_timesync_disable, 283 .timesync_read_rx_timestamp = axgbe_timesync_read_rx_timestamp, 284 .timesync_read_tx_timestamp = axgbe_timesync_read_tx_timestamp, 285 .timesync_adjust_time = axgbe_timesync_adjust_time, 286 .timesync_read_time = axgbe_timesync_read_time, 287 .timesync_write_time = axgbe_timesync_write_time, 288 .fw_version_get = axgbe_dev_fw_version_get, 289 }; 290 291 static int axgbe_phy_reset(struct axgbe_port *pdata) 292 { 293 pdata->phy_link = -1; 294 pdata->phy_speed = SPEED_UNKNOWN; 295 return pdata->phy_if.phy_reset(pdata); 296 } 297 298 /* 299 * Interrupt handler triggered by NIC for handling 300 * specific interrupt. 301 * 302 * @param handle 303 * Pointer to interrupt handle. 304 * @param param 305 * The address of parameter (struct rte_eth_dev *) registered before. 306 * 307 * @return 308 * void 309 */ 310 static void 311 axgbe_dev_interrupt_handler(void *param) 312 { 313 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 314 struct axgbe_port *pdata = dev->data->dev_private; 315 unsigned int dma_isr, dma_ch_isr; 316 317 pdata->phy_if.an_isr(pdata); 318 /*DMA related interrupts*/ 319 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR); 320 PMD_DRV_LOG(DEBUG, "DMA_ISR=%#010x\n", dma_isr); 321 if (dma_isr) { 322 if (dma_isr & 1) { 323 dma_ch_isr = 324 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *) 325 pdata->rx_queues[0], 326 DMA_CH_SR); 327 PMD_DRV_LOG(DEBUG, "DMA_CH0_ISR=%#010x\n", dma_ch_isr); 328 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *) 329 pdata->rx_queues[0], 330 DMA_CH_SR, dma_ch_isr); 331 } 332 } 333 /* Unmask interrupts since disabled after generation */ 334 rte_intr_ack(pdata->pci_dev->intr_handle); 335 } 336 337 /* 338 * Configure device link speed and setup link. 339 * It returns 0 on success. 340 */ 341 static int 342 axgbe_dev_configure(struct rte_eth_dev *dev) 343 { 344 struct axgbe_port *pdata = dev->data->dev_private; 345 /* Checksum offload to hardware */ 346 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads & 347 RTE_ETH_RX_OFFLOAD_CHECKSUM; 348 return 0; 349 } 350 351 static int 352 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev) 353 { 354 struct axgbe_port *pdata = dev->data->dev_private; 355 356 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) 357 pdata->rss_enable = 1; 358 else if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_NONE) 359 pdata->rss_enable = 0; 360 else 361 return -1; 362 return 0; 363 } 364 365 static int 366 axgbe_dev_start(struct rte_eth_dev *dev) 367 { 368 struct axgbe_port *pdata = dev->data->dev_private; 369 uint16_t i; 370 int ret; 371 372 dev->dev_ops = &axgbe_eth_dev_ops; 373 374 PMD_INIT_FUNC_TRACE(); 375 376 /* Multiqueue RSS */ 377 ret = axgbe_dev_rx_mq_config(dev); 378 if (ret) { 379 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n"); 380 return ret; 381 } 382 ret = axgbe_phy_reset(pdata); 383 if (ret) { 384 PMD_DRV_LOG(ERR, "phy reset failed\n"); 385 return ret; 386 } 387 ret = pdata->hw_if.init(pdata); 388 if (ret) { 389 PMD_DRV_LOG(ERR, "dev_init failed\n"); 390 return ret; 391 } 392 393 /* enable uio/vfio intr/eventfd mapping */ 394 rte_intr_enable(pdata->pci_dev->intr_handle); 395 396 /* phy start*/ 397 pdata->phy_if.phy_start(pdata); 398 axgbe_dev_enable_tx(dev); 399 axgbe_dev_enable_rx(dev); 400 401 rte_bit_relaxed_clear32(AXGBE_STOPPED, &pdata->dev_state); 402 rte_bit_relaxed_clear32(AXGBE_DOWN, &pdata->dev_state); 403 404 axgbe_set_rx_function(dev); 405 axgbe_set_tx_function(dev); 406 407 for (i = 0; i < dev->data->nb_rx_queues; i++) 408 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 409 for (i = 0; i < dev->data->nb_tx_queues; i++) 410 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 411 412 return 0; 413 } 414 415 /* Stop device: disable rx and tx functions to allow for reconfiguring. */ 416 static int 417 axgbe_dev_stop(struct rte_eth_dev *dev) 418 { 419 struct axgbe_port *pdata = dev->data->dev_private; 420 421 PMD_INIT_FUNC_TRACE(); 422 423 rte_intr_disable(pdata->pci_dev->intr_handle); 424 425 if (rte_bit_relaxed_get32(AXGBE_STOPPED, &pdata->dev_state)) 426 return 0; 427 428 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 429 axgbe_dev_disable_tx(dev); 430 axgbe_dev_disable_rx(dev); 431 432 pdata->phy_if.phy_stop(pdata); 433 pdata->hw_if.exit(pdata); 434 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); 435 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 436 437 return 0; 438 } 439 440 static int 441 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 442 { 443 struct axgbe_port *pdata = dev->data->dev_private; 444 445 PMD_INIT_FUNC_TRACE(); 446 447 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); 448 449 return 0; 450 } 451 452 static int 453 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 454 { 455 struct axgbe_port *pdata = dev->data->dev_private; 456 457 PMD_INIT_FUNC_TRACE(); 458 459 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); 460 461 return 0; 462 } 463 464 static int 465 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 466 { 467 struct axgbe_port *pdata = dev->data->dev_private; 468 469 PMD_INIT_FUNC_TRACE(); 470 471 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 472 return 0; 473 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1); 474 475 return 0; 476 } 477 478 static int 479 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 480 { 481 struct axgbe_port *pdata = dev->data->dev_private; 482 483 PMD_INIT_FUNC_TRACE(); 484 485 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 486 return 0; 487 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0); 488 489 return 0; 490 } 491 492 static int 493 axgbe_dev_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr) 494 { 495 struct axgbe_port *pdata = dev->data->dev_private; 496 497 /* Set Default MAC Addr */ 498 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, 0); 499 500 return 0; 501 } 502 503 static int 504 axgbe_dev_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 505 uint32_t index, uint32_t pool __rte_unused) 506 { 507 struct axgbe_port *pdata = dev->data->dev_private; 508 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 509 510 if (index > hw_feat->addn_mac) { 511 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index); 512 return -EINVAL; 513 } 514 axgbe_set_mac_addn_addr(pdata, (u8 *)mac_addr, index); 515 return 0; 516 } 517 518 static int 519 axgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 520 struct rte_eth_rss_reta_entry64 *reta_conf, 521 uint16_t reta_size) 522 { 523 struct axgbe_port *pdata = dev->data->dev_private; 524 unsigned int i, idx, shift; 525 int ret; 526 527 if (!pdata->rss_enable) { 528 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 529 return -ENOTSUP; 530 } 531 532 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 533 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size); 534 return -EINVAL; 535 } 536 537 for (i = 0; i < reta_size; i++) { 538 idx = i / RTE_ETH_RETA_GROUP_SIZE; 539 shift = i % RTE_ETH_RETA_GROUP_SIZE; 540 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 541 continue; 542 pdata->rss_table[i] = reta_conf[idx].reta[shift]; 543 } 544 545 /* Program the lookup table */ 546 ret = axgbe_write_rss_lookup_table(pdata); 547 return ret; 548 } 549 550 static int 551 axgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 552 struct rte_eth_rss_reta_entry64 *reta_conf, 553 uint16_t reta_size) 554 { 555 struct axgbe_port *pdata = dev->data->dev_private; 556 unsigned int i, idx, shift; 557 558 if (!pdata->rss_enable) { 559 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 560 return -ENOTSUP; 561 } 562 563 if (reta_size == 0 || reta_size > AXGBE_RSS_MAX_TABLE_SIZE) { 564 PMD_DRV_LOG(ERR, "reta_size %d is not supported\n", reta_size); 565 return -EINVAL; 566 } 567 568 for (i = 0; i < reta_size; i++) { 569 idx = i / RTE_ETH_RETA_GROUP_SIZE; 570 shift = i % RTE_ETH_RETA_GROUP_SIZE; 571 if ((reta_conf[idx].mask & (1ULL << shift)) == 0) 572 continue; 573 reta_conf[idx].reta[shift] = pdata->rss_table[i]; 574 } 575 return 0; 576 } 577 578 static int 579 axgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 580 struct rte_eth_rss_conf *rss_conf) 581 { 582 struct axgbe_port *pdata = dev->data->dev_private; 583 int ret; 584 585 if (!pdata->rss_enable) { 586 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 587 return -ENOTSUP; 588 } 589 590 if (rss_conf == NULL) { 591 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n"); 592 return -EINVAL; 593 } 594 595 if (rss_conf->rss_key != NULL && 596 rss_conf->rss_key_len == AXGBE_RSS_HASH_KEY_SIZE) { 597 rte_memcpy(pdata->rss_key, rss_conf->rss_key, 598 AXGBE_RSS_HASH_KEY_SIZE); 599 /* Program the hash key */ 600 ret = axgbe_write_rss_hash_key(pdata); 601 if (ret != 0) 602 return ret; 603 } 604 605 pdata->rss_hf = rss_conf->rss_hf & AXGBE_RSS_OFFLOAD; 606 607 if (pdata->rss_hf & (RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_IPV6)) 608 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1); 609 if (pdata->rss_hf & 610 (RTE_ETH_RSS_NONFRAG_IPV4_TCP | RTE_ETH_RSS_NONFRAG_IPV6_TCP)) 611 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1); 612 if (pdata->rss_hf & 613 (RTE_ETH_RSS_NONFRAG_IPV4_UDP | RTE_ETH_RSS_NONFRAG_IPV6_UDP)) 614 AXGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); 615 616 /* Set the RSS options */ 617 AXGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); 618 619 return 0; 620 } 621 622 static int 623 axgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 624 struct rte_eth_rss_conf *rss_conf) 625 { 626 struct axgbe_port *pdata = dev->data->dev_private; 627 628 if (!pdata->rss_enable) { 629 PMD_DRV_LOG(ERR, "RSS not enabled\n"); 630 return -ENOTSUP; 631 } 632 633 if (rss_conf == NULL) { 634 PMD_DRV_LOG(ERR, "rss_conf value isn't valid\n"); 635 return -EINVAL; 636 } 637 638 if (rss_conf->rss_key != NULL && 639 rss_conf->rss_key_len >= AXGBE_RSS_HASH_KEY_SIZE) { 640 rte_memcpy(rss_conf->rss_key, pdata->rss_key, 641 AXGBE_RSS_HASH_KEY_SIZE); 642 } 643 rss_conf->rss_key_len = AXGBE_RSS_HASH_KEY_SIZE; 644 rss_conf->rss_hf = pdata->rss_hf; 645 return 0; 646 } 647 648 static int 649 axgbe_dev_reset(struct rte_eth_dev *dev) 650 { 651 int ret = 0; 652 653 ret = axgbe_dev_close(dev); 654 if (ret) 655 return ret; 656 657 ret = eth_axgbe_dev_init(dev); 658 659 return ret; 660 } 661 662 static void 663 axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) 664 { 665 struct axgbe_port *pdata = dev->data->dev_private; 666 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 667 668 if (index > hw_feat->addn_mac) { 669 PMD_DRV_LOG(ERR, "Invalid Index %d\n", index); 670 return; 671 } 672 axgbe_set_mac_addn_addr(pdata, NULL, index); 673 } 674 675 static int 676 axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, 677 struct rte_ether_addr *mc_addr_set, 678 uint32_t nb_mc_addr) 679 { 680 struct axgbe_port *pdata = dev->data->dev_private; 681 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 682 uint32_t index = 1; /* 0 is always default mac */ 683 uint32_t i; 684 685 if (nb_mc_addr > hw_feat->addn_mac) { 686 PMD_DRV_LOG(ERR, "Invalid Index %d\n", nb_mc_addr); 687 return -EINVAL; 688 } 689 690 /* clear unicast addresses */ 691 for (i = 1; i < hw_feat->addn_mac; i++) { 692 if (rte_is_zero_ether_addr(&dev->data->mac_addrs[i])) 693 continue; 694 memset(&dev->data->mac_addrs[i], 0, 695 sizeof(struct rte_ether_addr)); 696 } 697 698 while (nb_mc_addr--) 699 axgbe_set_mac_addn_addr(pdata, (u8 *)mc_addr_set++, index++); 700 701 return 0; 702 } 703 704 static int 705 axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, 706 struct rte_ether_addr *mac_addr, uint8_t add) 707 { 708 struct axgbe_port *pdata = dev->data->dev_private; 709 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 710 711 if (!hw_feat->hash_table_size) { 712 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); 713 return -ENOTSUP; 714 } 715 716 axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add); 717 718 if (pdata->uc_hash_mac_addr > 0) { 719 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 720 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 721 } else { 722 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 723 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 724 } 725 return 0; 726 } 727 728 static int 729 axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add) 730 { 731 struct axgbe_port *pdata = dev->data->dev_private; 732 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 733 uint32_t index; 734 735 if (!hw_feat->hash_table_size) { 736 PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); 737 return -ENOTSUP; 738 } 739 740 for (index = 0; index < pdata->hash_table_count; index++) { 741 if (add) 742 pdata->uc_hash_table[index] = ~0; 743 else 744 pdata->uc_hash_table[index] = 0; 745 746 PMD_DRV_LOG(DEBUG, "%s MAC hash table at Index %#x\n", 747 add ? "set" : "clear", index); 748 749 AXGMAC_IOWRITE(pdata, MAC_HTR(index), 750 pdata->uc_hash_table[index]); 751 } 752 753 if (add) { 754 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); 755 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); 756 } else { 757 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); 758 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); 759 } 760 return 0; 761 } 762 763 /* return 0 means link status changed, -1 means not changed */ 764 static int 765 axgbe_dev_link_update(struct rte_eth_dev *dev, 766 int wait_to_complete __rte_unused) 767 { 768 struct axgbe_port *pdata = dev->data->dev_private; 769 struct rte_eth_link link; 770 int ret = 0; 771 772 PMD_INIT_FUNC_TRACE(); 773 rte_delay_ms(800); 774 775 pdata->phy_if.phy_status(pdata); 776 777 memset(&link, 0, sizeof(struct rte_eth_link)); 778 link.link_duplex = pdata->phy.duplex; 779 link.link_status = pdata->phy_link; 780 link.link_speed = pdata->phy_speed; 781 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 782 RTE_ETH_LINK_SPEED_FIXED); 783 ret = rte_eth_linkstatus_set(dev, &link); 784 if (ret == -1) 785 PMD_DRV_LOG(ERR, "No change in link status\n"); 786 787 return ret; 788 } 789 790 static int 791 axgbe_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs) 792 { 793 struct axgbe_port *pdata = dev->data->dev_private; 794 795 if (regs->data == NULL) { 796 regs->length = axgbe_regs_get_count(pdata); 797 regs->width = sizeof(uint32_t); 798 return 0; 799 } 800 801 /* Only full register dump is supported */ 802 if (regs->length && 803 regs->length != (uint32_t)axgbe_regs_get_count(pdata)) 804 return -ENOTSUP; 805 806 regs->version = pdata->pci_dev->id.vendor_id << 16 | 807 pdata->pci_dev->id.device_id; 808 axgbe_regs_dump(pdata, regs->data); 809 return 0; 810 } 811 static void axgbe_read_mmc_stats(struct axgbe_port *pdata) 812 { 813 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 814 815 /* Freeze counters */ 816 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); 817 818 /* Tx counters */ 819 stats->txoctetcount_gb += 820 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_LO); 821 stats->txoctetcount_gb += 822 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_GB_HI) << 32); 823 824 stats->txframecount_gb += 825 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_LO); 826 stats->txframecount_gb += 827 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_GB_HI) << 32); 828 829 stats->txbroadcastframes_g += 830 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_LO); 831 stats->txbroadcastframes_g += 832 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_G_HI) << 32); 833 834 stats->txmulticastframes_g += 835 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_LO); 836 stats->txmulticastframes_g += 837 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_G_HI) << 32); 838 839 stats->tx64octets_gb += 840 AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_LO); 841 stats->tx64octets_gb += 842 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX64OCTETS_GB_HI) << 32); 843 844 stats->tx65to127octets_gb += 845 AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_LO); 846 stats->tx65to127octets_gb += 847 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX65TO127OCTETS_GB_HI) << 32); 848 849 stats->tx128to255octets_gb += 850 AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_LO); 851 stats->tx128to255octets_gb += 852 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX128TO255OCTETS_GB_HI) << 32); 853 854 stats->tx256to511octets_gb += 855 AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_LO); 856 stats->tx256to511octets_gb += 857 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX256TO511OCTETS_GB_HI) << 32); 858 859 stats->tx512to1023octets_gb += 860 AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_LO); 861 stats->tx512to1023octets_gb += 862 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX512TO1023OCTETS_GB_HI) << 32); 863 864 stats->tx1024tomaxoctets_gb += 865 AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); 866 stats->tx1024tomaxoctets_gb += 867 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TX1024TOMAXOCTETS_GB_HI) << 32); 868 869 stats->txunicastframes_gb += 870 AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_LO); 871 stats->txunicastframes_gb += 872 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNICASTFRAMES_GB_HI) << 32); 873 874 stats->txmulticastframes_gb += 875 AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_LO); 876 stats->txmulticastframes_gb += 877 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXMULTICASTFRAMES_GB_HI) << 32); 878 879 stats->txbroadcastframes_g += 880 AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_LO); 881 stats->txbroadcastframes_g += 882 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXBROADCASTFRAMES_GB_HI) << 32); 883 884 stats->txunderflowerror += 885 AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_LO); 886 stats->txunderflowerror += 887 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXUNDERFLOWERROR_HI) << 32); 888 889 stats->txoctetcount_g += 890 AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_LO); 891 stats->txoctetcount_g += 892 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXOCTETCOUNT_G_HI) << 32); 893 894 stats->txframecount_g += 895 AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_LO); 896 stats->txframecount_g += 897 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXFRAMECOUNT_G_HI) << 32); 898 899 stats->txpauseframes += 900 AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_LO); 901 stats->txpauseframes += 902 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXPAUSEFRAMES_HI) << 32); 903 904 stats->txvlanframes_g += 905 AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_LO); 906 stats->txvlanframes_g += 907 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_TXVLANFRAMES_G_HI) << 32); 908 909 /* Rx counters */ 910 stats->rxframecount_gb += 911 AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_LO); 912 stats->rxframecount_gb += 913 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFRAMECOUNT_GB_HI) << 32); 914 915 stats->rxoctetcount_gb += 916 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_LO); 917 stats->rxoctetcount_gb += 918 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_GB_HI) << 32); 919 920 stats->rxoctetcount_g += 921 AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_LO); 922 stats->rxoctetcount_g += 923 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOCTETCOUNT_G_HI) << 32); 924 925 stats->rxbroadcastframes_g += 926 AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_LO); 927 stats->rxbroadcastframes_g += 928 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXBROADCASTFRAMES_G_HI) << 32); 929 930 stats->rxmulticastframes_g += 931 AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_LO); 932 stats->rxmulticastframes_g += 933 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXMULTICASTFRAMES_G_HI) << 32); 934 935 stats->rxcrcerror += 936 AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_LO); 937 stats->rxcrcerror += 938 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXCRCERROR_HI) << 32); 939 940 stats->rxrunterror += 941 AXGMAC_IOREAD(pdata, MMC_RXRUNTERROR); 942 943 stats->rxjabbererror += 944 AXGMAC_IOREAD(pdata, MMC_RXJABBERERROR); 945 946 stats->rxundersize_g += 947 AXGMAC_IOREAD(pdata, MMC_RXUNDERSIZE_G); 948 949 stats->rxoversize_g += 950 AXGMAC_IOREAD(pdata, MMC_RXOVERSIZE_G); 951 952 stats->rx64octets_gb += 953 AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_LO); 954 stats->rx64octets_gb += 955 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX64OCTETS_GB_HI) << 32); 956 957 stats->rx65to127octets_gb += 958 AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_LO); 959 stats->rx65to127octets_gb += 960 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX65TO127OCTETS_GB_HI) << 32); 961 962 stats->rx128to255octets_gb += 963 AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_LO); 964 stats->rx128to255octets_gb += 965 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX128TO255OCTETS_GB_HI) << 32); 966 967 stats->rx256to511octets_gb += 968 AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_LO); 969 stats->rx256to511octets_gb += 970 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX256TO511OCTETS_GB_HI) << 32); 971 972 stats->rx512to1023octets_gb += 973 AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_LO); 974 stats->rx512to1023octets_gb += 975 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX512TO1023OCTETS_GB_HI) << 32); 976 977 stats->rx1024tomaxoctets_gb += 978 AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); 979 stats->rx1024tomaxoctets_gb += 980 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RX1024TOMAXOCTETS_GB_HI) << 32); 981 982 stats->rxunicastframes_g += 983 AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_LO); 984 stats->rxunicastframes_g += 985 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXUNICASTFRAMES_G_HI) << 32); 986 987 stats->rxlengtherror += 988 AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_LO); 989 stats->rxlengtherror += 990 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXLENGTHERROR_HI) << 32); 991 992 stats->rxoutofrangetype += 993 AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_LO); 994 stats->rxoutofrangetype += 995 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXOUTOFRANGETYPE_HI) << 32); 996 997 stats->rxpauseframes += 998 AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_LO); 999 stats->rxpauseframes += 1000 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXPAUSEFRAMES_HI) << 32); 1001 1002 stats->rxfifooverflow += 1003 AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_LO); 1004 stats->rxfifooverflow += 1005 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXFIFOOVERFLOW_HI) << 32); 1006 1007 stats->rxvlanframes_gb += 1008 AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_LO); 1009 stats->rxvlanframes_gb += 1010 ((uint64_t)AXGMAC_IOREAD(pdata, MMC_RXVLANFRAMES_GB_HI) << 32); 1011 1012 stats->rxwatchdogerror += 1013 AXGMAC_IOREAD(pdata, MMC_RXWATCHDOGERROR); 1014 1015 /* Un-freeze counters */ 1016 AXGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); 1017 } 1018 1019 static int 1020 axgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1021 unsigned int n) 1022 { 1023 struct axgbe_port *pdata = dev->data->dev_private; 1024 unsigned int i; 1025 1026 if (n < AXGBE_XSTATS_COUNT) 1027 return AXGBE_XSTATS_COUNT; 1028 1029 axgbe_read_mmc_stats(pdata); 1030 1031 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1032 stats[i].id = i; 1033 stats[i].value = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1034 axgbe_xstats_strings[i].offset); 1035 } 1036 1037 return AXGBE_XSTATS_COUNT; 1038 } 1039 1040 static int 1041 axgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1042 struct rte_eth_xstat_name *xstats_names, 1043 unsigned int n) 1044 { 1045 unsigned int i; 1046 1047 if (n >= AXGBE_XSTATS_COUNT && xstats_names) { 1048 for (i = 0; i < AXGBE_XSTATS_COUNT; ++i) { 1049 snprintf(xstats_names[i].name, 1050 RTE_ETH_XSTATS_NAME_SIZE, "%s", 1051 axgbe_xstats_strings[i].name); 1052 } 1053 } 1054 1055 return AXGBE_XSTATS_COUNT; 1056 } 1057 1058 static int 1059 axgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1060 uint64_t *values, unsigned int n) 1061 { 1062 unsigned int i; 1063 uint64_t values_copy[AXGBE_XSTATS_COUNT]; 1064 1065 if (!ids) { 1066 struct axgbe_port *pdata = dev->data->dev_private; 1067 1068 if (n < AXGBE_XSTATS_COUNT) 1069 return AXGBE_XSTATS_COUNT; 1070 1071 axgbe_read_mmc_stats(pdata); 1072 1073 for (i = 0; i < AXGBE_XSTATS_COUNT; i++) { 1074 values[i] = *(u64 *)((uint8_t *)&pdata->mmc_stats + 1075 axgbe_xstats_strings[i].offset); 1076 } 1077 1078 return i; 1079 } 1080 1081 axgbe_dev_xstats_get_by_id(dev, NULL, values_copy, AXGBE_XSTATS_COUNT); 1082 1083 for (i = 0; i < n; i++) { 1084 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1085 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 1086 return -1; 1087 } 1088 values[i] = values_copy[ids[i]]; 1089 } 1090 return n; 1091 } 1092 1093 static int 1094 axgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 1095 const uint64_t *ids, 1096 struct rte_eth_xstat_name *xstats_names, 1097 unsigned int size) 1098 { 1099 struct rte_eth_xstat_name xstats_names_copy[AXGBE_XSTATS_COUNT]; 1100 unsigned int i; 1101 1102 if (!ids) 1103 return axgbe_dev_xstats_get_names(dev, xstats_names, size); 1104 1105 axgbe_dev_xstats_get_names(dev, xstats_names_copy, size); 1106 1107 for (i = 0; i < size; i++) { 1108 if (ids[i] >= AXGBE_XSTATS_COUNT) { 1109 PMD_DRV_LOG(ERR, "id value isn't valid\n"); 1110 return -1; 1111 } 1112 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1113 } 1114 return size; 1115 } 1116 1117 static int 1118 axgbe_dev_xstats_reset(struct rte_eth_dev *dev) 1119 { 1120 struct axgbe_port *pdata = dev->data->dev_private; 1121 struct axgbe_mmc_stats *stats = &pdata->mmc_stats; 1122 1123 /* MMC registers are configured for reset on read */ 1124 axgbe_read_mmc_stats(pdata); 1125 1126 /* Reset stats */ 1127 memset(stats, 0, sizeof(*stats)); 1128 1129 return 0; 1130 } 1131 1132 static int 1133 axgbe_dev_stats_get(struct rte_eth_dev *dev, 1134 struct rte_eth_stats *stats) 1135 { 1136 struct axgbe_rx_queue *rxq; 1137 struct axgbe_tx_queue *txq; 1138 struct axgbe_port *pdata = dev->data->dev_private; 1139 struct axgbe_mmc_stats *mmc_stats = &pdata->mmc_stats; 1140 unsigned int i; 1141 1142 axgbe_read_mmc_stats(pdata); 1143 1144 stats->imissed = mmc_stats->rxfifooverflow; 1145 1146 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1147 rxq = dev->data->rx_queues[i]; 1148 if (rxq) { 1149 stats->q_ipackets[i] = rxq->pkts; 1150 stats->ipackets += rxq->pkts; 1151 stats->q_ibytes[i] = rxq->bytes; 1152 stats->ibytes += rxq->bytes; 1153 stats->rx_nombuf += rxq->rx_mbuf_alloc_failed; 1154 stats->q_errors[i] = rxq->errors 1155 + rxq->rx_mbuf_alloc_failed; 1156 stats->ierrors += rxq->errors; 1157 } else { 1158 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n", 1159 dev->data->port_id); 1160 } 1161 } 1162 1163 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1164 txq = dev->data->tx_queues[i]; 1165 if (txq) { 1166 stats->q_opackets[i] = txq->pkts; 1167 stats->opackets += txq->pkts; 1168 stats->q_obytes[i] = txq->bytes; 1169 stats->obytes += txq->bytes; 1170 stats->oerrors += txq->errors; 1171 } else { 1172 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n", 1173 dev->data->port_id); 1174 } 1175 } 1176 1177 return 0; 1178 } 1179 1180 static int 1181 axgbe_dev_stats_reset(struct rte_eth_dev *dev) 1182 { 1183 struct axgbe_rx_queue *rxq; 1184 struct axgbe_tx_queue *txq; 1185 unsigned int i; 1186 1187 for (i = 0; i < dev->data->nb_rx_queues; i++) { 1188 rxq = dev->data->rx_queues[i]; 1189 if (rxq) { 1190 rxq->pkts = 0; 1191 rxq->bytes = 0; 1192 rxq->errors = 0; 1193 rxq->rx_mbuf_alloc_failed = 0; 1194 } else { 1195 PMD_DRV_LOG(DEBUG, "Rx queue not setup for port %d\n", 1196 dev->data->port_id); 1197 } 1198 } 1199 for (i = 0; i < dev->data->nb_tx_queues; i++) { 1200 txq = dev->data->tx_queues[i]; 1201 if (txq) { 1202 txq->pkts = 0; 1203 txq->bytes = 0; 1204 txq->errors = 0; 1205 } else { 1206 PMD_DRV_LOG(DEBUG, "Tx queue not setup for port %d\n", 1207 dev->data->port_id); 1208 } 1209 } 1210 1211 return 0; 1212 } 1213 1214 static int 1215 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 1216 { 1217 struct axgbe_port *pdata = dev->data->dev_private; 1218 1219 dev_info->max_rx_queues = pdata->rx_ring_count; 1220 dev_info->max_tx_queues = pdata->tx_ring_count; 1221 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE; 1222 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE; 1223 dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1; 1224 dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size; 1225 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10G; 1226 1227 dev_info->rx_offload_capa = 1228 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 1229 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 1230 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | 1231 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 1232 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 1233 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 1234 RTE_ETH_RX_OFFLOAD_SCATTER | 1235 RTE_ETH_RX_OFFLOAD_KEEP_CRC; 1236 1237 dev_info->tx_offload_capa = 1238 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 1239 RTE_ETH_TX_OFFLOAD_QINQ_INSERT | 1240 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 1241 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | 1242 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 1243 RTE_ETH_TX_OFFLOAD_TCP_CKSUM; 1244 1245 if (pdata->hw_feat.rss) { 1246 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD; 1247 dev_info->reta_size = pdata->hw_feat.hash_table_size; 1248 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE; 1249 } 1250 1251 dev_info->rx_desc_lim = rx_desc_lim; 1252 dev_info->tx_desc_lim = tx_desc_lim; 1253 1254 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1255 .rx_free_thresh = AXGBE_RX_FREE_THRESH, 1256 }; 1257 1258 dev_info->default_txconf = (struct rte_eth_txconf) { 1259 .tx_free_thresh = AXGBE_TX_FREE_THRESH, 1260 }; 1261 1262 return 0; 1263 } 1264 1265 static int 1266 axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1267 { 1268 struct axgbe_port *pdata = dev->data->dev_private; 1269 struct xgbe_fc_info fc = pdata->fc; 1270 unsigned int reg, reg_val = 0; 1271 1272 reg = MAC_Q0TFCR; 1273 reg_val = AXGMAC_IOREAD(pdata, reg); 1274 fc.low_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFA); 1275 fc.high_water[0] = AXGMAC_MTL_IOREAD_BITS(pdata, 0, MTL_Q_RQFCR, RFD); 1276 fc.pause_time[0] = AXGMAC_GET_BITS(reg_val, MAC_Q0TFCR, PT); 1277 fc.autoneg = pdata->pause_autoneg; 1278 1279 if (pdata->rx_pause && pdata->tx_pause) 1280 fc.mode = RTE_ETH_FC_FULL; 1281 else if (pdata->rx_pause) 1282 fc.mode = RTE_ETH_FC_RX_PAUSE; 1283 else if (pdata->tx_pause) 1284 fc.mode = RTE_ETH_FC_TX_PAUSE; 1285 else 1286 fc.mode = RTE_ETH_FC_NONE; 1287 1288 fc_conf->high_water = (1024 + (fc.low_water[0] << 9)) / 1024; 1289 fc_conf->low_water = (1024 + (fc.high_water[0] << 9)) / 1024; 1290 fc_conf->pause_time = fc.pause_time[0]; 1291 fc_conf->send_xon = fc.send_xon; 1292 fc_conf->mode = fc.mode; 1293 1294 return 0; 1295 } 1296 1297 static int 1298 axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1299 { 1300 struct axgbe_port *pdata = dev->data->dev_private; 1301 struct xgbe_fc_info fc = pdata->fc; 1302 unsigned int reg, reg_val = 0; 1303 reg = MAC_Q0TFCR; 1304 1305 pdata->pause_autoneg = fc_conf->autoneg; 1306 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1307 fc.send_xon = fc_conf->send_xon; 1308 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFA, 1309 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->high_water)); 1310 AXGMAC_MTL_IOWRITE_BITS(pdata, 0, MTL_Q_RQFCR, RFD, 1311 AXGMAC_FLOW_CONTROL_VALUE(1024 * fc_conf->low_water)); 1312 AXGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, fc_conf->pause_time); 1313 AXGMAC_IOWRITE(pdata, reg, reg_val); 1314 fc.mode = fc_conf->mode; 1315 1316 if (fc.mode == RTE_ETH_FC_FULL) { 1317 pdata->tx_pause = 1; 1318 pdata->rx_pause = 1; 1319 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) { 1320 pdata->tx_pause = 0; 1321 pdata->rx_pause = 1; 1322 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) { 1323 pdata->tx_pause = 1; 1324 pdata->rx_pause = 0; 1325 } else { 1326 pdata->tx_pause = 0; 1327 pdata->rx_pause = 0; 1328 } 1329 1330 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1331 pdata->hw_if.config_tx_flow_control(pdata); 1332 1333 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1334 pdata->hw_if.config_rx_flow_control(pdata); 1335 1336 pdata->hw_if.config_flow_control(pdata); 1337 pdata->phy.tx_pause = pdata->tx_pause; 1338 pdata->phy.rx_pause = pdata->rx_pause; 1339 1340 return 0; 1341 } 1342 1343 static int 1344 axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, 1345 struct rte_eth_pfc_conf *pfc_conf) 1346 { 1347 struct axgbe_port *pdata = dev->data->dev_private; 1348 struct xgbe_fc_info fc = pdata->fc; 1349 uint8_t tc_num; 1350 1351 tc_num = pdata->pfc_map[pfc_conf->priority]; 1352 1353 if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) { 1354 PMD_INIT_LOG(ERR, "Max supported traffic class: %d\n", 1355 pdata->hw_feat.tc_cnt); 1356 return -EINVAL; 1357 } 1358 1359 pdata->pause_autoneg = pfc_conf->fc.autoneg; 1360 pdata->phy.pause_autoneg = pdata->pause_autoneg; 1361 fc.send_xon = pfc_conf->fc.send_xon; 1362 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA, 1363 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water)); 1364 AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD, 1365 AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water)); 1366 1367 switch (tc_num) { 1368 case 0: 1369 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1370 PSTC0, pfc_conf->fc.pause_time); 1371 break; 1372 case 1: 1373 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1374 PSTC1, pfc_conf->fc.pause_time); 1375 break; 1376 case 2: 1377 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1378 PSTC2, pfc_conf->fc.pause_time); 1379 break; 1380 case 3: 1381 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, 1382 PSTC3, pfc_conf->fc.pause_time); 1383 break; 1384 case 4: 1385 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1386 PSTC4, pfc_conf->fc.pause_time); 1387 break; 1388 case 5: 1389 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1390 PSTC5, pfc_conf->fc.pause_time); 1391 break; 1392 case 7: 1393 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1394 PSTC6, pfc_conf->fc.pause_time); 1395 break; 1396 case 6: 1397 AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, 1398 PSTC7, pfc_conf->fc.pause_time); 1399 break; 1400 } 1401 1402 fc.mode = pfc_conf->fc.mode; 1403 1404 if (fc.mode == RTE_ETH_FC_FULL) { 1405 pdata->tx_pause = 1; 1406 pdata->rx_pause = 1; 1407 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1408 } else if (fc.mode == RTE_ETH_FC_RX_PAUSE) { 1409 pdata->tx_pause = 0; 1410 pdata->rx_pause = 1; 1411 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); 1412 } else if (fc.mode == RTE_ETH_FC_TX_PAUSE) { 1413 pdata->tx_pause = 1; 1414 pdata->rx_pause = 0; 1415 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1416 } else { 1417 pdata->tx_pause = 0; 1418 pdata->rx_pause = 0; 1419 AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); 1420 } 1421 1422 if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) 1423 pdata->hw_if.config_tx_flow_control(pdata); 1424 1425 if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) 1426 pdata->hw_if.config_rx_flow_control(pdata); 1427 pdata->hw_if.config_flow_control(pdata); 1428 pdata->phy.tx_pause = pdata->tx_pause; 1429 pdata->phy.rx_pause = pdata->rx_pause; 1430 1431 return 0; 1432 } 1433 1434 void 1435 axgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1436 struct rte_eth_rxq_info *qinfo) 1437 { 1438 struct axgbe_rx_queue *rxq; 1439 1440 rxq = dev->data->rx_queues[queue_id]; 1441 qinfo->mp = rxq->mb_pool; 1442 qinfo->scattered_rx = dev->data->scattered_rx; 1443 qinfo->nb_desc = rxq->nb_desc; 1444 qinfo->conf.rx_free_thresh = rxq->free_thresh; 1445 } 1446 1447 void 1448 axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1449 struct rte_eth_txq_info *qinfo) 1450 { 1451 struct axgbe_tx_queue *txq; 1452 1453 txq = dev->data->tx_queues[queue_id]; 1454 qinfo->nb_desc = txq->nb_desc; 1455 qinfo->conf.tx_free_thresh = txq->free_thresh; 1456 } 1457 const uint32_t * 1458 axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 1459 { 1460 static const uint32_t ptypes[] = { 1461 RTE_PTYPE_L2_ETHER, 1462 RTE_PTYPE_L2_ETHER_TIMESYNC, 1463 RTE_PTYPE_L2_ETHER_LLDP, 1464 RTE_PTYPE_L2_ETHER_ARP, 1465 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 1466 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 1467 RTE_PTYPE_L4_FRAG, 1468 RTE_PTYPE_L4_ICMP, 1469 RTE_PTYPE_L4_NONFRAG, 1470 RTE_PTYPE_L4_SCTP, 1471 RTE_PTYPE_L4_TCP, 1472 RTE_PTYPE_L4_UDP, 1473 RTE_PTYPE_TUNNEL_GRENAT, 1474 RTE_PTYPE_TUNNEL_IP, 1475 RTE_PTYPE_INNER_L2_ETHER, 1476 RTE_PTYPE_INNER_L2_ETHER_VLAN, 1477 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 1478 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 1479 RTE_PTYPE_INNER_L4_FRAG, 1480 RTE_PTYPE_INNER_L4_ICMP, 1481 RTE_PTYPE_INNER_L4_NONFRAG, 1482 RTE_PTYPE_INNER_L4_SCTP, 1483 RTE_PTYPE_INNER_L4_TCP, 1484 RTE_PTYPE_INNER_L4_UDP, 1485 }; 1486 1487 if (dev->rx_pkt_burst == axgbe_recv_pkts) { 1488 *no_of_elements = RTE_DIM(ptypes); 1489 return ptypes; 1490 } 1491 return NULL; 1492 } 1493 1494 static int axgb_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1495 { 1496 struct axgbe_port *pdata = dev->data->dev_private; 1497 unsigned int val; 1498 1499 /* mtu setting is forbidden if port is start */ 1500 if (dev->data->dev_started) { 1501 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration", 1502 dev->data->port_id); 1503 return -EBUSY; 1504 } 1505 val = mtu > RTE_ETHER_MTU ? 1 : 0; 1506 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); 1507 1508 return 0; 1509 } 1510 1511 static void 1512 axgbe_update_tstamp_time(struct axgbe_port *pdata, 1513 unsigned int sec, unsigned int nsec, int addsub) 1514 { 1515 unsigned int count = 100; 1516 uint32_t sub_val = 0; 1517 uint32_t sub_val_sec = 0xFFFFFFFF; 1518 uint32_t sub_val_nsec = 0x3B9ACA00; 1519 1520 if (addsub) { 1521 if (sec) 1522 sub_val = sub_val_sec - (sec - 1); 1523 else 1524 sub_val = sec; 1525 1526 AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val); 1527 sub_val = sub_val_nsec - nsec; 1528 AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val); 1529 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1); 1530 } else { 1531 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1532 AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0); 1533 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1534 } 1535 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1536 /* Wait for time update to complete */ 1537 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1538 rte_delay_ms(1); 1539 } 1540 1541 static inline uint64_t 1542 div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) 1543 { 1544 *remainder = dividend % divisor; 1545 return dividend / divisor; 1546 } 1547 1548 static inline uint64_t 1549 div_u64(uint64_t dividend, uint32_t divisor) 1550 { 1551 uint32_t remainder; 1552 return div_u64_rem(dividend, divisor, &remainder); 1553 } 1554 1555 static int 1556 axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta) 1557 { 1558 uint64_t adjust; 1559 uint32_t addend, diff; 1560 unsigned int neg_adjust = 0; 1561 1562 if (delta < 0) { 1563 neg_adjust = 1; 1564 delta = -delta; 1565 } 1566 adjust = (uint64_t)pdata->tstamp_addend; 1567 adjust *= delta; 1568 diff = (uint32_t)div_u64(adjust, 1000000000UL); 1569 addend = (neg_adjust) ? pdata->tstamp_addend - diff : 1570 pdata->tstamp_addend + diff; 1571 pdata->tstamp_addend = addend; 1572 axgbe_update_tstamp_addend(pdata, addend); 1573 return 0; 1574 } 1575 1576 static int 1577 axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 1578 { 1579 struct axgbe_port *pdata = dev->data->dev_private; 1580 struct timespec timestamp_delta; 1581 1582 axgbe_adjfreq(pdata, delta); 1583 pdata->systime_tc.nsec += delta; 1584 1585 if (delta < 0) { 1586 delta = -delta; 1587 timestamp_delta = rte_ns_to_timespec(delta); 1588 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1589 timestamp_delta.tv_nsec, 1); 1590 } else { 1591 timestamp_delta = rte_ns_to_timespec(delta); 1592 axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, 1593 timestamp_delta.tv_nsec, 0); 1594 } 1595 return 0; 1596 } 1597 1598 static int 1599 axgbe_timesync_read_time(struct rte_eth_dev *dev, 1600 struct timespec *timestamp) 1601 { 1602 uint64_t nsec; 1603 struct axgbe_port *pdata = dev->data->dev_private; 1604 1605 nsec = AXGMAC_IOREAD(pdata, MAC_STSR); 1606 nsec *= NSEC_PER_SEC; 1607 nsec += AXGMAC_IOREAD(pdata, MAC_STNR); 1608 *timestamp = rte_ns_to_timespec(nsec); 1609 return 0; 1610 } 1611 static int 1612 axgbe_timesync_write_time(struct rte_eth_dev *dev, 1613 const struct timespec *timestamp) 1614 { 1615 unsigned int count = 100; 1616 struct axgbe_port *pdata = dev->data->dev_private; 1617 1618 AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec); 1619 AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec); 1620 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); 1621 /* Wait for time update to complete */ 1622 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) 1623 rte_delay_ms(1); 1624 if (!count) 1625 PMD_DRV_LOG(ERR, "Timed out update timestamp\n"); 1626 return 0; 1627 } 1628 1629 static void 1630 axgbe_update_tstamp_addend(struct axgbe_port *pdata, 1631 uint32_t addend) 1632 { 1633 unsigned int count = 100; 1634 1635 AXGMAC_IOWRITE(pdata, MAC_TSAR, addend); 1636 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); 1637 1638 /* Wait for addend update to complete */ 1639 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) 1640 rte_delay_ms(1); 1641 if (!count) 1642 PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n"); 1643 } 1644 1645 static void 1646 axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, 1647 unsigned int nsec) 1648 { 1649 unsigned int count = 100; 1650 1651 /*System Time Sec Update*/ 1652 AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); 1653 /*System Time nanoSec Update*/ 1654 AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); 1655 /*Initialize Timestamp*/ 1656 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); 1657 1658 /* Wait for time update to complete */ 1659 while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) 1660 rte_delay_ms(1); 1661 if (!count) 1662 PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n"); 1663 } 1664 1665 static int 1666 axgbe_timesync_enable(struct rte_eth_dev *dev) 1667 { 1668 struct axgbe_port *pdata = dev->data->dev_private; 1669 unsigned int mac_tscr = 0; 1670 uint64_t dividend; 1671 struct timespec timestamp; 1672 uint64_t nsec; 1673 1674 /* Set one nano-second accuracy */ 1675 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); 1676 1677 /* Set fine timestamp update */ 1678 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); 1679 1680 /* Overwrite earlier timestamps */ 1681 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); 1682 1683 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1684 1685 /* Enabling processing of ptp over eth pkt */ 1686 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1687 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1688 /* Enable timestamp for all pkts*/ 1689 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 1690 1691 /* enabling timestamp */ 1692 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1693 AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); 1694 1695 /* Exit if timestamping is not enabled */ 1696 if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) { 1697 PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n"); 1698 return 0; 1699 } 1700 1701 /* Sub-second Increment Value*/ 1702 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC); 1703 /* Sub-nanosecond Increment Value */ 1704 AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC); 1705 1706 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 1707 dividend = 50000000; 1708 dividend <<= 32; 1709 pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate); 1710 1711 axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); 1712 axgbe_set_tstamp_time(pdata, 0, 0); 1713 1714 /* Initialize the timecounter */ 1715 memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter)); 1716 1717 pdata->systime_tc.cc_mask = AXGBE_CYCLECOUNTER_MASK; 1718 pdata->systime_tc.cc_shift = 0; 1719 pdata->systime_tc.nsec_mask = 0; 1720 1721 PMD_DRV_LOG(DEBUG, "Initializing system time counter with realtime\n"); 1722 1723 /* Updating the counter once with clock real time */ 1724 clock_gettime(CLOCK_REALTIME, ×tamp); 1725 nsec = rte_timespec_to_ns(×tamp); 1726 nsec = rte_timecounter_update(&pdata->systime_tc, nsec); 1727 axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec); 1728 return 0; 1729 } 1730 1731 static int 1732 axgbe_timesync_disable(struct rte_eth_dev *dev) 1733 { 1734 struct axgbe_port *pdata = dev->data->dev_private; 1735 unsigned int mac_tscr = 0; 1736 1737 /*disable timestamp for all pkts*/ 1738 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0); 1739 /*disable the addened register*/ 1740 AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0); 1741 /* disable timestamp update */ 1742 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0); 1743 /*disable time stamp*/ 1744 AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0); 1745 return 0; 1746 } 1747 1748 static int 1749 axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 1750 struct timespec *timestamp, uint32_t flags) 1751 { 1752 uint64_t nsec = 0; 1753 volatile union axgbe_rx_desc *desc; 1754 uint16_t idx, pmt; 1755 struct axgbe_rx_queue *rxq = *dev->data->rx_queues; 1756 1757 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 1758 desc = &rxq->desc[idx]; 1759 1760 while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 1761 rte_delay_ms(1); 1762 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) { 1763 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) && 1764 !AXGMAC_GET_BITS_LE(desc->write.desc3, 1765 RX_CONTEXT_DESC3, TSD)) { 1766 pmt = AXGMAC_GET_BITS_LE(desc->write.desc3, 1767 RX_CONTEXT_DESC3, PMT); 1768 nsec = rte_le_to_cpu_32(desc->write.desc1); 1769 nsec *= NSEC_PER_SEC; 1770 nsec += rte_le_to_cpu_32(desc->write.desc0); 1771 if (nsec != 0xffffffffffffffffULL) { 1772 if (pmt == 0x01) 1773 *timestamp = rte_ns_to_timespec(nsec); 1774 PMD_DRV_LOG(DEBUG, 1775 "flags = 0x%x nsec = %"PRIu64"\n", 1776 flags, nsec); 1777 } 1778 } 1779 } 1780 1781 return 0; 1782 } 1783 1784 static int 1785 axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 1786 struct timespec *timestamp) 1787 { 1788 uint64_t nsec; 1789 struct axgbe_port *pdata = dev->data->dev_private; 1790 unsigned int tx_snr, tx_ssr; 1791 1792 rte_delay_us(5); 1793 if (pdata->vdata->tx_tstamp_workaround) { 1794 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1795 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1796 1797 } else { 1798 tx_ssr = AXGMAC_IOREAD(pdata, MAC_TXSSR); 1799 tx_snr = AXGMAC_IOREAD(pdata, MAC_TXSNR); 1800 } 1801 if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) { 1802 PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n"); 1803 return 0; 1804 } 1805 nsec = tx_ssr; 1806 nsec *= NSEC_PER_SEC; 1807 nsec += tx_snr; 1808 PMD_DRV_LOG(DEBUG, "nsec = %"PRIu64" tx_ssr = %d tx_snr = %d\n", 1809 nsec, tx_ssr, tx_snr); 1810 *timestamp = rte_ns_to_timespec(nsec); 1811 return 0; 1812 } 1813 1814 static int 1815 axgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on) 1816 { 1817 struct axgbe_port *pdata = dev->data->dev_private; 1818 unsigned long vid_bit, vid_idx; 1819 1820 vid_bit = VLAN_TABLE_BIT(vid); 1821 vid_idx = VLAN_TABLE_IDX(vid); 1822 1823 if (on) { 1824 PMD_DRV_LOG(DEBUG, "Set VLAN vid=%d for device = %s\n", 1825 vid, pdata->eth_dev->device->name); 1826 pdata->active_vlans[vid_idx] |= vid_bit; 1827 } else { 1828 PMD_DRV_LOG(DEBUG, "Reset VLAN vid=%d for device = %s\n", 1829 vid, pdata->eth_dev->device->name); 1830 pdata->active_vlans[vid_idx] &= ~vid_bit; 1831 } 1832 pdata->hw_if.update_vlan_hash_table(pdata); 1833 return 0; 1834 } 1835 1836 static int 1837 axgbe_vlan_tpid_set(struct rte_eth_dev *dev, 1838 enum rte_vlan_type vlan_type, 1839 uint16_t tpid) 1840 { 1841 struct axgbe_port *pdata = dev->data->dev_private; 1842 uint32_t reg = 0; 1843 uint32_t qinq = 0; 1844 1845 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1846 PMD_DRV_LOG(DEBUG, "EDVLP: qinq = 0x%x\n", qinq); 1847 1848 switch (vlan_type) { 1849 case RTE_ETH_VLAN_TYPE_INNER: 1850 PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_INNER\n"); 1851 if (qinq) { 1852 if (tpid != 0x8100 && tpid != 0x88a8) 1853 PMD_DRV_LOG(ERR, 1854 "tag supported 0x8100/0x88A8\n"); 1855 PMD_DRV_LOG(DEBUG, "qinq with inner tag\n"); 1856 1857 /*Enable Inner VLAN Tag */ 1858 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 1); 1859 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1860 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg); 1861 1862 } else { 1863 PMD_DRV_LOG(ERR, 1864 "Inner type not supported in single tag\n"); 1865 } 1866 break; 1867 case RTE_ETH_VLAN_TYPE_OUTER: 1868 PMD_DRV_LOG(DEBUG, "RTE_ETH_VLAN_TYPE_OUTER\n"); 1869 if (qinq) { 1870 PMD_DRV_LOG(DEBUG, "double tagging is enabled\n"); 1871 /*Enable outer VLAN tag*/ 1872 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERIVLT, 0); 1873 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, ERIVLT); 1874 PMD_DRV_LOG(DEBUG, "bit ERIVLT = 0x%x\n", reg); 1875 1876 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 1); 1877 reg = AXGMAC_IOREAD_BITS(pdata, MAC_VLANIR, CSVL); 1878 PMD_DRV_LOG(DEBUG, "bit CSVL = 0x%x\n", reg); 1879 } else { 1880 if (tpid != 0x8100 && tpid != 0x88a8) 1881 PMD_DRV_LOG(ERR, 1882 "tag supported 0x8100/0x88A8\n"); 1883 } 1884 break; 1885 case RTE_ETH_VLAN_TYPE_MAX: 1886 PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_MAX\n"); 1887 break; 1888 case RTE_ETH_VLAN_TYPE_UNKNOWN: 1889 PMD_DRV_LOG(ERR, "RTE_ETH_VLAN_TYPE_UNKNOWN\n"); 1890 break; 1891 } 1892 return 0; 1893 } 1894 1895 static void axgbe_vlan_extend_enable(struct axgbe_port *pdata) 1896 { 1897 int qinq = 0; 1898 1899 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 1); 1900 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1901 PMD_DRV_LOG(DEBUG, "vlan double tag enabled EDVLP:qinq=0x%x\n", qinq); 1902 } 1903 1904 static void axgbe_vlan_extend_disable(struct axgbe_port *pdata) 1905 { 1906 int qinq = 0; 1907 1908 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EDVLP, 0); 1909 qinq = AXGMAC_IOREAD_BITS(pdata, MAC_VLANTR, EDVLP); 1910 PMD_DRV_LOG(DEBUG, "vlan double tag disable EDVLP:qinq=0x%x\n", qinq); 1911 } 1912 1913 static int 1914 axgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask) 1915 { 1916 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode; 1917 struct axgbe_port *pdata = dev->data->dev_private; 1918 1919 /* Indicate that VLAN Tx CTAGs come from context descriptors */ 1920 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); 1921 AXGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); 1922 1923 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 1924 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) { 1925 PMD_DRV_LOG(DEBUG, "Strip ON for device = %s\n", 1926 pdata->eth_dev->device->name); 1927 pdata->hw_if.enable_rx_vlan_stripping(pdata); 1928 } else { 1929 PMD_DRV_LOG(DEBUG, "Strip OFF for device = %s\n", 1930 pdata->eth_dev->device->name); 1931 pdata->hw_if.disable_rx_vlan_stripping(pdata); 1932 } 1933 } 1934 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 1935 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 1936 PMD_DRV_LOG(DEBUG, "Filter ON for device = %s\n", 1937 pdata->eth_dev->device->name); 1938 pdata->hw_if.enable_rx_vlan_filtering(pdata); 1939 } else { 1940 PMD_DRV_LOG(DEBUG, "Filter OFF for device = %s\n", 1941 pdata->eth_dev->device->name); 1942 pdata->hw_if.disable_rx_vlan_filtering(pdata); 1943 } 1944 } 1945 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 1946 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) { 1947 PMD_DRV_LOG(DEBUG, "enabling vlan extended mode\n"); 1948 axgbe_vlan_extend_enable(pdata); 1949 /* Set global registers with default ethertype*/ 1950 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER, 1951 RTE_ETHER_TYPE_VLAN); 1952 axgbe_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER, 1953 RTE_ETHER_TYPE_VLAN); 1954 } else { 1955 PMD_DRV_LOG(DEBUG, "disabling vlan extended mode\n"); 1956 axgbe_vlan_extend_disable(pdata); 1957 } 1958 } 1959 return 0; 1960 } 1961 1962 static void axgbe_get_all_hw_features(struct axgbe_port *pdata) 1963 { 1964 unsigned int mac_hfr0, mac_hfr1, mac_hfr2, mac_hfr3; 1965 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 1966 1967 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R); 1968 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R); 1969 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R); 1970 mac_hfr3 = AXGMAC_IOREAD(pdata, MAC_HWF3R); 1971 1972 memset(hw_feat, 0, sizeof(*hw_feat)); 1973 1974 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR); 1975 1976 /* Hardware feature register 0 */ 1977 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 1978 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 1979 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 1980 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 1981 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 1982 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 1983 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 1984 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 1985 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 1986 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 1987 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 1988 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 1989 ADDMACADRSEL); 1990 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 1991 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 1992 1993 /* Hardware feature register 1 */ 1994 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1995 RXFIFOSIZE); 1996 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 1997 TXFIFOSIZE); 1998 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1, 1999 MAC_HWF1R, ADVTHWORD); 2000 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 2001 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 2002 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 2003 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 2004 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 2005 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 2006 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 2007 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 2008 HASHTBLSZ); 2009 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 2010 L3L4FNUM); 2011 2012 /* Hardware feature register 2 */ 2013 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 2014 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 2015 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 2016 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 2017 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 2018 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, 2019 AUXSNAPNUM); 2020 2021 /* Hardware feature register 3 */ 2022 hw_feat->tx_q_vlan_tag_ins = AXGMAC_GET_BITS(mac_hfr3, 2023 MAC_HWF3R, CBTISEL); 2024 hw_feat->no_of_vlan_extn = AXGMAC_GET_BITS(mac_hfr3, 2025 MAC_HWF3R, NRVF); 2026 2027 /* Translate the Hash Table size into actual number */ 2028 switch (hw_feat->hash_table_size) { 2029 case 0: 2030 break; 2031 case 1: 2032 hw_feat->hash_table_size = 64; 2033 break; 2034 case 2: 2035 hw_feat->hash_table_size = 128; 2036 break; 2037 case 3: 2038 hw_feat->hash_table_size = 256; 2039 break; 2040 } 2041 2042 /* Translate the address width setting into actual number */ 2043 switch (hw_feat->dma_width) { 2044 case 0: 2045 hw_feat->dma_width = 32; 2046 break; 2047 case 1: 2048 hw_feat->dma_width = 40; 2049 break; 2050 case 2: 2051 hw_feat->dma_width = 48; 2052 break; 2053 default: 2054 hw_feat->dma_width = 32; 2055 } 2056 2057 /* The Queue, Channel and TC counts are zero based so increment them 2058 * to get the actual number 2059 */ 2060 hw_feat->rx_q_cnt++; 2061 hw_feat->tx_q_cnt++; 2062 hw_feat->rx_ch_cnt++; 2063 hw_feat->tx_ch_cnt++; 2064 hw_feat->tc_cnt++; 2065 2066 /* Translate the fifo sizes into actual numbers */ 2067 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 2068 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 2069 } 2070 2071 static void axgbe_init_all_fptrs(struct axgbe_port *pdata) 2072 { 2073 axgbe_init_function_ptrs_dev(&pdata->hw_if); 2074 axgbe_init_function_ptrs_phy(&pdata->phy_if); 2075 axgbe_init_function_ptrs_i2c(&pdata->i2c_if); 2076 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 2077 } 2078 2079 static void axgbe_set_counts(struct axgbe_port *pdata) 2080 { 2081 /* Set all the function pointers */ 2082 axgbe_init_all_fptrs(pdata); 2083 2084 /* Populate the hardware features */ 2085 axgbe_get_all_hw_features(pdata); 2086 2087 /* Set default max values if not provided */ 2088 if (!pdata->tx_max_channel_count) 2089 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 2090 if (!pdata->rx_max_channel_count) 2091 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 2092 2093 if (!pdata->tx_max_q_count) 2094 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 2095 if (!pdata->rx_max_q_count) 2096 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 2097 2098 /* Calculate the number of Tx and Rx rings to be created 2099 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 2100 * the number of Tx queues to the number of Tx channels 2101 * enabled 2102 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 2103 * number of Rx queues or maximum allowed 2104 */ 2105 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt, 2106 pdata->tx_max_channel_count); 2107 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count, 2108 pdata->tx_max_q_count); 2109 2110 pdata->tx_q_count = pdata->tx_ring_count; 2111 2112 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt, 2113 pdata->rx_max_channel_count); 2114 2115 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt, 2116 pdata->rx_max_q_count); 2117 } 2118 2119 static void axgbe_default_config(struct axgbe_port *pdata) 2120 { 2121 pdata->pblx8 = DMA_PBL_X8_ENABLE; 2122 pdata->tx_sf_mode = MTL_TSF_ENABLE; 2123 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 2124 pdata->tx_pbl = DMA_PBL_32; 2125 pdata->tx_osp_mode = DMA_OSP_ENABLE; 2126 pdata->rx_sf_mode = MTL_RSF_ENABLE; 2127 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 2128 pdata->rx_pbl = DMA_PBL_32; 2129 pdata->pause_autoneg = 1; 2130 pdata->tx_pause = 0; 2131 pdata->rx_pause = 0; 2132 pdata->phy_speed = SPEED_UNKNOWN; 2133 pdata->power_down = 0; 2134 } 2135 2136 /* Used in dev_start by primary process and then 2137 * in dev_init by secondary process when attaching to an existing ethdev. 2138 */ 2139 void 2140 axgbe_set_tx_function(struct rte_eth_dev *dev) 2141 { 2142 struct axgbe_port *pdata = dev->data->dev_private; 2143 2144 dev->tx_pkt_burst = &axgbe_xmit_pkts; 2145 2146 if (pdata->multi_segs_tx) 2147 dev->tx_pkt_burst = &axgbe_xmit_pkts_seg; 2148 #ifdef RTE_ARCH_X86 2149 struct axgbe_tx_queue *txq = dev->data->tx_queues[0]; 2150 if (!txq->vector_disable && 2151 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) 2152 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec; 2153 #endif 2154 } 2155 2156 void 2157 axgbe_set_rx_function(struct rte_eth_dev *dev) 2158 { 2159 struct rte_eth_dev_data *dev_data = dev->data; 2160 uint16_t max_pkt_len; 2161 struct axgbe_port *pdata; 2162 2163 pdata = dev->data->dev_private; 2164 max_pkt_len = dev_data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 2165 if ((dev_data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) || 2166 max_pkt_len > pdata->rx_buf_size) 2167 dev_data->scattered_rx = 1; 2168 /* Scatter Rx handling */ 2169 if (dev_data->scattered_rx) 2170 dev->rx_pkt_burst = ð_axgbe_recv_scattered_pkts; 2171 else 2172 dev->rx_pkt_burst = &axgbe_recv_pkts; 2173 } 2174 2175 /* 2176 * It returns 0 on success. 2177 */ 2178 static int 2179 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) 2180 { 2181 PMD_INIT_FUNC_TRACE(); 2182 struct axgbe_port *pdata; 2183 struct rte_pci_device *pci_dev; 2184 uint32_t reg, mac_lo, mac_hi; 2185 uint32_t len; 2186 int ret; 2187 2188 unsigned int eax = 0, ebx = 0, ecx = 0, edx = 0; 2189 unsigned char cpu_family = 0, cpu_model = 0; 2190 2191 eth_dev->dev_ops = &axgbe_eth_dev_ops; 2192 2193 eth_dev->rx_descriptor_status = axgbe_dev_rx_descriptor_status; 2194 eth_dev->tx_descriptor_status = axgbe_dev_tx_descriptor_status; 2195 2196 eth_dev->tx_pkt_burst = &axgbe_xmit_pkts; 2197 eth_dev->rx_pkt_burst = &axgbe_recv_pkts; 2198 2199 /* 2200 * For secondary processes, we don't initialise any further as primary 2201 * has already done this work. 2202 */ 2203 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2204 axgbe_set_tx_function(eth_dev); 2205 axgbe_set_rx_function(eth_dev); 2206 return 0; 2207 } 2208 2209 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2210 2211 pdata = eth_dev->data->dev_private; 2212 /* initial state */ 2213 rte_bit_relaxed_set32(AXGBE_DOWN, &pdata->dev_state); 2214 rte_bit_relaxed_set32(AXGBE_STOPPED, &pdata->dev_state); 2215 pdata->eth_dev = eth_dev; 2216 2217 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2218 pdata->pci_dev = pci_dev; 2219 2220 pdata->xgmac_regs = 2221 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; 2222 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs 2223 + AXGBE_MAC_PROP_OFFSET); 2224 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs 2225 + AXGBE_I2C_CTRL_OFFSET); 2226 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; 2227 2228 /* version specific driver data*/ 2229 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A) 2230 pdata->vdata = &axgbe_v2a; 2231 else 2232 pdata->vdata = &axgbe_v2b; 2233 2234 /* 2235 * Use CPUID to get Family and model ID to identify the CPU 2236 */ 2237 __cpuid(0x0, eax, ebx, ecx, edx); 2238 2239 if (ebx == CPUID_VENDOR_AuthenticAMD_ebx && 2240 edx == CPUID_VENDOR_AuthenticAMD_edx && 2241 ecx == CPUID_VENDOR_AuthenticAMD_ecx) { 2242 int unknown_cpu = 0; 2243 eax = 0, ebx = 0, ecx = 0, edx = 0; 2244 2245 __cpuid(0x1, eax, ebx, ecx, edx); 2246 2247 cpu_family = ((GET_BITS(eax, 8, 4)) + (GET_BITS(eax, 20, 8))); 2248 cpu_model = ((GET_BITS(eax, 4, 4)) | (((GET_BITS(eax, 16, 4)) << 4) & 0xF0)); 2249 2250 switch (cpu_family) { 2251 case Fam17h: 2252 /* V1000/R1000 */ 2253 if (cpu_model >= 0x10 && cpu_model <= 0x1F) { 2254 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF; 2255 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT; 2256 /* EPYC 3000 */ 2257 } else if (cpu_model >= 0x01 && cpu_model <= 0x0F) { 2258 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 2259 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 2260 } else { 2261 unknown_cpu = 1; 2262 } 2263 break; 2264 case Fam19h: 2265 /* V3000 (Yellow Carp) */ 2266 if (cpu_model >= 0x44 && cpu_model <= 0x47) { 2267 pdata->xpcs_window_def_reg = PCS_V2_YC_WINDOW_DEF; 2268 pdata->xpcs_window_sel_reg = PCS_V2_YC_WINDOW_SELECT; 2269 2270 /* Yellow Carp devices do not need cdr workaround */ 2271 pdata->vdata->an_cdr_workaround = 0; 2272 } else { 2273 unknown_cpu = 1; 2274 } 2275 break; 2276 default: 2277 unknown_cpu = 1; 2278 break; 2279 } 2280 if (unknown_cpu) { 2281 PMD_DRV_LOG(ERR, "Unknown CPU family, no supported axgbe device found\n"); 2282 return -ENODEV; 2283 } 2284 } 2285 2286 /* Configure the PCS indirect addressing support */ 2287 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg); 2288 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 2289 pdata->xpcs_window <<= 6; 2290 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 2291 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 2292 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 2293 2294 PMD_INIT_LOG(DEBUG, 2295 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, 2296 pdata->xpcs_window_size, pdata->xpcs_window_mask); 2297 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 2298 2299 /* Retrieve the MAC address */ 2300 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 2301 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 2302 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff; 2303 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff; 2304 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff; 2305 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff; 2306 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff; 2307 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff; 2308 2309 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_MAC_ADDRS; 2310 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", len, 0); 2311 2312 if (!eth_dev->data->mac_addrs) { 2313 PMD_INIT_LOG(ERR, 2314 "Failed to alloc %u bytes needed to " 2315 "store MAC addresses", len); 2316 return -ENOMEM; 2317 } 2318 2319 /* Allocate memory for storing hash filter MAC addresses */ 2320 len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS; 2321 eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr", 2322 len, 0); 2323 2324 if (eth_dev->data->hash_mac_addrs == NULL) { 2325 PMD_INIT_LOG(ERR, 2326 "Failed to allocate %d bytes needed to " 2327 "store MAC addresses", len); 2328 return -ENOMEM; 2329 } 2330 2331 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr)) 2332 rte_eth_random_addr(pdata->mac_addr.addr_bytes); 2333 2334 /* Copy the permanent MAC address */ 2335 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]); 2336 2337 /* Clock settings */ 2338 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ; 2339 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 2340 2341 /* Set the DMA coherency values */ 2342 pdata->coherent = 1; 2343 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN; 2344 pdata->arcache = AXGBE_DMA_OS_ARCACHE; 2345 pdata->awcache = AXGBE_DMA_OS_AWCACHE; 2346 2347 /* Read the port property registers */ 2348 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0); 2349 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1); 2350 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2); 2351 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3); 2352 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4); 2353 2354 /* Set the maximum channels and queues */ 2355 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_TX_DMA); 2356 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_RX_DMA); 2357 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_TX_QUEUES); 2358 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_RX_QUEUES); 2359 2360 /* Set the hardware channel and queue counts */ 2361 axgbe_set_counts(pdata); 2362 2363 /* Set the maximum fifo amounts */ 2364 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2, TX_FIFO_SIZE); 2365 pdata->tx_max_fifo_size *= 16384; 2366 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size, 2367 pdata->vdata->tx_max_fifo_size); 2368 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2, RX_FIFO_SIZE); 2369 pdata->rx_max_fifo_size *= 16384; 2370 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size, 2371 pdata->vdata->rx_max_fifo_size); 2372 /* Issue software reset to DMA */ 2373 ret = pdata->hw_if.exit(pdata); 2374 if (ret) 2375 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n"); 2376 2377 /* Set default configuration data */ 2378 axgbe_default_config(pdata); 2379 2380 /* Set default max values if not provided */ 2381 if (!pdata->tx_max_fifo_size) 2382 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 2383 if (!pdata->rx_max_fifo_size) 2384 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 2385 2386 pdata->tx_desc_count = AXGBE_MAX_RING_DESC; 2387 pdata->rx_desc_count = AXGBE_MAX_RING_DESC; 2388 pthread_mutex_init(&pdata->xpcs_mutex, NULL); 2389 pthread_mutex_init(&pdata->i2c_mutex, NULL); 2390 pthread_mutex_init(&pdata->an_mutex, NULL); 2391 pthread_mutex_init(&pdata->phy_mutex, NULL); 2392 2393 ret = pdata->phy_if.phy_init(pdata); 2394 if (ret) { 2395 rte_free(eth_dev->data->mac_addrs); 2396 eth_dev->data->mac_addrs = NULL; 2397 return ret; 2398 } 2399 2400 rte_intr_callback_register(pci_dev->intr_handle, 2401 axgbe_dev_interrupt_handler, 2402 (void *)eth_dev); 2403 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 2404 eth_dev->data->port_id, pci_dev->id.vendor_id, 2405 pci_dev->id.device_id); 2406 2407 return 0; 2408 } 2409 2410 static int 2411 axgbe_dev_close(struct rte_eth_dev *eth_dev) 2412 { 2413 struct rte_pci_device *pci_dev; 2414 2415 PMD_INIT_FUNC_TRACE(); 2416 2417 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2418 return 0; 2419 2420 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 2421 axgbe_dev_clear_queues(eth_dev); 2422 2423 /* disable uio intr before callback unregister */ 2424 rte_intr_disable(pci_dev->intr_handle); 2425 rte_intr_callback_unregister(pci_dev->intr_handle, 2426 axgbe_dev_interrupt_handler, 2427 (void *)eth_dev); 2428 2429 return 0; 2430 } 2431 2432 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2433 struct rte_pci_device *pci_dev) 2434 { 2435 return rte_eth_dev_pci_generic_probe(pci_dev, 2436 sizeof(struct axgbe_port), eth_axgbe_dev_init); 2437 } 2438 2439 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev) 2440 { 2441 return rte_eth_dev_pci_generic_remove(pci_dev, axgbe_dev_close); 2442 } 2443 2444 static struct rte_pci_driver rte_axgbe_pmd = { 2445 .id_table = pci_id_axgbe_map, 2446 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 2447 .probe = eth_axgbe_pci_probe, 2448 .remove = eth_axgbe_pci_remove, 2449 }; 2450 2451 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd); 2452 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map); 2453 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 2454 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_init, init, NOTICE); 2455 RTE_LOG_REGISTER_SUFFIX(axgbe_logtype_driver, driver, NOTICE); 2456