1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */ 2 /* Copyright (C) 2014-2017 aQuantia Corporation. */ 3 4 /* File hw_atl_llh_internal.h: Preprocessor definitions 5 * for Atlantic registers. 6 */ 7 8 #ifndef HW_ATL_LLH_INTERNAL_H 9 #define HW_ATL_LLH_INTERNAL_H 10 11 /* global microprocessor semaphore definitions 12 * base address: 0x000003a0 13 * parameter: semaphore {s} | stride size 0x4 | range [0, 15] 14 */ 15 #define HW_ATL_GLB_CPU_SEM_ADR(semaphore) (0x000003a0u + (semaphore) * 0x4) 16 /* register address for bitfield rx dma good octet counter lsw [1f:0] */ 17 #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808 18 /* register address for bitfield rx dma good packet counter lsw [1f:0] */ 19 #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800 20 /* register address for bitfield tx dma good octet counter lsw [1f:0] */ 21 #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808 22 /* register address for bitfield tx dma good packet counter lsw [1f:0] */ 23 #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800 24 25 /* register address for bitfield rx dma good octet counter msw [3f:20] */ 26 #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c 27 /* register address for bitfield rx dma good packet counter msw [3f:20] */ 28 #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804 29 /* register address for bitfield tx dma good octet counter msw [3f:20] */ 30 #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c 31 /* register address for bitfield tx dma good packet counter msw [3f:20] */ 32 #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804 33 34 /* preprocessor definitions for msm rx errors counter register */ 35 #define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u 36 37 /* preprocessor definitions for msm rx unicast frames counter register */ 38 #define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR 0x000000e0u 39 40 /* preprocessor definitions for msm rx multicast frames counter register */ 41 #define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR 0x000000e8u 42 43 /* preprocessor definitions for msm rx broadcast frames counter register */ 44 #define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR 0x000000f0u 45 46 /* preprocessor definitions for msm rx broadcast octets counter register 1 */ 47 #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR 0x000001b0u 48 49 /* preprocessor definitions for msm rx broadcast octets counter register 2 */ 50 #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR 0x000001b4u 51 52 /* preprocessor definitions for msm rx unicast octets counter register 0 */ 53 #define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u 54 55 /* preprocessor definitions for msm tx unicast frames counter register */ 56 #define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u 57 58 /* preprocessor definitions for msm tx multicast frames counter register */ 59 #define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR 0x00000110u 60 61 /* preprocessor definitions for global mif identification */ 62 #define HW_ATL_GLB_MIF_ID_ADR 0x0000001cu 63 64 /* register address for bitfield iamr_lsw[1f:0] */ 65 #define HW_ATL_ITR_IAMRLSW_ADR 0x00002090 66 /* register address for bitfield rx dma drop packet counter [1f:0] */ 67 #define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR 0x00006818 68 69 /* register address for bitfield imcr_lsw[1f:0] */ 70 #define HW_ATL_ITR_IMCRLSW_ADR 0x00002070 71 /* register address for bitfield imsr_lsw[1f:0] */ 72 #define HW_ATL_ITR_IMSRLSW_ADR 0x00002060 73 /* register address for bitfield itr_reg_res_dsbl */ 74 #define HW_ATL_ITR_REG_RES_DSBL_ADR 0x00002300 75 /* bitmask for bitfield itr_reg_res_dsbl */ 76 #define HW_ATL_ITR_REG_RES_DSBL_MSK 0x20000000 77 /* lower bit position of bitfield itr_reg_res_dsbl */ 78 #define HW_ATL_ITR_REG_RES_DSBL_SHIFT 29 79 /* register address for bitfield iscr_lsw[1f:0] */ 80 #define HW_ATL_ITR_ISCRLSW_ADR 0x00002050 81 /* register address for bitfield isr_lsw[1f:0] */ 82 #define HW_ATL_ITR_ISRLSW_ADR 0x00002000 83 /* register address for bitfield itr_reset */ 84 #define HW_ATL_ITR_RES_ADR 0x00002300 85 /* bitmask for bitfield itr_reset */ 86 #define HW_ATL_ITR_RES_MSK 0x80000000 87 /* lower bit position of bitfield itr_reset */ 88 #define HW_ATL_ITR_RES_SHIFT 31 89 /* register address for bitfield dca{d}_cpuid[7:0] */ 90 #define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4) 91 /* bitmask for bitfield dca{d}_cpuid[7:0] */ 92 #define HW_ATL_RDM_DCADCPUID_MSK 0x000000ff 93 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ 94 #define HW_ATL_RDM_DCADCPUID_SHIFT 0 95 /* register address for bitfield dca_en */ 96 #define HW_ATL_RDM_DCA_EN_ADR 0x00006180 97 98 /* rx dca_en bitfield definitions 99 * preprocessor definitions for the bitfield "dca_en". 100 * port="pif_rdm_dca_en_i" 101 */ 102 103 /* register address for bitfield dca_en */ 104 #define HW_ATL_RDM_DCA_EN_ADR 0x00006180 105 /* bitmask for bitfield dca_en */ 106 #define HW_ATL_RDM_DCA_EN_MSK 0x80000000 107 /* inverted bitmask for bitfield dca_en */ 108 #define HW_ATL_RDM_DCA_EN_MSKN 0x7fffffff 109 /* lower bit position of bitfield dca_en */ 110 #define HW_ATL_RDM_DCA_EN_SHIFT 31 111 /* width of bitfield dca_en */ 112 #define HW_ATL_RDM_DCA_EN_WIDTH 1 113 /* default value of bitfield dca_en */ 114 #define HW_ATL_RDM_DCA_EN_DEFAULT 0x1 115 116 /* rx dca_mode[3:0] bitfield definitions 117 * preprocessor definitions for the bitfield "dca_mode[3:0]". 118 * port="pif_rdm_dca_mode_i[3:0]" 119 */ 120 121 /* register address for bitfield dca_mode[3:0] */ 122 #define HW_ATL_RDM_DCA_MODE_ADR 0x00006180 123 /* bitmask for bitfield dca_mode[3:0] */ 124 #define HW_ATL_RDM_DCA_MODE_MSK 0x0000000f 125 /* inverted bitmask for bitfield dca_mode[3:0] */ 126 #define HW_ATL_RDM_DCA_MODE_MSKN 0xfffffff0 127 /* lower bit position of bitfield dca_mode[3:0] */ 128 #define HW_ATL_RDM_DCA_MODE_SHIFT 0 129 /* width of bitfield dca_mode[3:0] */ 130 #define HW_ATL_RDM_DCA_MODE_WIDTH 4 131 /* default value of bitfield dca_mode[3:0] */ 132 #define HW_ATL_RDM_DCA_MODE_DEFAULT 0x0 133 134 /* rx desc{d}_data_size[4:0] bitfield definitions 135 * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]". 136 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 137 * port="pif_rdm_desc0_data_size_i[4:0]" 138 */ 139 140 /* register address for bitfield desc{d}_data_size[4:0] */ 141 #define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) \ 142 (0x00005b18 + (descriptor) * 0x20) 143 /* bitmask for bitfield desc{d}_data_size[4:0] */ 144 #define HW_ATL_RDM_DESCDDATA_SIZE_MSK 0x0000001f 145 /* inverted bitmask for bitfield desc{d}_data_size[4:0] */ 146 #define HW_ATL_RDM_DESCDDATA_SIZE_MSKN 0xffffffe0 147 /* lower bit position of bitfield desc{d}_data_size[4:0] */ 148 #define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT 0 149 /* width of bitfield desc{d}_data_size[4:0] */ 150 #define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH 5 151 /* default value of bitfield desc{d}_data_size[4:0] */ 152 #define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT 0x0 153 154 /* rx dca{d}_desc_en bitfield definitions 155 * preprocessor definitions for the bitfield "dca{d}_desc_en". 156 * parameter: dca {d} | stride size 0x4 | range [0, 31] 157 * port="pif_rdm_dca_desc_en_i[0]" 158 */ 159 160 /* register address for bitfield dca{d}_desc_en */ 161 #define HW_ATL_RDM_DCADDESC_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 162 /* bitmask for bitfield dca{d}_desc_en */ 163 #define HW_ATL_RDM_DCADDESC_EN_MSK 0x80000000 164 /* inverted bitmask for bitfield dca{d}_desc_en */ 165 #define HW_ATL_RDM_DCADDESC_EN_MSKN 0x7fffffff 166 /* lower bit position of bitfield dca{d}_desc_en */ 167 #define HW_ATL_RDM_DCADDESC_EN_SHIFT 31 168 /* width of bitfield dca{d}_desc_en */ 169 #define HW_ATL_RDM_DCADDESC_EN_WIDTH 1 170 /* default value of bitfield dca{d}_desc_en */ 171 #define HW_ATL_RDM_DCADDESC_EN_DEFAULT 0x0 172 173 /* rx desc{d}_en bitfield definitions 174 * preprocessor definitions for the bitfield "desc{d}_en". 175 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 176 * port="pif_rdm_desc_en_i[0]" 177 */ 178 179 /* register address for bitfield desc{d}_en */ 180 #define HW_ATL_RDM_DESCDEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 181 /* bitmask for bitfield desc{d}_en */ 182 #define HW_ATL_RDM_DESCDEN_MSK 0x80000000 183 /* inverted bitmask for bitfield desc{d}_en */ 184 #define HW_ATL_RDM_DESCDEN_MSKN 0x7fffffff 185 /* lower bit position of bitfield desc{d}_en */ 186 #define HW_ATL_RDM_DESCDEN_SHIFT 31 187 /* width of bitfield desc{d}_en */ 188 #define HW_ATL_RDM_DESCDEN_WIDTH 1 189 /* default value of bitfield desc{d}_en */ 190 #define HW_ATL_RDM_DESCDEN_DEFAULT 0x0 191 192 /* rx desc{d}_hdr_size[4:0] bitfield definitions 193 * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]". 194 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 195 * port="pif_rdm_desc0_hdr_size_i[4:0]" 196 */ 197 198 /* register address for bitfield desc{d}_hdr_size[4:0] */ 199 #define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) \ 200 (0x00005b18 + (descriptor) * 0x20) 201 /* bitmask for bitfield desc{d}_hdr_size[4:0] */ 202 #define HW_ATL_RDM_DESCDHDR_SIZE_MSK 0x00001f00 203 /* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */ 204 #define HW_ATL_RDM_DESCDHDR_SIZE_MSKN 0xffffe0ff 205 /* lower bit position of bitfield desc{d}_hdr_size[4:0] */ 206 #define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT 8 207 /* width of bitfield desc{d}_hdr_size[4:0] */ 208 #define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH 5 209 /* default value of bitfield desc{d}_hdr_size[4:0] */ 210 #define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT 0x0 211 212 /* rx desc{d}_hdr_split bitfield definitions 213 * preprocessor definitions for the bitfield "desc{d}_hdr_split". 214 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 215 * port="pif_rdm_desc_hdr_split_i[0]" 216 */ 217 218 /* register address for bitfield desc{d}_hdr_split */ 219 #define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) \ 220 (0x00005b08 + (descriptor) * 0x20) 221 /* bitmask for bitfield desc{d}_hdr_split */ 222 #define HW_ATL_RDM_DESCDHDR_SPLIT_MSK 0x10000000 223 /* inverted bitmask for bitfield desc{d}_hdr_split */ 224 #define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN 0xefffffff 225 /* lower bit position of bitfield desc{d}_hdr_split */ 226 #define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT 28 227 /* width of bitfield desc{d}_hdr_split */ 228 #define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH 1 229 /* default value of bitfield desc{d}_hdr_split */ 230 #define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT 0x0 231 232 /* rx desc{d}_hd[c:0] bitfield definitions 233 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 234 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 235 * port="rdm_pif_desc0_hd_o[12:0]" 236 */ 237 238 /* register address for bitfield desc{d}_hd[c:0] */ 239 #define HW_ATL_RDM_DESCDHD_ADR(descriptor) (0x00005b0c + (descriptor) * 0x20) 240 /* bitmask for bitfield desc{d}_hd[c:0] */ 241 #define HW_ATL_RDM_DESCDHD_MSK 0x00001fff 242 /* inverted bitmask for bitfield desc{d}_hd[c:0] */ 243 #define HW_ATL_RDM_DESCDHD_MSKN 0xffffe000 244 /* lower bit position of bitfield desc{d}_hd[c:0] */ 245 #define HW_ATL_RDM_DESCDHD_SHIFT 0 246 /* width of bitfield desc{d}_hd[c:0] */ 247 #define HW_ATL_RDM_DESCDHD_WIDTH 13 248 249 /* rx desc{d}_len[9:0] bitfield definitions 250 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 251 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 252 * port="pif_rdm_desc0_len_i[9:0]" 253 */ 254 255 /* register address for bitfield desc{d}_len[9:0] */ 256 #define HW_ATL_RDM_DESCDLEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 257 /* bitmask for bitfield desc{d}_len[9:0] */ 258 #define HW_ATL_RDM_DESCDLEN_MSK 0x00001ff8 259 /* inverted bitmask for bitfield desc{d}_len[9:0] */ 260 #define HW_ATL_RDM_DESCDLEN_MSKN 0xffffe007 261 /* lower bit position of bitfield desc{d}_len[9:0] */ 262 #define HW_ATL_RDM_DESCDLEN_SHIFT 3 263 /* width of bitfield desc{d}_len[9:0] */ 264 #define HW_ATL_RDM_DESCDLEN_WIDTH 10 265 /* default value of bitfield desc{d}_len[9:0] */ 266 #define HW_ATL_RDM_DESCDLEN_DEFAULT 0x0 267 268 /* rx desc{d}_reset bitfield definitions 269 * preprocessor definitions for the bitfield "desc{d}_reset". 270 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 271 * port="pif_rdm_q_pf_res_i[0]" 272 */ 273 274 /* register address for bitfield desc{d}_reset */ 275 #define HW_ATL_RDM_DESCDRESET_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 276 /* bitmask for bitfield desc{d}_reset */ 277 #define HW_ATL_RDM_DESCDRESET_MSK 0x02000000 278 /* inverted bitmask for bitfield desc{d}_reset */ 279 #define HW_ATL_RDM_DESCDRESET_MSKN 0xfdffffff 280 /* lower bit position of bitfield desc{d}_reset */ 281 #define HW_ATL_RDM_DESCDRESET_SHIFT 25 282 /* width of bitfield desc{d}_reset */ 283 #define HW_ATL_RDM_DESCDRESET_WIDTH 1 284 /* default value of bitfield desc{d}_reset */ 285 #define HW_ATL_RDM_DESCDRESET_DEFAULT 0x0 286 287 /* rx int_desc_wrb_en bitfield definitions 288 * preprocessor definitions for the bitfield "int_desc_wrb_en". 289 * port="pif_rdm_int_desc_wrb_en_i" 290 */ 291 292 /* register address for bitfield int_desc_wrb_en */ 293 #define HW_ATL_RDM_INT_DESC_WRB_EN_ADR 0x00005a30 294 /* bitmask for bitfield int_desc_wrb_en */ 295 #define HW_ATL_RDM_INT_DESC_WRB_EN_MSK 0x00000004 296 /* inverted bitmask for bitfield int_desc_wrb_en */ 297 #define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN 0xfffffffb 298 /* lower bit position of bitfield int_desc_wrb_en */ 299 #define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT 2 300 /* width of bitfield int_desc_wrb_en */ 301 #define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH 1 302 /* default value of bitfield int_desc_wrb_en */ 303 #define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT 0x0 304 305 /* rx dca{d}_hdr_en bitfield definitions 306 * preprocessor definitions for the bitfield "dca{d}_hdr_en". 307 * parameter: dca {d} | stride size 0x4 | range [0, 31] 308 * port="pif_rdm_dca_hdr_en_i[0]" 309 */ 310 311 /* register address for bitfield dca{d}_hdr_en */ 312 #define HW_ATL_RDM_DCADHDR_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 313 /* bitmask for bitfield dca{d}_hdr_en */ 314 #define HW_ATL_RDM_DCADHDR_EN_MSK 0x40000000 315 /* inverted bitmask for bitfield dca{d}_hdr_en */ 316 #define HW_ATL_RDM_DCADHDR_EN_MSKN 0xbfffffff 317 /* lower bit position of bitfield dca{d}_hdr_en */ 318 #define HW_ATL_RDM_DCADHDR_EN_SHIFT 30 319 /* width of bitfield dca{d}_hdr_en */ 320 #define HW_ATL_RDM_DCADHDR_EN_WIDTH 1 321 /* default value of bitfield dca{d}_hdr_en */ 322 #define HW_ATL_RDM_DCADHDR_EN_DEFAULT 0x0 323 324 /* rx dca{d}_pay_en bitfield definitions 325 * preprocessor definitions for the bitfield "dca{d}_pay_en". 326 * parameter: dca {d} | stride size 0x4 | range [0, 31] 327 * port="pif_rdm_dca_pay_en_i[0]" 328 */ 329 330 /* register address for bitfield dca{d}_pay_en */ 331 #define HW_ATL_RDM_DCADPAY_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 332 /* bitmask for bitfield dca{d}_pay_en */ 333 #define HW_ATL_RDM_DCADPAY_EN_MSK 0x20000000 334 /* inverted bitmask for bitfield dca{d}_pay_en */ 335 #define HW_ATL_RDM_DCADPAY_EN_MSKN 0xdfffffff 336 /* lower bit position of bitfield dca{d}_pay_en */ 337 #define HW_ATL_RDM_DCADPAY_EN_SHIFT 29 338 /* width of bitfield dca{d}_pay_en */ 339 #define HW_ATL_RDM_DCADPAY_EN_WIDTH 1 340 /* default value of bitfield dca{d}_pay_en */ 341 #define HW_ATL_RDM_DCADPAY_EN_DEFAULT 0x0 342 343 /* RX rdm_int_rim_en Bitfield Definitions 344 * Preprocessor definitions for the bitfield "rdm_int_rim_en". 345 * PORT="pif_rdm_int_rim_en_i" 346 */ 347 348 /* Register address for bitfield rdm_int_rim_en */ 349 #define HW_ATL_RDM_INT_RIM_EN_ADR 0x00005A30 350 /* Bitmask for bitfield rdm_int_rim_en */ 351 #define HW_ATL_RDM_INT_RIM_EN_MSK 0x00000008 352 /* Inverted bitmask for bitfield rdm_int_rim_en */ 353 #define HW_ATL_RDM_INT_RIM_EN_MSKN 0xFFFFFFF7 354 /* Lower bit position of bitfield rdm_int_rim_en */ 355 #define HW_ATL_RDM_INT_RIM_EN_SHIFT 3 356 /* Width of bitfield rdm_int_rim_en */ 357 #define HW_ATL_RDM_INT_RIM_EN_WIDTH 1 358 /* Default value of bitfield rdm_int_rim_en */ 359 #define HW_ATL_RDM_INT_RIM_EN_DEFAULT 0x0 360 361 /* general interrupt mapping register definitions 362 * preprocessor definitions for general interrupt mapping register 363 * base address: 0x00002180 364 * parameter: regidx {f} | stride size 0x4 | range [0, 3] 365 */ 366 #define HW_ATL_GEN_INTR_MAP_ADR(regidx) (0x00002180u + (regidx) * 0x4) 367 368 /* general interrupt status register definitions 369 * preprocessor definitions for general interrupt status register 370 * address: 0x000021A0 371 */ 372 373 #define HW_ATL_GEN_INTR_STAT_ADR 0x000021A4U 374 375 /* interrupt global control register definitions 376 * preprocessor definitions for interrupt global control register 377 * address: 0x00002300 378 */ 379 #define HW_ATL_INTR_GLB_CTL_ADR 0x00002300u 380 381 /* interrupt throttle register definitions 382 * preprocessor definitions for interrupt throttle register 383 * base address: 0x00002800 384 * parameter: throttle {t} | stride size 0x4 | range [0, 31] 385 */ 386 #define HW_ATL_INTR_THR_ADR(throttle) (0x00002800u + (throttle) * 0x4) 387 388 /* rx dma descriptor base address lsw definitions 389 * preprocessor definitions for rx dma descriptor base address lsw 390 * base address: 0x00005b00 391 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 392 */ 393 #define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ 394 (0x00005b00u + (descriptor) * 0x20) 395 396 /* rx dma descriptor base address msw definitions 397 * preprocessor definitions for rx dma descriptor base address msw 398 * base address: 0x00005b04 399 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 400 */ 401 #define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ 402 (0x00005b04u + (descriptor) * 0x20) 403 404 /* rx dma descriptor status register definitions 405 * preprocessor definitions for rx dma descriptor status register 406 * base address: 0x00005b14 407 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 408 */ 409 #define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) \ 410 (0x00005b14u + (descriptor) * 0x20) 411 412 /* rx dma descriptor tail pointer register definitions 413 * preprocessor definitions for rx dma descriptor tail pointer register 414 * base address: 0x00005b10 415 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 416 */ 417 #define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ 418 (0x00005b10u + (descriptor) * 0x20) 419 420 /* rx interrupt moderation control register definitions 421 * Preprocessor definitions for RX Interrupt Moderation Control Register 422 * Base Address: 0x00005A40 423 * Parameter: RIM {R} | stride size 0x4 | range [0, 31] 424 */ 425 #define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) (0x00005A40u + (rim) * 0x4) 426 427 /* rx filter multicast filter mask register definitions 428 * preprocessor definitions for rx filter multicast filter mask register 429 * address: 0x00005270 430 */ 431 #define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR 0x00005270u 432 433 /* rx filter multicast filter register definitions 434 * preprocessor definitions for rx filter multicast filter register 435 * base address: 0x00005250 436 * parameter: filter {f} | stride size 0x4 | range [0, 7] 437 */ 438 #define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) (0x00005250u + (filter) * 0x4) 439 440 /* RX Filter RSS Control Register 1 Definitions 441 * Preprocessor definitions for RX Filter RSS Control Register 1 442 * Address: 0x000054C0 443 */ 444 #define HW_ATL_RX_FLR_RSS_CONTROL1_ADR 0x000054C0u 445 446 /* RX Filter Control Register 2 Definitions 447 * Preprocessor definitions for RX Filter Control Register 2 448 * Address: 0x00005104 449 */ 450 #define HW_ATL_RX_FLR_CONTROL2_ADR 0x00005104u 451 452 /* tx tx dma debug control [1f:0] bitfield definitions 453 * preprocessor definitions for the bitfield "tx dma debug control [1f:0]". 454 * port="pif_tdm_debug_cntl_i[31:0]" 455 */ 456 457 /* register address for bitfield tx dma debug control [1f:0] */ 458 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR 0x00008920 459 /* bitmask for bitfield tx dma debug control [1f:0] */ 460 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK 0xffffffff 461 /* inverted bitmask for bitfield tx dma debug control [1f:0] */ 462 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN 0x00000000 463 /* lower bit position of bitfield tx dma debug control [1f:0] */ 464 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT 0 465 /* width of bitfield tx dma debug control [1f:0] */ 466 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH 32 467 /* default value of bitfield tx dma debug control [1f:0] */ 468 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT 0x0 469 470 /* tx dma descriptor base address lsw definitions 471 * preprocessor definitions for tx dma descriptor base address lsw 472 * base address: 0x00007c00 473 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 474 */ 475 #define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ 476 (0x00007c00u + (descriptor) * 0x40) 477 478 /* tx dma descriptor tail pointer register definitions 479 * preprocessor definitions for tx dma descriptor tail pointer register 480 * base address: 0x00007c10 481 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 482 */ 483 #define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ 484 (0x00007c10u + (descriptor) * 0x40) 485 486 /* rx dma_sys_loopback bitfield definitions 487 * preprocessor definitions for the bitfield "dma_sys_loopback". 488 * port="pif_rpb_dma_sys_lbk_i" 489 */ 490 491 /* register address for bitfield dma_sys_loopback */ 492 #define HW_ATL_RPB_DMA_SYS_LBK_ADR 0x00005000 493 /* bitmask for bitfield dma_sys_loopback */ 494 #define HW_ATL_RPB_DMA_SYS_LBK_MSK 0x00000040 495 /* inverted bitmask for bitfield dma_sys_loopback */ 496 #define HW_ATL_RPB_DMA_SYS_LBK_MSKN 0xffffffbf 497 /* lower bit position of bitfield dma_sys_loopback */ 498 #define HW_ATL_RPB_DMA_SYS_LBK_SHIFT 6 499 /* width of bitfield dma_sys_loopback */ 500 #define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1 501 /* default value of bitfield dma_sys_loopback */ 502 #define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0 503 504 /* rx rx_tc_mode bitfield definitions 505 * preprocessor definitions for the bitfield "rx_tc_mode". 506 * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i" 507 */ 508 509 /* register address for bitfield rx_tc_mode */ 510 #define HW_ATL_RPB_RPF_RX_TC_MODE_ADR 0x00005700 511 /* bitmask for bitfield rx_tc_mode */ 512 #define HW_ATL_RPB_RPF_RX_TC_MODE_MSK 0x00000100 513 /* inverted bitmask for bitfield rx_tc_mode */ 514 #define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN 0xfffffeff 515 /* lower bit position of bitfield rx_tc_mode */ 516 #define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT 8 517 /* width of bitfield rx_tc_mode */ 518 #define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH 1 519 /* default value of bitfield rx_tc_mode */ 520 #define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT 0x0 521 522 /* rx rx_buf_en bitfield definitions 523 * preprocessor definitions for the bitfield "rx_buf_en". 524 * port="pif_rpb_rx_buf_en_i" 525 */ 526 527 /* register address for bitfield rx_buf_en */ 528 #define HW_ATL_RPB_RX_BUF_EN_ADR 0x00005700 529 /* bitmask for bitfield rx_buf_en */ 530 #define HW_ATL_RPB_RX_BUF_EN_MSK 0x00000001 531 /* inverted bitmask for bitfield rx_buf_en */ 532 #define HW_ATL_RPB_RX_BUF_EN_MSKN 0xfffffffe 533 /* lower bit position of bitfield rx_buf_en */ 534 #define HW_ATL_RPB_RX_BUF_EN_SHIFT 0 535 /* width of bitfield rx_buf_en */ 536 #define HW_ATL_RPB_RX_BUF_EN_WIDTH 1 537 /* default value of bitfield rx_buf_en */ 538 #define HW_ATL_RPB_RX_BUF_EN_DEFAULT 0x0 539 540 /* rx rx{b}_hi_thresh[d:0] bitfield definitions 541 * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]". 542 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 543 * port="pif_rpb_rx0_hi_thresh_i[13:0]" 544 */ 545 546 /* register address for bitfield rx{b}_hi_thresh[d:0] */ 547 #define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) 548 /* bitmask for bitfield rx{b}_hi_thresh[d:0] */ 549 #define HW_ATL_RPB_RXBHI_THRESH_MSK 0x3fff0000 550 /* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */ 551 #define HW_ATL_RPB_RXBHI_THRESH_MSKN 0xc000ffff 552 /* lower bit position of bitfield rx{b}_hi_thresh[d:0] */ 553 #define HW_ATL_RPB_RXBHI_THRESH_SHIFT 16 554 /* width of bitfield rx{b}_hi_thresh[d:0] */ 555 #define HW_ATL_RPB_RXBHI_THRESH_WIDTH 14 556 /* default value of bitfield rx{b}_hi_thresh[d:0] */ 557 #define HW_ATL_RPB_RXBHI_THRESH_DEFAULT 0x0 558 559 /* rx rx{b}_lo_thresh[d:0] bitfield definitions 560 * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]". 561 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 562 * port="pif_rpb_rx0_lo_thresh_i[13:0]" 563 */ 564 565 /* register address for bitfield rx{b}_lo_thresh[d:0] */ 566 #define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) 567 /* bitmask for bitfield rx{b}_lo_thresh[d:0] */ 568 #define HW_ATL_RPB_RXBLO_THRESH_MSK 0x00003fff 569 /* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */ 570 #define HW_ATL_RPB_RXBLO_THRESH_MSKN 0xffffc000 571 /* lower bit position of bitfield rx{b}_lo_thresh[d:0] */ 572 #define HW_ATL_RPB_RXBLO_THRESH_SHIFT 0 573 /* width of bitfield rx{b}_lo_thresh[d:0] */ 574 #define HW_ATL_RPB_RXBLO_THRESH_WIDTH 14 575 /* default value of bitfield rx{b}_lo_thresh[d:0] */ 576 #define HW_ATL_RPB_RXBLO_THRESH_DEFAULT 0x0 577 578 /* rx rx_fc_mode[1:0] bitfield definitions 579 * preprocessor definitions for the bitfield "rx_fc_mode[1:0]". 580 * port="pif_rpb_rx_fc_mode_i[1:0]" 581 */ 582 583 /* register address for bitfield rx_fc_mode[1:0] */ 584 #define HW_ATL_RPB_RX_FC_MODE_ADR 0x00005700 585 /* bitmask for bitfield rx_fc_mode[1:0] */ 586 #define HW_ATL_RPB_RX_FC_MODE_MSK 0x00000030 587 /* inverted bitmask for bitfield rx_fc_mode[1:0] */ 588 #define HW_ATL_RPB_RX_FC_MODE_MSKN 0xffffffcf 589 /* lower bit position of bitfield rx_fc_mode[1:0] */ 590 #define HW_ATL_RPB_RX_FC_MODE_SHIFT 4 591 /* width of bitfield rx_fc_mode[1:0] */ 592 #define HW_ATL_RPB_RX_FC_MODE_WIDTH 2 593 /* default value of bitfield rx_fc_mode[1:0] */ 594 #define HW_ATL_RPB_RX_FC_MODE_DEFAULT 0x0 595 596 /* rx rx{b}_buf_size[8:0] bitfield definitions 597 * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]". 598 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 599 * port="pif_rpb_rx0_buf_size_i[8:0]" 600 */ 601 602 /* register address for bitfield rx{b}_buf_size[8:0] */ 603 #define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) (0x00005710 + (buffer) * 0x10) 604 /* bitmask for bitfield rx{b}_buf_size[8:0] */ 605 #define HW_ATL_RPB_RXBBUF_SIZE_MSK 0x000001ff 606 /* inverted bitmask for bitfield rx{b}_buf_size[8:0] */ 607 #define HW_ATL_RPB_RXBBUF_SIZE_MSKN 0xfffffe00 608 /* lower bit position of bitfield rx{b}_buf_size[8:0] */ 609 #define HW_ATL_RPB_RXBBUF_SIZE_SHIFT 0 610 /* width of bitfield rx{b}_buf_size[8:0] */ 611 #define HW_ATL_RPB_RXBBUF_SIZE_WIDTH 9 612 /* default value of bitfield rx{b}_buf_size[8:0] */ 613 #define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT 0x0 614 615 /* rx rx{b}_xoff_en bitfield definitions 616 * preprocessor definitions for the bitfield "rx{b}_xoff_en". 617 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 618 * port="pif_rpb_rx_xoff_en_i[0]" 619 */ 620 621 /* register address for bitfield rx{b}_xoff_en */ 622 #define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) (0x00005714 + (buffer) * 0x10) 623 /* bitmask for bitfield rx{b}_xoff_en */ 624 #define HW_ATL_RPB_RXBXOFF_EN_MSK 0x80000000 625 /* inverted bitmask for bitfield rx{b}_xoff_en */ 626 #define HW_ATL_RPB_RXBXOFF_EN_MSKN 0x7fffffff 627 /* lower bit position of bitfield rx{b}_xoff_en */ 628 #define HW_ATL_RPB_RXBXOFF_EN_SHIFT 31 629 /* width of bitfield rx{b}_xoff_en */ 630 #define HW_ATL_RPB_RXBXOFF_EN_WIDTH 1 631 /* default value of bitfield rx{b}_xoff_en */ 632 #define HW_ATL_RPB_RXBXOFF_EN_DEFAULT 0x0 633 634 /* rx l2_bc_thresh[f:0] bitfield definitions 635 * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]". 636 * port="pif_rpf_l2_bc_thresh_i[15:0]" 637 */ 638 639 /* register address for bitfield l2_bc_thresh[f:0] */ 640 #define HW_ATL_RPFL2BC_THRESH_ADR 0x00005100 641 /* bitmask for bitfield l2_bc_thresh[f:0] */ 642 #define HW_ATL_RPFL2BC_THRESH_MSK 0xffff0000 643 /* inverted bitmask for bitfield l2_bc_thresh[f:0] */ 644 #define HW_ATL_RPFL2BC_THRESH_MSKN 0x0000ffff 645 /* lower bit position of bitfield l2_bc_thresh[f:0] */ 646 #define HW_ATL_RPFL2BC_THRESH_SHIFT 16 647 /* width of bitfield l2_bc_thresh[f:0] */ 648 #define HW_ATL_RPFL2BC_THRESH_WIDTH 16 649 /* default value of bitfield l2_bc_thresh[f:0] */ 650 #define HW_ATL_RPFL2BC_THRESH_DEFAULT 0x0 651 652 /* rx l2_bc_en bitfield definitions 653 * preprocessor definitions for the bitfield "l2_bc_en". 654 * port="pif_rpf_l2_bc_en_i" 655 */ 656 657 /* register address for bitfield l2_bc_en */ 658 #define HW_ATL_RPFL2BC_EN_ADR 0x00005100 659 /* bitmask for bitfield l2_bc_en */ 660 #define HW_ATL_RPFL2BC_EN_MSK 0x00000001 661 /* inverted bitmask for bitfield l2_bc_en */ 662 #define HW_ATL_RPFL2BC_EN_MSKN 0xfffffffe 663 /* lower bit position of bitfield l2_bc_en */ 664 #define HW_ATL_RPFL2BC_EN_SHIFT 0 665 /* width of bitfield l2_bc_en */ 666 #define HW_ATL_RPFL2BC_EN_WIDTH 1 667 /* default value of bitfield l2_bc_en */ 668 #define HW_ATL_RPFL2BC_EN_DEFAULT 0x0 669 670 /* rx l2_bc_act[2:0] bitfield definitions 671 * preprocessor definitions for the bitfield "l2_bc_act[2:0]". 672 * port="pif_rpf_l2_bc_act_i[2:0]" 673 */ 674 675 /* register address for bitfield l2_bc_act[2:0] */ 676 #define HW_ATL_RPFL2BC_ACT_ADR 0x00005100 677 /* bitmask for bitfield l2_bc_act[2:0] */ 678 #define HW_ATL_RPFL2BC_ACT_MSK 0x00007000 679 /* inverted bitmask for bitfield l2_bc_act[2:0] */ 680 #define HW_ATL_RPFL2BC_ACT_MSKN 0xffff8fff 681 /* lower bit position of bitfield l2_bc_act[2:0] */ 682 #define HW_ATL_RPFL2BC_ACT_SHIFT 12 683 /* width of bitfield l2_bc_act[2:0] */ 684 #define HW_ATL_RPFL2BC_ACT_WIDTH 3 685 /* default value of bitfield l2_bc_act[2:0] */ 686 #define HW_ATL_RPFL2BC_ACT_DEFAULT 0x0 687 688 /* rx l2_mc_en{f} bitfield definitions 689 * preprocessor definitions for the bitfield "l2_mc_en{f}". 690 * parameter: filter {f} | stride size 0x4 | range [0, 7] 691 * port="pif_rpf_l2_mc_en_i[0]" 692 */ 693 694 /* register address for bitfield l2_mc_en{f} */ 695 #define HW_ATL_RPFL2MC_ENF_ADR(filter) (0x00005250 + (filter) * 0x4) 696 /* bitmask for bitfield l2_mc_en{f} */ 697 #define HW_ATL_RPFL2MC_ENF_MSK 0x80000000 698 /* inverted bitmask for bitfield l2_mc_en{f} */ 699 #define HW_ATL_RPFL2MC_ENF_MSKN 0x7fffffff 700 /* lower bit position of bitfield l2_mc_en{f} */ 701 #define HW_ATL_RPFL2MC_ENF_SHIFT 31 702 /* width of bitfield l2_mc_en{f} */ 703 #define HW_ATL_RPFL2MC_ENF_WIDTH 1 704 /* default value of bitfield l2_mc_en{f} */ 705 #define HW_ATL_RPFL2MC_ENF_DEFAULT 0x0 706 707 /* rx l2_promis_mode bitfield definitions 708 * preprocessor definitions for the bitfield "l2_promis_mode". 709 * port="pif_rpf_l2_promis_mode_i" 710 */ 711 712 /* register address for bitfield l2_promis_mode */ 713 #define HW_ATL_RPFL2PROMIS_MODE_ADR 0x00005100 714 /* bitmask for bitfield l2_promis_mode */ 715 #define HW_ATL_RPFL2PROMIS_MODE_MSK 0x00000008 716 /* inverted bitmask for bitfield l2_promis_mode */ 717 #define HW_ATL_RPFL2PROMIS_MODE_MSKN 0xfffffff7 718 /* lower bit position of bitfield l2_promis_mode */ 719 #define HW_ATL_RPFL2PROMIS_MODE_SHIFT 3 720 /* width of bitfield l2_promis_mode */ 721 #define HW_ATL_RPFL2PROMIS_MODE_WIDTH 1 722 /* default value of bitfield l2_promis_mode */ 723 #define HW_ATL_RPFL2PROMIS_MODE_DEFAULT 0x0 724 725 /* rx l2_uc_act{f}[2:0] bitfield definitions 726 * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]". 727 * parameter: filter {f} | stride size 0x8 | range [0, 37] 728 * port="pif_rpf_l2_uc_act0_i[2:0]" 729 */ 730 731 /* register address for bitfield l2_uc_act{f}[2:0] */ 732 #define HW_ATL_RPFL2UC_ACTF_ADR(filter) (0x00005114 + (filter) * 0x8) 733 /* bitmask for bitfield l2_uc_act{f}[2:0] */ 734 #define HW_ATL_RPFL2UC_ACTF_MSK 0x00070000 735 /* inverted bitmask for bitfield l2_uc_act{f}[2:0] */ 736 #define HW_ATL_RPFL2UC_ACTF_MSKN 0xfff8ffff 737 /* lower bit position of bitfield l2_uc_act{f}[2:0] */ 738 #define HW_ATL_RPFL2UC_ACTF_SHIFT 16 739 /* width of bitfield l2_uc_act{f}[2:0] */ 740 #define HW_ATL_RPFL2UC_ACTF_WIDTH 3 741 /* default value of bitfield l2_uc_act{f}[2:0] */ 742 #define HW_ATL_RPFL2UC_ACTF_DEFAULT 0x0 743 744 /* rx l2_uc_en{f} bitfield definitions 745 * preprocessor definitions for the bitfield "l2_uc_en{f}". 746 * parameter: filter {f} | stride size 0x8 | range [0, 37] 747 * port="pif_rpf_l2_uc_en_i[0]" 748 */ 749 750 /* register address for bitfield l2_uc_en{f} */ 751 #define HW_ATL_RPFL2UC_ENF_ADR(filter) (0x00005114 + (filter) * 0x8) 752 /* bitmask for bitfield l2_uc_en{f} */ 753 #define HW_ATL_RPFL2UC_ENF_MSK 0x80000000 754 /* inverted bitmask for bitfield l2_uc_en{f} */ 755 #define HW_ATL_RPFL2UC_ENF_MSKN 0x7fffffff 756 /* lower bit position of bitfield l2_uc_en{f} */ 757 #define HW_ATL_RPFL2UC_ENF_SHIFT 31 758 /* width of bitfield l2_uc_en{f} */ 759 #define HW_ATL_RPFL2UC_ENF_WIDTH 1 760 /* default value of bitfield l2_uc_en{f} */ 761 #define HW_ATL_RPFL2UC_ENF_DEFAULT 0x0 762 763 /* register address for bitfield l2_uc_da{f}_lsw[1f:0] */ 764 #define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) (0x00005110 + (filter) * 0x8) 765 /* register address for bitfield l2_uc_da{f}_msw[f:0] */ 766 #define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) (0x00005114 + (filter) * 0x8) 767 /* bitmask for bitfield l2_uc_da{f}_msw[f:0] */ 768 #define HW_ATL_RPFL2UC_DAFMSW_MSK 0x0000ffff 769 /* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */ 770 #define HW_ATL_RPFL2UC_DAFMSW_SHIFT 0 771 772 /* rx l2_mc_accept_all bitfield definitions 773 * Preprocessor definitions for the bitfield "l2_mc_accept_all". 774 * PORT="pif_rpf_l2_mc_all_accept_i" 775 */ 776 777 /* Register address for bitfield l2_mc_accept_all */ 778 #define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR 0x00005270 779 /* Bitmask for bitfield l2_mc_accept_all */ 780 #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK 0x00004000 781 /* Inverted bitmask for bitfield l2_mc_accept_all */ 782 #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN 0xFFFFBFFF 783 /* Lower bit position of bitfield l2_mc_accept_all */ 784 #define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT 14 785 /* Width of bitfield l2_mc_accept_all */ 786 #define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH 1 787 /* Default value of bitfield l2_mc_accept_all */ 788 #define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT 0x0 789 790 /* width of bitfield rx_tc_up{t}[2:0] */ 791 #define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH 3 792 /* default value of bitfield rx_tc_up{t}[2:0] */ 793 #define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT 0x0 794 795 /* rx rss_key_addr[4:0] bitfield definitions 796 * preprocessor definitions for the bitfield "rss_key_addr[4:0]". 797 * port="pif_rpf_rss_key_addr_i[4:0]" 798 */ 799 800 /* register address for bitfield rss_key_addr[4:0] */ 801 #define HW_ATL_RPF_RSS_KEY_ADDR_ADR 0x000054d0 802 /* bitmask for bitfield rss_key_addr[4:0] */ 803 #define HW_ATL_RPF_RSS_KEY_ADDR_MSK 0x0000001f 804 /* inverted bitmask for bitfield rss_key_addr[4:0] */ 805 #define HW_ATL_RPF_RSS_KEY_ADDR_MSKN 0xffffffe0 806 /* lower bit position of bitfield rss_key_addr[4:0] */ 807 #define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT 0 808 /* width of bitfield rss_key_addr[4:0] */ 809 #define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH 5 810 /* default value of bitfield rss_key_addr[4:0] */ 811 #define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT 0x0 812 813 /* rx rss_key_wr_data[1f:0] bitfield definitions 814 * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]". 815 * port="pif_rpf_rss_key_wr_data_i[31:0]" 816 */ 817 818 /* register address for bitfield rss_key_wr_data[1f:0] */ 819 #define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR 0x000054d4 820 /* bitmask for bitfield rss_key_wr_data[1f:0] */ 821 #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK 0xffffffff 822 /* inverted bitmask for bitfield rss_key_wr_data[1f:0] */ 823 #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN 0x00000000 824 /* lower bit position of bitfield rss_key_wr_data[1f:0] */ 825 #define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT 0 826 /* width of bitfield rss_key_wr_data[1f:0] */ 827 #define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH 32 828 /* default value of bitfield rss_key_wr_data[1f:0] */ 829 #define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT 0x0 830 831 /* rx rss_key_wr_en_i bitfield definitions 832 * preprocessor definitions for the bitfield "rss_key_wr_en_i". 833 * port="pif_rpf_rss_key_wr_en_i" 834 */ 835 836 /* register address for bitfield rss_key_wr_en_i */ 837 #define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR 0x000054d0 838 /* bitmask for bitfield rss_key_wr_en_i */ 839 #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK 0x00000020 840 /* inverted bitmask for bitfield rss_key_wr_en_i */ 841 #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN 0xffffffdf 842 /* lower bit position of bitfield rss_key_wr_en_i */ 843 #define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT 5 844 /* width of bitfield rss_key_wr_en_i */ 845 #define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH 1 846 /* default value of bitfield rss_key_wr_en_i */ 847 #define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT 0x0 848 849 /* rx rss_redir_addr[3:0] bitfield definitions 850 * preprocessor definitions for the bitfield "rss_redir_addr[3:0]". 851 * port="pif_rpf_rss_redir_addr_i[3:0]" 852 */ 853 854 /* register address for bitfield rss_redir_addr[3:0] */ 855 #define HW_ATL_RPF_RSS_REDIR_ADDR_ADR 0x000054e0 856 /* bitmask for bitfield rss_redir_addr[3:0] */ 857 #define HW_ATL_RPF_RSS_REDIR_ADDR_MSK 0x0000000f 858 /* inverted bitmask for bitfield rss_redir_addr[3:0] */ 859 #define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN 0xfffffff0 860 /* lower bit position of bitfield rss_redir_addr[3:0] */ 861 #define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT 0 862 /* width of bitfield rss_redir_addr[3:0] */ 863 #define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH 4 864 /* default value of bitfield rss_redir_addr[3:0] */ 865 #define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT 0x0 866 867 /* rx rss_redir_wr_data[f:0] bitfield definitions 868 * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]". 869 * port="pif_rpf_rss_redir_wr_data_i[15:0]" 870 */ 871 872 /* register address for bitfield rss_redir_wr_data[f:0] */ 873 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR 0x000054e4 874 /* bitmask for bitfield rss_redir_wr_data[f:0] */ 875 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK 0x0000ffff 876 /* inverted bitmask for bitfield rss_redir_wr_data[f:0] */ 877 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN 0xffff0000 878 /* lower bit position of bitfield rss_redir_wr_data[f:0] */ 879 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT 0 880 /* width of bitfield rss_redir_wr_data[f:0] */ 881 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH 16 882 /* default value of bitfield rss_redir_wr_data[f:0] */ 883 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT 0x0 884 885 /* rx rss_redir_wr_en_i bitfield definitions 886 * preprocessor definitions for the bitfield "rss_redir_wr_en_i". 887 * port="pif_rpf_rss_redir_wr_en_i" 888 */ 889 890 /* register address for bitfield rss_redir_wr_en_i */ 891 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR 0x000054e0 892 /* bitmask for bitfield rss_redir_wr_en_i */ 893 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK 0x00000010 894 /* inverted bitmask for bitfield rss_redir_wr_en_i */ 895 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN 0xffffffef 896 /* lower bit position of bitfield rss_redir_wr_en_i */ 897 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT 4 898 /* width of bitfield rss_redir_wr_en_i */ 899 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH 1 900 /* default value of bitfield rss_redir_wr_en_i */ 901 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT 0x0 902 903 /* rx tpo_rpf_sys_loopback bitfield definitions 904 * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback". 905 * port="pif_rpf_tpo_pkt_sys_lbk_i" 906 */ 907 908 /* register address for bitfield tpo_rpf_sys_loopback */ 909 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR 0x00005000 910 /* bitmask for bitfield tpo_rpf_sys_loopback */ 911 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK 0x00000100 912 /* inverted bitmask for bitfield tpo_rpf_sys_loopback */ 913 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN 0xfffffeff 914 /* lower bit position of bitfield tpo_rpf_sys_loopback */ 915 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT 8 916 /* width of bitfield tpo_rpf_sys_loopback */ 917 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH 1 918 /* default value of bitfield tpo_rpf_sys_loopback */ 919 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT 0x0 920 921 /* rx vl_inner_tpid[f:0] bitfield definitions 922 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]". 923 * port="pif_rpf_vl_inner_tpid_i[15:0]" 924 */ 925 926 /* register address for bitfield vl_inner_tpid[f:0] */ 927 #define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284 928 /* bitmask for bitfield vl_inner_tpid[f:0] */ 929 #define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff 930 /* inverted bitmask for bitfield vl_inner_tpid[f:0] */ 931 #define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000 932 /* lower bit position of bitfield vl_inner_tpid[f:0] */ 933 #define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0 934 /* width of bitfield vl_inner_tpid[f:0] */ 935 #define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16 936 /* default value of bitfield vl_inner_tpid[f:0] */ 937 #define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100 938 939 /* rx vl_outer_tpid[f:0] bitfield definitions 940 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]". 941 * port="pif_rpf_vl_outer_tpid_i[15:0]" 942 */ 943 944 /* register address for bitfield vl_outer_tpid[f:0] */ 945 #define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284 946 /* bitmask for bitfield vl_outer_tpid[f:0] */ 947 #define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000 948 /* inverted bitmask for bitfield vl_outer_tpid[f:0] */ 949 #define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff 950 /* lower bit position of bitfield vl_outer_tpid[f:0] */ 951 #define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16 952 /* width of bitfield vl_outer_tpid[f:0] */ 953 #define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16 954 /* default value of bitfield vl_outer_tpid[f:0] */ 955 #define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8 956 957 /* rx vl_promis_mode bitfield definitions 958 * preprocessor definitions for the bitfield "vl_promis_mode". 959 * port="pif_rpf_vl_promis_mode_i" 960 */ 961 962 /* register address for bitfield vl_promis_mode */ 963 #define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280 964 /* bitmask for bitfield vl_promis_mode */ 965 #define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002 966 /* inverted bitmask for bitfield vl_promis_mode */ 967 #define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd 968 /* lower bit position of bitfield vl_promis_mode */ 969 #define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1 970 /* width of bitfield vl_promis_mode */ 971 #define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1 972 /* default value of bitfield vl_promis_mode */ 973 #define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0 974 975 /* RX vl_accept_untagged_mode Bitfield Definitions 976 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode". 977 * PORT="pif_rpf_vl_accept_untagged_i" 978 */ 979 980 /* Register address for bitfield vl_accept_untagged_mode */ 981 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280 982 /* Bitmask for bitfield vl_accept_untagged_mode */ 983 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004 984 /* Inverted bitmask for bitfield vl_accept_untagged_mode */ 985 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB 986 /* Lower bit position of bitfield vl_accept_untagged_mode */ 987 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2 988 /* Width of bitfield vl_accept_untagged_mode */ 989 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1 990 /* Default value of bitfield vl_accept_untagged_mode */ 991 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0 992 993 /* rX vl_untagged_act[2:0] Bitfield Definitions 994 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]". 995 * PORT="pif_rpf_vl_untagged_act_i[2:0]" 996 */ 997 998 /* Register address for bitfield vl_untagged_act[2:0] */ 999 #define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280 1000 /* Bitmask for bitfield vl_untagged_act[2:0] */ 1001 #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038 1002 /* Inverted bitmask for bitfield vl_untagged_act[2:0] */ 1003 #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7 1004 /* Lower bit position of bitfield vl_untagged_act[2:0] */ 1005 #define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3 1006 /* Width of bitfield vl_untagged_act[2:0] */ 1007 #define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3 1008 /* Default value of bitfield vl_untagged_act[2:0] */ 1009 #define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0 1010 1011 /* RX vl_en{F} Bitfield Definitions 1012 * Preprocessor definitions for the bitfield "vl_en{F}". 1013 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1014 * PORT="pif_rpf_vl_en_i[0]" 1015 */ 1016 1017 /* Register address for bitfield vl_en{F} */ 1018 #define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1019 /* Bitmask for bitfield vl_en{F} */ 1020 #define HW_ATL_RPF_VL_EN_F_MSK 0x80000000 1021 /* Inverted bitmask for bitfield vl_en{F} */ 1022 #define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF 1023 /* Lower bit position of bitfield vl_en{F} */ 1024 #define HW_ATL_RPF_VL_EN_F_SHIFT 31 1025 /* Width of bitfield vl_en{F} */ 1026 #define HW_ATL_RPF_VL_EN_F_WIDTH 1 1027 /* Default value of bitfield vl_en{F} */ 1028 #define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0 1029 1030 /* RX vl_act{F}[2:0] Bitfield Definitions 1031 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]". 1032 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1033 * PORT="pif_rpf_vl_act0_i[2:0]" 1034 */ 1035 1036 /* Register address for bitfield vl_act{F}[2:0] */ 1037 #define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1038 /* Bitmask for bitfield vl_act{F}[2:0] */ 1039 #define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000 1040 /* Inverted bitmask for bitfield vl_act{F}[2:0] */ 1041 #define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF 1042 /* Lower bit position of bitfield vl_act{F}[2:0] */ 1043 #define HW_ATL_RPF_VL_ACT_F_SHIFT 16 1044 /* Width of bitfield vl_act{F}[2:0] */ 1045 #define HW_ATL_RPF_VL_ACT_F_WIDTH 3 1046 /* Default value of bitfield vl_act{F}[2:0] */ 1047 #define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0 1048 1049 /* RX vl_id{F}[B:0] Bitfield Definitions 1050 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]". 1051 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1052 * PORT="pif_rpf_vl_id0_i[11:0]" 1053 */ 1054 1055 /* Register address for bitfield vl_id{F}[B:0] */ 1056 #define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1057 /* Bitmask for bitfield vl_id{F}[B:0] */ 1058 #define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF 1059 /* Inverted bitmask for bitfield vl_id{F}[B:0] */ 1060 #define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000 1061 /* Lower bit position of bitfield vl_id{F}[B:0] */ 1062 #define HW_ATL_RPF_VL_ID_F_SHIFT 0 1063 /* Width of bitfield vl_id{F}[B:0] */ 1064 #define HW_ATL_RPF_VL_ID_F_WIDTH 12 1065 /* Default value of bitfield vl_id{F}[B:0] */ 1066 #define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0 1067 1068 /* RX et_en{F} Bitfield Definitions 1069 * Preprocessor definitions for the bitfield "et_en{F}". 1070 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1071 * PORT="pif_rpf_et_en_i[0]" 1072 */ 1073 1074 /* Register address for bitfield et_en{F} */ 1075 #define HW_ATL_RPF_ET_EN_F_ADR(filter) (0x00005300 + (filter) * 0x4) 1076 /* Bitmask for bitfield et_en{F} */ 1077 #define HW_ATL_RPF_ET_EN_F_MSK 0x80000000 1078 /* Inverted bitmask for bitfield et_en{F} */ 1079 #define HW_ATL_RPF_ET_EN_F_MSKN 0x7FFFFFFF 1080 /* Lower bit position of bitfield et_en{F} */ 1081 #define HW_ATL_RPF_ET_EN_F_SHIFT 31 1082 /* Width of bitfield et_en{F} */ 1083 #define HW_ATL_RPF_ET_EN_F_WIDTH 1 1084 /* Default value of bitfield et_en{F} */ 1085 #define HW_ATL_RPF_ET_EN_F_DEFAULT 0x0 1086 1087 /* rx et_en{f} bitfield definitions 1088 * preprocessor definitions for the bitfield "et_en{f}". 1089 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1090 * port="pif_rpf_et_en_i[0]" 1091 */ 1092 1093 /* register address for bitfield et_en{f} */ 1094 #define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4) 1095 /* bitmask for bitfield et_en{f} */ 1096 #define HW_ATL_RPF_ET_ENF_MSK 0x80000000 1097 /* inverted bitmask for bitfield et_en{f} */ 1098 #define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff 1099 /* lower bit position of bitfield et_en{f} */ 1100 #define HW_ATL_RPF_ET_ENF_SHIFT 31 1101 /* width of bitfield et_en{f} */ 1102 #define HW_ATL_RPF_ET_ENF_WIDTH 1 1103 /* default value of bitfield et_en{f} */ 1104 #define HW_ATL_RPF_ET_ENF_DEFAULT 0x0 1105 1106 /* rx et_up{f}_en bitfield definitions 1107 * preprocessor definitions for the bitfield "et_up{f}_en". 1108 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1109 * port="pif_rpf_et_up_en_i[0]" 1110 */ 1111 1112 /* register address for bitfield et_up{f}_en */ 1113 #define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4) 1114 /* bitmask for bitfield et_up{f}_en */ 1115 #define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000 1116 /* inverted bitmask for bitfield et_up{f}_en */ 1117 #define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff 1118 /* lower bit position of bitfield et_up{f}_en */ 1119 #define HW_ATL_RPF_ET_UPFEN_SHIFT 30 1120 /* width of bitfield et_up{f}_en */ 1121 #define HW_ATL_RPF_ET_UPFEN_WIDTH 1 1122 /* default value of bitfield et_up{f}_en */ 1123 #define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0 1124 1125 /* rx et_rxq{f}_en bitfield definitions 1126 * preprocessor definitions for the bitfield "et_rxq{f}_en". 1127 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1128 * port="pif_rpf_et_rxq_en_i[0]" 1129 */ 1130 1131 /* register address for bitfield et_rxq{f}_en */ 1132 #define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4) 1133 /* bitmask for bitfield et_rxq{f}_en */ 1134 #define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000 1135 /* inverted bitmask for bitfield et_rxq{f}_en */ 1136 #define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff 1137 /* lower bit position of bitfield et_rxq{f}_en */ 1138 #define HW_ATL_RPF_ET_RXQFEN_SHIFT 29 1139 /* width of bitfield et_rxq{f}_en */ 1140 #define HW_ATL_RPF_ET_RXQFEN_WIDTH 1 1141 /* default value of bitfield et_rxq{f}_en */ 1142 #define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0 1143 1144 /* rx et_up{f}[2:0] bitfield definitions 1145 * preprocessor definitions for the bitfield "et_up{f}[2:0]". 1146 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1147 * port="pif_rpf_et_up0_i[2:0]" 1148 */ 1149 1150 /* register address for bitfield et_up{f}[2:0] */ 1151 #define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4) 1152 /* bitmask for bitfield et_up{f}[2:0] */ 1153 #define HW_ATL_RPF_ET_UPF_MSK 0x1c000000 1154 /* inverted bitmask for bitfield et_up{f}[2:0] */ 1155 #define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff 1156 /* lower bit position of bitfield et_up{f}[2:0] */ 1157 #define HW_ATL_RPF_ET_UPF_SHIFT 26 1158 /* width of bitfield et_up{f}[2:0] */ 1159 #define HW_ATL_RPF_ET_UPF_WIDTH 3 1160 /* default value of bitfield et_up{f}[2:0] */ 1161 #define HW_ATL_RPF_ET_UPF_DEFAULT 0x0 1162 1163 /* rx et_rxq{f}[4:0] bitfield definitions 1164 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]". 1165 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1166 * port="pif_rpf_et_rxq0_i[4:0]" 1167 */ 1168 1169 /* register address for bitfield et_rxq{f}[4:0] */ 1170 #define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) 1171 /* bitmask for bitfield et_rxq{f}[4:0] */ 1172 #define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000 1173 /* inverted bitmask for bitfield et_rxq{f}[4:0] */ 1174 #define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff 1175 /* lower bit position of bitfield et_rxq{f}[4:0] */ 1176 #define HW_ATL_RPF_ET_RXQF_SHIFT 20 1177 /* width of bitfield et_rxq{f}[4:0] */ 1178 #define HW_ATL_RPF_ET_RXQF_WIDTH 5 1179 /* default value of bitfield et_rxq{f}[4:0] */ 1180 #define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0 1181 1182 /* rx et_mng_rxq{f} bitfield definitions 1183 * preprocessor definitions for the bitfield "et_mng_rxq{f}". 1184 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1185 * port="pif_rpf_et_mng_rxq_i[0]" 1186 */ 1187 1188 /* register address for bitfield et_mng_rxq{f} */ 1189 #define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) 1190 /* bitmask for bitfield et_mng_rxq{f} */ 1191 #define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000 1192 /* inverted bitmask for bitfield et_mng_rxq{f} */ 1193 #define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff 1194 /* lower bit position of bitfield et_mng_rxq{f} */ 1195 #define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19 1196 /* width of bitfield et_mng_rxq{f} */ 1197 #define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1 1198 /* default value of bitfield et_mng_rxq{f} */ 1199 #define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0 1200 1201 /* rx et_act{f}[2:0] bitfield definitions 1202 * preprocessor definitions for the bitfield "et_act{f}[2:0]". 1203 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1204 * port="pif_rpf_et_act0_i[2:0]" 1205 */ 1206 1207 /* register address for bitfield et_act{f}[2:0] */ 1208 #define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4) 1209 /* bitmask for bitfield et_act{f}[2:0] */ 1210 #define HW_ATL_RPF_ET_ACTF_MSK 0x00070000 1211 /* inverted bitmask for bitfield et_act{f}[2:0] */ 1212 #define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff 1213 /* lower bit position of bitfield et_act{f}[2:0] */ 1214 #define HW_ATL_RPF_ET_ACTF_SHIFT 16 1215 /* width of bitfield et_act{f}[2:0] */ 1216 #define HW_ATL_RPF_ET_ACTF_WIDTH 3 1217 /* default value of bitfield et_act{f}[2:0] */ 1218 #define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0 1219 1220 /* rx et_val{f}[f:0] bitfield definitions 1221 * preprocessor definitions for the bitfield "et_val{f}[f:0]". 1222 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1223 * port="pif_rpf_et_val0_i[15:0]" 1224 */ 1225 1226 /* register address for bitfield et_val{f}[f:0] */ 1227 #define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4) 1228 /* bitmask for bitfield et_val{f}[f:0] */ 1229 #define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff 1230 /* inverted bitmask for bitfield et_val{f}[f:0] */ 1231 #define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000 1232 /* lower bit position of bitfield et_val{f}[f:0] */ 1233 #define HW_ATL_RPF_ET_VALF_SHIFT 0 1234 /* width of bitfield et_val{f}[f:0] */ 1235 #define HW_ATL_RPF_ET_VALF_WIDTH 16 1236 /* default value of bitfield et_val{f}[f:0] */ 1237 #define HW_ATL_RPF_ET_VALF_DEFAULT 0x0 1238 1239 /* rx ipv4_chk_en bitfield definitions 1240 * preprocessor definitions for the bitfield "ipv4_chk_en". 1241 * port="pif_rpo_ipv4_chk_en_i" 1242 */ 1243 1244 /* register address for bitfield ipv4_chk_en */ 1245 #define HW_ATL_RPO_IPV4CHK_EN_ADR 0x00005580 1246 /* bitmask for bitfield ipv4_chk_en */ 1247 #define HW_ATL_RPO_IPV4CHK_EN_MSK 0x00000002 1248 /* inverted bitmask for bitfield ipv4_chk_en */ 1249 #define HW_ATL_RPO_IPV4CHK_EN_MSKN 0xfffffffd 1250 /* lower bit position of bitfield ipv4_chk_en */ 1251 #define HW_ATL_RPO_IPV4CHK_EN_SHIFT 1 1252 /* width of bitfield ipv4_chk_en */ 1253 #define HW_ATL_RPO_IPV4CHK_EN_WIDTH 1 1254 /* default value of bitfield ipv4_chk_en */ 1255 #define HW_ATL_RPO_IPV4CHK_EN_DEFAULT 0x0 1256 1257 /* rx desc{d}_vl_strip bitfield definitions 1258 * preprocessor definitions for the bitfield "desc{d}_vl_strip". 1259 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 1260 * port="pif_rpo_desc_vl_strip_i[0]" 1261 */ 1262 1263 /* register address for bitfield desc{d}_vl_strip */ 1264 #define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) \ 1265 (0x00005b08 + (descriptor) * 0x20) 1266 /* bitmask for bitfield desc{d}_vl_strip */ 1267 #define HW_ATL_RPO_DESCDVL_STRIP_MSK 0x20000000 1268 /* inverted bitmask for bitfield desc{d}_vl_strip */ 1269 #define HW_ATL_RPO_DESCDVL_STRIP_MSKN 0xdfffffff 1270 /* lower bit position of bitfield desc{d}_vl_strip */ 1271 #define HW_ATL_RPO_DESCDVL_STRIP_SHIFT 29 1272 /* width of bitfield desc{d}_vl_strip */ 1273 #define HW_ATL_RPO_DESCDVL_STRIP_WIDTH 1 1274 /* default value of bitfield desc{d}_vl_strip */ 1275 #define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT 0x0 1276 1277 /* rx l4_chk_en bitfield definitions 1278 * preprocessor definitions for the bitfield "l4_chk_en". 1279 * port="pif_rpo_l4_chk_en_i" 1280 */ 1281 1282 /* register address for bitfield l4_chk_en */ 1283 #define HW_ATL_RPOL4CHK_EN_ADR 0x00005580 1284 /* bitmask for bitfield l4_chk_en */ 1285 #define HW_ATL_RPOL4CHK_EN_MSK 0x00000001 1286 /* inverted bitmask for bitfield l4_chk_en */ 1287 #define HW_ATL_RPOL4CHK_EN_MSKN 0xfffffffe 1288 /* lower bit position of bitfield l4_chk_en */ 1289 #define HW_ATL_RPOL4CHK_EN_SHIFT 0 1290 /* width of bitfield l4_chk_en */ 1291 #define HW_ATL_RPOL4CHK_EN_WIDTH 1 1292 /* default value of bitfield l4_chk_en */ 1293 #define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0 1294 1295 /* rx reg_res_dsbl bitfield definitions 1296 * preprocessor definitions for the bitfield "reg_res_dsbl". 1297 * port="pif_rx_reg_res_dsbl_i" 1298 */ 1299 1300 /* register address for bitfield reg_res_dsbl */ 1301 #define HW_ATL_RX_REG_RES_DSBL_ADR 0x00005000 1302 /* bitmask for bitfield reg_res_dsbl */ 1303 #define HW_ATL_RX_REG_RES_DSBL_MSK 0x20000000 1304 /* inverted bitmask for bitfield reg_res_dsbl */ 1305 #define HW_ATL_RX_REG_RES_DSBL_MSKN 0xdfffffff 1306 /* lower bit position of bitfield reg_res_dsbl */ 1307 #define HW_ATL_RX_REG_RES_DSBL_SHIFT 29 1308 /* width of bitfield reg_res_dsbl */ 1309 #define HW_ATL_RX_REG_RES_DSBL_WIDTH 1 1310 /* default value of bitfield reg_res_dsbl */ 1311 #define HW_ATL_RX_REG_RES_DSBL_DEFAULT 0x1 1312 1313 /* tx dca{d}_cpuid[7:0] bitfield definitions 1314 * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]". 1315 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1316 * port="pif_tdm_dca0_cpuid_i[7:0]" 1317 */ 1318 1319 /* register address for bitfield dca{d}_cpuid[7:0] */ 1320 #define HW_ATL_TDM_DCADCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) 1321 /* bitmask for bitfield dca{d}_cpuid[7:0] */ 1322 #define HW_ATL_TDM_DCADCPUID_MSK 0x000000ff 1323 /* inverted bitmask for bitfield dca{d}_cpuid[7:0] */ 1324 #define HW_ATL_TDM_DCADCPUID_MSKN 0xffffff00 1325 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ 1326 #define HW_ATL_TDM_DCADCPUID_SHIFT 0 1327 /* width of bitfield dca{d}_cpuid[7:0] */ 1328 #define HW_ATL_TDM_DCADCPUID_WIDTH 8 1329 /* default value of bitfield dca{d}_cpuid[7:0] */ 1330 #define HW_ATL_TDM_DCADCPUID_DEFAULT 0x0 1331 1332 /* tx lso_en[1f:0] bitfield definitions 1333 * preprocessor definitions for the bitfield "lso_en[1f:0]". 1334 * port="pif_tdm_lso_en_i[31:0]" 1335 */ 1336 1337 /* register address for bitfield lso_en[1f:0] */ 1338 #define HW_ATL_TDM_LSO_EN_ADR 0x00007810 1339 /* bitmask for bitfield lso_en[1f:0] */ 1340 #define HW_ATL_TDM_LSO_EN_MSK 0xffffffff 1341 /* inverted bitmask for bitfield lso_en[1f:0] */ 1342 #define HW_ATL_TDM_LSO_EN_MSKN 0x00000000 1343 /* lower bit position of bitfield lso_en[1f:0] */ 1344 #define HW_ATL_TDM_LSO_EN_SHIFT 0 1345 /* width of bitfield lso_en[1f:0] */ 1346 #define HW_ATL_TDM_LSO_EN_WIDTH 32 1347 /* default value of bitfield lso_en[1f:0] */ 1348 #define HW_ATL_TDM_LSO_EN_DEFAULT 0x0 1349 1350 /* tx dca_en bitfield definitions 1351 * preprocessor definitions for the bitfield "dca_en". 1352 * port="pif_tdm_dca_en_i" 1353 */ 1354 1355 /* register address for bitfield dca_en */ 1356 #define HW_ATL_TDM_DCA_EN_ADR 0x00008480 1357 /* bitmask for bitfield dca_en */ 1358 #define HW_ATL_TDM_DCA_EN_MSK 0x80000000 1359 /* inverted bitmask for bitfield dca_en */ 1360 #define HW_ATL_TDM_DCA_EN_MSKN 0x7fffffff 1361 /* lower bit position of bitfield dca_en */ 1362 #define HW_ATL_TDM_DCA_EN_SHIFT 31 1363 /* width of bitfield dca_en */ 1364 #define HW_ATL_TDM_DCA_EN_WIDTH 1 1365 /* default value of bitfield dca_en */ 1366 #define HW_ATL_TDM_DCA_EN_DEFAULT 0x1 1367 1368 /* tx dca_mode[3:0] bitfield definitions 1369 * preprocessor definitions for the bitfield "dca_mode[3:0]". 1370 * port="pif_tdm_dca_mode_i[3:0]" 1371 */ 1372 1373 /* register address for bitfield dca_mode[3:0] */ 1374 #define HW_ATL_TDM_DCA_MODE_ADR 0x00008480 1375 /* bitmask for bitfield dca_mode[3:0] */ 1376 #define HW_ATL_TDM_DCA_MODE_MSK 0x0000000f 1377 /* inverted bitmask for bitfield dca_mode[3:0] */ 1378 #define HW_ATL_TDM_DCA_MODE_MSKN 0xfffffff0 1379 /* lower bit position of bitfield dca_mode[3:0] */ 1380 #define HW_ATL_TDM_DCA_MODE_SHIFT 0 1381 /* width of bitfield dca_mode[3:0] */ 1382 #define HW_ATL_TDM_DCA_MODE_WIDTH 4 1383 /* default value of bitfield dca_mode[3:0] */ 1384 #define HW_ATL_TDM_DCA_MODE_DEFAULT 0x0 1385 1386 /* tx dca{d}_desc_en bitfield definitions 1387 * preprocessor definitions for the bitfield "dca{d}_desc_en". 1388 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1389 * port="pif_tdm_dca_desc_en_i[0]" 1390 */ 1391 1392 /* register address for bitfield dca{d}_desc_en */ 1393 #define HW_ATL_TDM_DCADDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) 1394 /* bitmask for bitfield dca{d}_desc_en */ 1395 #define HW_ATL_TDM_DCADDESC_EN_MSK 0x80000000 1396 /* inverted bitmask for bitfield dca{d}_desc_en */ 1397 #define HW_ATL_TDM_DCADDESC_EN_MSKN 0x7fffffff 1398 /* lower bit position of bitfield dca{d}_desc_en */ 1399 #define HW_ATL_TDM_DCADDESC_EN_SHIFT 31 1400 /* width of bitfield dca{d}_desc_en */ 1401 #define HW_ATL_TDM_DCADDESC_EN_WIDTH 1 1402 /* default value of bitfield dca{d}_desc_en */ 1403 #define HW_ATL_TDM_DCADDESC_EN_DEFAULT 0x0 1404 1405 /* tx desc{d}_en bitfield definitions 1406 * preprocessor definitions for the bitfield "desc{d}_en". 1407 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1408 * port="pif_tdm_desc_en_i[0]" 1409 */ 1410 1411 /* register address for bitfield desc{d}_en */ 1412 #define HW_ATL_TDM_DESCDEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) 1413 /* bitmask for bitfield desc{d}_en */ 1414 #define HW_ATL_TDM_DESCDEN_MSK 0x80000000 1415 /* inverted bitmask for bitfield desc{d}_en */ 1416 #define HW_ATL_TDM_DESCDEN_MSKN 0x7fffffff 1417 /* lower bit position of bitfield desc{d}_en */ 1418 #define HW_ATL_TDM_DESCDEN_SHIFT 31 1419 /* width of bitfield desc{d}_en */ 1420 #define HW_ATL_TDM_DESCDEN_WIDTH 1 1421 /* default value of bitfield desc{d}_en */ 1422 #define HW_ATL_TDM_DESCDEN_DEFAULT 0x0 1423 1424 /* tx desc{d}_hd[c:0] bitfield definitions 1425 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 1426 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1427 * port="tdm_pif_desc0_hd_o[12:0]" 1428 */ 1429 1430 /* register address for bitfield desc{d}_hd[c:0] */ 1431 #define HW_ATL_TDM_DESCDHD_ADR(descriptor) (0x00007c0c + (descriptor) * 0x40) 1432 /* bitmask for bitfield desc{d}_hd[c:0] */ 1433 #define HW_ATL_TDM_DESCDHD_MSK 0x00001fff 1434 /* inverted bitmask for bitfield desc{d}_hd[c:0] */ 1435 #define HW_ATL_TDM_DESCDHD_MSKN 0xffffe000 1436 /* lower bit position of bitfield desc{d}_hd[c:0] */ 1437 #define HW_ATL_TDM_DESCDHD_SHIFT 0 1438 /* width of bitfield desc{d}_hd[c:0] */ 1439 #define HW_ATL_TDM_DESCDHD_WIDTH 13 1440 1441 /* tx desc{d}_len[9:0] bitfield definitions 1442 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 1443 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1444 * port="pif_tdm_desc0_len_i[9:0]" 1445 */ 1446 1447 /* register address for bitfield desc{d}_len[9:0] */ 1448 #define HW_ATL_TDM_DESCDLEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) 1449 /* bitmask for bitfield desc{d}_len[9:0] */ 1450 #define HW_ATL_TDM_DESCDLEN_MSK 0x00001ff8 1451 /* inverted bitmask for bitfield desc{d}_len[9:0] */ 1452 #define HW_ATL_TDM_DESCDLEN_MSKN 0xffffe007 1453 /* lower bit position of bitfield desc{d}_len[9:0] */ 1454 #define HW_ATL_TDM_DESCDLEN_SHIFT 3 1455 /* width of bitfield desc{d}_len[9:0] */ 1456 #define HW_ATL_TDM_DESCDLEN_WIDTH 10 1457 /* default value of bitfield desc{d}_len[9:0] */ 1458 #define HW_ATL_TDM_DESCDLEN_DEFAULT 0x0 1459 1460 /* tx int_desc_wrb_en bitfield definitions 1461 * preprocessor definitions for the bitfield "int_desc_wrb_en". 1462 * port="pif_tdm_int_desc_wrb_en_i" 1463 */ 1464 1465 /* register address for bitfield int_desc_wrb_en */ 1466 #define HW_ATL_TDM_INT_DESC_WRB_EN_ADR 0x00007b40 1467 /* bitmask for bitfield int_desc_wrb_en */ 1468 #define HW_ATL_TDM_INT_DESC_WRB_EN_MSK 0x00000002 1469 /* inverted bitmask for bitfield int_desc_wrb_en */ 1470 #define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN 0xfffffffd 1471 /* lower bit position of bitfield int_desc_wrb_en */ 1472 #define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT 1 1473 /* width of bitfield int_desc_wrb_en */ 1474 #define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH 1 1475 /* default value of bitfield int_desc_wrb_en */ 1476 #define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT 0x0 1477 1478 /* tx desc{d}_wrb_thresh[6:0] bitfield definitions 1479 * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]". 1480 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1481 * port="pif_tdm_desc0_wrb_thresh_i[6:0]" 1482 */ 1483 1484 /* register address for bitfield desc{d}_wrb_thresh[6:0] */ 1485 #define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) \ 1486 (0x00007c18 + (descriptor) * 0x40) 1487 /* bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1488 #define HW_ATL_TDM_DESCDWRB_THRESH_MSK 0x00007f00 1489 /* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1490 #define HW_ATL_TDM_DESCDWRB_THRESH_MSKN 0xffff80ff 1491 /* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */ 1492 #define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT 8 1493 /* width of bitfield desc{d}_wrb_thresh[6:0] */ 1494 #define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH 7 1495 /* default value of bitfield desc{d}_wrb_thresh[6:0] */ 1496 #define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT 0x0 1497 1498 /* tx lso_tcp_flag_first[b:0] bitfield definitions 1499 * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]". 1500 * port="pif_thm_lso_tcp_flag_first_i[11:0]" 1501 */ 1502 1503 /* register address for bitfield lso_tcp_flag_first[b:0] */ 1504 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR 0x00007820 1505 /* bitmask for bitfield lso_tcp_flag_first[b:0] */ 1506 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK 0x00000fff 1507 /* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */ 1508 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN 0xfffff000 1509 /* lower bit position of bitfield lso_tcp_flag_first[b:0] */ 1510 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT 0 1511 /* width of bitfield lso_tcp_flag_first[b:0] */ 1512 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH 12 1513 /* default value of bitfield lso_tcp_flag_first[b:0] */ 1514 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT 0x0 1515 1516 /* tx lso_tcp_flag_last[b:0] bitfield definitions 1517 * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]". 1518 * port="pif_thm_lso_tcp_flag_last_i[11:0]" 1519 */ 1520 1521 /* register address for bitfield lso_tcp_flag_last[b:0] */ 1522 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR 0x00007824 1523 /* bitmask for bitfield lso_tcp_flag_last[b:0] */ 1524 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK 0x00000fff 1525 /* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */ 1526 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN 0xfffff000 1527 /* lower bit position of bitfield lso_tcp_flag_last[b:0] */ 1528 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT 0 1529 /* width of bitfield lso_tcp_flag_last[b:0] */ 1530 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH 12 1531 /* default value of bitfield lso_tcp_flag_last[b:0] */ 1532 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT 0x0 1533 1534 /* tx lso_tcp_flag_mid[b:0] bitfield definitions 1535 * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]". 1536 * port="pif_thm_lso_tcp_flag_mid_i[11:0]" 1537 */ 1538 1539 /* Register address for bitfield lro_rsc_max[1F:0] */ 1540 #define HW_ATL_RPO_LRO_RSC_MAX_ADR 0x00005598 1541 /* Bitmask for bitfield lro_rsc_max[1F:0] */ 1542 #define HW_ATL_RPO_LRO_RSC_MAX_MSK 0xFFFFFFFF 1543 /* Inverted bitmask for bitfield lro_rsc_max[1F:0] */ 1544 #define HW_ATL_RPO_LRO_RSC_MAX_MSKN 0x00000000 1545 /* Lower bit position of bitfield lro_rsc_max[1F:0] */ 1546 #define HW_ATL_RPO_LRO_RSC_MAX_SHIFT 0 1547 /* Width of bitfield lro_rsc_max[1F:0] */ 1548 #define HW_ATL_RPO_LRO_RSC_MAX_WIDTH 32 1549 /* Default value of bitfield lro_rsc_max[1F:0] */ 1550 #define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT 0x0 1551 1552 /* RX lro_en[1F:0] Bitfield Definitions 1553 * Preprocessor definitions for the bitfield "lro_en[1F:0]". 1554 * PORT="pif_rpo_lro_en_i[31:0]" 1555 */ 1556 1557 /* Register address for bitfield lro_en[1F:0] */ 1558 #define HW_ATL_RPO_LRO_EN_ADR 0x00005590 1559 /* Bitmask for bitfield lro_en[1F:0] */ 1560 #define HW_ATL_RPO_LRO_EN_MSK 0xFFFFFFFF 1561 /* Inverted bitmask for bitfield lro_en[1F:0] */ 1562 #define HW_ATL_RPO_LRO_EN_MSKN 0x00000000 1563 /* Lower bit position of bitfield lro_en[1F:0] */ 1564 #define HW_ATL_RPO_LRO_EN_SHIFT 0 1565 /* Width of bitfield lro_en[1F:0] */ 1566 #define HW_ATL_RPO_LRO_EN_WIDTH 32 1567 /* Default value of bitfield lro_en[1F:0] */ 1568 #define HW_ATL_RPO_LRO_EN_DEFAULT 0x0 1569 1570 /* RX lro_ptopt_en Bitfield Definitions 1571 * Preprocessor definitions for the bitfield "lro_ptopt_en". 1572 * PORT="pif_rpo_lro_ptopt_en_i" 1573 */ 1574 1575 /* Register address for bitfield lro_ptopt_en */ 1576 #define HW_ATL_RPO_LRO_PTOPT_EN_ADR 0x00005594 1577 /* Bitmask for bitfield lro_ptopt_en */ 1578 #define HW_ATL_RPO_LRO_PTOPT_EN_MSK 0x00008000 1579 /* Inverted bitmask for bitfield lro_ptopt_en */ 1580 #define HW_ATL_RPO_LRO_PTOPT_EN_MSKN 0xFFFF7FFF 1581 /* Lower bit position of bitfield lro_ptopt_en */ 1582 #define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT 15 1583 /* Width of bitfield lro_ptopt_en */ 1584 #define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH 1 1585 /* Default value of bitfield lro_ptopt_en */ 1586 #define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT 0x1 1587 1588 /* RX lro_q_ses_lmt Bitfield Definitions 1589 * Preprocessor definitions for the bitfield "lro_q_ses_lmt". 1590 * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]" 1591 */ 1592 1593 /* Register address for bitfield lro_q_ses_lmt */ 1594 #define HW_ATL_RPO_LRO_QSES_LMT_ADR 0x00005594 1595 /* Bitmask for bitfield lro_q_ses_lmt */ 1596 #define HW_ATL_RPO_LRO_QSES_LMT_MSK 0x00003000 1597 /* Inverted bitmask for bitfield lro_q_ses_lmt */ 1598 #define HW_ATL_RPO_LRO_QSES_LMT_MSKN 0xFFFFCFFF 1599 /* Lower bit position of bitfield lro_q_ses_lmt */ 1600 #define HW_ATL_RPO_LRO_QSES_LMT_SHIFT 12 1601 /* Width of bitfield lro_q_ses_lmt */ 1602 #define HW_ATL_RPO_LRO_QSES_LMT_WIDTH 2 1603 /* Default value of bitfield lro_q_ses_lmt */ 1604 #define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT 0x1 1605 1606 /* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions 1607 * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]". 1608 * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]" 1609 */ 1610 1611 /* Register address for bitfield lro_tot_dsc_lmt[1:0] */ 1612 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR 0x00005594 1613 /* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1614 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK 0x00000060 1615 /* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1616 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN 0xFFFFFF9F 1617 /* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */ 1618 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT 5 1619 /* Width of bitfield lro_tot_dsc_lmt[1:0] */ 1620 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH 2 1621 /* Default value of bitfield lro_tot_dsc_lmt[1:0] */ 1622 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT 0x1 1623 1624 /* RX lro_pkt_min[4:0] Bitfield Definitions 1625 * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]". 1626 * PORT="pif_rpo_lro_pkt_min_i[4:0]" 1627 */ 1628 1629 /* Register address for bitfield lro_pkt_min[4:0] */ 1630 #define HW_ATL_RPO_LRO_PKT_MIN_ADR 0x00005594 1631 /* Bitmask for bitfield lro_pkt_min[4:0] */ 1632 #define HW_ATL_RPO_LRO_PKT_MIN_MSK 0x0000001F 1633 /* Inverted bitmask for bitfield lro_pkt_min[4:0] */ 1634 #define HW_ATL_RPO_LRO_PKT_MIN_MSKN 0xFFFFFFE0 1635 /* Lower bit position of bitfield lro_pkt_min[4:0] */ 1636 #define HW_ATL_RPO_LRO_PKT_MIN_SHIFT 0 1637 /* Width of bitfield lro_pkt_min[4:0] */ 1638 #define HW_ATL_RPO_LRO_PKT_MIN_WIDTH 5 1639 /* Default value of bitfield lro_pkt_min[4:0] */ 1640 #define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT 0x8 1641 1642 /* Width of bitfield lro{L}_des_max[1:0] */ 1643 #define HW_ATL_RPO_LRO_LDES_MAX_WIDTH 2 1644 /* Default value of bitfield lro{L}_des_max[1:0] */ 1645 #define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT 0x0 1646 1647 /* RX lro_tb_div[11:0] Bitfield Definitions 1648 * Preprocessor definitions for the bitfield "lro_tb_div[11:0]". 1649 * PORT="pif_rpo_lro_tb_div_i[11:0]" 1650 */ 1651 1652 /* Register address for bitfield lro_tb_div[11:0] */ 1653 #define HW_ATL_RPO_LRO_TB_DIV_ADR 0x00005620 1654 /* Bitmask for bitfield lro_tb_div[11:0] */ 1655 #define HW_ATL_RPO_LRO_TB_DIV_MSK 0xFFF00000 1656 /* Inverted bitmask for bitfield lro_tb_div[11:0] */ 1657 #define HW_ATL_RPO_LRO_TB_DIV_MSKN 0x000FFFFF 1658 /* Lower bit position of bitfield lro_tb_div[11:0] */ 1659 #define HW_ATL_RPO_LRO_TB_DIV_SHIFT 20 1660 /* Width of bitfield lro_tb_div[11:0] */ 1661 #define HW_ATL_RPO_LRO_TB_DIV_WIDTH 12 1662 /* Default value of bitfield lro_tb_div[11:0] */ 1663 #define HW_ATL_RPO_LRO_TB_DIV_DEFAULT 0xC35 1664 1665 /* RX lro_ina_ival[9:0] Bitfield Definitions 1666 * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]". 1667 * PORT="pif_rpo_lro_ina_ival_i[9:0]" 1668 */ 1669 1670 /* Register address for bitfield lro_ina_ival[9:0] */ 1671 #define HW_ATL_RPO_LRO_INA_IVAL_ADR 0x00005620 1672 /* Bitmask for bitfield lro_ina_ival[9:0] */ 1673 #define HW_ATL_RPO_LRO_INA_IVAL_MSK 0x000FFC00 1674 /* Inverted bitmask for bitfield lro_ina_ival[9:0] */ 1675 #define HW_ATL_RPO_LRO_INA_IVAL_MSKN 0xFFF003FF 1676 /* Lower bit position of bitfield lro_ina_ival[9:0] */ 1677 #define HW_ATL_RPO_LRO_INA_IVAL_SHIFT 10 1678 /* Width of bitfield lro_ina_ival[9:0] */ 1679 #define HW_ATL_RPO_LRO_INA_IVAL_WIDTH 10 1680 /* Default value of bitfield lro_ina_ival[9:0] */ 1681 #define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT 0xA 1682 1683 /* RX lro_max_ival[9:0] Bitfield Definitions 1684 * Preprocessor definitions for the bitfield "lro_max_ival[9:0]". 1685 * PORT="pif_rpo_lro_max_ival_i[9:0]" 1686 */ 1687 1688 /* Register address for bitfield lro_max_ival[9:0] */ 1689 #define HW_ATL_RPO_LRO_MAX_IVAL_ADR 0x00005620 1690 /* Bitmask for bitfield lro_max_ival[9:0] */ 1691 #define HW_ATL_RPO_LRO_MAX_IVAL_MSK 0x000003FF 1692 /* Inverted bitmask for bitfield lro_max_ival[9:0] */ 1693 #define HW_ATL_RPO_LRO_MAX_IVAL_MSKN 0xFFFFFC00 1694 /* Lower bit position of bitfield lro_max_ival[9:0] */ 1695 #define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT 0 1696 /* Width of bitfield lro_max_ival[9:0] */ 1697 #define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH 10 1698 /* Default value of bitfield lro_max_ival[9:0] */ 1699 #define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT 0x19 1700 1701 /* TX dca{D}_cpuid[7:0] Bitfield Definitions 1702 * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]". 1703 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1704 * PORT="pif_tdm_dca0_cpuid_i[7:0]" 1705 */ 1706 1707 /* Register address for bitfield dca{D}_cpuid[7:0] */ 1708 #define HW_ATL_TDM_DCA_DCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) 1709 /* Bitmask for bitfield dca{D}_cpuid[7:0] */ 1710 #define HW_ATL_TDM_DCA_DCPUID_MSK 0x000000FF 1711 /* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */ 1712 #define HW_ATL_TDM_DCA_DCPUID_MSKN 0xFFFFFF00 1713 /* Lower bit position of bitfield dca{D}_cpuid[7:0] */ 1714 #define HW_ATL_TDM_DCA_DCPUID_SHIFT 0 1715 /* Width of bitfield dca{D}_cpuid[7:0] */ 1716 #define HW_ATL_TDM_DCA_DCPUID_WIDTH 8 1717 /* Default value of bitfield dca{D}_cpuid[7:0] */ 1718 #define HW_ATL_TDM_DCA_DCPUID_DEFAULT 0x0 1719 1720 /* TX dca{D}_desc_en Bitfield Definitions 1721 * Preprocessor definitions for the bitfield "dca{D}_desc_en". 1722 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1723 * PORT="pif_tdm_dca_desc_en_i[0]" 1724 */ 1725 1726 /* Register address for bitfield dca{D}_desc_en */ 1727 #define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) 1728 /* Bitmask for bitfield dca{D}_desc_en */ 1729 #define HW_ATL_TDM_DCA_DDESC_EN_MSK 0x80000000 1730 /* Inverted bitmask for bitfield dca{D}_desc_en */ 1731 #define HW_ATL_TDM_DCA_DDESC_EN_MSKN 0x7FFFFFFF 1732 /* Lower bit position of bitfield dca{D}_desc_en */ 1733 #define HW_ATL_TDM_DCA_DDESC_EN_SHIFT 31 1734 /* Width of bitfield dca{D}_desc_en */ 1735 #define HW_ATL_TDM_DCA_DDESC_EN_WIDTH 1 1736 /* Default value of bitfield dca{D}_desc_en */ 1737 #define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT 0x0 1738 1739 /* TX desc{D}_en Bitfield Definitions 1740 * Preprocessor definitions for the bitfield "desc{D}_en". 1741 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1742 * PORT="pif_tdm_desc_en_i[0]" 1743 */ 1744 1745 /* Register address for bitfield desc{D}_en */ 1746 #define HW_ATL_TDM_DESC_DEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) 1747 /* Bitmask for bitfield desc{D}_en */ 1748 #define HW_ATL_TDM_DESC_DEN_MSK 0x80000000 1749 /* Inverted bitmask for bitfield desc{D}_en */ 1750 #define HW_ATL_TDM_DESC_DEN_MSKN 0x7FFFFFFF 1751 /* Lower bit position of bitfield desc{D}_en */ 1752 #define HW_ATL_TDM_DESC_DEN_SHIFT 31 1753 /* Width of bitfield desc{D}_en */ 1754 #define HW_ATL_TDM_DESC_DEN_WIDTH 1 1755 /* Default value of bitfield desc{D}_en */ 1756 #define HW_ATL_TDM_DESC_DEN_DEFAULT 0x0 1757 1758 /* TX desc{D}_hd[C:0] Bitfield Definitions 1759 * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]". 1760 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1761 * PORT="tdm_pif_desc0_hd_o[12:0]" 1762 */ 1763 1764 /* Register address for bitfield desc{D}_hd[C:0] */ 1765 #define HW_ATL_TDM_DESC_DHD_ADR(descriptor) (0x00007C0C + (descriptor) * 0x40) 1766 /* Bitmask for bitfield desc{D}_hd[C:0] */ 1767 #define HW_ATL_TDM_DESC_DHD_MSK 0x00001FFF 1768 /* Inverted bitmask for bitfield desc{D}_hd[C:0] */ 1769 #define HW_ATL_TDM_DESC_DHD_MSKN 0xFFFFE000 1770 /* Lower bit position of bitfield desc{D}_hd[C:0] */ 1771 #define HW_ATL_TDM_DESC_DHD_SHIFT 0 1772 /* Width of bitfield desc{D}_hd[C:0] */ 1773 #define HW_ATL_TDM_DESC_DHD_WIDTH 13 1774 1775 /* TX desc{D}_len[9:0] Bitfield Definitions 1776 * Preprocessor definitions for the bitfield "desc{D}_len[9:0]". 1777 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1778 * PORT="pif_tdm_desc0_len_i[9:0]" 1779 */ 1780 1781 /* Register address for bitfield desc{D}_len[9:0] */ 1782 #define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) 1783 /* Bitmask for bitfield desc{D}_len[9:0] */ 1784 #define HW_ATL_TDM_DESC_DLEN_MSK 0x00001FF8 1785 /* Inverted bitmask for bitfield desc{D}_len[9:0] */ 1786 #define HW_ATL_TDM_DESC_DLEN_MSKN 0xFFFFE007 1787 /* Lower bit position of bitfield desc{D}_len[9:0] */ 1788 #define HW_ATL_TDM_DESC_DLEN_SHIFT 3 1789 /* Width of bitfield desc{D}_len[9:0] */ 1790 #define HW_ATL_TDM_DESC_DLEN_WIDTH 10 1791 /* Default value of bitfield desc{D}_len[9:0] */ 1792 #define HW_ATL_TDM_DESC_DLEN_DEFAULT 0x0 1793 1794 /* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions 1795 * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]". 1796 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1797 * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]" 1798 */ 1799 1800 /* Register address for bitfield desc{D}_wrb_thresh[6:0] */ 1801 #define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) \ 1802 (0x00007C18 + (descriptor) * 0x40) 1803 /* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 1804 #define HW_ATL_TDM_DESC_DWRB_THRESH_MSK 0x00007F00 1805 /* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 1806 #define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN 0xFFFF80FF 1807 /* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */ 1808 #define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT 8 1809 /* Width of bitfield desc{D}_wrb_thresh[6:0] */ 1810 #define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH 7 1811 /* Default value of bitfield desc{D}_wrb_thresh[6:0] */ 1812 #define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT 0x0 1813 1814 /* TX tdm_int_mod_en Bitfield Definitions 1815 * Preprocessor definitions for the bitfield "tdm_int_mod_en". 1816 * PORT="pif_tdm_int_mod_en_i" 1817 */ 1818 1819 /* Register address for bitfield tdm_int_mod_en */ 1820 #define HW_ATL_TDM_INT_MOD_EN_ADR 0x00007B40 1821 /* Bitmask for bitfield tdm_int_mod_en */ 1822 #define HW_ATL_TDM_INT_MOD_EN_MSK 0x00000010 1823 /* Inverted bitmask for bitfield tdm_int_mod_en */ 1824 #define HW_ATL_TDM_INT_MOD_EN_MSKN 0xFFFFFFEF 1825 /* Lower bit position of bitfield tdm_int_mod_en */ 1826 #define HW_ATL_TDM_INT_MOD_EN_SHIFT 4 1827 /* Width of bitfield tdm_int_mod_en */ 1828 #define HW_ATL_TDM_INT_MOD_EN_WIDTH 1 1829 /* Default value of bitfield tdm_int_mod_en */ 1830 #define HW_ATL_TDM_INT_MOD_EN_DEFAULT 0x0 1831 1832 /* TX lso_tcp_flag_mid[B:0] Bitfield Definitions 1833 * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]". 1834 * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]" 1835 */ 1836 /* register address for bitfield lso_tcp_flag_mid[b:0] */ 1837 #define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR 0x00007820 1838 /* bitmask for bitfield lso_tcp_flag_mid[b:0] */ 1839 #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK 0x0fff0000 1840 /* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */ 1841 #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN 0xf000ffff 1842 /* lower bit position of bitfield lso_tcp_flag_mid[b:0] */ 1843 #define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT 16 1844 /* width of bitfield lso_tcp_flag_mid[b:0] */ 1845 #define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH 12 1846 /* default value of bitfield lso_tcp_flag_mid[b:0] */ 1847 #define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0 1848 1849 /* tx tx_buf_en bitfield definitions 1850 * preprocessor definitions for the bitfield "tx_buf_en". 1851 * port="pif_tpb_tx_buf_en_i" 1852 */ 1853 1854 /* register address for bitfield tx_buf_en */ 1855 #define HW_ATL_TPB_TX_BUF_EN_ADR 0x00007900 1856 /* bitmask for bitfield tx_buf_en */ 1857 #define HW_ATL_TPB_TX_BUF_EN_MSK 0x00000001 1858 /* inverted bitmask for bitfield tx_buf_en */ 1859 #define HW_ATL_TPB_TX_BUF_EN_MSKN 0xfffffffe 1860 /* lower bit position of bitfield tx_buf_en */ 1861 #define HW_ATL_TPB_TX_BUF_EN_SHIFT 0 1862 /* width of bitfield tx_buf_en */ 1863 #define HW_ATL_TPB_TX_BUF_EN_WIDTH 1 1864 /* default value of bitfield tx_buf_en */ 1865 #define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0 1866 1867 /* register address for bitfield tx_tc_mode */ 1868 #define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900 1869 /* bitmask for bitfield tx_tc_mode */ 1870 #define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100 1871 /* inverted bitmask for bitfield tx_tc_mode */ 1872 #define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF 1873 /* lower bit position of bitfield tx_tc_mode */ 1874 #define HW_ATL_TPB_TX_TC_MODE_SHIFT 8 1875 /* width of bitfield tx_tc_mode */ 1876 #define HW_ATL_TPB_TX_TC_MODE_WIDTH 1 1877 /* default value of bitfield tx_tc_mode */ 1878 #define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0 1879 1880 /* tx tx{b}_hi_thresh[c:0] bitfield definitions 1881 * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". 1882 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 1883 * port="pif_tpb_tx0_hi_thresh_i[12:0]" 1884 */ 1885 1886 /* register address for bitfield tx{b}_hi_thresh[c:0] */ 1887 #define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) 1888 /* bitmask for bitfield tx{b}_hi_thresh[c:0] */ 1889 #define HW_ATL_TPB_TXBHI_THRESH_MSK 0x1fff0000 1890 /* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */ 1891 #define HW_ATL_TPB_TXBHI_THRESH_MSKN 0xe000ffff 1892 /* lower bit position of bitfield tx{b}_hi_thresh[c:0] */ 1893 #define HW_ATL_TPB_TXBHI_THRESH_SHIFT 16 1894 /* width of bitfield tx{b}_hi_thresh[c:0] */ 1895 #define HW_ATL_TPB_TXBHI_THRESH_WIDTH 13 1896 /* default value of bitfield tx{b}_hi_thresh[c:0] */ 1897 #define HW_ATL_TPB_TXBHI_THRESH_DEFAULT 0x0 1898 1899 /* tx tx{b}_lo_thresh[c:0] bitfield definitions 1900 * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]". 1901 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 1902 * port="pif_tpb_tx0_lo_thresh_i[12:0]" 1903 */ 1904 1905 /* register address for bitfield tx{b}_lo_thresh[c:0] */ 1906 #define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) 1907 /* bitmask for bitfield tx{b}_lo_thresh[c:0] */ 1908 #define HW_ATL_TPB_TXBLO_THRESH_MSK 0x00001fff 1909 /* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */ 1910 #define HW_ATL_TPB_TXBLO_THRESH_MSKN 0xffffe000 1911 /* lower bit position of bitfield tx{b}_lo_thresh[c:0] */ 1912 #define HW_ATL_TPB_TXBLO_THRESH_SHIFT 0 1913 /* width of bitfield tx{b}_lo_thresh[c:0] */ 1914 #define HW_ATL_TPB_TXBLO_THRESH_WIDTH 13 1915 /* default value of bitfield tx{b}_lo_thresh[c:0] */ 1916 #define HW_ATL_TPB_TXBLO_THRESH_DEFAULT 0x0 1917 1918 /* tx dma_sys_loopback bitfield definitions 1919 * preprocessor definitions for the bitfield "dma_sys_loopback". 1920 * port="pif_tpb_dma_sys_lbk_i" 1921 */ 1922 1923 /* register address for bitfield dma_sys_loopback */ 1924 #define HW_ATL_TPB_DMA_SYS_LBK_ADR 0x00007000 1925 /* bitmask for bitfield dma_sys_loopback */ 1926 #define HW_ATL_TPB_DMA_SYS_LBK_MSK 0x00000040 1927 /* inverted bitmask for bitfield dma_sys_loopback */ 1928 #define HW_ATL_TPB_DMA_SYS_LBK_MSKN 0xffffffbf 1929 /* lower bit position of bitfield dma_sys_loopback */ 1930 #define HW_ATL_TPB_DMA_SYS_LBK_SHIFT 6 1931 /* width of bitfield dma_sys_loopback */ 1932 #define HW_ATL_TPB_DMA_SYS_LBK_WIDTH 1 1933 /* default value of bitfield dma_sys_loopback */ 1934 #define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0 1935 1936 /* tx tx{b}_buf_size[7:0] bitfield definitions 1937 * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]". 1938 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 1939 * port="pif_tpb_tx0_buf_size_i[7:0]" 1940 */ 1941 1942 /* register address for bitfield tx{b}_buf_size[7:0] */ 1943 #define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) (0x00007910 + (buffer) * 0x10) 1944 /* bitmask for bitfield tx{b}_buf_size[7:0] */ 1945 #define HW_ATL_TPB_TXBBUF_SIZE_MSK 0x000000ff 1946 /* inverted bitmask for bitfield tx{b}_buf_size[7:0] */ 1947 #define HW_ATL_TPB_TXBBUF_SIZE_MSKN 0xffffff00 1948 /* lower bit position of bitfield tx{b}_buf_size[7:0] */ 1949 #define HW_ATL_TPB_TXBBUF_SIZE_SHIFT 0 1950 /* width of bitfield tx{b}_buf_size[7:0] */ 1951 #define HW_ATL_TPB_TXBBUF_SIZE_WIDTH 8 1952 /* default value of bitfield tx{b}_buf_size[7:0] */ 1953 #define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT 0x0 1954 1955 /* tx tx_scp_ins_en bitfield definitions 1956 * preprocessor definitions for the bitfield "tx_scp_ins_en". 1957 * port="pif_tpb_scp_ins_en_i" 1958 */ 1959 1960 /* register address for bitfield tx_scp_ins_en */ 1961 #define HW_ATL_TPB_TX_SCP_INS_EN_ADR 0x00007900 1962 /* bitmask for bitfield tx_scp_ins_en */ 1963 #define HW_ATL_TPB_TX_SCP_INS_EN_MSK 0x00000004 1964 /* inverted bitmask for bitfield tx_scp_ins_en */ 1965 #define HW_ATL_TPB_TX_SCP_INS_EN_MSKN 0xfffffffb 1966 /* lower bit position of bitfield tx_scp_ins_en */ 1967 #define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT 2 1968 /* width of bitfield tx_scp_ins_en */ 1969 #define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1 1970 /* default value of bitfield tx_scp_ins_en */ 1971 #define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0 1972 1973 /* tx ipv4_chk_en bitfield definitions 1974 * preprocessor definitions for the bitfield "ipv4_chk_en". 1975 * port="pif_tpo_ipv4_chk_en_i" 1976 */ 1977 1978 /* register address for bitfield ipv4_chk_en */ 1979 #define HW_ATL_TPO_IPV4CHK_EN_ADR 0x00007800 1980 /* bitmask for bitfield ipv4_chk_en */ 1981 #define HW_ATL_TPO_IPV4CHK_EN_MSK 0x00000002 1982 /* inverted bitmask for bitfield ipv4_chk_en */ 1983 #define HW_ATL_TPO_IPV4CHK_EN_MSKN 0xfffffffd 1984 /* lower bit position of bitfield ipv4_chk_en */ 1985 #define HW_ATL_TPO_IPV4CHK_EN_SHIFT 1 1986 /* width of bitfield ipv4_chk_en */ 1987 #define HW_ATL_TPO_IPV4CHK_EN_WIDTH 1 1988 /* default value of bitfield ipv4_chk_en */ 1989 #define HW_ATL_TPO_IPV4CHK_EN_DEFAULT 0x0 1990 1991 /* tx l4_chk_en bitfield definitions 1992 * preprocessor definitions for the bitfield "l4_chk_en". 1993 * port="pif_tpo_l4_chk_en_i" 1994 */ 1995 1996 /* register address for bitfield l4_chk_en */ 1997 #define HW_ATL_TPOL4CHK_EN_ADR 0x00007800 1998 /* bitmask for bitfield l4_chk_en */ 1999 #define HW_ATL_TPOL4CHK_EN_MSK 0x00000001 2000 /* inverted bitmask for bitfield l4_chk_en */ 2001 #define HW_ATL_TPOL4CHK_EN_MSKN 0xfffffffe 2002 /* lower bit position of bitfield l4_chk_en */ 2003 #define HW_ATL_TPOL4CHK_EN_SHIFT 0 2004 /* width of bitfield l4_chk_en */ 2005 #define HW_ATL_TPOL4CHK_EN_WIDTH 1 2006 /* default value of bitfield l4_chk_en */ 2007 #define HW_ATL_TPOL4CHK_EN_DEFAULT 0x0 2008 2009 /* tx pkt_sys_loopback bitfield definitions 2010 * preprocessor definitions for the bitfield "pkt_sys_loopback". 2011 * port="pif_tpo_pkt_sys_lbk_i" 2012 */ 2013 2014 /* register address for bitfield pkt_sys_loopback */ 2015 #define HW_ATL_TPO_PKT_SYS_LBK_ADR 0x00007000 2016 /* bitmask for bitfield pkt_sys_loopback */ 2017 #define HW_ATL_TPO_PKT_SYS_LBK_MSK 0x00000080 2018 /* inverted bitmask for bitfield pkt_sys_loopback */ 2019 #define HW_ATL_TPO_PKT_SYS_LBK_MSKN 0xffffff7f 2020 /* lower bit position of bitfield pkt_sys_loopback */ 2021 #define HW_ATL_TPO_PKT_SYS_LBK_SHIFT 7 2022 /* width of bitfield pkt_sys_loopback */ 2023 #define HW_ATL_TPO_PKT_SYS_LBK_WIDTH 1 2024 /* default value of bitfield pkt_sys_loopback */ 2025 #define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT 0x0 2026 2027 /* tx data_tc_arb_mode bitfield definitions 2028 * preprocessor definitions for the bitfield "data_tc_arb_mode". 2029 * port="pif_tps_data_tc_arb_mode_i" 2030 */ 2031 2032 /* register address for bitfield data_tc_arb_mode */ 2033 #define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR 0x00007100 2034 /* bitmask for bitfield data_tc_arb_mode */ 2035 #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK 0x00000001 2036 /* inverted bitmask for bitfield data_tc_arb_mode */ 2037 #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffe 2038 /* lower bit position of bitfield data_tc_arb_mode */ 2039 #define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT 0 2040 /* width of bitfield data_tc_arb_mode */ 2041 #define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1 2042 /* default value of bitfield data_tc_arb_mode */ 2043 #define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0 2044 2045 /* tx desc_rate_ta_rst bitfield definitions 2046 * preprocessor definitions for the bitfield "desc_rate_ta_rst". 2047 * port="pif_tps_desc_rate_ta_rst_i" 2048 */ 2049 2050 /* register address for bitfield desc_rate_ta_rst */ 2051 #define HW_ATL_TPS_DESC_RATE_TA_RST_ADR 0x00007310 2052 /* bitmask for bitfield desc_rate_ta_rst */ 2053 #define HW_ATL_TPS_DESC_RATE_TA_RST_MSK 0x80000000 2054 /* inverted bitmask for bitfield desc_rate_ta_rst */ 2055 #define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN 0x7fffffff 2056 /* lower bit position of bitfield desc_rate_ta_rst */ 2057 #define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT 31 2058 /* width of bitfield desc_rate_ta_rst */ 2059 #define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH 1 2060 /* default value of bitfield desc_rate_ta_rst */ 2061 #define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT 0x0 2062 2063 /* tx desc_rate_limit[a:0] bitfield definitions 2064 * preprocessor definitions for the bitfield "desc_rate_limit[a:0]". 2065 * port="pif_tps_desc_rate_lim_i[10:0]" 2066 */ 2067 2068 /* register address for bitfield desc_rate_limit[a:0] */ 2069 #define HW_ATL_TPS_DESC_RATE_LIM_ADR 0x00007310 2070 /* bitmask for bitfield desc_rate_limit[a:0] */ 2071 #define HW_ATL_TPS_DESC_RATE_LIM_MSK 0x000007ff 2072 /* inverted bitmask for bitfield desc_rate_limit[a:0] */ 2073 #define HW_ATL_TPS_DESC_RATE_LIM_MSKN 0xfffff800 2074 /* lower bit position of bitfield desc_rate_limit[a:0] */ 2075 #define HW_ATL_TPS_DESC_RATE_LIM_SHIFT 0 2076 /* width of bitfield desc_rate_limit[a:0] */ 2077 #define HW_ATL_TPS_DESC_RATE_LIM_WIDTH 11 2078 /* default value of bitfield desc_rate_limit[a:0] */ 2079 #define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT 0x0 2080 2081 /* tx desc_tc_arb_mode[1:0] bitfield definitions 2082 * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]". 2083 * port="pif_tps_desc_tc_arb_mode_i[1:0]" 2084 */ 2085 2086 /* register address for bitfield desc_tc_arb_mode[1:0] */ 2087 #define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR 0x00007200 2088 /* bitmask for bitfield desc_tc_arb_mode[1:0] */ 2089 #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK 0x00000003 2090 /* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */ 2091 #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN 0xfffffffc 2092 /* lower bit position of bitfield desc_tc_arb_mode[1:0] */ 2093 #define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT 0 2094 /* width of bitfield desc_tc_arb_mode[1:0] */ 2095 #define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH 2 2096 /* default value of bitfield desc_tc_arb_mode[1:0] */ 2097 #define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT 0x0 2098 2099 /* tx desc_tc{t}_credit_max[b:0] bitfield definitions 2100 * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]". 2101 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2102 * port="pif_tps_desc_tc0_credit_max_i[11:0]" 2103 */ 2104 2105 /* register address for bitfield desc_tc{t}_credit_max[b:0] */ 2106 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) (0x00007210 + (tc) * 0x4) 2107 /* bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2108 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK 0x0fff0000 2109 /* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2110 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN 0xf000ffff 2111 /* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */ 2112 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT 16 2113 /* width of bitfield desc_tc{t}_credit_max[b:0] */ 2114 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH 12 2115 /* default value of bitfield desc_tc{t}_credit_max[b:0] */ 2116 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT 0x0 2117 2118 /* tx desc_tc{t}_weight[8:0] bitfield definitions 2119 * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]". 2120 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2121 * port="pif_tps_desc_tc0_weight_i[8:0]" 2122 */ 2123 2124 /* register address for bitfield desc_tc{t}_weight[8:0] */ 2125 #define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) (0x00007210 + (tc) * 0x4) 2126 /* bitmask for bitfield desc_tc{t}_weight[8:0] */ 2127 #define HW_ATL_TPS_DESC_TCTWEIGHT_MSK 0x000001ff 2128 /* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */ 2129 #define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN 0xfffffe00 2130 /* lower bit position of bitfield desc_tc{t}_weight[8:0] */ 2131 #define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT 0 2132 /* width of bitfield desc_tc{t}_weight[8:0] */ 2133 #define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH 9 2134 /* default value of bitfield desc_tc{t}_weight[8:0] */ 2135 #define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT 0x0 2136 2137 /* tx desc_vm_arb_mode bitfield definitions 2138 * preprocessor definitions for the bitfield "desc_vm_arb_mode". 2139 * port="pif_tps_desc_vm_arb_mode_i" 2140 */ 2141 2142 /* register address for bitfield desc_vm_arb_mode */ 2143 #define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR 0x00007300 2144 /* bitmask for bitfield desc_vm_arb_mode */ 2145 #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK 0x00000001 2146 /* inverted bitmask for bitfield desc_vm_arb_mode */ 2147 #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN 0xfffffffe 2148 /* lower bit position of bitfield desc_vm_arb_mode */ 2149 #define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT 0 2150 /* width of bitfield desc_vm_arb_mode */ 2151 #define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH 1 2152 /* default value of bitfield desc_vm_arb_mode */ 2153 #define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT 0x0 2154 2155 /* tx data_tc{t}_credit_max[b:0] bitfield definitions 2156 * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]". 2157 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2158 * port="pif_tps_data_tc0_credit_max_i[11:0]" 2159 */ 2160 2161 /* register address for bitfield data_tc{t}_credit_max[b:0] */ 2162 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4) 2163 /* bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2164 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000 2165 /* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2166 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff 2167 /* lower bit position of bitfield data_tc{t}_credit_max[b:0] */ 2168 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT 16 2169 /* width of bitfield data_tc{t}_credit_max[b:0] */ 2170 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH 12 2171 /* default value of bitfield data_tc{t}_credit_max[b:0] */ 2172 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0 2173 2174 /* tx data_tc{t}_weight[8:0] bitfield definitions 2175 * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]". 2176 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2177 * port="pif_tps_data_tc0_weight_i[8:0]" 2178 */ 2179 2180 /* register address for bitfield data_tc{t}_weight[8:0] */ 2181 #define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4) 2182 /* bitmask for bitfield data_tc{t}_weight[8:0] */ 2183 #define HW_ATL_TPS_DATA_TCTWEIGHT_MSK 0x000001ff 2184 /* inverted bitmask for bitfield data_tc{t}_weight[8:0] */ 2185 #define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00 2186 /* lower bit position of bitfield data_tc{t}_weight[8:0] */ 2187 #define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT 0 2188 /* width of bitfield data_tc{t}_weight[8:0] */ 2189 #define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH 9 2190 /* default value of bitfield data_tc{t}_weight[8:0] */ 2191 #define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT 0x0 2192 2193 /* tx reg_res_dsbl bitfield definitions 2194 * preprocessor definitions for the bitfield "reg_res_dsbl". 2195 * port="pif_tx_reg_res_dsbl_i" 2196 */ 2197 2198 /* register address for bitfield reg_res_dsbl */ 2199 #define HW_ATL_TX_REG_RES_DSBL_ADR 0x00007000 2200 /* bitmask for bitfield reg_res_dsbl */ 2201 #define HW_ATL_TX_REG_RES_DSBL_MSK 0x20000000 2202 /* inverted bitmask for bitfield reg_res_dsbl */ 2203 #define HW_ATL_TX_REG_RES_DSBL_MSKN 0xdfffffff 2204 /* lower bit position of bitfield reg_res_dsbl */ 2205 #define HW_ATL_TX_REG_RES_DSBL_SHIFT 29 2206 /* width of bitfield reg_res_dsbl */ 2207 #define HW_ATL_TX_REG_RES_DSBL_WIDTH 1 2208 /* default value of bitfield reg_res_dsbl */ 2209 #define HW_ATL_TX_REG_RES_DSBL_DEFAULT 0x1 2210 2211 /* mac_phy register access busy bitfield definitions 2212 * preprocessor definitions for the bitfield "register access busy". 2213 * port="msm_pif_reg_busy_o" 2214 */ 2215 2216 /* register address for bitfield register access busy */ 2217 #define HW_ATL_MSM_REG_ACCESS_BUSY_ADR 0x00004400 2218 /* bitmask for bitfield register access busy */ 2219 #define HW_ATL_MSM_REG_ACCESS_BUSY_MSK 0x00001000 2220 /* inverted bitmask for bitfield register access busy */ 2221 #define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN 0xffffefff 2222 /* lower bit position of bitfield register access busy */ 2223 #define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT 12 2224 /* width of bitfield register access busy */ 2225 #define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH 1 2226 2227 /* mac_phy msm register address[7:0] bitfield definitions 2228 * preprocessor definitions for the bitfield "msm register address[7:0]". 2229 * port="pif_msm_reg_addr_i[7:0]" 2230 */ 2231 2232 /* register address for bitfield msm register address[7:0] */ 2233 #define HW_ATL_MSM_REG_ADDR_ADR 0x00004400 2234 /* bitmask for bitfield msm register address[7:0] */ 2235 #define HW_ATL_MSM_REG_ADDR_MSK 0x000000ff 2236 /* inverted bitmask for bitfield msm register address[7:0] */ 2237 #define HW_ATL_MSM_REG_ADDR_MSKN 0xffffff00 2238 /* lower bit position of bitfield msm register address[7:0] */ 2239 #define HW_ATL_MSM_REG_ADDR_SHIFT 0 2240 /* width of bitfield msm register address[7:0] */ 2241 #define HW_ATL_MSM_REG_ADDR_WIDTH 8 2242 /* default value of bitfield msm register address[7:0] */ 2243 #define HW_ATL_MSM_REG_ADDR_DEFAULT 0x0 2244 2245 /* mac_phy register read strobe bitfield definitions 2246 * preprocessor definitions for the bitfield "register read strobe". 2247 * port="pif_msm_reg_rden_i" 2248 */ 2249 2250 /* register address for bitfield register read strobe */ 2251 #define HW_ATL_MSM_REG_RD_STROBE_ADR 0x00004400 2252 /* bitmask for bitfield register read strobe */ 2253 #define HW_ATL_MSM_REG_RD_STROBE_MSK 0x00000200 2254 /* inverted bitmask for bitfield register read strobe */ 2255 #define HW_ATL_MSM_REG_RD_STROBE_MSKN 0xfffffdff 2256 /* lower bit position of bitfield register read strobe */ 2257 #define HW_ATL_MSM_REG_RD_STROBE_SHIFT 9 2258 /* width of bitfield register read strobe */ 2259 #define HW_ATL_MSM_REG_RD_STROBE_WIDTH 1 2260 /* default value of bitfield register read strobe */ 2261 #define HW_ATL_MSM_REG_RD_STROBE_DEFAULT 0x0 2262 2263 /* mac_phy msm register read data[31:0] bitfield definitions 2264 * preprocessor definitions for the bitfield "msm register read data[31:0]". 2265 * port="msm_pif_reg_rd_data_o[31:0]" 2266 */ 2267 2268 /* register address for bitfield msm register read data[31:0] */ 2269 #define HW_ATL_MSM_REG_RD_DATA_ADR 0x00004408 2270 /* bitmask for bitfield msm register read data[31:0] */ 2271 #define HW_ATL_MSM_REG_RD_DATA_MSK 0xffffffff 2272 /* inverted bitmask for bitfield msm register read data[31:0] */ 2273 #define HW_ATL_MSM_REG_RD_DATA_MSKN 0x00000000 2274 /* lower bit position of bitfield msm register read data[31:0] */ 2275 #define HW_ATL_MSM_REG_RD_DATA_SHIFT 0 2276 /* width of bitfield msm register read data[31:0] */ 2277 #define HW_ATL_MSM_REG_RD_DATA_WIDTH 32 2278 2279 /* mac_phy msm register write data[31:0] bitfield definitions 2280 * preprocessor definitions for the bitfield "msm register write data[31:0]". 2281 * port="pif_msm_reg_wr_data_i[31:0]" 2282 */ 2283 2284 /* register address for bitfield msm register write data[31:0] */ 2285 #define HW_ATL_MSM_REG_WR_DATA_ADR 0x00004404 2286 /* bitmask for bitfield msm register write data[31:0] */ 2287 #define HW_ATL_MSM_REG_WR_DATA_MSK 0xffffffff 2288 /* inverted bitmask for bitfield msm register write data[31:0] */ 2289 #define HW_ATL_MSM_REG_WR_DATA_MSKN 0x00000000 2290 /* lower bit position of bitfield msm register write data[31:0] */ 2291 #define HW_ATL_MSM_REG_WR_DATA_SHIFT 0 2292 /* width of bitfield msm register write data[31:0] */ 2293 #define HW_ATL_MSM_REG_WR_DATA_WIDTH 32 2294 /* default value of bitfield msm register write data[31:0] */ 2295 #define HW_ATL_MSM_REG_WR_DATA_DEFAULT 0x0 2296 2297 /* mac_phy register write strobe bitfield definitions 2298 * preprocessor definitions for the bitfield "register write strobe". 2299 * port="pif_msm_reg_wren_i" 2300 */ 2301 2302 /* register address for bitfield register write strobe */ 2303 #define HW_ATL_MSM_REG_WR_STROBE_ADR 0x00004400 2304 /* bitmask for bitfield register write strobe */ 2305 #define HW_ATL_MSM_REG_WR_STROBE_MSK 0x00000100 2306 /* inverted bitmask for bitfield register write strobe */ 2307 #define HW_ATL_MSM_REG_WR_STROBE_MSKN 0xfffffeff 2308 /* lower bit position of bitfield register write strobe */ 2309 #define HW_ATL_MSM_REG_WR_STROBE_SHIFT 8 2310 /* width of bitfield register write strobe */ 2311 #define HW_ATL_MSM_REG_WR_STROBE_WIDTH 1 2312 /* default value of bitfield register write strobe */ 2313 #define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0 2314 2315 /* mif soft reset bitfield definitions 2316 * preprocessor definitions for the bitfield "soft reset". 2317 * port="pif_glb_res_i" 2318 */ 2319 2320 /* register address for bitfield soft reset */ 2321 #define HW_ATL_GLB_SOFT_RES_ADR 0x00000000 2322 /* bitmask for bitfield soft reset */ 2323 #define HW_ATL_GLB_SOFT_RES_MSK 0x00008000 2324 /* inverted bitmask for bitfield soft reset */ 2325 #define HW_ATL_GLB_SOFT_RES_MSKN 0xffff7fff 2326 /* lower bit position of bitfield soft reset */ 2327 #define HW_ATL_GLB_SOFT_RES_SHIFT 15 2328 /* width of bitfield soft reset */ 2329 #define HW_ATL_GLB_SOFT_RES_WIDTH 1 2330 /* default value of bitfield soft reset */ 2331 #define HW_ATL_GLB_SOFT_RES_DEFAULT 0x0 2332 2333 /* mif register reset disable bitfield definitions 2334 * preprocessor definitions for the bitfield "register reset disable". 2335 * port="pif_glb_reg_res_dsbl_i" 2336 */ 2337 2338 /* register address for bitfield register reset disable */ 2339 #define HW_ATL_GLB_REG_RES_DIS_ADR 0x00000000 2340 /* bitmask for bitfield register reset disable */ 2341 #define HW_ATL_GLB_REG_RES_DIS_MSK 0x00004000 2342 /* inverted bitmask for bitfield register reset disable */ 2343 #define HW_ATL_GLB_REG_RES_DIS_MSKN 0xffffbfff 2344 /* lower bit position of bitfield register reset disable */ 2345 #define HW_ATL_GLB_REG_RES_DIS_SHIFT 14 2346 /* width of bitfield register reset disable */ 2347 #define HW_ATL_GLB_REG_RES_DIS_WIDTH 1 2348 /* default value of bitfield register reset disable */ 2349 #define HW_ATL_GLB_REG_RES_DIS_DEFAULT 0x1 2350 2351 /* tx dma debug control definitions */ 2352 #define HW_ATL_TX_DMA_DEBUG_CTL_ADR 0x00008920u 2353 2354 /* tx dma descriptor base address msw definitions */ 2355 #define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ 2356 (0x00007c04u + (descriptor) * 0x40) 2357 2358 /* tx dma total request limit */ 2359 #define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20u 2360 2361 /* tx interrupt moderation control register definitions 2362 * Preprocessor definitions for TX Interrupt Moderation Control Register 2363 * Base Address: 0x00008980 2364 * Parameter: queue {Q} | stride size 0x4 | range [0, 31] 2365 */ 2366 2367 #define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) (0x00008980u + (queue) * 0x4) 2368 2369 /* pcie reg_res_dsbl bitfield definitions 2370 * preprocessor definitions for the bitfield "reg_res_dsbl". 2371 * port="pif_pci_reg_res_dsbl_i" 2372 */ 2373 2374 /* register address for bitfield reg_res_dsbl */ 2375 #define HW_ATL_PCI_REG_RES_DSBL_ADR 0x00001000 2376 /* bitmask for bitfield reg_res_dsbl */ 2377 #define HW_ATL_PCI_REG_RES_DSBL_MSK 0x20000000 2378 /* inverted bitmask for bitfield reg_res_dsbl */ 2379 #define HW_ATL_PCI_REG_RES_DSBL_MSKN 0xdfffffff 2380 /* lower bit position of bitfield reg_res_dsbl */ 2381 #define HW_ATL_PCI_REG_RES_DSBL_SHIFT 29 2382 /* width of bitfield reg_res_dsbl */ 2383 #define HW_ATL_PCI_REG_RES_DSBL_WIDTH 1 2384 /* default value of bitfield reg_res_dsbl */ 2385 #define HW_ATL_PCI_REG_RES_DSBL_DEFAULT 0x1 2386 2387 /* PCI core control register */ 2388 #define HW_ATL_PCI_REG_CONTROL6_ADR 0x1014u 2389 2390 /* global microprocessor scratch pad definitions */ 2391 #define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) \ 2392 (0x00000300u + (scratch_scp) * 0x4) 2393 2394 /* register address for bitfield uP Force Interrupt */ 2395 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR 0x00000404 2396 /* bitmask for bitfield uP Force Interrupt */ 2397 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK 0x00000002 2398 /* inverted bitmask for bitfield uP Force Interrupt */ 2399 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSKN 0xFFFFFFFD 2400 /* lower bit position of bitfield uP Force Interrupt */ 2401 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT 1 2402 /* width of bitfield uP Force Interrupt */ 2403 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_WIDTH 1 2404 /* default value of bitfield uP Force Interrupt */ 2405 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT 0x0 2406 2407 #endif /* HW_ATL_LLH_INTERNAL_H */ 2408