1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2018 Atomic Rules LLC 3 */ 4 5 #ifndef _ARK_UDM_H_ 6 #define _ARK_UDM_H_ 7 8 #include <stdint.h> 9 10 #include <rte_memory.h> 11 12 /* The UDM or Upstream Data Mover is an internal Arkville hardware 13 * module for moving packet from the RX packet streams to host memory. 14 * This module is *not* intended for end-user manipulation, hence 15 * there is minimal documentation. 16 */ 17 18 /* Meta data structure passed from FPGA, must match layout in FPGA 19 * -- 32 bytes 20 */ 21 struct ark_rx_meta { 22 uint32_t user_meta[5]; /* user defined based on fpga code */ 23 uint8_t reserved[10]; 24 uint16_t pkt_len; 25 } __rte_packed; 26 27 /* 28 * UDM hardware structures 29 * These are overlay structures to a memory mapped FPGA device. These 30 * structs will never be instantiated in ram memory 31 */ 32 33 #define ARK_RX_WRITE_TIME_NS 2500 34 #define ARK_UDM_SETUP 0 35 #define ARK_UDM_CONST2 0xbACECACE 36 #define ARK_UDM_CONST3 0x334d4455 37 #define ARK_UDM_CONST ARK_UDM_CONST3 38 struct ark_udm_setup_t { 39 uint32_t r0; 40 uint32_t r4; 41 volatile uint32_t cycle_count; 42 uint32_t const0; 43 }; 44 45 #define ARK_UDM_CFG 0x010 46 struct ark_udm_cfg_t { 47 volatile uint32_t stop_flushed; /* RO */ 48 volatile uint32_t command; 49 uint32_t dataroom; 50 uint32_t headroom; 51 }; 52 53 typedef enum { 54 ARK_UDM_START = 0x1, 55 ARK_UDM_STOP = 0x2, 56 ARK_UDM_RESET = 0x3 57 } ark_udm_commands; 58 59 #define ARK_UDM_STATS 0x020 60 struct ark_udm_stats_t { 61 volatile uint64_t rx_byte_count; 62 volatile uint64_t rx_packet_count; 63 volatile uint64_t rx_mbuf_count; 64 volatile uint64_t rx_sent_packets; 65 }; 66 67 #define ARK_UDM_PQ 0x040 68 struct ark_udm_queue_stats_t { 69 volatile uint64_t q_byte_count; 70 volatile uint64_t q_packet_count; /* includes drops */ 71 volatile uint64_t q_mbuf_count; 72 volatile uint64_t q_ff_packet_count; 73 volatile uint64_t q_pkt_drop; 74 uint32_t q_enable; 75 }; 76 77 #define ARK_UDM_TLP 0x0070 78 struct ark_udm_tlp_t { 79 volatile uint64_t pkt_drop; /* global */ 80 volatile uint32_t tlp_q1; 81 volatile uint32_t tlp_q2; 82 volatile uint32_t tlp_q3; 83 volatile uint32_t tlp_q4; 84 volatile uint32_t tlp_full; 85 }; 86 87 #define ARK_UDM_PCIBP 0x00a0 88 struct ark_udm_pcibp_t { 89 volatile uint32_t pci_clear; 90 volatile uint32_t pci_empty; 91 volatile uint32_t pci_q1; 92 volatile uint32_t pci_q2; 93 volatile uint32_t pci_q3; 94 volatile uint32_t pci_q4; 95 volatile uint32_t pci_full; 96 }; 97 98 #define ARK_UDM_TLP_PS 0x00bc 99 struct ark_udm_tlp_ps_t { 100 volatile uint32_t tlp_clear; 101 volatile uint32_t tlp_ps_min; 102 volatile uint32_t tlp_ps_max; 103 volatile uint32_t tlp_full_ps_min; 104 volatile uint32_t tlp_full_ps_max; 105 volatile uint32_t tlp_dw_ps_min; 106 volatile uint32_t tlp_dw_ps_max; 107 volatile uint32_t tlp_pldw_ps_min; 108 volatile uint32_t tlp_pldw_ps_max; 109 }; 110 111 #define ARK_UDM_RT_CFG 0x00e0 112 struct ark_udm_rt_cfg_t { 113 rte_iova_t hw_prod_addr; 114 uint32_t write_interval; /* 4ns cycles */ 115 volatile uint32_t prod_idx; /* RO */ 116 }; 117 118 /* Consolidated structure */ 119 #define ARK_UDM_EXPECT_SIZE (0x00fc + 4) 120 #define ARK_UDM_QOFFSET ARK_UDM_EXPECT_SIZE 121 struct ark_udm_t { 122 struct ark_udm_setup_t setup; 123 struct ark_udm_cfg_t cfg; 124 struct ark_udm_stats_t stats; 125 struct ark_udm_queue_stats_t qstats; 126 uint8_t reserved1[(ARK_UDM_TLP - ARK_UDM_PQ) - 127 sizeof(struct ark_udm_queue_stats_t)]; 128 struct ark_udm_tlp_t tlp; 129 uint8_t reserved2[(ARK_UDM_PCIBP - ARK_UDM_TLP) - 130 sizeof(struct ark_udm_tlp_t)]; 131 struct ark_udm_pcibp_t pcibp; 132 struct ark_udm_tlp_ps_t tlp_ps; 133 struct ark_udm_rt_cfg_t rt_cfg; 134 int8_t reserved3[(ARK_UDM_EXPECT_SIZE - ARK_UDM_RT_CFG) - 135 sizeof(struct ark_udm_rt_cfg_t)]; 136 }; 137 138 139 int ark_udm_verify(struct ark_udm_t *udm); 140 int ark_udm_stop(struct ark_udm_t *udm, int wait); 141 void ark_udm_start(struct ark_udm_t *udm); 142 int ark_udm_reset(struct ark_udm_t *udm); 143 void ark_udm_configure(struct ark_udm_t *udm, 144 uint32_t headroom, 145 uint32_t dataroom, 146 uint32_t write_interval_ns); 147 void ark_udm_write_addr(struct ark_udm_t *udm, rte_iova_t addr); 148 void ark_udm_stats_reset(struct ark_udm_t *udm); 149 void ark_udm_dump_stats(struct ark_udm_t *udm, const char *msg); 150 void ark_udm_dump_queue_stats(struct ark_udm_t *udm, const char *msg, 151 uint16_t qid); 152 void ark_udm_dump(struct ark_udm_t *udm, const char *msg); 153 void ark_udm_dump_perf(struct ark_udm_t *udm, const char *msg); 154 void ark_udm_dump_setup(struct ark_udm_t *udm, uint16_t q_id); 155 int ark_udm_is_flushed(struct ark_udm_t *udm); 156 157 /* Per queue data */ 158 uint64_t ark_udm_dropped(struct ark_udm_t *udm); 159 uint64_t ark_udm_bytes(struct ark_udm_t *udm); 160 uint64_t ark_udm_packets(struct ark_udm_t *udm); 161 162 void ark_udm_queue_stats_reset(struct ark_udm_t *udm); 163 void ark_udm_queue_enable(struct ark_udm_t *udm, int enable); 164 165 #endif 166