1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2018 Atomic Rules LLC 3 */ 4 5 #ifndef _ARK_DDM_H_ 6 #define _ARK_DDM_H_ 7 8 #include <stdint.h> 9 10 #include <rte_memory.h> 11 12 13 /* The DDM or Downstream Data Mover is an internal Arkville hardware 14 * module for moving packet from host memory to the TX packet streams. 15 * This module is *not* intended for end-user manipulation, hence 16 * there is minimal documentation. 17 */ 18 19 /* struct defining Tx meta data -- fixed in FPGA -- 8 bytes */ 20 union ark_tx_meta { 21 uint64_t physaddr; 22 struct { 23 uint32_t usermeta0; 24 uint32_t usermeta1; 25 }; 26 struct { 27 uint16_t data_len; /* of this MBUF */ 28 #define ARK_DDM_EOP 0x01 29 #define ARK_DDM_SOP 0x02 30 uint8_t flags; 31 uint8_t meta_cnt; 32 uint32_t user1; 33 }; 34 } __rte_packed; 35 36 /* 37 * DDM core hardware structures 38 * These are overlay structures to a memory mapped FPGA device. These 39 * structs will never be instantiated in ram memory 40 */ 41 #define ARK_DDM_CFG 0x0000 42 /* Set unique HW ID for hardware version */ 43 #define ARK_DDM_CONST3 (0x334d4444) 44 #define ARK_DDM_CONST2 (0x324d4444) 45 #define ARK_DDM_CONST1 (0xfacecafe) 46 47 struct ark_ddm_cfg_t { 48 uint32_t r0; 49 volatile uint32_t tlp_stats_clear; 50 uint32_t const0; 51 volatile uint32_t tag_max; 52 volatile uint32_t command; 53 volatile uint32_t stop_flushed; 54 }; 55 56 #define ARK_DDM_STATS 0x0020 57 struct ark_ddm_stats_t { 58 volatile uint64_t tx_byte_count; 59 volatile uint64_t tx_pkt_count; 60 volatile uint64_t tx_mbuf_count; 61 }; 62 63 #define ARK_DDM_MRDQ 0x0040 64 struct ark_ddm_mrdq_t { 65 volatile uint32_t mrd_q1; 66 volatile uint32_t mrd_q2; 67 volatile uint32_t mrd_q3; 68 volatile uint32_t mrd_q4; 69 volatile uint32_t mrd_full; 70 }; 71 72 #define ARK_DDM_CPLDQ 0x0068 73 struct ark_ddm_cpldq_t { 74 volatile uint32_t cpld_q1; 75 volatile uint32_t cpld_q2; 76 volatile uint32_t cpld_q3; 77 volatile uint32_t cpld_q4; 78 volatile uint32_t cpld_full; 79 }; 80 81 #define ARK_DDM_MRD_PS 0x0090 82 struct ark_ddm_mrd_ps_t { 83 volatile uint32_t mrd_ps_min; 84 volatile uint32_t mrd_ps_max; 85 volatile uint32_t mrd_full_ps_min; 86 volatile uint32_t mrd_full_ps_max; 87 volatile uint32_t mrd_dw_ps_min; 88 volatile uint32_t mrd_dw_ps_max; 89 }; 90 91 #define ARK_DDM_QUEUE_STATS 0x00a8 92 struct ark_ddm_qstats_t { 93 volatile uint64_t byte_count; 94 volatile uint64_t pkt_count; 95 volatile uint64_t mbuf_count; 96 }; 97 98 #define ARK_DDM_CPLD_PS 0x00c0 99 struct ark_ddm_cpld_ps_t { 100 volatile uint32_t cpld_ps_min; 101 volatile uint32_t cpld_ps_max; 102 volatile uint32_t cpld_full_ps_min; 103 volatile uint32_t cpld_full_ps_max; 104 volatile uint32_t cpld_dw_ps_min; 105 volatile uint32_t cpld_dw_ps_max; 106 }; 107 108 #define ARK_DDM_SETUP 0x00e0 109 struct ark_ddm_setup_t { 110 rte_iova_t cons_write_index_addr; 111 uint32_t write_index_interval; /* 4ns each */ 112 volatile uint32_t cons_index; 113 }; 114 115 #define ARK_DDM_EXPECTED_SIZE 256 116 #define ARK_DDM_QOFFSET ARK_DDM_EXPECTED_SIZE 117 /* Consolidated structure */ 118 struct ark_ddm_t { 119 struct ark_ddm_cfg_t cfg; 120 uint8_t reserved0[(ARK_DDM_STATS - ARK_DDM_CFG) - 121 sizeof(struct ark_ddm_cfg_t)]; 122 struct ark_ddm_stats_t stats; 123 uint8_t reserved1[(ARK_DDM_MRDQ - ARK_DDM_STATS) - 124 sizeof(struct ark_ddm_stats_t)]; 125 struct ark_ddm_mrdq_t mrdq; 126 uint8_t reserved2[(ARK_DDM_CPLDQ - ARK_DDM_MRDQ) - 127 sizeof(struct ark_ddm_mrdq_t)]; 128 struct ark_ddm_cpldq_t cpldq; 129 uint8_t reserved3[(ARK_DDM_MRD_PS - ARK_DDM_CPLDQ) - 130 sizeof(struct ark_ddm_cpldq_t)]; 131 struct ark_ddm_mrd_ps_t mrd_ps; 132 struct ark_ddm_qstats_t queue_stats; 133 struct ark_ddm_cpld_ps_t cpld_ps; 134 uint8_t reserved5[(ARK_DDM_SETUP - ARK_DDM_CPLD_PS) - 135 sizeof(struct ark_ddm_cpld_ps_t)]; 136 struct ark_ddm_setup_t setup; 137 uint8_t reserved_p[(ARK_DDM_EXPECTED_SIZE - ARK_DDM_SETUP) - 138 sizeof(struct ark_ddm_setup_t)]; 139 }; 140 141 142 /* DDM function prototype */ 143 int ark_ddm_verify(struct ark_ddm_t *ddm); 144 void ark_ddm_start(struct ark_ddm_t *ddm); 145 int ark_ddm_stop(struct ark_ddm_t *ddm, const int wait); 146 void ark_ddm_reset(struct ark_ddm_t *ddm); 147 void ark_ddm_stats_reset(struct ark_ddm_t *ddm); 148 void ark_ddm_setup(struct ark_ddm_t *ddm, rte_iova_t cons_addr, 149 uint32_t interval); 150 void ark_ddm_dump_stats(struct ark_ddm_t *ddm, const char *msg); 151 void ark_ddm_dump(struct ark_ddm_t *ddm, const char *msg); 152 int ark_ddm_is_stopped(struct ark_ddm_t *ddm); 153 uint64_t ark_ddm_queue_byte_count(struct ark_ddm_t *ddm); 154 uint64_t ark_ddm_queue_pkt_count(struct ark_ddm_t *ddm); 155 void ark_ddm_queue_reset_stats(struct ark_ddm_t *ddm); 156 157 #endif 158