1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Cavium, Inc 3 */ 4 5 #ifndef __TIMVF_EVDEV_H__ 6 #define __TIMVF_EVDEV_H__ 7 8 #include <event_timer_adapter_pmd.h> 9 #include <rte_common.h> 10 #include <rte_cycles.h> 11 #include <rte_debug.h> 12 #include <rte_eal.h> 13 #include <rte_event_timer_adapter.h> 14 #include <rte_eventdev.h> 15 #include <rte_io.h> 16 #include <rte_lcore.h> 17 #include <rte_log.h> 18 #include <rte_malloc.h> 19 #include <rte_mbuf_pool_ops.h> 20 #include <rte_mempool.h> 21 #include <rte_memzone.h> 22 #include <rte_pci.h> 23 #include <rte_prefetch.h> 24 #include <rte_reciprocal.h> 25 26 #include <octeontx_mbox.h> 27 #include <octeontx_fpavf.h> 28 29 #define timvf_log(level, ...) \ 30 RTE_LOG_LINE_PREFIX(level, OTX_TIMVF, "[%s] %s() ", \ 31 RTE_STR(event_timer_octeontx) RTE_LOG_COMMA __func__, __VA_ARGS__) 32 33 #define timvf_log_info(fmt, ...) timvf_log(INFO, fmt, ##__VA_ARGS__) 34 #define timvf_log_dbg(fmt, ...) timvf_log(DEBUG, fmt, ##__VA_ARGS__) 35 #define timvf_log_err(fmt, ...) timvf_log(ERR, fmt, ##__VA_ARGS__) 36 #define timvf_func_trace timvf_log_dbg 37 38 #define TIM_COPROC (8) 39 #define TIM_GET_DEV_INFO (1) 40 #define TIM_GET_RING_INFO (2) 41 #define TIM_SET_RING_INFO (3) 42 #define TIM_RING_START_CYC_GET (4) 43 44 #define TIM_MAX_RINGS (64) 45 #define TIM_DEV_PER_NODE (1) 46 #define TIM_VF_PER_DEV (64) 47 #define TIM_RING_PER_DEV (TIM_VF_PER_DEV) 48 #define TIM_RING_NODE_SHIFT (6) 49 #define TIM_RING_MASK ((TIM_RING_PER_DEV) - 1) 50 #define TIM_RING_INVALID (-1) 51 52 #define TIM_MIN_INTERVAL (1E3) 53 #define TIM_MAX_INTERVAL ((1ull << 32) - 1) 54 #define TIM_MAX_BUCKETS (1ull << 20) 55 #define TIM_CHUNK_SIZE (4096) 56 #define TIM_MAX_CHUNKS_PER_BUCKET (1ull << 32) 57 58 #define TIMVF_MAX_BURST (8) 59 60 /* TIM VF Control/Status registers (CSRs): */ 61 /* VF_BAR0: */ 62 #define TIM_VF_NRSPERR_INT (0x0) 63 #define TIM_VF_NRSPERR_INT_W1S (0x8) 64 #define TIM_VF_NRSPERR_ENA_W1C (0x10) 65 #define TIM_VF_NRSPERR_ENA_W1S (0x18) 66 #define TIM_VRING_FR_RN_CYCLES (0x20) 67 #define TIM_VRING_FR_RN_GPIOS (0x28) 68 #define TIM_VRING_FR_RN_GTI (0x30) 69 #define TIM_VRING_FR_RN_PTP (0x38) 70 #define TIM_VRING_CTL0 (0x40) 71 #define TIM_VRING_CTL1 (0x50) 72 #define TIM_VRING_CTL2 (0x60) 73 #define TIM_VRING_BASE (0x100) 74 #define TIM_VRING_AURA (0x108) 75 #define TIM_VRING_REL (0x110) 76 77 #define TIM_CTL1_W0_S_BUCKET 20 78 #define TIM_CTL1_W0_M_BUCKET ((1ull << (40 - 20)) - 1) 79 80 #define TIM_BUCKET_W1_S_NUM_ENTRIES (0) /*Shift*/ 81 #define TIM_BUCKET_W1_M_NUM_ENTRIES ((1ull << (32 - 0)) - 1) 82 #define TIM_BUCKET_W1_S_SBT (32) 83 #define TIM_BUCKET_W1_M_SBT ((1ull << (33 - 32)) - 1) 84 #define TIM_BUCKET_W1_S_HBT (33) 85 #define TIM_BUCKET_W1_M_HBT ((1ull << (34 - 33)) - 1) 86 #define TIM_BUCKET_W1_S_BSK (34) 87 #define TIM_BUCKET_W1_M_BSK ((1ull << (35 - 34)) - 1) 88 #define TIM_BUCKET_W1_S_LOCK (40) 89 #define TIM_BUCKET_W1_M_LOCK ((1ull << (48 - 40)) - 1) 90 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48) 91 #define TIM_BUCKET_W1_M_CHUNK_REMAINDER ((1ull << (64 - 48)) - 1) 92 93 #define TIM_BUCKET_SEMA \ 94 (TIM_BUCKET_CHUNK_REMAIN) 95 96 #define TIM_BUCKET_CHUNK_REMAIN \ 97 (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER) 98 99 #define TIM_BUCKET_LOCK \ 100 (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK) 101 102 #define TIM_BUCKET_SEMA_WLOCK \ 103 (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK)) 104 105 #define NSEC_PER_SEC 1E9 106 #define NSEC2CLK(__ns, __freq) (((__ns) * (__freq)) / NSEC_PER_SEC) 107 #define CLK2NSEC(__clk, __freq) (((__clk) * NSEC_PER_SEC) / (__freq)) 108 109 #define timvf_read64 rte_read64_relaxed 110 #define timvf_write64 rte_write64_relaxed 111 112 #define TIMVF_ENABLE_STATS_ARG ("timvf_stats") 113 114 extern int otx_logtype_timvf; 115 #define RTE_LOGTYPE_OTX_TIMVF otx_logtype_timvf 116 static const uint16_t nb_chunk_slots = (TIM_CHUNK_SIZE / 16) - 1; 117 118 enum timvf_clk_src { 119 TIM_CLK_SRC_SCLK = RTE_EVENT_TIMER_ADAPTER_CPU_CLK, 120 TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0, 121 TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1, 122 TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2, 123 }; 124 125 /* TIM_MEM_BUCKET */ 126 struct __rte_aligned(8) __rte_packed_begin tim_mem_bucket { 127 uint64_t first_chunk; 128 union { 129 RTE_ATOMIC(uint64_t) w1; 130 struct { 131 RTE_ATOMIC(uint32_t) nb_entry; 132 uint8_t sbt:1; 133 uint8_t hbt:1; 134 uint8_t bsk:1; 135 uint8_t rsvd:5; 136 RTE_ATOMIC(uint8_t) lock; 137 RTE_ATOMIC(int16_t) chunk_remainder; 138 }; 139 }; 140 uint64_t current_chunk; 141 uint64_t pad; 142 } __rte_packed_end; 143 144 struct __rte_packed_begin tim_mem_entry { 145 uint64_t w0; 146 uint64_t wqe; 147 } __rte_packed_end; 148 149 struct __rte_packed_begin timvf_ctrl_reg { 150 uint64_t rctrl0; 151 uint64_t rctrl1; 152 uint64_t rctrl2; 153 uint8_t use_pmu; 154 } __rte_packed_end; 155 156 struct timvf_ring; 157 158 typedef uint32_t (*bkt_id)(const uint32_t bkt_tcks, const uint32_t nb_bkts); 159 typedef struct tim_mem_entry * (*refill_chunk)( 160 struct tim_mem_bucket * const bkt, 161 struct timvf_ring * const timr); 162 163 struct __rte_cache_aligned timvf_ring { 164 bkt_id get_target_bkt; 165 refill_chunk refill_chunk; 166 struct rte_reciprocal_u64 fast_div; 167 uint64_t ring_start_cyc; 168 uint32_t nb_bkts; 169 struct tim_mem_bucket *bkt; 170 void *chunk_pool; 171 uint64_t tck_int; 172 volatile uint64_t tim_arm_cnt; 173 uint64_t tck_nsec; 174 void *vbar0; 175 void *bkt_pos; 176 uint64_t max_tout; 177 uint64_t nb_chunks; 178 uint64_t nb_timers; 179 enum timvf_clk_src clk_src; 180 uint16_t tim_ring_id; 181 }; 182 183 static __rte_always_inline uint32_t 184 bkt_mod(const uint32_t rel_bkt, const uint32_t nb_bkts) 185 { 186 return rel_bkt % nb_bkts; 187 } 188 189 static __rte_always_inline uint32_t 190 bkt_and(uint32_t rel_bkt, uint32_t nb_bkts) 191 { 192 return rel_bkt & (nb_bkts - 1); 193 } 194 195 uint8_t timvf_get_ring(void); 196 void timvf_release_ring(uint8_t vfid); 197 void *timvf_bar(uint8_t id, uint8_t bar); 198 int timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags, 199 uint32_t *caps, 200 const struct event_timer_adapter_ops **ops, 201 uint8_t enable_stats); 202 uint16_t timvf_timer_cancel_burst(const struct rte_event_timer_adapter *adptr, 203 struct rte_event_timer **tim, const uint16_t nb_timers); 204 uint16_t timvf_timer_arm_burst_sp(const struct rte_event_timer_adapter *adptr, 205 struct rte_event_timer **tim, const uint16_t nb_timers); 206 uint16_t timvf_timer_arm_burst_sp_stats( 207 const struct rte_event_timer_adapter *adptr, 208 struct rte_event_timer **tim, const uint16_t nb_timers); 209 uint16_t timvf_timer_arm_burst_mp(const struct rte_event_timer_adapter *adptr, 210 struct rte_event_timer **tim, const uint16_t nb_timers); 211 uint16_t timvf_timer_arm_burst_mp_stats( 212 const struct rte_event_timer_adapter *adptr, 213 struct rte_event_timer **tim, const uint16_t nb_timers); 214 uint16_t timvf_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr, 215 struct rte_event_timer **tim, const uint64_t timeout_tick, 216 const uint16_t nb_timers); 217 uint16_t timvf_timer_arm_tmo_brst_stats( 218 const struct rte_event_timer_adapter *adptr, 219 struct rte_event_timer **tim, const uint64_t timeout_tick, 220 const uint16_t nb_timers); 221 void timvf_set_chunk_refill(struct timvf_ring * const timr, uint8_t use_fpa); 222 void timvf_set_eventdevice(struct rte_eventdev *dev); 223 224 #endif /* __TIMVF_EVDEV_H__ */ 225