1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(C) 2024 Marvell. 3 */ 4 5 #ifndef _ODM_H_ 6 #define _ODM_H_ 7 8 #include <stdint.h> 9 10 #include <rte_common.h> 11 #include <rte_compat.h> 12 #include <rte_io.h> 13 #include <rte_log.h> 14 #include <rte_memzone.h> 15 16 /* ODM VF register offsets from VF_BAR0 */ 17 #define ODM_VDMA_EN(x) (0x00 | (x << 3)) 18 #define ODM_VDMA_REQQ_CTL(x) (0x80 | (x << 3)) 19 #define ODM_VDMA_DBELL(x) (0x100 | (x << 3)) 20 #define ODM_VDMA_RING_CFG(x) (0x180 | (x << 3)) 21 #define ODM_VDMA_IRING_BADDR(x) (0x200 | (x << 3)) 22 #define ODM_VDMA_CRING_BADDR(x) (0x280 | (x << 3)) 23 #define ODM_VDMA_COUNTS(x) (0x300 | (x << 3)) 24 #define ODM_VDMA_IRING_NADDR(x) (0x380 | (x << 3)) 25 #define ODM_VDMA_CRING_NADDR(x) (0x400 | (x << 3)) 26 #define ODM_VDMA_IRING_DBG(x) (0x480 | (x << 3)) 27 #define ODM_VDMA_CNT(x) (0x580 | (x << 3)) 28 #define ODM_VF_INT (0x1000) 29 #define ODM_VF_INT_W1S (0x1008) 30 #define ODM_VF_INT_ENA_W1C (0x1010) 31 #define ODM_VF_INT_ENA_W1S (0x1018) 32 #define ODM_MBOX_VF_PF_DATA(i) (0x2000 | (i << 3)) 33 #define ODM_MBOX_RETRY_CNT (0xfffffff) 34 #define ODM_MBOX_ERR_CODE_MAX (0xf) 35 #define ODM_IRING_IDLE_WAIT_CNT (0xfffffff) 36 37 /* 38 * Enumeration odm_hdr_xtype_e 39 * 40 * ODM Transfer Type Enumeration 41 * Enumerates the pointer type in ODM_DMA_INSTR_HDR_S[XTYPE] 42 */ 43 #define ODM_XTYPE_INTERNAL 2 44 #define ODM_XTYPE_FILL0 4 45 #define ODM_XTYPE_FILL1 5 46 47 /* 48 * ODM Header completion type enumeration 49 * Enumerates the completion type in ODM_DMA_INSTR_HDR_S[CT] 50 */ 51 #define ODM_HDR_CT_CW_CA 0x0 52 #define ODM_HDR_CT_CW_NC 0x1 53 54 #define ODM_MAX_QUEUES_PER_DEV 16 55 56 #define ODM_IRING_MAX_SIZE (256 * 1024) 57 #define ODM_IRING_ENTRY_SIZE_MIN 4 58 #define ODM_IRING_ENTRY_SIZE_MAX 13 59 #define ODM_IRING_MAX_WORDS (ODM_IRING_MAX_SIZE / 8) 60 #define ODM_IRING_MAX_ENTRY (ODM_IRING_MAX_WORDS / ODM_IRING_ENTRY_SIZE_MIN) 61 62 #define ODM_MAX_POINTER 4 63 64 #define odm_read64(addr) rte_read64_relaxed((volatile void *)(addr)) 65 #define odm_write64(val, addr) rte_write64_relaxed((val), (volatile void *)(addr)) 66 67 extern int odm_logtype; 68 #define RTE_LOGTYPE_ODM odm_logtype 69 70 #define ODM_LOG(level, ...) \ 71 RTE_LOG_LINE_PREFIX(level, ODM, "%s(): %u", __func__ RTE_LOG_COMMA __LINE__, __VA_ARGS__) 72 73 /* 74 * Structure odm_instr_hdr_s for ODM 75 * 76 * ODM DMA Instruction Header Format 77 */ 78 union odm_instr_hdr_s { 79 uint64_t u; 80 struct odm_instr_hdr { 81 uint64_t nfst : 3; 82 uint64_t reserved_3 : 1; 83 uint64_t nlst : 3; 84 uint64_t reserved_7_9 : 3; 85 uint64_t ct : 2; 86 uint64_t stse : 1; 87 uint64_t reserved_13_28 : 16; 88 uint64_t sts : 1; 89 uint64_t reserved_30_49 : 20; 90 uint64_t xtype : 3; 91 uint64_t reserved_53_63 : 11; 92 } s; 93 }; 94 95 /* ODM Completion Entry Structure */ 96 union odm_cmpl_ent_s { 97 uint32_t u; 98 struct odm_cmpl_ent { 99 uint32_t cmp_code : 8; 100 uint32_t rsvd : 23; 101 uint32_t valid : 1; 102 } s; 103 }; 104 105 /* ODM DMA Ring Configuration Register */ 106 union odm_vdma_ring_cfg_s { 107 uint64_t u; 108 struct { 109 uint64_t isize : 8; 110 uint64_t rsvd_8_15 : 8; 111 uint64_t csize : 8; 112 uint64_t rsvd_24_63 : 40; 113 } s; 114 }; 115 116 /* ODM DMA Instruction Ring DBG */ 117 union odm_vdma_iring_dbg_s { 118 uint64_t u; 119 struct { 120 uint64_t dbell_cnt : 32; 121 uint64_t offset : 16; 122 uint64_t rsvd_48_62 : 15; 123 uint64_t iwbusy : 1; 124 } s; 125 }; 126 127 /* ODM DMA Counts */ 128 union odm_vdma_counts_s { 129 uint64_t u; 130 struct { 131 uint64_t dbell : 32; 132 uint64_t buf_used_cnt : 9; 133 uint64_t rsvd_41_43 : 3; 134 uint64_t rsvd_buf_used_cnt : 3; 135 uint64_t rsvd_47_63 : 17; 136 } s; 137 }; 138 139 struct vq_stats { 140 uint64_t submitted; 141 uint64_t completed; 142 uint64_t errors; 143 /* 144 * Since stats.completed is used to return completion index, account for any packets 145 * received before stats is reset. 146 */ 147 uint64_t completed_offset; 148 }; 149 150 struct odm_queue { 151 struct odm_dev *dev; 152 /* Instructions that are prepared on the iring, but is not pushed to hw yet. */ 153 uint16_t pending_submit_cnt; 154 /* Length (in words) of instructions that are not yet pushed to hw. */ 155 uint16_t pending_submit_len; 156 uint16_t desc_idx; 157 /* Instruction ring head. Used for enqueue. */ 158 uint16_t iring_head; 159 /* Completion ring head. Used for dequeue. */ 160 uint16_t cring_head; 161 /* Extra instruction size ring head. Used in enqueue-dequeue.*/ 162 uint16_t ins_ring_head; 163 /* Extra instruction size ring tail. Used in enqueue-dequeue.*/ 164 uint16_t ins_ring_tail; 165 /* Instruction size available.*/ 166 uint16_t iring_sz_available; 167 /* Number of 8-byte words in iring.*/ 168 uint16_t iring_max_words; 169 /* Number of words in cring.*/ 170 uint16_t cring_max_entry; 171 /* Extra instruction size used per inflight instruction.*/ 172 uint8_t *extra_ins_sz; 173 struct vq_stats stats; 174 const struct rte_memzone *iring_mz; 175 const struct rte_memzone *cring_mz; 176 }; 177 178 struct __rte_cache_aligned odm_dev { 179 struct rte_pci_device *pci_dev; 180 struct odm_queue vq[ODM_MAX_QUEUES_PER_DEV]; 181 uint8_t *rbase; 182 uint16_t vfid; 183 uint8_t max_qs; 184 uint8_t num_qs; 185 }; 186 187 int odm_dev_init(struct odm_dev *odm); 188 int odm_dev_fini(struct odm_dev *odm); 189 int odm_configure(struct odm_dev *odm); 190 int odm_enable(struct odm_dev *odm); 191 int odm_disable(struct odm_dev *odm); 192 int odm_vchan_setup(struct odm_dev *odm, int vchan, int nb_desc); 193 194 #endif /* _ODM_H_ */ 195