1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2021-2024 NXP 3 */ 4 5 #ifndef _DPAA_QDMA_H_ 6 #define _DPAA_QDMA_H_ 7 8 #include <rte_io.h> 9 10 #ifndef BIT 11 #define BIT(nr) (1UL << (nr)) 12 #endif 13 14 #define RETRIES 5 15 16 #ifndef GENMASK 17 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8) 18 #define GENMASK(h, l) \ 19 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) 20 #endif 21 22 #define QDMA_CTRL_REGION_OFFSET 0 23 #define QDMA_CTRL_REGION_SIZE 0x10000 24 #define QDMA_STATUS_REGION_OFFSET \ 25 (QDMA_CTRL_REGION_OFFSET + QDMA_CTRL_REGION_SIZE) 26 #define QDMA_STATUS_REGION_SIZE 0x10000 27 28 #define DPAA_QDMA_FLAGS_INDEX RTE_BIT64(63) 29 #define DPAA_QDMA_COPY_IDX_OFFSET 8 30 #define DPAA_QDMA_SG_IDX_ADDR_ALIGN \ 31 RTE_BIT64(DPAA_QDMA_COPY_IDX_OFFSET) 32 #define DPAA_QDMA_SG_IDX_ADDR_MASK \ 33 (DPAA_QDMA_SG_IDX_ADDR_ALIGN - 1) 34 35 #define FSL_QDMA_DMR 0x0 36 #define FSL_QDMA_DSR 0x4 37 #define FSL_QDMA_DEDR 0xe04 38 #define FSL_QDMA_DECFDW0R 0xe10 39 #define FSL_QDMA_DECFDW1R 0xe14 40 #define FSL_QDMA_DECFDW2R 0xe18 41 #define FSL_QDMA_DECFDW3R 0xe1c 42 #define FSL_QDMA_DECFQIDR 0xe30 43 #define FSL_QDMA_DECBR 0xe34 44 45 #define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x)) 46 #define FSL_QDMA_BCQSR(x) (0xc4 + 0x100 * (x)) 47 #define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x)) 48 #define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x)) 49 #define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x)) 50 #define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x)) 51 #define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x)) 52 #define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x)) 53 54 #define FSL_QDMA_SQEDPAR 0x808 55 #define FSL_QDMA_SQDPAR 0x80c 56 #define FSL_QDMA_SQEEPAR 0x810 57 #define FSL_QDMA_SQEPAR 0x814 58 #define FSL_QDMA_BSQMR 0x800 59 #define FSL_QDMA_BSQSR 0x804 60 #define FSL_QDMA_BSQICR 0x828 61 #define FSL_QDMA_CQIER 0xa10 62 #define FSL_QDMA_SQCCMR 0xa20 63 64 #define FSL_QDMA_SQCCMR_ENTER_WM 0x200000 65 66 #define FSL_QDMA_QUEUE_MAX 8 67 68 #define FSL_QDMA_BCQMR_EN 0x80000000 69 #define FSL_QDMA_BCQMR_EI 0x40000000 70 71 #define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20) 72 #define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16) 73 74 #define FSL_QDMA_BCQSR_QF_XOFF_BE 0x1000100 75 76 #define FSL_QDMA_BSQMR_EN 0x80000000 77 #define FSL_QDMA_BSQMR_CQ_SIZE(x) ((x) << 16) 78 #define FSL_QDMA_BSQMR_DI 0xc0 79 80 #define FSL_QDMA_BSQSR_QE_BE 0x200 81 82 #define FSL_QDMA_DMR_DQD 0x40000000 83 #define FSL_QDMA_DSR_DB 0x80000000 84 85 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64 86 #define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384 87 #define FSL_QDMA_QUEUE_NUM_MAX 8 88 89 #define FSL_QDMA_COMP_SG_FORMAT 0x1 90 91 #define FSL_QDMA_CMD_RWTTYPE 0x4 92 #define FSL_QDMA_CMD_LWC 0x2 93 94 #define FSL_QDMA_CMD_SS_ERR050757_LEN 128 95 96 /* qdma engine attribute */ 97 #define QDMA_QUEUE_SIZE FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 98 #define QDMA_STATUS_SIZE QDMA_QUEUE_SIZE 99 #define QDMA_CCSR_BASE 0x8380000 100 #define QDMA_BLOCK_OFFSET 0x10000 101 #define QDMA_BLOCKS 4 102 #define QDMA_QUEUES 8 103 #define QDMA_QUEUE_CR_WM 32 104 105 #define QDMA_BIG_ENDIAN 1 106 #ifdef QDMA_BIG_ENDIAN 107 #define QDMA_IN(addr) be32_to_cpu(rte_read32(addr)) 108 #define QDMA_OUT(addr, val) rte_write32(be32_to_cpu(val), addr) 109 #define QDMA_IN_BE(addr) rte_read32(addr) 110 #define QDMA_OUT_BE(addr, val) rte_write32(val, addr) 111 #else 112 #define QDMA_IN(addr) rte_read32(addr) 113 #define QDMA_OUT(addr, val) rte_write32(val, addr) 114 #define QDMA_IN_BE(addr) be32_to_cpu(rte_write32(addr)) 115 #define QDMA_OUT_BE(addr, val) rte_write32(be32_to_cpu(val), addr) 116 #endif 117 118 #define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x) \ 119 (((fsl_qdma_engine)->block_offset) * (x)) 120 121 /* qDMA Command Descriptor Formats */ 122 struct __rte_packed_begin fsl_qdma_comp_cmd_desc { 123 uint8_t status; 124 uint32_t rsv0:22; 125 uint32_t ser:1; 126 uint32_t rsv1:21; 127 uint32_t offset:9; 128 uint32_t format:3; 129 uint32_t addr_lo; 130 uint8_t addr_hi; 131 uint16_t rsv3; 132 uint8_t queue:3; 133 uint8_t rsv4:3; 134 uint8_t dd:2; 135 } __rte_packed_end; 136 137 struct __rte_packed_begin fsl_qdma_comp_sg_desc { 138 uint32_t offset:13; 139 uint32_t rsv0:19; 140 uint32_t length:30; 141 uint32_t final:1; 142 uint32_t extion:1; 143 uint32_t addr_lo; 144 uint8_t addr_hi; 145 uint32_t rsv1:24; 146 } __rte_packed_end; 147 148 struct __rte_packed_begin fsl_qdma_sdf { 149 uint32_t rsv0; 150 uint32_t ssd:12; 151 uint32_t sss:12; 152 uint32_t rsv1:8; 153 uint32_t rsv2; 154 155 uint32_t rsv3:17; 156 uint32_t prefetch:1; 157 uint32_t rsv4:1; 158 uint32_t ssen:1; 159 uint32_t rthrotl:4; 160 uint32_t sqos:3; 161 uint32_t ns:1; 162 uint32_t srttype:4; 163 } __rte_packed_end; 164 165 struct __rte_packed_begin fsl_qdma_ddf { 166 uint32_t rsv0; 167 uint32_t dsd:12; 168 uint32_t dss:12; 169 uint32_t rsv1:8; 170 uint32_t rsv2; 171 172 uint16_t rsv3; 173 uint32_t lwc:2; 174 uint32_t rsv4:1; 175 uint32_t dsen:1; 176 uint32_t wthrotl:4; 177 uint32_t dqos:3; 178 uint32_t ns:1; 179 uint32_t dwttype:4; 180 } __rte_packed_end; 181 182 struct fsl_qdma_df { 183 struct fsl_qdma_sdf sdf; 184 struct fsl_qdma_ddf ddf; 185 }; 186 187 #define FSL_QDMA_SG_MAX_ENTRY 64 188 #define FSL_QDMA_MAX_DESC_NUM (FSL_QDMA_SG_MAX_ENTRY * QDMA_QUEUE_SIZE) 189 struct __rte_packed_begin fsl_qdma_cmpd_ft { 190 struct fsl_qdma_comp_sg_desc desc_buf; 191 struct fsl_qdma_comp_sg_desc desc_sbuf; 192 struct fsl_qdma_comp_sg_desc desc_dbuf; 193 uint64_t cache_align[2]; 194 struct fsl_qdma_comp_sg_desc desc_ssge[FSL_QDMA_SG_MAX_ENTRY]; 195 struct fsl_qdma_comp_sg_desc desc_dsge[FSL_QDMA_SG_MAX_ENTRY]; 196 struct fsl_qdma_df df; 197 uint64_t phy_ssge; 198 uint64_t phy_dsge; 199 uint64_t phy_df; 200 } __rte_packed_end; 201 202 #define FSL_QDMA_ERR_REG_STATUS_OFFSET 0xe00 203 204 struct fsl_qdma_dedr_reg { 205 uint32_t me:1; 206 uint32_t rsv0:1; 207 uint32_t rte:1; 208 uint32_t wte:1; 209 uint32_t cde:1; 210 uint32_t sde:1; 211 uint32_t dde:1; 212 uint32_t ere:1; 213 uint32_t rsv1:24; 214 }; 215 216 struct fsl_qdma_deccqidr_reg { 217 uint32_t rsv:27; 218 uint32_t block:2; 219 uint32_t queue:3; 220 }; 221 222 #define FSL_QDMA_DECCD_ERR_NUM \ 223 (sizeof(struct fsl_qdma_comp_cmd_desc) / sizeof(uint32_t)) 224 225 struct fsl_qdma_err_reg { 226 uint32_t deier; 227 union { 228 rte_be32_t dedr_be; 229 struct fsl_qdma_dedr_reg dedr; 230 }; 231 uint32_t rsv0[2]; 232 union { 233 rte_le32_t deccd_le[FSL_QDMA_DECCD_ERR_NUM]; 234 struct fsl_qdma_comp_cmd_desc err_cmd; 235 }; 236 uint32_t rsv1[4]; 237 union { 238 rte_be32_t deccqidr_be; 239 struct fsl_qdma_deccqidr_reg deccqidr; 240 }; 241 rte_be32_t decbr; 242 }; 243 244 #define DPAA_QDMA_IDXADDR_FROM_SG_FLAG(flag) \ 245 ((void *)(uintptr_t)((flag) - ((flag) & DPAA_QDMA_SG_IDX_ADDR_MASK))) 246 247 #define DPAA_QDMA_IDX_FROM_FLAG(flag) \ 248 ((flag) >> DPAA_QDMA_COPY_IDX_OFFSET) 249 250 struct fsl_qdma_desc { 251 rte_iova_t src; 252 rte_iova_t dst; 253 uint64_t flag; 254 uint64_t len; 255 }; 256 257 struct fsl_qdma_queue { 258 int used; 259 struct fsl_qdma_cmpd_ft **ft; 260 uint16_t ci; 261 struct rte_ring *complete_burst; 262 struct rte_ring *complete_desc; 263 struct rte_ring *complete_pool; 264 uint16_t n_cq; 265 uint8_t block_id; 266 uint8_t queue_id; 267 uint8_t channel_id; 268 void *block_vir; 269 uint32_t le_cqmr; 270 struct fsl_qdma_comp_cmd_desc *cq; 271 uint16_t desc_in_hw[QDMA_QUEUE_SIZE]; 272 struct rte_dma_stats stats; 273 struct fsl_qdma_desc *pending_desc; 274 uint16_t pending_max; 275 uint16_t pending_start; 276 uint16_t pending_num; 277 uint16_t complete_start; 278 dma_addr_t bus_addr; 279 void *engine; 280 }; 281 282 struct fsl_qdma_status_queue { 283 uint16_t n_cq; 284 uint16_t complete; 285 uint8_t block_id; 286 void *block_vir; 287 struct fsl_qdma_comp_cmd_desc *cq; 288 struct rte_dma_stats stats; 289 dma_addr_t bus_addr; 290 void *engine; 291 }; 292 293 struct fsl_qdma_engine { 294 void *reg_base; 295 void *ctrl_base; 296 void *status_base; 297 void *block_base; 298 uint32_t n_queues; 299 uint8_t block_queues[QDMA_BLOCKS]; 300 struct fsl_qdma_queue cmd_queues[QDMA_BLOCKS][QDMA_QUEUES]; 301 struct fsl_qdma_status_queue stat_queues[QDMA_BLOCKS]; 302 struct fsl_qdma_queue *chan[QDMA_BLOCKS * QDMA_QUEUES]; 303 uint32_t num_blocks; 304 int block_offset; 305 int is_silent; 306 }; 307 308 #endif /* _DPAA_QDMA_H_ */ 309