1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 HUAWEI TECHNOLOGIES CO., LTD. 3 */ 4 5 #ifndef _VIRTIO_PCI_H_ 6 #define _VIRTIO_PCI_H_ 7 8 #include <stdint.h> 9 10 #include <rte_pci.h> 11 #include <rte_bus_pci.h> 12 #include <rte_cryptodev.h> 13 14 #include "virtio_crypto.h" 15 16 struct virtqueue; 17 18 /* VirtIO PCI vendor/device ID. */ 19 #define VIRTIO_CRYPTO_PCI_VENDORID 0x1AF4 20 #define VIRTIO_CRYPTO_PCI_DEVICEID 0x1054 21 22 /* VirtIO ABI version, this must match exactly. */ 23 #define VIRTIO_PCI_ABI_VERSION 0 24 25 /* 26 * VirtIO Header, located in BAR 0. 27 */ 28 #define VIRTIO_PCI_HOST_FEATURES 0 /* host's supported features (32bit, RO)*/ 29 #define VIRTIO_PCI_GUEST_FEATURES 4 /* guest's supported features (32, RW) */ 30 #define VIRTIO_PCI_QUEUE_PFN 8 /* physical address of VQ (32, RW) */ 31 #define VIRTIO_PCI_QUEUE_NUM 12 /* number of ring entries (16, RO) */ 32 #define VIRTIO_PCI_QUEUE_SEL 14 /* current VQ selection (16, RW) */ 33 #define VIRTIO_PCI_QUEUE_NOTIFY 16 /* notify host regarding VQ (16, RW) */ 34 #define VIRTIO_PCI_STATUS 18 /* device status register (8, RW) */ 35 #define VIRTIO_PCI_ISR 19 /* interrupt status register, reading 36 * also clears the register (8, RO) 37 */ 38 /* Only if MSIX is enabled: */ 39 40 /* configuration change vector (16, RW) */ 41 #define VIRTIO_MSI_CONFIG_VECTOR 20 42 /* vector for selected VQ notifications */ 43 #define VIRTIO_MSI_QUEUE_VECTOR 22 44 45 /* The bit of the ISR which indicates a device has an interrupt. */ 46 #define VIRTIO_PCI_ISR_INTR 0x1 47 /* The bit of the ISR which indicates a device configuration change. */ 48 #define VIRTIO_PCI_ISR_CONFIG 0x2 49 /* Vector value used to disable MSI for queue. */ 50 #define VIRTIO_MSI_NO_VECTOR 0xFFFF 51 52 /* Status byte for guest to report progress. */ 53 #define VIRTIO_CONFIG_STATUS_RESET 0x00 54 #define VIRTIO_CONFIG_STATUS_ACK 0x01 55 #define VIRTIO_CONFIG_STATUS_DRIVER 0x02 56 #define VIRTIO_CONFIG_STATUS_DRIVER_OK 0x04 57 #define VIRTIO_CONFIG_STATUS_FEATURES_OK 0x08 58 #define VIRTIO_CONFIG_STATUS_FAILED 0x80 59 60 /* 61 * Each virtqueue indirect descriptor list must be physically contiguous. 62 * To allow us to malloc(9) each list individually, limit the number 63 * supported to what will fit in one page. With 4KB pages, this is a limit 64 * of 256 descriptors. If there is ever a need for more, we can switch to 65 * contigmalloc(9) for the larger allocations, similar to what 66 * bus_dmamem_alloc(9) does. 67 * 68 * Note the sizeof(struct vring_desc) is 16 bytes. 69 */ 70 #define VIRTIO_MAX_INDIRECT ((int) (PAGE_SIZE / 16)) 71 72 /* Do we get callbacks when the ring is completely used, even if we've 73 * suppressed them? 74 */ 75 #define VIRTIO_F_NOTIFY_ON_EMPTY 24 76 77 /* Can the device handle any descriptor layout? */ 78 #define VIRTIO_F_ANY_LAYOUT 27 79 80 /* We support indirect buffer descriptors */ 81 #define VIRTIO_RING_F_INDIRECT_DESC 28 82 83 #define VIRTIO_F_VERSION_1 32 84 #define VIRTIO_F_IOMMU_PLATFORM 33 85 86 /* The Guest publishes the used index for which it expects an interrupt 87 * at the end of the avail ring. Host should ignore the avail->flags field. 88 */ 89 /* The Host publishes the avail index for which it expects a kick 90 * at the end of the used ring. Guest should ignore the used->flags field. 91 */ 92 #define VIRTIO_RING_F_EVENT_IDX 29 93 94 /* Common configuration */ 95 #define VIRTIO_PCI_CAP_COMMON_CFG 1 96 /* Notifications */ 97 #define VIRTIO_PCI_CAP_NOTIFY_CFG 2 98 /* ISR Status */ 99 #define VIRTIO_PCI_CAP_ISR_CFG 3 100 /* Device specific configuration */ 101 #define VIRTIO_PCI_CAP_DEVICE_CFG 4 102 /* PCI configuration access */ 103 #define VIRTIO_PCI_CAP_PCI_CFG 5 104 105 /* This is the PCI capability header: */ 106 struct virtio_pci_cap { 107 uint8_t cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */ 108 uint8_t cap_next; /* Generic PCI field: next ptr. */ 109 uint8_t cap_len; /* Generic PCI field: capability length */ 110 uint8_t cfg_type; /* Identifies the structure. */ 111 uint8_t bar; /* Where to find it. */ 112 uint8_t padding[3]; /* Pad to full dword. */ 113 uint32_t offset; /* Offset within bar. */ 114 uint32_t length; /* Length of the structure, in bytes. */ 115 }; 116 117 struct virtio_pci_notify_cap { 118 struct virtio_pci_cap cap; 119 uint32_t notify_off_multiplier; /* Multiplier for queue_notify_off. */ 120 }; 121 122 /* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */ 123 struct virtio_pci_common_cfg { 124 /* About the whole device. */ 125 uint32_t device_feature_select; /* read-write */ 126 uint32_t device_feature; /* read-only */ 127 uint32_t guest_feature_select; /* read-write */ 128 uint32_t guest_feature; /* read-write */ 129 uint16_t msix_config; /* read-write */ 130 uint16_t num_queues; /* read-only */ 131 uint8_t device_status; /* read-write */ 132 uint8_t config_generation; /* read-only */ 133 134 /* About a specific virtqueue. */ 135 uint16_t queue_select; /* read-write */ 136 uint16_t queue_size; /* read-write, power of 2. */ 137 uint16_t queue_msix_vector; /* read-write */ 138 uint16_t queue_enable; /* read-write */ 139 uint16_t queue_notify_off; /* read-only */ 140 uint32_t queue_desc_lo; /* read-write */ 141 uint32_t queue_desc_hi; /* read-write */ 142 uint32_t queue_avail_lo; /* read-write */ 143 uint32_t queue_avail_hi; /* read-write */ 144 uint32_t queue_used_lo; /* read-write */ 145 uint32_t queue_used_hi; /* read-write */ 146 }; 147 148 struct virtio_crypto_hw; 149 150 struct virtio_pci_ops { 151 void (*read_dev_cfg)(struct virtio_crypto_hw *hw, size_t offset, 152 void *dst, int len); 153 void (*write_dev_cfg)(struct virtio_crypto_hw *hw, size_t offset, 154 const void *src, int len); 155 void (*reset)(struct virtio_crypto_hw *hw); 156 157 uint8_t (*get_status)(struct virtio_crypto_hw *hw); 158 void (*set_status)(struct virtio_crypto_hw *hw, uint8_t status); 159 160 uint64_t (*get_features)(struct virtio_crypto_hw *hw); 161 void (*set_features)(struct virtio_crypto_hw *hw, uint64_t features); 162 163 uint8_t (*get_isr)(struct virtio_crypto_hw *hw); 164 165 uint16_t (*set_config_irq)(struct virtio_crypto_hw *hw, uint16_t vec); 166 167 uint16_t (*set_queue_irq)(struct virtio_crypto_hw *hw, 168 struct virtqueue *vq, uint16_t vec); 169 170 uint16_t (*get_queue_num)(struct virtio_crypto_hw *hw, 171 uint16_t queue_id); 172 int (*setup_queue)(struct virtio_crypto_hw *hw, struct virtqueue *vq); 173 void (*del_queue)(struct virtio_crypto_hw *hw, struct virtqueue *vq); 174 void (*notify_queue)(struct virtio_crypto_hw *hw, struct virtqueue *vq); 175 }; 176 177 struct virtio_crypto_hw { 178 /* control queue */ 179 struct virtqueue *cvq; 180 uint16_t dev_id; 181 uint16_t max_dataqueues; 182 uint64_t req_guest_features; 183 uint64_t guest_features; 184 uint8_t use_msix; 185 uint8_t modern; 186 uint32_t notify_off_multiplier; 187 uint8_t *isr; 188 uint16_t *notify_base; 189 struct virtio_pci_common_cfg *common_cfg; 190 struct virtio_crypto_config *dev_cfg; 191 const struct rte_cryptodev_capabilities *virtio_dev_capabilities; 192 }; 193 194 /* 195 * While virtio_crypto_hw is stored in shared memory, this structure stores 196 * some infos that may vary in the multiple process model locally. 197 * For example, the vtpci_ops pointer. 198 */ 199 struct virtio_hw_internal { 200 const struct virtio_pci_ops *vtpci_ops; 201 struct rte_pci_ioport io; 202 }; 203 204 #define VTPCI_OPS(hw) (virtio_hw_internal[(hw)->dev_id].vtpci_ops) 205 #define VTPCI_IO(hw) (&virtio_hw_internal[(hw)->dev_id].io) 206 207 extern struct virtio_hw_internal virtio_hw_internal[RTE_MAX_VIRTIO_CRYPTO]; 208 209 /* 210 * How many bits to shift physical queue address written to QUEUE_PFN. 211 * 12 is historical, and due to x86 page size. 212 */ 213 #define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12 214 215 /* The alignment to use between consumer and producer parts of vring. */ 216 #define VIRTIO_PCI_VRING_ALIGN 4096 217 218 enum virtio_msix_status { 219 VIRTIO_MSIX_NONE = 0, 220 VIRTIO_MSIX_DISABLED = 1, 221 VIRTIO_MSIX_ENABLED = 2 222 }; 223 224 static inline int 225 vtpci_with_feature(struct virtio_crypto_hw *hw, uint64_t bit) 226 { 227 return (hw->guest_features & (1ULL << bit)) != 0; 228 } 229 230 /* 231 * Function declaration from virtio_pci.c 232 */ 233 int vtpci_cryptodev_init(struct rte_pci_device *dev, 234 struct virtio_crypto_hw *hw); 235 void vtpci_cryptodev_reset(struct virtio_crypto_hw *hw); 236 237 void vtpci_cryptodev_reinit_complete(struct virtio_crypto_hw *hw); 238 239 uint8_t vtpci_cryptodev_get_status(struct virtio_crypto_hw *hw); 240 void vtpci_cryptodev_set_status(struct virtio_crypto_hw *hw, uint8_t status); 241 242 uint64_t vtpci_cryptodev_negotiate_features(struct virtio_crypto_hw *hw, 243 uint64_t host_features); 244 245 void vtpci_write_cryptodev_config(struct virtio_crypto_hw *hw, size_t offset, 246 const void *src, int length); 247 248 void vtpci_read_cryptodev_config(struct virtio_crypto_hw *hw, size_t offset, 249 void *dst, int length); 250 251 uint8_t vtpci_cryptodev_isr(struct virtio_crypto_hw *hw); 252 253 #endif /* _VIRTIO_PCI_H_ */ 254