1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 HUAWEI TECHNOLOGIES CO., LTD.
3 */
4
5 #ifndef _VIRTIO_PCI_H_
6 #define _VIRTIO_PCI_H_
7
8 #include <stdint.h>
9
10 #include <rte_eal_paging.h>
11 #include <rte_pci.h>
12 #include <bus_pci_driver.h>
13 #include <rte_cryptodev.h>
14
15 #include "virtio_crypto.h"
16
17 struct virtqueue;
18
19 /* VirtIO PCI vendor/device ID. */
20 #define VIRTIO_CRYPTO_PCI_VENDORID 0x1AF4
21 #define VIRTIO_CRYPTO_PCI_DEVICEID 0x1054
22
23 /* VirtIO ABI version, this must match exactly. */
24 #define VIRTIO_PCI_ABI_VERSION 0
25
26 /*
27 * VirtIO Header, located in BAR 0.
28 */
29 #define VIRTIO_PCI_HOST_FEATURES 0 /* host's supported features (32bit, RO)*/
30 #define VIRTIO_PCI_GUEST_FEATURES 4 /* guest's supported features (32, RW) */
31 #define VIRTIO_PCI_QUEUE_PFN 8 /* physical address of VQ (32, RW) */
32 #define VIRTIO_PCI_QUEUE_NUM 12 /* number of ring entries (16, RO) */
33 #define VIRTIO_PCI_QUEUE_SEL 14 /* current VQ selection (16, RW) */
34 #define VIRTIO_PCI_QUEUE_NOTIFY 16 /* notify host regarding VQ (16, RW) */
35 #define VIRTIO_PCI_STATUS 18 /* device status register (8, RW) */
36 #define VIRTIO_PCI_ISR 19 /* interrupt status register, reading
37 * also clears the register (8, RO)
38 */
39 /* Only if MSIX is enabled: */
40
41 /* configuration change vector (16, RW) */
42 #define VIRTIO_MSI_CONFIG_VECTOR 20
43 /* vector for selected VQ notifications */
44 #define VIRTIO_MSI_QUEUE_VECTOR 22
45
46 /* The bit of the ISR which indicates a device has an interrupt. */
47 #define VIRTIO_PCI_ISR_INTR 0x1
48 /* The bit of the ISR which indicates a device configuration change. */
49 #define VIRTIO_PCI_ISR_CONFIG 0x2
50 /* Vector value used to disable MSI for queue. */
51 #define VIRTIO_MSI_NO_VECTOR 0xFFFF
52
53 /* Status byte for guest to report progress. */
54 #define VIRTIO_CONFIG_STATUS_RESET 0x00
55 #define VIRTIO_CONFIG_STATUS_ACK 0x01
56 #define VIRTIO_CONFIG_STATUS_DRIVER 0x02
57 #define VIRTIO_CONFIG_STATUS_DRIVER_OK 0x04
58 #define VIRTIO_CONFIG_STATUS_FEATURES_OK 0x08
59 #define VIRTIO_CONFIG_STATUS_FAILED 0x80
60
61 /*
62 * Each virtqueue indirect descriptor list must be physically contiguous.
63 * To allow us to malloc(9) each list individually, limit the number
64 * supported to what will fit in one page. With 4KB pages, this is a limit
65 * of 256 descriptors. If there is ever a need for more, we can switch to
66 * contigmalloc(9) for the larger allocations, similar to what
67 * bus_dmamem_alloc(9) does.
68 *
69 * Note the sizeof(struct vring_desc) is 16 bytes.
70 */
71 #define VIRTIO_MAX_INDIRECT ((int) (rte_mem_page_size() / 16))
72
73 /* Do we get callbacks when the ring is completely used, even if we've
74 * suppressed them?
75 */
76 #define VIRTIO_F_NOTIFY_ON_EMPTY 24
77
78 /* Can the device handle any descriptor layout? */
79 #define VIRTIO_F_ANY_LAYOUT 27
80
81 /* We support indirect buffer descriptors */
82 #define VIRTIO_RING_F_INDIRECT_DESC 28
83
84 #define VIRTIO_F_VERSION_1 32
85 #define VIRTIO_F_IOMMU_PLATFORM 33
86
87 /* The Guest publishes the used index for which it expects an interrupt
88 * at the end of the avail ring. Host should ignore the avail->flags field.
89 */
90 /* The Host publishes the avail index for which it expects a kick
91 * at the end of the used ring. Guest should ignore the used->flags field.
92 */
93 #define VIRTIO_RING_F_EVENT_IDX 29
94
95 /* Common configuration */
96 #define VIRTIO_PCI_CAP_COMMON_CFG 1
97 /* Notifications */
98 #define VIRTIO_PCI_CAP_NOTIFY_CFG 2
99 /* ISR Status */
100 #define VIRTIO_PCI_CAP_ISR_CFG 3
101 /* Device specific configuration */
102 #define VIRTIO_PCI_CAP_DEVICE_CFG 4
103 /* PCI configuration access */
104 #define VIRTIO_PCI_CAP_PCI_CFG 5
105
106 /* This is the PCI capability header: */
107 struct virtio_pci_cap {
108 uint8_t cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */
109 uint8_t cap_next; /* Generic PCI field: next ptr. */
110 uint8_t cap_len; /* Generic PCI field: capability length */
111 uint8_t cfg_type; /* Identifies the structure. */
112 uint8_t bar; /* Where to find it. */
113 uint8_t padding[3]; /* Pad to full dword. */
114 uint32_t offset; /* Offset within bar. */
115 uint32_t length; /* Length of the structure, in bytes. */
116 };
117
118 struct virtio_pci_notify_cap {
119 struct virtio_pci_cap cap;
120 uint32_t notify_off_multiplier; /* Multiplier for queue_notify_off. */
121 };
122
123 /* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */
124 struct virtio_pci_common_cfg {
125 /* About the whole device. */
126 uint32_t device_feature_select; /* read-write */
127 uint32_t device_feature; /* read-only */
128 uint32_t guest_feature_select; /* read-write */
129 uint32_t guest_feature; /* read-write */
130 uint16_t msix_config; /* read-write */
131 uint16_t num_queues; /* read-only */
132 uint8_t device_status; /* read-write */
133 uint8_t config_generation; /* read-only */
134
135 /* About a specific virtqueue. */
136 uint16_t queue_select; /* read-write */
137 uint16_t queue_size; /* read-write, power of 2. */
138 uint16_t queue_msix_vector; /* read-write */
139 uint16_t queue_enable; /* read-write */
140 uint16_t queue_notify_off; /* read-only */
141 uint32_t queue_desc_lo; /* read-write */
142 uint32_t queue_desc_hi; /* read-write */
143 uint32_t queue_avail_lo; /* read-write */
144 uint32_t queue_avail_hi; /* read-write */
145 uint32_t queue_used_lo; /* read-write */
146 uint32_t queue_used_hi; /* read-write */
147 };
148
149 struct virtio_crypto_hw;
150
151 struct virtio_pci_ops {
152 void (*read_dev_cfg)(struct virtio_crypto_hw *hw, size_t offset,
153 void *dst, int len);
154 void (*write_dev_cfg)(struct virtio_crypto_hw *hw, size_t offset,
155 const void *src, int len);
156 void (*reset)(struct virtio_crypto_hw *hw);
157
158 uint8_t (*get_status)(struct virtio_crypto_hw *hw);
159 void (*set_status)(struct virtio_crypto_hw *hw, uint8_t status);
160
161 uint64_t (*get_features)(struct virtio_crypto_hw *hw);
162 void (*set_features)(struct virtio_crypto_hw *hw, uint64_t features);
163
164 uint8_t (*get_isr)(struct virtio_crypto_hw *hw);
165
166 uint16_t (*set_config_irq)(struct virtio_crypto_hw *hw, uint16_t vec);
167
168 uint16_t (*set_queue_irq)(struct virtio_crypto_hw *hw,
169 struct virtqueue *vq, uint16_t vec);
170
171 uint16_t (*get_queue_num)(struct virtio_crypto_hw *hw,
172 uint16_t queue_id);
173 int (*setup_queue)(struct virtio_crypto_hw *hw, struct virtqueue *vq);
174 void (*del_queue)(struct virtio_crypto_hw *hw, struct virtqueue *vq);
175 void (*notify_queue)(struct virtio_crypto_hw *hw, struct virtqueue *vq);
176 };
177
178 struct virtio_crypto_hw {
179 /* control queue */
180 struct virtqueue *cvq;
181 uint16_t dev_id;
182 uint16_t max_dataqueues;
183 uint64_t req_guest_features;
184 uint64_t guest_features;
185 uint8_t use_msix;
186 uint8_t modern;
187 uint32_t notify_off_multiplier;
188 uint8_t *isr;
189 uint16_t *notify_base;
190 struct virtio_pci_common_cfg *common_cfg;
191 struct virtio_crypto_config *dev_cfg;
192 const struct rte_cryptodev_capabilities *virtio_dev_capabilities;
193 };
194
195 /*
196 * While virtio_crypto_hw is stored in shared memory, this structure stores
197 * some infos that may vary in the multiple process model locally.
198 * For example, the vtpci_ops pointer.
199 */
200 struct virtio_hw_internal {
201 const struct virtio_pci_ops *vtpci_ops;
202 struct rte_pci_ioport io;
203 };
204
205 #define VTPCI_OPS(hw) (crypto_virtio_hw_internal[(hw)->dev_id].vtpci_ops)
206 #define VTPCI_IO(hw) (&crypto_virtio_hw_internal[(hw)->dev_id].io)
207
208 extern struct virtio_hw_internal crypto_virtio_hw_internal[RTE_MAX_VIRTIO_CRYPTO];
209
210 /*
211 * How many bits to shift physical queue address written to QUEUE_PFN.
212 * 12 is historical, and due to x86 page size.
213 */
214 #define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12
215
216 /* The alignment to use between consumer and producer parts of vring. */
217 #define VIRTIO_PCI_VRING_ALIGN 4096
218
219 enum virtio_msix_status {
220 VIRTIO_MSIX_NONE = 0,
221 VIRTIO_MSIX_DISABLED = 1,
222 VIRTIO_MSIX_ENABLED = 2
223 };
224
225 static inline int
vtpci_with_feature(struct virtio_crypto_hw * hw,uint64_t bit)226 vtpci_with_feature(struct virtio_crypto_hw *hw, uint64_t bit)
227 {
228 return (hw->guest_features & (1ULL << bit)) != 0;
229 }
230
231 /*
232 * Function declaration from virtio_pci.c
233 */
234 int vtpci_cryptodev_init(struct rte_pci_device *dev,
235 struct virtio_crypto_hw *hw);
236 void vtpci_cryptodev_reset(struct virtio_crypto_hw *hw);
237
238 void vtpci_cryptodev_reinit_complete(struct virtio_crypto_hw *hw);
239
240 uint8_t vtpci_cryptodev_get_status(struct virtio_crypto_hw *hw);
241 void vtpci_cryptodev_set_status(struct virtio_crypto_hw *hw, uint8_t status);
242
243 uint64_t vtpci_cryptodev_negotiate_features(struct virtio_crypto_hw *hw,
244 uint64_t host_features);
245
246 void vtpci_write_cryptodev_config(struct virtio_crypto_hw *hw, size_t offset,
247 const void *src, int length);
248
249 void vtpci_read_cryptodev_config(struct virtio_crypto_hw *hw, size_t offset,
250 void *dst, int length);
251
252 uint8_t vtpci_cryptodev_isr(struct virtio_crypto_hw *hw);
253
254 #endif /* _VIRTIO_PCI_H_ */
255