1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017-2022 Intel Corporation
3 */
4
5 #include <rte_cryptodev.h>
6 #include <cryptodev_pmd.h>
7 #include "qat_asym.h"
8 #include "qat_crypto.h"
9 #include "qat_crypto_pmd_gens.h"
10
11 struct rte_cryptodev_ops qat_asym_crypto_ops_gen1 = {
12 /* Device related operations */
13 .dev_configure = qat_cryptodev_config,
14 .dev_start = qat_cryptodev_start,
15 .dev_stop = qat_cryptodev_stop,
16 .dev_close = qat_cryptodev_close,
17 .dev_infos_get = qat_cryptodev_info_get,
18
19 .stats_get = qat_cryptodev_stats_get,
20 .stats_reset = qat_cryptodev_stats_reset,
21 .queue_pair_setup = qat_cryptodev_qp_setup,
22 .queue_pair_release = qat_cryptodev_qp_release,
23
24 /* Crypto related operations */
25 .asym_session_get_size = qat_asym_session_get_private_size,
26 .asym_session_configure = qat_asym_session_configure,
27 .asym_session_clear = qat_asym_session_clear
28 };
29
30 static struct rte_cryptodev_capabilities qat_asym_crypto_caps_gen1[] = {
31 QAT_ASYM_CAP(MODEX,
32 0, 1, 512, 1),
33 QAT_ASYM_CAP(MODINV,
34 0, 1, 512, 1),
35 QAT_ASYM_CAP(RSA,
36 ((1 << RTE_CRYPTO_ASYM_OP_SIGN) |
37 (1 << RTE_CRYPTO_ASYM_OP_VERIFY) |
38 (1 << RTE_CRYPTO_ASYM_OP_ENCRYPT) |
39 (1 << RTE_CRYPTO_ASYM_OP_DECRYPT)),
40 64, 512, 64),
41 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
42 };
43
44 int
qat_asym_crypto_cap_get_gen1(struct qat_cryptodev_private * internals,const char * capa_memz_name,const uint16_t __rte_unused slice_map)45 qat_asym_crypto_cap_get_gen1(struct qat_cryptodev_private *internals,
46 const char *capa_memz_name,
47 const uint16_t __rte_unused slice_map)
48 {
49 const uint32_t size = sizeof(qat_asym_crypto_caps_gen1);
50 uint32_t i;
51
52 internals->capa_mz = rte_memzone_lookup(capa_memz_name);
53 if (internals->capa_mz == NULL) {
54 internals->capa_mz = rte_memzone_reserve(capa_memz_name,
55 size, rte_socket_id(), 0);
56 if (internals->capa_mz == NULL) {
57 QAT_LOG(DEBUG,
58 "Error allocating memzone for capabilities");
59 return -1;
60 }
61 }
62
63 struct rte_cryptodev_capabilities *addr =
64 (struct rte_cryptodev_capabilities *)
65 internals->capa_mz->addr;
66 const struct rte_cryptodev_capabilities *capabilities =
67 qat_asym_crypto_caps_gen1;
68 const uint32_t capa_num =
69 size / sizeof(struct rte_cryptodev_capabilities);
70 uint32_t curr_capa = 0;
71
72 for (i = 0; i < capa_num; i++) {
73 memcpy(addr + curr_capa, capabilities + i,
74 sizeof(struct rte_cryptodev_capabilities));
75 curr_capa++;
76 }
77 internals->qat_dev_capabilities = internals->capa_mz->addr;
78
79 return 0;
80 }
81
82 uint64_t
qat_asym_crypto_feature_flags_get_gen1(struct qat_pci_device * qat_dev __rte_unused)83 qat_asym_crypto_feature_flags_get_gen1(
84 struct qat_pci_device *qat_dev __rte_unused)
85 {
86 uint64_t feature_flags = RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO |
87 RTE_CRYPTODEV_FF_HW_ACCELERATED |
88 RTE_CRYPTODEV_FF_ASYM_SESSIONLESS |
89 RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_EXP |
90 RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT;
91
92 return feature_flags;
93 }
94
95 int
qat_asym_crypto_set_session_gen1(void * cdev __rte_unused,void * session __rte_unused)96 qat_asym_crypto_set_session_gen1(void *cdev __rte_unused,
97 void *session __rte_unused)
98 {
99 return 0;
100 }
101
RTE_INIT(qat_asym_crypto_gen1_init)102 RTE_INIT(qat_asym_crypto_gen1_init)
103 {
104 qat_asym_gen_dev_ops[QAT_GEN1].cryptodev_ops =
105 &qat_asym_crypto_ops_gen1;
106 qat_asym_gen_dev_ops[QAT_GEN1].get_capabilities =
107 qat_asym_crypto_cap_get_gen1;
108 qat_asym_gen_dev_ops[QAT_GEN1].get_feature_flags =
109 qat_asym_crypto_feature_flags_get_gen1;
110 }
111