1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 */ 4 5 #ifndef _CCP_DEV_H_ 6 #define _CCP_DEV_H_ 7 8 #include <limits.h> 9 #include <stdbool.h> 10 #include <stdint.h> 11 #include <string.h> 12 13 #include <rte_bus_pci.h> 14 #include <rte_atomic.h> 15 #include <rte_byteorder.h> 16 #include <rte_io.h> 17 #include <rte_pci.h> 18 #include <rte_spinlock.h> 19 #include <rte_crypto_sym.h> 20 #include <rte_cryptodev.h> 21 22 /**< CCP sspecific */ 23 #define MAX_HW_QUEUES 5 24 25 /**< CCP Register Mappings */ 26 #define Q_MASK_REG 0x000 27 #define TRNG_OUT_REG 0x00c 28 29 /* CCP Version 5 Specifics */ 30 #define CMD_QUEUE_MASK_OFFSET 0x00 31 #define CMD_QUEUE_PRIO_OFFSET 0x04 32 #define CMD_REQID_CONFIG_OFFSET 0x08 33 #define CMD_CMD_TIMEOUT_OFFSET 0x10 34 #define LSB_PUBLIC_MASK_LO_OFFSET 0x18 35 #define LSB_PUBLIC_MASK_HI_OFFSET 0x1C 36 #define LSB_PRIVATE_MASK_LO_OFFSET 0x20 37 #define LSB_PRIVATE_MASK_HI_OFFSET 0x24 38 39 #define CMD_Q_CONTROL_BASE 0x0000 40 #define CMD_Q_TAIL_LO_BASE 0x0004 41 #define CMD_Q_HEAD_LO_BASE 0x0008 42 #define CMD_Q_INT_ENABLE_BASE 0x000C 43 #define CMD_Q_INTERRUPT_STATUS_BASE 0x0010 44 45 #define CMD_Q_STATUS_BASE 0x0100 46 #define CMD_Q_INT_STATUS_BASE 0x0104 47 48 #define CMD_CONFIG_0_OFFSET 0x6000 49 #define CMD_TRNG_CTL_OFFSET 0x6008 50 #define CMD_AES_MASK_OFFSET 0x6010 51 #define CMD_CLK_GATE_CTL_OFFSET 0x603C 52 53 /* Address offset between two virtual queue registers */ 54 #define CMD_Q_STATUS_INCR 0x1000 55 56 /* Bit masks */ 57 #define CMD_Q_RUN 0x1 58 #define CMD_Q_SIZE 0x1F 59 #define CMD_Q_SHIFT 3 60 #define COMMANDS_PER_QUEUE 2048 61 62 #define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \ 63 CMD_Q_SIZE) 64 #define Q_DESC_SIZE sizeof(struct ccp_desc) 65 #define Q_SIZE(n) (COMMANDS_PER_QUEUE*(n)) 66 67 #define INT_COMPLETION 0x1 68 #define INT_ERROR 0x2 69 #define INT_QUEUE_STOPPED 0x4 70 #define ALL_INTERRUPTS (INT_COMPLETION| \ 71 INT_ERROR| \ 72 INT_QUEUE_STOPPED) 73 74 #define LSB_REGION_WIDTH 5 75 #define MAX_LSB_CNT 8 76 77 #define LSB_SIZE 16 78 #define LSB_ITEM_SIZE 32 79 #define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE) 80 81 /* General CCP Defines */ 82 83 #define CCP_SB_BYTES 32 84 85 /* bitmap */ 86 enum { 87 BITS_PER_WORD = sizeof(unsigned long) * CHAR_BIT 88 }; 89 90 #define WORD_OFFSET(b) ((b) / BITS_PER_WORD) 91 #define BIT_OFFSET(b) ((b) % BITS_PER_WORD) 92 93 #define CCP_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 94 #define CCP_BITMAP_SIZE(nr) \ 95 CCP_DIV_ROUND_UP(nr, CHAR_BIT * sizeof(unsigned long)) 96 97 #define CCP_BITMAP_FIRST_WORD_MASK(start) \ 98 (~0UL << ((start) & (BITS_PER_WORD - 1))) 99 #define CCP_BITMAP_LAST_WORD_MASK(nbits) \ 100 (~0UL >> (-(nbits) & (BITS_PER_WORD - 1))) 101 102 #define __ccp_round_mask(x, y) ((typeof(x))((y)-1)) 103 #define ccp_round_down(x, y) ((x) & ~__ccp_round_mask(x, y)) 104 105 /** CCP registers Write/Read */ 106 107 static inline void ccp_pci_reg_write(void *base, int offset, 108 uint32_t value) 109 { 110 volatile void *reg_addr = ((uint8_t *)base + offset); 111 112 rte_write32((rte_cpu_to_le_32(value)), reg_addr); 113 } 114 115 static inline uint32_t ccp_pci_reg_read(void *base, int offset) 116 { 117 volatile void *reg_addr = ((uint8_t *)base + offset); 118 119 return rte_le_to_cpu_32(rte_read32(reg_addr)); 120 } 121 122 #define CCP_READ_REG(hw_addr, reg_offset) \ 123 ccp_pci_reg_read(hw_addr, reg_offset) 124 125 #define CCP_WRITE_REG(hw_addr, reg_offset, value) \ 126 ccp_pci_reg_write(hw_addr, reg_offset, value) 127 128 TAILQ_HEAD(ccp_list, ccp_device); 129 130 extern struct ccp_list ccp_list; 131 132 /** 133 * CCP device version 134 */ 135 enum ccp_device_version { 136 CCP_VERSION_5A = 0, 137 CCP_VERSION_5B, 138 }; 139 140 /** 141 * A structure describing a CCP command queue. 142 */ 143 struct ccp_queue { 144 struct ccp_device *dev; 145 char memz_name[RTE_MEMZONE_NAMESIZE]; 146 147 rte_atomic64_t free_slots; 148 /**< available free slots updated from enq/deq calls */ 149 150 /* Queue identifier */ 151 uint64_t id; /**< queue id */ 152 uint64_t qidx; /**< queue index */ 153 uint64_t qsize; /**< queue size */ 154 155 /* Queue address */ 156 struct ccp_desc *qbase_desc; 157 void *qbase_addr; 158 phys_addr_t qbase_phys_addr; 159 /**< queue-page registers addr */ 160 void *reg_base; 161 162 uint32_t qcontrol; 163 /**< queue ctrl reg */ 164 165 int lsb; 166 /**< lsb region assigned to queue */ 167 unsigned long lsbmask; 168 /**< lsb regions queue can access */ 169 unsigned long lsbmap[CCP_BITMAP_SIZE(LSB_SIZE)]; 170 /**< all lsb resources which queue is using */ 171 uint32_t sb_key; 172 /**< lsb assigned for queue */ 173 uint32_t sb_iv; 174 /**< lsb assigned for iv */ 175 uint32_t sb_sha; 176 /**< lsb assigned for sha ctx */ 177 uint32_t sb_hmac; 178 /**< lsb assigned for hmac ctx */ 179 } ____cacheline_aligned; 180 181 /** 182 * A structure describing a CCP device. 183 */ 184 struct ccp_device { 185 TAILQ_ENTRY(ccp_device) next; 186 int id; 187 /**< ccp dev id on platform */ 188 struct ccp_queue cmd_q[MAX_HW_QUEUES]; 189 /**< ccp queue */ 190 int cmd_q_count; 191 /**< no. of ccp Queues */ 192 struct rte_pci_device pci; 193 /**< ccp pci identifier */ 194 unsigned long lsbmap[CCP_BITMAP_SIZE(SLSB_MAP_SIZE)]; 195 /**< shared lsb mask of ccp */ 196 rte_spinlock_t lsb_lock; 197 /**< protection for shared lsb region allocation */ 198 int qidx; 199 /**< current queue index */ 200 } __rte_cache_aligned; 201 202 /** 203 * descriptor for version 5 CPP commands 204 * 8 32-bit words: 205 * word 0: function; engine; control bits 206 * word 1: length of source data 207 * word 2: low 32 bits of source pointer 208 * word 3: upper 16 bits of source pointer; source memory type 209 * word 4: low 32 bits of destination pointer 210 * word 5: upper 16 bits of destination pointer; destination memory 211 * type 212 * word 6: low 32 bits of key pointer 213 * word 7: upper 16 bits of key pointer; key memory type 214 */ 215 struct dword0 { 216 uint32_t soc:1; 217 uint32_t ioc:1; 218 uint32_t rsvd1:1; 219 uint32_t init:1; 220 uint32_t eom:1; 221 uint32_t function:15; 222 uint32_t engine:4; 223 uint32_t prot:1; 224 uint32_t rsvd2:7; 225 }; 226 227 struct dword3 { 228 uint32_t src_hi:16; 229 uint32_t src_mem:2; 230 uint32_t lsb_cxt_id:8; 231 uint32_t rsvd1:5; 232 uint32_t fixed:1; 233 }; 234 235 union dword4 { 236 uint32_t dst_lo; /* NON-SHA */ 237 uint32_t sha_len_lo; /* SHA */ 238 }; 239 240 union dword5 { 241 struct { 242 uint32_t dst_hi:16; 243 uint32_t dst_mem:2; 244 uint32_t rsvd1:13; 245 uint32_t fixed:1; 246 } 247 fields; 248 uint32_t sha_len_hi; 249 }; 250 251 struct dword7 { 252 uint32_t key_hi:16; 253 uint32_t key_mem:2; 254 uint32_t rsvd1:14; 255 }; 256 257 struct ccp_desc { 258 struct dword0 dw0; 259 uint32_t length; 260 uint32_t src_lo; 261 struct dword3 dw3; 262 union dword4 dw4; 263 union dword5 dw5; 264 uint32_t key_lo; 265 struct dword7 dw7; 266 }; 267 268 static inline uint32_t 269 low32_value(unsigned long addr) 270 { 271 return ((uint64_t)addr) & 0x0ffffffff; 272 } 273 274 static inline uint32_t 275 high32_value(unsigned long addr) 276 { 277 return ((uint64_t)addr >> 32) & 0x00000ffff; 278 } 279 280 /* 281 * Start CCP device 282 */ 283 int ccp_dev_start(struct rte_cryptodev *dev); 284 285 /** 286 * Detect ccp platform and initialize all ccp devices 287 * 288 * @param ccp_id rte_pci_id list for supported CCP devices 289 * @return no. of successfully initialized CCP devices 290 */ 291 int ccp_probe_devices(const struct rte_pci_id *ccp_id); 292 293 #endif /* _CCP_DEV_H_ */ 294