1INTERNAL { 2 global: 3 4 efx_crc32_calculate; 5 6 efx_ev_fini; 7 efx_ev_init; 8 efx_ev_qcreate; 9 efx_ev_qcreate_check_init_done; 10 efx_ev_qcreate_irq; 11 efx_ev_qdestroy; 12 efx_ev_qmoderate; 13 efx_ev_qpending; 14 efx_ev_qpoll; 15 efx_ev_qpost; 16 efx_ev_qprime; 17 efx_ev_usecs_to_ticks; 18 19 efx_evb_fini; 20 efx_evb_init; 21 efx_evb_vport_mac_set; 22 efx_evb_vport_reset; 23 efx_evb_vport_stats; 24 efx_evb_vport_vlan_set; 25 efx_evb_vswitch_create; 26 efx_evb_vswitch_destroy; 27 28 efx_evq_nbufs; 29 efx_evq_size; 30 31 efx_family; 32 efx_family_probe_bar; 33 34 efx_filter_fini; 35 efx_filter_init; 36 efx_filter_insert; 37 efx_filter_remove; 38 efx_filter_restore; 39 efx_filter_spec_init_rx; 40 efx_filter_spec_init_tx; 41 efx_filter_spec_set_encap_type; 42 efx_filter_spec_set_eth_local; 43 efx_filter_spec_set_ether_type; 44 efx_filter_spec_set_geneve; 45 efx_filter_spec_set_ipv4_full; 46 efx_filter_spec_set_ipv4_local; 47 efx_filter_spec_set_mc_def; 48 efx_filter_spec_set_nvgre; 49 efx_filter_spec_set_rss_context; 50 efx_filter_spec_set_uc_def; 51 efx_filter_spec_set_vxlan; 52 efx_filter_supported_filters; 53 54 efx_hash_bytes; 55 efx_hash_dwords; 56 57 efx_intr_disable; 58 efx_intr_disable_unlocked; 59 efx_intr_enable; 60 efx_intr_fatal; 61 efx_intr_fini; 62 efx_intr_init; 63 efx_intr_status_line; 64 efx_intr_status_message; 65 efx_intr_trigger; 66 67 efx_loopback_mask; 68 efx_loopback_type_name; 69 70 efx_mac_addr_set; 71 efx_mac_drain; 72 efx_mac_fcntl_get; 73 efx_mac_fcntl_set; 74 efx_mac_include_fcs_set; 75 efx_mac_filter_default_rxq_clear; 76 efx_mac_filter_default_rxq_set; 77 efx_mac_filter_get_all_ucast_mcast; 78 efx_mac_filter_set; 79 efx_mac_multicast_list_set; 80 efx_mac_pdu_get; 81 efx_mac_pdu_set; 82 efx_mac_stat_name; 83 efx_mac_stats_clear; 84 efx_mac_stats_get_mask; 85 efx_mac_stats_periodic; 86 efx_mac_stats_update; 87 efx_mac_stats_upload; 88 efx_mac_up; 89 90 efx_mae_action_rule_insert; 91 efx_mae_action_rule_remove; 92 efx_mae_action_set_alloc; 93 efx_mae_action_set_clear_fw_rsrc_ids; 94 efx_mae_action_set_fill_in_counter_id; 95 efx_mae_action_set_fill_in_dst_mac_id; 96 efx_mae_action_set_fill_in_eh_id; 97 efx_mae_action_set_fill_in_src_mac_id; 98 efx_mae_action_set_free; 99 efx_mae_action_set_get_nb_count; 100 efx_mae_action_set_list_alloc; 101 efx_mae_action_set_list_free; 102 efx_mae_action_set_populate_count; 103 efx_mae_action_set_populate_decap; 104 efx_mae_action_set_populate_decr_ip_ttl; 105 efx_mae_action_set_populate_deliver; 106 efx_mae_action_set_populate_drop; 107 efx_mae_action_set_populate_encap; 108 efx_mae_action_set_populate_flag; 109 efx_mae_action_set_populate_mark; 110 efx_mae_action_set_populate_mark_reset; 111 efx_mae_action_set_populate_nat; 112 efx_mae_action_set_populate_set_dst_mac; 113 efx_mae_action_set_populate_set_src_mac; 114 efx_mae_action_set_populate_vlan_pop; 115 efx_mae_action_set_populate_vlan_push; 116 efx_mae_action_set_replay; 117 efx_mae_action_set_spec_fini; 118 efx_mae_action_set_spec_init; 119 efx_mae_action_set_specs_equal; 120 efx_mae_counters_alloc; 121 efx_mae_counters_alloc_type; 122 efx_mae_counters_free; 123 efx_mae_counters_free_type; 124 efx_mae_counters_stream_give_credits; 125 efx_mae_counters_stream_start; 126 efx_mae_counters_stream_stop; 127 efx_mae_encap_header_alloc; 128 efx_mae_encap_header_free; 129 efx_mae_encap_header_update; 130 efx_mae_fini; 131 efx_mae_get_limits; 132 efx_mae_init; 133 efx_mae_mac_addr_alloc; 134 efx_mae_mac_addr_free; 135 efx_mae_match_spec_bit_set; 136 efx_mae_match_spec_clone; 137 efx_mae_match_spec_ct_mark_set; 138 efx_mae_match_spec_field_get; 139 efx_mae_match_spec_field_set; 140 efx_mae_match_spec_fini; 141 efx_mae_match_spec_init; 142 efx_mae_match_spec_is_valid; 143 efx_mae_match_spec_mport_set; 144 efx_mae_match_spec_outer_rule_id_set; 145 efx_mae_match_spec_recirc_id_set; 146 efx_mae_match_specs_class_cmp; 147 efx_mae_match_specs_equal; 148 efx_mae_mport_by_pcie_function; 149 efx_mae_mport_by_pcie_mh_function; 150 efx_mae_mport_by_phy_port; 151 efx_mae_mport_by_id; 152 efx_mae_mport_free; 153 efx_mae_mport_id_by_selector; 154 efx_mae_mport_invalid; 155 efx_mae_outer_rule_do_ct_set; 156 efx_mae_outer_rule_insert; 157 efx_mae_outer_rule_recirc_id_set; 158 efx_mae_outer_rule_remove; 159 efx_mae_read_mport_journal; 160 161 efx_mcdi_client_mac_addr_get; 162 efx_mcdi_client_mac_addr_set; 163 efx_mcdi_fini; 164 efx_mcdi_get_client_handle; 165 efx_mcdi_get_own_client_handle; 166 efx_mcdi_get_proxy_handle; 167 efx_mcdi_get_timeout; 168 efx_mcdi_init; 169 efx_mcdi_mport_alloc_alias; 170 efx_mcdi_new_epoch; 171 efx_mcdi_reboot; 172 efx_mcdi_request_abort; 173 efx_mcdi_request_poll; 174 efx_mcdi_request_start; 175 176 efx_mon_fini; 177 efx_mon_init; 178 efx_mon_name; 179 180 efx_nic_calculate_pcie_link_bandwidth; 181 efx_nic_cfg_get; 182 efx_nic_check_pcie_link_speed; 183 efx_nic_create; 184 efx_nic_destroy; 185 efx_nic_dma_config_add; 186 efx_nic_dma_map; 187 efx_nic_dma_reconfigure; 188 efx_nic_fini; 189 efx_nic_get_bar_region; 190 efx_nic_get_board_info; 191 efx_nic_get_fw_subvariant; 192 efx_nic_get_fw_version; 193 efx_nic_get_vi_pool; 194 efx_nic_hw_unavailable; 195 efx_nic_init; 196 efx_nic_probe; 197 efx_nic_reset; 198 efx_nic_set_drv_limits; 199 efx_nic_set_drv_version; 200 efx_nic_set_fw_subvariant; 201 efx_nic_set_hw_unavailable; 202 efx_nic_unprobe; 203 204 efx_phy_adv_cap_get; 205 efx_phy_adv_cap_set; 206 efx_phy_fec_type_get; 207 efx_phy_link_state_get; 208 efx_phy_lp_cap_get; 209 efx_phy_media_type_get; 210 efx_phy_module_get_info; 211 efx_phy_oui_get; 212 efx_phy_verify; 213 214 efx_port_fini; 215 efx_port_init; 216 efx_port_loopback_set; 217 efx_port_poll; 218 efx_port_vlan_strip_set; 219 220 efx_pseudo_hdr_hash_get; 221 efx_pseudo_hdr_pkt_length_get; 222 223 efx_rx_fini; 224 efx_rx_hash_default_support_get; 225 efx_rx_init; 226 efx_rx_prefix_get_layout; 227 efx_rx_prefix_layout_check; 228 efx_rx_qcreate; 229 efx_rx_qcreate_es_super_buffer; 230 efx_rx_qdestroy; 231 efx_rx_qenable; 232 efx_rx_qflush; 233 efx_rx_qpost; 234 efx_rx_qpush; 235 efx_rx_scale_context_alloc; 236 efx_rx_scale_context_alloc_v2; 237 efx_rx_scale_context_free; 238 efx_rx_scale_default_support_get; 239 efx_rx_scale_hash_flags_get; 240 efx_rx_scale_key_set; 241 efx_rx_scale_mode_set; 242 efx_rx_scale_tbl_set; 243 efx_rxq_nbufs; 244 efx_rxq_size; 245 246 efx_sram_buf_tbl_clear; 247 efx_sram_buf_tbl_set; 248 249 efx_table_describe; 250 efx_table_entry_delete; 251 efx_table_entry_insert; 252 efx_table_is_supported; 253 efx_table_list; 254 efx_table_supported_num_get; 255 256 efx_tunnel_config_clear; 257 efx_tunnel_config_udp_add; 258 efx_tunnel_config_udp_remove; 259 efx_tunnel_fini; 260 efx_tunnel_init; 261 efx_tunnel_reconfigure; 262 263 efx_tx_fini; 264 efx_tx_init; 265 efx_tx_qcreate; 266 efx_tx_qdesc_checksum_create; 267 efx_tx_qdesc_dma_create; 268 efx_tx_qdesc_post; 269 efx_tx_qdesc_tso_create; 270 efx_tx_qdesc_tso2_create; 271 efx_tx_qdesc_vlantci_create; 272 efx_tx_qdestroy; 273 efx_tx_qenable; 274 efx_tx_qflush; 275 efx_tx_qpace; 276 efx_tx_qpio_disable; 277 efx_tx_qpio_enable; 278 efx_tx_qpio_post; 279 efx_tx_qpio_write; 280 efx_tx_qpost; 281 efx_tx_qpush; 282 efx_txq_nbufs; 283 efx_txq_size; 284 285 efx_virtio_fini; 286 efx_virtio_get_doorbell_offset; 287 efx_virtio_get_features; 288 efx_virtio_init; 289 efx_virtio_qcreate; 290 efx_virtio_qdestroy; 291 efx_virtio_qstart; 292 efx_virtio_qstop; 293 efx_virtio_verify_features; 294 295 sfc_efx_dev_class_get; 296 sfc_efx_family; 297 298 sfc_efx_mcdi_init; 299 sfc_efx_mcdi_fini; 300 301 local: *; 302}; 303