1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2015-2019 Solarflare Communications Inc.
5 */
6
7 #include "efx.h"
8 #include "efx_impl.h"
9
10
11 #if EFSYS_OPT_MEDFORD
12
13 static __checkReturn efx_rc_t
medford_nic_get_required_pcie_bandwidth(__in efx_nic_t * enp,__out uint32_t * bandwidth_mbpsp)14 medford_nic_get_required_pcie_bandwidth(
15 __in efx_nic_t *enp,
16 __out uint32_t *bandwidth_mbpsp)
17 {
18 uint32_t bandwidth;
19 efx_rc_t rc;
20
21 if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
22 &bandwidth)) != 0)
23 goto fail1;
24
25 *bandwidth_mbpsp = bandwidth;
26
27 return (0);
28
29 fail1:
30 EFSYS_PROBE1(fail1, efx_rc_t, rc);
31
32 return (rc);
33 }
34
35 __checkReturn efx_rc_t
medford_board_cfg(__in efx_nic_t * enp)36 medford_board_cfg(
37 __in efx_nic_t *enp)
38 {
39 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
40 uint32_t sysclk, dpcpu_clk;
41 uint32_t end_padding;
42 uint32_t bandwidth;
43 efx_rc_t rc;
44
45 /*
46 * Event queue creation is complete when an
47 * EVQ_INIT_DONE_EV event is received.
48 */
49 encp->enc_evq_init_done_ev_supported = B_TRUE;
50
51 /*
52 * Enable firmware workarounds for hardware errata.
53 * Expected responses are:
54 * - 0 (zero):
55 * Success: workaround enabled or disabled as requested.
56 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
57 * Firmware does not support the MC_CMD_WORKAROUND request.
58 * (assume that the workaround is not supported).
59 * - MC_CMD_ERR_ENOENT (reported as ENOENT):
60 * Firmware does not support the requested workaround.
61 * - MC_CMD_ERR_EPERM (reported as EACCES):
62 * Unprivileged function cannot enable/disable workarounds.
63 *
64 * See efx_mcdi_request_errcode() for MCDI error translations.
65 */
66
67
68 if (EFX_PCI_FUNCTION_IS_VF(encp)) {
69 /*
70 * Interrupt testing does not work for VFs. See bug50084 and
71 * bug71432 comment 21.
72 */
73 encp->enc_bug41750_workaround = B_TRUE;
74 }
75
76 /*
77 * If the bug61265 workaround is enabled, then interrupt holdoff timers
78 * cannot be controlled by timer table writes, so MCDI must be used
79 * (timer table writes can still be used for wakeup timers).
80 */
81 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE,
82 NULL);
83 if ((rc == 0) || (rc == EACCES))
84 encp->enc_bug61265_workaround = B_TRUE;
85 else if ((rc == ENOTSUP) || (rc == ENOENT))
86 encp->enc_bug61265_workaround = B_FALSE;
87 else
88 goto fail1;
89
90 /* Checksums for TSO sends can be incorrect on Medford. */
91 encp->enc_bug61297_workaround = B_TRUE;
92
93 /* Get clock frequencies (in MHz). */
94 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
95 goto fail2;
96
97 /*
98 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
99 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
100 */
101 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */
102 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
103 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
104
105 encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
106 encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
107 encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
108
109 /* Alignment for receive packet DMA buffers */
110 encp->enc_rx_buf_align_start = 1;
111
112 /* Get the RX DMA end padding alignment configuration */
113 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
114 if (rc != EACCES)
115 goto fail3;
116
117 /* Assume largest tail padding size supported by hardware */
118 end_padding = 256;
119 }
120 encp->enc_rx_buf_align_end = end_padding;
121
122 encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
123 encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
124
125 encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
126 encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
127
128 /*
129 * The maximum supported transmit queue size is 2048. TXQs with 4096
130 * descriptors are not supported as the top bit is used for vfifo
131 * stuffing.
132 */
133 encp->enc_txq_max_ndescs = MEDFORD_TXQ_MAXNDESCS;
134 encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
135
136 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
137 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
138 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
139 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
140
141 /*
142 * Medford stores a single global copy of VPD, not per-PF as on
143 * Huntington.
144 */
145 encp->enc_vpd_is_global = B_TRUE;
146
147 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
148 if (rc != 0)
149 goto fail4;
150 encp->enc_required_pcie_bandwidth_mbps = bandwidth;
151 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
152
153 encp->enc_table_api_supported = B_FALSE;
154
155 return (0);
156
157 fail4:
158 EFSYS_PROBE(fail4);
159 fail3:
160 EFSYS_PROBE(fail3);
161 fail2:
162 EFSYS_PROBE(fail2);
163 fail1:
164 EFSYS_PROBE1(fail1, efx_rc_t, rc);
165
166 return (rc);
167 }
168
169 #endif /* EFSYS_OPT_MEDFORD */
170