1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2007-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_REGS_PCI_H 8 #define _SYS_EFX_REGS_PCI_H 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /* 15 * PC_VEND_ID_REG(16bit): 16 * Vendor ID register 17 */ 18 19 #define PCR_AZ_VEND_ID_REG 0x00000000 20 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 21 22 #define PCRF_AZ_VEND_ID_LBN 0 23 #define PCRF_AZ_VEND_ID_WIDTH 16 24 25 26 /* 27 * PC_DEV_ID_REG(16bit): 28 * Device ID register 29 */ 30 31 #define PCR_AZ_DEV_ID_REG 0x00000002 32 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 33 34 #define PCRF_AZ_DEV_ID_LBN 0 35 #define PCRF_AZ_DEV_ID_WIDTH 16 36 37 38 /* 39 * PC_CMD_REG(16bit): 40 * Command register 41 */ 42 43 #define PCR_AZ_CMD_REG 0x00000004 44 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 45 46 #define PCRF_AZ_INTX_DIS_LBN 10 47 #define PCRF_AZ_INTX_DIS_WIDTH 1 48 #define PCRF_AZ_FB2B_EN_LBN 9 49 #define PCRF_AZ_FB2B_EN_WIDTH 1 50 #define PCRF_AZ_SERR_EN_LBN 8 51 #define PCRF_AZ_SERR_EN_WIDTH 1 52 #define PCRF_AZ_IDSEL_CTL_LBN 7 53 #define PCRF_AZ_IDSEL_CTL_WIDTH 1 54 #define PCRF_AZ_PERR_EN_LBN 6 55 #define PCRF_AZ_PERR_EN_WIDTH 1 56 #define PCRF_AZ_VGA_PAL_SNP_LBN 5 57 #define PCRF_AZ_VGA_PAL_SNP_WIDTH 1 58 #define PCRF_AZ_MWI_EN_LBN 4 59 #define PCRF_AZ_MWI_EN_WIDTH 1 60 #define PCRF_AZ_SPEC_CYC_LBN 3 61 #define PCRF_AZ_SPEC_CYC_WIDTH 1 62 #define PCRF_AZ_MST_EN_LBN 2 63 #define PCRF_AZ_MST_EN_WIDTH 1 64 #define PCRF_AZ_MEM_EN_LBN 1 65 #define PCRF_AZ_MEM_EN_WIDTH 1 66 #define PCRF_AZ_IO_EN_LBN 0 67 #define PCRF_AZ_IO_EN_WIDTH 1 68 69 70 /* 71 * PC_STAT_REG(16bit): 72 * Status register 73 */ 74 75 #define PCR_AZ_STAT_REG 0x00000006 76 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 77 78 #define PCRF_AZ_DET_PERR_LBN 15 79 #define PCRF_AZ_DET_PERR_WIDTH 1 80 #define PCRF_AZ_SIG_SERR_LBN 14 81 #define PCRF_AZ_SIG_SERR_WIDTH 1 82 #define PCRF_AZ_GOT_MABRT_LBN 13 83 #define PCRF_AZ_GOT_MABRT_WIDTH 1 84 #define PCRF_AZ_GOT_TABRT_LBN 12 85 #define PCRF_AZ_GOT_TABRT_WIDTH 1 86 #define PCRF_AZ_SIG_TABRT_LBN 11 87 #define PCRF_AZ_SIG_TABRT_WIDTH 1 88 #define PCRF_AZ_DEVSEL_TIM_LBN 9 89 #define PCRF_AZ_DEVSEL_TIM_WIDTH 2 90 #define PCRF_AZ_MDAT_PERR_LBN 8 91 #define PCRF_AZ_MDAT_PERR_WIDTH 1 92 #define PCRF_AZ_FB2B_CAP_LBN 7 93 #define PCRF_AZ_FB2B_CAP_WIDTH 1 94 #define PCRF_AZ_66MHZ_CAP_LBN 5 95 #define PCRF_AZ_66MHZ_CAP_WIDTH 1 96 #define PCRF_AZ_CAP_LIST_LBN 4 97 #define PCRF_AZ_CAP_LIST_WIDTH 1 98 #define PCRF_AZ_INTX_STAT_LBN 3 99 #define PCRF_AZ_INTX_STAT_WIDTH 1 100 101 102 /* 103 * PC_REV_ID_REG(8bit): 104 * Class code & revision ID register 105 */ 106 107 #define PCR_AZ_REV_ID_REG 0x00000008 108 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 109 110 #define PCRF_AZ_REV_ID_LBN 0 111 #define PCRF_AZ_REV_ID_WIDTH 8 112 113 114 /* 115 * PC_CC_REG(24bit): 116 * Class code register 117 */ 118 119 #define PCR_AZ_CC_REG 0x00000009 120 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 121 122 #define PCRF_AZ_BASE_CC_LBN 16 123 #define PCRF_AZ_BASE_CC_WIDTH 8 124 #define PCRF_AZ_SUB_CC_LBN 8 125 #define PCRF_AZ_SUB_CC_WIDTH 8 126 #define PCRF_AZ_PROG_IF_LBN 0 127 #define PCRF_AZ_PROG_IF_WIDTH 8 128 129 130 /* 131 * PC_CACHE_LSIZE_REG(8bit): 132 * Cache line size 133 */ 134 135 #define PCR_AZ_CACHE_LSIZE_REG 0x0000000c 136 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 137 138 #define PCRF_AZ_CACHE_LSIZE_LBN 0 139 #define PCRF_AZ_CACHE_LSIZE_WIDTH 8 140 141 142 /* 143 * PC_MST_LAT_REG(8bit): 144 * Master latency timer register 145 */ 146 147 #define PCR_AZ_MST_LAT_REG 0x0000000d 148 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 149 150 #define PCRF_AZ_MST_LAT_LBN 0 151 #define PCRF_AZ_MST_LAT_WIDTH 8 152 153 154 /* 155 * PC_HDR_TYPE_REG(8bit): 156 * Header type register 157 */ 158 159 #define PCR_AZ_HDR_TYPE_REG 0x0000000e 160 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 161 162 #define PCRF_AZ_MULT_FUNC_LBN 7 163 #define PCRF_AZ_MULT_FUNC_WIDTH 1 164 #define PCRF_AZ_TYPE_LBN 0 165 #define PCRF_AZ_TYPE_WIDTH 7 166 167 168 /* 169 * PC_BIST_REG(8bit): 170 * BIST register 171 */ 172 173 #define PCR_AZ_BIST_REG 0x0000000f 174 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 175 176 #define PCRF_AZ_BIST_LBN 0 177 #define PCRF_AZ_BIST_WIDTH 8 178 179 180 /* 181 * PC_BAR0_REG(32bit): 182 * Primary function base address register 0 183 */ 184 185 #define PCR_AZ_BAR0_REG 0x00000010 186 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 187 188 #define PCRF_AZ_BAR0_LBN 4 189 #define PCRF_AZ_BAR0_WIDTH 28 190 #define PCRF_AZ_BAR0_PREF_LBN 3 191 #define PCRF_AZ_BAR0_PREF_WIDTH 1 192 #define PCRF_AZ_BAR0_TYPE_LBN 1 193 #define PCRF_AZ_BAR0_TYPE_WIDTH 2 194 #define PCRF_AZ_BAR0_IOM_LBN 0 195 #define PCRF_AZ_BAR0_IOM_WIDTH 1 196 197 198 /* 199 * PC_BAR1_REG(32bit): 200 * Primary function base address register 1, BAR1 is not implemented so read only. 201 */ 202 203 #define PCR_DZ_BAR1_REG 0x00000014 204 /* hunta0=pci_f0_config */ 205 206 #define PCRF_DZ_BAR1_LBN 0 207 #define PCRF_DZ_BAR1_WIDTH 32 208 209 210 /* 211 * PC_BAR2_LO_REG(32bit): 212 * Primary function base address register 2 low bits 213 */ 214 215 #define PCR_AZ_BAR2_LO_REG 0x00000018 216 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 217 218 #define PCRF_AZ_BAR2_LO_LBN 4 219 #define PCRF_AZ_BAR2_LO_WIDTH 28 220 #define PCRF_AZ_BAR2_PREF_LBN 3 221 #define PCRF_AZ_BAR2_PREF_WIDTH 1 222 #define PCRF_AZ_BAR2_TYPE_LBN 1 223 #define PCRF_AZ_BAR2_TYPE_WIDTH 2 224 #define PCRF_AZ_BAR2_IOM_LBN 0 225 #define PCRF_AZ_BAR2_IOM_WIDTH 1 226 227 228 /* 229 * PC_BAR2_HI_REG(32bit): 230 * Primary function base address register 2 high bits 231 */ 232 233 #define PCR_AZ_BAR2_HI_REG 0x0000001c 234 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 235 236 #define PCRF_AZ_BAR2_HI_LBN 0 237 #define PCRF_AZ_BAR2_HI_WIDTH 32 238 239 240 /* 241 * PC_BAR4_LO_REG(32bit): 242 * Primary function base address register 2 low bits 243 */ 244 245 #define PCR_CZ_BAR4_LO_REG 0x00000020 246 /* sienaa0,hunta0=pci_f0_config */ 247 248 #define PCRF_CZ_BAR4_LO_LBN 4 249 #define PCRF_CZ_BAR4_LO_WIDTH 28 250 #define PCRF_CZ_BAR4_PREF_LBN 3 251 #define PCRF_CZ_BAR4_PREF_WIDTH 1 252 #define PCRF_CZ_BAR4_TYPE_LBN 1 253 #define PCRF_CZ_BAR4_TYPE_WIDTH 2 254 #define PCRF_CZ_BAR4_IOM_LBN 0 255 #define PCRF_CZ_BAR4_IOM_WIDTH 1 256 257 258 /* 259 * PC_BAR4_HI_REG(32bit): 260 * Primary function base address register 2 high bits 261 */ 262 263 #define PCR_CZ_BAR4_HI_REG 0x00000024 264 /* sienaa0,hunta0=pci_f0_config */ 265 266 #define PCRF_CZ_BAR4_HI_LBN 0 267 #define PCRF_CZ_BAR4_HI_WIDTH 32 268 269 270 /* 271 * PC_SS_VEND_ID_REG(16bit): 272 * Sub-system vendor ID register 273 */ 274 275 #define PCR_AZ_SS_VEND_ID_REG 0x0000002c 276 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 277 278 #define PCRF_AZ_SS_VEND_ID_LBN 0 279 #define PCRF_AZ_SS_VEND_ID_WIDTH 16 280 281 282 /* 283 * PC_SS_ID_REG(16bit): 284 * Sub-system ID register 285 */ 286 287 #define PCR_AZ_SS_ID_REG 0x0000002e 288 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 289 290 #define PCRF_AZ_SS_ID_LBN 0 291 #define PCRF_AZ_SS_ID_WIDTH 16 292 293 294 /* 295 * PC_EXPROM_BAR_REG(32bit): 296 * Expansion ROM base address register 297 */ 298 299 #define PCR_AZ_EXPROM_BAR_REG 0x00000030 300 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 301 302 #define PCRF_AZ_EXPROM_BAR_LBN 11 303 #define PCRF_AZ_EXPROM_BAR_WIDTH 21 304 #define PCRF_AB_EXPROM_MIN_SIZE_LBN 2 305 #define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9 306 #define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1 307 #define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10 308 #define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1 309 #define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1 310 #define PCRF_AZ_EXPROM_EN_LBN 0 311 #define PCRF_AZ_EXPROM_EN_WIDTH 1 312 313 314 /* 315 * PC_CAP_PTR_REG(8bit): 316 * Capability pointer register 317 */ 318 319 #define PCR_AZ_CAP_PTR_REG 0x00000034 320 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 321 322 #define PCRF_AZ_CAP_PTR_LBN 0 323 #define PCRF_AZ_CAP_PTR_WIDTH 8 324 325 326 /* 327 * PC_INT_LINE_REG(8bit): 328 * Interrupt line register 329 */ 330 331 #define PCR_AZ_INT_LINE_REG 0x0000003c 332 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 333 334 #define PCRF_AZ_INT_LINE_LBN 0 335 #define PCRF_AZ_INT_LINE_WIDTH 8 336 337 338 /* 339 * PC_INT_PIN_REG(8bit): 340 * Interrupt pin register 341 */ 342 343 #define PCR_AZ_INT_PIN_REG 0x0000003d 344 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 345 346 #define PCRF_AZ_INT_PIN_LBN 0 347 #define PCRF_AZ_INT_PIN_WIDTH 8 348 #define PCFE_DZ_INTPIN_INTD 4 349 #define PCFE_DZ_INTPIN_INTC 3 350 #define PCFE_DZ_INTPIN_INTB 2 351 #define PCFE_DZ_INTPIN_INTA 1 352 353 354 /* 355 * PC_PM_CAP_ID_REG(8bit): 356 * Power management capability ID 357 */ 358 359 #define PCR_AZ_PM_CAP_ID_REG 0x00000040 360 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 361 362 #define PCRF_AZ_PM_CAP_ID_LBN 0 363 #define PCRF_AZ_PM_CAP_ID_WIDTH 8 364 365 366 /* 367 * PC_PM_NXT_PTR_REG(8bit): 368 * Power management next item pointer 369 */ 370 371 #define PCR_AZ_PM_NXT_PTR_REG 0x00000041 372 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 373 374 #define PCRF_AZ_PM_NXT_PTR_LBN 0 375 #define PCRF_AZ_PM_NXT_PTR_WIDTH 8 376 377 378 /* 379 * PC_PM_CAP_REG(16bit): 380 * Power management capabilities register 381 */ 382 383 #define PCR_AZ_PM_CAP_REG 0x00000042 384 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 385 386 #define PCRF_AZ_PM_PME_SUPT_LBN 11 387 #define PCRF_AZ_PM_PME_SUPT_WIDTH 5 388 #define PCRF_AZ_PM_D2_SUPT_LBN 10 389 #define PCRF_AZ_PM_D2_SUPT_WIDTH 1 390 #define PCRF_AZ_PM_D1_SUPT_LBN 9 391 #define PCRF_AZ_PM_D1_SUPT_WIDTH 1 392 #define PCRF_AZ_PM_AUX_CURR_LBN 6 393 #define PCRF_AZ_PM_AUX_CURR_WIDTH 3 394 #define PCRF_AZ_PM_DSI_LBN 5 395 #define PCRF_AZ_PM_DSI_WIDTH 1 396 #define PCRF_AZ_PM_PME_CLK_LBN 3 397 #define PCRF_AZ_PM_PME_CLK_WIDTH 1 398 #define PCRF_AZ_PM_PME_VER_LBN 0 399 #define PCRF_AZ_PM_PME_VER_WIDTH 3 400 401 402 /* 403 * PC_PM_CS_REG(16bit): 404 * Power management control & status register 405 */ 406 407 #define PCR_AZ_PM_CS_REG 0x00000044 408 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 409 410 #define PCRF_AZ_PM_PME_STAT_LBN 15 411 #define PCRF_AZ_PM_PME_STAT_WIDTH 1 412 #define PCRF_AZ_PM_DAT_SCALE_LBN 13 413 #define PCRF_AZ_PM_DAT_SCALE_WIDTH 2 414 #define PCRF_AZ_PM_DAT_SEL_LBN 9 415 #define PCRF_AZ_PM_DAT_SEL_WIDTH 4 416 #define PCRF_AZ_PM_PME_EN_LBN 8 417 #define PCRF_AZ_PM_PME_EN_WIDTH 1 418 #define PCRF_CZ_NO_SOFT_RESET_LBN 3 419 #define PCRF_CZ_NO_SOFT_RESET_WIDTH 1 420 #define PCRF_AZ_PM_PWR_ST_LBN 0 421 #define PCRF_AZ_PM_PWR_ST_WIDTH 2 422 423 424 /* 425 * PC_MSI_CAP_ID_REG(8bit): 426 * MSI capability ID 427 */ 428 429 #define PCR_AZ_MSI_CAP_ID_REG 0x00000050 430 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 431 432 #define PCRF_AZ_MSI_CAP_ID_LBN 0 433 #define PCRF_AZ_MSI_CAP_ID_WIDTH 8 434 435 436 /* 437 * PC_MSI_NXT_PTR_REG(8bit): 438 * MSI next item pointer 439 */ 440 441 #define PCR_AZ_MSI_NXT_PTR_REG 0x00000051 442 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 443 444 #define PCRF_AZ_MSI_NXT_PTR_LBN 0 445 #define PCRF_AZ_MSI_NXT_PTR_WIDTH 8 446 447 448 /* 449 * PC_MSI_CTL_REG(16bit): 450 * MSI control register 451 */ 452 453 #define PCR_AZ_MSI_CTL_REG 0x00000052 454 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 455 456 #define PCRF_AZ_MSI_64_EN_LBN 7 457 #define PCRF_AZ_MSI_64_EN_WIDTH 1 458 #define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4 459 #define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3 460 #define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1 461 #define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3 462 #define PCRF_AZ_MSI_EN_LBN 0 463 #define PCRF_AZ_MSI_EN_WIDTH 1 464 465 466 /* 467 * PC_MSI_ADR_LO_REG(32bit): 468 * MSI low 32 bits address register 469 */ 470 471 #define PCR_AZ_MSI_ADR_LO_REG 0x00000054 472 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 473 474 #define PCRF_AZ_MSI_ADR_LO_LBN 2 475 #define PCRF_AZ_MSI_ADR_LO_WIDTH 30 476 477 478 /* 479 * PC_MSI_ADR_HI_REG(32bit): 480 * MSI high 32 bits address register 481 */ 482 483 #define PCR_AZ_MSI_ADR_HI_REG 0x00000058 484 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 485 486 #define PCRF_AZ_MSI_ADR_HI_LBN 0 487 #define PCRF_AZ_MSI_ADR_HI_WIDTH 32 488 489 490 /* 491 * PC_MSI_DAT_REG(16bit): 492 * MSI data register 493 */ 494 495 #define PCR_AZ_MSI_DAT_REG 0x0000005c 496 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 497 498 #define PCRF_AZ_MSI_DAT_LBN 0 499 #define PCRF_AZ_MSI_DAT_WIDTH 16 500 501 502 /* 503 * PC_PCIE_CAP_LIST_REG(16bit): 504 * PCIe capability list register 505 */ 506 507 #define PCR_AB_PCIE_CAP_LIST_REG 0x00000060 508 /* falcona0,falconb0=pci_f0_config */ 509 510 #define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070 511 /* sienaa0,hunta0=pci_f0_config */ 512 513 #define PCRF_AZ_PCIE_NXT_PTR_LBN 8 514 #define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8 515 #define PCRF_AZ_PCIE_CAP_ID_LBN 0 516 #define PCRF_AZ_PCIE_CAP_ID_WIDTH 8 517 518 519 /* 520 * PC_PCIE_CAP_REG(16bit): 521 * PCIe capability register 522 */ 523 524 #define PCR_AB_PCIE_CAP_REG 0x00000062 525 /* falcona0,falconb0=pci_f0_config */ 526 527 #define PCR_CZ_PCIE_CAP_REG 0x00000072 528 /* sienaa0,hunta0=pci_f0_config */ 529 530 #define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9 531 #define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5 532 #define PCRF_AZ_PCIE_SLOT_IMP_LBN 8 533 #define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1 534 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4 535 #define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4 536 #define PCRF_AZ_PCIE_CAP_VER_LBN 0 537 #define PCRF_AZ_PCIE_CAP_VER_WIDTH 4 538 539 540 /* 541 * PC_DEV_CAP_REG(32bit): 542 * PCIe device capabilities register 543 */ 544 545 #define PCR_AB_DEV_CAP_REG 0x00000064 546 /* falcona0,falconb0=pci_f0_config */ 547 548 #define PCR_CZ_DEV_CAP_REG 0x00000074 549 /* sienaa0=pci_f0_config,hunta0=pci_f0_config */ 550 551 #define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28 552 #define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1 553 #define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26 554 #define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2 555 #define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18 556 #define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8 557 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15 558 #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1 559 #define PCRF_AB_PWR_IND_LBN 14 560 #define PCRF_AB_PWR_IND_WIDTH 1 561 #define PCRF_AB_ATTN_IND_LBN 13 562 #define PCRF_AB_ATTN_IND_WIDTH 1 563 #define PCRF_AB_ATTN_BUTTON_LBN 12 564 #define PCRF_AB_ATTN_BUTTON_WIDTH 1 565 #define PCRF_AZ_ENDPT_L1_LAT_LBN 9 566 #define PCRF_AZ_ENDPT_L1_LAT_WIDTH 3 567 #define PCRF_AZ_ENDPT_L0_LAT_LBN 6 568 #define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3 569 #define PCRF_AZ_TAG_FIELD_LBN 5 570 #define PCRF_AZ_TAG_FIELD_WIDTH 1 571 #define PCRF_AZ_PHAN_FUNC_LBN 3 572 #define PCRF_AZ_PHAN_FUNC_WIDTH 2 573 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0 574 #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3 575 576 577 /* 578 * PC_DEV_CTL_REG(16bit): 579 * PCIe device control register 580 */ 581 582 #define PCR_AB_DEV_CTL_REG 0x00000068 583 /* falcona0,falconb0=pci_f0_config */ 584 585 #define PCR_CZ_DEV_CTL_REG 0x00000078 586 /* sienaa0,hunta0=pci_f0_config */ 587 588 #define PCRF_CZ_FN_LEVEL_RESET_LBN 15 589 #define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1 590 #define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12 591 #define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3 592 #define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5 593 #define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4 594 #define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3 595 #define PCFE_AZ_MAX_RD_REQ_SIZE_512 2 596 #define PCFE_AZ_MAX_RD_REQ_SIZE_256 1 597 #define PCFE_AZ_MAX_RD_REQ_SIZE_128 0 598 #define PCRF_AZ_EN_NO_SNOOP_LBN 11 599 #define PCRF_AZ_EN_NO_SNOOP_WIDTH 1 600 #define PCRF_AZ_AUX_PWR_PM_EN_LBN 10 601 #define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1 602 #define PCRF_AZ_PHAN_FUNC_EN_LBN 9 603 #define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1 604 #define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8 605 #define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1 606 #define PCRF_CZ_EXTENDED_TAG_EN_LBN 8 607 #define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1 608 #define PCRF_AZ_MAX_PAYL_SIZE_LBN 5 609 #define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3 610 #define PCFE_AZ_MAX_PAYL_SIZE_4096 5 611 #define PCFE_AZ_MAX_PAYL_SIZE_2048 4 612 #define PCFE_AZ_MAX_PAYL_SIZE_1024 3 613 #define PCFE_AZ_MAX_PAYL_SIZE_512 2 614 #define PCFE_AZ_MAX_PAYL_SIZE_256 1 615 #define PCFE_AZ_MAX_PAYL_SIZE_128 0 616 #define PCRF_AZ_EN_RELAX_ORDER_LBN 4 617 #define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1 618 #define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3 619 #define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1 620 #define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2 621 #define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1 622 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1 623 #define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1 624 #define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0 625 #define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1 626 627 628 /* 629 * PC_DEV_STAT_REG(16bit): 630 * PCIe device status register 631 */ 632 633 #define PCR_AB_DEV_STAT_REG 0x0000006a 634 /* falcona0,falconb0=pci_f0_config */ 635 636 #define PCR_CZ_DEV_STAT_REG 0x0000007a 637 /* sienaa0,hunta0=pci_f0_config */ 638 639 #define PCRF_AZ_TRNS_PEND_LBN 5 640 #define PCRF_AZ_TRNS_PEND_WIDTH 1 641 #define PCRF_AZ_AUX_PWR_DET_LBN 4 642 #define PCRF_AZ_AUX_PWR_DET_WIDTH 1 643 #define PCRF_AZ_UNSUP_REQ_DET_LBN 3 644 #define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1 645 #define PCRF_AZ_FATAL_ERR_DET_LBN 2 646 #define PCRF_AZ_FATAL_ERR_DET_WIDTH 1 647 #define PCRF_AZ_NONFATAL_ERR_DET_LBN 1 648 #define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1 649 #define PCRF_AZ_CORR_ERR_DET_LBN 0 650 #define PCRF_AZ_CORR_ERR_DET_WIDTH 1 651 652 653 /* 654 * PC_LNK_CAP_REG(32bit): 655 * PCIe link capabilities register 656 */ 657 658 #define PCR_AB_LNK_CAP_REG 0x0000006c 659 /* falcona0,falconb0=pci_f0_config */ 660 661 #define PCR_CZ_LNK_CAP_REG 0x0000007c 662 /* sienaa0,hunta0=pci_f0_config */ 663 664 #define PCRF_AZ_PORT_NUM_LBN 24 665 #define PCRF_AZ_PORT_NUM_WIDTH 8 666 #define PCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22 667 #define PCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1 668 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21 669 #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1 670 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20 671 #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1 672 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19 673 #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1 674 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18 675 #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1 676 #define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15 677 #define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3 678 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12 679 #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3 680 #define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10 681 #define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2 682 #define PCRF_AZ_MAX_LNK_WIDTH_LBN 4 683 #define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6 684 #define PCRF_AZ_MAX_LNK_SP_LBN 0 685 #define PCRF_AZ_MAX_LNK_SP_WIDTH 4 686 687 688 /* 689 * PC_LNK_CTL_REG(16bit): 690 * PCIe link control register 691 */ 692 693 #define PCR_AB_LNK_CTL_REG 0x00000070 694 /* falcona0,falconb0=pci_f0_config */ 695 696 #define PCR_CZ_LNK_CTL_REG 0x00000080 697 /* sienaa0,hunta0=pci_f0_config */ 698 699 #define PCRF_AZ_EXT_SYNC_LBN 7 700 #define PCRF_AZ_EXT_SYNC_WIDTH 1 701 #define PCRF_AZ_COMM_CLK_CFG_LBN 6 702 #define PCRF_AZ_COMM_CLK_CFG_WIDTH 1 703 #define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5 704 #define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1 705 #define PCRF_CZ_LNK_RETRAIN_LBN 5 706 #define PCRF_CZ_LNK_RETRAIN_WIDTH 1 707 #define PCRF_AZ_LNK_DIS_LBN 4 708 #define PCRF_AZ_LNK_DIS_WIDTH 1 709 #define PCRF_AZ_RD_COM_BDRY_LBN 3 710 #define PCRF_AZ_RD_COM_BDRY_WIDTH 1 711 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0 712 #define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2 713 714 715 /* 716 * PC_LNK_STAT_REG(16bit): 717 * PCIe link status register 718 */ 719 720 #define PCR_AB_LNK_STAT_REG 0x00000072 721 /* falcona0,falconb0=pci_f0_config */ 722 723 #define PCR_CZ_LNK_STAT_REG 0x00000082 724 /* sienaa0,hunta0=pci_f0_config */ 725 726 #define PCRF_AZ_SLOT_CLK_CFG_LBN 12 727 #define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1 728 #define PCRF_AZ_LNK_TRAIN_LBN 11 729 #define PCRF_AZ_LNK_TRAIN_WIDTH 1 730 #define PCRF_AB_TRAIN_ERR_LBN 10 731 #define PCRF_AB_TRAIN_ERR_WIDTH 1 732 #define PCRF_AZ_LNK_WIDTH_LBN 4 733 #define PCRF_AZ_LNK_WIDTH_WIDTH 6 734 #define PCRF_AZ_LNK_SP_LBN 0 735 #define PCRF_AZ_LNK_SP_WIDTH 4 736 737 738 /* 739 * PC_SLOT_CAP_REG(32bit): 740 * PCIe slot capabilities register 741 */ 742 743 #define PCR_AB_SLOT_CAP_REG 0x00000074 744 /* falcona0,falconb0=pci_f0_config */ 745 746 #define PCRF_AB_SLOT_NUM_LBN 19 747 #define PCRF_AB_SLOT_NUM_WIDTH 13 748 #define PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15 749 #define PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2 750 #define PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7 751 #define PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8 752 #define PCRF_AB_SLOT_HP_CAP_LBN 6 753 #define PCRF_AB_SLOT_HP_CAP_WIDTH 1 754 #define PCRF_AB_SLOT_HP_SURP_LBN 5 755 #define PCRF_AB_SLOT_HP_SURP_WIDTH 1 756 #define PCRF_AB_SLOT_PWR_IND_PRST_LBN 4 757 #define PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1 758 #define PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3 759 #define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1 760 #define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2 761 #define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1 762 #define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1 763 #define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1 764 #define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0 765 #define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1 766 767 768 /* 769 * PC_SLOT_CTL_REG(16bit): 770 * PCIe slot control register 771 */ 772 773 #define PCR_AB_SLOT_CTL_REG 0x00000078 774 /* falcona0,falconb0=pci_f0_config */ 775 776 #define PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10 777 #define PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1 778 #define PCRF_AB_SLOT_PWR_IND_CTL_LBN 8 779 #define PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2 780 #define PCRF_AB_SLOT_ATT_IND_CTL_LBN 6 781 #define PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2 782 #define PCRF_AB_SLOT_HP_INT_EN_LBN 5 783 #define PCRF_AB_SLOT_HP_INT_EN_WIDTH 1 784 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4 785 #define PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1 786 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3 787 #define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1 788 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2 789 #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1 790 #define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1 791 #define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1 792 #define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0 793 #define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1 794 795 796 /* 797 * PC_SLOT_STAT_REG(16bit): 798 * PCIe slot status register 799 */ 800 801 #define PCR_AB_SLOT_STAT_REG 0x0000007a 802 /* falcona0,falconb0=pci_f0_config */ 803 804 #define PCRF_AB_PRES_DET_ST_LBN 6 805 #define PCRF_AB_PRES_DET_ST_WIDTH 1 806 #define PCRF_AB_MRL_SENS_ST_LBN 5 807 #define PCRF_AB_MRL_SENS_ST_WIDTH 1 808 #define PCRF_AB_SLOT_PWR_IND_LBN 4 809 #define PCRF_AB_SLOT_PWR_IND_WIDTH 1 810 #define PCRF_AB_SLOT_ATTN_IND_LBN 3 811 #define PCRF_AB_SLOT_ATTN_IND_WIDTH 1 812 #define PCRF_AB_SLOT_MRL_SENS_LBN 2 813 #define PCRF_AB_SLOT_MRL_SENS_WIDTH 1 814 #define PCRF_AB_PWR_FLTDET_LBN 1 815 #define PCRF_AB_PWR_FLTDET_WIDTH 1 816 #define PCRF_AB_ATTN_BUTDET_LBN 0 817 #define PCRF_AB_ATTN_BUTDET_WIDTH 1 818 819 820 /* 821 * PC_MSIX_CAP_ID_REG(8bit): 822 * MSIX Capability ID 823 */ 824 825 #define PCR_BB_MSIX_CAP_ID_REG 0x00000090 826 /* falconb0=pci_f0_config */ 827 828 #define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0 829 /* sienaa0,hunta0=pci_f0_config */ 830 831 #define PCRF_BZ_MSIX_CAP_ID_LBN 0 832 #define PCRF_BZ_MSIX_CAP_ID_WIDTH 8 833 834 835 /* 836 * PC_MSIX_NXT_PTR_REG(8bit): 837 * MSIX Capability Next Capability Ptr 838 */ 839 840 #define PCR_BB_MSIX_NXT_PTR_REG 0x00000091 841 /* falconb0=pci_f0_config */ 842 843 #define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1 844 /* sienaa0,hunta0=pci_f0_config */ 845 846 #define PCRF_BZ_MSIX_NXT_PTR_LBN 0 847 #define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8 848 849 850 /* 851 * PC_MSIX_CTL_REG(16bit): 852 * MSIX control register 853 */ 854 855 #define PCR_BB_MSIX_CTL_REG 0x00000092 856 /* falconb0=pci_f0_config */ 857 858 #define PCR_CZ_MSIX_CTL_REG 0x000000b2 859 /* sienaa0,hunta0=pci_f0_config */ 860 861 #define PCRF_BZ_MSIX_EN_LBN 15 862 #define PCRF_BZ_MSIX_EN_WIDTH 1 863 #define PCRF_BZ_MSIX_FUNC_MASK_LBN 14 864 #define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1 865 #define PCRF_BZ_MSIX_TBL_SIZE_LBN 0 866 #define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11 867 868 869 /* 870 * PC_MSIX_TBL_BASE_REG(32bit): 871 * MSIX Capability Vector Table Base 872 */ 873 874 #define PCR_BB_MSIX_TBL_BASE_REG 0x00000094 875 /* falconb0=pci_f0_config */ 876 877 #define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4 878 /* sienaa0,hunta0=pci_f0_config */ 879 880 #define PCRF_BZ_MSIX_TBL_OFF_LBN 3 881 #define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29 882 #define PCRF_BZ_MSIX_TBL_BIR_LBN 0 883 #define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3 884 885 886 /* 887 * PC_DEV_CAP2_REG(32bit): 888 * PCIe Device Capabilities 2 889 */ 890 891 #define PCR_CZ_DEV_CAP2_REG 0x00000094 892 /* sienaa0=pci_f0_config,hunta0=pci_f0_config */ 893 894 #define PCRF_DZ_OBFF_SUPPORTED_LBN 18 895 #define PCRF_DZ_OBFF_SUPPORTED_WIDTH 2 896 #define PCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12 897 #define PCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2 898 #define PCRF_DZ_LTR_M_SUPPORTED_LBN 11 899 #define PCRF_DZ_LTR_M_SUPPORTED_WIDTH 1 900 #define PCRF_CC_CMPL_TIMEOUT_DIS_LBN 4 901 #define PCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1 902 #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4 903 #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1 904 #define PCRF_CZ_CMPL_TIMEOUT_LBN 0 905 #define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4 906 #define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14 907 #define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13 908 #define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10 909 #define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9 910 #define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6 911 #define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5 912 #define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2 913 #define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1 914 #define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0 915 916 917 /* 918 * PC_DEV_CTL2_REG(16bit): 919 * PCIe Device Control 2 920 */ 921 922 #define PCR_CZ_DEV_CTL2_REG 0x00000098 923 /* sienaa0,hunta0=pci_f0_config */ 924 925 #define PCRF_DZ_OBFF_ENABLE_LBN 13 926 #define PCRF_DZ_OBFF_ENABLE_WIDTH 2 927 #define PCRF_DZ_LTR_ENABLE_LBN 10 928 #define PCRF_DZ_LTR_ENABLE_WIDTH 1 929 #define PCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9 930 #define PCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1 931 #define PCRF_DZ_IDO_REQUEST_ENABLE_LBN 8 932 #define PCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1 933 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4 934 #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1 935 #define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0 936 #define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4 937 938 939 /* 940 * PC_MSIX_PBA_BASE_REG(32bit): 941 * MSIX Capability PBA Base 942 */ 943 944 #define PCR_BB_MSIX_PBA_BASE_REG 0x00000098 945 /* falconb0=pci_f0_config */ 946 947 #define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8 948 /* sienaa0,hunta0=pci_f0_config */ 949 950 #define PCRF_BZ_MSIX_PBA_OFF_LBN 3 951 #define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29 952 #define PCRF_BZ_MSIX_PBA_BIR_LBN 0 953 #define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3 954 955 956 /* 957 * PC_LNK_CAP2_REG(32bit): 958 * PCIe Link Capability 2 959 */ 960 961 #define PCR_DZ_LNK_CAP2_REG 0x0000009c 962 /* hunta0=pci_f0_config */ 963 964 #define PCRF_DZ_LNK_SPEED_SUP_LBN 1 965 #define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7 966 967 968 /* 969 * PC_LNK_CTL2_REG(16bit): 970 * PCIe Link Control 2 971 */ 972 973 #define PCR_CZ_LNK_CTL2_REG 0x000000a0 974 /* sienaa0,hunta0=pci_f0_config */ 975 976 #define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12 977 #define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1 978 #define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11 979 #define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1 980 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10 981 #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1 982 #define PCRF_CZ_TRANSMIT_MARGIN_LBN 7 983 #define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3 984 #define PCRF_CZ_SELECT_DEEMPH_LBN 6 985 #define PCRF_CZ_SELECT_DEEMPH_WIDTH 1 986 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5 987 #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1 988 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4 989 #define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1 990 #define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0 991 #define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4 992 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN3 3 993 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2 994 #define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1 995 996 997 /* 998 * PC_LNK_STAT2_REG(16bit): 999 * PCIe Link Status 2 1000 */ 1001 1002 #define PCR_CZ_LNK_STAT2_REG 0x000000a2 1003 /* sienaa0,hunta0=pci_f0_config */ 1004 1005 #define PCRF_CZ_CURRENT_DEEMPH_LBN 0 1006 #define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1 1007 1008 1009 /* 1010 * PC_VPD_CAP_ID_REG(8bit): 1011 * VPD data register 1012 */ 1013 1014 #define PCR_AB_VPD_CAP_ID_REG 0x000000b0 1015 /* falcona0,falconb0=pci_f0_config */ 1016 1017 #define PCRF_AB_VPD_CAP_ID_LBN 0 1018 #define PCRF_AB_VPD_CAP_ID_WIDTH 8 1019 1020 1021 /* 1022 * PC_VPD_NXT_PTR_REG(8bit): 1023 * VPD next item pointer 1024 */ 1025 1026 #define PCR_AB_VPD_NXT_PTR_REG 0x000000b1 1027 /* falcona0,falconb0=pci_f0_config */ 1028 1029 #define PCRF_AB_VPD_NXT_PTR_LBN 0 1030 #define PCRF_AB_VPD_NXT_PTR_WIDTH 8 1031 1032 1033 /* 1034 * PC_VPD_ADDR_REG(16bit): 1035 * VPD address register 1036 */ 1037 1038 #define PCR_AB_VPD_ADDR_REG 0x000000b2 1039 /* falcona0,falconb0=pci_f0_config */ 1040 1041 #define PCRF_AB_VPD_FLAG_LBN 15 1042 #define PCRF_AB_VPD_FLAG_WIDTH 1 1043 #define PCRF_AB_VPD_ADDR_LBN 0 1044 #define PCRF_AB_VPD_ADDR_WIDTH 15 1045 1046 1047 /* 1048 * PC_VPD_CAP_DATA_REG(32bit): 1049 * documentation to be written for sum_PC_VPD_CAP_DATA_REG 1050 */ 1051 1052 #define PCR_AB_VPD_CAP_DATA_REG 0x000000b4 1053 /* falcona0,falconb0=pci_f0_config */ 1054 1055 #define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4 1056 /* sienaa0,hunta0=pci_f0_config */ 1057 1058 #define PCRF_AZ_VPD_DATA_LBN 0 1059 #define PCRF_AZ_VPD_DATA_WIDTH 32 1060 1061 1062 /* 1063 * PC_VPD_CAP_CTL_REG(8bit): 1064 * VPD control and capabilities register 1065 */ 1066 1067 #define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0 1068 /* sienaa0,hunta0=pci_f0_config */ 1069 1070 #define PCRF_CZ_VPD_FLAG_LBN 31 1071 #define PCRF_CZ_VPD_FLAG_WIDTH 1 1072 #define PCRF_CZ_VPD_ADDR_LBN 16 1073 #define PCRF_CZ_VPD_ADDR_WIDTH 15 1074 #define PCRF_CZ_VPD_NXT_PTR_LBN 8 1075 #define PCRF_CZ_VPD_NXT_PTR_WIDTH 8 1076 #define PCRF_CZ_VPD_CAP_ID_LBN 0 1077 #define PCRF_CZ_VPD_CAP_ID_WIDTH 8 1078 1079 1080 /* 1081 * PC_AER_CAP_HDR_REG(32bit): 1082 * AER capability header register 1083 */ 1084 1085 #define PCR_AZ_AER_CAP_HDR_REG 0x00000100 1086 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1087 1088 #define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20 1089 #define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12 1090 #define PCRF_AZ_AERCAPHDR_VER_LBN 16 1091 #define PCRF_AZ_AERCAPHDR_VER_WIDTH 4 1092 #define PCRF_AZ_AERCAPHDR_ID_LBN 0 1093 #define PCRF_AZ_AERCAPHDR_ID_WIDTH 16 1094 1095 1096 /* 1097 * PC_AER_UNCORR_ERR_STAT_REG(32bit): 1098 * AER Uncorrectable error status register 1099 */ 1100 1101 #define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104 1102 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1103 1104 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20 1105 #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1 1106 #define PCRF_AZ_ECRC_ERR_STAT_LBN 19 1107 #define PCRF_AZ_ECRC_ERR_STAT_WIDTH 1 1108 #define PCRF_AZ_MALF_TLP_STAT_LBN 18 1109 #define PCRF_AZ_MALF_TLP_STAT_WIDTH 1 1110 #define PCRF_AZ_RX_OVF_STAT_LBN 17 1111 #define PCRF_AZ_RX_OVF_STAT_WIDTH 1 1112 #define PCRF_AZ_UNEXP_COMP_STAT_LBN 16 1113 #define PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1 1114 #define PCRF_AZ_COMP_ABRT_STAT_LBN 15 1115 #define PCRF_AZ_COMP_ABRT_STAT_WIDTH 1 1116 #define PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14 1117 #define PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1 1118 #define PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13 1119 #define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1 1120 #define PCRF_AZ_PSON_TLP_STAT_LBN 12 1121 #define PCRF_AZ_PSON_TLP_STAT_WIDTH 1 1122 #define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4 1123 #define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1 1124 #define PCRF_AB_TRAIN_ERR_STAT_LBN 0 1125 #define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1 1126 1127 1128 /* 1129 * PC_AER_UNCORR_ERR_MASK_REG(32bit): 1130 * AER Uncorrectable error mask register 1131 */ 1132 1133 #define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108 1134 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1135 1136 #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24 1137 #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1 1138 #define PCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22 1139 #define PCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1 1140 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20 1141 #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1 1142 #define PCRF_AZ_ECRC_ERR_MASK_LBN 19 1143 #define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1 1144 #define PCRF_AZ_MALF_TLP_MASK_LBN 18 1145 #define PCRF_AZ_MALF_TLP_MASK_WIDTH 1 1146 #define PCRF_AZ_RX_OVF_MASK_LBN 17 1147 #define PCRF_AZ_RX_OVF_MASK_WIDTH 1 1148 #define PCRF_AZ_UNEXP_COMP_MASK_LBN 16 1149 #define PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1 1150 #define PCRF_AZ_COMP_ABRT_MASK_LBN 15 1151 #define PCRF_AZ_COMP_ABRT_MASK_WIDTH 1 1152 #define PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14 1153 #define PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1 1154 #define PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13 1155 #define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1 1156 #define PCRF_AZ_PSON_TLP_MASK_LBN 12 1157 #define PCRF_AZ_PSON_TLP_MASK_WIDTH 1 1158 #define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4 1159 #define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1 1160 #define PCRF_AB_TRAIN_ERR_MASK_LBN 0 1161 #define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1 1162 1163 1164 /* 1165 * PC_AER_UNCORR_ERR_SEV_REG(32bit): 1166 * AER Uncorrectable error severity register 1167 */ 1168 1169 #define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c 1170 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1171 1172 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20 1173 #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1 1174 #define PCRF_AZ_ECRC_ERR_SEV_LBN 19 1175 #define PCRF_AZ_ECRC_ERR_SEV_WIDTH 1 1176 #define PCRF_AZ_MALF_TLP_SEV_LBN 18 1177 #define PCRF_AZ_MALF_TLP_SEV_WIDTH 1 1178 #define PCRF_AZ_RX_OVF_SEV_LBN 17 1179 #define PCRF_AZ_RX_OVF_SEV_WIDTH 1 1180 #define PCRF_AZ_UNEXP_COMP_SEV_LBN 16 1181 #define PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1 1182 #define PCRF_AZ_COMP_ABRT_SEV_LBN 15 1183 #define PCRF_AZ_COMP_ABRT_SEV_WIDTH 1 1184 #define PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14 1185 #define PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1 1186 #define PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13 1187 #define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1 1188 #define PCRF_AZ_PSON_TLP_SEV_LBN 12 1189 #define PCRF_AZ_PSON_TLP_SEV_WIDTH 1 1190 #define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4 1191 #define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1 1192 #define PCRF_AB_TRAIN_ERR_SEV_LBN 0 1193 #define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1 1194 1195 1196 /* 1197 * PC_AER_CORR_ERR_STAT_REG(32bit): 1198 * AER Correctable error status register 1199 */ 1200 1201 #define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110 1202 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1203 1204 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13 1205 #define PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1 1206 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12 1207 #define PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1 1208 #define PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8 1209 #define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1 1210 #define PCRF_AZ_BAD_DLLP_STAT_LBN 7 1211 #define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1 1212 #define PCRF_AZ_BAD_TLP_STAT_LBN 6 1213 #define PCRF_AZ_BAD_TLP_STAT_WIDTH 1 1214 #define PCRF_AZ_RX_ERR_STAT_LBN 0 1215 #define PCRF_AZ_RX_ERR_STAT_WIDTH 1 1216 1217 1218 /* 1219 * PC_AER_CORR_ERR_MASK_REG(32bit): 1220 * AER Correctable error status register 1221 */ 1222 1223 #define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114 1224 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1225 1226 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13 1227 #define PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1 1228 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12 1229 #define PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1 1230 #define PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8 1231 #define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1 1232 #define PCRF_AZ_BAD_DLLP_MASK_LBN 7 1233 #define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1 1234 #define PCRF_AZ_BAD_TLP_MASK_LBN 6 1235 #define PCRF_AZ_BAD_TLP_MASK_WIDTH 1 1236 #define PCRF_AZ_RX_ERR_MASK_LBN 0 1237 #define PCRF_AZ_RX_ERR_MASK_WIDTH 1 1238 1239 1240 /* 1241 * PC_AER_CAP_CTL_REG(32bit): 1242 * AER capability and control register 1243 */ 1244 1245 #define PCR_AZ_AER_CAP_CTL_REG 0x00000118 1246 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1247 1248 #define PCRF_AZ_ECRC_CHK_EN_LBN 8 1249 #define PCRF_AZ_ECRC_CHK_EN_WIDTH 1 1250 #define PCRF_AZ_ECRC_CHK_CAP_LBN 7 1251 #define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1 1252 #define PCRF_AZ_ECRC_GEN_EN_LBN 6 1253 #define PCRF_AZ_ECRC_GEN_EN_WIDTH 1 1254 #define PCRF_AZ_ECRC_GEN_CAP_LBN 5 1255 #define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1 1256 #define PCRF_AZ_1ST_ERR_PTR_LBN 0 1257 #define PCRF_AZ_1ST_ERR_PTR_WIDTH 5 1258 1259 1260 /* 1261 * PC_AER_HDR_LOG_REG(128bit): 1262 * AER Header log register 1263 */ 1264 1265 #define PCR_AZ_AER_HDR_LOG_REG 0x0000011c 1266 /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1267 1268 #define PCRF_AZ_HDR_LOG_LBN 0 1269 #define PCRF_AZ_HDR_LOG_WIDTH 128 1270 1271 1272 /* 1273 * PC_DEVSN_CAP_HDR_REG(32bit): 1274 * Device serial number capability header register 1275 */ 1276 1277 #define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140 1278 /* sienaa0,hunta0=pci_f0_config */ 1279 1280 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20 1281 #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12 1282 #define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16 1283 #define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4 1284 #define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0 1285 #define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16 1286 1287 1288 /* 1289 * PC_DEVSN_DWORD0_REG(32bit): 1290 * Device serial number DWORD0 1291 */ 1292 1293 #define PCR_CZ_DEVSN_DWORD0_REG 0x00000144 1294 /* sienaa0,hunta0=pci_f0_config */ 1295 1296 #define PCRF_CZ_DEVSN_DWORD0_LBN 0 1297 #define PCRF_CZ_DEVSN_DWORD0_WIDTH 32 1298 1299 1300 /* 1301 * PC_DEVSN_DWORD1_REG(32bit): 1302 * Device serial number DWORD0 1303 */ 1304 1305 #define PCR_CZ_DEVSN_DWORD1_REG 0x00000148 1306 /* sienaa0,hunta0=pci_f0_config */ 1307 1308 #define PCRF_CZ_DEVSN_DWORD1_LBN 0 1309 #define PCRF_CZ_DEVSN_DWORD1_WIDTH 32 1310 1311 1312 /* 1313 * PC_ARI_CAP_HDR_REG(32bit): 1314 * ARI capability header register 1315 */ 1316 1317 #define PCR_CZ_ARI_CAP_HDR_REG 0x00000150 1318 /* sienaa0,hunta0=pci_f0_config */ 1319 1320 #define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20 1321 #define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12 1322 #define PCRF_CZ_ARICAPHDR_VER_LBN 16 1323 #define PCRF_CZ_ARICAPHDR_VER_WIDTH 4 1324 #define PCRF_CZ_ARICAPHDR_ID_LBN 0 1325 #define PCRF_CZ_ARICAPHDR_ID_WIDTH 16 1326 1327 1328 /* 1329 * PC_ARI_CAP_REG(16bit): 1330 * ARI Capabilities 1331 */ 1332 1333 #define PCR_CZ_ARI_CAP_REG 0x00000154 1334 /* sienaa0,hunta0=pci_f0_config */ 1335 1336 #define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8 1337 #define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8 1338 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1 1339 #define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1 1340 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0 1341 #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1 1342 1343 1344 /* 1345 * PC_ARI_CTL_REG(16bit): 1346 * ARI Control 1347 */ 1348 1349 #define PCR_CZ_ARI_CTL_REG 0x00000156 1350 /* sienaa0,hunta0=pci_f0_config */ 1351 1352 #define PCRF_CZ_ARI_FN_GRP_LBN 4 1353 #define PCRF_CZ_ARI_FN_GRP_WIDTH 3 1354 #define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1 1355 #define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1 1356 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0 1357 #define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1 1358 1359 1360 /* 1361 * PC_SEC_PCIE_CAP_REG(32bit): 1362 * Secondary PCIE Capability Register 1363 */ 1364 1365 #define PCR_DZ_SEC_PCIE_CAP_REG 0x00000160 1366 /* hunta0=pci_f0_config */ 1367 1368 #define PCRF_DZ_SEC_NXT_PTR_LBN 20 1369 #define PCRF_DZ_SEC_NXT_PTR_WIDTH 12 1370 #define PCRF_DZ_SEC_VERSION_LBN 16 1371 #define PCRF_DZ_SEC_VERSION_WIDTH 4 1372 #define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0 1373 #define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16 1374 1375 1376 /* 1377 * PC_SRIOV_CAP_HDR_REG(32bit): 1378 * SRIOV capability header register 1379 */ 1380 1381 #define PCR_CC_SRIOV_CAP_HDR_REG 0x00000160 1382 /* sienaa0=pci_f0_config */ 1383 1384 #define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000180 1385 /* hunta0=pci_f0_config */ 1386 1387 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20 1388 #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12 1389 #define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16 1390 #define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4 1391 #define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0 1392 #define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16 1393 1394 1395 /* 1396 * PC_SRIOV_CAP_REG(32bit): 1397 * SRIOV Capabilities 1398 */ 1399 1400 #define PCR_CC_SRIOV_CAP_REG 0x00000164 1401 /* sienaa0=pci_f0_config */ 1402 1403 #define PCR_DZ_SRIOV_CAP_REG 0x00000184 1404 /* hunta0=pci_f0_config */ 1405 1406 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21 1407 #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11 1408 #define PCRF_DZ_VF_ARI_CAP_PRESV_LBN 1 1409 #define PCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1 1410 #define PCRF_CZ_VF_MIGR_CAP_LBN 0 1411 #define PCRF_CZ_VF_MIGR_CAP_WIDTH 1 1412 1413 1414 /* 1415 * PC_LINK_CONTROL3_REG(32bit): 1416 * Link Control 3. 1417 */ 1418 1419 #define PCR_DZ_LINK_CONTROL3_REG 0x00000164 1420 /* hunta0=pci_f0_config */ 1421 1422 #define PCRF_DZ_LINK_EQ_INT_EN_LBN 1 1423 #define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1 1424 #define PCRF_DZ_PERFORM_EQL_LBN 0 1425 #define PCRF_DZ_PERFORM_EQL_WIDTH 1 1426 1427 1428 /* 1429 * PC_LANE_ERROR_STAT_REG(32bit): 1430 * Lane Error Status Register. 1431 */ 1432 1433 #define PCR_DZ_LANE_ERROR_STAT_REG 0x00000168 1434 /* hunta0=pci_f0_config */ 1435 1436 #define PCRF_DZ_LANE_STATUS_LBN 0 1437 #define PCRF_DZ_LANE_STATUS_WIDTH 8 1438 1439 1440 /* 1441 * PC_SRIOV_CTL_REG(16bit): 1442 * SRIOV Control 1443 */ 1444 1445 #define PCR_CC_SRIOV_CTL_REG 0x00000168 1446 /* sienaa0=pci_f0_config */ 1447 1448 #define PCR_DZ_SRIOV_CTL_REG 0x00000188 1449 /* hunta0=pci_f0_config */ 1450 1451 #define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4 1452 #define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1 1453 #define PCRF_CZ_VF_MSE_LBN 3 1454 #define PCRF_CZ_VF_MSE_WIDTH 1 1455 #define PCRF_CZ_VF_MIGR_INT_EN_LBN 2 1456 #define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1 1457 #define PCRF_CZ_VF_MIGR_EN_LBN 1 1458 #define PCRF_CZ_VF_MIGR_EN_WIDTH 1 1459 #define PCRF_CZ_VF_EN_LBN 0 1460 #define PCRF_CZ_VF_EN_WIDTH 1 1461 1462 1463 /* 1464 * PC_SRIOV_STAT_REG(16bit): 1465 * SRIOV Status 1466 */ 1467 1468 #define PCR_CC_SRIOV_STAT_REG 0x0000016a 1469 /* sienaa0=pci_f0_config */ 1470 1471 #define PCR_DZ_SRIOV_STAT_REG 0x0000018a 1472 /* hunta0=pci_f0_config */ 1473 1474 #define PCRF_CZ_VF_MIGR_STAT_LBN 0 1475 #define PCRF_CZ_VF_MIGR_STAT_WIDTH 1 1476 1477 1478 /* 1479 * PC_LANE01_EQU_CONTROL_REG(32bit): 1480 * Lanes 0,1 Equalization Control Register. 1481 */ 1482 1483 #define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c 1484 /* hunta0=pci_f0_config */ 1485 1486 #define PCRF_DZ_LANE1_EQ_CTRL_LBN 16 1487 #define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16 1488 #define PCRF_DZ_LANE0_EQ_CTRL_LBN 0 1489 #define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16 1490 1491 1492 /* 1493 * PC_SRIOV_INITIALVFS_REG(16bit): 1494 * SRIOV Initial VFs 1495 */ 1496 1497 #define PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c 1498 /* sienaa0=pci_f0_config */ 1499 1500 #define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c 1501 /* hunta0=pci_f0_config */ 1502 1503 #define PCRF_CZ_VF_INITIALVFS_LBN 0 1504 #define PCRF_CZ_VF_INITIALVFS_WIDTH 16 1505 1506 1507 /* 1508 * PC_SRIOV_TOTALVFS_REG(10bit): 1509 * SRIOV Total VFs 1510 */ 1511 1512 #define PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e 1513 /* sienaa0=pci_f0_config */ 1514 1515 #define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e 1516 /* hunta0=pci_f0_config */ 1517 1518 #define PCRF_CZ_VF_TOTALVFS_LBN 0 1519 #define PCRF_CZ_VF_TOTALVFS_WIDTH 16 1520 1521 1522 /* 1523 * PC_SRIOV_NUMVFS_REG(16bit): 1524 * SRIOV Number of VFs 1525 */ 1526 1527 #define PCR_CC_SRIOV_NUMVFS_REG 0x00000170 1528 /* sienaa0=pci_f0_config */ 1529 1530 #define PCR_DZ_SRIOV_NUMVFS_REG 0x00000190 1531 /* hunta0=pci_f0_config */ 1532 1533 #define PCRF_CZ_VF_NUMVFS_LBN 0 1534 #define PCRF_CZ_VF_NUMVFS_WIDTH 16 1535 1536 1537 /* 1538 * PC_LANE23_EQU_CONTROL_REG(32bit): 1539 * Lanes 2,3 Equalization Control Register. 1540 */ 1541 1542 #define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170 1543 /* hunta0=pci_f0_config */ 1544 1545 #define PCRF_DZ_LANE3_EQ_CTRL_LBN 16 1546 #define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16 1547 #define PCRF_DZ_LANE2_EQ_CTRL_LBN 0 1548 #define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16 1549 1550 1551 /* 1552 * PC_SRIOV_FN_DPND_LNK_REG(16bit): 1553 * SRIOV Function dependency link 1554 */ 1555 1556 #define PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172 1557 /* sienaa0=pci_f0_config */ 1558 1559 #define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192 1560 /* hunta0=pci_f0_config */ 1561 1562 #define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0 1563 #define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8 1564 1565 1566 /* 1567 * PC_SRIOV_1STVF_OFFSET_REG(16bit): 1568 * SRIOV First VF Offset 1569 */ 1570 1571 #define PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174 1572 /* sienaa0=pci_f0_config */ 1573 1574 #define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194 1575 /* hunta0=pci_f0_config */ 1576 1577 #define PCRF_CZ_VF_1STVF_OFFSET_LBN 0 1578 #define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16 1579 1580 1581 /* 1582 * PC_LANE45_EQU_CONTROL_REG(32bit): 1583 * Lanes 4,5 Equalization Control Register. 1584 */ 1585 1586 #define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174 1587 /* hunta0=pci_f0_config */ 1588 1589 #define PCRF_DZ_LANE5_EQ_CTRL_LBN 16 1590 #define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16 1591 #define PCRF_DZ_LANE4_EQ_CTRL_LBN 0 1592 #define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16 1593 1594 1595 /* 1596 * PC_SRIOV_VFSTRIDE_REG(16bit): 1597 * SRIOV VF Stride 1598 */ 1599 1600 #define PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176 1601 /* sienaa0=pci_f0_config */ 1602 1603 #define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196 1604 /* hunta0=pci_f0_config */ 1605 1606 #define PCRF_CZ_VF_VFSTRIDE_LBN 0 1607 #define PCRF_CZ_VF_VFSTRIDE_WIDTH 16 1608 1609 1610 /* 1611 * PC_LANE67_EQU_CONTROL_REG(32bit): 1612 * Lanes 6,7 Equalization Control Register. 1613 */ 1614 1615 #define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178 1616 /* hunta0=pci_f0_config */ 1617 1618 #define PCRF_DZ_LANE7_EQ_CTRL_LBN 16 1619 #define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16 1620 #define PCRF_DZ_LANE6_EQ_CTRL_LBN 0 1621 #define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16 1622 1623 1624 /* 1625 * PC_SRIOV_DEVID_REG(16bit): 1626 * SRIOV VF Device ID 1627 */ 1628 1629 #define PCR_CC_SRIOV_DEVID_REG 0x0000017a 1630 /* sienaa0=pci_f0_config */ 1631 1632 #define PCR_DZ_SRIOV_DEVID_REG 0x0000019a 1633 /* hunta0=pci_f0_config */ 1634 1635 #define PCRF_CZ_VF_DEVID_LBN 0 1636 #define PCRF_CZ_VF_DEVID_WIDTH 16 1637 1638 1639 /* 1640 * PC_SRIOV_SUP_PAGESZ_REG(16bit): 1641 * SRIOV Supported Page Sizes 1642 */ 1643 1644 #define PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c 1645 /* sienaa0=pci_f0_config */ 1646 1647 #define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c 1648 /* hunta0=pci_f0_config */ 1649 1650 #define PCRF_CZ_VF_SUP_PAGESZ_LBN 0 1651 #define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16 1652 1653 1654 /* 1655 * PC_SRIOV_SYS_PAGESZ_REG(32bit): 1656 * SRIOV System Page Size 1657 */ 1658 1659 #define PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180 1660 /* sienaa0=pci_f0_config */ 1661 1662 #define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0 1663 /* hunta0=pci_f0_config */ 1664 1665 #define PCRF_CZ_VF_SYS_PAGESZ_LBN 0 1666 #define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16 1667 1668 1669 /* 1670 * PC_SRIOV_BAR0_REG(32bit): 1671 * SRIOV VF Bar0 1672 */ 1673 1674 #define PCR_CC_SRIOV_BAR0_REG 0x00000184 1675 /* sienaa0=pci_f0_config */ 1676 1677 #define PCR_DZ_SRIOV_BAR0_REG 0x000001a4 1678 /* hunta0=pci_f0_config */ 1679 1680 #define PCRF_CC_VF_BAR_ADDRESS_LBN 0 1681 #define PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 1682 #define PCRF_DZ_VF_BAR0_ADDRESS_LBN 4 1683 #define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28 1684 #define PCRF_DZ_VF_BAR0_PREF_LBN 3 1685 #define PCRF_DZ_VF_BAR0_PREF_WIDTH 1 1686 #define PCRF_DZ_VF_BAR0_TYPE_LBN 1 1687 #define PCRF_DZ_VF_BAR0_TYPE_WIDTH 2 1688 #define PCRF_DZ_VF_BAR0_IOM_LBN 0 1689 #define PCRF_DZ_VF_BAR0_IOM_WIDTH 1 1690 1691 1692 /* 1693 * PC_SRIOV_BAR1_REG(32bit): 1694 * SRIOV Bar1 1695 */ 1696 1697 #define PCR_CC_SRIOV_BAR1_REG 0x00000188 1698 /* sienaa0=pci_f0_config */ 1699 1700 #define PCR_DZ_SRIOV_BAR1_REG 0x000001a8 1701 /* hunta0=pci_f0_config */ 1702 1703 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1704 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1705 #define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0 1706 #define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32 1707 1708 1709 /* 1710 * PC_SRIOV_BAR2_REG(32bit): 1711 * SRIOV Bar2 1712 */ 1713 1714 #define PCR_CC_SRIOV_BAR2_REG 0x0000018c 1715 /* sienaa0=pci_f0_config */ 1716 1717 #define PCR_DZ_SRIOV_BAR2_REG 0x000001ac 1718 /* hunta0=pci_f0_config */ 1719 1720 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1721 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1722 #define PCRF_DZ_VF_BAR2_ADDRESS_LBN 4 1723 #define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28 1724 #define PCRF_DZ_VF_BAR2_PREF_LBN 3 1725 #define PCRF_DZ_VF_BAR2_PREF_WIDTH 1 1726 #define PCRF_DZ_VF_BAR2_TYPE_LBN 1 1727 #define PCRF_DZ_VF_BAR2_TYPE_WIDTH 2 1728 #define PCRF_DZ_VF_BAR2_IOM_LBN 0 1729 #define PCRF_DZ_VF_BAR2_IOM_WIDTH 1 1730 1731 1732 /* 1733 * PC_SRIOV_BAR3_REG(32bit): 1734 * SRIOV Bar3 1735 */ 1736 1737 #define PCR_CC_SRIOV_BAR3_REG 0x00000190 1738 /* sienaa0=pci_f0_config */ 1739 1740 #define PCR_DZ_SRIOV_BAR3_REG 0x000001b0 1741 /* hunta0=pci_f0_config */ 1742 1743 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1744 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1745 #define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0 1746 #define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32 1747 1748 1749 /* 1750 * PC_SRIOV_BAR4_REG(32bit): 1751 * SRIOV Bar4 1752 */ 1753 1754 #define PCR_CC_SRIOV_BAR4_REG 0x00000194 1755 /* sienaa0=pci_f0_config */ 1756 1757 #define PCR_DZ_SRIOV_BAR4_REG 0x000001b4 1758 /* hunta0=pci_f0_config */ 1759 1760 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1761 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1762 #define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0 1763 #define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32 1764 1765 1766 /* 1767 * PC_SRIOV_BAR5_REG(32bit): 1768 * SRIOV Bar5 1769 */ 1770 1771 #define PCR_CC_SRIOV_BAR5_REG 0x00000198 1772 /* sienaa0=pci_f0_config */ 1773 1774 #define PCR_DZ_SRIOV_BAR5_REG 0x000001b8 1775 /* hunta0=pci_f0_config */ 1776 1777 /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1778 /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1779 #define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0 1780 #define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32 1781 1782 1783 /* 1784 * PC_SRIOV_RSVD_REG(16bit): 1785 * Reserved register 1786 */ 1787 1788 #define PCR_DZ_SRIOV_RSVD_REG 0x00000198 1789 /* hunta0=pci_f0_config */ 1790 1791 #define PCRF_DZ_VF_RSVD_LBN 0 1792 #define PCRF_DZ_VF_RSVD_WIDTH 16 1793 1794 1795 /* 1796 * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit): 1797 * SRIOV VF Migration State Array Offset 1798 */ 1799 1800 #define PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c 1801 /* sienaa0=pci_f0_config */ 1802 1803 #define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc 1804 /* hunta0=pci_f0_config */ 1805 1806 #define PCRF_CZ_VF_MIGR_OFFSET_LBN 3 1807 #define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29 1808 #define PCRF_CZ_VF_MIGR_BIR_LBN 0 1809 #define PCRF_CZ_VF_MIGR_BIR_WIDTH 3 1810 1811 1812 /* 1813 * PC_TPH_CAP_HDR_REG(32bit): 1814 * TPH Capability Header Register 1815 */ 1816 1817 #define PCR_DZ_TPH_CAP_HDR_REG 0x000001c0 1818 /* hunta0=pci_f0_config */ 1819 1820 #define PCRF_DZ_TPH_NXT_PTR_LBN 20 1821 #define PCRF_DZ_TPH_NXT_PTR_WIDTH 12 1822 #define PCRF_DZ_TPH_VERSION_LBN 16 1823 #define PCRF_DZ_TPH_VERSION_WIDTH 4 1824 #define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0 1825 #define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16 1826 1827 1828 /* 1829 * PC_TPH_REQ_CAP_REG(32bit): 1830 * TPH Requester Capability Register 1831 */ 1832 1833 #define PCR_DZ_TPH_REQ_CAP_REG 0x000001c4 1834 /* hunta0=pci_f0_config */ 1835 1836 #define PCRF_DZ_ST_TBLE_SIZE_LBN 16 1837 #define PCRF_DZ_ST_TBLE_SIZE_WIDTH 11 1838 #define PCRF_DZ_ST_TBLE_LOC_LBN 9 1839 #define PCRF_DZ_ST_TBLE_LOC_WIDTH 2 1840 #define PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8 1841 #define PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1 1842 #define PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2 1843 #define PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1 1844 #define PCRF_DZ_TPH_INT_MODE_SUP_LBN 1 1845 #define PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1 1846 #define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0 1847 #define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1 1848 1849 1850 /* 1851 * PC_TPH_REQ_CTL_REG(32bit): 1852 * TPH Requester Control Register 1853 */ 1854 1855 #define PCR_DZ_TPH_REQ_CTL_REG 0x000001c8 1856 /* hunta0=pci_f0_config */ 1857 1858 #define PCRF_DZ_TPH_REQ_ENABLE_LBN 8 1859 #define PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2 1860 #define PCRF_DZ_TPH_ST_MODE_LBN 0 1861 #define PCRF_DZ_TPH_ST_MODE_WIDTH 3 1862 1863 1864 /* 1865 * PC_LTR_CAP_HDR_REG(32bit): 1866 * Latency Tolerance Reporting Cap Header Reg 1867 */ 1868 1869 #define PCR_DZ_LTR_CAP_HDR_REG 0x00000290 1870 /* hunta0=pci_f0_config */ 1871 1872 #define PCRF_DZ_LTR_NXT_PTR_LBN 20 1873 #define PCRF_DZ_LTR_NXT_PTR_WIDTH 12 1874 #define PCRF_DZ_LTR_VERSION_LBN 16 1875 #define PCRF_DZ_LTR_VERSION_WIDTH 4 1876 #define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0 1877 #define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16 1878 1879 1880 /* 1881 * PC_LTR_MAX_SNOOP_REG(32bit): 1882 * LTR Maximum Snoop/No Snoop Register 1883 */ 1884 1885 #define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000294 1886 /* hunta0=pci_f0_config */ 1887 1888 #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26 1889 #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3 1890 #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16 1891 #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10 1892 #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10 1893 #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3 1894 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0 1895 #define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10 1896 1897 1898 /* 1899 * PC_ACK_LAT_TMR_REG(32bit): 1900 * ACK latency timer & replay timer register 1901 */ 1902 1903 #define PCR_AC_ACK_LAT_TMR_REG 0x00000700 1904 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1905 1906 #define PCRF_AC_RT_LBN 16 1907 #define PCRF_AC_RT_WIDTH 16 1908 #define PCRF_AC_ALT_LBN 0 1909 #define PCRF_AC_ALT_WIDTH 16 1910 1911 1912 /* 1913 * PC_OTHER_MSG_REG(32bit): 1914 * Other message register 1915 */ 1916 1917 #define PCR_AC_OTHER_MSG_REG 0x00000704 1918 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1919 1920 #define PCRF_AC_OM_CRPT3_LBN 24 1921 #define PCRF_AC_OM_CRPT3_WIDTH 8 1922 #define PCRF_AC_OM_CRPT2_LBN 16 1923 #define PCRF_AC_OM_CRPT2_WIDTH 8 1924 #define PCRF_AC_OM_CRPT1_LBN 8 1925 #define PCRF_AC_OM_CRPT1_WIDTH 8 1926 #define PCRF_AC_OM_CRPT0_LBN 0 1927 #define PCRF_AC_OM_CRPT0_WIDTH 8 1928 1929 1930 /* 1931 * PC_FORCE_LNK_REG(24bit): 1932 * Port force link register 1933 */ 1934 1935 #define PCR_AC_FORCE_LNK_REG 0x00000708 1936 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1937 1938 #define PCRF_AC_LFS_LBN 16 1939 #define PCRF_AC_LFS_WIDTH 6 1940 #define PCRF_AC_FL_LBN 15 1941 #define PCRF_AC_FL_WIDTH 1 1942 #define PCRF_AC_LN_LBN 0 1943 #define PCRF_AC_LN_WIDTH 8 1944 1945 1946 /* 1947 * PC_ACK_FREQ_REG(32bit): 1948 * ACK frequency register 1949 */ 1950 1951 #define PCR_AC_ACK_FREQ_REG 0x0000070c 1952 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1953 1954 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_LBN 30 1955 #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_WIDTH 1 1956 #define PCRF_AC_L1_ENTR_LAT_LBN 27 1957 #define PCRF_AC_L1_ENTR_LAT_WIDTH 3 1958 #define PCRF_AC_L0_ENTR_LAT_LBN 24 1959 #define PCRF_AC_L0_ENTR_LAT_WIDTH 3 1960 #define PCRF_CC_COMM_NFTS_LBN 16 1961 #define PCRF_CC_COMM_NFTS_WIDTH 8 1962 #define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16 1963 #define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3 1964 #define PCRF_AC_MAX_FTS_LBN 8 1965 #define PCRF_AC_MAX_FTS_WIDTH 8 1966 #define PCRF_AC_ACK_FREQ_LBN 0 1967 #define PCRF_AC_ACK_FREQ_WIDTH 8 1968 1969 1970 /* 1971 * PC_PORT_LNK_CTL_REG(32bit): 1972 * Port link control register 1973 */ 1974 1975 #define PCR_AC_PORT_LNK_CTL_REG 0x00000710 1976 /* falcona0,falconb0,sienaa0=pci_f0_config */ 1977 1978 #define PCRF_AB_LRE_LBN 27 1979 #define PCRF_AB_LRE_WIDTH 1 1980 #define PCRF_AB_ESYNC_LBN 26 1981 #define PCRF_AB_ESYNC_WIDTH 1 1982 #define PCRF_AB_CRPT_LBN 25 1983 #define PCRF_AB_CRPT_WIDTH 1 1984 #define PCRF_AB_XB_LBN 24 1985 #define PCRF_AB_XB_WIDTH 1 1986 #define PCRF_AC_LC_LBN 16 1987 #define PCRF_AC_LC_WIDTH 6 1988 #define PCRF_AC_LDR_LBN 8 1989 #define PCRF_AC_LDR_WIDTH 4 1990 #define PCRF_AC_FLM_LBN 7 1991 #define PCRF_AC_FLM_WIDTH 1 1992 #define PCRF_AC_LKD_LBN 6 1993 #define PCRF_AC_LKD_WIDTH 1 1994 #define PCRF_AC_DLE_LBN 5 1995 #define PCRF_AC_DLE_WIDTH 1 1996 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_LBN 4 1997 #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_WIDTH 1 1998 #define PCRF_AC_RA_LBN 3 1999 #define PCRF_AC_RA_WIDTH 1 2000 #define PCRF_AC_LE_LBN 2 2001 #define PCRF_AC_LE_WIDTH 1 2002 #define PCRF_AC_SD_LBN 1 2003 #define PCRF_AC_SD_WIDTH 1 2004 #define PCRF_AC_OMR_LBN 0 2005 #define PCRF_AC_OMR_WIDTH 1 2006 2007 2008 /* 2009 * PC_LN_SKEW_REG(32bit): 2010 * Lane skew register 2011 */ 2012 2013 #define PCR_AC_LN_SKEW_REG 0x00000714 2014 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2015 2016 #define PCRF_AC_DIS_LBN 31 2017 #define PCRF_AC_DIS_WIDTH 1 2018 #define PCRF_AB_RST_LBN 30 2019 #define PCRF_AB_RST_WIDTH 1 2020 #define PCRF_AC_AD_LBN 25 2021 #define PCRF_AC_AD_WIDTH 1 2022 #define PCRF_AC_FCD_LBN 24 2023 #define PCRF_AC_FCD_WIDTH 1 2024 #define PCRF_AC_LS2_LBN 16 2025 #define PCRF_AC_LS2_WIDTH 8 2026 #define PCRF_AC_LS1_LBN 8 2027 #define PCRF_AC_LS1_WIDTH 8 2028 #define PCRF_AC_LS0_LBN 0 2029 #define PCRF_AC_LS0_WIDTH 8 2030 2031 2032 /* 2033 * PC_SYM_NUM_REG(16bit): 2034 * Symbol number register 2035 */ 2036 2037 #define PCR_AC_SYM_NUM_REG 0x00000718 2038 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2039 2040 #define PCRF_CC_MAX_FUNCTIONS_LBN 29 2041 #define PCRF_CC_MAX_FUNCTIONS_WIDTH 3 2042 #define PCRF_CC_FC_WATCHDOG_TMR_LBN 24 2043 #define PCRF_CC_FC_WATCHDOG_TMR_WIDTH 5 2044 #define PCRF_CC_ACK_NAK_TMR_MOD_LBN 19 2045 #define PCRF_CC_ACK_NAK_TMR_MOD_WIDTH 5 2046 #define PCRF_CC_REPLAY_TMR_MOD_LBN 14 2047 #define PCRF_CC_REPLAY_TMR_MOD_WIDTH 5 2048 #define PCRF_AB_ES_LBN 12 2049 #define PCRF_AB_ES_WIDTH 3 2050 #define PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11 2051 #define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1 2052 #define PCRF_CC_NUM_SKP_SYMS_LBN 8 2053 #define PCRF_CC_NUM_SKP_SYMS_WIDTH 3 2054 #define PCRF_AB_TS2_LBN 4 2055 #define PCRF_AB_TS2_WIDTH 4 2056 #define PCRF_AC_TS1_LBN 0 2057 #define PCRF_AC_TS1_WIDTH 4 2058 2059 2060 /* 2061 * PC_SYM_TMR_FLT_MSK_REG(16bit): 2062 * Symbol timer and Filter Mask Register 2063 */ 2064 2065 #define PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c 2066 /* sienaa0=pci_f0_config */ 2067 2068 #define PCRF_CC_DEFAULT_FLT_MSK1_LBN 16 2069 #define PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16 2070 #define PCRF_CC_FC_WDOG_TMR_DIS_LBN 15 2071 #define PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1 2072 #define PCRF_CC_SI1_LBN 8 2073 #define PCRF_CC_SI1_WIDTH 3 2074 #define PCRF_CC_SKIP_INT_VAL_LBN 0 2075 #define PCRF_CC_SKIP_INT_VAL_WIDTH 11 2076 #define PCRF_CC_SI0_LBN 0 2077 #define PCRF_CC_SI0_WIDTH 8 2078 2079 2080 /* 2081 * PC_SYM_TMR_REG(16bit): 2082 * Symbol timer register 2083 */ 2084 2085 #define PCR_AB_SYM_TMR_REG 0x0000071c 2086 /* falcona0,falconb0=pci_f0_config */ 2087 2088 #define PCRF_AB_ET_LBN 11 2089 #define PCRF_AB_ET_WIDTH 4 2090 #define PCRF_AB_SI1_LBN 8 2091 #define PCRF_AB_SI1_WIDTH 3 2092 #define PCRF_AB_SI0_LBN 0 2093 #define PCRF_AB_SI0_WIDTH 8 2094 2095 2096 /* 2097 * PC_FLT_MSK_REG(32bit): 2098 * Filter Mask Register 2 2099 */ 2100 2101 #define PCR_CC_FLT_MSK_REG 0x00000720 2102 /* sienaa0=pci_f0_config */ 2103 2104 #define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0 2105 #define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32 2106 2107 2108 /* 2109 * PC_PHY_STAT_REG(32bit): 2110 * PHY status register 2111 */ 2112 2113 #define PCR_AB_PHY_STAT_REG 0x00000720 2114 /* falcona0,falconb0=pci_f0_config */ 2115 2116 #define PCR_CC_PHY_STAT_REG 0x00000810 2117 /* sienaa0=pci_f0_config */ 2118 2119 #define PCRF_AC_SSL_LBN 3 2120 #define PCRF_AC_SSL_WIDTH 1 2121 #define PCRF_AC_SSR_LBN 2 2122 #define PCRF_AC_SSR_WIDTH 1 2123 #define PCRF_AC_SSCL_LBN 1 2124 #define PCRF_AC_SSCL_WIDTH 1 2125 #define PCRF_AC_SSCD_LBN 0 2126 #define PCRF_AC_SSCD_WIDTH 1 2127 2128 2129 /* 2130 * PC_PHY_CTL_REG(32bit): 2131 * PHY control register 2132 */ 2133 2134 #define PCR_AB_PHY_CTL_REG 0x00000724 2135 /* falcona0,falconb0=pci_f0_config */ 2136 2137 #define PCR_CC_PHY_CTL_REG 0x00000814 2138 /* sienaa0=pci_f0_config */ 2139 2140 #define PCRF_AC_BD_LBN 31 2141 #define PCRF_AC_BD_WIDTH 1 2142 #define PCRF_AC_CDS_LBN 30 2143 #define PCRF_AC_CDS_WIDTH 1 2144 #define PCRF_AC_DWRAP_LB_LBN 29 2145 #define PCRF_AC_DWRAP_LB_WIDTH 1 2146 #define PCRF_AC_EBD_LBN 28 2147 #define PCRF_AC_EBD_WIDTH 1 2148 #define PCRF_AC_SNR_LBN 27 2149 #define PCRF_AC_SNR_WIDTH 1 2150 #define PCRF_AC_RX_NOT_DET_LBN 2 2151 #define PCRF_AC_RX_NOT_DET_WIDTH 1 2152 #define PCRF_AC_FORCE_LOS_VAL_LBN 1 2153 #define PCRF_AC_FORCE_LOS_VAL_WIDTH 1 2154 #define PCRF_AC_FORCE_LOS_EN_LBN 0 2155 #define PCRF_AC_FORCE_LOS_EN_WIDTH 1 2156 2157 2158 /* 2159 * PC_DEBUG0_REG(32bit): 2160 * Debug register 0 2161 */ 2162 2163 #define PCR_AC_DEBUG0_REG 0x00000728 2164 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2165 2166 #define PCRF_AC_CDI03_LBN 24 2167 #define PCRF_AC_CDI03_WIDTH 8 2168 #define PCRF_AC_CDI0_LBN 0 2169 #define PCRF_AC_CDI0_WIDTH 32 2170 #define PCRF_AC_CDI02_LBN 16 2171 #define PCRF_AC_CDI02_WIDTH 8 2172 #define PCRF_AC_CDI01_LBN 8 2173 #define PCRF_AC_CDI01_WIDTH 8 2174 #define PCRF_AC_CDI00_LBN 0 2175 #define PCRF_AC_CDI00_WIDTH 8 2176 2177 2178 /* 2179 * PC_DEBUG1_REG(32bit): 2180 * Debug register 1 2181 */ 2182 2183 #define PCR_AC_DEBUG1_REG 0x0000072c 2184 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2185 2186 #define PCRF_AC_CDI13_LBN 24 2187 #define PCRF_AC_CDI13_WIDTH 8 2188 #define PCRF_AC_CDI1_LBN 0 2189 #define PCRF_AC_CDI1_WIDTH 32 2190 #define PCRF_AC_CDI12_LBN 16 2191 #define PCRF_AC_CDI12_WIDTH 8 2192 #define PCRF_AC_CDI11_LBN 8 2193 #define PCRF_AC_CDI11_WIDTH 8 2194 #define PCRF_AC_CDI10_LBN 0 2195 #define PCRF_AC_CDI10_WIDTH 8 2196 2197 2198 /* 2199 * PC_XPFCC_STAT_REG(24bit): 2200 * documentation to be written for sum_PC_XPFCC_STAT_REG 2201 */ 2202 2203 #define PCR_AC_XPFCC_STAT_REG 0x00000730 2204 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2205 2206 #define PCRF_AC_XPDC_LBN 12 2207 #define PCRF_AC_XPDC_WIDTH 8 2208 #define PCRF_AC_XPHC_LBN 0 2209 #define PCRF_AC_XPHC_WIDTH 12 2210 2211 2212 /* 2213 * PC_XNPFCC_STAT_REG(24bit): 2214 * documentation to be written for sum_PC_XNPFCC_STAT_REG 2215 */ 2216 2217 #define PCR_AC_XNPFCC_STAT_REG 0x00000734 2218 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2219 2220 #define PCRF_AC_XNPDC_LBN 12 2221 #define PCRF_AC_XNPDC_WIDTH 8 2222 #define PCRF_AC_XNPHC_LBN 0 2223 #define PCRF_AC_XNPHC_WIDTH 12 2224 2225 2226 /* 2227 * PC_XCFCC_STAT_REG(24bit): 2228 * documentation to be written for sum_PC_XCFCC_STAT_REG 2229 */ 2230 2231 #define PCR_AC_XCFCC_STAT_REG 0x00000738 2232 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2233 2234 #define PCRF_AC_XCDC_LBN 12 2235 #define PCRF_AC_XCDC_WIDTH 8 2236 #define PCRF_AC_XCHC_LBN 0 2237 #define PCRF_AC_XCHC_WIDTH 12 2238 2239 2240 /* 2241 * PC_Q_STAT_REG(8bit): 2242 * documentation to be written for sum_PC_Q_STAT_REG 2243 */ 2244 2245 #define PCR_AC_Q_STAT_REG 0x0000073c 2246 /* falcona0,falconb0,sienaa0=pci_f0_config */ 2247 2248 #define PCRF_AC_RQNE_LBN 2 2249 #define PCRF_AC_RQNE_WIDTH 1 2250 #define PCRF_AC_XRNE_LBN 1 2251 #define PCRF_AC_XRNE_WIDTH 1 2252 #define PCRF_AC_RCNR_LBN 0 2253 #define PCRF_AC_RCNR_WIDTH 1 2254 2255 2256 /* 2257 * PC_VC_XMIT_ARB1_REG(32bit): 2258 * VC Transmit Arbitration Register 1 2259 */ 2260 2261 #define PCR_CC_VC_XMIT_ARB1_REG 0x00000740 2262 /* sienaa0=pci_f0_config */ 2263 2264 2265 2266 /* 2267 * PC_VC_XMIT_ARB2_REG(32bit): 2268 * VC Transmit Arbitration Register 2 2269 */ 2270 2271 #define PCR_CC_VC_XMIT_ARB2_REG 0x00000744 2272 /* sienaa0=pci_f0_config */ 2273 2274 2275 2276 /* 2277 * PC_VC0_P_RQ_CTL_REG(32bit): 2278 * VC0 Posted Receive Queue Control 2279 */ 2280 2281 #define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748 2282 /* sienaa0=pci_f0_config */ 2283 2284 2285 2286 /* 2287 * PC_VC0_NP_RQ_CTL_REG(32bit): 2288 * VC0 Non-Posted Receive Queue Control 2289 */ 2290 2291 #define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c 2292 /* sienaa0=pci_f0_config */ 2293 2294 2295 2296 /* 2297 * PC_VC0_C_RQ_CTL_REG(32bit): 2298 * VC0 Completion Receive Queue Control 2299 */ 2300 2301 #define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750 2302 /* sienaa0=pci_f0_config */ 2303 2304 2305 2306 /* 2307 * PC_GEN2_REG(32bit): 2308 * Gen2 Register 2309 */ 2310 2311 #define PCR_CC_GEN2_REG 0x0000080c 2312 /* sienaa0=pci_f0_config */ 2313 2314 #define PCRF_CC_SET_DE_EMPHASIS_LBN 20 2315 #define PCRF_CC_SET_DE_EMPHASIS_WIDTH 1 2316 #define PCRF_CC_CFG_TX_COMPLIANCE_LBN 19 2317 #define PCRF_CC_CFG_TX_COMPLIANCE_WIDTH 1 2318 #define PCRF_CC_CFG_TX_SWING_LBN 18 2319 #define PCRF_CC_CFG_TX_SWING_WIDTH 1 2320 #define PCRF_CC_DIR_SPEED_CHANGE_LBN 17 2321 #define PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1 2322 #define PCRF_CC_LANE_ENABLE_LBN 8 2323 #define PCRF_CC_LANE_ENABLE_WIDTH 9 2324 #define PCRF_CC_NUM_FTS_LBN 0 2325 #define PCRF_CC_NUM_FTS_WIDTH 8 2326 2327 2328 #ifdef __cplusplus 2329 } 2330 #endif 2331 2332 #endif /* _SYS_EFX_REGS_PCI_H */ 2333