1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2008-2019 Solarflare Communications Inc. 5 */ 6 7 /* 8 * This file is automatically generated. DO NOT EDIT IT. 9 * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and 10 * rebuild this file with "make mcdi_headers_v5". 11 */ 12 13 #ifndef _SIENA_MC_DRIVER_PCOL_AOE_H 14 #define _SIENA_MC_DRIVER_PCOL_AOE_H 15 16 17 18 /***********************************/ 19 /* MC_CMD_FC 20 * Perform an FC operation 21 */ 22 #define MC_CMD_FC 0x9 23 24 /* MC_CMD_FC_IN msgrequest */ 25 #define MC_CMD_FC_IN_LEN 4 26 #define MC_CMD_FC_IN_OP_HDR_OFST 0 27 #define MC_CMD_FC_IN_OP_HDR_LEN 4 28 #define MC_CMD_FC_IN_OP_OFST 0 29 #define MC_CMD_FC_IN_OP_LBN 0 30 #define MC_CMD_FC_IN_OP_WIDTH 8 31 /* enum: NULL MCDI command to FC. */ 32 #define MC_CMD_FC_OP_NULL 0x1 33 /* enum: Unused opcode */ 34 #define MC_CMD_FC_OP_UNUSED 0x2 35 /* enum: MAC driver commands */ 36 #define MC_CMD_FC_OP_MAC 0x3 37 /* enum: Read FC memory */ 38 #define MC_CMD_FC_OP_READ32 0x4 39 /* enum: Write to FC memory */ 40 #define MC_CMD_FC_OP_WRITE32 0x5 41 /* enum: Read FC memory */ 42 #define MC_CMD_FC_OP_TRC_READ 0x6 43 /* enum: Write to FC memory */ 44 #define MC_CMD_FC_OP_TRC_WRITE 0x7 45 /* enum: FC firmware Version */ 46 #define MC_CMD_FC_OP_GET_VERSION 0x8 47 /* enum: Read FC memory */ 48 #define MC_CMD_FC_OP_TRC_RX_READ 0x9 49 /* enum: Write to FC memory */ 50 #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa 51 /* enum: SFP parameters */ 52 #define MC_CMD_FC_OP_SFP 0xb 53 /* enum: DDR3 test */ 54 #define MC_CMD_FC_OP_DDR_TEST 0xc 55 /* enum: Get Crash context from FC */ 56 #define MC_CMD_FC_OP_GET_ASSERT 0xd 57 /* enum: Get FPGA Build registers */ 58 #define MC_CMD_FC_OP_FPGA_BUILD 0xe 59 /* enum: Read map support commands */ 60 #define MC_CMD_FC_OP_READ_MAP 0xf 61 /* enum: FC Capabilities */ 62 #define MC_CMD_FC_OP_CAPABILITIES 0x10 63 /* enum: FC Global flags */ 64 #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 65 /* enum: FC IO using relative addressing modes */ 66 #define MC_CMD_FC_OP_IO_REL 0x12 67 /* enum: FPGA link information */ 68 #define MC_CMD_FC_OP_UHLINK 0x13 69 /* enum: Configure loopbacks and link on FPGA ports */ 70 #define MC_CMD_FC_OP_SET_LINK 0x14 71 /* enum: Licensing operations relating to AOE */ 72 #define MC_CMD_FC_OP_LICENSE 0x15 73 /* enum: Startup information to the FC */ 74 #define MC_CMD_FC_OP_STARTUP 0x16 75 /* enum: Configure a DMA read */ 76 #define MC_CMD_FC_OP_DMA 0x17 77 /* enum: Configure a timed read */ 78 #define MC_CMD_FC_OP_TIMED_READ 0x18 79 /* enum: Control UART logging */ 80 #define MC_CMD_FC_OP_LOG 0x19 81 /* enum: Get the value of a given clock_id */ 82 #define MC_CMD_FC_OP_CLOCK 0x1a 83 /* enum: DDR3/QDR3 parameters */ 84 #define MC_CMD_FC_OP_DDR 0x1b 85 /* enum: PTP and timestamp control */ 86 #define MC_CMD_FC_OP_TIMESTAMP 0x1c 87 /* enum: Commands for SPI Flash interface */ 88 #define MC_CMD_FC_OP_SPI 0x1d 89 /* enum: Commands for diagnostic components */ 90 #define MC_CMD_FC_OP_DIAG 0x1e 91 /* enum: External AOE port. */ 92 #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 93 /* enum: Internal AOE port. */ 94 #define MC_CMD_FC_IN_PORT_INT_OFST 0x40 95 96 /* MC_CMD_FC_IN_NULL msgrequest */ 97 #define MC_CMD_FC_IN_NULL_LEN 4 98 #define MC_CMD_FC_IN_CMD_OFST 0 99 #define MC_CMD_FC_IN_CMD_LEN 4 100 101 /* MC_CMD_FC_IN_PHY msgrequest */ 102 #define MC_CMD_FC_IN_PHY_LEN 5 103 /* MC_CMD_FC_IN_CMD_OFST 0 */ 104 /* MC_CMD_FC_IN_CMD_LEN 4 */ 105 /* FC PHY driver operation code */ 106 #define MC_CMD_FC_IN_PHY_OP_OFST 4 107 #define MC_CMD_FC_IN_PHY_OP_LEN 1 108 /* enum: PHY init handler */ 109 #define MC_CMD_FC_OP_PHY_OP_INIT 0x1 110 /* enum: PHY reconfigure handler */ 111 #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2 112 /* enum: PHY reboot handler */ 113 #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3 114 /* enum: PHY get_supported_cap handler */ 115 #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4 116 /* enum: PHY get_config handler */ 117 #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5 118 /* enum: PHY get_media_info handler */ 119 #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6 120 /* enum: PHY set_led handler */ 121 #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7 122 /* enum: PHY lasi_interrupt handler */ 123 #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8 124 /* enum: PHY check_link handler */ 125 #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9 126 /* enum: PHY fill_stats handler */ 127 #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa 128 /* enum: PHY bpx_link_state_changed handler */ 129 #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb 130 /* enum: PHY get_state handler */ 131 #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc 132 /* enum: PHY start_bist handler */ 133 #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd 134 /* enum: PHY poll_bist handler */ 135 #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe 136 /* enum: PHY nvram_test handler */ 137 #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf 138 /* enum: PHY relinquish handler */ 139 #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10 140 /* enum: PHY read connection from FC - may be not required */ 141 #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11 142 /* enum: PHY read flags from FC - may be not required */ 143 #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12 144 145 /* MC_CMD_FC_IN_PHY_INIT msgrequest */ 146 #define MC_CMD_FC_IN_PHY_INIT_LEN 4 147 #define MC_CMD_FC_IN_PHY_CMD_OFST 0 148 #define MC_CMD_FC_IN_PHY_CMD_LEN 4 149 150 /* MC_CMD_FC_IN_MAC msgrequest */ 151 #define MC_CMD_FC_IN_MAC_LEN 8 152 /* MC_CMD_FC_IN_CMD_OFST 0 */ 153 /* MC_CMD_FC_IN_CMD_LEN 4 */ 154 #define MC_CMD_FC_IN_MAC_HEADER_OFST 4 155 #define MC_CMD_FC_IN_MAC_HEADER_LEN 4 156 #define MC_CMD_FC_IN_MAC_OP_OFST 4 157 #define MC_CMD_FC_IN_MAC_OP_LBN 0 158 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8 159 /* enum: MAC reconfigure handler */ 160 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 161 /* enum: MAC Set command - same as MC_CMD_SET_MAC */ 162 #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 163 /* enum: MAC statistics */ 164 #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 165 /* enum: MAC RX statistics */ 166 #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 167 /* enum: MAC TX statistics */ 168 #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 169 /* enum: MAC Read status */ 170 #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 171 #define MC_CMD_FC_IN_MAC_PORT_TYPE_OFST 4 172 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 173 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 174 /* enum: External FPGA port. */ 175 #define MC_CMD_FC_PORT_EXT 0x0 176 /* enum: Internal Siena-facing FPGA ports. */ 177 #define MC_CMD_FC_PORT_INT 0x1 178 #define MC_CMD_FC_IN_MAC_PORT_IDX_OFST 4 179 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 180 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 181 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_OFST 4 182 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 183 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 184 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 185 * irrelevant. Port number is derived from pci_fn; passed in FC header. 186 */ 187 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 188 /* enum: Override default port number. Port number determined by fields 189 * PORT_TYPE and PORT_IDX. 190 */ 191 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 192 193 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ 194 #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 195 /* MC_CMD_FC_IN_CMD_OFST 0 */ 196 /* MC_CMD_FC_IN_CMD_LEN 4 */ 197 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 198 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 199 200 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ 201 #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 202 /* MC_CMD_FC_IN_CMD_OFST 0 */ 203 /* MC_CMD_FC_IN_CMD_LEN 4 */ 204 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 205 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 206 /* MTU size */ 207 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 208 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_LEN 4 209 /* Drain Tx FIFO */ 210 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 211 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_LEN 4 212 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 213 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 214 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 215 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 216 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 217 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4 218 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_OFST 24 219 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 220 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 221 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_OFST 24 222 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 223 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 224 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 225 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_LEN 4 226 227 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ 228 #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 229 /* MC_CMD_FC_IN_CMD_OFST 0 */ 230 /* MC_CMD_FC_IN_CMD_LEN 4 */ 231 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 232 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 233 234 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ 235 #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 236 /* MC_CMD_FC_IN_CMD_OFST 0 */ 237 /* MC_CMD_FC_IN_CMD_LEN 4 */ 238 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 239 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 240 241 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ 242 #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 243 /* MC_CMD_FC_IN_CMD_OFST 0 */ 244 /* MC_CMD_FC_IN_CMD_LEN 4 */ 245 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 246 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 247 248 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ 249 #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 250 /* MC_CMD_FC_IN_CMD_OFST 0 */ 251 /* MC_CMD_FC_IN_CMD_LEN 4 */ 252 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 253 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 254 /* MC Statistics index */ 255 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 256 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_LEN 4 257 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 258 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_LEN 4 259 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_OFST 12 260 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 261 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 262 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_OFST 12 263 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 264 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 265 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_OFST 12 266 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 267 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 268 /* Number of statistics to read */ 269 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 270 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_LEN 4 271 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ 272 #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ 273 274 /* MC_CMD_FC_IN_READ32 msgrequest */ 275 #define MC_CMD_FC_IN_READ32_LEN 16 276 /* MC_CMD_FC_IN_CMD_OFST 0 */ 277 /* MC_CMD_FC_IN_CMD_LEN 4 */ 278 #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 279 #define MC_CMD_FC_IN_READ32_ADDR_HI_LEN 4 280 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 281 #define MC_CMD_FC_IN_READ32_ADDR_LO_LEN 4 282 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 283 #define MC_CMD_FC_IN_READ32_NUMWORDS_LEN 4 284 285 /* MC_CMD_FC_IN_WRITE32 msgrequest */ 286 #define MC_CMD_FC_IN_WRITE32_LENMIN 16 287 #define MC_CMD_FC_IN_WRITE32_LENMAX 252 288 #define MC_CMD_FC_IN_WRITE32_LENMAX_MCDI2 1020 289 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) 290 #define MC_CMD_FC_IN_WRITE32_BUFFER_NUM(len) (((len)-12)/4) 291 /* MC_CMD_FC_IN_CMD_OFST 0 */ 292 /* MC_CMD_FC_IN_CMD_LEN 4 */ 293 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 294 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_LEN 4 295 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 296 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_LEN 4 297 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 298 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 299 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 300 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 301 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM_MCDI2 252 302 303 /* MC_CMD_FC_IN_TRC_READ msgrequest */ 304 #define MC_CMD_FC_IN_TRC_READ_LEN 12 305 /* MC_CMD_FC_IN_CMD_OFST 0 */ 306 /* MC_CMD_FC_IN_CMD_LEN 4 */ 307 #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 308 #define MC_CMD_FC_IN_TRC_READ_TRC_LEN 4 309 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 310 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_LEN 4 311 312 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */ 313 #define MC_CMD_FC_IN_TRC_WRITE_LEN 28 314 /* MC_CMD_FC_IN_CMD_OFST 0 */ 315 /* MC_CMD_FC_IN_CMD_LEN 4 */ 316 #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 317 #define MC_CMD_FC_IN_TRC_WRITE_TRC_LEN 4 318 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 319 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_LEN 4 320 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 321 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 322 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 323 324 /* MC_CMD_FC_IN_GET_VERSION msgrequest */ 325 #define MC_CMD_FC_IN_GET_VERSION_LEN 4 326 /* MC_CMD_FC_IN_CMD_OFST 0 */ 327 /* MC_CMD_FC_IN_CMD_LEN 4 */ 328 329 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ 330 #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 331 /* MC_CMD_FC_IN_CMD_OFST 0 */ 332 /* MC_CMD_FC_IN_CMD_LEN 4 */ 333 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 334 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_LEN 4 335 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 336 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_LEN 4 337 338 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ 339 #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 340 /* MC_CMD_FC_IN_CMD_OFST 0 */ 341 /* MC_CMD_FC_IN_CMD_LEN 4 */ 342 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 343 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_LEN 4 344 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 345 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_LEN 4 346 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 347 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 348 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 349 350 /* MC_CMD_FC_IN_SFP msgrequest */ 351 #define MC_CMD_FC_IN_SFP_LEN 28 352 /* MC_CMD_FC_IN_CMD_OFST 0 */ 353 /* MC_CMD_FC_IN_CMD_LEN 4 */ 354 /* Link speed is 100, 1000, 10000, 40000 */ 355 #define MC_CMD_FC_IN_SFP_SPEED_OFST 4 356 #define MC_CMD_FC_IN_SFP_SPEED_LEN 4 357 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */ 358 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 359 #define MC_CMD_FC_IN_SFP_COPPER_LEN_LEN 4 360 /* Not relevant for cards with QSFP modules. For older cards, true if module is 361 * a dual speed SFP+ module. 362 */ 363 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 364 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_LEN 4 365 /* True if an SFP Module is present (other fields valid when true) */ 366 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 367 #define MC_CMD_FC_IN_SFP_PRESENT_LEN 4 368 /* The type of the SFP+ Module. For later cards with QSFP modules, this field 369 * is unused and the type is communicated by other means. 370 */ 371 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20 372 #define MC_CMD_FC_IN_SFP_TYPE_LEN 4 373 /* Capabilities corresponding to 1 bits. */ 374 #define MC_CMD_FC_IN_SFP_CAPS_OFST 24 375 #define MC_CMD_FC_IN_SFP_CAPS_LEN 4 376 377 /* MC_CMD_FC_IN_DDR_TEST msgrequest */ 378 #define MC_CMD_FC_IN_DDR_TEST_LEN 8 379 /* MC_CMD_FC_IN_CMD_OFST 0 */ 380 /* MC_CMD_FC_IN_CMD_LEN 4 */ 381 #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 382 #define MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 383 #define MC_CMD_FC_IN_DDR_TEST_OP_OFST 4 384 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 385 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 386 /* enum: DRAM Test Start */ 387 #define MC_CMD_FC_OP_DDR_TEST_START 0x1 388 /* enum: DRAM Test Poll */ 389 #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 390 391 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ 392 #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 393 /* MC_CMD_FC_IN_CMD_OFST 0 */ 394 /* MC_CMD_FC_IN_CMD_LEN 4 */ 395 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 396 /* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */ 397 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 398 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_LEN 4 399 #define MC_CMD_FC_IN_DDR_TEST_START_T0_OFST 8 400 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 401 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 402 #define MC_CMD_FC_IN_DDR_TEST_START_T1_OFST 8 403 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 404 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 405 #define MC_CMD_FC_IN_DDR_TEST_START_B0_OFST 8 406 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 407 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 408 #define MC_CMD_FC_IN_DDR_TEST_START_B1_OFST 8 409 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 410 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 411 412 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ 413 #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 414 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 415 #define MC_CMD_FC_IN_DDR_TEST_CMD_LEN 4 416 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 417 /* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */ 418 /* Clear previous test result and prepare for restarting DDR test */ 419 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 420 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_LEN 4 421 422 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ 423 #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 424 /* MC_CMD_FC_IN_CMD_OFST 0 */ 425 /* MC_CMD_FC_IN_CMD_LEN 4 */ 426 427 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ 428 #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 429 /* MC_CMD_FC_IN_CMD_OFST 0 */ 430 /* MC_CMD_FC_IN_CMD_LEN 4 */ 431 /* FPGA build info operation code */ 432 #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 433 #define MC_CMD_FC_IN_FPGA_BUILD_OP_LEN 4 434 /* enum: Get the build registers */ 435 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 436 /* enum: Get the services registers */ 437 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 438 /* enum: Get the BSP version */ 439 #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 440 /* enum: Get build register for V2 (SFA974X) */ 441 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 442 /* enum: GEt the services register for V2 (SFA974X) */ 443 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 444 445 /* MC_CMD_FC_IN_READ_MAP msgrequest */ 446 #define MC_CMD_FC_IN_READ_MAP_LEN 8 447 /* MC_CMD_FC_IN_CMD_OFST 0 */ 448 /* MC_CMD_FC_IN_CMD_LEN 4 */ 449 #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 450 #define MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 451 #define MC_CMD_FC_IN_READ_MAP_OP_OFST 4 452 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 453 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 454 /* enum: Get the number of map regions */ 455 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 456 /* enum: Get the specified map */ 457 #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 458 459 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ 460 #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 461 /* MC_CMD_FC_IN_CMD_OFST 0 */ 462 /* MC_CMD_FC_IN_CMD_LEN 4 */ 463 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 464 /* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */ 465 466 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ 467 #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 468 /* MC_CMD_FC_IN_CMD_OFST 0 */ 469 /* MC_CMD_FC_IN_CMD_LEN 4 */ 470 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 471 /* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */ 472 #define MC_CMD_FC_IN_MAP_INDEX_OFST 8 473 #define MC_CMD_FC_IN_MAP_INDEX_LEN 4 474 475 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */ 476 #define MC_CMD_FC_IN_CAPABILITIES_LEN 4 477 /* MC_CMD_FC_IN_CMD_OFST 0 */ 478 /* MC_CMD_FC_IN_CMD_LEN 4 */ 479 480 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ 481 #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 482 /* MC_CMD_FC_IN_CMD_OFST 0 */ 483 /* MC_CMD_FC_IN_CMD_LEN 4 */ 484 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 485 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_LEN 4 486 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_OFST 4 487 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 488 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 489 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_OFST 4 490 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 491 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 492 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_OFST 4 493 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 494 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 495 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_OFST 4 496 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 497 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 498 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_OFST 4 499 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 500 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 501 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_OFST 4 502 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 503 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 504 505 /* MC_CMD_FC_IN_IO_REL msgrequest */ 506 #define MC_CMD_FC_IN_IO_REL_LEN 8 507 /* MC_CMD_FC_IN_CMD_OFST 0 */ 508 /* MC_CMD_FC_IN_CMD_LEN 4 */ 509 #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 510 #define MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 511 #define MC_CMD_FC_IN_IO_REL_OP_OFST 4 512 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0 513 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 514 /* enum: Get the base address that the FC applies to relative commands */ 515 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 516 /* enum: Read data */ 517 #define MC_CMD_FC_IN_IO_REL_READ32 0x2 518 /* enum: Write data */ 519 #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 520 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_OFST 4 521 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 522 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 523 /* enum: Application address space */ 524 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 525 /* enum: Flash address space */ 526 #define MC_CMD_FC_COMP_TYPE_FLASH 0x2 527 528 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ 529 #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 530 /* MC_CMD_FC_IN_CMD_OFST 0 */ 531 /* MC_CMD_FC_IN_CMD_LEN 4 */ 532 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 533 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 534 535 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ 536 #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 537 /* MC_CMD_FC_IN_CMD_OFST 0 */ 538 /* MC_CMD_FC_IN_CMD_LEN 4 */ 539 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 540 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 541 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 542 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_LEN 4 543 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 544 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_LEN 4 545 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 546 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_LEN 4 547 548 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ 549 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 550 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 551 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX_MCDI2 1020 552 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) 553 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_NUM(len) (((len)-16)/4) 554 /* MC_CMD_FC_IN_CMD_OFST 0 */ 555 /* MC_CMD_FC_IN_CMD_LEN 4 */ 556 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 557 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 558 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 559 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_LEN 4 560 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 561 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_LEN 4 562 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 563 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 564 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 565 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 566 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM_MCDI2 251 567 568 /* MC_CMD_FC_IN_UHLINK msgrequest */ 569 #define MC_CMD_FC_IN_UHLINK_LEN 8 570 /* MC_CMD_FC_IN_CMD_OFST 0 */ 571 /* MC_CMD_FC_IN_CMD_LEN 4 */ 572 #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 573 #define MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 574 #define MC_CMD_FC_IN_UHLINK_OP_OFST 4 575 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0 576 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 577 /* enum: Get PHY configuration info */ 578 #define MC_CMD_FC_OP_UHLINK_PHY 0x1 579 /* enum: Get MAC configuration info */ 580 #define MC_CMD_FC_OP_UHLINK_MAC 0x2 581 /* enum: Get Rx eye table */ 582 #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 583 /* enum: Get Rx eye plot */ 584 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 585 /* enum: Get Rx eye plot */ 586 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 587 /* enum: Retune Rx settings */ 588 #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 589 /* enum: Set loopback mode on fpga port */ 590 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 591 /* enum: Get loopback mode config state on fpga port */ 592 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 593 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_OFST 4 594 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 595 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 596 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_OFST 4 597 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 598 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 599 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_OFST 4 600 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 601 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 602 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 603 * irrelevant. Port number is derived from pci_fn; passed in FC header. 604 */ 605 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 606 /* enum: Override default port number. Port number determined by fields 607 * PORT_TYPE and PORT_IDX. 608 */ 609 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 610 611 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ 612 #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 613 /* MC_CMD_FC_IN_CMD_OFST 0 */ 614 /* MC_CMD_FC_IN_CMD_LEN 4 */ 615 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 616 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 617 618 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ 619 #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 620 /* MC_CMD_FC_IN_CMD_OFST 0 */ 621 /* MC_CMD_FC_IN_CMD_LEN 4 */ 622 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 623 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 624 625 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ 626 #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 627 /* MC_CMD_FC_IN_CMD_OFST 0 */ 628 /* MC_CMD_FC_IN_CMD_LEN 4 */ 629 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 630 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 631 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 632 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_LEN 4 633 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ 634 635 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ 636 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 637 /* MC_CMD_FC_IN_CMD_OFST 0 */ 638 /* MC_CMD_FC_IN_CMD_LEN 4 */ 639 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 640 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 641 642 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ 643 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 644 /* MC_CMD_FC_IN_CMD_OFST 0 */ 645 /* MC_CMD_FC_IN_CMD_LEN 4 */ 646 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 647 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 648 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 649 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_LEN 4 650 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 651 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_LEN 4 652 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 653 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_LEN 4 654 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ 655 656 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ 657 #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 658 /* MC_CMD_FC_IN_CMD_OFST 0 */ 659 /* MC_CMD_FC_IN_CMD_LEN 4 */ 660 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 661 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 662 663 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ 664 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 665 /* MC_CMD_FC_IN_CMD_OFST 0 */ 666 /* MC_CMD_FC_IN_CMD_LEN 4 */ 667 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 668 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 669 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 670 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_LEN 4 671 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ 672 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ 673 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ 674 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 675 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_LEN 4 676 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ 677 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ 678 679 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ 680 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 681 /* MC_CMD_FC_IN_CMD_OFST 0 */ 682 /* MC_CMD_FC_IN_CMD_LEN 4 */ 683 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 684 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 685 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 686 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_LEN 4 687 688 /* MC_CMD_FC_IN_SET_LINK msgrequest */ 689 #define MC_CMD_FC_IN_SET_LINK_LEN 16 690 /* MC_CMD_FC_IN_CMD_OFST 0 */ 691 /* MC_CMD_FC_IN_CMD_LEN 4 */ 692 /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 693 #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 694 #define MC_CMD_FC_IN_SET_LINK_MODE_LEN 4 695 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 696 #define MC_CMD_FC_IN_SET_LINK_SPEED_LEN 4 697 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 698 #define MC_CMD_FC_IN_SET_LINK_FLAGS_LEN 4 699 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_OFST 12 700 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 701 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 702 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_OFST 12 703 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 704 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 705 #define MC_CMD_FC_IN_SET_LINK_TXDIS_OFST 12 706 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 707 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 708 709 /* MC_CMD_FC_IN_LICENSE msgrequest */ 710 #define MC_CMD_FC_IN_LICENSE_LEN 8 711 /* MC_CMD_FC_IN_CMD_OFST 0 */ 712 /* MC_CMD_FC_IN_CMD_LEN 4 */ 713 #define MC_CMD_FC_IN_LICENSE_OP_OFST 4 714 #define MC_CMD_FC_IN_LICENSE_OP_LEN 4 715 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ 716 #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ 717 718 /* MC_CMD_FC_IN_STARTUP msgrequest */ 719 #define MC_CMD_FC_IN_STARTUP_LEN 40 720 /* MC_CMD_FC_IN_CMD_OFST 0 */ 721 /* MC_CMD_FC_IN_CMD_LEN 4 */ 722 #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 723 #define MC_CMD_FC_IN_STARTUP_BASE_LEN 4 724 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 725 #define MC_CMD_FC_IN_STARTUP_LENGTH_LEN 4 726 /* Length of identifier */ 727 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 728 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_LEN 4 729 /* Identifier for AOE FPGA */ 730 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16 731 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1 732 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24 733 734 /* MC_CMD_FC_IN_DMA msgrequest */ 735 #define MC_CMD_FC_IN_DMA_LEN 8 736 /* MC_CMD_FC_IN_CMD_OFST 0 */ 737 /* MC_CMD_FC_IN_CMD_LEN 4 */ 738 #define MC_CMD_FC_IN_DMA_OP_OFST 4 739 #define MC_CMD_FC_IN_DMA_OP_LEN 4 740 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ 741 #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ 742 743 /* MC_CMD_FC_IN_DMA_STOP msgrequest */ 744 #define MC_CMD_FC_IN_DMA_STOP_LEN 12 745 /* MC_CMD_FC_IN_CMD_OFST 0 */ 746 /* MC_CMD_FC_IN_CMD_LEN 4 */ 747 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 748 /* MC_CMD_FC_IN_DMA_OP_LEN 4 */ 749 /* FC supplied handle */ 750 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 751 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_LEN 4 752 753 /* MC_CMD_FC_IN_DMA_READ msgrequest */ 754 #define MC_CMD_FC_IN_DMA_READ_LEN 16 755 /* MC_CMD_FC_IN_CMD_OFST 0 */ 756 /* MC_CMD_FC_IN_CMD_LEN 4 */ 757 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 758 /* MC_CMD_FC_IN_DMA_OP_LEN 4 */ 759 #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 760 #define MC_CMD_FC_IN_DMA_READ_OFFSET_LEN 4 761 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 762 #define MC_CMD_FC_IN_DMA_READ_LENGTH_LEN 4 763 764 /* MC_CMD_FC_IN_TIMED_READ msgrequest */ 765 #define MC_CMD_FC_IN_TIMED_READ_LEN 8 766 /* MC_CMD_FC_IN_CMD_OFST 0 */ 767 /* MC_CMD_FC_IN_CMD_LEN 4 */ 768 #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 769 #define MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 770 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ 771 #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ 772 #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ 773 774 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ 775 #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 776 /* MC_CMD_FC_IN_CMD_OFST 0 */ 777 /* MC_CMD_FC_IN_CMD_LEN 4 */ 778 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 779 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 780 /* Host supplied handle (unique) */ 781 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 782 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_LEN 4 783 /* Address into which to transfer data in host */ 784 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 785 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 786 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 787 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 788 /* AOE address from which to transfer data */ 789 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 790 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 791 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 792 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 793 /* Length of AOE transfer (total) */ 794 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 795 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4 796 /* Length of host transfer (total) */ 797 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 798 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_LEN 4 799 /* Offset back from aoe_address to apply operation to */ 800 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 801 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_LEN 4 802 /* Data to apply at offset */ 803 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 804 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_LEN 4 805 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 806 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_LEN 4 807 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_OFST 44 808 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 809 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 810 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_OFST 44 811 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 812 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 813 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_OFST 44 814 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 815 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 816 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_OFST 44 817 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 818 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 819 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ 820 #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ 821 #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ 822 #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ 823 /* Period at which reads are performed (100ms units) */ 824 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 825 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_LEN 4 826 827 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ 828 #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 829 /* MC_CMD_FC_IN_CMD_OFST 0 */ 830 /* MC_CMD_FC_IN_CMD_LEN 4 */ 831 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 832 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 833 /* FC supplied handle */ 834 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 835 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_LEN 4 836 837 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ 838 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 839 /* MC_CMD_FC_IN_CMD_OFST 0 */ 840 /* MC_CMD_FC_IN_CMD_LEN 4 */ 841 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 842 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 843 /* FC supplied handle */ 844 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 845 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_LEN 4 846 847 /* MC_CMD_FC_IN_LOG msgrequest */ 848 #define MC_CMD_FC_IN_LOG_LEN 8 849 /* MC_CMD_FC_IN_CMD_OFST 0 */ 850 /* MC_CMD_FC_IN_CMD_LEN 4 */ 851 #define MC_CMD_FC_IN_LOG_OP_OFST 4 852 #define MC_CMD_FC_IN_LOG_OP_LEN 4 853 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ 854 #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ 855 856 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ 857 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 858 /* MC_CMD_FC_IN_CMD_OFST 0 */ 859 /* MC_CMD_FC_IN_CMD_LEN 4 */ 860 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 861 /* MC_CMD_FC_IN_LOG_OP_LEN 4 */ 862 /* Partition offset into flash */ 863 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 864 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_LEN 4 865 /* Partition length */ 866 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 867 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_LEN 4 868 /* Partition erase size */ 869 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 870 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_LEN 4 871 872 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ 873 #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 874 /* MC_CMD_FC_IN_CMD_OFST 0 */ 875 /* MC_CMD_FC_IN_CMD_LEN 4 */ 876 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 877 /* MC_CMD_FC_IN_LOG_OP_LEN 4 */ 878 /* Enable/disable printing to JTAG UART */ 879 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 880 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_LEN 4 881 882 /* MC_CMD_FC_IN_CLOCK msgrequest: Perform a clock operation */ 883 #define MC_CMD_FC_IN_CLOCK_LEN 12 884 /* MC_CMD_FC_IN_CMD_OFST 0 */ 885 /* MC_CMD_FC_IN_CMD_LEN 4 */ 886 #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 887 #define MC_CMD_FC_IN_CLOCK_OP_LEN 4 888 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ 889 #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ 890 #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 891 #define MC_CMD_FC_IN_CLOCK_ID_LEN 4 892 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ 893 #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ 894 895 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest: Retrieve the clock value of the 896 * specified clock 897 */ 898 #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 899 /* MC_CMD_FC_IN_CMD_OFST 0 */ 900 /* MC_CMD_FC_IN_CMD_LEN 4 */ 901 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 902 /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ 903 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 904 /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ 905 906 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest: Set the clock value of the specified 907 * clock 908 */ 909 #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 910 /* MC_CMD_FC_IN_CMD_OFST 0 */ 911 /* MC_CMD_FC_IN_CMD_LEN 4 */ 912 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 913 /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ 914 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 915 /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ 916 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 917 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 918 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 919 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 920 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 921 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4 922 923 /* MC_CMD_FC_IN_DDR msgrequest */ 924 #define MC_CMD_FC_IN_DDR_LEN 12 925 /* MC_CMD_FC_IN_CMD_OFST 0 */ 926 /* MC_CMD_FC_IN_CMD_LEN 4 */ 927 #define MC_CMD_FC_IN_DDR_OP_OFST 4 928 #define MC_CMD_FC_IN_DDR_OP_LEN 4 929 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ 930 #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ 931 #define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ 932 #define MC_CMD_FC_IN_DDR_BANK_OFST 8 933 #define MC_CMD_FC_IN_DDR_BANK_LEN 4 934 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ 935 #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ 936 #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ 937 #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ 938 #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ 939 940 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ 941 #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 942 /* MC_CMD_FC_IN_CMD_OFST 0 */ 943 /* MC_CMD_FC_IN_CMD_LEN 4 */ 944 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 945 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 946 /* Affected bank */ 947 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 948 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 949 /* Flags */ 950 #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 951 #define MC_CMD_FC_IN_DDR_FLAGS_LEN 4 952 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ 953 /* 128-byte page of serial presence detect data read from module's EEPROM */ 954 #define MC_CMD_FC_IN_DDR_SPD_OFST 16 955 #define MC_CMD_FC_IN_DDR_SPD_LEN 1 956 #define MC_CMD_FC_IN_DDR_SPD_NUM 128 957 /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ 958 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 959 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_LEN 4 960 961 /* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ 962 #define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 963 /* MC_CMD_FC_IN_CMD_OFST 0 */ 964 /* MC_CMD_FC_IN_CMD_LEN 4 */ 965 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 966 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 967 /* Affected bank */ 968 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 969 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 970 /* Size of DDR */ 971 #define MC_CMD_FC_IN_DDR_SIZE_OFST 12 972 #define MC_CMD_FC_IN_DDR_SIZE_LEN 4 973 974 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ 975 #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 976 /* MC_CMD_FC_IN_CMD_OFST 0 */ 977 /* MC_CMD_FC_IN_CMD_LEN 4 */ 978 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 979 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 980 /* Affected bank */ 981 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 982 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 983 984 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */ 985 #define MC_CMD_FC_IN_TIMESTAMP_LEN 8 986 /* MC_CMD_FC_IN_CMD_OFST 0 */ 987 /* MC_CMD_FC_IN_CMD_LEN 4 */ 988 /* FC timestamp operation code */ 989 #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 990 #define MC_CMD_FC_IN_TIMESTAMP_OP_LEN 4 991 /* enum: Read transmit timestamp(s) */ 992 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 993 /* enum: Read snapshot timestamps */ 994 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 995 /* enum: Clear all transmit timestamps */ 996 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 997 998 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ 999 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 1000 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1001 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1002 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 1003 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_LEN 4 1004 /* Control filtering of the returned timestamp and sequence number specified 1005 * here 1006 */ 1007 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 1008 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_LEN 4 1009 /* enum: Return most recent timestamp. No filtering */ 1010 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 1011 /* enum: Match timestamp against the PTP clock ID, port number and sequence 1012 * number specified 1013 */ 1014 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 1015 /* Clock identity of PTP packet for which timestamp required */ 1016 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 1017 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 1018 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 1019 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 1020 /* Port number of PTP packet for which timestamp required */ 1021 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 1022 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4 1023 /* Sequence number of PTP packet for which timestamp required */ 1024 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 1025 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_LEN 4 1026 1027 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ 1028 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 1029 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1030 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1031 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 1032 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_LEN 4 1033 1034 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ 1035 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 1036 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1037 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1038 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 1039 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_LEN 4 1040 1041 /* MC_CMD_FC_IN_SPI msgrequest */ 1042 #define MC_CMD_FC_IN_SPI_LEN 8 1043 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1044 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1045 /* Basic commands for SPI Flash. */ 1046 #define MC_CMD_FC_IN_SPI_OP_OFST 4 1047 #define MC_CMD_FC_IN_SPI_OP_LEN 4 1048 /* enum: SPI Flash read */ 1049 #define MC_CMD_FC_IN_SPI_READ 0x0 1050 /* enum: SPI Flash write */ 1051 #define MC_CMD_FC_IN_SPI_WRITE 0x1 1052 /* enum: SPI Flash erase */ 1053 #define MC_CMD_FC_IN_SPI_ERASE 0x2 1054 1055 /* MC_CMD_FC_IN_SPI_READ msgrequest */ 1056 #define MC_CMD_FC_IN_SPI_READ_LEN 16 1057 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1058 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1059 #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 1060 #define MC_CMD_FC_IN_SPI_READ_OP_LEN 4 1061 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 1062 #define MC_CMD_FC_IN_SPI_READ_ADDR_LEN 4 1063 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 1064 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_LEN 4 1065 1066 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ 1067 #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 1068 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 1069 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX_MCDI2 1020 1070 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) 1071 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_NUM(len) (((len)-12)/4) 1072 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1073 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1074 #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 1075 #define MC_CMD_FC_IN_SPI_WRITE_OP_LEN 4 1076 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 1077 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_LEN 4 1078 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 1079 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 1080 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 1081 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 1082 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM_MCDI2 252 1083 1084 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ 1085 #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 1086 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1087 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1088 #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 1089 #define MC_CMD_FC_IN_SPI_ERASE_OP_LEN 4 1090 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 1091 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_LEN 4 1092 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 1093 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_LEN 4 1094 1095 /* MC_CMD_FC_IN_DIAG msgrequest */ 1096 #define MC_CMD_FC_IN_DIAG_LEN 8 1097 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1098 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1099 /* Operation code indicating component type */ 1100 #define MC_CMD_FC_IN_DIAG_OP_OFST 4 1101 #define MC_CMD_FC_IN_DIAG_OP_LEN 4 1102 /* enum: Power noise generator. */ 1103 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 1104 /* enum: DDR soak test component. */ 1105 #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 1106 /* enum: Diagnostics datapath control component. */ 1107 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 1108 1109 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ 1110 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 1111 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1112 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1113 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 1114 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_LEN 4 1115 /* Sub-opcode describing the operation to be carried out */ 1116 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 1117 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_LEN 4 1118 /* enum: Read the configuration (the 32-bit values in each of the clock enable 1119 * count and toggle count registers) 1120 */ 1121 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 1122 /* enum: Write a new configuration to the clock enable count and toggle count 1123 * registers 1124 */ 1125 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 1126 1127 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ 1128 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 1129 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1130 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1131 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 1132 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_LEN 4 1133 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 1134 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_LEN 4 1135 1136 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ 1137 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 1138 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1139 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1140 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 1141 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_LEN 4 1142 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 1143 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_LEN 4 1144 /* The 32-bit value to be written to the toggle count register */ 1145 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 1146 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_LEN 4 1147 /* The 32-bit value to be written to the clock enable count register */ 1148 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 1149 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_LEN 4 1150 1151 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ 1152 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 1153 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1154 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1155 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 1156 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_LEN 4 1157 /* Sub-opcode describing the operation to be carried out */ 1158 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 1159 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_LEN 4 1160 /* enum: Starts DDR soak test on selected banks */ 1161 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 1162 /* enum: Read status of DDR soak test */ 1163 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 1164 /* enum: Stop test */ 1165 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 1166 /* enum: Set or clear bit that triggers fake errors. These cause subsequent 1167 * tests to fail until the bit is cleared. 1168 */ 1169 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 1170 1171 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ 1172 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 1173 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1174 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1175 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 1176 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_LEN 4 1177 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 1178 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_LEN 4 1179 /* Mask of DDR banks to be tested */ 1180 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 1181 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_LEN 4 1182 /* Pattern to use in the soak test */ 1183 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 1184 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_LEN 4 1185 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ 1186 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ 1187 /* Either multiple automatic tests until a STOP command is issued, or one 1188 * single test 1189 */ 1190 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 1191 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_LEN 4 1192 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ 1193 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ 1194 1195 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ 1196 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 1197 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1198 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1199 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 1200 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_LEN 4 1201 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 1202 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_LEN 4 1203 /* DDR bank to read status from */ 1204 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 1205 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_LEN 4 1206 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ 1207 #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ 1208 #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ 1209 #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ 1210 #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ 1211 1212 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ 1213 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 1214 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1215 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1216 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 1217 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_LEN 4 1218 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 1219 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_LEN 4 1220 /* Mask of DDR banks to be tested */ 1221 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 1222 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_LEN 4 1223 1224 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ 1225 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 1226 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1227 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1228 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 1229 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_LEN 4 1230 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 1231 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_LEN 4 1232 /* Mask of DDR banks to set/clear error flag on */ 1233 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 1234 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_LEN 4 1235 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 1236 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_LEN 4 1237 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ 1238 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ 1239 1240 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ 1241 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 1242 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1243 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1244 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 1245 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_LEN 4 1246 /* Sub-opcode describing the operation to be carried out */ 1247 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 1248 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_LEN 4 1249 /* enum: Set a known datapath configuration */ 1250 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 1251 /* enum: Apply raw config to datapath control registers */ 1252 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 1253 1254 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ 1255 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 1256 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1257 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1258 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 1259 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_LEN 4 1260 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 1261 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_LEN 4 1262 /* Datapath configuration identifier */ 1263 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 1264 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_LEN 4 1265 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ 1266 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ 1267 1268 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ 1269 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 1270 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1271 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1272 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 1273 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_LEN 4 1274 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 1275 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_LEN 4 1276 /* Value to write into control register 1 */ 1277 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 1278 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_LEN 4 1279 /* Value to write into control register 2 */ 1280 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 1281 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_LEN 4 1282 /* Value to write into control register 3 */ 1283 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 1284 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_LEN 4 1285 1286 /* MC_CMD_FC_OUT msgresponse */ 1287 #define MC_CMD_FC_OUT_LEN 0 1288 1289 /* MC_CMD_FC_OUT_NULL msgresponse */ 1290 #define MC_CMD_FC_OUT_NULL_LEN 0 1291 1292 /* MC_CMD_FC_OUT_READ32 msgresponse */ 1293 #define MC_CMD_FC_OUT_READ32_LENMIN 4 1294 #define MC_CMD_FC_OUT_READ32_LENMAX 252 1295 #define MC_CMD_FC_OUT_READ32_LENMAX_MCDI2 1020 1296 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) 1297 #define MC_CMD_FC_OUT_READ32_BUFFER_NUM(len) (((len)-0)/4) 1298 #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 1299 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 1300 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 1301 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 1302 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM_MCDI2 255 1303 1304 /* MC_CMD_FC_OUT_WRITE32 msgresponse */ 1305 #define MC_CMD_FC_OUT_WRITE32_LEN 0 1306 1307 /* MC_CMD_FC_OUT_TRC_READ msgresponse */ 1308 #define MC_CMD_FC_OUT_TRC_READ_LEN 16 1309 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 1310 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 1311 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 1312 1313 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ 1314 #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 1315 1316 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */ 1317 #define MC_CMD_FC_OUT_GET_VERSION_LEN 12 1318 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 1319 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_LEN 4 1320 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 1321 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 1322 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 1323 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 1324 1325 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ 1326 #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 1327 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 1328 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 1329 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 1330 1331 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ 1332 #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 1333 1334 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ 1335 #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 1336 1337 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ 1338 #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 1339 1340 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ 1341 #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 1342 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 1343 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_LEN 4 1344 1345 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ 1346 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) 1347 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 1348 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 1349 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 1350 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 1351 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS 1352 #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ 1353 #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ 1354 #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ 1355 #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 1356 #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ 1357 #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ 1358 #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ 1359 #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ 1360 #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ 1361 #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ 1362 #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ 1363 #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ 1364 #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ 1365 #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 1366 #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ 1367 #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ 1368 #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ 1369 #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ 1370 #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ 1371 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ 1372 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ 1373 #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ 1374 #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ 1375 #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ 1376 #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ 1377 /* enum: (Last entry) */ 1378 #define MC_CMD_FC_MAC_RX_NSTATS 0x19 1379 1380 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ 1381 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) 1382 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 1383 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 1384 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 1385 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 1386 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS 1387 #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ 1388 #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ 1389 #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ 1390 #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 1391 #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ 1392 #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ 1393 #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ 1394 #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ 1395 #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ 1396 #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ 1397 #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ 1398 #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ 1399 #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ 1400 #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 1401 #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ 1402 #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ 1403 #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ 1404 #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ 1405 #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ 1406 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ 1407 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ 1408 #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ 1409 /* enum: (Last entry) */ 1410 #define MC_CMD_FC_MAC_TX_NSTATS 0x16 1411 1412 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ 1413 #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) 1414 /* MAC Statistics */ 1415 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 1416 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 1417 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 1418 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 1419 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK 1420 1421 /* MC_CMD_FC_OUT_MAC msgresponse */ 1422 #define MC_CMD_FC_OUT_MAC_LEN 0 1423 1424 /* MC_CMD_FC_OUT_SFP msgresponse */ 1425 #define MC_CMD_FC_OUT_SFP_LEN 0 1426 1427 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ 1428 #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 1429 1430 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ 1431 #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 1432 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 1433 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_LEN 4 1434 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_OFST 0 1435 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 1436 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 1437 /* enum: Test not yet initiated */ 1438 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 1439 /* enum: Test is in progress */ 1440 #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 1441 /* enum: Timed completed */ 1442 #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 1443 /* enum: Test did not complete in specified time */ 1444 #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 1445 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_OFST 0 1446 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 1447 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 1448 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_OFST 0 1449 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 1450 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 1451 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_OFST 0 1452 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 1453 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 1454 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_OFST 0 1455 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 1456 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 1457 /* Test result from FPGA */ 1458 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 1459 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_LEN 4 1460 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_OFST 4 1461 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 1462 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 1463 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_OFST 4 1464 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 1465 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 1466 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_OFST 4 1467 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 1468 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 1469 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_OFST 4 1470 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 1471 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 1472 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_OFST 4 1473 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 1474 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 1475 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_OFST 4 1476 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 1477 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 1478 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_OFST 4 1479 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 1480 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 1481 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_OFST 4 1482 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 1483 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 1484 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ 1485 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ 1486 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ 1487 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ 1488 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ 1489 1490 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */ 1491 #define MC_CMD_FC_OUT_DDR_TEST_LEN 0 1492 1493 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ 1494 #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 1495 /* Assertion status flag. */ 1496 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 1497 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_LEN 4 1498 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_OFST 0 1499 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 1500 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 1501 /* enum: No crash data available */ 1502 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 1503 /* enum: New crash data available */ 1504 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 1505 /* enum: Crash data has been sent */ 1506 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 1507 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_OFST 0 1508 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 1509 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 1510 /* enum: No crash has been recorded. */ 1511 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 1512 /* enum: Crash due to exception. */ 1513 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 1514 /* enum: Crash due to assertion. */ 1515 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 1516 /* Failing PC value */ 1517 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 1518 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_LEN 4 1519 /* Saved GP regs */ 1520 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 1521 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 1522 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 1523 /* Exception Type */ 1524 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 1525 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_LEN 4 1526 /* Instruction at which exception occurred */ 1527 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 1528 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_LEN 4 1529 /* BAD Address that triggered address-based exception */ 1530 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 1531 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_LEN 4 1532 1533 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ 1534 #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 1535 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 1536 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_LEN 4 1537 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_OFST 0 1538 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 1539 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 1540 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_OFST 0 1541 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 1542 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 1543 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_OFST 0 1544 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 1545 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 1546 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_OFST 0 1547 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 1548 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 1549 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_OFST 0 1550 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 1551 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 1552 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_OFST 0 1553 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 1554 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 1555 /* Build timestamp (seconds since epoch) */ 1556 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 1557 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_LEN 4 1558 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 1559 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_LEN 4 1560 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_OFST 8 1561 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 1562 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 1563 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ 1564 #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ 1565 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_OFST 8 1566 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 1567 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 1568 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_OFST 8 1569 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 1570 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 1571 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_OFST 8 1572 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 1573 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 1574 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_OFST 8 1575 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 1576 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 1577 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_OFST 8 1578 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 1579 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 1580 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_OFST 8 1581 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 1582 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 1583 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_OFST 8 1584 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 1585 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 1586 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_OFST 8 1587 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 1588 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 1589 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_OFST 8 1590 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 1591 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 1592 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_OFST 8 1593 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 1594 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 1595 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_OFST 8 1596 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 1597 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 1598 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_OFST 8 1599 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 1600 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 1601 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_OFST 8 1602 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 1603 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 1604 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_OFST 8 1605 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 1606 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 1607 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 1608 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_LEN 4 1609 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_OFST 12 1610 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 1611 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 1612 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_OFST 12 1613 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 1614 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 1615 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ 1616 #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ 1617 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_OFST 12 1618 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 1619 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 1620 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 1621 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_LEN 4 1622 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_OFST 16 1623 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 1624 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 1625 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_OFST 16 1626 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 1627 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 1628 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 1629 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_LEN 4 1630 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_OFST 20 1631 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 1632 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 1633 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_OFST 20 1634 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 1635 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 1636 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 1637 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 1638 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 1639 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 1640 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 1641 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4 1642 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 1643 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_LEN 4 1644 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_OFST 28 1645 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 1646 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 1647 1648 /* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ 1649 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 1650 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 1651 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_LEN 4 1652 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_OFST 0 1653 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 1654 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 1655 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_OFST 0 1656 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 1657 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 1658 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_OFST 0 1659 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 1660 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 1661 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_OFST 0 1662 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 1663 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 1664 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_OFST 0 1665 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 1666 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 1667 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_OFST 0 1668 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 1669 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 1670 /* Build timestamp (seconds since epoch) */ 1671 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 1672 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_LEN 4 1673 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 1674 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_LEN 4 1675 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_OFST 8 1676 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 1677 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 1678 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_OFST 8 1679 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 1680 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 1681 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_OFST 8 1682 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 1683 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 1684 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_OFST 8 1685 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 1686 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 1687 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_OFST 8 1688 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 1689 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 1690 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_OFST 8 1691 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 1692 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 1693 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_OFST 8 1694 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 1695 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 1696 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_OFST 8 1697 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 1698 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 1699 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_OFST 8 1700 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 1701 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 1702 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_OFST 8 1703 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 1704 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 1705 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_OFST 8 1706 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 1707 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 1708 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_OFST 8 1709 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 1710 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 1711 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_OFST 8 1712 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 1713 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 1714 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ 1715 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ 1716 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_OFST 8 1717 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 1718 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 1719 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ 1720 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ 1721 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_OFST 8 1722 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 1723 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 1724 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ 1725 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ 1726 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_OFST 8 1727 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 1728 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 1729 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_OFST 8 1730 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 1731 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 1732 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_OFST 8 1733 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 1734 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 1735 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_OFST 8 1736 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 1737 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 1738 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_OFST 8 1739 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 1740 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 1741 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_OFST 8 1742 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 1743 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 1744 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_OFST 8 1745 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 1746 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 1747 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_OFST 8 1748 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 1749 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 1750 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_OFST 8 1751 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 1752 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 1753 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_OFST 8 1754 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 1755 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 1756 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_OFST 8 1757 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 1758 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 1759 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_OFST 8 1760 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 1761 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 1762 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_OFST 8 1763 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 1764 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 1765 #define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ 1766 #define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ 1767 #define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ 1768 #define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ 1769 #define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ 1770 #define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ 1771 #define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ 1772 #define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ 1773 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 1774 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_LEN 4 1775 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_OFST 12 1776 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 1777 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 1778 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_OFST 12 1779 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 1780 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 1781 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 1782 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 1783 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 1784 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_LEN 4 1785 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_OFST 16 1786 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 1787 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 1788 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_OFST 16 1789 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 1790 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 1791 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 1792 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_LEN 4 1793 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_OFST 20 1794 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 1795 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 1796 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_OFST 20 1797 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 1798 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 1799 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 1800 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_LEN 4 1801 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 1802 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_LEN 4 1803 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_OFST 28 1804 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 1805 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 1806 1807 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ 1808 #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 1809 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 1810 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_LEN 4 1811 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_OFST 0 1812 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 1813 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 1814 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_OFST 0 1815 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 1816 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 1817 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_OFST 0 1818 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 1819 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 1820 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_OFST 0 1821 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 1822 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 1823 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_OFST 0 1824 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 1825 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 1826 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_OFST 0 1827 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 1828 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 1829 /* Build timestamp (seconds since epoch) */ 1830 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 1831 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_LEN 4 1832 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 1833 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_LEN 4 1834 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_OFST 8 1835 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 1836 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 1837 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_OFST 8 1838 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 1839 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 1840 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_OFST 8 1841 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 1842 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 1843 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_OFST 8 1844 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 1845 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 1846 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_OFST 8 1847 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 1848 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 1849 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_OFST 8 1850 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 1851 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 1852 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 1853 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_LEN 4 1854 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_OFST 12 1855 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 1856 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 1857 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_OFST 12 1858 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 1859 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 1860 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 1861 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_LEN 4 1862 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_OFST 16 1863 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 1864 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 1865 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_OFST 16 1866 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 1867 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 1868 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 1869 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_LEN 4 1870 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_OFST 20 1871 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 1872 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 1873 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_OFST 20 1874 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 1875 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 1876 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 1877 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_LEN 4 1878 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 1879 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_LEN 4 1880 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_OFST 28 1881 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 1882 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 1883 1884 /* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ 1885 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 1886 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 1887 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_LEN 4 1888 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_OFST 0 1889 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 1890 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 1891 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_OFST 0 1892 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 1893 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 1894 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_OFST 0 1895 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 1896 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 1897 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_OFST 0 1898 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 1899 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 1900 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_OFST 0 1901 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 1902 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 1903 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_OFST 0 1904 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 1905 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 1906 /* Build timestamp (seconds since epoch) */ 1907 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 1908 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_LEN 4 1909 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 1910 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_LEN 4 1911 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_OFST 8 1912 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 1913 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 1914 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_OFST 8 1915 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 1916 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 1917 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 1918 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_LEN 4 1919 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_OFST 12 1920 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 1921 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 1922 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_OFST 12 1923 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 1924 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 1925 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 1926 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 1927 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 1928 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_LEN 4 1929 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 1930 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_LEN 4 1931 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_OFST 28 1932 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 1933 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 1934 1935 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ 1936 #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 1937 /* Qsys system ID */ 1938 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 1939 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_LEN 4 1940 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_OFST 0 1941 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 1942 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 1943 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_OFST 0 1944 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 1945 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 1946 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_OFST 0 1947 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 1948 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 1949 1950 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ 1951 #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 1952 /* Number of maps */ 1953 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 1954 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_LEN 4 1955 1956 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ 1957 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 1958 /* Index of the map */ 1959 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 1960 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_LEN 4 1961 /* Options for the map */ 1962 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 1963 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_LEN 4 1964 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ 1965 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ 1966 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ 1967 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ 1968 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ 1969 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ 1970 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ 1971 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ 1972 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ 1973 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ 1974 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ 1975 /* Address of start of map */ 1976 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 1977 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 1978 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 1979 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 1980 /* Length of address map */ 1981 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 1982 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 1983 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 1984 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 1985 /* Component information field */ 1986 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 1987 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4 1988 /* License expiry data for map */ 1989 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 1990 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 1991 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 1992 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 1993 /* Name of the component */ 1994 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 1995 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 1996 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 1997 1998 /* MC_CMD_FC_OUT_READ_MAP msgresponse */ 1999 #define MC_CMD_FC_OUT_READ_MAP_LEN 0 2000 2001 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ 2002 #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 2003 /* Number of internal ports */ 2004 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 2005 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_LEN 4 2006 /* Number of external ports */ 2007 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 2008 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_LEN 4 2009 2010 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ 2011 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 2012 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 2013 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_LEN 4 2014 2015 /* MC_CMD_FC_OUT_IO_REL msgresponse */ 2016 #define MC_CMD_FC_OUT_IO_REL_LEN 0 2017 2018 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ 2019 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 2020 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 2021 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_LEN 4 2022 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 2023 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_LEN 4 2024 2025 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ 2026 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 2027 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 2028 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX_MCDI2 1020 2029 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) 2030 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_NUM(len) (((len)-0)/4) 2031 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 2032 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 2033 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 2034 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 2035 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM_MCDI2 255 2036 2037 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ 2038 #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 2039 2040 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ 2041 #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 2042 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 2043 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_LEN 4 2044 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_OFST 0 2045 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 2046 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 2047 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_OFST 0 2048 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 2049 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 2050 /* Transceiver Transmit settings */ 2051 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 2052 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_LEN 4 2053 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_OFST 4 2054 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 2055 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 2056 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_OFST 4 2057 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 2058 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 2059 /* Transceiver Receive settings */ 2060 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 2061 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_LEN 4 2062 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_OFST 8 2063 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 2064 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 2065 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_OFST 8 2066 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 2067 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 2068 /* Rx eye opening */ 2069 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 2070 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_LEN 4 2071 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_OFST 12 2072 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 2073 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 2074 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_OFST 12 2075 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 2076 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 2077 /* PCS status word */ 2078 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 2079 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_LEN 4 2080 /* Link status word */ 2081 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 2082 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_LEN 4 2083 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_OFST 20 2084 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 2085 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 2086 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_OFST 20 2087 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 2088 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 2089 /* Current SFp parameters applied */ 2090 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 2091 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 2092 /* Link speed is 100, 1000, 10000 */ 2093 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 2094 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_LEN 4 2095 /* Length of copper cable - zero when not relevant */ 2096 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 2097 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_LEN 4 2098 /* True if a dual speed SFP+ module */ 2099 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 2100 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_LEN 4 2101 /* True if an SFP Module is present (other fields valid when true) */ 2102 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 2103 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_LEN 4 2104 /* The type of the SFP+ Module */ 2105 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 2106 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_LEN 4 2107 /* PHY config flags */ 2108 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 2109 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_LEN 4 2110 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_OFST 44 2111 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 2112 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 2113 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_OFST 44 2114 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 2115 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 2116 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_OFST 44 2117 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 2118 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 2119 2120 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ 2121 #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 2122 /* MAC configuration applied */ 2123 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 2124 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_LEN 4 2125 /* MTU size */ 2126 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 2127 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_LEN 4 2128 /* IF Mode status */ 2129 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 2130 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_LEN 4 2131 /* MAC address configured */ 2132 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 2133 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 2134 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 2135 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 2136 2137 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ 2138 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) 2139 /* Rx Eye measurements */ 2140 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 2141 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 2142 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 2143 2144 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ 2145 #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 2146 2147 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ 2148 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) 2149 /* Has the eye plot dump completed and data returned is valid? */ 2150 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 2151 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_LEN 4 2152 /* Rx Eye binary plot */ 2153 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 2154 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 2155 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 2156 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 2157 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 2158 2159 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ 2160 #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 2161 2162 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ 2163 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 2164 2165 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ 2166 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 2167 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 2168 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_LEN 4 2169 2170 /* MC_CMD_FC_OUT_UHLINK msgresponse */ 2171 #define MC_CMD_FC_OUT_UHLINK_LEN 0 2172 2173 /* MC_CMD_FC_OUT_SET_LINK msgresponse */ 2174 #define MC_CMD_FC_OUT_SET_LINK_LEN 0 2175 2176 /* MC_CMD_FC_OUT_LICENSE msgresponse */ 2177 #define MC_CMD_FC_OUT_LICENSE_LEN 12 2178 /* Count of valid keys */ 2179 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 2180 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_LEN 4 2181 /* Count of invalid keys */ 2182 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 2183 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_LEN 4 2184 /* Count of blacklisted keys */ 2185 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 2186 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_LEN 4 2187 2188 /* MC_CMD_FC_OUT_STARTUP msgresponse */ 2189 #define MC_CMD_FC_OUT_STARTUP_LEN 4 2190 /* Capabilities of the FPGA/FC */ 2191 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 2192 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_LEN 4 2193 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_OFST 0 2194 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 2195 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 2196 2197 /* MC_CMD_FC_OUT_DMA_READ msgresponse */ 2198 #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 2199 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 2200 #define MC_CMD_FC_OUT_DMA_READ_LENMAX_MCDI2 1020 2201 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) 2202 #define MC_CMD_FC_OUT_DMA_READ_DATA_NUM(len) (((len)-0)/1) 2203 /* The data read */ 2204 #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 2205 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 2206 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 2207 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 2208 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM_MCDI2 1020 2209 2210 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ 2211 #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 2212 /* Timer handle */ 2213 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 2214 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_LEN 4 2215 2216 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ 2217 #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 2218 /* Host supplied handle (unique) */ 2219 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 2220 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_LEN 4 2221 /* Address into which to transfer data in host */ 2222 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 2223 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 2224 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 2225 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 2226 /* AOE address from which to transfer data */ 2227 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 2228 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 2229 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 2230 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 2231 /* Length of AOE transfer (total) */ 2232 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 2233 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4 2234 /* Length of host transfer (total) */ 2235 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 2236 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_LEN 4 2237 /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */ 2238 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 2239 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_LEN 4 2240 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 2241 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_LEN 4 2242 /* When active, start read time */ 2243 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 2244 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 2245 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 2246 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 2247 /* When active, end read time */ 2248 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 2249 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 2250 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 2251 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 2252 2253 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ 2254 #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 2255 2256 /* MC_CMD_FC_OUT_LOG msgresponse */ 2257 #define MC_CMD_FC_OUT_LOG_LEN 0 2258 2259 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ 2260 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 2261 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 2262 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_LEN 4 2263 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 2264 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 2265 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 2266 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 2267 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 2268 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4 2269 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 2270 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_LEN 4 2271 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 2272 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_LEN 4 2273 2274 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ 2275 #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 2276 2277 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ 2278 #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 2279 2280 /* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ 2281 #define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 2282 2283 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ 2284 #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 2285 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 2286 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_LEN 4 2287 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_OFST 0 2288 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 2289 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 2290 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_OFST 0 2291 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 2292 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 2293 2294 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ 2295 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 2296 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 2297 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_LEN 4 2298 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 2299 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_LEN 4 2300 2301 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ 2302 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 2303 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 2304 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX_MCDI2 1016 2305 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) 2306 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_NUM(len) (((len)-0)/8) 2307 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 2308 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_LEN 4 2309 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 2310 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_LEN 4 2311 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 2312 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 2313 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 2314 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 2315 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 2316 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 2317 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM_MCDI2 127 2318 2319 /* MC_CMD_FC_OUT_SPI_READ msgresponse */ 2320 #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 2321 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 2322 #define MC_CMD_FC_OUT_SPI_READ_LENMAX_MCDI2 1020 2323 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) 2324 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_NUM(len) (((len)-0)/4) 2325 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 2326 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 2327 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 2328 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 2329 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM_MCDI2 255 2330 2331 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ 2332 #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 2333 2334 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ 2335 #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 2336 2337 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ 2338 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 2339 /* The 32-bit value read from the toggle count register */ 2340 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 2341 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_LEN 4 2342 /* The 32-bit value read from the clock enable count register */ 2343 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 2344 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_LEN 4 2345 2346 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ 2347 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 2348 2349 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ 2350 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 2351 2352 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ 2353 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 2354 /* DDR soak test status word; bits [4:0] are relevant. */ 2355 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 2356 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_LEN 4 2357 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_OFST 0 2358 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 2359 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 2360 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_OFST 0 2361 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 2362 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 2363 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_OFST 0 2364 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 2365 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 2366 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_OFST 0 2367 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 2368 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 2369 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_OFST 0 2370 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 2371 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 2372 /* DDR soak test error count */ 2373 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 2374 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_LEN 4 2375 2376 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ 2377 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 2378 2379 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ 2380 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 2381 2382 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ 2383 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 2384 2385 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ 2386 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 2387 2388 2389 /***********************************/ 2390 /* MC_CMD_AOE 2391 * AOE operations on MC 2392 */ 2393 #define MC_CMD_AOE 0xa 2394 2395 /* MC_CMD_AOE_IN msgrequest */ 2396 #define MC_CMD_AOE_IN_LEN 4 2397 #define MC_CMD_AOE_IN_OP_HDR_OFST 0 2398 #define MC_CMD_AOE_IN_OP_HDR_LEN 4 2399 #define MC_CMD_AOE_IN_OP_OFST 0 2400 #define MC_CMD_AOE_IN_OP_LBN 0 2401 #define MC_CMD_AOE_IN_OP_WIDTH 8 2402 /* enum: FPGA and CPLD information */ 2403 #define MC_CMD_AOE_OP_INFO 0x1 2404 /* enum: Currents and voltages read from MCP3424s; DEBUG */ 2405 #define MC_CMD_AOE_OP_CURRENTS 0x2 2406 /* enum: Temperatures at locations around the PCB; DEBUG */ 2407 #define MC_CMD_AOE_OP_TEMPERATURES 0x3 2408 /* enum: Set CPLD to idle */ 2409 #define MC_CMD_AOE_OP_CPLD_IDLE 0x4 2410 /* enum: Read from CPLD register */ 2411 #define MC_CMD_AOE_OP_CPLD_READ 0x5 2412 /* enum: Write to CPLD register */ 2413 #define MC_CMD_AOE_OP_CPLD_WRITE 0x6 2414 /* enum: Execute CPLD instruction */ 2415 #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 2416 /* enum: Reprogram the CPLD on the AOE device */ 2417 #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 2418 /* enum: AOE power control */ 2419 #define MC_CMD_AOE_OP_POWER 0x9 2420 /* enum: AOE image loading */ 2421 #define MC_CMD_AOE_OP_LOAD 0xa 2422 /* enum: Fan monitoring */ 2423 #define MC_CMD_AOE_OP_FAN_CONTROL 0xb 2424 /* enum: Fan failures since last reset */ 2425 #define MC_CMD_AOE_OP_FAN_FAILURES 0xc 2426 /* enum: Get generic AOE MAC statistics */ 2427 #define MC_CMD_AOE_OP_MAC_STATS 0xd 2428 /* enum: Retrieve PHY specific information */ 2429 #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe 2430 /* enum: Write a number of JTAG primitive commands, return will give data */ 2431 #define MC_CMD_AOE_OP_JTAG_WRITE 0xf 2432 /* enum: Control access to the FPGA via the Siena JTAG Chain */ 2433 #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 2434 /* enum: Set the MTU offset between Siena and AOE MACs */ 2435 #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 2436 /* enum: How link state is handled */ 2437 #define MC_CMD_AOE_OP_LINK_STATE 0x12 2438 /* enum: How Siena MAC statistics are reported (deprecated - use 2439 * MC_CMD_AOE_OP_ASIC_STATS) 2440 */ 2441 #define MC_CMD_AOE_OP_SIENA_STATS 0x13 2442 /* enum: How native ASIC MAC statistics are reported - replaces the deprecated 2443 * command MC_CMD_AOE_OP_SIENA_STATS 2444 */ 2445 #define MC_CMD_AOE_OP_ASIC_STATS 0x13 2446 /* enum: DDR memory information */ 2447 #define MC_CMD_AOE_OP_DDR 0x14 2448 /* enum: FC control */ 2449 #define MC_CMD_AOE_OP_FC 0x15 2450 /* enum: DDR ECC status reads */ 2451 #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 2452 /* enum: Commands for MC-SPI Master emulation */ 2453 #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 2454 /* enum: Commands for FC boot control */ 2455 #define MC_CMD_AOE_OP_FC_BOOT 0x18 2456 /* enum: Get number of internal ports */ 2457 #define MC_CMD_AOE_OP_GET_ASIC_PORTS 0x19 2458 /* enum: Get FC assert information and register dump */ 2459 #define MC_CMD_AOE_OP_GET_FC_ASSERT_INFO 0x1a 2460 /* enum: Set MUM startup FUSE byte with extended delay */ 2461 #define MC_CMD_AOE_OP_MUM_STARTUP_FUSE 0x1b 2462 2463 /* MC_CMD_AOE_OUT msgresponse */ 2464 #define MC_CMD_AOE_OUT_LEN 0 2465 2466 /* MC_CMD_AOE_IN_INFO msgrequest */ 2467 #define MC_CMD_AOE_IN_INFO_LEN 4 2468 #define MC_CMD_AOE_IN_CMD_OFST 0 2469 #define MC_CMD_AOE_IN_CMD_LEN 4 2470 2471 /* MC_CMD_AOE_IN_CURRENTS msgrequest */ 2472 #define MC_CMD_AOE_IN_CURRENTS_LEN 4 2473 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2474 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2475 2476 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ 2477 #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 2478 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2479 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2480 2481 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ 2482 #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 2483 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2484 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2485 2486 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */ 2487 #define MC_CMD_AOE_IN_CPLD_READ_LEN 12 2488 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2489 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2490 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 2491 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_LEN 4 2492 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 2493 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_LEN 4 2494 2495 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ 2496 #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 2497 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2498 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2499 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 2500 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_LEN 4 2501 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 2502 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_LEN 4 2503 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 2504 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_LEN 4 2505 2506 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ 2507 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 2508 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2509 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2510 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 2511 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_LEN 4 2512 2513 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ 2514 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 2515 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2516 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2517 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 2518 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_LEN 4 2519 /* enum: Reprogram CPLD, poll for completion */ 2520 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 2521 /* enum: Reprogram CPLD, send event on completion */ 2522 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 2523 /* enum: Get status of reprogramming operation */ 2524 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 2525 2526 /* MC_CMD_AOE_IN_POWER msgrequest */ 2527 #define MC_CMD_AOE_IN_POWER_LEN 8 2528 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2529 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2530 /* Turn on or off AOE power */ 2531 #define MC_CMD_AOE_IN_POWER_OP_OFST 4 2532 #define MC_CMD_AOE_IN_POWER_OP_LEN 4 2533 /* enum: Turn off FPGA power */ 2534 #define MC_CMD_AOE_IN_POWER_OFF 0x0 2535 /* enum: Turn on FPGA power */ 2536 #define MC_CMD_AOE_IN_POWER_ON 0x1 2537 /* enum: Clear peak power measurement */ 2538 #define MC_CMD_AOE_IN_POWER_CLEAR 0x2 2539 /* enum: Show current power in sensors output */ 2540 #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 2541 /* enum: Show peak power in sensors output */ 2542 #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 2543 /* enum: Show current DDR current */ 2544 #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 2545 /* enum: Show peak DDR current */ 2546 #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 2547 /* enum: Clear peak DDR current */ 2548 #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 2549 2550 /* MC_CMD_AOE_IN_LOAD msgrequest */ 2551 #define MC_CMD_AOE_IN_LOAD_LEN 8 2552 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2553 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2554 /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence 2555 */ 2556 #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 2557 #define MC_CMD_AOE_IN_LOAD_IMAGE_LEN 4 2558 2559 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ 2560 #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 2561 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2562 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2563 /* If non zero report measured fan RPM rather than nominal */ 2564 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 2565 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_LEN 4 2566 2567 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ 2568 #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 2569 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2570 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2571 2572 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */ 2573 #define MC_CMD_AOE_IN_MAC_STATS_LEN 24 2574 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2575 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2576 /* AOE port */ 2577 #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 2578 #define MC_CMD_AOE_IN_MAC_STATS_PORT_LEN 4 2579 /* Host memory address for statistics */ 2580 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 2581 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 2582 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 2583 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 2584 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 2585 #define MC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4 2586 #define MC_CMD_AOE_IN_MAC_STATS_DMA_OFST 16 2587 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 2588 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 2589 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_OFST 16 2590 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 2591 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 2592 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_OFST 16 2593 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 2594 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 2595 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_OFST 16 2596 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 2597 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 2598 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_OFST 16 2599 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 2600 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 2601 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_OFST 16 2602 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 2603 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 2604 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_OFST 16 2605 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 2606 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 2607 /* Length of DMA data (optional) */ 2608 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 2609 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_LEN 4 2610 2611 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ 2612 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 2613 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2614 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2615 /* AOE port */ 2616 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 2617 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_LEN 4 2618 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 2619 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_LEN 4 2620 2621 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ 2622 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 2623 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 2624 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX_MCDI2 1020 2625 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) 2626 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_NUM(len) (((len)-8)/4) 2627 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2628 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2629 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 2630 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_LEN 4 2631 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 2632 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 2633 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 2634 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 2635 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM_MCDI2 253 2636 2637 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ 2638 #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 2639 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2640 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2641 /* Enable or disable access */ 2642 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 2643 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_LEN 4 2644 /* enum: Enable access */ 2645 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 2646 /* enum: Disable access */ 2647 #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 2648 2649 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ 2650 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 2651 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2652 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2653 /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */ 2654 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 2655 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_LEN 4 2656 /* enum: Apply to all external ports */ 2657 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 2658 /* enum: Apply to all internal ports */ 2659 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 2660 /* The MTU offset to be applied to the external ports */ 2661 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 2662 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_LEN 4 2663 2664 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */ 2665 #define MC_CMD_AOE_IN_LINK_STATE_LEN 8 2666 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2667 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2668 #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 2669 #define MC_CMD_AOE_IN_LINK_STATE_MODE_LEN 4 2670 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_OFST 4 2671 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 2672 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 2673 /* enum: AOE and associated external port */ 2674 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 2675 /* enum: AOE and OR of all external ports */ 2676 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 2677 /* enum: Individual ports */ 2678 #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 2679 /* enum: Configure link state mode on given AOE port */ 2680 #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 2681 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_OFST 4 2682 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 2683 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 2684 /* enum: No-op */ 2685 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 2686 /* enum: logical OR of all SFP ports link status */ 2687 #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 2688 /* enum: logical AND of all SFP ports link status */ 2689 #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 2690 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_OFST 4 2691 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 2692 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 2693 2694 /* MC_CMD_AOE_IN_GET_ASIC_PORTS msgrequest */ 2695 #define MC_CMD_AOE_IN_GET_ASIC_PORTS_LEN 4 2696 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2697 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2698 2699 /* MC_CMD_AOE_IN_GET_FC_ASSERT_INFO msgrequest */ 2700 #define MC_CMD_AOE_IN_GET_FC_ASSERT_INFO_LEN 4 2701 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2702 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2703 2704 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ 2705 #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 2706 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2707 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2708 /* How MAC statistics are reported */ 2709 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 2710 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_LEN 4 2711 /* enum: Statistics from Siena (default) */ 2712 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 2713 /* enum: Statistics from AOE external ports */ 2714 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 2715 2716 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ 2717 #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 2718 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2719 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2720 /* How MAC statistics are reported */ 2721 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 2722 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_LEN 4 2723 /* enum: Statistics from the ASIC (default) */ 2724 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 2725 /* enum: Statistics from AOE external ports */ 2726 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 2727 2728 /* MC_CMD_AOE_IN_DDR msgrequest */ 2729 #define MC_CMD_AOE_IN_DDR_LEN 12 2730 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2731 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2732 #define MC_CMD_AOE_IN_DDR_BANK_OFST 4 2733 #define MC_CMD_AOE_IN_DDR_BANK_LEN 4 2734 /* Enum values, see field(s): */ 2735 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 2736 /* Page index of SPD data */ 2737 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 2738 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_LEN 4 2739 2740 /* MC_CMD_AOE_IN_FC msgrequest */ 2741 #define MC_CMD_AOE_IN_FC_LEN 4 2742 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2743 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2744 2745 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ 2746 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 2747 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2748 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2749 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 2750 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_LEN 4 2751 /* Enum values, see field(s): */ 2752 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 2753 2754 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ 2755 #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 2756 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2757 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2758 /* Basic commands for MC SPI Master emulation. */ 2759 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 2760 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_LEN 4 2761 /* enum: MC SPI read */ 2762 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 2763 /* enum: MC SPI write */ 2764 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 2765 2766 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ 2767 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 2768 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2769 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2770 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 2771 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_LEN 4 2772 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 2773 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_LEN 4 2774 2775 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ 2776 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 2777 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2778 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2779 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 2780 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_LEN 4 2781 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 2782 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_LEN 4 2783 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 2784 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_LEN 4 2785 2786 /* MC_CMD_AOE_IN_FC_BOOT msgrequest */ 2787 #define MC_CMD_AOE_IN_FC_BOOT_LEN 8 2788 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2789 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2790 /* FC boot control flags */ 2791 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4 2792 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_LEN 4 2793 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_OFST 4 2794 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 2795 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 2796 2797 /* MC_CMD_AOE_IN_MUM_STARTUP_FUSE msgrequest: On AOE2, set MUM startup FUSE 2798 * byte with extended delay of 64ms. On some servers with noisy power rails, 2799 * this ensures that the MUM IO pins do not show spurious transitions while the 2800 * power rails are stabilising. Note that this operation requires a hard- 2801 * powercycle to take effect. See bug76446. 2802 */ 2803 #define MC_CMD_AOE_IN_MUM_STARTUP_FUSE_LEN 4 2804 /* Must be MC_CMD_AOE_OP_MUM_STARTUP_FUSE */ 2805 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2806 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2807 2808 /* MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO msgresponse */ 2809 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_LEN 144 2810 /* Assertion status flag. */ 2811 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_OFST 0 2812 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_LEN 4 2813 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_OFST 0 2814 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_LBN 8 2815 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_WIDTH 8 2816 /* enum: No crash data available */ 2817 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 */ 2818 /* enum: New crash data available */ 2819 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 */ 2820 /* enum: Crash data has been sent */ 2821 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 */ 2822 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_OFST 0 2823 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_LBN 0 2824 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_WIDTH 8 2825 /* enum: No crash has been recorded. */ 2826 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 */ 2827 /* enum: Crash due to exception. */ 2828 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 */ 2829 /* enum: Crash due to assertion. */ 2830 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 */ 2831 /* Failing PC value */ 2832 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_OFST 4 2833 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_LEN 4 2834 /* Saved GP regs */ 2835 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_OFST 8 2836 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_LEN 4 2837 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_NUM 31 2838 /* Exception Type */ 2839 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_OFST 132 2840 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_LEN 4 2841 /* Instruction at which exception occurred */ 2842 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_OFST 136 2843 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_LEN 4 2844 /* BAD Address that triggered address-based exception */ 2845 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_OFST 140 2846 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_LEN 4 2847 2848 /* MC_CMD_AOE_OUT_INFO msgresponse */ 2849 #define MC_CMD_AOE_OUT_INFO_LEN 44 2850 /* JTAG IDCODE of CPLD */ 2851 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 2852 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_LEN 4 2853 /* Version of CPLD */ 2854 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 2855 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_LEN 4 2856 /* JTAG IDCODE of FPGA */ 2857 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 2858 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_LEN 4 2859 /* JTAG USERCODE of FPGA */ 2860 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 2861 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_LEN 4 2862 /* FPGA type - read from CPLD straps */ 2863 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 2864 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_LEN 4 2865 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ 2866 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ 2867 /* FPGA state (debug) */ 2868 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 2869 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_LEN 4 2870 /* FPGA image - partition from which loaded */ 2871 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 2872 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_LEN 4 2873 /* FC state */ 2874 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 2875 #define MC_CMD_AOE_OUT_INFO_FC_STATE_LEN 4 2876 /* enum: Set if watchdog working */ 2877 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 2878 /* enum: Set if MC-FC communications working */ 2879 #define MC_CMD_AOE_OUT_INFO_COMMS 0x2 2880 /* Random pieces of information */ 2881 #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 2882 #define MC_CMD_AOE_OUT_INFO_FLAGS_LEN 4 2883 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ 2884 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 2885 /* enum: CPLD apparently good */ 2886 #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 2887 /* enum: FPGA working normally */ 2888 #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 2889 /* enum: FPGA is powered */ 2890 #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 2891 /* enum: Board has incompatible SODIMMs fitted */ 2892 #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 2893 /* enum: Board has ByteBlaster connected */ 2894 #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 2895 /* enum: FPGA Boot flash has an invalid header. */ 2896 #define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 2897 /* enum: FPGA Application flash is accessible. */ 2898 #define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 2899 /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ 2900 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 2901 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_LEN 4 2902 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ 2903 #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ 2904 #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ 2905 #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ 2906 #define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ 2907 /* Result of FC booting - not valid while a ByteBlaster is connected. */ 2908 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 2909 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_LEN 4 2910 /* enum: No error */ 2911 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 2912 /* enum: Bad address set in CPLD */ 2913 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 2914 /* enum: Bad header */ 2915 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 2916 /* enum: Bad text section details */ 2917 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 2918 /* enum: Bad checksum */ 2919 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 2920 /* enum: Bad BSP */ 2921 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 2922 /* enum: Flash mode is invalid */ 2923 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6 2924 /* enum: FC application loaded and execution attempted */ 2925 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 2926 /* enum: FC application Started */ 2927 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81 2928 /* enum: No bootrom in FPGA */ 2929 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff 2930 2931 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */ 2932 #define MC_CMD_AOE_OUT_CURRENTS_LEN 68 2933 /* Set of currents and voltages (mA or mV as appropriate) */ 2934 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 2935 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 2936 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 2937 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ 2938 #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ 2939 #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ 2940 #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ 2941 #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ 2942 #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ 2943 #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ 2944 #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ 2945 #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ 2946 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ 2947 #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ 2948 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ 2949 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ 2950 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ 2951 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ 2952 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ 2953 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ 2954 2955 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ 2956 #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 2957 /* Set of temperatures */ 2958 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 2959 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 2960 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 2961 /* enum: The first set of enum values are for Modena code. */ 2962 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 2963 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ 2964 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ 2965 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ 2966 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ 2967 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ 2968 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ 2969 #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ 2970 #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ 2971 #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ 2972 /* enum: The second set of enum values are for Sorrento code. */ 2973 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0 2974 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */ 2975 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */ 2976 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */ 2977 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */ 2978 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */ 2979 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */ 2980 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */ 2981 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */ 2982 2983 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ 2984 #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 2985 /* The value read from the CPLD */ 2986 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 2987 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_LEN 4 2988 2989 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ 2990 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 2991 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 2992 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX_MCDI2 1020 2993 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) 2994 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_NUM(len) (((len)-0)/4) 2995 /* Failure counts for each fan */ 2996 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 2997 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 2998 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 2999 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 3000 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM_MCDI2 255 3001 3002 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ 3003 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 3004 /* Results of status command (only) */ 3005 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 3006 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_LEN 4 3007 3008 /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */ 3009 #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0 3010 3011 /* MC_CMD_AOE_OUT_POWER_ON msgresponse */ 3012 #define MC_CMD_AOE_OUT_POWER_ON_LEN 0 3013 3014 /* MC_CMD_AOE_OUT_LOAD msgresponse */ 3015 #define MC_CMD_AOE_OUT_LOAD_LEN 0 3016 3017 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ 3018 #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 3019 3020 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA 3021 * for details 3022 */ 3023 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 3024 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 3025 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 3026 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 3027 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 3028 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 3029 3030 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ 3031 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 3032 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 3033 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX_MCDI2 1020 3034 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) 3035 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1) 3036 /* in bytes */ 3037 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 3038 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_LEN 4 3039 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 3040 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 3041 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 3042 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 3043 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM_MCDI2 1016 3044 3045 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ 3046 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 3047 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 3048 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX_MCDI2 1020 3049 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) 3050 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_NUM(len) (((len)-8)/4) 3051 /* Used to align the in and out data blocks so the MC can re-use the cmd */ 3052 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 3053 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_LEN 4 3054 /* out bytes */ 3055 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 3056 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_LEN 4 3057 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 3058 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 3059 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 3060 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 3061 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM_MCDI2 253 3062 3063 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ 3064 #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 3065 3066 /* MC_CMD_AOE_OUT_DDR msgresponse */ 3067 #define MC_CMD_AOE_OUT_DDR_LENMIN 17 3068 #define MC_CMD_AOE_OUT_DDR_LENMAX 252 3069 #define MC_CMD_AOE_OUT_DDR_LENMAX_MCDI2 1020 3070 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) 3071 #define MC_CMD_AOE_OUT_DDR_SPD_NUM(len) (((len)-16)/1) 3072 /* Information on the module. */ 3073 #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 3074 #define MC_CMD_AOE_OUT_DDR_FLAGS_LEN 4 3075 #define MC_CMD_AOE_OUT_DDR_PRESENT_OFST 0 3076 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 3077 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 3078 #define MC_CMD_AOE_OUT_DDR_POWERED_OFST 0 3079 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 3080 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 3081 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_OFST 0 3082 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 3083 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 3084 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_OFST 0 3085 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3 3086 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1 3087 /* Memory size, in MB. */ 3088 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 3089 #define MC_CMD_AOE_OUT_DDR_CAPACITY_LEN 4 3090 /* The memory type, as reported from SPD information */ 3091 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 3092 #define MC_CMD_AOE_OUT_DDR_TYPE_LEN 4 3093 /* Nominal voltage of the module (as applied) */ 3094 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 3095 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_LEN 4 3096 /* SPD data read from the module */ 3097 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 3098 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 3099 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 3100 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 3101 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM_MCDI2 1004 3102 3103 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ 3104 #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 3105 3106 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ 3107 #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 3108 3109 /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */ 3110 #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0 3111 3112 /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */ 3113 #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0 3114 3115 /* MC_CMD_AOE_OUT_FC msgresponse */ 3116 #define MC_CMD_AOE_OUT_FC_LEN 0 3117 3118 /* MC_CMD_AOE_OUT_GET_ASIC_PORTS msgresponse */ 3119 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_LEN 4 3120 /* get the number of internal ports */ 3121 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_OFST 0 3122 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_LEN 4 3123 3124 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ 3125 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 3126 /* Flags describing status info on the module. */ 3127 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 3128 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_LEN 4 3129 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_OFST 0 3130 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 3131 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 3132 /* DDR ECC status on the module. */ 3133 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 3134 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_LEN 4 3135 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_OFST 4 3136 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 3137 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 3138 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_OFST 4 3139 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 3140 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 3141 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_OFST 4 3142 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 3143 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 3144 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_OFST 4 3145 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 3146 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 3147 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_OFST 4 3148 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 3149 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 3150 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_OFST 4 3151 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 3152 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 3153 3154 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ 3155 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 3156 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 3157 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_LEN 4 3158 3159 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ 3160 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 3161 3162 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ 3163 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 3164 3165 /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ 3166 #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 3167 3168 /* MC_CMD_AOE_OUT_MUM_STARTUP_FUSE msgresponse */ 3169 #define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_LEN 4 3170 /* Current value of startup FUSE byte (fusebyte#4) read back after the update 3171 * operation. 3172 */ 3173 #define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_READBACK_VALUE_OFST 0 3174 #define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_READBACK_VALUE_LEN 4 3175 3176 #endif /* _SIENA_MC_DRIVER_PCOL_AOE_H */ 3177