1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2008-2019 Solarflare Communications Inc. 5 */ 6 7 /* 8 * This file is automatically generated. DO NOT EDIT IT. 9 * To make changes, edit the .yml files in smartnic_registry under doc/mcdi/ and 10 * rebuild this file with "make mcdi_headers_v5". 11 */ 12 13 #ifndef _SIENA_MC_DRIVER_PCOL_AOE_H 14 #define _SIENA_MC_DRIVER_PCOL_AOE_H 15 16 17 18 /***********************************/ 19 /* MC_CMD_FC 20 * Perform an FC operation 21 */ 22 #define MC_CMD_FC 0x9 23 #define MC_CMD_FC_MSGSET 0x9 24 25 /* MC_CMD_FC_IN msgrequest */ 26 #define MC_CMD_FC_IN_LEN 4 27 #define MC_CMD_FC_IN_OP_HDR_OFST 0 28 #define MC_CMD_FC_IN_OP_HDR_LEN 4 29 #define MC_CMD_FC_IN_OP_OFST 0 30 #define MC_CMD_FC_IN_OP_LBN 0 31 #define MC_CMD_FC_IN_OP_WIDTH 8 32 /* enum: NULL MCDI command to FC. */ 33 #define MC_CMD_FC_OP_NULL 0x1 34 /* enum: Unused opcode */ 35 #define MC_CMD_FC_OP_UNUSED 0x2 36 /* enum: MAC driver commands */ 37 #define MC_CMD_FC_OP_MAC 0x3 38 /* enum: Read FC memory */ 39 #define MC_CMD_FC_OP_READ32 0x4 40 /* enum: Write to FC memory */ 41 #define MC_CMD_FC_OP_WRITE32 0x5 42 /* enum: Read FC memory */ 43 #define MC_CMD_FC_OP_TRC_READ 0x6 44 /* enum: Write to FC memory */ 45 #define MC_CMD_FC_OP_TRC_WRITE 0x7 46 /* enum: FC firmware Version */ 47 #define MC_CMD_FC_OP_GET_VERSION 0x8 48 /* enum: Read FC memory */ 49 #define MC_CMD_FC_OP_TRC_RX_READ 0x9 50 /* enum: Write to FC memory */ 51 #define MC_CMD_FC_OP_TRC_RX_WRITE 0xa 52 /* enum: SFP parameters */ 53 #define MC_CMD_FC_OP_SFP 0xb 54 /* enum: DDR3 test */ 55 #define MC_CMD_FC_OP_DDR_TEST 0xc 56 /* enum: Get Crash context from FC */ 57 #define MC_CMD_FC_OP_GET_ASSERT 0xd 58 /* enum: Get FPGA Build registers */ 59 #define MC_CMD_FC_OP_FPGA_BUILD 0xe 60 /* enum: Read map support commands */ 61 #define MC_CMD_FC_OP_READ_MAP 0xf 62 /* enum: FC Capabilities */ 63 #define MC_CMD_FC_OP_CAPABILITIES 0x10 64 /* enum: FC Global flags */ 65 #define MC_CMD_FC_OP_GLOBAL_FLAGS 0x11 66 /* enum: FC IO using relative addressing modes */ 67 #define MC_CMD_FC_OP_IO_REL 0x12 68 /* enum: FPGA link information */ 69 #define MC_CMD_FC_OP_UHLINK 0x13 70 /* enum: Configure loopbacks and link on FPGA ports */ 71 #define MC_CMD_FC_OP_SET_LINK 0x14 72 /* enum: Licensing operations relating to AOE */ 73 #define MC_CMD_FC_OP_LICENSE 0x15 74 /* enum: Startup information to the FC */ 75 #define MC_CMD_FC_OP_STARTUP 0x16 76 /* enum: Configure a DMA read */ 77 #define MC_CMD_FC_OP_DMA 0x17 78 /* enum: Configure a timed read */ 79 #define MC_CMD_FC_OP_TIMED_READ 0x18 80 /* enum: Control UART logging */ 81 #define MC_CMD_FC_OP_LOG 0x19 82 /* enum: Get the value of a given clock_id */ 83 #define MC_CMD_FC_OP_CLOCK 0x1a 84 /* enum: DDR3/QDR3 parameters */ 85 #define MC_CMD_FC_OP_DDR 0x1b 86 /* enum: PTP and timestamp control */ 87 #define MC_CMD_FC_OP_TIMESTAMP 0x1c 88 /* enum: Commands for SPI Flash interface */ 89 #define MC_CMD_FC_OP_SPI 0x1d 90 /* enum: Commands for diagnostic components */ 91 #define MC_CMD_FC_OP_DIAG 0x1e 92 /* enum: External AOE port. */ 93 #define MC_CMD_FC_IN_PORT_EXT_OFST 0x0 94 /* enum: Internal AOE port. */ 95 #define MC_CMD_FC_IN_PORT_INT_OFST 0x40 96 97 /* MC_CMD_FC_IN_NULL msgrequest */ 98 #define MC_CMD_FC_IN_NULL_LEN 4 99 #define MC_CMD_FC_IN_CMD_OFST 0 100 #define MC_CMD_FC_IN_CMD_LEN 4 101 102 /* MC_CMD_FC_IN_PHY msgrequest */ 103 #define MC_CMD_FC_IN_PHY_LEN 5 104 /* MC_CMD_FC_IN_CMD_OFST 0 */ 105 /* MC_CMD_FC_IN_CMD_LEN 4 */ 106 /* FC PHY driver operation code */ 107 #define MC_CMD_FC_IN_PHY_OP_OFST 4 108 #define MC_CMD_FC_IN_PHY_OP_LEN 1 109 /* enum: PHY init handler */ 110 #define MC_CMD_FC_OP_PHY_OP_INIT 0x1 111 /* enum: PHY reconfigure handler */ 112 #define MC_CMD_FC_OP_PHY_OP_RECONFIGURE 0x2 113 /* enum: PHY reboot handler */ 114 #define MC_CMD_FC_OP_PHY_OP_REBOOT 0x3 115 /* enum: PHY get_supported_cap handler */ 116 #define MC_CMD_FC_OP_PHY_OP_GET_SUPPORTED_CAP 0x4 117 /* enum: PHY get_config handler */ 118 #define MC_CMD_FC_OP_PHY_OP_GET_CONFIG 0x5 119 /* enum: PHY get_media_info handler */ 120 #define MC_CMD_FC_OP_PHY_OP_GET_MEDIA_INFO 0x6 121 /* enum: PHY set_led handler */ 122 #define MC_CMD_FC_OP_PHY_OP_SET_LED 0x7 123 /* enum: PHY lasi_interrupt handler */ 124 #define MC_CMD_FC_OP_PHY_OP_LASI_INTERRUPT 0x8 125 /* enum: PHY check_link handler */ 126 #define MC_CMD_FC_OP_PHY_OP_CHECK_LINK 0x9 127 /* enum: PHY fill_stats handler */ 128 #define MC_CMD_FC_OP_PHY_OP_FILL_STATS 0xa 129 /* enum: PHY bpx_link_state_changed handler */ 130 #define MC_CMD_FC_OP_PHY_OP_BPX_LINK_STATE_CHANGED 0xb 131 /* enum: PHY get_state handler */ 132 #define MC_CMD_FC_OP_PHY_OP_GET_STATE 0xc 133 /* enum: PHY start_bist handler */ 134 #define MC_CMD_FC_OP_PHY_OP_START_BIST 0xd 135 /* enum: PHY poll_bist handler */ 136 #define MC_CMD_FC_OP_PHY_OP_POLL_BIST 0xe 137 /* enum: PHY nvram_test handler */ 138 #define MC_CMD_FC_OP_PHY_OP_NVRAM_TEST 0xf 139 /* enum: PHY relinquish handler */ 140 #define MC_CMD_FC_OP_PHY_OP_RELINQUISH_SPI 0x10 141 /* enum: PHY read connection from FC - may be not required */ 142 #define MC_CMD_FC_OP_PHY_OP_GET_CONNECTION 0x11 143 /* enum: PHY read flags from FC - may be not required */ 144 #define MC_CMD_FC_OP_PHY_OP_GET_FLAGS 0x12 145 146 /* MC_CMD_FC_IN_PHY_INIT msgrequest */ 147 #define MC_CMD_FC_IN_PHY_INIT_LEN 4 148 #define MC_CMD_FC_IN_PHY_CMD_OFST 0 149 #define MC_CMD_FC_IN_PHY_CMD_LEN 4 150 151 /* MC_CMD_FC_IN_MAC msgrequest */ 152 #define MC_CMD_FC_IN_MAC_LEN 8 153 /* MC_CMD_FC_IN_CMD_OFST 0 */ 154 /* MC_CMD_FC_IN_CMD_LEN 4 */ 155 #define MC_CMD_FC_IN_MAC_HEADER_OFST 4 156 #define MC_CMD_FC_IN_MAC_HEADER_LEN 4 157 #define MC_CMD_FC_IN_MAC_OP_OFST 4 158 #define MC_CMD_FC_IN_MAC_OP_LBN 0 159 #define MC_CMD_FC_IN_MAC_OP_WIDTH 8 160 /* enum: MAC reconfigure handler */ 161 #define MC_CMD_FC_OP_MAC_OP_RECONFIGURE 0x1 162 /* enum: MAC Set command - same as MC_CMD_SET_MAC */ 163 #define MC_CMD_FC_OP_MAC_OP_SET_LINK 0x2 164 /* enum: MAC statistics */ 165 #define MC_CMD_FC_OP_MAC_OP_GET_STATS 0x3 166 /* enum: MAC RX statistics */ 167 #define MC_CMD_FC_OP_MAC_OP_GET_RX_STATS 0x6 168 /* enum: MAC TX statistics */ 169 #define MC_CMD_FC_OP_MAC_OP_GET_TX_STATS 0x7 170 /* enum: MAC Read status */ 171 #define MC_CMD_FC_OP_MAC_OP_READ_STATUS 0x8 172 #define MC_CMD_FC_IN_MAC_PORT_TYPE_OFST 4 173 #define MC_CMD_FC_IN_MAC_PORT_TYPE_LBN 8 174 #define MC_CMD_FC_IN_MAC_PORT_TYPE_WIDTH 8 175 /* enum: External FPGA port. */ 176 #define MC_CMD_FC_PORT_EXT 0x0 177 /* enum: Internal Siena-facing FPGA ports. */ 178 #define MC_CMD_FC_PORT_INT 0x1 179 #define MC_CMD_FC_IN_MAC_PORT_IDX_OFST 4 180 #define MC_CMD_FC_IN_MAC_PORT_IDX_LBN 16 181 #define MC_CMD_FC_IN_MAC_PORT_IDX_WIDTH 8 182 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_OFST 4 183 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_LBN 24 184 #define MC_CMD_FC_IN_MAC_CMD_FORMAT_WIDTH 8 185 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 186 * irrelevant. Port number is derived from pci_fn; passed in FC header. 187 */ 188 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_DEFAULT 0x0 189 /* enum: Override default port number. Port number determined by fields 190 * PORT_TYPE and PORT_IDX. 191 */ 192 #define MC_CMD_FC_OP_MAC_CMD_FORMAT_PORT_OVERRIDE 0x1 193 194 /* MC_CMD_FC_IN_MAC_RECONFIGURE msgrequest */ 195 #define MC_CMD_FC_IN_MAC_RECONFIGURE_LEN 8 196 /* MC_CMD_FC_IN_CMD_OFST 0 */ 197 /* MC_CMD_FC_IN_CMD_LEN 4 */ 198 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 199 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 200 201 /* MC_CMD_FC_IN_MAC_SET_LINK msgrequest */ 202 #define MC_CMD_FC_IN_MAC_SET_LINK_LEN 32 203 /* MC_CMD_FC_IN_CMD_OFST 0 */ 204 /* MC_CMD_FC_IN_CMD_LEN 4 */ 205 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 206 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 207 /* MTU size */ 208 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_OFST 8 209 #define MC_CMD_FC_IN_MAC_SET_LINK_MTU_LEN 4 210 /* Drain Tx FIFO */ 211 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_OFST 12 212 #define MC_CMD_FC_IN_MAC_SET_LINK_DRAIN_LEN 4 213 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_OFST 16 214 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LEN 8 215 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_OFST 16 216 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_LEN 4 217 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_LBN 128 218 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_LO_WIDTH 32 219 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_OFST 20 220 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_LEN 4 221 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_LBN 160 222 #define MC_CMD_FC_IN_MAC_SET_LINK_ADDR_HI_WIDTH 32 223 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_OFST 24 224 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_LEN 4 225 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_OFST 24 226 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_LBN 0 227 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_UNICAST_WIDTH 1 228 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_OFST 24 229 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_LBN 1 230 #define MC_CMD_FC_IN_MAC_SET_LINK_REJECT_BRDCAST_WIDTH 1 231 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_OFST 28 232 #define MC_CMD_FC_IN_MAC_SET_LINK_FCNTL_LEN 4 233 234 /* MC_CMD_FC_IN_MAC_READ_STATUS msgrequest */ 235 #define MC_CMD_FC_IN_MAC_READ_STATUS_LEN 8 236 /* MC_CMD_FC_IN_CMD_OFST 0 */ 237 /* MC_CMD_FC_IN_CMD_LEN 4 */ 238 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 239 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 240 241 /* MC_CMD_FC_IN_MAC_GET_RX_STATS msgrequest */ 242 #define MC_CMD_FC_IN_MAC_GET_RX_STATS_LEN 8 243 /* MC_CMD_FC_IN_CMD_OFST 0 */ 244 /* MC_CMD_FC_IN_CMD_LEN 4 */ 245 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 246 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 247 248 /* MC_CMD_FC_IN_MAC_GET_TX_STATS msgrequest */ 249 #define MC_CMD_FC_IN_MAC_GET_TX_STATS_LEN 8 250 /* MC_CMD_FC_IN_CMD_OFST 0 */ 251 /* MC_CMD_FC_IN_CMD_LEN 4 */ 252 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 253 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 254 255 /* MC_CMD_FC_IN_MAC_GET_STATS msgrequest */ 256 #define MC_CMD_FC_IN_MAC_GET_STATS_LEN 20 257 /* MC_CMD_FC_IN_CMD_OFST 0 */ 258 /* MC_CMD_FC_IN_CMD_LEN 4 */ 259 /* MC_CMD_FC_IN_MAC_HEADER_OFST 4 */ 260 /* MC_CMD_FC_IN_MAC_HEADER_LEN 4 */ 261 /* MC Statistics index */ 262 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_OFST 8 263 #define MC_CMD_FC_IN_MAC_GET_STATS_STATS_INDEX_LEN 4 264 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_OFST 12 265 #define MC_CMD_FC_IN_MAC_GET_STATS_FLAGS_LEN 4 266 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_OFST 12 267 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_LBN 0 268 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_ALL_WIDTH 1 269 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_OFST 12 270 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_LBN 1 271 #define MC_CMD_FC_IN_MAC_GET_STATS_CLEAR_WIDTH 1 272 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_OFST 12 273 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_LBN 2 274 #define MC_CMD_FC_IN_MAC_GET_STATS_UPDATE_WIDTH 1 275 /* Number of statistics to read */ 276 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_OFST 16 277 #define MC_CMD_FC_IN_MAC_GET_STATS_NUM_LEN 4 278 #define MC_CMD_FC_MAC_NSTATS_PER_BLOCK 0x1e /* enum */ 279 #define MC_CMD_FC_MAC_NBYTES_PER_STAT 0x8 /* enum */ 280 281 /* MC_CMD_FC_IN_READ32 msgrequest */ 282 #define MC_CMD_FC_IN_READ32_LEN 16 283 /* MC_CMD_FC_IN_CMD_OFST 0 */ 284 /* MC_CMD_FC_IN_CMD_LEN 4 */ 285 #define MC_CMD_FC_IN_READ32_ADDR_HI_OFST 4 286 #define MC_CMD_FC_IN_READ32_ADDR_HI_LEN 4 287 #define MC_CMD_FC_IN_READ32_ADDR_LO_OFST 8 288 #define MC_CMD_FC_IN_READ32_ADDR_LO_LEN 4 289 #define MC_CMD_FC_IN_READ32_NUMWORDS_OFST 12 290 #define MC_CMD_FC_IN_READ32_NUMWORDS_LEN 4 291 292 /* MC_CMD_FC_IN_WRITE32 msgrequest */ 293 #define MC_CMD_FC_IN_WRITE32_LENMIN 16 294 #define MC_CMD_FC_IN_WRITE32_LENMAX 252 295 #define MC_CMD_FC_IN_WRITE32_LENMAX_MCDI2 1020 296 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) 297 #define MC_CMD_FC_IN_WRITE32_BUFFER_NUM(len) (((len)-12)/4) 298 /* MC_CMD_FC_IN_CMD_OFST 0 */ 299 /* MC_CMD_FC_IN_CMD_LEN 4 */ 300 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 301 #define MC_CMD_FC_IN_WRITE32_ADDR_HI_LEN 4 302 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_OFST 8 303 #define MC_CMD_FC_IN_WRITE32_ADDR_LO_LEN 4 304 #define MC_CMD_FC_IN_WRITE32_BUFFER_OFST 12 305 #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 306 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 307 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 308 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM_MCDI2 252 309 310 /* MC_CMD_FC_IN_TRC_READ msgrequest */ 311 #define MC_CMD_FC_IN_TRC_READ_LEN 12 312 /* MC_CMD_FC_IN_CMD_OFST 0 */ 313 /* MC_CMD_FC_IN_CMD_LEN 4 */ 314 #define MC_CMD_FC_IN_TRC_READ_TRC_OFST 4 315 #define MC_CMD_FC_IN_TRC_READ_TRC_LEN 4 316 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_OFST 8 317 #define MC_CMD_FC_IN_TRC_READ_CHANNEL_LEN 4 318 319 /* MC_CMD_FC_IN_TRC_WRITE msgrequest */ 320 #define MC_CMD_FC_IN_TRC_WRITE_LEN 28 321 /* MC_CMD_FC_IN_CMD_OFST 0 */ 322 /* MC_CMD_FC_IN_CMD_LEN 4 */ 323 #define MC_CMD_FC_IN_TRC_WRITE_TRC_OFST 4 324 #define MC_CMD_FC_IN_TRC_WRITE_TRC_LEN 4 325 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_OFST 8 326 #define MC_CMD_FC_IN_TRC_WRITE_CHANNEL_LEN 4 327 #define MC_CMD_FC_IN_TRC_WRITE_DATA_OFST 12 328 #define MC_CMD_FC_IN_TRC_WRITE_DATA_LEN 4 329 #define MC_CMD_FC_IN_TRC_WRITE_DATA_NUM 4 330 331 /* MC_CMD_FC_IN_GET_VERSION msgrequest */ 332 #define MC_CMD_FC_IN_GET_VERSION_LEN 4 333 /* MC_CMD_FC_IN_CMD_OFST 0 */ 334 /* MC_CMD_FC_IN_CMD_LEN 4 */ 335 336 /* MC_CMD_FC_IN_TRC_RX_READ msgrequest */ 337 #define MC_CMD_FC_IN_TRC_RX_READ_LEN 12 338 /* MC_CMD_FC_IN_CMD_OFST 0 */ 339 /* MC_CMD_FC_IN_CMD_LEN 4 */ 340 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_OFST 4 341 #define MC_CMD_FC_IN_TRC_RX_READ_TRC_LEN 4 342 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_OFST 8 343 #define MC_CMD_FC_IN_TRC_RX_READ_CHANNEL_LEN 4 344 345 /* MC_CMD_FC_IN_TRC_RX_WRITE msgrequest */ 346 #define MC_CMD_FC_IN_TRC_RX_WRITE_LEN 20 347 /* MC_CMD_FC_IN_CMD_OFST 0 */ 348 /* MC_CMD_FC_IN_CMD_LEN 4 */ 349 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_OFST 4 350 #define MC_CMD_FC_IN_TRC_RX_WRITE_TRC_LEN 4 351 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_OFST 8 352 #define MC_CMD_FC_IN_TRC_RX_WRITE_CHANNEL_LEN 4 353 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_OFST 12 354 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_LEN 4 355 #define MC_CMD_FC_IN_TRC_RX_WRITE_DATA_NUM 2 356 357 /* MC_CMD_FC_IN_SFP msgrequest */ 358 #define MC_CMD_FC_IN_SFP_LEN 28 359 /* MC_CMD_FC_IN_CMD_OFST 0 */ 360 /* MC_CMD_FC_IN_CMD_LEN 4 */ 361 /* Link speed is 100, 1000, 10000, 40000 */ 362 #define MC_CMD_FC_IN_SFP_SPEED_OFST 4 363 #define MC_CMD_FC_IN_SFP_SPEED_LEN 4 364 /* Length of copper cable - zero when not relevant (e.g. if cable is fibre) */ 365 #define MC_CMD_FC_IN_SFP_COPPER_LEN_OFST 8 366 #define MC_CMD_FC_IN_SFP_COPPER_LEN_LEN 4 367 /* Not relevant for cards with QSFP modules. For older cards, true if module is 368 * a dual speed SFP+ module. 369 */ 370 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_OFST 12 371 #define MC_CMD_FC_IN_SFP_DUAL_SPEED_LEN 4 372 /* True if an SFP Module is present (other fields valid when true) */ 373 #define MC_CMD_FC_IN_SFP_PRESENT_OFST 16 374 #define MC_CMD_FC_IN_SFP_PRESENT_LEN 4 375 /* The type of the SFP+ Module. For later cards with QSFP modules, this field 376 * is unused and the type is communicated by other means. 377 */ 378 #define MC_CMD_FC_IN_SFP_TYPE_OFST 20 379 #define MC_CMD_FC_IN_SFP_TYPE_LEN 4 380 /* Capabilities corresponding to 1 bits. */ 381 #define MC_CMD_FC_IN_SFP_CAPS_OFST 24 382 #define MC_CMD_FC_IN_SFP_CAPS_LEN 4 383 384 /* MC_CMD_FC_IN_DDR_TEST msgrequest */ 385 #define MC_CMD_FC_IN_DDR_TEST_LEN 8 386 /* MC_CMD_FC_IN_CMD_OFST 0 */ 387 /* MC_CMD_FC_IN_CMD_LEN 4 */ 388 #define MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 389 #define MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 390 #define MC_CMD_FC_IN_DDR_TEST_OP_OFST 4 391 #define MC_CMD_FC_IN_DDR_TEST_OP_LBN 0 392 #define MC_CMD_FC_IN_DDR_TEST_OP_WIDTH 8 393 /* enum: DRAM Test Start */ 394 #define MC_CMD_FC_OP_DDR_TEST_START 0x1 395 /* enum: DRAM Test Poll */ 396 #define MC_CMD_FC_OP_DDR_TEST_POLL 0x2 397 398 /* MC_CMD_FC_IN_DDR_TEST_START msgrequest */ 399 #define MC_CMD_FC_IN_DDR_TEST_START_LEN 12 400 /* MC_CMD_FC_IN_CMD_OFST 0 */ 401 /* MC_CMD_FC_IN_CMD_LEN 4 */ 402 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 403 /* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */ 404 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_OFST 8 405 #define MC_CMD_FC_IN_DDR_TEST_START_MASK_LEN 4 406 #define MC_CMD_FC_IN_DDR_TEST_START_T0_OFST 8 407 #define MC_CMD_FC_IN_DDR_TEST_START_T0_LBN 0 408 #define MC_CMD_FC_IN_DDR_TEST_START_T0_WIDTH 1 409 #define MC_CMD_FC_IN_DDR_TEST_START_T1_OFST 8 410 #define MC_CMD_FC_IN_DDR_TEST_START_T1_LBN 1 411 #define MC_CMD_FC_IN_DDR_TEST_START_T1_WIDTH 1 412 #define MC_CMD_FC_IN_DDR_TEST_START_B0_OFST 8 413 #define MC_CMD_FC_IN_DDR_TEST_START_B0_LBN 2 414 #define MC_CMD_FC_IN_DDR_TEST_START_B0_WIDTH 1 415 #define MC_CMD_FC_IN_DDR_TEST_START_B1_OFST 8 416 #define MC_CMD_FC_IN_DDR_TEST_START_B1_LBN 3 417 #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 418 419 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ 420 #define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 421 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 422 #define MC_CMD_FC_IN_DDR_TEST_CMD_LEN 4 423 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ 424 /* MC_CMD_FC_IN_DDR_TEST_HEADER_LEN 4 */ 425 /* Clear previous test result and prepare for restarting DDR test */ 426 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 427 #define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_LEN 4 428 429 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ 430 #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 431 /* MC_CMD_FC_IN_CMD_OFST 0 */ 432 /* MC_CMD_FC_IN_CMD_LEN 4 */ 433 434 /* MC_CMD_FC_IN_FPGA_BUILD msgrequest */ 435 #define MC_CMD_FC_IN_FPGA_BUILD_LEN 8 436 /* MC_CMD_FC_IN_CMD_OFST 0 */ 437 /* MC_CMD_FC_IN_CMD_LEN 4 */ 438 /* FPGA build info operation code */ 439 #define MC_CMD_FC_IN_FPGA_BUILD_OP_OFST 4 440 #define MC_CMD_FC_IN_FPGA_BUILD_OP_LEN 4 441 /* enum: Get the build registers */ 442 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD 0x1 443 /* enum: Get the services registers */ 444 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 445 /* enum: Get the BSP version */ 446 #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 447 /* enum: Get build register for V2 (SFA974X) */ 448 #define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 449 /* enum: GEt the services register for V2 (SFA974X) */ 450 #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 451 452 /* MC_CMD_FC_IN_READ_MAP msgrequest */ 453 #define MC_CMD_FC_IN_READ_MAP_LEN 8 454 /* MC_CMD_FC_IN_CMD_OFST 0 */ 455 /* MC_CMD_FC_IN_CMD_LEN 4 */ 456 #define MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 457 #define MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 458 #define MC_CMD_FC_IN_READ_MAP_OP_OFST 4 459 #define MC_CMD_FC_IN_READ_MAP_OP_LBN 0 460 #define MC_CMD_FC_IN_READ_MAP_OP_WIDTH 8 461 /* enum: Get the number of map regions */ 462 #define MC_CMD_FC_OP_READ_MAP_COUNT 0x1 463 /* enum: Get the specified map */ 464 #define MC_CMD_FC_OP_READ_MAP_INDEX 0x2 465 466 /* MC_CMD_FC_IN_READ_MAP_COUNT msgrequest */ 467 #define MC_CMD_FC_IN_READ_MAP_COUNT_LEN 8 468 /* MC_CMD_FC_IN_CMD_OFST 0 */ 469 /* MC_CMD_FC_IN_CMD_LEN 4 */ 470 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 471 /* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */ 472 473 /* MC_CMD_FC_IN_READ_MAP_INDEX msgrequest */ 474 #define MC_CMD_FC_IN_READ_MAP_INDEX_LEN 12 475 /* MC_CMD_FC_IN_CMD_OFST 0 */ 476 /* MC_CMD_FC_IN_CMD_LEN 4 */ 477 /* MC_CMD_FC_IN_READ_MAP_HEADER_OFST 4 */ 478 /* MC_CMD_FC_IN_READ_MAP_HEADER_LEN 4 */ 479 #define MC_CMD_FC_IN_MAP_INDEX_OFST 8 480 #define MC_CMD_FC_IN_MAP_INDEX_LEN 4 481 482 /* MC_CMD_FC_IN_CAPABILITIES msgrequest */ 483 #define MC_CMD_FC_IN_CAPABILITIES_LEN 4 484 /* MC_CMD_FC_IN_CMD_OFST 0 */ 485 /* MC_CMD_FC_IN_CMD_LEN 4 */ 486 487 /* MC_CMD_FC_IN_GLOBAL_FLAGS msgrequest */ 488 #define MC_CMD_FC_IN_GLOBAL_FLAGS_LEN 8 489 /* MC_CMD_FC_IN_CMD_OFST 0 */ 490 /* MC_CMD_FC_IN_CMD_LEN 4 */ 491 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_OFST 4 492 #define MC_CMD_FC_IN_GLOBAL_FLAGS_FLAGS_LEN 4 493 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_OFST 4 494 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_LBN 0 495 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_CABLE_PLUGGED_IN_WIDTH 1 496 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_OFST 4 497 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_LBN 1 498 #define MC_CMD_FC_IN_GLOBAL_FLAGS_RX_TUNING_LINK_MONITORING_WIDTH 1 499 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_OFST 4 500 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_LBN 2 501 #define MC_CMD_FC_IN_GLOBAL_FLAGS_DFE_ENABLE_WIDTH 1 502 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_OFST 4 503 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_LBN 3 504 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_EYE_ENABLE_WIDTH 1 505 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_OFST 4 506 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_LBN 4 507 #define MC_CMD_FC_IN_GLOBAL_FLAGS_1D_TUNING_ENABLE_WIDTH 1 508 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_OFST 4 509 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_LBN 5 510 #define MC_CMD_FC_IN_GLOBAL_FLAGS_OFFCAL_ENABLE_WIDTH 1 511 512 /* MC_CMD_FC_IN_IO_REL msgrequest */ 513 #define MC_CMD_FC_IN_IO_REL_LEN 8 514 /* MC_CMD_FC_IN_CMD_OFST 0 */ 515 /* MC_CMD_FC_IN_CMD_LEN 4 */ 516 #define MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 517 #define MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 518 #define MC_CMD_FC_IN_IO_REL_OP_OFST 4 519 #define MC_CMD_FC_IN_IO_REL_OP_LBN 0 520 #define MC_CMD_FC_IN_IO_REL_OP_WIDTH 8 521 /* enum: Get the base address that the FC applies to relative commands */ 522 #define MC_CMD_FC_IN_IO_REL_GET_ADDR 0x1 523 /* enum: Read data */ 524 #define MC_CMD_FC_IN_IO_REL_READ32 0x2 525 /* enum: Write data */ 526 #define MC_CMD_FC_IN_IO_REL_WRITE32 0x3 527 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_OFST 4 528 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_LBN 8 529 #define MC_CMD_FC_IN_IO_REL_COMP_TYPE_WIDTH 8 530 /* enum: Application address space */ 531 #define MC_CMD_FC_COMP_TYPE_APP_ADDR_SPACE 0x1 532 /* enum: Flash address space */ 533 #define MC_CMD_FC_COMP_TYPE_FLASH 0x2 534 535 /* MC_CMD_FC_IN_IO_REL_GET_ADDR msgrequest */ 536 #define MC_CMD_FC_IN_IO_REL_GET_ADDR_LEN 8 537 /* MC_CMD_FC_IN_CMD_OFST 0 */ 538 /* MC_CMD_FC_IN_CMD_LEN 4 */ 539 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 540 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 541 542 /* MC_CMD_FC_IN_IO_REL_READ32 msgrequest */ 543 #define MC_CMD_FC_IN_IO_REL_READ32_LEN 20 544 /* MC_CMD_FC_IN_CMD_OFST 0 */ 545 /* MC_CMD_FC_IN_CMD_LEN 4 */ 546 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 547 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 548 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_OFST 8 549 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_HI_LEN 4 550 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_OFST 12 551 #define MC_CMD_FC_IN_IO_REL_READ32_ADDR_LO_LEN 4 552 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_OFST 16 553 #define MC_CMD_FC_IN_IO_REL_READ32_NUMWORDS_LEN 4 554 555 /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ 556 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 557 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 558 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX_MCDI2 1020 559 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) 560 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_NUM(len) (((len)-16)/4) 561 /* MC_CMD_FC_IN_CMD_OFST 0 */ 562 /* MC_CMD_FC_IN_CMD_LEN 4 */ 563 /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ 564 /* MC_CMD_FC_IN_IO_REL_HEADER_LEN 4 */ 565 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_OFST 8 566 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_HI_LEN 4 567 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_OFST 12 568 #define MC_CMD_FC_IN_IO_REL_WRITE32_ADDR_LO_LEN 4 569 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_OFST 16 570 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 571 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 572 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 573 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM_MCDI2 251 574 575 /* MC_CMD_FC_IN_UHLINK msgrequest */ 576 #define MC_CMD_FC_IN_UHLINK_LEN 8 577 /* MC_CMD_FC_IN_CMD_OFST 0 */ 578 /* MC_CMD_FC_IN_CMD_LEN 4 */ 579 #define MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 580 #define MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 581 #define MC_CMD_FC_IN_UHLINK_OP_OFST 4 582 #define MC_CMD_FC_IN_UHLINK_OP_LBN 0 583 #define MC_CMD_FC_IN_UHLINK_OP_WIDTH 8 584 /* enum: Get PHY configuration info */ 585 #define MC_CMD_FC_OP_UHLINK_PHY 0x1 586 /* enum: Get MAC configuration info */ 587 #define MC_CMD_FC_OP_UHLINK_MAC 0x2 588 /* enum: Get Rx eye table */ 589 #define MC_CMD_FC_OP_UHLINK_RX_EYE 0x3 590 /* enum: Get Rx eye plot */ 591 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT 0x4 592 /* enum: Get Rx eye plot */ 593 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT 0x5 594 /* enum: Retune Rx settings */ 595 #define MC_CMD_FC_OP_UHLINK_RX_TUNE 0x6 596 /* enum: Set loopback mode on fpga port */ 597 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET 0x7 598 /* enum: Get loopback mode config state on fpga port */ 599 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET 0x8 600 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_OFST 4 601 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_LBN 8 602 #define MC_CMD_FC_IN_UHLINK_PORT_TYPE_WIDTH 8 603 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_OFST 4 604 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_LBN 16 605 #define MC_CMD_FC_IN_UHLINK_PORT_IDX_WIDTH 8 606 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_OFST 4 607 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_LBN 24 608 #define MC_CMD_FC_IN_UHLINK_CMD_FORMAT_WIDTH 8 609 /* enum: Default FC command format; the fields PORT_TYPE and PORT_IDX are 610 * irrelevant. Port number is derived from pci_fn; passed in FC header. 611 */ 612 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_DEFAULT 0x0 613 /* enum: Override default port number. Port number determined by fields 614 * PORT_TYPE and PORT_IDX. 615 */ 616 #define MC_CMD_FC_OP_UHLINK_CMD_FORMAT_PORT_OVERRIDE 0x1 617 618 /* MC_CMD_FC_OP_UHLINK_PHY msgrequest */ 619 #define MC_CMD_FC_OP_UHLINK_PHY_LEN 8 620 /* MC_CMD_FC_IN_CMD_OFST 0 */ 621 /* MC_CMD_FC_IN_CMD_LEN 4 */ 622 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 623 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 624 625 /* MC_CMD_FC_OP_UHLINK_MAC msgrequest */ 626 #define MC_CMD_FC_OP_UHLINK_MAC_LEN 8 627 /* MC_CMD_FC_IN_CMD_OFST 0 */ 628 /* MC_CMD_FC_IN_CMD_LEN 4 */ 629 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 630 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 631 632 /* MC_CMD_FC_OP_UHLINK_RX_EYE msgrequest */ 633 #define MC_CMD_FC_OP_UHLINK_RX_EYE_LEN 12 634 /* MC_CMD_FC_IN_CMD_OFST 0 */ 635 /* MC_CMD_FC_IN_CMD_LEN 4 */ 636 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 637 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 638 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_OFST 8 639 #define MC_CMD_FC_OP_UHLINK_RX_EYE_INDEX_LEN 4 640 #define MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 0x30 /* enum */ 641 642 /* MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT msgrequest */ 643 #define MC_CMD_FC_OP_UHLINK_DUMP_RX_EYE_PLOT_LEN 8 644 /* MC_CMD_FC_IN_CMD_OFST 0 */ 645 /* MC_CMD_FC_IN_CMD_LEN 4 */ 646 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 647 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 648 649 /* MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT msgrequest */ 650 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_LEN 20 651 /* MC_CMD_FC_IN_CMD_OFST 0 */ 652 /* MC_CMD_FC_IN_CMD_LEN 4 */ 653 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 654 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 655 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_OFST 8 656 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_DC_GAIN_LEN 4 657 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_OFST 12 658 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_EQ_CONTROL_LEN 4 659 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_OFST 16 660 #define MC_CMD_FC_OP_UHLINK_READ_RX_EYE_PLOT_INDEX_LEN 4 661 #define MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 0x1e /* enum */ 662 663 /* MC_CMD_FC_OP_UHLINK_RX_TUNE msgrequest */ 664 #define MC_CMD_FC_OP_UHLINK_RX_TUNE_LEN 8 665 /* MC_CMD_FC_IN_CMD_OFST 0 */ 666 /* MC_CMD_FC_IN_CMD_LEN 4 */ 667 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 668 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 669 670 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_SET msgrequest */ 671 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_LEN 16 672 /* MC_CMD_FC_IN_CMD_OFST 0 */ 673 /* MC_CMD_FC_IN_CMD_LEN 4 */ 674 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 675 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 676 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_OFST 8 677 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_TYPE_LEN 4 678 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PCS_SERIAL 0x0 /* enum */ 679 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_PRE_CDR 0x1 /* enum */ 680 #define MC_CMD_FC_UHLINK_LOOPBACK_TYPE_PMA_POST_CDR 0x2 /* enum */ 681 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_OFST 12 682 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_SET_STATE_LEN 4 683 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_OFF 0x0 /* enum */ 684 #define MC_CMD_FC_UHLINK_LOOPBACK_STATE_ON 0x1 /* enum */ 685 686 /* MC_CMD_FC_OP_UHLINK_LOOPBACK_GET msgrequest */ 687 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_LEN 12 688 /* MC_CMD_FC_IN_CMD_OFST 0 */ 689 /* MC_CMD_FC_IN_CMD_LEN 4 */ 690 /* MC_CMD_FC_IN_UHLINK_HEADER_OFST 4 */ 691 /* MC_CMD_FC_IN_UHLINK_HEADER_LEN 4 */ 692 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_OFST 8 693 #define MC_CMD_FC_OP_UHLINK_LOOPBACK_GET_TYPE_LEN 4 694 695 /* MC_CMD_FC_IN_SET_LINK msgrequest */ 696 #define MC_CMD_FC_IN_SET_LINK_LEN 16 697 /* MC_CMD_FC_IN_CMD_OFST 0 */ 698 /* MC_CMD_FC_IN_CMD_LEN 4 */ 699 /* See MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ 700 #define MC_CMD_FC_IN_SET_LINK_MODE_OFST 4 701 #define MC_CMD_FC_IN_SET_LINK_MODE_LEN 4 702 #define MC_CMD_FC_IN_SET_LINK_SPEED_OFST 8 703 #define MC_CMD_FC_IN_SET_LINK_SPEED_LEN 4 704 #define MC_CMD_FC_IN_SET_LINK_FLAGS_OFST 12 705 #define MC_CMD_FC_IN_SET_LINK_FLAGS_LEN 4 706 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_OFST 12 707 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_LBN 0 708 #define MC_CMD_FC_IN_SET_LINK_LOWPOWER_WIDTH 1 709 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_OFST 12 710 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_LBN 1 711 #define MC_CMD_FC_IN_SET_LINK_POWEROFF_WIDTH 1 712 #define MC_CMD_FC_IN_SET_LINK_TXDIS_OFST 12 713 #define MC_CMD_FC_IN_SET_LINK_TXDIS_LBN 2 714 #define MC_CMD_FC_IN_SET_LINK_TXDIS_WIDTH 1 715 716 /* MC_CMD_FC_IN_LICENSE msgrequest */ 717 #define MC_CMD_FC_IN_LICENSE_LEN 8 718 /* MC_CMD_FC_IN_CMD_OFST 0 */ 719 /* MC_CMD_FC_IN_CMD_LEN 4 */ 720 #define MC_CMD_FC_IN_LICENSE_OP_OFST 4 721 #define MC_CMD_FC_IN_LICENSE_OP_LEN 4 722 #define MC_CMD_FC_IN_LICENSE_UPDATE_LICENSE 0x0 /* enum */ 723 #define MC_CMD_FC_IN_LICENSE_GET_KEY_STATS 0x1 /* enum */ 724 725 /* MC_CMD_FC_IN_STARTUP msgrequest */ 726 #define MC_CMD_FC_IN_STARTUP_LEN 40 727 /* MC_CMD_FC_IN_CMD_OFST 0 */ 728 /* MC_CMD_FC_IN_CMD_LEN 4 */ 729 #define MC_CMD_FC_IN_STARTUP_BASE_OFST 4 730 #define MC_CMD_FC_IN_STARTUP_BASE_LEN 4 731 #define MC_CMD_FC_IN_STARTUP_LENGTH_OFST 8 732 #define MC_CMD_FC_IN_STARTUP_LENGTH_LEN 4 733 /* Length of identifier */ 734 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_OFST 12 735 #define MC_CMD_FC_IN_STARTUP_IDLENGTH_LEN 4 736 /* Identifier for AOE FPGA */ 737 #define MC_CMD_FC_IN_STARTUP_ID_OFST 16 738 #define MC_CMD_FC_IN_STARTUP_ID_LEN 1 739 #define MC_CMD_FC_IN_STARTUP_ID_NUM 24 740 741 /* MC_CMD_FC_IN_DMA msgrequest */ 742 #define MC_CMD_FC_IN_DMA_LEN 8 743 /* MC_CMD_FC_IN_CMD_OFST 0 */ 744 /* MC_CMD_FC_IN_CMD_LEN 4 */ 745 #define MC_CMD_FC_IN_DMA_OP_OFST 4 746 #define MC_CMD_FC_IN_DMA_OP_LEN 4 747 #define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ 748 #define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ 749 750 /* MC_CMD_FC_IN_DMA_STOP msgrequest */ 751 #define MC_CMD_FC_IN_DMA_STOP_LEN 12 752 /* MC_CMD_FC_IN_CMD_OFST 0 */ 753 /* MC_CMD_FC_IN_CMD_LEN 4 */ 754 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 755 /* MC_CMD_FC_IN_DMA_OP_LEN 4 */ 756 /* FC supplied handle */ 757 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_OFST 8 758 #define MC_CMD_FC_IN_DMA_STOP_FC_HANDLE_LEN 4 759 760 /* MC_CMD_FC_IN_DMA_READ msgrequest */ 761 #define MC_CMD_FC_IN_DMA_READ_LEN 16 762 /* MC_CMD_FC_IN_CMD_OFST 0 */ 763 /* MC_CMD_FC_IN_CMD_LEN 4 */ 764 /* MC_CMD_FC_IN_DMA_OP_OFST 4 */ 765 /* MC_CMD_FC_IN_DMA_OP_LEN 4 */ 766 #define MC_CMD_FC_IN_DMA_READ_OFFSET_OFST 8 767 #define MC_CMD_FC_IN_DMA_READ_OFFSET_LEN 4 768 #define MC_CMD_FC_IN_DMA_READ_LENGTH_OFST 12 769 #define MC_CMD_FC_IN_DMA_READ_LENGTH_LEN 4 770 771 /* MC_CMD_FC_IN_TIMED_READ msgrequest */ 772 #define MC_CMD_FC_IN_TIMED_READ_LEN 8 773 /* MC_CMD_FC_IN_CMD_OFST 0 */ 774 /* MC_CMD_FC_IN_CMD_LEN 4 */ 775 #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 776 #define MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 777 #define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ 778 #define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ 779 #define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ 780 781 /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ 782 #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 783 /* MC_CMD_FC_IN_CMD_OFST 0 */ 784 /* MC_CMD_FC_IN_CMD_LEN 4 */ 785 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 786 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 787 /* Host supplied handle (unique) */ 788 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_OFST 8 789 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_HANDLE_LEN 4 790 /* Address into which to transfer data in host */ 791 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_OFST 12 792 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LEN 8 793 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_OFST 12 794 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_LEN 4 795 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_LBN 96 796 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_LO_WIDTH 32 797 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_OFST 16 798 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_LEN 4 799 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_LBN 128 800 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_DMA_ADDRESS_HI_WIDTH 32 801 /* AOE address from which to transfer data */ 802 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_OFST 20 803 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LEN 8 804 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_OFST 20 805 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_LEN 4 806 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_LBN 160 807 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_LO_WIDTH 32 808 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_OFST 24 809 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_LEN 4 810 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_LBN 192 811 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_ADDRESS_HI_WIDTH 32 812 /* Length of AOE transfer (total) */ 813 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_OFST 28 814 #define MC_CMD_FC_IN_TIMED_READ_SET_AOE_LENGTH_LEN 4 815 /* Length of host transfer (total) */ 816 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_OFST 32 817 #define MC_CMD_FC_IN_TIMED_READ_SET_HOST_LENGTH_LEN 4 818 /* Offset back from aoe_address to apply operation to */ 819 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_OFST 36 820 #define MC_CMD_FC_IN_TIMED_READ_SET_OFFSET_LEN 4 821 /* Data to apply at offset */ 822 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_OFST 40 823 #define MC_CMD_FC_IN_TIMED_READ_SET_DATA_LEN 4 824 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_OFST 44 825 #define MC_CMD_FC_IN_TIMED_READ_SET_FLAGS_LEN 4 826 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_OFST 44 827 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_LBN 0 828 #define MC_CMD_FC_IN_TIMED_READ_SET_INDIRECT_WIDTH 1 829 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_OFST 44 830 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_LBN 1 831 #define MC_CMD_FC_IN_TIMED_READ_SET_DOUBLE_WIDTH 1 832 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_OFST 44 833 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_LBN 2 834 #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 835 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_OFST 44 836 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 837 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 838 #define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ 839 #define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ 840 #define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ 841 #define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ 842 /* Period at which reads are performed (100ms units) */ 843 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 844 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_LEN 4 845 846 /* MC_CMD_FC_IN_TIMED_READ_GET msgrequest */ 847 #define MC_CMD_FC_IN_TIMED_READ_GET_LEN 12 848 /* MC_CMD_FC_IN_CMD_OFST 0 */ 849 /* MC_CMD_FC_IN_CMD_LEN 4 */ 850 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 851 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 852 /* FC supplied handle */ 853 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_OFST 8 854 #define MC_CMD_FC_IN_TIMED_READ_GET_FC_HANDLE_LEN 4 855 856 /* MC_CMD_FC_IN_TIMED_READ_CLEAR msgrequest */ 857 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_LEN 12 858 /* MC_CMD_FC_IN_CMD_OFST 0 */ 859 /* MC_CMD_FC_IN_CMD_LEN 4 */ 860 /* MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 */ 861 /* MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 */ 862 /* FC supplied handle */ 863 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_OFST 8 864 #define MC_CMD_FC_IN_TIMED_READ_CLEAR_FC_HANDLE_LEN 4 865 866 /* MC_CMD_FC_IN_LOG msgrequest */ 867 #define MC_CMD_FC_IN_LOG_LEN 8 868 /* MC_CMD_FC_IN_CMD_OFST 0 */ 869 /* MC_CMD_FC_IN_CMD_LEN 4 */ 870 #define MC_CMD_FC_IN_LOG_OP_OFST 4 871 #define MC_CMD_FC_IN_LOG_OP_LEN 4 872 #define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ 873 #define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ 874 875 /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ 876 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 877 /* MC_CMD_FC_IN_CMD_OFST 0 */ 878 /* MC_CMD_FC_IN_CMD_LEN 4 */ 879 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 880 /* MC_CMD_FC_IN_LOG_OP_LEN 4 */ 881 /* Partition offset into flash */ 882 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_OFST 8 883 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_OFFSET_LEN 4 884 /* Partition length */ 885 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_OFST 12 886 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LENGTH_LEN 4 887 /* Partition erase size */ 888 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_OFST 16 889 #define MC_CMD_FC_IN_LOG_ADDR_RANGE_ERASE_SIZE_LEN 4 890 891 /* MC_CMD_FC_IN_LOG_JTAG_UART msgrequest */ 892 #define MC_CMD_FC_IN_LOG_JTAG_UART_LEN 12 893 /* MC_CMD_FC_IN_CMD_OFST 0 */ 894 /* MC_CMD_FC_IN_CMD_LEN 4 */ 895 /* MC_CMD_FC_IN_LOG_OP_OFST 4 */ 896 /* MC_CMD_FC_IN_LOG_OP_LEN 4 */ 897 /* Enable/disable printing to JTAG UART */ 898 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 899 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_LEN 4 900 901 /* MC_CMD_FC_IN_CLOCK msgrequest: Perform a clock operation */ 902 #define MC_CMD_FC_IN_CLOCK_LEN 12 903 /* MC_CMD_FC_IN_CMD_OFST 0 */ 904 /* MC_CMD_FC_IN_CMD_LEN 4 */ 905 #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 906 #define MC_CMD_FC_IN_CLOCK_OP_LEN 4 907 #define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ 908 #define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ 909 #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 910 #define MC_CMD_FC_IN_CLOCK_ID_LEN 4 911 #define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ 912 #define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ 913 914 /* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest: Retrieve the clock value of the 915 * specified clock 916 */ 917 #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 918 /* MC_CMD_FC_IN_CMD_OFST 0 */ 919 /* MC_CMD_FC_IN_CMD_LEN 4 */ 920 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 921 /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ 922 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 923 /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ 924 925 /* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest: Set the clock value of the specified 926 * clock 927 */ 928 #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 929 /* MC_CMD_FC_IN_CMD_OFST 0 */ 930 /* MC_CMD_FC_IN_CMD_LEN 4 */ 931 /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ 932 /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ 933 /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ 934 /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ 935 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_OFST 12 936 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 937 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 938 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_LEN 4 939 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_LBN 96 940 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_WIDTH 32 941 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 942 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_LEN 4 943 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_LBN 128 944 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_WIDTH 32 945 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 946 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4 947 948 /* MC_CMD_FC_IN_DDR msgrequest */ 949 #define MC_CMD_FC_IN_DDR_LEN 12 950 /* MC_CMD_FC_IN_CMD_OFST 0 */ 951 /* MC_CMD_FC_IN_CMD_LEN 4 */ 952 #define MC_CMD_FC_IN_DDR_OP_OFST 4 953 #define MC_CMD_FC_IN_DDR_OP_LEN 4 954 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ 955 #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ 956 #define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ 957 #define MC_CMD_FC_IN_DDR_BANK_OFST 8 958 #define MC_CMD_FC_IN_DDR_BANK_LEN 4 959 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ 960 #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ 961 #define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ 962 #define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ 963 #define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ 964 965 /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ 966 #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 967 /* MC_CMD_FC_IN_CMD_OFST 0 */ 968 /* MC_CMD_FC_IN_CMD_LEN 4 */ 969 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 970 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 971 /* Affected bank */ 972 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 973 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 974 /* Flags */ 975 #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 976 #define MC_CMD_FC_IN_DDR_FLAGS_LEN 4 977 #define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ 978 /* 128-byte page of serial presence detect data read from module's EEPROM */ 979 #define MC_CMD_FC_IN_DDR_SPD_OFST 16 980 #define MC_CMD_FC_IN_DDR_SPD_LEN 1 981 #define MC_CMD_FC_IN_DDR_SPD_NUM 128 982 /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ 983 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 984 #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_LEN 4 985 986 /* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ 987 #define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 988 /* MC_CMD_FC_IN_CMD_OFST 0 */ 989 /* MC_CMD_FC_IN_CMD_LEN 4 */ 990 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 991 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 992 /* Affected bank */ 993 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 994 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 995 /* Size of DDR */ 996 #define MC_CMD_FC_IN_DDR_SIZE_OFST 12 997 #define MC_CMD_FC_IN_DDR_SIZE_LEN 4 998 999 /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ 1000 #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 1001 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1002 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1003 /* MC_CMD_FC_IN_DDR_OP_OFST 4 */ 1004 /* MC_CMD_FC_IN_DDR_OP_LEN 4 */ 1005 /* Affected bank */ 1006 /* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ 1007 /* MC_CMD_FC_IN_DDR_BANK_LEN 4 */ 1008 1009 /* MC_CMD_FC_IN_TIMESTAMP msgrequest */ 1010 #define MC_CMD_FC_IN_TIMESTAMP_LEN 8 1011 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1012 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1013 /* FC timestamp operation code */ 1014 #define MC_CMD_FC_IN_TIMESTAMP_OP_OFST 4 1015 #define MC_CMD_FC_IN_TIMESTAMP_OP_LEN 4 1016 /* enum: Read transmit timestamp(s) */ 1017 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT 0x0 1018 /* enum: Read snapshot timestamps */ 1019 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT 0x1 1020 /* enum: Clear all transmit timestamps */ 1021 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT 0x2 1022 1023 /* MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT msgrequest */ 1024 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LEN 28 1025 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1026 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1027 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_OFST 4 1028 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_OP_LEN 4 1029 /* Control filtering of the returned timestamp and sequence number specified 1030 * here 1031 */ 1032 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_OFST 8 1033 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_FILTER_LEN 4 1034 /* enum: Return most recent timestamp. No filtering */ 1035 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_LATEST 0x0 1036 /* enum: Match timestamp against the PTP clock ID, port number and sequence 1037 * number specified 1038 */ 1039 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_MATCH 0x1 1040 /* Clock identity of PTP packet for which timestamp required */ 1041 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_OFST 12 1042 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LEN 8 1043 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_OFST 12 1044 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_LEN 4 1045 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_LBN 96 1046 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_LO_WIDTH 32 1047 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_OFST 16 1048 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_LEN 4 1049 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_LBN 128 1050 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_CLOCK_ID_HI_WIDTH 32 1051 /* Port number of PTP packet for which timestamp required */ 1052 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_OFST 20 1053 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_PORT_NUM_LEN 4 1054 /* Sequence number of PTP packet for which timestamp required */ 1055 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_OFST 24 1056 #define MC_CMD_FC_IN_TIMESTAMP_READ_TRANSMIT_SEQ_NUM_LEN 4 1057 1058 /* MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT msgrequest */ 1059 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_LEN 8 1060 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1061 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1062 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_OFST 4 1063 #define MC_CMD_FC_IN_TIMESTAMP_READ_SNAPSHOT_OP_LEN 4 1064 1065 /* MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT msgrequest */ 1066 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_LEN 8 1067 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1068 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1069 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_OFST 4 1070 #define MC_CMD_FC_IN_TIMESTAMP_CLEAR_TRANSMIT_OP_LEN 4 1071 1072 /* MC_CMD_FC_IN_SPI msgrequest */ 1073 #define MC_CMD_FC_IN_SPI_LEN 8 1074 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1075 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1076 /* Basic commands for SPI Flash. */ 1077 #define MC_CMD_FC_IN_SPI_OP_OFST 4 1078 #define MC_CMD_FC_IN_SPI_OP_LEN 4 1079 /* enum: SPI Flash read */ 1080 #define MC_CMD_FC_IN_SPI_READ 0x0 1081 /* enum: SPI Flash write */ 1082 #define MC_CMD_FC_IN_SPI_WRITE 0x1 1083 /* enum: SPI Flash erase */ 1084 #define MC_CMD_FC_IN_SPI_ERASE 0x2 1085 1086 /* MC_CMD_FC_IN_SPI_READ msgrequest */ 1087 #define MC_CMD_FC_IN_SPI_READ_LEN 16 1088 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1089 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1090 #define MC_CMD_FC_IN_SPI_READ_OP_OFST 4 1091 #define MC_CMD_FC_IN_SPI_READ_OP_LEN 4 1092 #define MC_CMD_FC_IN_SPI_READ_ADDR_OFST 8 1093 #define MC_CMD_FC_IN_SPI_READ_ADDR_LEN 4 1094 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_OFST 12 1095 #define MC_CMD_FC_IN_SPI_READ_NUMBYTES_LEN 4 1096 1097 /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ 1098 #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 1099 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 1100 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX_MCDI2 1020 1101 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) 1102 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_NUM(len) (((len)-12)/4) 1103 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1104 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1105 #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 1106 #define MC_CMD_FC_IN_SPI_WRITE_OP_LEN 4 1107 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_OFST 8 1108 #define MC_CMD_FC_IN_SPI_WRITE_ADDR_LEN 4 1109 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_OFST 12 1110 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 1111 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 1112 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 1113 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM_MCDI2 252 1114 1115 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ 1116 #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 1117 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1118 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1119 #define MC_CMD_FC_IN_SPI_ERASE_OP_OFST 4 1120 #define MC_CMD_FC_IN_SPI_ERASE_OP_LEN 4 1121 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_OFST 8 1122 #define MC_CMD_FC_IN_SPI_ERASE_ADDR_LEN 4 1123 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_OFST 12 1124 #define MC_CMD_FC_IN_SPI_ERASE_NUMBYTES_LEN 4 1125 1126 /* MC_CMD_FC_IN_DIAG msgrequest */ 1127 #define MC_CMD_FC_IN_DIAG_LEN 8 1128 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1129 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1130 /* Operation code indicating component type */ 1131 #define MC_CMD_FC_IN_DIAG_OP_OFST 4 1132 #define MC_CMD_FC_IN_DIAG_OP_LEN 4 1133 /* enum: Power noise generator. */ 1134 #define MC_CMD_FC_IN_DIAG_POWER_NOISE 0x0 1135 /* enum: DDR soak test component. */ 1136 #define MC_CMD_FC_IN_DIAG_DDR_SOAK 0x1 1137 /* enum: Diagnostics datapath control component. */ 1138 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL 0x2 1139 1140 /* MC_CMD_FC_IN_DIAG_POWER_NOISE msgrequest */ 1141 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_LEN 12 1142 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1143 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1144 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_OFST 4 1145 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_OP_LEN 4 1146 /* Sub-opcode describing the operation to be carried out */ 1147 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_OFST 8 1148 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_SUB_OP_LEN 4 1149 /* enum: Read the configuration (the 32-bit values in each of the clock enable 1150 * count and toggle count registers) 1151 */ 1152 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG 0x0 1153 /* enum: Write a new configuration to the clock enable count and toggle count 1154 * registers 1155 */ 1156 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG 0x1 1157 1158 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG msgrequest */ 1159 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_LEN 12 1160 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1161 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1162 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_OFST 4 1163 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_OP_LEN 4 1164 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_OFST 8 1165 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_READ_CONFIG_SUB_OP_LEN 4 1166 1167 /* MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG msgrequest */ 1168 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 20 1169 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1170 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1171 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_OFST 4 1172 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_OP_LEN 4 1173 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_OFST 8 1174 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_SUB_OP_LEN 4 1175 /* The 32-bit value to be written to the toggle count register */ 1176 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_OFST 12 1177 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_TOGGLE_COUNT_LEN 4 1178 /* The 32-bit value to be written to the clock enable count register */ 1179 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_OFST 16 1180 #define MC_CMD_FC_IN_DIAG_POWER_NOISE_WRITE_CONFIG_CLKEN_COUNT_LEN 4 1181 1182 /* MC_CMD_FC_IN_DIAG_DDR_SOAK msgrequest */ 1183 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_LEN 12 1184 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1185 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1186 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_OFST 4 1187 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_OP_LEN 4 1188 /* Sub-opcode describing the operation to be carried out */ 1189 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_OFST 8 1190 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_SUB_OP_LEN 4 1191 /* enum: Starts DDR soak test on selected banks */ 1192 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START 0x0 1193 /* enum: Read status of DDR soak test */ 1194 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT 0x1 1195 /* enum: Stop test */ 1196 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP 0x2 1197 /* enum: Set or clear bit that triggers fake errors. These cause subsequent 1198 * tests to fail until the bit is cleared. 1199 */ 1200 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR 0x3 1201 1202 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_START msgrequest */ 1203 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_LEN 24 1204 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1205 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1206 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_OFST 4 1207 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_OP_LEN 4 1208 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_OFST 8 1209 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SUB_OP_LEN 4 1210 /* Mask of DDR banks to be tested */ 1211 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_OFST 12 1212 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_BANK_MASK_LEN 4 1213 /* Pattern to use in the soak test */ 1214 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_OFST 16 1215 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_PATTERN_LEN 4 1216 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ZEROS 0x0 /* enum */ 1217 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONES 0x1 /* enum */ 1218 /* Either multiple automatic tests until a STOP command is issued, or one 1219 * single test 1220 */ 1221 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_OFST 20 1222 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_TEST_TYPE_LEN 4 1223 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_ONGOING_TEST 0x0 /* enum */ 1224 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_START_SINGLE_TEST 0x1 /* enum */ 1225 1226 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT msgrequest */ 1227 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_LEN 16 1228 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1229 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1230 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_OFST 4 1231 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_OP_LEN 4 1232 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_OFST 8 1233 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_SUB_OP_LEN 4 1234 /* DDR bank to read status from */ 1235 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_OFST 12 1236 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_RESULT_BANK_ID_LEN 4 1237 #define MC_CMD_FC_DDR_BANK0 0x0 /* enum */ 1238 #define MC_CMD_FC_DDR_BANK1 0x1 /* enum */ 1239 #define MC_CMD_FC_DDR_BANK2 0x2 /* enum */ 1240 #define MC_CMD_FC_DDR_BANK3 0x3 /* enum */ 1241 #define MC_CMD_FC_DDR_AOEMEM_MAX_BANKS 0x4 /* enum */ 1242 1243 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP msgrequest */ 1244 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_LEN 16 1245 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1246 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1247 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_OFST 4 1248 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_OP_LEN 4 1249 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_OFST 8 1250 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_SUB_OP_LEN 4 1251 /* Mask of DDR banks to be tested */ 1252 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_OFST 12 1253 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_STOP_BANK_MASK_LEN 4 1254 1255 /* MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR msgrequest */ 1256 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_LEN 20 1257 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1258 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1259 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_OFST 4 1260 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_OP_LEN 4 1261 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_OFST 8 1262 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SUB_OP_LEN 4 1263 /* Mask of DDR banks to set/clear error flag on */ 1264 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_OFST 12 1265 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_BANK_MASK_LEN 4 1266 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_OFST 16 1267 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_FLAG_ACTION_LEN 4 1268 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_CLEAR 0x0 /* enum */ 1269 #define MC_CMD_FC_IN_DIAG_DDR_SOAK_ERROR_SET 0x1 /* enum */ 1270 1271 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL msgrequest */ 1272 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_LEN 12 1273 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1274 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1275 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_OFST 4 1276 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_OP_LEN 4 1277 /* Sub-opcode describing the operation to be carried out */ 1278 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_OFST 8 1279 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SUB_OP_LEN 4 1280 /* enum: Set a known datapath configuration */ 1281 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE 0x0 1282 /* enum: Apply raw config to datapath control registers */ 1283 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG 0x1 1284 1285 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE msgrequest */ 1286 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_LEN 16 1287 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1288 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1289 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_OFST 4 1290 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_OP_LEN 4 1291 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_OFST 8 1292 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SUB_OP_LEN 4 1293 /* Datapath configuration identifier */ 1294 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_OFST 12 1295 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_MODE_LEN 4 1296 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_PASSTHROUGH 0x0 /* enum */ 1297 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_SET_MODE_SNAKE 0x1 /* enum */ 1298 1299 /* MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG msgrequest */ 1300 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 24 1301 /* MC_CMD_FC_IN_CMD_OFST 0 */ 1302 /* MC_CMD_FC_IN_CMD_LEN 4 */ 1303 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_OFST 4 1304 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_OP_LEN 4 1305 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_OFST 8 1306 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_SUB_OP_LEN 4 1307 /* Value to write into control register 1 */ 1308 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_OFST 12 1309 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL1_LEN 4 1310 /* Value to write into control register 2 */ 1311 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_OFST 16 1312 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL2_LEN 4 1313 /* Value to write into control register 3 */ 1314 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_OFST 20 1315 #define MC_CMD_FC_IN_DIAG_DATAPATH_CTRL_RAW_CONFIG_CONTROL3_LEN 4 1316 1317 /* MC_CMD_FC_OUT msgresponse */ 1318 #define MC_CMD_FC_OUT_LEN 0 1319 1320 /* MC_CMD_FC_OUT_NULL msgresponse */ 1321 #define MC_CMD_FC_OUT_NULL_LEN 0 1322 1323 /* MC_CMD_FC_OUT_READ32 msgresponse */ 1324 #define MC_CMD_FC_OUT_READ32_LENMIN 4 1325 #define MC_CMD_FC_OUT_READ32_LENMAX 252 1326 #define MC_CMD_FC_OUT_READ32_LENMAX_MCDI2 1020 1327 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) 1328 #define MC_CMD_FC_OUT_READ32_BUFFER_NUM(len) (((len)-0)/4) 1329 #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 1330 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 1331 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 1332 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 1333 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM_MCDI2 255 1334 1335 /* MC_CMD_FC_OUT_WRITE32 msgresponse */ 1336 #define MC_CMD_FC_OUT_WRITE32_LEN 0 1337 1338 /* MC_CMD_FC_OUT_TRC_READ msgresponse */ 1339 #define MC_CMD_FC_OUT_TRC_READ_LEN 16 1340 #define MC_CMD_FC_OUT_TRC_READ_DATA_OFST 0 1341 #define MC_CMD_FC_OUT_TRC_READ_DATA_LEN 4 1342 #define MC_CMD_FC_OUT_TRC_READ_DATA_NUM 4 1343 1344 /* MC_CMD_FC_OUT_TRC_WRITE msgresponse */ 1345 #define MC_CMD_FC_OUT_TRC_WRITE_LEN 0 1346 1347 /* MC_CMD_FC_OUT_GET_VERSION msgresponse */ 1348 #define MC_CMD_FC_OUT_GET_VERSION_LEN 12 1349 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_OFST 0 1350 #define MC_CMD_FC_OUT_GET_VERSION_FIRMWARE_LEN 4 1351 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_OFST 4 1352 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LEN 8 1353 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_OFST 4 1354 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_LEN 4 1355 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_LBN 32 1356 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_LO_WIDTH 32 1357 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_OFST 8 1358 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_LEN 4 1359 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_LBN 64 1360 #define MC_CMD_FC_OUT_GET_VERSION_VERSION_HI_WIDTH 32 1361 1362 /* MC_CMD_FC_OUT_TRC_RX_READ msgresponse */ 1363 #define MC_CMD_FC_OUT_TRC_RX_READ_LEN 8 1364 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_OFST 0 1365 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_LEN 4 1366 #define MC_CMD_FC_OUT_TRC_RX_READ_DATA_NUM 2 1367 1368 /* MC_CMD_FC_OUT_TRC_RX_WRITE msgresponse */ 1369 #define MC_CMD_FC_OUT_TRC_RX_WRITE_LEN 0 1370 1371 /* MC_CMD_FC_OUT_MAC_RECONFIGURE msgresponse */ 1372 #define MC_CMD_FC_OUT_MAC_RECONFIGURE_LEN 0 1373 1374 /* MC_CMD_FC_OUT_MAC_SET_LINK msgresponse */ 1375 #define MC_CMD_FC_OUT_MAC_SET_LINK_LEN 0 1376 1377 /* MC_CMD_FC_OUT_MAC_READ_STATUS msgresponse */ 1378 #define MC_CMD_FC_OUT_MAC_READ_STATUS_LEN 4 1379 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_OFST 0 1380 #define MC_CMD_FC_OUT_MAC_READ_STATUS_STATUS_LEN 4 1381 1382 /* MC_CMD_FC_OUT_MAC_GET_RX_STATS msgresponse */ 1383 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_RX_NSTATS))+1))>>3) 1384 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_OFST 0 1385 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LEN 8 1386 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 1387 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_LEN 4 1388 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_LBN 0 1389 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_WIDTH 32 1390 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 1391 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_LEN 4 1392 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_LBN 32 1393 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_WIDTH 32 1394 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS 1395 #define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ 1396 #define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ 1397 #define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ 1398 #define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 1399 #define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ 1400 #define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ 1401 #define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ 1402 #define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ 1403 #define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ 1404 #define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ 1405 #define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ 1406 #define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ 1407 #define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ 1408 #define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 1409 #define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ 1410 #define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ 1411 #define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ 1412 #define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ 1413 #define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ 1414 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ 1415 #define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ 1416 #define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ 1417 #define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ 1418 #define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ 1419 #define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ 1420 /* enum: (Last entry) */ 1421 #define MC_CMD_FC_MAC_RX_NSTATS 0x19 1422 1423 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ 1424 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) 1425 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_OFST 0 1426 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LEN 8 1427 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 1428 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_LEN 4 1429 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_LBN 0 1430 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_WIDTH 32 1431 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 1432 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_LEN 4 1433 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_LBN 32 1434 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_WIDTH 32 1435 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS 1436 #define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ 1437 #define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ 1438 #define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ 1439 #define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ 1440 #define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ 1441 #define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ 1442 #define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ 1443 #define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ 1444 #define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ 1445 #define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ 1446 #define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ 1447 #define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ 1448 #define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ 1449 #define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ 1450 #define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ 1451 #define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ 1452 #define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ 1453 #define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ 1454 #define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ 1455 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ 1456 #define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ 1457 #define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ 1458 /* enum: (Last entry) */ 1459 #define MC_CMD_FC_MAC_TX_NSTATS 0x16 1460 1461 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ 1462 #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) 1463 /* MAC Statistics */ 1464 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_OFST 0 1465 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LEN 8 1466 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_OFST 0 1467 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_LEN 4 1468 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_LBN 0 1469 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_LO_WIDTH 32 1470 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_OFST 4 1471 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_LEN 4 1472 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_LBN 32 1473 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_HI_WIDTH 32 1474 #define MC_CMD_FC_OUT_MAC_GET_STATS_STATISTICS_NUM MC_CMD_FC_MAC_NSTATS_PER_BLOCK 1475 1476 /* MC_CMD_FC_OUT_MAC msgresponse */ 1477 #define MC_CMD_FC_OUT_MAC_LEN 0 1478 1479 /* MC_CMD_FC_OUT_SFP msgresponse */ 1480 #define MC_CMD_FC_OUT_SFP_LEN 0 1481 1482 /* MC_CMD_FC_OUT_DDR_TEST_START msgresponse */ 1483 #define MC_CMD_FC_OUT_DDR_TEST_START_LEN 0 1484 1485 /* MC_CMD_FC_OUT_DDR_TEST_POLL msgresponse */ 1486 #define MC_CMD_FC_OUT_DDR_TEST_POLL_LEN 8 1487 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_OFST 0 1488 #define MC_CMD_FC_OUT_DDR_TEST_POLL_STATUS_LEN 4 1489 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_OFST 0 1490 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_LBN 0 1491 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CODE_WIDTH 8 1492 /* enum: Test not yet initiated */ 1493 #define MC_CMD_FC_OP_DDR_TEST_NONE 0x0 1494 /* enum: Test is in progress */ 1495 #define MC_CMD_FC_OP_DDR_TEST_INPROGRESS 0x1 1496 /* enum: Timed completed */ 1497 #define MC_CMD_FC_OP_DDR_TEST_SUCCESS 0x2 1498 /* enum: Test did not complete in specified time */ 1499 #define MC_CMD_FC_OP_DDR_TEST_TIMER_EXPIRED 0x3 1500 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_OFST 0 1501 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_LBN 11 1502 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T0_WIDTH 1 1503 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_OFST 0 1504 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_LBN 10 1505 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_T1_WIDTH 1 1506 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_OFST 0 1507 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_LBN 9 1508 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B0_WIDTH 1 1509 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_OFST 0 1510 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_LBN 8 1511 #define MC_CMD_FC_OUT_DDR_TEST_POLL_PRESENT_B1_WIDTH 1 1512 /* Test result from FPGA */ 1513 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_OFST 4 1514 #define MC_CMD_FC_OUT_DDR_TEST_POLL_RESULT_LEN 4 1515 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_OFST 4 1516 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_LBN 31 1517 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T0_WIDTH 1 1518 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_OFST 4 1519 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_LBN 30 1520 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_T1_WIDTH 1 1521 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_OFST 4 1522 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_LBN 29 1523 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B0_WIDTH 1 1524 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_OFST 4 1525 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_LBN 28 1526 #define MC_CMD_FC_OUT_DDR_TEST_POLL_FPGA_SUPPORTS_B1_WIDTH 1 1527 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_OFST 4 1528 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_LBN 15 1529 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T0_WIDTH 5 1530 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_OFST 4 1531 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_LBN 10 1532 #define MC_CMD_FC_OUT_DDR_TEST_POLL_T1_WIDTH 5 1533 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_OFST 4 1534 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_LBN 5 1535 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B0_WIDTH 5 1536 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_OFST 4 1537 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_LBN 0 1538 #define MC_CMD_FC_OUT_DDR_TEST_POLL_B1_WIDTH 5 1539 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_COMPLETE 0x0 /* enum */ 1540 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_FAIL 0x1 /* enum */ 1541 #define MC_CMD_FC_OUT_DDR_TEST_POLL_TEST_PASS 0x2 /* enum */ 1542 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_FAIL 0x3 /* enum */ 1543 #define MC_CMD_FC_OUT_DDR_TEST_POLL_CAL_SUCCESS 0x4 /* enum */ 1544 1545 /* MC_CMD_FC_OUT_DDR_TEST msgresponse */ 1546 #define MC_CMD_FC_OUT_DDR_TEST_LEN 0 1547 1548 /* MC_CMD_FC_OUT_GET_ASSERT msgresponse */ 1549 #define MC_CMD_FC_OUT_GET_ASSERT_LEN 144 1550 /* Assertion status flag. */ 1551 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_OFST 0 1552 #define MC_CMD_FC_OUT_GET_ASSERT_GLOBAL_FLAGS_LEN 4 1553 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_OFST 0 1554 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_LBN 8 1555 #define MC_CMD_FC_OUT_GET_ASSERT_STATE_WIDTH 8 1556 /* enum: No crash data available */ 1557 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 1558 /* enum: New crash data available */ 1559 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 1560 /* enum: Crash data has been sent */ 1561 #define MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 1562 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_OFST 0 1563 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_LBN 0 1564 #define MC_CMD_FC_OUT_GET_ASSERT_TYPE_WIDTH 8 1565 /* enum: No crash has been recorded. */ 1566 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 1567 /* enum: Crash due to exception. */ 1568 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 1569 /* enum: Crash due to assertion. */ 1570 #define MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 1571 /* Failing PC value */ 1572 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_OFST 4 1573 #define MC_CMD_FC_OUT_GET_ASSERT_SAVED_PC_OFFS_LEN 4 1574 /* Saved GP regs */ 1575 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_OFST 8 1576 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_LEN 4 1577 #define MC_CMD_FC_OUT_GET_ASSERT_GP_REGS_OFFS_NUM 31 1578 /* Exception Type */ 1579 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_OFST 132 1580 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_TYPE_OFFS_LEN 4 1581 /* Instruction at which exception occurred */ 1582 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_OFST 136 1583 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_PC_ADDR_OFFS_LEN 4 1584 /* BAD Address that triggered address-based exception */ 1585 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_OFST 140 1586 #define MC_CMD_FC_OUT_GET_ASSERT_EXCEPTION_BAD_ADDR_OFFS_LEN 4 1587 1588 /* MC_CMD_FC_OUT_FPGA_BUILD msgresponse */ 1589 #define MC_CMD_FC_OUT_FPGA_BUILD_LEN 32 1590 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_OFST 0 1591 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_INFO_LEN 4 1592 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_OFST 0 1593 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_LBN 31 1594 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_APPLICATION_WIDTH 1 1595 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_OFST 0 1596 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_LBN 30 1597 #define MC_CMD_FC_OUT_FPGA_BUILD_IS_LICENSED_WIDTH 1 1598 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_OFST 0 1599 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_LBN 16 1600 #define MC_CMD_FC_OUT_FPGA_BUILD_COMPONENT_ID_WIDTH 14 1601 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_OFST 0 1602 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_LBN 12 1603 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MAJOR_WIDTH 4 1604 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_OFST 0 1605 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_LBN 4 1606 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_MINOR_WIDTH 8 1607 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_OFST 0 1608 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_LBN 0 1609 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_NUM_WIDTH 4 1610 /* Build timestamp (seconds since epoch) */ 1611 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_OFST 4 1612 #define MC_CMD_FC_OUT_FPGA_BUILD_TIMESTAMP_LEN 4 1613 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_OFST 8 1614 #define MC_CMD_FC_OUT_FPGA_BUILD_PARAMETERS_LEN 4 1615 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_OFST 8 1616 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_LBN 0 1617 #define MC_CMD_FC_OUT_FPGA_BUILD_FPGA_TYPE_WIDTH 8 1618 #define MC_CMD_FC_FPGA_TYPE_A7 0xa7 /* enum */ 1619 #define MC_CMD_FC_FPGA_TYPE_A5 0xa5 /* enum */ 1620 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_OFST 8 1621 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_LBN 8 1622 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED1_WIDTH 10 1623 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_OFST 8 1624 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_LBN 18 1625 #define MC_CMD_FC_OUT_FPGA_BUILD_PTP_ENABLED_WIDTH 1 1626 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_OFST 8 1627 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_LBN 19 1628 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM1_RLDRAM_DEF_WIDTH 1 1629 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_OFST 8 1630 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_LBN 20 1631 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM2_RLDRAM_DEF_WIDTH 1 1632 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_OFST 8 1633 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_LBN 21 1634 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM3_RLDRAM_DEF_WIDTH 1 1635 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_OFST 8 1636 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_LBN 22 1637 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM4_RLDRAM_DEF_WIDTH 1 1638 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_OFST 8 1639 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_LBN 23 1640 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T0_DDR3_DEF_WIDTH 1 1641 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_OFST 8 1642 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_LBN 24 1643 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_DDR3_DEF_WIDTH 1 1644 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_OFST 8 1645 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_LBN 25 1646 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B0_DDR3_DEF_WIDTH 1 1647 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_OFST 8 1648 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_LBN 26 1649 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_B1_DDR3_DEF_WIDTH 1 1650 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_OFST 8 1651 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_LBN 27 1652 #define MC_CMD_FC_OUT_FPGA_BUILD_DDR3_ECC_ENABLED_WIDTH 1 1653 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_OFST 8 1654 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_LBN 28 1655 #define MC_CMD_FC_OUT_FPGA_BUILD_SODIMM_T1_QDR_DEF_WIDTH 1 1656 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_OFST 8 1657 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_LBN 29 1658 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED2_WIDTH 2 1659 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_OFST 8 1660 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_LBN 31 1661 #define MC_CMD_FC_OUT_FPGA_BUILD_CRC_APPEND_WIDTH 1 1662 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_OFST 12 1663 #define MC_CMD_FC_OUT_FPGA_BUILD_IDENTIFIER_LEN 4 1664 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_OFST 12 1665 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_LBN 0 1666 #define MC_CMD_FC_OUT_FPGA_BUILD_CHANGESET_WIDTH 16 1667 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_OFST 12 1668 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_LBN 16 1669 #define MC_CMD_FC_OUT_FPGA_BUILD_BUILD_FLAG_WIDTH 1 1670 #define MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 /* enum */ 1671 #define MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 /* enum */ 1672 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_OFST 12 1673 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_LBN 17 1674 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED3_WIDTH 15 1675 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_OFST 16 1676 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_HI_LEN 4 1677 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_OFST 16 1678 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_LBN 0 1679 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MINOR_WIDTH 16 1680 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_OFST 16 1681 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_LBN 16 1682 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 1683 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_OFST 20 1684 #define MC_CMD_FC_OUT_FPGA_BUILD_VERSION_LO_LEN 4 1685 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_OFST 20 1686 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_LBN 0 1687 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_BUILD_WIDTH 16 1688 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_OFST 20 1689 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_LBN 16 1690 #define MC_CMD_FC_OUT_FPGA_BUILD_DEPLOYMENT_VERSION_MICRO_WIDTH 16 1691 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_OFST 16 1692 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LEN 8 1693 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_OFST 16 1694 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_LEN 4 1695 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_LBN 128 1696 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_LO_WIDTH 32 1697 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_OFST 20 1698 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_LEN 4 1699 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_LBN 160 1700 #define MC_CMD_FC_OUT_FPGA_BUILD_RESERVED4_HI_WIDTH 32 1701 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_OFST 24 1702 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_LO_LEN 4 1703 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_OFST 28 1704 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HI_LEN 4 1705 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_OFST 28 1706 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 1707 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 1708 1709 /* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ 1710 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 1711 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 1712 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_LEN 4 1713 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_OFST 0 1714 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 1715 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 1716 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_OFST 0 1717 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 1718 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 1719 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_OFST 0 1720 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 1721 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 1722 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_OFST 0 1723 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 1724 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 1725 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_OFST 0 1726 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 1727 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 1728 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_OFST 0 1729 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 1730 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 1731 /* Build timestamp (seconds since epoch) */ 1732 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 1733 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_LEN 4 1734 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 1735 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_LEN 4 1736 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_OFST 8 1737 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 1738 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 1739 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_OFST 8 1740 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 1741 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 1742 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_OFST 8 1743 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 1744 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 1745 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_OFST 8 1746 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 1747 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 1748 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_OFST 8 1749 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 1750 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 1751 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_OFST 8 1752 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 1753 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 1754 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_OFST 8 1755 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 1756 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 1757 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_OFST 8 1758 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 1759 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 1760 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_OFST 8 1761 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 1762 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 1763 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_OFST 8 1764 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 1765 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 1766 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_OFST 8 1767 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 1768 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 1769 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_OFST 8 1770 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 1771 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 1772 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_OFST 8 1773 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 1774 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 1775 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ 1776 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ 1777 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_OFST 8 1778 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 1779 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 1780 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ 1781 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ 1782 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_OFST 8 1783 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 1784 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 1785 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ 1786 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ 1787 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_OFST 8 1788 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 1789 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 1790 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_OFST 8 1791 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 1792 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 1793 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_OFST 8 1794 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 1795 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 1796 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_OFST 8 1797 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 1798 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 1799 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_OFST 8 1800 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 1801 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 1802 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_OFST 8 1803 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 1804 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 1805 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_OFST 8 1806 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 1807 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 1808 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_OFST 8 1809 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 1810 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 1811 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_OFST 8 1812 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 1813 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 1814 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_OFST 8 1815 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 1816 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 1817 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_OFST 8 1818 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 1819 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 1820 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_OFST 8 1821 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 1822 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 1823 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_OFST 8 1824 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 1825 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 1826 #define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ 1827 #define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ 1828 #define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ 1829 #define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ 1830 #define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ 1831 #define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ 1832 #define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ 1833 #define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ 1834 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 1835 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_LEN 4 1836 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_OFST 12 1837 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 1838 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 1839 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_OFST 12 1840 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 1841 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 1842 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 1843 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 1844 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 1845 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_LEN 4 1846 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_OFST 16 1847 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 1848 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 1849 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_OFST 16 1850 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 1851 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 1852 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 1853 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_LEN 4 1854 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_OFST 20 1855 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 1856 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 1857 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_OFST 20 1858 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 1859 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 1860 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 1861 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_LEN 4 1862 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 1863 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_LEN 4 1864 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_OFST 28 1865 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 1866 #define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 1867 1868 /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ 1869 #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 1870 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 1871 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_LEN 4 1872 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_OFST 0 1873 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_LBN 31 1874 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_APPLICATION_WIDTH 1 1875 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_OFST 0 1876 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_LBN 30 1877 #define MC_CMD_FC_OUT_FPGA_SERVICES_IS_LICENSED_WIDTH 1 1878 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_OFST 0 1879 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_LBN 16 1880 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_ID_WIDTH 14 1881 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_OFST 0 1882 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_LBN 12 1883 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MAJOR_WIDTH 4 1884 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_OFST 0 1885 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_LBN 4 1886 #define MC_CMD_FC_OUT_FPGA_SERVICES_VERSION_MINOR_WIDTH 8 1887 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_OFST 0 1888 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_LBN 0 1889 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_NUM_WIDTH 4 1890 /* Build timestamp (seconds since epoch) */ 1891 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_OFST 4 1892 #define MC_CMD_FC_OUT_FPGA_SERVICES_TIMESTAMP_LEN 4 1893 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_OFST 8 1894 #define MC_CMD_FC_OUT_FPGA_SERVICES_PARAMETERS_LEN 4 1895 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_OFST 8 1896 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_LBN 8 1897 #define MC_CMD_FC_OUT_FPGA_SERVICES_FC_FLASH_BOOTED_WIDTH 1 1898 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_OFST 8 1899 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_LBN 27 1900 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC0_DEF_WIDTH 1 1901 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_OFST 8 1902 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_LBN 28 1903 #define MC_CMD_FC_OUT_FPGA_SERVICES_NIC1_DEF_WIDTH 1 1904 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_OFST 8 1905 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_LBN 29 1906 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP0_DEF_WIDTH 1 1907 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_OFST 8 1908 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_LBN 30 1909 #define MC_CMD_FC_OUT_FPGA_SERVICES_SFP1_DEF_WIDTH 1 1910 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_OFST 8 1911 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_LBN 31 1912 #define MC_CMD_FC_OUT_FPGA_SERVICES_RESERVED_WIDTH 1 1913 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_OFST 12 1914 #define MC_CMD_FC_OUT_FPGA_SERVICES_IDENTIFIER_LEN 4 1915 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_OFST 12 1916 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_LBN 0 1917 #define MC_CMD_FC_OUT_FPGA_SERVICES_CHANGESET_WIDTH 16 1918 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_OFST 12 1919 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_LBN 16 1920 #define MC_CMD_FC_OUT_FPGA_SERVICES_BUILD_FLAG_WIDTH 1 1921 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_OFST 16 1922 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_LEN 4 1923 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_OFST 16 1924 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_LBN 0 1925 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_WIDTH_WIDTH 16 1926 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_OFST 16 1927 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_LBN 16 1928 #define MC_CMD_FC_OUT_FPGA_SERVICES_MEMORY_SIZE_COUNT_WIDTH 16 1929 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_OFST 20 1930 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_LEN 4 1931 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_OFST 20 1932 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_LBN 0 1933 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_WIDTH_WIDTH 16 1934 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_OFST 20 1935 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_LBN 16 1936 #define MC_CMD_FC_OUT_FPGA_SERVICES_INSTANCE_SIZE_COUNT_WIDTH 16 1937 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_OFST 24 1938 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_LO_LEN 4 1939 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_OFST 28 1940 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HI_LEN 4 1941 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_OFST 28 1942 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 1943 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 1944 1945 /* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ 1946 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 1947 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 1948 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_LEN 4 1949 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_OFST 0 1950 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 1951 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 1952 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_OFST 0 1953 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 1954 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 1955 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_OFST 0 1956 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 1957 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 1958 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_OFST 0 1959 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 1960 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 1961 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_OFST 0 1962 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 1963 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 1964 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_OFST 0 1965 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 1966 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 1967 /* Build timestamp (seconds since epoch) */ 1968 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 1969 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_LEN 4 1970 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 1971 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_LEN 4 1972 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_OFST 8 1973 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 1974 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 1975 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_OFST 8 1976 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 1977 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 1978 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 1979 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_LEN 4 1980 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_OFST 12 1981 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 1982 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 1983 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_OFST 12 1984 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 1985 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 1986 /* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ 1987 /* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ 1988 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 1989 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_LEN 4 1990 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 1991 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_LEN 4 1992 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_OFST 28 1993 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 1994 #define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 1995 1996 /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ 1997 #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 1998 /* Qsys system ID */ 1999 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_OFST 0 2000 #define MC_CMD_FC_OUT_BSP_VERSION_SYSID_LEN 4 2001 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_OFST 0 2002 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_LBN 12 2003 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MAJOR_WIDTH 4 2004 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_OFST 0 2005 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_LBN 4 2006 #define MC_CMD_FC_OUT_BSP_VERSION_VERSION_MINOR_WIDTH 8 2007 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_OFST 0 2008 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_LBN 0 2009 #define MC_CMD_FC_OUT_BSP_VERSION_BUILD_NUM_WIDTH 4 2010 2011 /* MC_CMD_FC_OUT_READ_MAP_COUNT msgresponse */ 2012 #define MC_CMD_FC_OUT_READ_MAP_COUNT_LEN 4 2013 /* Number of maps */ 2014 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_OFST 0 2015 #define MC_CMD_FC_OUT_READ_MAP_COUNT_NUM_MAPS_LEN 4 2016 2017 /* MC_CMD_FC_OUT_READ_MAP_INDEX msgresponse */ 2018 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN 164 2019 /* Index of the map */ 2020 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_OFST 0 2021 #define MC_CMD_FC_OUT_READ_MAP_INDEX_INDEX_LEN 4 2022 /* Options for the map */ 2023 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 2024 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_LEN 4 2025 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ 2026 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ 2027 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ 2028 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ 2029 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ 2030 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ 2031 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ 2032 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ 2033 #define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ 2034 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ 2035 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ 2036 /* Address of start of map */ 2037 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 2038 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 2039 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_OFST 8 2040 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_LEN 4 2041 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_LBN 64 2042 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LO_WIDTH 32 2043 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_OFST 12 2044 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_LEN 4 2045 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_LBN 96 2046 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_HI_WIDTH 32 2047 /* Length of address map */ 2048 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_OFST 16 2049 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LEN 8 2050 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_OFST 16 2051 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_LEN 4 2052 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_LBN 128 2053 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_LO_WIDTH 32 2054 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_OFST 20 2055 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_LEN 4 2056 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_LBN 160 2057 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LEN_HI_WIDTH 32 2058 /* Component information field */ 2059 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_OFST 24 2060 #define MC_CMD_FC_OUT_READ_MAP_INDEX_COMP_INFO_LEN 4 2061 /* License expiry data for map */ 2062 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_OFST 28 2063 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LEN 8 2064 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_OFST 28 2065 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_LEN 4 2066 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_LBN 224 2067 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_LO_WIDTH 32 2068 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_OFST 32 2069 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_LEN 4 2070 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_LBN 256 2071 #define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_DATE_HI_WIDTH 32 2072 /* Name of the component */ 2073 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_OFST 36 2074 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_LEN 1 2075 #define MC_CMD_FC_OUT_READ_MAP_INDEX_NAME_NUM 128 2076 2077 /* MC_CMD_FC_OUT_READ_MAP msgresponse */ 2078 #define MC_CMD_FC_OUT_READ_MAP_LEN 0 2079 2080 /* MC_CMD_FC_OUT_CAPABILITIES msgresponse */ 2081 #define MC_CMD_FC_OUT_CAPABILITIES_LEN 8 2082 /* Number of internal ports */ 2083 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_OFST 0 2084 #define MC_CMD_FC_OUT_CAPABILITIES_INTERNAL_LEN 4 2085 /* Number of external ports */ 2086 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_OFST 4 2087 #define MC_CMD_FC_OUT_CAPABILITIES_EXTERNAL_LEN 4 2088 2089 /* MC_CMD_FC_OUT_GLOBAL_FLAGS msgresponse */ 2090 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_LEN 4 2091 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_OFST 0 2092 #define MC_CMD_FC_OUT_GLOBAL_FLAGS_FLAGS_LEN 4 2093 2094 /* MC_CMD_FC_OUT_IO_REL msgresponse */ 2095 #define MC_CMD_FC_OUT_IO_REL_LEN 0 2096 2097 /* MC_CMD_FC_OUT_IO_REL_GET_ADDR msgresponse */ 2098 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_LEN 8 2099 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_OFST 0 2100 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_HI_LEN 4 2101 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_OFST 4 2102 #define MC_CMD_FC_OUT_IO_REL_GET_ADDR_ADDR_LO_LEN 4 2103 2104 /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ 2105 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 2106 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 2107 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX_MCDI2 1020 2108 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) 2109 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_NUM(len) (((len)-0)/4) 2110 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 2111 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 2112 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 2113 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 2114 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM_MCDI2 255 2115 2116 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ 2117 #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 2118 2119 /* MC_CMD_FC_OUT_UHLINK_PHY msgresponse */ 2120 #define MC_CMD_FC_OUT_UHLINK_PHY_LEN 48 2121 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_OFST 0 2122 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_0_LEN 4 2123 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_OFST 0 2124 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_LBN 0 2125 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_VOD_WIDTH 16 2126 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_OFST 0 2127 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_LBN 16 2128 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_1STPOSTTAP_WIDTH 16 2129 /* Transceiver Transmit settings */ 2130 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_OFST 4 2131 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_SETTINGS_1_LEN 4 2132 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_OFST 4 2133 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_LBN 0 2134 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_PRETAP_WIDTH 16 2135 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_OFST 4 2136 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_LBN 16 2137 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_TX_PREEMP_2NDPOSTTAP_WIDTH 16 2138 /* Transceiver Receive settings */ 2139 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_OFST 8 2140 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_SETTINGS_LEN 4 2141 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_OFST 8 2142 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_LBN 0 2143 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_DC_GAIN_WIDTH 16 2144 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_OFST 8 2145 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_LBN 16 2146 #define MC_CMD_FC_OUT_UHLINK_PHY_TRC_RX_EQ_CONTROL_WIDTH 16 2147 /* Rx eye opening */ 2148 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_OFST 12 2149 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_LEN 4 2150 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_OFST 12 2151 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_LBN 0 2152 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_WIDTH_WIDTH 16 2153 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_OFST 12 2154 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_LBN 16 2155 #define MC_CMD_FC_OUT_UHLINK_PHY_RX_EYE_HEIGHT_WIDTH 16 2156 /* PCS status word */ 2157 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_OFST 16 2158 #define MC_CMD_FC_OUT_UHLINK_PHY_PCS_STATUS_LEN 4 2159 /* Link status word */ 2160 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_OFST 20 2161 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WORD_LEN 4 2162 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_OFST 20 2163 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_LBN 0 2164 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_STATE_WIDTH 1 2165 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_OFST 20 2166 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_LBN 1 2167 #define MC_CMD_FC_OUT_UHLINK_PHY_LINK_CONFIGURED_WIDTH 1 2168 /* Current SFp parameters applied */ 2169 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_OFST 24 2170 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PARAMS_LEN 20 2171 /* Link speed is 100, 1000, 10000 */ 2172 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_OFST 24 2173 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_SPEED_LEN 4 2174 /* Length of copper cable - zero when not relevant */ 2175 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_OFST 28 2176 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_COPPER_LEN_LEN 4 2177 /* True if a dual speed SFP+ module */ 2178 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_OFST 32 2179 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_DUAL_SPEED_LEN 4 2180 /* True if an SFP Module is present (other fields valid when true) */ 2181 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_OFST 36 2182 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_PRESENT_LEN 4 2183 /* The type of the SFP+ Module */ 2184 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_OFST 40 2185 #define MC_CMD_FC_OUT_UHLINK_PHY_SFP_TYPE_LEN 4 2186 /* PHY config flags */ 2187 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_OFST 44 2188 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_LEN 4 2189 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_OFST 44 2190 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_LBN 0 2191 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_DFE_WIDTH 1 2192 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_OFST 44 2193 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_LBN 1 2194 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_AEQ_WIDTH 1 2195 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_OFST 44 2196 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_LBN 2 2197 #define MC_CMD_FC_OUT_UHLINK_PHY_PHY_CFG_RX_TUNING_WIDTH 1 2198 2199 /* MC_CMD_FC_OUT_UHLINK_MAC msgresponse */ 2200 #define MC_CMD_FC_OUT_UHLINK_MAC_LEN 20 2201 /* MAC configuration applied */ 2202 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_OFST 0 2203 #define MC_CMD_FC_OUT_UHLINK_MAC_CONFIG_LEN 4 2204 /* MTU size */ 2205 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_OFST 4 2206 #define MC_CMD_FC_OUT_UHLINK_MAC_MTU_LEN 4 2207 /* IF Mode status */ 2208 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_OFST 8 2209 #define MC_CMD_FC_OUT_UHLINK_MAC_IF_STATUS_LEN 4 2210 /* MAC address configured */ 2211 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_OFST 12 2212 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LEN 8 2213 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_OFST 12 2214 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_LEN 4 2215 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_LBN 96 2216 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_LO_WIDTH 32 2217 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_OFST 16 2218 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_LEN 4 2219 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_LBN 128 2220 #define MC_CMD_FC_OUT_UHLINK_MAC_ADDR_HI_WIDTH 32 2221 2222 /* MC_CMD_FC_OUT_UHLINK_RX_EYE msgresponse */ 2223 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_LEN ((((0-1+(32*MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK))+1))>>3) 2224 /* Rx Eye measurements */ 2225 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_OFST 0 2226 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_LEN 4 2227 #define MC_CMD_FC_OUT_UHLINK_RX_EYE_RX_EYE_NUM MC_CMD_FC_UHLINK_RX_EYE_PER_BLOCK 2228 2229 /* MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT msgresponse */ 2230 #define MC_CMD_FC_OUT_UHLINK_DUMP_RX_EYE_PLOT_LEN 0 2231 2232 /* MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT msgresponse */ 2233 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_LEN ((((32-1+(64*MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK))+1))>>3) 2234 /* Has the eye plot dump completed and data returned is valid? */ 2235 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_OFST 0 2236 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_VALID_LEN 4 2237 /* Rx Eye binary plot */ 2238 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_OFST 4 2239 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LEN 8 2240 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_OFST 4 2241 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_LEN 4 2242 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_LBN 32 2243 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_LO_WIDTH 32 2244 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_OFST 8 2245 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_LEN 4 2246 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_LBN 64 2247 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_HI_WIDTH 32 2248 #define MC_CMD_FC_OUT_UHLINK_READ_RX_EYE_PLOT_ROWS_NUM MC_CMD_FC_UHLINK_RX_EYE_PLOT_ROWS_PER_BLOCK 2249 2250 /* MC_CMD_FC_OUT_UHLINK_RX_TUNE msgresponse */ 2251 #define MC_CMD_FC_OUT_UHLINK_RX_TUNE_LEN 0 2252 2253 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET msgresponse */ 2254 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_SET_LEN 0 2255 2256 /* MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET msgresponse */ 2257 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_LEN 4 2258 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_OFST 0 2259 #define MC_CMD_FC_OUT_UHLINK_LOOPBACK_GET_STATE_LEN 4 2260 2261 /* MC_CMD_FC_OUT_UHLINK msgresponse */ 2262 #define MC_CMD_FC_OUT_UHLINK_LEN 0 2263 2264 /* MC_CMD_FC_OUT_SET_LINK msgresponse */ 2265 #define MC_CMD_FC_OUT_SET_LINK_LEN 0 2266 2267 /* MC_CMD_FC_OUT_LICENSE msgresponse */ 2268 #define MC_CMD_FC_OUT_LICENSE_LEN 12 2269 /* Count of valid keys */ 2270 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_OFST 0 2271 #define MC_CMD_FC_OUT_LICENSE_VALID_KEYS_LEN 4 2272 /* Count of invalid keys */ 2273 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_OFST 4 2274 #define MC_CMD_FC_OUT_LICENSE_INVALID_KEYS_LEN 4 2275 /* Count of blacklisted keys */ 2276 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_OFST 8 2277 #define MC_CMD_FC_OUT_LICENSE_BLACKLISTED_KEYS_LEN 4 2278 2279 /* MC_CMD_FC_OUT_STARTUP msgresponse */ 2280 #define MC_CMD_FC_OUT_STARTUP_LEN 4 2281 /* Capabilities of the FPGA/FC */ 2282 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_OFST 0 2283 #define MC_CMD_FC_OUT_STARTUP_CAPABILITIES_LEN 4 2284 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_OFST 0 2285 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_LBN 0 2286 #define MC_CMD_FC_OUT_STARTUP_CAN_ACCESS_FLASH_WIDTH 1 2287 2288 /* MC_CMD_FC_OUT_DMA_READ msgresponse */ 2289 #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 2290 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 2291 #define MC_CMD_FC_OUT_DMA_READ_LENMAX_MCDI2 1020 2292 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) 2293 #define MC_CMD_FC_OUT_DMA_READ_DATA_NUM(len) (((len)-0)/1) 2294 /* The data read */ 2295 #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 2296 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 2297 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 2298 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 2299 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM_MCDI2 1020 2300 2301 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ 2302 #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 2303 /* Timer handle */ 2304 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_OFST 0 2305 #define MC_CMD_FC_OUT_TIMED_READ_SET_FC_HANDLE_LEN 4 2306 2307 /* MC_CMD_FC_OUT_TIMED_READ_GET msgresponse */ 2308 #define MC_CMD_FC_OUT_TIMED_READ_GET_LEN 52 2309 /* Host supplied handle (unique) */ 2310 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_OFST 0 2311 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_HANDLE_LEN 4 2312 /* Address into which to transfer data in host */ 2313 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_OFST 4 2314 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LEN 8 2315 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_OFST 4 2316 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_LEN 4 2317 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_LBN 32 2318 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_LO_WIDTH 32 2319 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_OFST 8 2320 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_LEN 4 2321 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_LBN 64 2322 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_DMA_ADDRESS_HI_WIDTH 32 2323 /* AOE address from which to transfer data */ 2324 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_OFST 12 2325 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LEN 8 2326 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_OFST 12 2327 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_LEN 4 2328 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_LBN 96 2329 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_LO_WIDTH 32 2330 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_OFST 16 2331 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_LEN 4 2332 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_LBN 128 2333 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_ADDRESS_HI_WIDTH 32 2334 /* Length of AOE transfer (total) */ 2335 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_OFST 20 2336 #define MC_CMD_FC_OUT_TIMED_READ_GET_AOE_LENGTH_LEN 4 2337 /* Length of host transfer (total) */ 2338 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_OFST 24 2339 #define MC_CMD_FC_OUT_TIMED_READ_GET_HOST_LENGTH_LEN 4 2340 /* See FLAGS entry for MC_CMD_FC_IN_TIMED_READ_SET */ 2341 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_OFST 28 2342 #define MC_CMD_FC_OUT_TIMED_READ_GET_FLAGS_LEN 4 2343 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_OFST 32 2344 #define MC_CMD_FC_OUT_TIMED_READ_GET_PERIOD_LEN 4 2345 /* When active, start read time */ 2346 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_OFST 36 2347 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LEN 8 2348 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_OFST 36 2349 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_LEN 4 2350 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_LBN 288 2351 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_LO_WIDTH 32 2352 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_OFST 40 2353 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_LEN 4 2354 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_LBN 320 2355 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_START_HI_WIDTH 32 2356 /* When active, end read time */ 2357 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_OFST 44 2358 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LEN 8 2359 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_OFST 44 2360 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_LEN 4 2361 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_LBN 352 2362 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_LO_WIDTH 32 2363 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_OFST 48 2364 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_LEN 4 2365 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_LBN 384 2366 #define MC_CMD_FC_OUT_TIMED_READ_GET_CLOCK_END_HI_WIDTH 32 2367 2368 /* MC_CMD_FC_OUT_LOG_ADDR_RANGE msgresponse */ 2369 #define MC_CMD_FC_OUT_LOG_ADDR_RANGE_LEN 0 2370 2371 /* MC_CMD_FC_OUT_LOG msgresponse */ 2372 #define MC_CMD_FC_OUT_LOG_LEN 0 2373 2374 /* MC_CMD_FC_OUT_CLOCK_GET_TIME msgresponse */ 2375 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_LEN 24 2376 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_OFST 0 2377 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_CLOCK_ID_LEN 4 2378 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_OFST 4 2379 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LEN 8 2380 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_OFST 4 2381 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_LEN 4 2382 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_LBN 32 2383 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_LO_WIDTH 32 2384 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_OFST 8 2385 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_LEN 4 2386 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_LBN 64 2387 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_SECONDS_HI_WIDTH 32 2388 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_OFST 12 2389 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_NANOSECONDS_LEN 4 2390 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_OFST 16 2391 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_RANGE_LEN 4 2392 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_OFST 20 2393 #define MC_CMD_FC_OUT_CLOCK_GET_TIME_PRECISION_LEN 4 2394 2395 /* MC_CMD_FC_OUT_CLOCK_SET_TIME msgresponse */ 2396 #define MC_CMD_FC_OUT_CLOCK_SET_TIME_LEN 0 2397 2398 /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ 2399 #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 2400 2401 /* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ 2402 #define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 2403 2404 /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ 2405 #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 2406 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 2407 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_LEN 4 2408 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_OFST 0 2409 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_LBN 0 2410 #define MC_CMD_FC_OUT_DDR_GET_STATUS_READY_WIDTH 1 2411 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_OFST 0 2412 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_LBN 1 2413 #define MC_CMD_FC_OUT_DDR_GET_STATUS_CALIBRATED_WIDTH 1 2414 2415 /* MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT msgresponse */ 2416 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_LEN 8 2417 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_OFST 0 2418 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_SECONDS_LEN 4 2419 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_OFST 4 2420 #define MC_CMD_FC_OUT_TIMESTAMP_READ_TRANSMIT_NANOSECONDS_LEN 4 2421 2422 /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ 2423 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 2424 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 2425 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX_MCDI2 1016 2426 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) 2427 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_NUM(len) (((len)-0)/8) 2428 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 2429 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_LEN 4 2430 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 2431 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_LEN 4 2432 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_OFST 0 2433 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LEN 8 2434 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_OFST 0 2435 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_LEN 4 2436 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_LBN 0 2437 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_LO_WIDTH 32 2438 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 2439 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_LEN 4 2440 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_LBN 32 2441 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_WIDTH 32 2442 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 2443 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 2444 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM_MCDI2 127 2445 2446 /* MC_CMD_FC_OUT_SPI_READ msgresponse */ 2447 #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 2448 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 2449 #define MC_CMD_FC_OUT_SPI_READ_LENMAX_MCDI2 1020 2450 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) 2451 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_NUM(len) (((len)-0)/4) 2452 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 2453 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 2454 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 2455 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 2456 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM_MCDI2 255 2457 2458 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ 2459 #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 2460 2461 /* MC_CMD_FC_OUT_SPI_ERASE msgresponse */ 2462 #define MC_CMD_FC_OUT_SPI_ERASE_LEN 0 2463 2464 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG msgresponse */ 2465 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_LEN 8 2466 /* The 32-bit value read from the toggle count register */ 2467 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_OFST 0 2468 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_TOGGLE_COUNT_LEN 4 2469 /* The 32-bit value read from the clock enable count register */ 2470 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_OFST 4 2471 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_READ_CONFIG_CLKEN_COUNT_LEN 4 2472 2473 /* MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG msgresponse */ 2474 #define MC_CMD_FC_OUT_DIAG_POWER_NOISE_WRITE_CONFIG_LEN 0 2475 2476 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_START msgresponse */ 2477 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_START_LEN 0 2478 2479 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT msgresponse */ 2480 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_LEN 8 2481 /* DDR soak test status word; bits [4:0] are relevant. */ 2482 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_OFST 0 2483 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_STATUS_LEN 4 2484 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_OFST 0 2485 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_LBN 0 2486 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PASSED_WIDTH 1 2487 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_OFST 0 2488 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_LBN 1 2489 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_FAILED_WIDTH 1 2490 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_OFST 0 2491 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_LBN 2 2492 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_COMPLETED_WIDTH 1 2493 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_OFST 0 2494 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_LBN 3 2495 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_TIMEOUT_WIDTH 1 2496 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_OFST 0 2497 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_LBN 4 2498 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_PNF_WIDTH 1 2499 /* DDR soak test error count */ 2500 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_OFST 4 2501 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_RESULT_ERR_COUNT_LEN 4 2502 2503 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP msgresponse */ 2504 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_STOP_LEN 0 2505 2506 /* MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR msgresponse */ 2507 #define MC_CMD_FC_OUT_DIAG_DDR_SOAK_ERROR_LEN 0 2508 2509 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE msgresponse */ 2510 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_SET_MODE_LEN 0 2511 2512 /* MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG msgresponse */ 2513 #define MC_CMD_FC_OUT_DIAG_DATAPATH_CTRL_RAW_CONFIG_LEN 0 2514 2515 2516 /***********************************/ 2517 /* MC_CMD_AOE 2518 * AOE operations on MC 2519 */ 2520 #define MC_CMD_AOE 0xa 2521 #define MC_CMD_AOE_MSGSET 0xa 2522 2523 /* MC_CMD_AOE_IN msgrequest */ 2524 #define MC_CMD_AOE_IN_LEN 4 2525 #define MC_CMD_AOE_IN_OP_HDR_OFST 0 2526 #define MC_CMD_AOE_IN_OP_HDR_LEN 4 2527 #define MC_CMD_AOE_IN_OP_OFST 0 2528 #define MC_CMD_AOE_IN_OP_LBN 0 2529 #define MC_CMD_AOE_IN_OP_WIDTH 8 2530 /* enum: FPGA and CPLD information */ 2531 #define MC_CMD_AOE_OP_INFO 0x1 2532 /* enum: Currents and voltages read from MCP3424s; DEBUG */ 2533 #define MC_CMD_AOE_OP_CURRENTS 0x2 2534 /* enum: Temperatures at locations around the PCB; DEBUG */ 2535 #define MC_CMD_AOE_OP_TEMPERATURES 0x3 2536 /* enum: Set CPLD to idle */ 2537 #define MC_CMD_AOE_OP_CPLD_IDLE 0x4 2538 /* enum: Read from CPLD register */ 2539 #define MC_CMD_AOE_OP_CPLD_READ 0x5 2540 /* enum: Write to CPLD register */ 2541 #define MC_CMD_AOE_OP_CPLD_WRITE 0x6 2542 /* enum: Execute CPLD instruction */ 2543 #define MC_CMD_AOE_OP_CPLD_INSTRUCTION 0x7 2544 /* enum: Reprogram the CPLD on the AOE device */ 2545 #define MC_CMD_AOE_OP_CPLD_REPROGRAM 0x8 2546 /* enum: AOE power control */ 2547 #define MC_CMD_AOE_OP_POWER 0x9 2548 /* enum: AOE image loading */ 2549 #define MC_CMD_AOE_OP_LOAD 0xa 2550 /* enum: Fan monitoring */ 2551 #define MC_CMD_AOE_OP_FAN_CONTROL 0xb 2552 /* enum: Fan failures since last reset */ 2553 #define MC_CMD_AOE_OP_FAN_FAILURES 0xc 2554 /* enum: Get generic AOE MAC statistics */ 2555 #define MC_CMD_AOE_OP_MAC_STATS 0xd 2556 /* enum: Retrieve PHY specific information */ 2557 #define MC_CMD_AOE_OP_GET_PHY_MEDIA_INFO 0xe 2558 /* enum: Write a number of JTAG primitive commands, return will give data */ 2559 #define MC_CMD_AOE_OP_JTAG_WRITE 0xf 2560 /* enum: Control access to the FPGA via the Siena JTAG Chain */ 2561 #define MC_CMD_AOE_OP_FPGA_ACCESS 0x10 2562 /* enum: Set the MTU offset between Siena and AOE MACs */ 2563 #define MC_CMD_AOE_OP_SET_MTU_OFFSET 0x11 2564 /* enum: How link state is handled */ 2565 #define MC_CMD_AOE_OP_LINK_STATE 0x12 2566 /* enum: How Siena MAC statistics are reported (deprecated - use 2567 * MC_CMD_AOE_OP_ASIC_STATS) 2568 */ 2569 #define MC_CMD_AOE_OP_SIENA_STATS 0x13 2570 /* enum: How native ASIC MAC statistics are reported - replaces the deprecated 2571 * command MC_CMD_AOE_OP_SIENA_STATS 2572 */ 2573 #define MC_CMD_AOE_OP_ASIC_STATS 0x13 2574 /* enum: DDR memory information */ 2575 #define MC_CMD_AOE_OP_DDR 0x14 2576 /* enum: FC control */ 2577 #define MC_CMD_AOE_OP_FC 0x15 2578 /* enum: DDR ECC status reads */ 2579 #define MC_CMD_AOE_OP_DDR_ECC_STATUS 0x16 2580 /* enum: Commands for MC-SPI Master emulation */ 2581 #define MC_CMD_AOE_OP_MC_SPI_MASTER 0x17 2582 /* enum: Commands for FC boot control */ 2583 #define MC_CMD_AOE_OP_FC_BOOT 0x18 2584 /* enum: Get number of internal ports */ 2585 #define MC_CMD_AOE_OP_GET_ASIC_PORTS 0x19 2586 /* enum: Get FC assert information and register dump */ 2587 #define MC_CMD_AOE_OP_GET_FC_ASSERT_INFO 0x1a 2588 /* enum: Set MUM startup FUSE byte with extended delay */ 2589 #define MC_CMD_AOE_OP_MUM_STARTUP_FUSE 0x1b 2590 2591 /* MC_CMD_AOE_OUT msgresponse */ 2592 #define MC_CMD_AOE_OUT_LEN 0 2593 2594 /* MC_CMD_AOE_IN_INFO msgrequest */ 2595 #define MC_CMD_AOE_IN_INFO_LEN 4 2596 #define MC_CMD_AOE_IN_CMD_OFST 0 2597 #define MC_CMD_AOE_IN_CMD_LEN 4 2598 2599 /* MC_CMD_AOE_IN_CURRENTS msgrequest */ 2600 #define MC_CMD_AOE_IN_CURRENTS_LEN 4 2601 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2602 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2603 2604 /* MC_CMD_AOE_IN_TEMPERATURES msgrequest */ 2605 #define MC_CMD_AOE_IN_TEMPERATURES_LEN 4 2606 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2607 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2608 2609 /* MC_CMD_AOE_IN_CPLD_IDLE msgrequest */ 2610 #define MC_CMD_AOE_IN_CPLD_IDLE_LEN 4 2611 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2612 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2613 2614 /* MC_CMD_AOE_IN_CPLD_READ msgrequest */ 2615 #define MC_CMD_AOE_IN_CPLD_READ_LEN 12 2616 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2617 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2618 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_OFST 4 2619 #define MC_CMD_AOE_IN_CPLD_READ_REGISTER_LEN 4 2620 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_OFST 8 2621 #define MC_CMD_AOE_IN_CPLD_READ_WIDTH_LEN 4 2622 2623 /* MC_CMD_AOE_IN_CPLD_WRITE msgrequest */ 2624 #define MC_CMD_AOE_IN_CPLD_WRITE_LEN 16 2625 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2626 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2627 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_OFST 4 2628 #define MC_CMD_AOE_IN_CPLD_WRITE_REGISTER_LEN 4 2629 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_OFST 8 2630 #define MC_CMD_AOE_IN_CPLD_WRITE_WIDTH_LEN 4 2631 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_OFST 12 2632 #define MC_CMD_AOE_IN_CPLD_WRITE_VALUE_LEN 4 2633 2634 /* MC_CMD_AOE_IN_CPLD_INSTRUCTION msgrequest */ 2635 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_LEN 8 2636 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2637 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2638 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_OFST 4 2639 #define MC_CMD_AOE_IN_CPLD_INSTRUCTION_INSTRUCTION_LEN 4 2640 2641 /* MC_CMD_AOE_IN_CPLD_REPROGRAM msgrequest */ 2642 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_LEN 8 2643 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2644 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2645 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_OFST 4 2646 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_OP_LEN 4 2647 /* enum: Reprogram CPLD, poll for completion */ 2648 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM 0x1 2649 /* enum: Reprogram CPLD, send event on completion */ 2650 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_REPROGRAM_EVENT 0x3 2651 /* enum: Get status of reprogramming operation */ 2652 #define MC_CMD_AOE_IN_CPLD_REPROGRAM_STATUS 0x4 2653 2654 /* MC_CMD_AOE_IN_POWER msgrequest */ 2655 #define MC_CMD_AOE_IN_POWER_LEN 8 2656 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2657 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2658 /* Turn on or off AOE power */ 2659 #define MC_CMD_AOE_IN_POWER_OP_OFST 4 2660 #define MC_CMD_AOE_IN_POWER_OP_LEN 4 2661 /* enum: Turn off FPGA power */ 2662 #define MC_CMD_AOE_IN_POWER_OFF 0x0 2663 /* enum: Turn on FPGA power */ 2664 #define MC_CMD_AOE_IN_POWER_ON 0x1 2665 /* enum: Clear peak power measurement */ 2666 #define MC_CMD_AOE_IN_POWER_CLEAR 0x2 2667 /* enum: Show current power in sensors output */ 2668 #define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 2669 /* enum: Show peak power in sensors output */ 2670 #define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 2671 /* enum: Show current DDR current */ 2672 #define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 2673 /* enum: Show peak DDR current */ 2674 #define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 2675 /* enum: Clear peak DDR current */ 2676 #define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 2677 2678 /* MC_CMD_AOE_IN_LOAD msgrequest */ 2679 #define MC_CMD_AOE_IN_LOAD_LEN 8 2680 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2681 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2682 /* Image to be loaded (0 - main or 1 - diagnostic) to load in normal sequence 2683 */ 2684 #define MC_CMD_AOE_IN_LOAD_IMAGE_OFST 4 2685 #define MC_CMD_AOE_IN_LOAD_IMAGE_LEN 4 2686 2687 /* MC_CMD_AOE_IN_FAN_CONTROL msgrequest */ 2688 #define MC_CMD_AOE_IN_FAN_CONTROL_LEN 8 2689 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2690 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2691 /* If non zero report measured fan RPM rather than nominal */ 2692 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_OFST 4 2693 #define MC_CMD_AOE_IN_FAN_CONTROL_REAL_RPM_LEN 4 2694 2695 /* MC_CMD_AOE_IN_FAN_FAILURES msgrequest */ 2696 #define MC_CMD_AOE_IN_FAN_FAILURES_LEN 4 2697 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2698 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2699 2700 /* MC_CMD_AOE_IN_MAC_STATS msgrequest */ 2701 #define MC_CMD_AOE_IN_MAC_STATS_LEN 24 2702 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2703 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2704 /* AOE port */ 2705 #define MC_CMD_AOE_IN_MAC_STATS_PORT_OFST 4 2706 #define MC_CMD_AOE_IN_MAC_STATS_PORT_LEN 4 2707 /* Host memory address for statistics */ 2708 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_OFST 8 2709 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LEN 8 2710 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_OFST 8 2711 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_LEN 4 2712 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_LBN 64 2713 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_LO_WIDTH 32 2714 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_OFST 12 2715 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_LEN 4 2716 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_LBN 96 2717 #define MC_CMD_AOE_IN_MAC_STATS_DMA_ADDR_HI_WIDTH 32 2718 #define MC_CMD_AOE_IN_MAC_STATS_CMD_OFST 16 2719 #define MC_CMD_AOE_IN_MAC_STATS_CMD_LEN 4 2720 #define MC_CMD_AOE_IN_MAC_STATS_DMA_OFST 16 2721 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LBN 0 2722 #define MC_CMD_AOE_IN_MAC_STATS_DMA_WIDTH 1 2723 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_OFST 16 2724 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_LBN 1 2725 #define MC_CMD_AOE_IN_MAC_STATS_CLEAR_WIDTH 1 2726 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_OFST 16 2727 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_LBN 2 2728 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CHANGE_WIDTH 1 2729 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_OFST 16 2730 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_LBN 3 2731 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_ENABLE_WIDTH 1 2732 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_OFST 16 2733 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_LBN 4 2734 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_CLEAR_WIDTH 1 2735 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_OFST 16 2736 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_LBN 5 2737 #define MC_CMD_AOE_IN_MAC_STATS_PERIODIC_NOEVENT_WIDTH 1 2738 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_OFST 16 2739 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_LBN 16 2740 #define MC_CMD_AOE_IN_MAC_STATS_PERIOD_MS_WIDTH 16 2741 /* Length of DMA data (optional) */ 2742 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_OFST 20 2743 #define MC_CMD_AOE_IN_MAC_STATS_DMA_LEN_LEN 4 2744 2745 /* MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO msgrequest */ 2746 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_LEN 12 2747 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2748 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2749 /* AOE port */ 2750 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_OFST 4 2751 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PORT_LEN 4 2752 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_OFST 8 2753 #define MC_CMD_AOE_IN_GET_PHY_MEDIA_INFO_PAGE_LEN 4 2754 2755 /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ 2756 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 2757 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 2758 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX_MCDI2 1020 2759 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) 2760 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_NUM(len) (((len)-8)/4) 2761 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2762 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2763 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 2764 #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_LEN 4 2765 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_OFST 8 2766 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 2767 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 2768 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 2769 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM_MCDI2 253 2770 2771 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ 2772 #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 2773 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2774 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2775 /* Enable or disable access */ 2776 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_OFST 4 2777 #define MC_CMD_AOE_IN_FPGA_ACCESS_OP_LEN 4 2778 /* enum: Enable access */ 2779 #define MC_CMD_AOE_IN_FPGA_ACCESS_ENABLE 0x1 2780 /* enum: Disable access */ 2781 #define MC_CMD_AOE_IN_FPGA_ACCESS_DISABLE 0x2 2782 2783 /* MC_CMD_AOE_IN_SET_MTU_OFFSET msgrequest */ 2784 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_LEN 12 2785 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2786 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2787 /* AOE port - when not ALL_EXTERNAL or ALL_INTERNAL specifies port number */ 2788 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_OFST 4 2789 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_PORT_LEN 4 2790 /* enum: Apply to all external ports */ 2791 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_EXTERNAL 0x8000 2792 /* enum: Apply to all internal ports */ 2793 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_ALL_INTERNAL 0x4000 2794 /* The MTU offset to be applied to the external ports */ 2795 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_OFST 8 2796 #define MC_CMD_AOE_IN_SET_MTU_OFFSET_OFFSET_LEN 4 2797 2798 /* MC_CMD_AOE_IN_LINK_STATE msgrequest */ 2799 #define MC_CMD_AOE_IN_LINK_STATE_LEN 8 2800 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2801 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2802 #define MC_CMD_AOE_IN_LINK_STATE_MODE_OFST 4 2803 #define MC_CMD_AOE_IN_LINK_STATE_MODE_LEN 4 2804 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_OFST 4 2805 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 2806 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 2807 /* enum: AOE and associated external port */ 2808 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 2809 /* enum: AOE and OR of all external ports */ 2810 #define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 2811 /* enum: Individual ports */ 2812 #define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 2813 /* enum: Configure link state mode on given AOE port */ 2814 #define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 2815 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_OFST 4 2816 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 2817 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 2818 /* enum: No-op */ 2819 #define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 2820 /* enum: logical OR of all SFP ports link status */ 2821 #define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 2822 /* enum: logical AND of all SFP ports link status */ 2823 #define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 2824 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_OFST 4 2825 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 2826 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 2827 2828 /* MC_CMD_AOE_IN_GET_ASIC_PORTS msgrequest */ 2829 #define MC_CMD_AOE_IN_GET_ASIC_PORTS_LEN 4 2830 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2831 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2832 2833 /* MC_CMD_AOE_IN_GET_FC_ASSERT_INFO msgrequest */ 2834 #define MC_CMD_AOE_IN_GET_FC_ASSERT_INFO_LEN 4 2835 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2836 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2837 2838 /* MC_CMD_AOE_IN_SIENA_STATS msgrequest */ 2839 #define MC_CMD_AOE_IN_SIENA_STATS_LEN 8 2840 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2841 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2842 /* How MAC statistics are reported */ 2843 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 2844 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_LEN 4 2845 /* enum: Statistics from Siena (default) */ 2846 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 2847 /* enum: Statistics from AOE external ports */ 2848 #define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 2849 2850 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ 2851 #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 2852 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2853 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2854 /* How MAC statistics are reported */ 2855 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 2856 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_LEN 4 2857 /* enum: Statistics from the ASIC (default) */ 2858 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 2859 /* enum: Statistics from AOE external ports */ 2860 #define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 2861 2862 /* MC_CMD_AOE_IN_DDR msgrequest */ 2863 #define MC_CMD_AOE_IN_DDR_LEN 12 2864 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2865 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2866 #define MC_CMD_AOE_IN_DDR_BANK_OFST 4 2867 #define MC_CMD_AOE_IN_DDR_BANK_LEN 4 2868 /* Enum values, see field(s): */ 2869 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 2870 /* Page index of SPD data */ 2871 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_OFST 8 2872 #define MC_CMD_AOE_IN_DDR_SPD_PAGE_ID_LEN 4 2873 2874 /* MC_CMD_AOE_IN_FC msgrequest */ 2875 #define MC_CMD_AOE_IN_FC_LEN 4 2876 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2877 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2878 2879 /* MC_CMD_AOE_IN_DDR_ECC_STATUS msgrequest */ 2880 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_LEN 8 2881 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2882 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2883 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_OFST 4 2884 #define MC_CMD_AOE_IN_DDR_ECC_STATUS_BANK_LEN 4 2885 /* Enum values, see field(s): */ 2886 /* MC_CMD_FC/MC_CMD_FC_IN_DDR/MC_CMD_FC_IN_DDR_BANK */ 2887 2888 /* MC_CMD_AOE_IN_MC_SPI_MASTER msgrequest */ 2889 #define MC_CMD_AOE_IN_MC_SPI_MASTER_LEN 8 2890 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2891 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2892 /* Basic commands for MC SPI Master emulation. */ 2893 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_OFST 4 2894 #define MC_CMD_AOE_IN_MC_SPI_MASTER_OP_LEN 4 2895 /* enum: MC SPI read */ 2896 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ 0x0 2897 /* enum: MC SPI write */ 2898 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE 0x1 2899 2900 /* MC_CMD_AOE_IN_MC_SPI_MASTER_READ msgrequest */ 2901 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_LEN 12 2902 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2903 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2904 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_OFST 4 2905 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OP_LEN 4 2906 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_OFST 8 2907 #define MC_CMD_AOE_IN_MC_SPI_MASTER_READ_OFFSET_LEN 4 2908 2909 /* MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE msgrequest */ 2910 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_LEN 16 2911 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2912 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2913 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_OFST 4 2914 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OP_LEN 4 2915 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_OFST 8 2916 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_OFFSET_LEN 4 2917 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_OFST 12 2918 #define MC_CMD_AOE_IN_MC_SPI_MASTER_WRITE_DATA_LEN 4 2919 2920 /* MC_CMD_AOE_IN_FC_BOOT msgrequest */ 2921 #define MC_CMD_AOE_IN_FC_BOOT_LEN 8 2922 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2923 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2924 /* FC boot control flags */ 2925 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_OFST 4 2926 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_LEN 4 2927 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_OFST 4 2928 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 2929 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 2930 2931 /* MC_CMD_AOE_IN_MUM_STARTUP_FUSE msgrequest: On AOE2, set MUM startup FUSE 2932 * byte with extended delay of 64ms. On some servers with noisy power rails, 2933 * this ensures that the MUM IO pins do not show spurious transitions while the 2934 * power rails are stabilising. Note that this operation requires a hard- 2935 * powercycle to take effect. See bug76446. 2936 */ 2937 #define MC_CMD_AOE_IN_MUM_STARTUP_FUSE_LEN 4 2938 /* Must be MC_CMD_AOE_OP_MUM_STARTUP_FUSE */ 2939 /* MC_CMD_AOE_IN_CMD_OFST 0 */ 2940 /* MC_CMD_AOE_IN_CMD_LEN 4 */ 2941 2942 /* MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO msgresponse */ 2943 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_LEN 144 2944 /* Assertion status flag. */ 2945 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_OFST 0 2946 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GLOBAL_FLAGS_LEN 4 2947 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_OFST 0 2948 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_LBN 8 2949 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_STATE_WIDTH 8 2950 /* enum: No crash data available */ 2951 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_CLEAR 0x0 */ 2952 /* enum: New crash data available */ 2953 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NEW 0x1 */ 2954 /* enum: Crash data has been sent */ 2955 /* MC_CMD_FC_GET_ASSERT_FLAGS_STATE_NOTIFIED 0x2 */ 2956 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_OFST 0 2957 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_LBN 0 2958 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_TYPE_WIDTH 8 2959 /* enum: No crash has been recorded. */ 2960 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_NONE 0x0 */ 2961 /* enum: Crash due to exception. */ 2962 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_EXCEPTION 0x1 */ 2963 /* enum: Crash due to assertion. */ 2964 /* MC_CMD_FC_GET_ASSERT_FLAGS_TYPE_ASSERTION 0x2 */ 2965 /* Failing PC value */ 2966 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_OFST 4 2967 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_SAVED_PC_OFFS_LEN 4 2968 /* Saved GP regs */ 2969 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_OFST 8 2970 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_LEN 4 2971 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_GP_REGS_OFFS_NUM 31 2972 /* Exception Type */ 2973 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_OFST 132 2974 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_TYPE_OFFS_LEN 4 2975 /* Instruction at which exception occurred */ 2976 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_OFST 136 2977 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_PC_ADDR_OFFS_LEN 4 2978 /* BAD Address that triggered address-based exception */ 2979 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_OFST 140 2980 #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_EXCEPTION_BAD_ADDR_OFFS_LEN 4 2981 2982 /* MC_CMD_AOE_OUT_INFO msgresponse */ 2983 #define MC_CMD_AOE_OUT_INFO_LEN 44 2984 /* JTAG IDCODE of CPLD */ 2985 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_OFST 0 2986 #define MC_CMD_AOE_OUT_INFO_CPLD_IDCODE_LEN 4 2987 /* Version of CPLD */ 2988 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_OFST 4 2989 #define MC_CMD_AOE_OUT_INFO_CPLD_VERSION_LEN 4 2990 /* JTAG IDCODE of FPGA */ 2991 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_OFST 8 2992 #define MC_CMD_AOE_OUT_INFO_FPGA_IDCODE_LEN 4 2993 /* JTAG USERCODE of FPGA */ 2994 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 2995 #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_LEN 4 2996 /* FPGA type - read from CPLD straps */ 2997 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 2998 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_LEN 4 2999 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ 3000 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ 3001 /* FPGA state (debug) */ 3002 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 3003 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_LEN 4 3004 /* FPGA image - partition from which loaded */ 3005 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_OFST 24 3006 #define MC_CMD_AOE_OUT_INFO_FPGA_IMAGE_LEN 4 3007 /* FC state */ 3008 #define MC_CMD_AOE_OUT_INFO_FC_STATE_OFST 28 3009 #define MC_CMD_AOE_OUT_INFO_FC_STATE_LEN 4 3010 /* enum: Set if watchdog working */ 3011 #define MC_CMD_AOE_OUT_INFO_WATCHDOG 0x1 3012 /* enum: Set if MC-FC communications working */ 3013 #define MC_CMD_AOE_OUT_INFO_COMMS 0x2 3014 /* Random pieces of information */ 3015 #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 3016 #define MC_CMD_AOE_OUT_INFO_FLAGS_LEN 4 3017 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ 3018 #define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 3019 /* enum: CPLD apparently good */ 3020 #define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 3021 /* enum: FPGA working normally */ 3022 #define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 3023 /* enum: FPGA is powered */ 3024 #define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 3025 /* enum: Board has incompatible SODIMMs fitted */ 3026 #define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 3027 /* enum: Board has ByteBlaster connected */ 3028 #define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 3029 /* enum: FPGA Boot flash has an invalid header. */ 3030 #define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 3031 /* enum: FPGA Application flash is accessible. */ 3032 #define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 3033 /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ 3034 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 3035 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_LEN 4 3036 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ 3037 #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ 3038 #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ 3039 #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ 3040 #define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ 3041 /* Result of FC booting - not valid while a ByteBlaster is connected. */ 3042 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 3043 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_LEN 4 3044 /* enum: No error */ 3045 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_NO_ERROR 0x0 3046 /* enum: Bad address set in CPLD */ 3047 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_ADDRESS 0x1 3048 /* enum: Bad header */ 3049 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_MAGIC 0x2 3050 /* enum: Bad text section details */ 3051 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_TEXT 0x3 3052 /* enum: Bad checksum */ 3053 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_CHECKSUM 0x4 3054 /* enum: Bad BSP */ 3055 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_BAD_BSP 0x5 3056 /* enum: Flash mode is invalid */ 3057 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_FAIL_INVALID_FLASH_MODE 0x6 3058 /* enum: FC application loaded and execution attempted */ 3059 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_EXECUTE 0x80 3060 /* enum: FC application Started */ 3061 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_APP_STARTED 0x81 3062 /* enum: No bootrom in FPGA */ 3063 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_NO_BOOTROM 0xff 3064 3065 /* MC_CMD_AOE_OUT_CURRENTS msgresponse */ 3066 #define MC_CMD_AOE_OUT_CURRENTS_LEN 68 3067 /* Set of currents and voltages (mA or mV as appropriate) */ 3068 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_OFST 0 3069 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_LEN 4 3070 #define MC_CMD_AOE_OUT_CURRENTS_VALUES_NUM 17 3071 #define MC_CMD_AOE_OUT_CURRENTS_I_2V5 0x0 /* enum */ 3072 #define MC_CMD_AOE_OUT_CURRENTS_I_1V8 0x1 /* enum */ 3073 #define MC_CMD_AOE_OUT_CURRENTS_I_GXB 0x2 /* enum */ 3074 #define MC_CMD_AOE_OUT_CURRENTS_I_PGM 0x3 /* enum */ 3075 #define MC_CMD_AOE_OUT_CURRENTS_I_XCVR 0x4 /* enum */ 3076 #define MC_CMD_AOE_OUT_CURRENTS_I_1V5 0x5 /* enum */ 3077 #define MC_CMD_AOE_OUT_CURRENTS_V_3V3 0x6 /* enum */ 3078 #define MC_CMD_AOE_OUT_CURRENTS_V_1V5 0x7 /* enum */ 3079 #define MC_CMD_AOE_OUT_CURRENTS_I_IN 0x8 /* enum */ 3080 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT 0x9 /* enum */ 3081 #define MC_CMD_AOE_OUT_CURRENTS_V_IN 0xa /* enum */ 3082 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR1 0xb /* enum */ 3083 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR1 0xc /* enum */ 3084 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR2 0xd /* enum */ 3085 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR2 0xe /* enum */ 3086 #define MC_CMD_AOE_OUT_CURRENTS_I_OUT_DDR3 0xf /* enum */ 3087 #define MC_CMD_AOE_OUT_CURRENTS_V_OUT_DDR3 0x10 /* enum */ 3088 3089 /* MC_CMD_AOE_OUT_TEMPERATURES msgresponse */ 3090 #define MC_CMD_AOE_OUT_TEMPERATURES_LEN 40 3091 /* Set of temperatures */ 3092 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_OFST 0 3093 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_LEN 4 3094 #define MC_CMD_AOE_OUT_TEMPERATURES_VALUES_NUM 10 3095 /* enum: The first set of enum values are for Modena code. */ 3096 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_0 0x0 3097 #define MC_CMD_AOE_OUT_TEMPERATURES_MAIN_1 0x1 /* enum */ 3098 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_0 0x2 /* enum */ 3099 #define MC_CMD_AOE_OUT_TEMPERATURES_IND_1 0x3 /* enum */ 3100 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO1 0x4 /* enum */ 3101 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO2 0x5 /* enum */ 3102 #define MC_CMD_AOE_OUT_TEMPERATURES_VCCIO3 0x6 /* enum */ 3103 #define MC_CMD_AOE_OUT_TEMPERATURES_PSU 0x7 /* enum */ 3104 #define MC_CMD_AOE_OUT_TEMPERATURES_FPGA 0x8 /* enum */ 3105 #define MC_CMD_AOE_OUT_TEMPERATURES_SIENA 0x9 /* enum */ 3106 /* enum: The second set of enum values are for Sorrento code. */ 3107 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_0 0x0 3108 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_MAIN_1 0x1 /* enum */ 3109 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_0 0x2 /* enum */ 3110 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_IND_1 0x3 /* enum */ 3111 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_0 0x4 /* enum */ 3112 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_SODIMM_1 0x5 /* enum */ 3113 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_FPGA 0x6 /* enum */ 3114 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY0 0x7 /* enum */ 3115 #define MC_CMD_AOE_OUT_TEMPERATURES_SORRENTO_PHY1 0x8 /* enum */ 3116 3117 /* MC_CMD_AOE_OUT_CPLD_READ msgresponse */ 3118 #define MC_CMD_AOE_OUT_CPLD_READ_LEN 4 3119 /* The value read from the CPLD */ 3120 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_OFST 0 3121 #define MC_CMD_AOE_OUT_CPLD_READ_VALUE_LEN 4 3122 3123 /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ 3124 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 3125 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 3126 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX_MCDI2 1020 3127 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) 3128 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_NUM(len) (((len)-0)/4) 3129 /* Failure counts for each fan */ 3130 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 3131 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 3132 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 3133 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 3134 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM_MCDI2 255 3135 3136 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ 3137 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 3138 /* Results of status command (only) */ 3139 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_OFST 0 3140 #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_STATUS_LEN 4 3141 3142 /* MC_CMD_AOE_OUT_POWER_OFF msgresponse */ 3143 #define MC_CMD_AOE_OUT_POWER_OFF_LEN 0 3144 3145 /* MC_CMD_AOE_OUT_POWER_ON msgresponse */ 3146 #define MC_CMD_AOE_OUT_POWER_ON_LEN 0 3147 3148 /* MC_CMD_AOE_OUT_LOAD msgresponse */ 3149 #define MC_CMD_AOE_OUT_LOAD_LEN 0 3150 3151 /* MC_CMD_AOE_OUT_MAC_STATS_DMA msgresponse */ 3152 #define MC_CMD_AOE_OUT_MAC_STATS_DMA_LEN 0 3153 3154 /* MC_CMD_AOE_OUT_MAC_STATS_NO_DMA msgresponse: See MC_CMD_MAC_STATS_OUT_NO_DMA 3155 * for details 3156 */ 3157 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) 3158 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_OFST 0 3159 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LEN 8 3160 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_OFST 0 3161 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_LEN 4 3162 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_LBN 0 3163 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_LO_WIDTH 32 3164 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_OFST 4 3165 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_LEN 4 3166 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_LBN 32 3167 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_HI_WIDTH 32 3168 #define MC_CMD_AOE_OUT_MAC_STATS_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS 3169 3170 /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ 3171 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 3172 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 3173 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX_MCDI2 1020 3174 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) 3175 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1) 3176 /* in bytes */ 3177 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 3178 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_LEN 4 3179 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_OFST 4 3180 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 3181 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 3182 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 3183 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM_MCDI2 1016 3184 3185 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ 3186 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 3187 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 3188 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX_MCDI2 1020 3189 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) 3190 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_NUM(len) (((len)-8)/4) 3191 /* Used to align the in and out data blocks so the MC can re-use the cmd */ 3192 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 3193 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_LEN 4 3194 /* out bytes */ 3195 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_OFST 4 3196 #define MC_CMD_AOE_OUT_JTAG_WRITE_PAD_LEN 4 3197 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_OFST 8 3198 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 3199 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 3200 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 3201 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM_MCDI2 253 3202 3203 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ 3204 #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 3205 3206 /* MC_CMD_AOE_OUT_DDR msgresponse */ 3207 #define MC_CMD_AOE_OUT_DDR_LENMIN 17 3208 #define MC_CMD_AOE_OUT_DDR_LENMAX 252 3209 #define MC_CMD_AOE_OUT_DDR_LENMAX_MCDI2 1020 3210 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) 3211 #define MC_CMD_AOE_OUT_DDR_SPD_NUM(len) (((len)-16)/1) 3212 /* Information on the module. */ 3213 #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 3214 #define MC_CMD_AOE_OUT_DDR_FLAGS_LEN 4 3215 #define MC_CMD_AOE_OUT_DDR_PRESENT_OFST 0 3216 #define MC_CMD_AOE_OUT_DDR_PRESENT_LBN 0 3217 #define MC_CMD_AOE_OUT_DDR_PRESENT_WIDTH 1 3218 #define MC_CMD_AOE_OUT_DDR_POWERED_OFST 0 3219 #define MC_CMD_AOE_OUT_DDR_POWERED_LBN 1 3220 #define MC_CMD_AOE_OUT_DDR_POWERED_WIDTH 1 3221 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_OFST 0 3222 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_LBN 2 3223 #define MC_CMD_AOE_OUT_DDR_OPERATIONAL_WIDTH 1 3224 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_OFST 0 3225 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_LBN 3 3226 #define MC_CMD_AOE_OUT_DDR_NOT_REACHABLE_WIDTH 1 3227 /* Memory size, in MB. */ 3228 #define MC_CMD_AOE_OUT_DDR_CAPACITY_OFST 4 3229 #define MC_CMD_AOE_OUT_DDR_CAPACITY_LEN 4 3230 /* The memory type, as reported from SPD information */ 3231 #define MC_CMD_AOE_OUT_DDR_TYPE_OFST 8 3232 #define MC_CMD_AOE_OUT_DDR_TYPE_LEN 4 3233 /* Nominal voltage of the module (as applied) */ 3234 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_OFST 12 3235 #define MC_CMD_AOE_OUT_DDR_VOLTAGE_LEN 4 3236 /* SPD data read from the module */ 3237 #define MC_CMD_AOE_OUT_DDR_SPD_OFST 16 3238 #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 3239 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 3240 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 3241 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM_MCDI2 1004 3242 3243 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ 3244 #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 3245 3246 /* MC_CMD_AOE_OUT_LINK_STATE msgresponse */ 3247 #define MC_CMD_AOE_OUT_LINK_STATE_LEN 0 3248 3249 /* MC_CMD_AOE_OUT_SIENA_STATS msgresponse */ 3250 #define MC_CMD_AOE_OUT_SIENA_STATS_LEN 0 3251 3252 /* MC_CMD_AOE_OUT_ASIC_STATS msgresponse */ 3253 #define MC_CMD_AOE_OUT_ASIC_STATS_LEN 0 3254 3255 /* MC_CMD_AOE_OUT_FC msgresponse */ 3256 #define MC_CMD_AOE_OUT_FC_LEN 0 3257 3258 /* MC_CMD_AOE_OUT_GET_ASIC_PORTS msgresponse */ 3259 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_LEN 4 3260 /* get the number of internal ports */ 3261 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_OFST 0 3262 #define MC_CMD_AOE_OUT_GET_ASIC_PORTS_COUNT_PORTS_LEN 4 3263 3264 /* MC_CMD_AOE_OUT_DDR_ECC_STATUS msgresponse */ 3265 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_LEN 8 3266 /* Flags describing status info on the module. */ 3267 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_OFST 0 3268 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_FLAGS_LEN 4 3269 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_OFST 0 3270 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_LBN 0 3271 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_VALID_WIDTH 1 3272 /* DDR ECC status on the module. */ 3273 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_OFST 4 3274 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_STATUS_LEN 4 3275 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_OFST 4 3276 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_LBN 0 3277 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_WIDTH 1 3278 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_OFST 4 3279 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_LBN 1 3280 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_WIDTH 1 3281 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_OFST 4 3282 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_LBN 2 3283 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_WIDTH 1 3284 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_OFST 4 3285 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_LBN 8 3286 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_SBE_COUNT_WIDTH 8 3287 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_OFST 4 3288 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_LBN 16 3289 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_DBE_COUNT_WIDTH 8 3290 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_OFST 4 3291 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_LBN 24 3292 #define MC_CMD_AOE_OUT_DDR_ECC_STATUS_CORDROP_COUNT_WIDTH 8 3293 3294 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_READ msgresponse */ 3295 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_LEN 4 3296 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_OFST 0 3297 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_READ_DATA_LEN 4 3298 3299 /* MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE msgresponse */ 3300 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_WRITE_LEN 0 3301 3302 /* MC_CMD_AOE_OUT_MC_SPI_MASTER msgresponse */ 3303 #define MC_CMD_AOE_OUT_MC_SPI_MASTER_LEN 0 3304 3305 /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ 3306 #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 3307 3308 /* MC_CMD_AOE_OUT_MUM_STARTUP_FUSE msgresponse */ 3309 #define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_LEN 4 3310 /* Current value of startup FUSE byte (fusebyte#4) read back after the update 3311 * operation. 3312 */ 3313 #define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_READBACK_VALUE_OFST 0 3314 #define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_READBACK_VALUE_LEN 4 3315 3316 #endif /* _SIENA_MC_DRIVER_PCOL_AOE_H */ 3317