1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2018-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_EF100_REGS_H 8 #define _SYS_EFX_EF100_REGS_H 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /************************************************************************** 15 * NOTE: the line below marks the start of the autogenerated section 16 * EF100 registers and descriptors 17 * 18 ************************************************************************** 19 */ 20 21 /* 22 * HW_REV_ID_REG(32bit): 23 * Hardware revision info register 24 */ 25 26 #define ER_GZ_HW_REV_ID_REG_OFST 0x00000000 27 /* rhead=rhead_host_regs */ 28 #define ER_GZ_HW_REV_ID_REG_RESET 0x0 29 30 31 32 33 /* 34 * NIC_REV_ID(32bit): 35 * SoftNIC revision info register 36 */ 37 38 #define ER_GZ_NIC_REV_ID_OFST 0x00000004 39 /* rhead=rhead_host_regs */ 40 #define ER_GZ_NIC_REV_ID_RESET 0x0 41 42 43 44 45 /* 46 * NIC_MAGIC(32bit): 47 * Signature register that should contain a well-known value 48 */ 49 50 #define ER_GZ_NIC_MAGIC_OFST 0x00000008 51 /* rhead=rhead_host_regs */ 52 #define ER_GZ_NIC_MAGIC_RESET 0x0 53 54 55 #define ERF_GZ_NIC_MAGIC_LBN 0 56 #define ERF_GZ_NIC_MAGIC_WIDTH 32 57 #define EFE_GZ_NIC_MAGIC_EXPECTED 0xEF100FCB 58 59 60 /* 61 * MC_SFT_STATUS(32bit): 62 * MC soft status 63 */ 64 65 #define ER_GZ_MC_SFT_STATUS_OFST 0x00000010 66 /* rhead=rhead_host_regs */ 67 #define ER_GZ_MC_SFT_STATUS_STEP 4 68 #define ER_GZ_MC_SFT_STATUS_ROWS 2 69 #define ER_GZ_MC_SFT_STATUS_RESET 0x0 70 71 72 73 74 /* 75 * MC_DB_LWRD_REG(32bit): 76 * MC doorbell register, low word 77 */ 78 79 #define ER_GZ_MC_DB_LWRD_REG_OFST 0x00000020 80 /* rhead=rhead_host_regs */ 81 #define ER_GZ_MC_DB_LWRD_REG_RESET 0x0 82 83 84 85 86 /* 87 * MC_DB_HWRD_REG(32bit): 88 * MC doorbell register, high word 89 */ 90 91 #define ER_GZ_MC_DB_HWRD_REG_OFST 0x00000024 92 /* rhead=rhead_host_regs */ 93 #define ER_GZ_MC_DB_HWRD_REG_RESET 0x0 94 95 96 97 98 /* 99 * EVQ_INT_PRIME(32bit): 100 * Prime EVQ 101 */ 102 103 #define ER_GZ_EVQ_INT_PRIME_OFST 0x00000040 104 /* rhead=rhead_host_regs */ 105 #define ER_GZ_EVQ_INT_PRIME_RESET 0x0 106 107 108 #define ERF_GZ_IDX_LBN 16 109 #define ERF_GZ_IDX_WIDTH 16 110 #define ERF_GZ_EVQ_ID_LBN 0 111 #define ERF_GZ_EVQ_ID_WIDTH 16 112 113 114 /* 115 * INT_AGG_RING_PRIME(32bit): 116 * Prime interrupt aggregation ring. 117 */ 118 119 #define ER_GZ_INT_AGG_RING_PRIME_OFST 0x00000048 120 /* rhead=rhead_host_regs */ 121 #define ER_GZ_INT_AGG_RING_PRIME_RESET 0x0 122 123 124 /* defined as ERF_GZ_IDX_LBN 16; */ 125 /* defined as ERF_GZ_IDX_WIDTH 16 */ 126 #define ERF_GZ_RING_ID_LBN 0 127 #define ERF_GZ_RING_ID_WIDTH 16 128 129 130 /* 131 * EVQ_TMR(32bit): 132 * EVQ timer control 133 */ 134 135 #define ER_GZ_EVQ_TMR_OFST 0x00000104 136 /* rhead=rhead_host_regs */ 137 #define ER_GZ_EVQ_TMR_STEP 65536 138 #define ER_GZ_EVQ_TMR_ROWS 1024 139 #define ER_GZ_EVQ_TMR_RESET 0x0 140 141 142 143 144 /* 145 * EVQ_UNSOL_CREDIT_GRANT_SEQ(32bit): 146 * Grant credits for unsolicited events. 147 */ 148 149 #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_OFST 0x00000108 150 /* rhead=rhead_host_regs */ 151 #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_STEP 65536 152 #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_ROWS 1024 153 #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_RESET 0x0 154 155 156 157 158 /* 159 * EVQ_DESC_CREDIT_GRANT_SEQ(32bit): 160 * Grant credits for descriptor proxy events. 161 */ 162 163 #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_OFST 0x00000110 164 /* rhead=rhead_host_regs */ 165 #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_STEP 65536 166 #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_ROWS 1024 167 #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_RESET 0x0 168 169 170 171 172 /* 173 * RX_RING_DOORBELL(32bit): 174 * Ring Rx doorbell. 175 */ 176 177 #define ER_GZ_RX_RING_DOORBELL_OFST 0x00000180 178 /* rhead=rhead_host_regs */ 179 #define ER_GZ_RX_RING_DOORBELL_STEP 65536 180 #define ER_GZ_RX_RING_DOORBELL_ROWS 1024 181 #define ER_GZ_RX_RING_DOORBELL_RESET 0x0 182 183 184 #define ERF_GZ_RX_RING_PIDX_LBN 16 185 #define ERF_GZ_RX_RING_PIDX_WIDTH 16 186 187 188 /* 189 * TX_RING_DOORBELL(32bit): 190 * Ring Tx doorbell. 191 */ 192 193 #define ER_GZ_TX_RING_DOORBELL_OFST 0x00000200 194 /* rhead=rhead_host_regs */ 195 #define ER_GZ_TX_RING_DOORBELL_STEP 65536 196 #define ER_GZ_TX_RING_DOORBELL_ROWS 1024 197 #define ER_GZ_TX_RING_DOORBELL_RESET 0x0 198 199 200 #define ERF_GZ_TX_RING_PIDX_LBN 16 201 #define ERF_GZ_TX_RING_PIDX_WIDTH 16 202 203 204 /* 205 * TX_DESC_PUSH(128bit): 206 * Tx ring descriptor push. Reserved for future use. 207 */ 208 209 #define ER_GZ_TX_DESC_PUSH_OFST 0x00000210 210 /* rhead=rhead_host_regs */ 211 #define ER_GZ_TX_DESC_PUSH_STEP 65536 212 #define ER_GZ_TX_DESC_PUSH_ROWS 1024 213 #define ER_GZ_TX_DESC_PUSH_RESET 0x0 214 215 216 217 218 /* 219 * THE_TIME(64bit): 220 * NIC hardware time 221 */ 222 223 #define ER_GZ_THE_TIME_OFST 0x00000280 224 /* rhead=rhead_host_regs */ 225 #define ER_GZ_THE_TIME_STEP 65536 226 #define ER_GZ_THE_TIME_ROWS 1024 227 #define ER_GZ_THE_TIME_RESET 0x0 228 229 230 #define ERF_GZ_THE_TIME_SECS_LBN 32 231 #define ERF_GZ_THE_TIME_SECS_WIDTH 32 232 #define ERF_GZ_THE_TIME_NANOS_LBN 2 233 #define ERF_GZ_THE_TIME_NANOS_WIDTH 30 234 #define ERF_GZ_THE_TIME_CLOCK_IN_SYNC_LBN 1 235 #define ERF_GZ_THE_TIME_CLOCK_IN_SYNC_WIDTH 1 236 #define ERF_GZ_THE_TIME_CLOCK_IS_SET_LBN 0 237 #define ERF_GZ_THE_TIME_CLOCK_IS_SET_WIDTH 1 238 239 240 /* 241 * PARAMS_TLV_LEN(32bit): 242 * Size of design parameters area in bytes 243 */ 244 245 #define ER_GZ_PARAMS_TLV_LEN_OFST 0x00000c00 246 /* rhead=rhead_host_regs */ 247 #define ER_GZ_PARAMS_TLV_LEN_STEP 65536 248 #define ER_GZ_PARAMS_TLV_LEN_ROWS 1024 249 #define ER_GZ_PARAMS_TLV_LEN_RESET 0x0 250 251 252 253 254 /* 255 * PARAMS_TLV(8160bit): 256 * Design parameters 257 */ 258 259 #define ER_GZ_PARAMS_TLV_OFST 0x00000c04 260 /* rhead=rhead_host_regs */ 261 #define ER_GZ_PARAMS_TLV_STEP 65536 262 #define ER_GZ_PARAMS_TLV_ROWS 1024 263 #define ER_GZ_PARAMS_TLV_RESET 0x0 264 265 266 267 268 /* ES_EW_EMBEDDED_EVENT */ 269 #define ESF_GZ_EV_256_EVENT_DW0_LBN 0 270 #define ESF_GZ_EV_256_EVENT_DW0_WIDTH 32 271 #define ESF_GZ_EV_256_EVENT_DW1_LBN 32 272 #define ESF_GZ_EV_256_EVENT_DW1_WIDTH 32 273 #define ESF_GZ_EV_256_EVENT_LBN 0 274 #define ESF_GZ_EV_256_EVENT_WIDTH 64 275 #define ESE_GZ_EW_EMBEDDED_EVENT_STRUCT_SIZE 64 276 277 278 /* ES_NMMU_PAGESZ_2M_ADDR */ 279 #define ESF_GZ_NMMU_2M_PAGE_SIZE_ID_LBN 59 280 #define ESF_GZ_NMMU_2M_PAGE_SIZE_ID_WIDTH 5 281 #define ESE_GZ_NMMU_PAGE_SIZE_2M 9 282 #define ESF_GZ_NMMU_2M_PAGE_ID_DW0_LBN 21 283 #define ESF_GZ_NMMU_2M_PAGE_ID_DW0_WIDTH 32 284 #define ESF_GZ_NMMU_2M_PAGE_ID_DW1_LBN 53 285 #define ESF_GZ_NMMU_2M_PAGE_ID_DW1_WIDTH 6 286 #define ESF_GZ_NMMU_2M_PAGE_ID_LBN 21 287 #define ESF_GZ_NMMU_2M_PAGE_ID_WIDTH 38 288 #define ESF_GZ_NMMU_2M_PAGE_OFFSET_LBN 0 289 #define ESF_GZ_NMMU_2M_PAGE_OFFSET_WIDTH 21 290 #define ESE_GZ_NMMU_PAGESZ_2M_ADDR_STRUCT_SIZE 64 291 292 293 /* ES_PARAM_TLV */ 294 #define ESF_GZ_TLV_VALUE_LBN 16 295 #define ESF_GZ_TLV_VALUE_WIDTH 8 296 #define ESE_GZ_TLV_VALUE_LENMIN 8 297 #define ESE_GZ_TLV_VALUE_LENMAX 2040 298 #define ESF_GZ_TLV_LEN_LBN 8 299 #define ESF_GZ_TLV_LEN_WIDTH 8 300 #define ESF_GZ_TLV_TYPE_LBN 0 301 #define ESF_GZ_TLV_TYPE_WIDTH 8 302 #define ESE_GZ_DP_NMMU_GROUP_SIZE 5 303 #define ESE_GZ_DP_EVQ_UNSOL_CREDIT_SEQ_BITS 4 304 #define ESE_GZ_DP_TX_EV_NUM_DESCS_BITS 3 305 #define ESE_GZ_DP_RX_EV_NUM_PACKETS_BITS 2 306 #define ESE_GZ_DP_PARTIAL_TSTAMP_SUB_NANO_BITS 1 307 #define ESE_GZ_DP_PAD 0 308 #define ESE_GZ_PARAM_TLV_STRUCT_SIZE 24 309 310 311 /* ES_PCI_EXPRESS_XCAP_HDR */ 312 #define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_LBN 20 313 #define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_WIDTH 12 314 #define ESF_GZ_PCI_EXPRESS_XCAP_VER_LBN 16 315 #define ESF_GZ_PCI_EXPRESS_XCAP_VER_WIDTH 4 316 #define ESE_GZ_PCI_EXPRESS_XCAP_VER_VSEC 1 317 #define ESF_GZ_PCI_EXPRESS_XCAP_ID_LBN 0 318 #define ESF_GZ_PCI_EXPRESS_XCAP_ID_WIDTH 16 319 #define ESE_GZ_PCI_EXPRESS_XCAP_ID_VNDR 0xb 320 #define ESE_GZ_PCI_EXPRESS_XCAP_HDR_STRUCT_SIZE 32 321 322 323 /* ES_RHEAD_BASE_EVENT */ 324 #define ESF_GZ_E_TYPE_LBN 60 325 #define ESF_GZ_E_TYPE_WIDTH 4 326 #define ESE_GZ_EF100_EV_DRIVER 5 327 #define ESE_GZ_EF100_EV_MCDI 4 328 #define ESE_GZ_EF100_EV_CONTROL 3 329 #define ESE_GZ_EF100_EV_TX_TIMESTAMP 2 330 #define ESE_GZ_EF100_EV_TX_COMPLETION 1 331 #define ESE_GZ_EF100_EV_RX_PKTS 0 332 #define ESF_GZ_EV_EVQ_PHASE_LBN 59 333 #define ESF_GZ_EV_EVQ_PHASE_WIDTH 1 334 #define ESE_GZ_RHEAD_BASE_EVENT_STRUCT_SIZE 64 335 336 337 /* ES_RHEAD_EW_EVENT */ 338 #define ESF_GZ_EV_256_EV32_PHASE_LBN 255 339 #define ESF_GZ_EV_256_EV32_PHASE_WIDTH 1 340 #define ESF_GZ_EV_256_EV32_TYPE_LBN 251 341 #define ESF_GZ_EV_256_EV32_TYPE_WIDTH 4 342 #define ESE_GZ_EF100_EVEW_VIRTQ_DESC 2 343 #define ESE_GZ_EF100_EVEW_TXQ_DESC 1 344 #define ESE_GZ_EF100_EVEW_64BIT 0 345 #define ESE_GZ_RHEAD_EW_EVENT_STRUCT_SIZE 256 346 347 348 /* ES_RX_DESC */ 349 #define ESF_GZ_RX_BUF_ADDR_DW0_LBN 0 350 #define ESF_GZ_RX_BUF_ADDR_DW0_WIDTH 32 351 #define ESF_GZ_RX_BUF_ADDR_DW1_LBN 32 352 #define ESF_GZ_RX_BUF_ADDR_DW1_WIDTH 32 353 #define ESF_GZ_RX_BUF_ADDR_LBN 0 354 #define ESF_GZ_RX_BUF_ADDR_WIDTH 64 355 #define ESE_GZ_RX_DESC_STRUCT_SIZE 64 356 357 358 /* ES_TXQ_DESC_PROXY_EVENT */ 359 #define ESF_GZ_EV_TXQ_DP_VI_ID_LBN 128 360 #define ESF_GZ_EV_TXQ_DP_VI_ID_WIDTH 16 361 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW0_LBN 0 362 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW0_WIDTH 32 363 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW1_LBN 32 364 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW1_WIDTH 32 365 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW2_LBN 64 366 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW2_WIDTH 32 367 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW3_LBN 96 368 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW3_WIDTH 32 369 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_LBN 0 370 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_WIDTH 128 371 #define ESE_GZ_TXQ_DESC_PROXY_EVENT_STRUCT_SIZE 144 372 373 374 /* ES_TX_DESC_TYPE */ 375 #define ESF_GZ_TX_DESC_TYPE_LBN 124 376 #define ESF_GZ_TX_DESC_TYPE_WIDTH 4 377 #define ESE_GZ_TX_DESC_TYPE_DESC2CMPT 7 378 #define ESE_GZ_TX_DESC_TYPE_MEM2MEM 4 379 #define ESE_GZ_TX_DESC_TYPE_SEG 3 380 #define ESE_GZ_TX_DESC_TYPE_TSO 2 381 #define ESE_GZ_TX_DESC_TYPE_PREFIX 1 382 #define ESE_GZ_TX_DESC_TYPE_SEND 0 383 #define ESE_GZ_TX_DESC_TYPE_STRUCT_SIZE 128 384 385 386 /* ES_VIRTQ_DESC_PROXY_EVENT */ 387 #define ESF_GZ_EV_VQ_DP_AVAIL_ENTRY_LBN 144 388 #define ESF_GZ_EV_VQ_DP_AVAIL_ENTRY_WIDTH 16 389 #define ESF_GZ_EV_VQ_DP_VI_ID_LBN 128 390 #define ESF_GZ_EV_VQ_DP_VI_ID_WIDTH 16 391 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW0_LBN 0 392 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW0_WIDTH 32 393 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW1_LBN 32 394 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW1_WIDTH 32 395 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW2_LBN 64 396 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW2_WIDTH 32 397 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW3_LBN 96 398 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW3_WIDTH 32 399 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_LBN 0 400 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_WIDTH 128 401 #define ESE_GZ_VIRTQ_DESC_PROXY_EVENT_STRUCT_SIZE 160 402 403 404 /* ES_XIL_CFGBAR_TBL_ENTRY */ 405 #define ESF_GZ_CFGBAR_CONT_CAP_OFF_HI_LBN 96 406 #define ESF_GZ_CFGBAR_CONT_CAP_OFF_HI_WIDTH 32 407 #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_DW0_LBN 68 408 #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_DW0_WIDTH 32 409 #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_DW1_LBN 100 410 #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_DW1_WIDTH 28 411 #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_LBN 68 412 #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_WIDTH 60 413 #define ESE_GZ_CONT_CAP_OFFSET_BYTES_SHIFT 4 414 #define ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_LBN 67 415 #define ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_WIDTH 29 416 #define ESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT 4 417 #define ESF_GZ_CFGBAR_CONT_CAP_OFF_LO_LBN 68 418 #define ESF_GZ_CFGBAR_CONT_CAP_OFF_LO_WIDTH 28 419 #define ESF_GZ_CFGBAR_CONT_CAP_RSV_LBN 67 420 #define ESF_GZ_CFGBAR_CONT_CAP_RSV_WIDTH 1 421 #define ESF_GZ_CFGBAR_EF100_BAR_LBN 64 422 #define ESF_GZ_CFGBAR_EF100_BAR_WIDTH 3 423 #define ESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID 7 424 #define ESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM 6 425 #define ESF_GZ_CFGBAR_CONT_CAP_BAR_LBN 64 426 #define ESF_GZ_CFGBAR_CONT_CAP_BAR_WIDTH 3 427 #define ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_INVALID 7 428 #define ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_EXPANSION_ROM 6 429 #define ESF_GZ_CFGBAR_ENTRY_SIZE_LBN 32 430 #define ESF_GZ_CFGBAR_ENTRY_SIZE_WIDTH 32 431 #define ESE_GZ_CFGBAR_ENTRY_SIZE_EF100 12 432 #define ESE_GZ_CFGBAR_ENTRY_HEADER_SIZE 8 433 #define ESF_GZ_CFGBAR_ENTRY_LAST_LBN 28 434 #define ESF_GZ_CFGBAR_ENTRY_LAST_WIDTH 1 435 #define ESF_GZ_CFGBAR_ENTRY_REV_LBN 20 436 #define ESF_GZ_CFGBAR_ENTRY_REV_WIDTH 8 437 #define ESE_GZ_CFGBAR_ENTRY_REV_EF100 0 438 #define ESF_GZ_CFGBAR_ENTRY_FORMAT_LBN 0 439 #define ESF_GZ_CFGBAR_ENTRY_FORMAT_WIDTH 20 440 #define ESE_GZ_CFGBAR_ENTRY_LAST 0xfffff 441 #define ESE_GZ_CFGBAR_ENTRY_CONT_CAP_ADDR 0xffffe 442 #define ESE_GZ_CFGBAR_ENTRY_EF100 0xef100 443 #define ESE_GZ_XIL_CFGBAR_TBL_ENTRY_STRUCT_SIZE 128 444 445 446 /* ES_XIL_CFGBAR_VSEC */ 447 #define ESF_GZ_VSEC_TBL_OFF_HI_LBN 64 448 #define ESF_GZ_VSEC_TBL_OFF_HI_WIDTH 32 449 #define ESE_GZ_VSEC_TBL_OFF_HI_BYTES_SHIFT 32 450 #define ESF_GZ_VSEC_TBL_OFF_LO_LBN 36 451 #define ESF_GZ_VSEC_TBL_OFF_LO_WIDTH 28 452 #define ESE_GZ_VSEC_TBL_OFF_LO_BYTES_SHIFT 4 453 #define ESF_GZ_VSEC_TBL_BAR_LBN 32 454 #define ESF_GZ_VSEC_TBL_BAR_WIDTH 4 455 #define ESE_GZ_VSEC_BAR_NUM_INVALID 7 456 #define ESE_GZ_VSEC_BAR_NUM_EXPANSION_ROM 6 457 #define ESF_GZ_VSEC_LEN_LBN 20 458 #define ESF_GZ_VSEC_LEN_WIDTH 12 459 #define ESE_GZ_VSEC_LEN_HIGH_OFFT 16 460 #define ESE_GZ_VSEC_LEN_MIN 12 461 #define ESF_GZ_VSEC_VER_LBN 16 462 #define ESF_GZ_VSEC_VER_WIDTH 4 463 #define ESE_GZ_VSEC_VER_XIL_CFGBAR 0 464 #define ESF_GZ_VSEC_ID_LBN 0 465 #define ESF_GZ_VSEC_ID_WIDTH 16 466 #define ESE_GZ_XILINX_VSEC_ID 0x20 467 #define ESE_GZ_XIL_CFGBAR_VSEC_STRUCT_SIZE 96 468 469 470 /* ES_rh_egres_hclass */ 471 #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_LBN 15 472 #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_WIDTH 1 473 #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_LBN 13 474 #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_WIDTH 2 475 #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_LBN 12 476 #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_WIDTH 1 477 #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_LBN 10 478 #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_WIDTH 2 479 #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_LBN 8 480 #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_WIDTH 2 481 #define ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_LBN 5 482 #define ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_WIDTH 3 483 #define ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_LBN 3 484 #define ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_WIDTH 2 485 #define ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_LBN 2 486 #define ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_WIDTH 1 487 #define ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_LBN 0 488 #define ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_WIDTH 2 489 #define ESE_GZ_RH_EGRES_HCLASS_STRUCT_SIZE 16 490 491 492 /* ES_sf_driver */ 493 #define ESF_GZ_DRIVER_E_TYPE_LBN 60 494 #define ESF_GZ_DRIVER_E_TYPE_WIDTH 4 495 #define ESF_GZ_DRIVER_PHASE_LBN 59 496 #define ESF_GZ_DRIVER_PHASE_WIDTH 1 497 #define ESF_GZ_DRIVER_DATA_DW0_LBN 0 498 #define ESF_GZ_DRIVER_DATA_DW0_WIDTH 32 499 #define ESF_GZ_DRIVER_DATA_DW1_LBN 32 500 #define ESF_GZ_DRIVER_DATA_DW1_WIDTH 27 501 #define ESF_GZ_DRIVER_DATA_LBN 0 502 #define ESF_GZ_DRIVER_DATA_WIDTH 59 503 #define ESE_GZ_SF_DRIVER_STRUCT_SIZE 64 504 505 506 /* ES_sf_ev_rsvd */ 507 #define ESF_GZ_EV_RSVD_TBD_NEXT_LBN 34 508 #define ESF_GZ_EV_RSVD_TBD_NEXT_WIDTH 3 509 #define ESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_LBN 30 510 #define ESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_WIDTH 4 511 #define ESF_GZ_EV_RSVD_SRC_QID_LBN 18 512 #define ESF_GZ_EV_RSVD_SRC_QID_WIDTH 12 513 #define ESF_GZ_EV_RSVD_SEQ_NUM_LBN 2 514 #define ESF_GZ_EV_RSVD_SEQ_NUM_WIDTH 16 515 #define ESF_GZ_EV_RSVD_TBD_LBN 0 516 #define ESF_GZ_EV_RSVD_TBD_WIDTH 2 517 #define ESE_GZ_SF_EV_RSVD_STRUCT_SIZE 37 518 519 520 /* ES_sf_flush_evnt */ 521 #define ESF_GZ_EV_FLSH_E_TYPE_LBN 60 522 #define ESF_GZ_EV_FLSH_E_TYPE_WIDTH 4 523 #define ESF_GZ_EV_FLSH_PHASE_LBN 59 524 #define ESF_GZ_EV_FLSH_PHASE_WIDTH 1 525 #define ESF_GZ_EV_FLSH_SUB_TYPE_LBN 53 526 #define ESF_GZ_EV_FLSH_SUB_TYPE_WIDTH 6 527 #define ESF_GZ_EV_FLSH_RSVD_DW0_LBN 10 528 #define ESF_GZ_EV_FLSH_RSVD_DW0_WIDTH 32 529 #define ESF_GZ_EV_FLSH_RSVD_DW1_LBN 42 530 #define ESF_GZ_EV_FLSH_RSVD_DW1_WIDTH 11 531 #define ESF_GZ_EV_FLSH_RSVD_LBN 10 532 #define ESF_GZ_EV_FLSH_RSVD_WIDTH 43 533 #define ESF_GZ_EV_FLSH_LABEL_LBN 4 534 #define ESF_GZ_EV_FLSH_LABEL_WIDTH 6 535 #define ESF_GZ_EV_FLSH_FLUSH_TYPE_LBN 0 536 #define ESF_GZ_EV_FLSH_FLUSH_TYPE_WIDTH 4 537 #define ESE_GZ_SF_FLUSH_EVNT_STRUCT_SIZE 64 538 539 540 /* ES_sf_rx_pkts */ 541 #define ESF_GZ_EV_RXPKTS_E_TYPE_LBN 60 542 #define ESF_GZ_EV_RXPKTS_E_TYPE_WIDTH 4 543 #define ESF_GZ_EV_RXPKTS_PHASE_LBN 59 544 #define ESF_GZ_EV_RXPKTS_PHASE_WIDTH 1 545 #define ESF_GZ_EV_RXPKTS_RSVD_DW0_LBN 22 546 #define ESF_GZ_EV_RXPKTS_RSVD_DW0_WIDTH 32 547 #define ESF_GZ_EV_RXPKTS_RSVD_DW1_LBN 54 548 #define ESF_GZ_EV_RXPKTS_RSVD_DW1_WIDTH 5 549 #define ESF_GZ_EV_RXPKTS_RSVD_LBN 22 550 #define ESF_GZ_EV_RXPKTS_RSVD_WIDTH 37 551 #define ESF_GZ_EV_RXPKTS_Q_LABEL_LBN 16 552 #define ESF_GZ_EV_RXPKTS_Q_LABEL_WIDTH 6 553 #define ESF_GZ_EV_RXPKTS_NUM_PKT_LBN 0 554 #define ESF_GZ_EV_RXPKTS_NUM_PKT_WIDTH 16 555 #define ESE_GZ_SF_RX_PKTS_STRUCT_SIZE 64 556 557 558 /* ES_sf_rx_prefix */ 559 #define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_LBN 160 560 #define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_WIDTH 16 561 #define ESF_GZ_RX_PREFIX_CSUM_FRAME_LBN 144 562 #define ESF_GZ_RX_PREFIX_CSUM_FRAME_WIDTH 16 563 #define ESF_GZ_RX_PREFIX_INGRESS_VPORT_LBN 128 564 #define ESF_GZ_RX_PREFIX_INGRESS_VPORT_WIDTH 16 565 #define ESF_GZ_RX_PREFIX_USER_MARK_LBN 96 566 #define ESF_GZ_RX_PREFIX_USER_MARK_WIDTH 32 567 #define ESF_GZ_RX_PREFIX_RSS_HASH_LBN 64 568 #define ESF_GZ_RX_PREFIX_RSS_HASH_WIDTH 32 569 #define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN 32 570 #define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_WIDTH 32 571 #define ESF_GZ_RX_PREFIX_CLASS_LBN 16 572 #define ESF_GZ_RX_PREFIX_CLASS_WIDTH 16 573 #define ESF_GZ_RX_PREFIX_USER_FLAG_LBN 15 574 #define ESF_GZ_RX_PREFIX_USER_FLAG_WIDTH 1 575 #define ESF_GZ_RX_PREFIX_RSS_HASH_VALID_LBN 14 576 #define ESF_GZ_RX_PREFIX_RSS_HASH_VALID_WIDTH 1 577 #define ESF_GZ_RX_PREFIX_LENGTH_LBN 0 578 #define ESF_GZ_RX_PREFIX_LENGTH_WIDTH 14 579 #define ESE_GZ_SF_RX_PREFIX_STRUCT_SIZE 176 580 581 582 /* ES_sf_rxtx_generic */ 583 #define ESF_GZ_EV_BARRIER_LBN 167 584 #define ESF_GZ_EV_BARRIER_WIDTH 1 585 #define ESF_GZ_EV_RSVD_DW0_LBN 130 586 #define ESF_GZ_EV_RSVD_DW0_WIDTH 32 587 #define ESF_GZ_EV_RSVD_DW1_LBN 162 588 #define ESF_GZ_EV_RSVD_DW1_WIDTH 5 589 #define ESF_GZ_EV_RSVD_LBN 130 590 #define ESF_GZ_EV_RSVD_WIDTH 37 591 #define ESF_GZ_EV_DPRXY_LBN 129 592 #define ESF_GZ_EV_DPRXY_WIDTH 1 593 #define ESF_GZ_EV_VIRTIO_LBN 128 594 #define ESF_GZ_EV_VIRTIO_WIDTH 1 595 #define ESF_GZ_EV_COUNT_DW0_LBN 0 596 #define ESF_GZ_EV_COUNT_DW0_WIDTH 32 597 #define ESF_GZ_EV_COUNT_DW1_LBN 32 598 #define ESF_GZ_EV_COUNT_DW1_WIDTH 32 599 #define ESF_GZ_EV_COUNT_DW2_LBN 64 600 #define ESF_GZ_EV_COUNT_DW2_WIDTH 32 601 #define ESF_GZ_EV_COUNT_DW3_LBN 96 602 #define ESF_GZ_EV_COUNT_DW3_WIDTH 32 603 #define ESF_GZ_EV_COUNT_LBN 0 604 #define ESF_GZ_EV_COUNT_WIDTH 128 605 #define ESE_GZ_SF_RXTX_GENERIC_STRUCT_SIZE 168 606 607 608 /* ES_sf_ts_stamp */ 609 #define ESF_GZ_EV_TS_E_TYPE_LBN 60 610 #define ESF_GZ_EV_TS_E_TYPE_WIDTH 4 611 #define ESF_GZ_EV_TS_PHASE_LBN 59 612 #define ESF_GZ_EV_TS_PHASE_WIDTH 1 613 #define ESF_GZ_EV_TS_RSVD_LBN 56 614 #define ESF_GZ_EV_TS_RSVD_WIDTH 3 615 #define ESF_GZ_EV_TS_STATUS_LBN 54 616 #define ESF_GZ_EV_TS_STATUS_WIDTH 2 617 #define ESF_GZ_EV_TS_Q_LABEL_LBN 48 618 #define ESF_GZ_EV_TS_Q_LABEL_WIDTH 6 619 #define ESF_GZ_EV_TS_DESC_ID_LBN 32 620 #define ESF_GZ_EV_TS_DESC_ID_WIDTH 16 621 #define ESF_GZ_EV_TS_PARTIAL_STAMP_LBN 0 622 #define ESF_GZ_EV_TS_PARTIAL_STAMP_WIDTH 32 623 #define ESE_GZ_SF_TS_STAMP_STRUCT_SIZE 64 624 625 626 /* ES_sf_tx_cmplt */ 627 #define ESF_GZ_EV_TXCMPL_E_TYPE_LBN 60 628 #define ESF_GZ_EV_TXCMPL_E_TYPE_WIDTH 4 629 #define ESF_GZ_EV_TXCMPL_PHASE_LBN 59 630 #define ESF_GZ_EV_TXCMPL_PHASE_WIDTH 1 631 #define ESF_GZ_EV_TXCMPL_RSVD_DW0_LBN 22 632 #define ESF_GZ_EV_TXCMPL_RSVD_DW0_WIDTH 32 633 #define ESF_GZ_EV_TXCMPL_RSVD_DW1_LBN 54 634 #define ESF_GZ_EV_TXCMPL_RSVD_DW1_WIDTH 5 635 #define ESF_GZ_EV_TXCMPL_RSVD_LBN 22 636 #define ESF_GZ_EV_TXCMPL_RSVD_WIDTH 37 637 #define ESF_GZ_EV_TXCMPL_Q_LABEL_LBN 16 638 #define ESF_GZ_EV_TXCMPL_Q_LABEL_WIDTH 6 639 #define ESF_GZ_EV_TXCMPL_NUM_DESC_LBN 0 640 #define ESF_GZ_EV_TXCMPL_NUM_DESC_WIDTH 16 641 #define ESE_GZ_SF_TX_CMPLT_STRUCT_SIZE 64 642 643 644 /* ES_sf_tx_desc2cmpt_dsc_fmt */ 645 #define ESF_GZ_D2C_TGT_VI_ID_LBN 108 646 #define ESF_GZ_D2C_TGT_VI_ID_WIDTH 16 647 #define ESF_GZ_D2C_CMPT2_LBN 107 648 #define ESF_GZ_D2C_CMPT2_WIDTH 1 649 #define ESF_GZ_D2C_ABS_VI_ID_LBN 106 650 #define ESF_GZ_D2C_ABS_VI_ID_WIDTH 1 651 #define ESF_GZ_D2C_ORDERED_LBN 105 652 #define ESF_GZ_D2C_ORDERED_WIDTH 1 653 #define ESF_GZ_D2C_SKIP_N_LBN 97 654 #define ESF_GZ_D2C_SKIP_N_WIDTH 8 655 #define ESF_GZ_D2C_RSVD_DW0_LBN 64 656 #define ESF_GZ_D2C_RSVD_DW0_WIDTH 32 657 #define ESF_GZ_D2C_RSVD_DW1_LBN 96 658 #define ESF_GZ_D2C_RSVD_DW1_WIDTH 1 659 #define ESF_GZ_D2C_RSVD_LBN 64 660 #define ESF_GZ_D2C_RSVD_WIDTH 33 661 #define ESF_GZ_D2C_COMPLETION_DW0_LBN 0 662 #define ESF_GZ_D2C_COMPLETION_DW0_WIDTH 32 663 #define ESF_GZ_D2C_COMPLETION_DW1_LBN 32 664 #define ESF_GZ_D2C_COMPLETION_DW1_WIDTH 32 665 #define ESF_GZ_D2C_COMPLETION_LBN 0 666 #define ESF_GZ_D2C_COMPLETION_WIDTH 64 667 #define ESE_GZ_SF_TX_DESC2CMPT_DSC_FMT_STRUCT_SIZE 124 668 669 670 /* ES_sf_tx_mem2mem_dsc_fmt */ 671 #define ESF_GZ_M2M_ADDR_SPC_EN_LBN 123 672 #define ESF_GZ_M2M_ADDR_SPC_EN_WIDTH 1 673 #define ESF_GZ_M2M_TRANSLATE_ADDR_LBN 122 674 #define ESF_GZ_M2M_TRANSLATE_ADDR_WIDTH 1 675 #define ESF_GZ_M2M_RSVD_LBN 120 676 #define ESF_GZ_M2M_RSVD_WIDTH 2 677 #define ESF_GZ_M2M_ADDR_SPC_LBN 108 678 #define ESF_GZ_M2M_ADDR_SPC_WIDTH 12 679 #define ESF_GZ_M2M_ADDR_SPC_PASID_LBN 86 680 #define ESF_GZ_M2M_ADDR_SPC_PASID_WIDTH 22 681 #define ESF_GZ_M2M_ADDR_SPC_MODE_LBN 84 682 #define ESF_GZ_M2M_ADDR_SPC_MODE_WIDTH 2 683 #define ESF_GZ_M2M_LEN_MINUS_1_LBN 64 684 #define ESF_GZ_M2M_LEN_MINUS_1_WIDTH 20 685 #define ESF_GZ_M2M_ADDR_DW0_LBN 0 686 #define ESF_GZ_M2M_ADDR_DW0_WIDTH 32 687 #define ESF_GZ_M2M_ADDR_DW1_LBN 32 688 #define ESF_GZ_M2M_ADDR_DW1_WIDTH 32 689 #define ESF_GZ_M2M_ADDR_LBN 0 690 #define ESF_GZ_M2M_ADDR_WIDTH 64 691 #define ESE_GZ_SF_TX_MEM2MEM_DSC_FMT_STRUCT_SIZE 124 692 693 694 /* ES_sf_tx_ovr_dsc_fmt */ 695 #define ESF_GZ_TX_PREFIX_MARK_EN_LBN 123 696 #define ESF_GZ_TX_PREFIX_MARK_EN_WIDTH 1 697 #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_LBN 122 698 #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_WIDTH 1 699 #define ESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_LBN 121 700 #define ESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_WIDTH 1 701 #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_LBN 120 702 #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_WIDTH 1 703 #define ESF_GZ_TX_PREFIX_RSRVD_DW0_LBN 64 704 #define ESF_GZ_TX_PREFIX_RSRVD_DW0_WIDTH 32 705 #define ESF_GZ_TX_PREFIX_RSRVD_DW1_LBN 96 706 #define ESF_GZ_TX_PREFIX_RSRVD_DW1_WIDTH 24 707 #define ESF_GZ_TX_PREFIX_RSRVD_LBN 64 708 #define ESF_GZ_TX_PREFIX_RSRVD_WIDTH 56 709 #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_LBN 48 710 #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_WIDTH 16 711 #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_LBN 32 712 #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_WIDTH 16 713 #define ESF_GZ_TX_PREFIX_MARK_LBN 0 714 #define ESF_GZ_TX_PREFIX_MARK_WIDTH 32 715 #define ESE_GZ_SF_TX_OVR_DSC_FMT_STRUCT_SIZE 124 716 717 718 /* ES_sf_tx_seg_dsc_fmt */ 719 #define ESF_GZ_TX_SEG_ADDR_SPC_EN_LBN 123 720 #define ESF_GZ_TX_SEG_ADDR_SPC_EN_WIDTH 1 721 #define ESF_GZ_TX_SEG_TRANSLATE_ADDR_LBN 122 722 #define ESF_GZ_TX_SEG_TRANSLATE_ADDR_WIDTH 1 723 #define ESF_GZ_TX_SEG_RSVD2_LBN 120 724 #define ESF_GZ_TX_SEG_RSVD2_WIDTH 2 725 #define ESF_GZ_TX_SEG_ADDR_SPC_LBN 108 726 #define ESF_GZ_TX_SEG_ADDR_SPC_WIDTH 12 727 #define ESF_GZ_TX_SEG_ADDR_SPC_PASID_LBN 86 728 #define ESF_GZ_TX_SEG_ADDR_SPC_PASID_WIDTH 22 729 #define ESF_GZ_TX_SEG_ADDR_SPC_MODE_LBN 84 730 #define ESF_GZ_TX_SEG_ADDR_SPC_MODE_WIDTH 2 731 #define ESF_GZ_TX_SEG_RSVD_LBN 80 732 #define ESF_GZ_TX_SEG_RSVD_WIDTH 4 733 #define ESF_GZ_TX_SEG_LEN_LBN 64 734 #define ESF_GZ_TX_SEG_LEN_WIDTH 16 735 #define ESF_GZ_TX_SEG_ADDR_DW0_LBN 0 736 #define ESF_GZ_TX_SEG_ADDR_DW0_WIDTH 32 737 #define ESF_GZ_TX_SEG_ADDR_DW1_LBN 32 738 #define ESF_GZ_TX_SEG_ADDR_DW1_WIDTH 32 739 #define ESF_GZ_TX_SEG_ADDR_LBN 0 740 #define ESF_GZ_TX_SEG_ADDR_WIDTH 64 741 #define ESE_GZ_SF_TX_SEG_DSC_FMT_STRUCT_SIZE 124 742 743 744 /* ES_sf_tx_std_dsc_fmt */ 745 #define ESF_GZ_TX_SEND_VLAN_INSERT_TCI_LBN 108 746 #define ESF_GZ_TX_SEND_VLAN_INSERT_TCI_WIDTH 16 747 #define ESF_GZ_TX_SEND_VLAN_INSERT_EN_LBN 107 748 #define ESF_GZ_TX_SEND_VLAN_INSERT_EN_WIDTH 1 749 #define ESF_GZ_TX_SEND_TSTAMP_REQ_LBN 106 750 #define ESF_GZ_TX_SEND_TSTAMP_REQ_WIDTH 1 751 #define ESF_GZ_TX_SEND_CSO_OUTER_L4_LBN 105 752 #define ESF_GZ_TX_SEND_CSO_OUTER_L4_WIDTH 1 753 #define ESF_GZ_TX_SEND_CSO_OUTER_L3_LBN 104 754 #define ESF_GZ_TX_SEND_CSO_OUTER_L3_WIDTH 1 755 #define ESF_GZ_TX_SEND_CSO_INNER_L3_LBN 101 756 #define ESF_GZ_TX_SEND_CSO_INNER_L3_WIDTH 3 757 #define ESF_GZ_TX_SEND_RSVD_LBN 99 758 #define ESF_GZ_TX_SEND_RSVD_WIDTH 2 759 #define ESF_GZ_TX_SEND_CSO_PARTIAL_EN_LBN 97 760 #define ESF_GZ_TX_SEND_CSO_PARTIAL_EN_WIDTH 2 761 #define ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_LBN 92 762 #define ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_WIDTH 5 763 #define ESF_GZ_TX_SEND_CSO_PARTIAL_START_W_LBN 83 764 #define ESF_GZ_TX_SEND_CSO_PARTIAL_START_W_WIDTH 9 765 #define ESF_GZ_TX_SEND_NUM_SEGS_LBN 78 766 #define ESF_GZ_TX_SEND_NUM_SEGS_WIDTH 5 767 #define ESF_GZ_TX_SEND_LEN_LBN 64 768 #define ESF_GZ_TX_SEND_LEN_WIDTH 14 769 #define ESF_GZ_TX_SEND_ADDR_DW0_LBN 0 770 #define ESF_GZ_TX_SEND_ADDR_DW0_WIDTH 32 771 #define ESF_GZ_TX_SEND_ADDR_DW1_LBN 32 772 #define ESF_GZ_TX_SEND_ADDR_DW1_WIDTH 32 773 #define ESF_GZ_TX_SEND_ADDR_LBN 0 774 #define ESF_GZ_TX_SEND_ADDR_WIDTH 64 775 #define ESE_GZ_SF_TX_STD_DSC_FMT_STRUCT_SIZE 124 776 777 778 /* ES_sf_tx_tso_dsc_fmt */ 779 #define ESF_GZ_TX_TSO_VLAN_INSERT_TCI_LBN 108 780 #define ESF_GZ_TX_TSO_VLAN_INSERT_TCI_WIDTH 16 781 #define ESF_GZ_TX_TSO_VLAN_INSERT_EN_LBN 107 782 #define ESF_GZ_TX_TSO_VLAN_INSERT_EN_WIDTH 1 783 #define ESF_GZ_TX_TSO_TSTAMP_REQ_LBN 106 784 #define ESF_GZ_TX_TSO_TSTAMP_REQ_WIDTH 1 785 #define ESF_GZ_TX_TSO_CSO_OUTER_L4_LBN 105 786 #define ESF_GZ_TX_TSO_CSO_OUTER_L4_WIDTH 1 787 #define ESF_GZ_TX_TSO_CSO_OUTER_L3_LBN 104 788 #define ESF_GZ_TX_TSO_CSO_OUTER_L3_WIDTH 1 789 #define ESF_GZ_TX_TSO_CSO_INNER_L3_LBN 101 790 #define ESF_GZ_TX_TSO_CSO_INNER_L3_WIDTH 3 791 #define ESF_GZ_TX_TSO_RSVD_LBN 94 792 #define ESF_GZ_TX_TSO_RSVD_WIDTH 7 793 #define ESF_GZ_TX_TSO_CSO_INNER_L4_LBN 93 794 #define ESF_GZ_TX_TSO_CSO_INNER_L4_WIDTH 1 795 #define ESF_GZ_TX_TSO_INNER_L4_OFF_W_LBN 85 796 #define ESF_GZ_TX_TSO_INNER_L4_OFF_W_WIDTH 8 797 #define ESF_GZ_TX_TSO_INNER_L3_OFF_W_LBN 77 798 #define ESF_GZ_TX_TSO_INNER_L3_OFF_W_WIDTH 8 799 #define ESF_GZ_TX_TSO_OUTER_L4_OFF_W_LBN 69 800 #define ESF_GZ_TX_TSO_OUTER_L4_OFF_W_WIDTH 8 801 #define ESF_GZ_TX_TSO_OUTER_L3_OFF_W_LBN 64 802 #define ESF_GZ_TX_TSO_OUTER_L3_OFF_W_WIDTH 5 803 #define ESF_GZ_TX_TSO_PAYLOAD_LEN_LBN 42 804 #define ESF_GZ_TX_TSO_PAYLOAD_LEN_WIDTH 22 805 #define ESF_GZ_TX_TSO_HDR_LEN_W_LBN 34 806 #define ESF_GZ_TX_TSO_HDR_LEN_W_WIDTH 8 807 #define ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_LBN 33 808 #define ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_WIDTH 1 809 #define ESF_GZ_TX_TSO_ED_INNER_IP_LEN_LBN 32 810 #define ESF_GZ_TX_TSO_ED_INNER_IP_LEN_WIDTH 1 811 #define ESF_GZ_TX_TSO_ED_OUTER_IP_LEN_LBN 31 812 #define ESF_GZ_TX_TSO_ED_OUTER_IP_LEN_WIDTH 1 813 #define ESF_GZ_TX_TSO_ED_INNER_IP4_ID_LBN 29 814 #define ESF_GZ_TX_TSO_ED_INNER_IP4_ID_WIDTH 2 815 #define ESF_GZ_TX_TSO_ED_OUTER_IP4_ID_LBN 27 816 #define ESF_GZ_TX_TSO_ED_OUTER_IP4_ID_WIDTH 2 817 #define ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_LBN 17 818 #define ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_WIDTH 10 819 #define ESF_GZ_TX_TSO_HDR_NUM_SEGS_LBN 14 820 #define ESF_GZ_TX_TSO_HDR_NUM_SEGS_WIDTH 3 821 #define ESF_GZ_TX_TSO_MSS_LBN 0 822 #define ESF_GZ_TX_TSO_MSS_WIDTH 14 823 #define ESE_GZ_SF_TX_TSO_DSC_FMT_STRUCT_SIZE 124 824 825 826 827 /* Enum DESIGN_PARAMS */ 828 #define ESE_EF100_DP_GZ_RX_MAX_RUNT 17 829 #define ESE_EF100_DP_GZ_VI_STRIDES 16 830 #define ESE_EF100_DP_GZ_NMMU_PAGE_SIZES 15 831 #define ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS 14 832 #define ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN 13 833 #define ESE_EF100_DP_GZ_COMPAT 12 834 #define ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES 11 835 #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS 10 836 #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN 9 837 #define ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY 8 838 #define ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY 7 839 #define ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS 6 840 #define ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN 5 841 #define ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS 4 842 #define ESE_EF100_DP_GZ_NMMU_GROUP_SIZE 3 843 #define ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS 2 844 #define ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS 1 845 #define ESE_EF100_DP_GZ_PAD 0 846 847 /* Enum DESIGN_PARAM_DEFAULTS */ 848 #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT 0x3fffff 849 #define ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT 8192 850 #define ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN_DEFAULT 8192 851 #define ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS_DEFAULT 0x1106 852 #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT 0x3ff 853 #define ESE_EF100_DP_GZ_RX_MAX_RUNT_DEFAULT 640 854 #define ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS_DEFAULT 512 855 #define ESE_EF100_DP_GZ_NMMU_PAGE_SIZES_DEFAULT 512 856 #define ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT 192 857 #define ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY_DEFAULT 64 858 #define ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY_DEFAULT 64 859 #define ESE_EF100_DP_GZ_NMMU_GROUP_SIZE_DEFAULT 32 860 #define ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT 16 861 #define ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS_DEFAULT 7 862 #define ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT 4 863 #define ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS_DEFAULT 2 864 #define ESE_EF100_DP_GZ_COMPAT_DEFAULT 0 865 866 /* Enum HOST_IF_CONSTANTS */ 867 #define ESE_GZ_FCW_LEN 0x4C 868 #define ESE_GZ_RX_PKT_PREFIX_LEN 22 869 870 /* Enum PCI_CONSTANTS */ 871 #define ESE_GZ_PCI_BASE_CONFIG_SPACE_SIZE 256 872 #define ESE_GZ_PCI_EXPRESS_XCAP_HDR_SIZE 4 873 874 /* Enum RH_HCLASS_L2_CLASS */ 875 #define ESE_GZ_RH_HCLASS_L2_CLASS_E2_0123VLAN 1 876 #define ESE_GZ_RH_HCLASS_L2_CLASS_OTHER 0 877 878 /* Enum RH_HCLASS_L2_STATUS */ 879 #define ESE_GZ_RH_HCLASS_L2_STATUS_RESERVED 3 880 #define ESE_GZ_RH_HCLASS_L2_STATUS_FCS_ERR 2 881 #define ESE_GZ_RH_HCLASS_L2_STATUS_LEN_ERR 1 882 #define ESE_GZ_RH_HCLASS_L2_STATUS_OK 0 883 884 /* Enum RH_HCLASS_L3_CLASS */ 885 #define ESE_GZ_RH_HCLASS_L3_CLASS_OTHER 3 886 #define ESE_GZ_RH_HCLASS_L3_CLASS_IP6 2 887 #define ESE_GZ_RH_HCLASS_L3_CLASS_IP4BAD 1 888 #define ESE_GZ_RH_HCLASS_L3_CLASS_IP4GOOD 0 889 890 /* Enum RH_HCLASS_L4_CLASS */ 891 #define ESE_GZ_RH_HCLASS_L4_CLASS_OTHER 3 892 #define ESE_GZ_RH_HCLASS_L4_CLASS_FRAG 2 893 #define ESE_GZ_RH_HCLASS_L4_CLASS_UDP 1 894 #define ESE_GZ_RH_HCLASS_L4_CLASS_TCP 0 895 896 /* Enum RH_HCLASS_L4_CSUM */ 897 #define ESE_GZ_RH_HCLASS_L4_CSUM_GOOD 1 898 #define ESE_GZ_RH_HCLASS_L4_CSUM_BAD_OR_UNKNOWN 0 899 900 /* Enum RH_HCLASS_TUNNEL_CLASS */ 901 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_7 7 902 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_6 6 903 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_5 5 904 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_4 4 905 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_GENEVE 3 906 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NVGRE 2 907 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_VXLAN 1 908 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NONE 0 909 910 /* Enum TX_DESC_CSO_PARTIAL_EN */ 911 #define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_TCP 2 912 #define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_UDP 1 913 #define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_OFF 0 914 915 /* Enum TX_DESC_CS_INNER_L3 */ 916 #define ESE_GZ_TX_DESC_CS_INNER_L3_GENEVE 3 917 #define ESE_GZ_TX_DESC_CS_INNER_L3_NVGRE 2 918 #define ESE_GZ_TX_DESC_CS_INNER_L3_VXLAN 1 919 #define ESE_GZ_TX_DESC_CS_INNER_L3_OFF 0 920 921 /* Enum TX_DESC_IP4_ID */ 922 #define ESE_GZ_TX_DESC_IP4_ID_INC_MOD16 2 923 #define ESE_GZ_TX_DESC_IP4_ID_INC_MOD15 1 924 #define ESE_GZ_TX_DESC_IP4_ID_NO_OP 0 925 /************************************************************************* 926 * NOTE: the comment line above marks the end of the autogenerated section 927 */ 928 929 930 #ifdef __cplusplus 931 } 932 #endif 933 934 #endif /* _SYS_EFX_EF100_REGS_H */ 935