1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2018-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_EF100_REGS_H 8 #define _SYS_EFX_EF100_REGS_H 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /************************************************************************** 15 * NOTE: the line below marks the start of the autogenerated section 16 * EF100 registers and descriptors 17 * 18 ************************************************************************** 19 */ 20 21 /* 22 * HW_REV_ID_REG(32bit): 23 * Hardware revision info register 24 */ 25 26 #define ER_GZ_HW_REV_ID_REG_OFST 0x00000000 27 /* rhead=rhead_host_regs */ 28 #define ER_GZ_HW_REV_ID_REG_RESET 0x0 29 30 31 32 33 /* 34 * NIC_REV_ID(32bit): 35 * SoftNIC revision info register 36 */ 37 38 #define ER_GZ_NIC_REV_ID_OFST 0x00000004 39 /* rhead=rhead_host_regs */ 40 #define ER_GZ_NIC_REV_ID_RESET 0x0 41 42 43 44 45 /* 46 * NIC_MAGIC(32bit): 47 * Signature register that should contain a well-known value 48 */ 49 50 #define ER_GZ_NIC_MAGIC_OFST 0x00000008 51 /* rhead=rhead_host_regs */ 52 #define ER_GZ_NIC_MAGIC_RESET 0x0 53 54 55 #define ERF_GZ_NIC_MAGIC_LBN 0 56 #define ERF_GZ_NIC_MAGIC_WIDTH 32 57 #define EFE_GZ_NIC_MAGIC_EXPECTED 0xEF100FCB 58 59 60 /* 61 * MC_SFT_STATUS(32bit): 62 * MC soft status 63 */ 64 65 #define ER_GZ_MC_SFT_STATUS_OFST 0x00000010 66 /* rhead=rhead_host_regs */ 67 #define ER_GZ_MC_SFT_STATUS_STEP 4 68 #define ER_GZ_MC_SFT_STATUS_ROWS 2 69 #define ER_GZ_MC_SFT_STATUS_RESET 0x0 70 71 72 73 74 /* 75 * MC_DB_LWRD_REG(32bit): 76 * MC doorbell register, low word 77 */ 78 79 #define ER_GZ_MC_DB_LWRD_REG_OFST 0x00000020 80 /* rhead=rhead_host_regs */ 81 #define ER_GZ_MC_DB_LWRD_REG_RESET 0x0 82 83 84 85 86 /* 87 * MC_DB_HWRD_REG(32bit): 88 * MC doorbell register, high word 89 */ 90 91 #define ER_GZ_MC_DB_HWRD_REG_OFST 0x00000024 92 /* rhead=rhead_host_regs */ 93 #define ER_GZ_MC_DB_HWRD_REG_RESET 0x0 94 95 96 97 98 /* 99 * EVQ_INT_PRIME(32bit): 100 * Prime EVQ 101 */ 102 103 #define ER_GZ_EVQ_INT_PRIME_OFST 0x00000040 104 /* rhead=rhead_host_regs */ 105 #define ER_GZ_EVQ_INT_PRIME_RESET 0x0 106 107 108 #define ERF_GZ_IDX_LBN 16 109 #define ERF_GZ_IDX_WIDTH 16 110 #define ERF_GZ_EVQ_ID_LBN 0 111 #define ERF_GZ_EVQ_ID_WIDTH 16 112 113 114 /* 115 * INT_AGG_RING_PRIME(32bit): 116 * Prime interrupt aggregation ring. 117 */ 118 119 #define ER_GZ_INT_AGG_RING_PRIME_OFST 0x00000048 120 /* rhead=rhead_host_regs */ 121 #define ER_GZ_INT_AGG_RING_PRIME_RESET 0x0 122 123 124 /* defined as ERF_GZ_IDX_LBN 16; */ 125 /* defined as ERF_GZ_IDX_WIDTH 16 */ 126 #define ERF_GZ_RING_ID_LBN 0 127 #define ERF_GZ_RING_ID_WIDTH 16 128 129 130 /* 131 * EVQ_TMR(32bit): 132 * EVQ timer control 133 */ 134 135 #define ER_GZ_EVQ_TMR_OFST 0x00000104 136 /* rhead=rhead_host_regs */ 137 #define ER_GZ_EVQ_TMR_STEP 65536 138 #define ER_GZ_EVQ_TMR_ROWS 1024 139 #define ER_GZ_EVQ_TMR_RESET 0x0 140 141 142 143 144 /* 145 * EVQ_UNSOL_CREDIT_GRANT_SEQ(32bit): 146 * Grant credits for unsolicited events. 147 */ 148 149 #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_OFST 0x00000108 150 /* rhead=rhead_host_regs */ 151 #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_STEP 65536 152 #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_ROWS 1024 153 #define ER_GZ_EVQ_UNSOL_CREDIT_GRANT_SEQ_RESET 0x0 154 155 156 157 158 /* 159 * EVQ_DESC_CREDIT_GRANT_SEQ(32bit): 160 * Grant credits for descriptor proxy events. 161 */ 162 163 #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_OFST 0x00000110 164 /* rhead=rhead_host_regs */ 165 #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_STEP 65536 166 #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_ROWS 1024 167 #define ER_GZ_EVQ_DESC_CREDIT_GRANT_SEQ_RESET 0x0 168 169 170 171 172 /* 173 * RX_RING_DOORBELL(32bit): 174 * Ring Rx doorbell. 175 */ 176 177 #define ER_GZ_RX_RING_DOORBELL_OFST 0x00000180 178 /* rhead=rhead_host_regs */ 179 #define ER_GZ_RX_RING_DOORBELL_STEP 65536 180 #define ER_GZ_RX_RING_DOORBELL_ROWS 1024 181 #define ER_GZ_RX_RING_DOORBELL_RESET 0x0 182 183 184 #define ERF_GZ_RX_RING_PIDX_LBN 16 185 #define ERF_GZ_RX_RING_PIDX_WIDTH 16 186 187 188 /* 189 * TX_RING_DOORBELL(32bit): 190 * Ring Tx doorbell. 191 */ 192 193 #define ER_GZ_TX_RING_DOORBELL_OFST 0x00000200 194 /* rhead=rhead_host_regs */ 195 #define ER_GZ_TX_RING_DOORBELL_STEP 65536 196 #define ER_GZ_TX_RING_DOORBELL_ROWS 1024 197 #define ER_GZ_TX_RING_DOORBELL_RESET 0x0 198 199 200 #define ERF_GZ_TX_RING_PIDX_LBN 16 201 #define ERF_GZ_TX_RING_PIDX_WIDTH 16 202 203 204 /* 205 * TX_DESC_PUSH(128bit): 206 * Tx ring descriptor push. Reserved for future use. 207 */ 208 209 #define ER_GZ_TX_DESC_PUSH_OFST 0x00000210 210 /* rhead=rhead_host_regs */ 211 #define ER_GZ_TX_DESC_PUSH_STEP 65536 212 #define ER_GZ_TX_DESC_PUSH_ROWS 1024 213 #define ER_GZ_TX_DESC_PUSH_RESET 0x0 214 215 216 217 218 /* 219 * THE_TIME(64bit): 220 * NIC hardware time 221 */ 222 223 #define ER_GZ_THE_TIME_OFST 0x00000280 224 /* rhead=rhead_host_regs */ 225 #define ER_GZ_THE_TIME_STEP 65536 226 #define ER_GZ_THE_TIME_ROWS 1024 227 #define ER_GZ_THE_TIME_RESET 0x0 228 229 230 #define ERF_GZ_THE_TIME_SECS_LBN 32 231 #define ERF_GZ_THE_TIME_SECS_WIDTH 32 232 #define ERF_GZ_THE_TIME_NANOS_LBN 2 233 #define ERF_GZ_THE_TIME_NANOS_WIDTH 30 234 #define ERF_GZ_THE_TIME_CLOCK_IN_SYNC_LBN 1 235 #define ERF_GZ_THE_TIME_CLOCK_IN_SYNC_WIDTH 1 236 #define ERF_GZ_THE_TIME_CLOCK_IS_SET_LBN 0 237 #define ERF_GZ_THE_TIME_CLOCK_IS_SET_WIDTH 1 238 239 240 /* 241 * PARAMS_TLV_LEN(32bit): 242 * Size of design parameters area in bytes 243 */ 244 245 #define ER_GZ_PARAMS_TLV_LEN_OFST 0x00000c00 246 /* rhead=rhead_host_regs */ 247 #define ER_GZ_PARAMS_TLV_LEN_STEP 65536 248 #define ER_GZ_PARAMS_TLV_LEN_ROWS 1024 249 #define ER_GZ_PARAMS_TLV_LEN_RESET 0x0 250 251 252 253 254 /* 255 * PARAMS_TLV(8160bit): 256 * Design parameters 257 */ 258 259 #define ER_GZ_PARAMS_TLV_OFST 0x00000c04 260 /* rhead=rhead_host_regs */ 261 #define ER_GZ_PARAMS_TLV_STEP 65536 262 #define ER_GZ_PARAMS_TLV_ROWS 1024 263 #define ER_GZ_PARAMS_TLV_RESET 0x0 264 265 266 267 268 /* ES_EW_EMBEDDED_EVENT */ 269 #define ESF_GZ_EV_256_EVENT_DW0_LBN 0 270 #define ESF_GZ_EV_256_EVENT_DW0_WIDTH 32 271 #define ESF_GZ_EV_256_EVENT_DW1_LBN 32 272 #define ESF_GZ_EV_256_EVENT_DW1_WIDTH 32 273 #define ESF_GZ_EV_256_EVENT_LBN 0 274 #define ESF_GZ_EV_256_EVENT_WIDTH 64 275 #define ESE_GZ_EW_EMBEDDED_EVENT_STRUCT_SIZE 64 276 277 278 /* ES_NMMU_PAGESZ_2M_ADDR */ 279 #define ESF_GZ_NMMU_2M_PAGE_SIZE_ID_LBN 59 280 #define ESF_GZ_NMMU_2M_PAGE_SIZE_ID_WIDTH 5 281 #define ESE_GZ_NMMU_PAGE_SIZE_2M 9 282 #define ESF_GZ_NMMU_2M_PAGE_ID_DW0_LBN 21 283 #define ESF_GZ_NMMU_2M_PAGE_ID_DW0_WIDTH 32 284 #define ESF_GZ_NMMU_2M_PAGE_ID_DW1_LBN 53 285 #define ESF_GZ_NMMU_2M_PAGE_ID_DW1_WIDTH 6 286 #define ESF_GZ_NMMU_2M_PAGE_ID_LBN 21 287 #define ESF_GZ_NMMU_2M_PAGE_ID_WIDTH 38 288 #define ESF_GZ_NMMU_2M_PAGE_OFFSET_LBN 0 289 #define ESF_GZ_NMMU_2M_PAGE_OFFSET_WIDTH 21 290 #define ESE_GZ_NMMU_PAGESZ_2M_ADDR_STRUCT_SIZE 64 291 292 293 /* ES_PARAM_TLV */ 294 #define ESF_GZ_TLV_VALUE_LBN 16 295 #define ESF_GZ_TLV_VALUE_WIDTH 8 296 #define ESE_GZ_TLV_VALUE_LENMIN 8 297 #define ESE_GZ_TLV_VALUE_LENMAX 2040 298 #define ESF_GZ_TLV_LEN_LBN 8 299 #define ESF_GZ_TLV_LEN_WIDTH 8 300 #define ESF_GZ_TLV_TYPE_LBN 0 301 #define ESF_GZ_TLV_TYPE_WIDTH 8 302 #define ESE_GZ_DP_NMMU_GROUP_SIZE 5 303 #define ESE_GZ_DP_EVQ_UNSOL_CREDIT_SEQ_BITS 4 304 #define ESE_GZ_DP_TX_EV_NUM_DESCS_BITS 3 305 #define ESE_GZ_DP_RX_EV_NUM_PACKETS_BITS 2 306 #define ESE_GZ_DP_PARTIAL_TSTAMP_SUB_NANO_BITS 1 307 #define ESE_GZ_DP_PAD 0 308 #define ESE_GZ_PARAM_TLV_STRUCT_SIZE 24 309 310 311 /* ES_PCI_EXPRESS_XCAP_HDR */ 312 #define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_LBN 20 313 #define ESF_GZ_PCI_EXPRESS_XCAP_NEXT_WIDTH 12 314 #define ESF_GZ_PCI_EXPRESS_XCAP_VER_LBN 16 315 #define ESF_GZ_PCI_EXPRESS_XCAP_VER_WIDTH 4 316 #define ESE_GZ_PCI_EXPRESS_XCAP_VER_VSEC 1 317 #define ESF_GZ_PCI_EXPRESS_XCAP_ID_LBN 0 318 #define ESF_GZ_PCI_EXPRESS_XCAP_ID_WIDTH 16 319 #define ESE_GZ_PCI_EXPRESS_XCAP_ID_VNDR 0xb 320 #define ESE_GZ_PCI_EXPRESS_XCAP_HDR_STRUCT_SIZE 32 321 322 323 /* ES_RHEAD_BASE_EVENT */ 324 #define ESF_GZ_E_TYPE_LBN 60 325 #define ESF_GZ_E_TYPE_WIDTH 4 326 #define ESF_GZ_EV_EVQ_PHASE_LBN 59 327 #define ESF_GZ_EV_EVQ_PHASE_WIDTH 1 328 #define ESE_GZ_RHEAD_BASE_EVENT_STRUCT_SIZE 64 329 330 331 /* ES_RHEAD_EW_EVENT */ 332 #define ESF_GZ_EV_256_EV32_PHASE_LBN 255 333 #define ESF_GZ_EV_256_EV32_PHASE_WIDTH 1 334 #define ESF_GZ_EV_256_EV32_TYPE_LBN 251 335 #define ESF_GZ_EV_256_EV32_TYPE_WIDTH 4 336 #define ESE_GZ_EF100_EVEW_VIRTQ_DESC 2 337 #define ESE_GZ_EF100_EVEW_TXQ_DESC 1 338 #define ESE_GZ_EF100_EVEW_64BIT 0 339 #define ESE_GZ_RHEAD_EW_EVENT_STRUCT_SIZE 256 340 341 342 /* ES_RX_DESC */ 343 #define ESF_GZ_RX_BUF_ADDR_DW0_LBN 0 344 #define ESF_GZ_RX_BUF_ADDR_DW0_WIDTH 32 345 #define ESF_GZ_RX_BUF_ADDR_DW1_LBN 32 346 #define ESF_GZ_RX_BUF_ADDR_DW1_WIDTH 32 347 #define ESF_GZ_RX_BUF_ADDR_LBN 0 348 #define ESF_GZ_RX_BUF_ADDR_WIDTH 64 349 #define ESE_GZ_RX_DESC_STRUCT_SIZE 64 350 351 352 /* ES_TXQ_DESC_PROXY_EVENT */ 353 #define ESF_GZ_EV_TXQ_DP_VI_ID_LBN 128 354 #define ESF_GZ_EV_TXQ_DP_VI_ID_WIDTH 16 355 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW0_LBN 0 356 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW0_WIDTH 32 357 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW1_LBN 32 358 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW1_WIDTH 32 359 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW2_LBN 64 360 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW2_WIDTH 32 361 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW3_LBN 96 362 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_DW3_WIDTH 32 363 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_LBN 0 364 #define ESF_GZ_EV_TXQ_DP_TXQ_DESC_WIDTH 128 365 #define ESE_GZ_TXQ_DESC_PROXY_EVENT_STRUCT_SIZE 144 366 367 368 /* ES_TX_DESC_TYPE */ 369 #define ESF_GZ_TX_DESC_TYPE_LBN 124 370 #define ESF_GZ_TX_DESC_TYPE_WIDTH 4 371 #define ESE_GZ_TX_DESC_TYPE_DESC2CMPT 7 372 #define ESE_GZ_TX_DESC_TYPE_MEM2MEM 4 373 #define ESE_GZ_TX_DESC_TYPE_SEG 3 374 #define ESE_GZ_TX_DESC_TYPE_TSO 2 375 #define ESE_GZ_TX_DESC_TYPE_PREFIX 1 376 #define ESE_GZ_TX_DESC_TYPE_SEND 0 377 #define ESE_GZ_TX_DESC_TYPE_STRUCT_SIZE 128 378 379 380 /* ES_VIRTQ_DESC_PROXY_EVENT */ 381 #define ESF_GZ_EV_VQ_DP_AVAIL_ENTRY_LBN 144 382 #define ESF_GZ_EV_VQ_DP_AVAIL_ENTRY_WIDTH 16 383 #define ESF_GZ_EV_VQ_DP_VI_ID_LBN 128 384 #define ESF_GZ_EV_VQ_DP_VI_ID_WIDTH 16 385 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW0_LBN 0 386 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW0_WIDTH 32 387 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW1_LBN 32 388 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW1_WIDTH 32 389 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW2_LBN 64 390 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW2_WIDTH 32 391 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW3_LBN 96 392 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_DW3_WIDTH 32 393 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_LBN 0 394 #define ESF_GZ_EV_VQ_DP_VIRTQ_DESC_WIDTH 128 395 #define ESE_GZ_VIRTQ_DESC_PROXY_EVENT_STRUCT_SIZE 160 396 397 398 /* ES_XIL_CFGBAR_TBL_ENTRY */ 399 #define ESF_GZ_CFGBAR_CONT_CAP_OFF_HI_LBN 96 400 #define ESF_GZ_CFGBAR_CONT_CAP_OFF_HI_WIDTH 32 401 #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_DW0_LBN 68 402 #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_DW0_WIDTH 32 403 #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_DW1_LBN 100 404 #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_DW1_WIDTH 28 405 #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_LBN 68 406 #define ESF_GZ_CFGBAR_CONT_CAP_OFFSET_WIDTH 60 407 #define ESE_GZ_CONT_CAP_OFFSET_BYTES_SHIFT 4 408 #define ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_LBN 67 409 #define ESF_GZ_CFGBAR_EF100_FUNC_CTL_WIN_OFF_WIDTH 29 410 #define ESE_GZ_EF100_FUNC_CTL_WIN_OFF_SHIFT 4 411 #define ESF_GZ_CFGBAR_CONT_CAP_OFF_LO_LBN 68 412 #define ESF_GZ_CFGBAR_CONT_CAP_OFF_LO_WIDTH 28 413 #define ESF_GZ_CFGBAR_CONT_CAP_RSV_LBN 67 414 #define ESF_GZ_CFGBAR_CONT_CAP_RSV_WIDTH 1 415 #define ESF_GZ_CFGBAR_EF100_BAR_LBN 64 416 #define ESF_GZ_CFGBAR_EF100_BAR_WIDTH 3 417 #define ESE_GZ_CFGBAR_EF100_BAR_NUM_INVALID 7 418 #define ESE_GZ_CFGBAR_EF100_BAR_NUM_EXPANSION_ROM 6 419 #define ESF_GZ_CFGBAR_CONT_CAP_BAR_LBN 64 420 #define ESF_GZ_CFGBAR_CONT_CAP_BAR_WIDTH 3 421 #define ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_INVALID 7 422 #define ESE_GZ_CFGBAR_CONT_CAP_BAR_NUM_EXPANSION_ROM 6 423 #define ESF_GZ_CFGBAR_ENTRY_SIZE_LBN 32 424 #define ESF_GZ_CFGBAR_ENTRY_SIZE_WIDTH 32 425 #define ESE_GZ_CFGBAR_ENTRY_SIZE_EF100 12 426 #define ESE_GZ_CFGBAR_ENTRY_HEADER_SIZE 8 427 #define ESF_GZ_CFGBAR_ENTRY_LAST_LBN 28 428 #define ESF_GZ_CFGBAR_ENTRY_LAST_WIDTH 1 429 #define ESF_GZ_CFGBAR_ENTRY_REV_LBN 20 430 #define ESF_GZ_CFGBAR_ENTRY_REV_WIDTH 8 431 #define ESE_GZ_CFGBAR_ENTRY_REV_EF100 0 432 #define ESF_GZ_CFGBAR_ENTRY_FORMAT_LBN 0 433 #define ESF_GZ_CFGBAR_ENTRY_FORMAT_WIDTH 20 434 #define ESE_GZ_CFGBAR_ENTRY_LAST 0xfffff 435 #define ESE_GZ_CFGBAR_ENTRY_CONT_CAP_ADDR 0xffffe 436 #define ESE_GZ_CFGBAR_ENTRY_EF100 0xef100 437 #define ESE_GZ_XIL_CFGBAR_TBL_ENTRY_STRUCT_SIZE 128 438 439 440 /* ES_XIL_CFGBAR_VSEC */ 441 #define ESF_GZ_VSEC_TBL_OFF_HI_LBN 64 442 #define ESF_GZ_VSEC_TBL_OFF_HI_WIDTH 32 443 #define ESE_GZ_VSEC_TBL_OFF_HI_BYTES_SHIFT 32 444 #define ESF_GZ_VSEC_TBL_OFF_LO_LBN 36 445 #define ESF_GZ_VSEC_TBL_OFF_LO_WIDTH 28 446 #define ESE_GZ_VSEC_TBL_OFF_LO_BYTES_SHIFT 4 447 #define ESF_GZ_VSEC_TBL_BAR_LBN 32 448 #define ESF_GZ_VSEC_TBL_BAR_WIDTH 4 449 #define ESE_GZ_VSEC_BAR_NUM_INVALID 7 450 #define ESE_GZ_VSEC_BAR_NUM_EXPANSION_ROM 6 451 #define ESF_GZ_VSEC_LEN_LBN 20 452 #define ESF_GZ_VSEC_LEN_WIDTH 12 453 #define ESE_GZ_VSEC_LEN_HIGH_OFFT 16 454 #define ESE_GZ_VSEC_LEN_MIN 12 455 #define ESF_GZ_VSEC_VER_LBN 16 456 #define ESF_GZ_VSEC_VER_WIDTH 4 457 #define ESE_GZ_VSEC_VER_XIL_CFGBAR 0 458 #define ESF_GZ_VSEC_ID_LBN 0 459 #define ESF_GZ_VSEC_ID_WIDTH 16 460 #define ESE_GZ_XILINX_VSEC_ID 0x20 461 #define ESE_GZ_XIL_CFGBAR_VSEC_STRUCT_SIZE 96 462 463 464 /* ES_addr_spc */ 465 #define ESF_GZ_ADDR_SPC_FORMAT_1_FUNCTION_LBN 28 466 #define ESF_GZ_ADDR_SPC_FORMAT_1_FUNCTION_WIDTH 8 467 #define ESF_GZ_ADDR_SPC_FORMAT_2_FUNCTION_LBN 24 468 #define ESF_GZ_ADDR_SPC_FORMAT_2_FUNCTION_WIDTH 12 469 #define ESF_GZ_ADDR_SPC_FORMAT_1_PROFILE_ID_LBN 24 470 #define ESF_GZ_ADDR_SPC_FORMAT_1_PROFILE_ID_WIDTH 4 471 #define ESF_GZ_ADDR_SPC_PASID_LBN 2 472 #define ESF_GZ_ADDR_SPC_PASID_WIDTH 22 473 #define ESF_GZ_ADDR_SPC_FORMAT_LBN 0 474 #define ESF_GZ_ADDR_SPC_FORMAT_WIDTH 2 475 #define ESE_GZ_ADDR_SPC_FORMAT_1 3 476 #define ESF_GZ_ADDR_SPC_FORMAT_2_PROFILE_ID_IDX_LBN 0 477 #define ESF_GZ_ADDR_SPC_FORMAT_2_PROFILE_ID_IDX_WIDTH 2 478 #define ESE_GZ_ADDR_SPC_STRUCT_SIZE 36 479 480 481 /* ES_rh_egres_hclass */ 482 #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_LBN 15 483 #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L4_CSUM_WIDTH 1 484 #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_LBN 13 485 #define ESF_GZ_RX_PREFIX_HCLASS_TUN_OUTER_L3_CLASS_WIDTH 2 486 #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_LBN 12 487 #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CSUM_WIDTH 1 488 #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_LBN 10 489 #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L4_CLASS_WIDTH 2 490 #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_LBN 8 491 #define ESF_GZ_RX_PREFIX_HCLASS_NT_OR_INNER_L3_CLASS_WIDTH 2 492 #define ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_LBN 5 493 #define ESF_GZ_RX_PREFIX_HCLASS_TUNNEL_CLASS_WIDTH 3 494 #define ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_LBN 3 495 #define ESF_GZ_RX_PREFIX_HCLASS_L2_N_VLAN_WIDTH 2 496 #define ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_LBN 2 497 #define ESF_GZ_RX_PREFIX_HCLASS_L2_CLASS_WIDTH 1 498 #define ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_LBN 0 499 #define ESF_GZ_RX_PREFIX_HCLASS_L2_STATUS_WIDTH 2 500 #define ESE_GZ_RH_EGRES_HCLASS_STRUCT_SIZE 16 501 502 503 /* ES_sf_driver */ 504 #define ESF_GZ_DRIVER_E_TYPE_LBN 60 505 #define ESF_GZ_DRIVER_E_TYPE_WIDTH 4 506 #define ESF_GZ_DRIVER_PHASE_LBN 59 507 #define ESF_GZ_DRIVER_PHASE_WIDTH 1 508 #define ESF_GZ_DRIVER_DATA_DW0_LBN 0 509 #define ESF_GZ_DRIVER_DATA_DW0_WIDTH 32 510 #define ESF_GZ_DRIVER_DATA_DW1_LBN 32 511 #define ESF_GZ_DRIVER_DATA_DW1_WIDTH 27 512 #define ESF_GZ_DRIVER_DATA_LBN 0 513 #define ESF_GZ_DRIVER_DATA_WIDTH 59 514 #define ESE_GZ_SF_DRIVER_STRUCT_SIZE 64 515 516 517 /* ES_sf_ev_rsvd */ 518 #define ESF_GZ_EV_RSVD_TBD_NEXT_LBN 34 519 #define ESF_GZ_EV_RSVD_TBD_NEXT_WIDTH 3 520 #define ESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_LBN 30 521 #define ESF_GZ_EV_RSVD_EVENT_GEN_FLAGS_WIDTH 4 522 #define ESF_GZ_EV_RSVD_SRC_QID_LBN 18 523 #define ESF_GZ_EV_RSVD_SRC_QID_WIDTH 12 524 #define ESF_GZ_EV_RSVD_SEQ_NUM_LBN 2 525 #define ESF_GZ_EV_RSVD_SEQ_NUM_WIDTH 16 526 #define ESF_GZ_EV_RSVD_TBD_LBN 0 527 #define ESF_GZ_EV_RSVD_TBD_WIDTH 2 528 #define ESE_GZ_SF_EV_RSVD_STRUCT_SIZE 37 529 530 531 /* ES_sf_flush_evnt */ 532 #define ESF_GZ_EV_FLSH_E_TYPE_LBN 60 533 #define ESF_GZ_EV_FLSH_E_TYPE_WIDTH 4 534 #define ESF_GZ_EV_FLSH_PHASE_LBN 59 535 #define ESF_GZ_EV_FLSH_PHASE_WIDTH 1 536 #define ESF_GZ_EV_FLSH_SUB_TYPE_LBN 53 537 #define ESF_GZ_EV_FLSH_SUB_TYPE_WIDTH 6 538 #define ESF_GZ_EV_FLSH_RSVD_DW0_LBN 10 539 #define ESF_GZ_EV_FLSH_RSVD_DW0_WIDTH 32 540 #define ESF_GZ_EV_FLSH_RSVD_DW1_LBN 42 541 #define ESF_GZ_EV_FLSH_RSVD_DW1_WIDTH 11 542 #define ESF_GZ_EV_FLSH_RSVD_LBN 10 543 #define ESF_GZ_EV_FLSH_RSVD_WIDTH 43 544 #define ESF_GZ_EV_FLSH_LABEL_LBN 4 545 #define ESF_GZ_EV_FLSH_LABEL_WIDTH 6 546 #define ESF_GZ_EV_FLSH_FLUSH_TYPE_LBN 0 547 #define ESF_GZ_EV_FLSH_FLUSH_TYPE_WIDTH 4 548 #define ESE_GZ_SF_FLUSH_EVNT_STRUCT_SIZE 64 549 550 551 /* ES_sf_rx_pkts */ 552 #define ESF_GZ_EV_RXPKTS_E_TYPE_LBN 60 553 #define ESF_GZ_EV_RXPKTS_E_TYPE_WIDTH 4 554 #define ESF_GZ_EV_RXPKTS_PHASE_LBN 59 555 #define ESF_GZ_EV_RXPKTS_PHASE_WIDTH 1 556 #define ESF_GZ_EV_RXPKTS_RSVD_DW0_LBN 22 557 #define ESF_GZ_EV_RXPKTS_RSVD_DW0_WIDTH 32 558 #define ESF_GZ_EV_RXPKTS_RSVD_DW1_LBN 54 559 #define ESF_GZ_EV_RXPKTS_RSVD_DW1_WIDTH 5 560 #define ESF_GZ_EV_RXPKTS_RSVD_LBN 22 561 #define ESF_GZ_EV_RXPKTS_RSVD_WIDTH 37 562 #define ESF_GZ_EV_RXPKTS_Q_LABEL_LBN 16 563 #define ESF_GZ_EV_RXPKTS_Q_LABEL_WIDTH 6 564 #define ESF_GZ_EV_RXPKTS_NUM_PKT_LBN 0 565 #define ESF_GZ_EV_RXPKTS_NUM_PKT_WIDTH 16 566 #define ESE_GZ_SF_RX_PKTS_STRUCT_SIZE 64 567 568 569 /* ES_sf_rx_prefix */ 570 #define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_LBN 160 571 #define ESF_GZ_RX_PREFIX_VLAN_STRIP_TCI_WIDTH 16 572 #define ESF_GZ_RX_PREFIX_CSUM_FRAME_LBN 144 573 #define ESF_GZ_RX_PREFIX_CSUM_FRAME_WIDTH 16 574 #define ESF_GZ_RX_PREFIX_INGRESS_MPORT_LBN 128 575 #define ESF_GZ_RX_PREFIX_INGRESS_MPORT_WIDTH 16 576 #define ESF_GZ_RX_PREFIX_USER_MARK_LBN 96 577 #define ESF_GZ_RX_PREFIX_USER_MARK_WIDTH 32 578 #define ESF_GZ_RX_PREFIX_RSS_HASH_LBN 64 579 #define ESF_GZ_RX_PREFIX_RSS_HASH_WIDTH 32 580 #define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_LBN 34 581 #define ESF_GZ_RX_PREFIX_PARTIAL_TSTAMP_WIDTH 30 582 #define ESF_GZ_RX_PREFIX_VSWITCH_STATUS_LBN 33 583 #define ESF_GZ_RX_PREFIX_VSWITCH_STATUS_WIDTH 1 584 #define ESF_GZ_RX_PREFIX_VLAN_STRIPPED_LBN 32 585 #define ESF_GZ_RX_PREFIX_VLAN_STRIPPED_WIDTH 1 586 #define ESF_GZ_RX_PREFIX_CLASS_LBN 16 587 #define ESF_GZ_RX_PREFIX_CLASS_WIDTH 16 588 #define ESF_GZ_RX_PREFIX_USER_FLAG_LBN 15 589 #define ESF_GZ_RX_PREFIX_USER_FLAG_WIDTH 1 590 #define ESF_GZ_RX_PREFIX_RSS_HASH_VALID_LBN 14 591 #define ESF_GZ_RX_PREFIX_RSS_HASH_VALID_WIDTH 1 592 #define ESF_GZ_RX_PREFIX_LENGTH_LBN 0 593 #define ESF_GZ_RX_PREFIX_LENGTH_WIDTH 14 594 #define ESE_GZ_SF_RX_PREFIX_STRUCT_SIZE 176 595 596 597 /* ES_sf_rxtx_generic */ 598 #define ESF_GZ_EV_BARRIER_LBN 167 599 #define ESF_GZ_EV_BARRIER_WIDTH 1 600 #define ESF_GZ_EV_RSVD_DW0_LBN 130 601 #define ESF_GZ_EV_RSVD_DW0_WIDTH 32 602 #define ESF_GZ_EV_RSVD_DW1_LBN 162 603 #define ESF_GZ_EV_RSVD_DW1_WIDTH 5 604 #define ESF_GZ_EV_RSVD_LBN 130 605 #define ESF_GZ_EV_RSVD_WIDTH 37 606 #define ESF_GZ_EV_DPRXY_LBN 129 607 #define ESF_GZ_EV_DPRXY_WIDTH 1 608 #define ESF_GZ_EV_VIRTIO_LBN 128 609 #define ESF_GZ_EV_VIRTIO_WIDTH 1 610 #define ESF_GZ_EV_COUNT_DW0_LBN 0 611 #define ESF_GZ_EV_COUNT_DW0_WIDTH 32 612 #define ESF_GZ_EV_COUNT_DW1_LBN 32 613 #define ESF_GZ_EV_COUNT_DW1_WIDTH 32 614 #define ESF_GZ_EV_COUNT_DW2_LBN 64 615 #define ESF_GZ_EV_COUNT_DW2_WIDTH 32 616 #define ESF_GZ_EV_COUNT_DW3_LBN 96 617 #define ESF_GZ_EV_COUNT_DW3_WIDTH 32 618 #define ESF_GZ_EV_COUNT_LBN 0 619 #define ESF_GZ_EV_COUNT_WIDTH 128 620 #define ESE_GZ_SF_RXTX_GENERIC_STRUCT_SIZE 168 621 622 623 /* ES_sf_ts_stamp */ 624 #define ESF_GZ_EV_TS_E_TYPE_LBN 60 625 #define ESF_GZ_EV_TS_E_TYPE_WIDTH 4 626 #define ESF_GZ_EV_TS_PHASE_LBN 59 627 #define ESF_GZ_EV_TS_PHASE_WIDTH 1 628 #define ESF_GZ_EV_TS_RSVD_LBN 56 629 #define ESF_GZ_EV_TS_RSVD_WIDTH 3 630 #define ESF_GZ_EV_TS_STATUS_LBN 54 631 #define ESF_GZ_EV_TS_STATUS_WIDTH 2 632 #define ESF_GZ_EV_TS_Q_LABEL_LBN 48 633 #define ESF_GZ_EV_TS_Q_LABEL_WIDTH 6 634 #define ESF_GZ_EV_TS_DESC_ID_LBN 32 635 #define ESF_GZ_EV_TS_DESC_ID_WIDTH 16 636 #define ESF_GZ_EV_TS_PARTIAL_STAMP_LBN 0 637 #define ESF_GZ_EV_TS_PARTIAL_STAMP_WIDTH 32 638 #define ESE_GZ_SF_TS_STAMP_STRUCT_SIZE 64 639 640 641 /* ES_sf_tx_cmplt */ 642 #define ESF_GZ_EV_TXCMPL_E_TYPE_LBN 60 643 #define ESF_GZ_EV_TXCMPL_E_TYPE_WIDTH 4 644 #define ESF_GZ_EV_TXCMPL_PHASE_LBN 59 645 #define ESF_GZ_EV_TXCMPL_PHASE_WIDTH 1 646 #define ESF_GZ_EV_TXCMPL_RSVD_DW0_LBN 22 647 #define ESF_GZ_EV_TXCMPL_RSVD_DW0_WIDTH 32 648 #define ESF_GZ_EV_TXCMPL_RSVD_DW1_LBN 54 649 #define ESF_GZ_EV_TXCMPL_RSVD_DW1_WIDTH 5 650 #define ESF_GZ_EV_TXCMPL_RSVD_LBN 22 651 #define ESF_GZ_EV_TXCMPL_RSVD_WIDTH 37 652 #define ESF_GZ_EV_TXCMPL_Q_LABEL_LBN 16 653 #define ESF_GZ_EV_TXCMPL_Q_LABEL_WIDTH 6 654 #define ESF_GZ_EV_TXCMPL_NUM_DESC_LBN 0 655 #define ESF_GZ_EV_TXCMPL_NUM_DESC_WIDTH 16 656 #define ESE_GZ_SF_TX_CMPLT_STRUCT_SIZE 64 657 658 659 /* ES_sf_tx_desc2cmpt_dsc_fmt */ 660 #define ESF_GZ_D2C_TGT_VI_ID_LBN 108 661 #define ESF_GZ_D2C_TGT_VI_ID_WIDTH 16 662 #define ESF_GZ_D2C_CMPT2_LBN 107 663 #define ESF_GZ_D2C_CMPT2_WIDTH 1 664 #define ESF_GZ_D2C_ABS_VI_ID_LBN 106 665 #define ESF_GZ_D2C_ABS_VI_ID_WIDTH 1 666 #define ESF_GZ_D2C_ORDERED_LBN 105 667 #define ESF_GZ_D2C_ORDERED_WIDTH 1 668 #define ESF_GZ_D2C_SKIP_N_LBN 97 669 #define ESF_GZ_D2C_SKIP_N_WIDTH 8 670 #define ESF_GZ_D2C_RSVD_DW0_LBN 64 671 #define ESF_GZ_D2C_RSVD_DW0_WIDTH 32 672 #define ESF_GZ_D2C_RSVD_DW1_LBN 96 673 #define ESF_GZ_D2C_RSVD_DW1_WIDTH 1 674 #define ESF_GZ_D2C_RSVD_LBN 64 675 #define ESF_GZ_D2C_RSVD_WIDTH 33 676 #define ESF_GZ_D2C_COMPLETION_DW0_LBN 0 677 #define ESF_GZ_D2C_COMPLETION_DW0_WIDTH 32 678 #define ESF_GZ_D2C_COMPLETION_DW1_LBN 32 679 #define ESF_GZ_D2C_COMPLETION_DW1_WIDTH 32 680 #define ESF_GZ_D2C_COMPLETION_LBN 0 681 #define ESF_GZ_D2C_COMPLETION_WIDTH 64 682 #define ESE_GZ_SF_TX_DESC2CMPT_DSC_FMT_STRUCT_SIZE 124 683 684 685 /* ES_sf_tx_mem2mem_dsc_fmt */ 686 #define ESF_GZ_M2M_ADDR_SPC_EN_LBN 123 687 #define ESF_GZ_M2M_ADDR_SPC_EN_WIDTH 1 688 #define ESF_GZ_M2M_TRANSLATE_ADDR_LBN 122 689 #define ESF_GZ_M2M_TRANSLATE_ADDR_WIDTH 1 690 #define ESF_GZ_M2M_RSVD_LBN 120 691 #define ESF_GZ_M2M_RSVD_WIDTH 2 692 #define ESF_GZ_M2M_ADDR_SPC_ID_DW0_LBN 84 693 #define ESF_GZ_M2M_ADDR_SPC_ID_DW0_WIDTH 32 694 #define ESF_GZ_M2M_ADDR_SPC_ID_DW1_LBN 116 695 #define ESF_GZ_M2M_ADDR_SPC_ID_DW1_WIDTH 4 696 #define ESF_GZ_M2M_ADDR_SPC_ID_LBN 84 697 #define ESF_GZ_M2M_ADDR_SPC_ID_WIDTH 36 698 #define ESF_GZ_M2M_LEN_MINUS_1_LBN 64 699 #define ESF_GZ_M2M_LEN_MINUS_1_WIDTH 20 700 #define ESF_GZ_M2M_ADDR_DW0_LBN 0 701 #define ESF_GZ_M2M_ADDR_DW0_WIDTH 32 702 #define ESF_GZ_M2M_ADDR_DW1_LBN 32 703 #define ESF_GZ_M2M_ADDR_DW1_WIDTH 32 704 #define ESF_GZ_M2M_ADDR_LBN 0 705 #define ESF_GZ_M2M_ADDR_WIDTH 64 706 #define ESE_GZ_SF_TX_MEM2MEM_DSC_FMT_STRUCT_SIZE 124 707 708 709 /* ES_sf_tx_ovr_dsc_fmt */ 710 #define ESF_GZ_TX_PREFIX_MARK_EN_LBN 123 711 #define ESF_GZ_TX_PREFIX_MARK_EN_WIDTH 1 712 #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_LBN 122 713 #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_EN_WIDTH 1 714 #define ESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_LBN 121 715 #define ESF_GZ_TX_PREFIX_INLINE_CAPSULE_META_WIDTH 1 716 #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_LBN 120 717 #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_EN_WIDTH 1 718 #define ESF_GZ_TX_PREFIX_RSRVD_DW0_LBN 64 719 #define ESF_GZ_TX_PREFIX_RSRVD_DW0_WIDTH 32 720 #define ESF_GZ_TX_PREFIX_RSRVD_DW1_LBN 96 721 #define ESF_GZ_TX_PREFIX_RSRVD_DW1_WIDTH 24 722 #define ESF_GZ_TX_PREFIX_RSRVD_LBN 64 723 #define ESF_GZ_TX_PREFIX_RSRVD_WIDTH 56 724 #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_LBN 48 725 #define ESF_GZ_TX_PREFIX_EGRESS_MPORT_WIDTH 16 726 #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_LBN 32 727 #define ESF_GZ_TX_PREFIX_INGRESS_MPORT_WIDTH 16 728 #define ESF_GZ_TX_PREFIX_MARK_LBN 0 729 #define ESF_GZ_TX_PREFIX_MARK_WIDTH 32 730 #define ESE_GZ_SF_TX_OVR_DSC_FMT_STRUCT_SIZE 124 731 732 733 /* ES_sf_tx_seg_dsc_fmt */ 734 #define ESF_GZ_TX_SEG_ADDR_SPC_EN_LBN 123 735 #define ESF_GZ_TX_SEG_ADDR_SPC_EN_WIDTH 1 736 #define ESF_GZ_TX_SEG_TRANSLATE_ADDR_LBN 122 737 #define ESF_GZ_TX_SEG_TRANSLATE_ADDR_WIDTH 1 738 #define ESF_GZ_TX_SEG_RSVD2_LBN 120 739 #define ESF_GZ_TX_SEG_RSVD2_WIDTH 2 740 #define ESF_GZ_TX_SEG_ADDR_SPC_ID_DW0_LBN 84 741 #define ESF_GZ_TX_SEG_ADDR_SPC_ID_DW0_WIDTH 32 742 #define ESF_GZ_TX_SEG_ADDR_SPC_ID_DW1_LBN 116 743 #define ESF_GZ_TX_SEG_ADDR_SPC_ID_DW1_WIDTH 4 744 #define ESF_GZ_TX_SEG_ADDR_SPC_ID_LBN 84 745 #define ESF_GZ_TX_SEG_ADDR_SPC_ID_WIDTH 36 746 #define ESF_GZ_TX_SEG_RSVD_LBN 80 747 #define ESF_GZ_TX_SEG_RSVD_WIDTH 4 748 #define ESF_GZ_TX_SEG_LEN_LBN 64 749 #define ESF_GZ_TX_SEG_LEN_WIDTH 16 750 #define ESF_GZ_TX_SEG_ADDR_DW0_LBN 0 751 #define ESF_GZ_TX_SEG_ADDR_DW0_WIDTH 32 752 #define ESF_GZ_TX_SEG_ADDR_DW1_LBN 32 753 #define ESF_GZ_TX_SEG_ADDR_DW1_WIDTH 32 754 #define ESF_GZ_TX_SEG_ADDR_LBN 0 755 #define ESF_GZ_TX_SEG_ADDR_WIDTH 64 756 #define ESE_GZ_SF_TX_SEG_DSC_FMT_STRUCT_SIZE 124 757 758 759 /* ES_sf_tx_std_dsc_fmt */ 760 #define ESF_GZ_TX_SEND_VLAN_INSERT_TCI_LBN 108 761 #define ESF_GZ_TX_SEND_VLAN_INSERT_TCI_WIDTH 16 762 #define ESF_GZ_TX_SEND_VLAN_INSERT_EN_LBN 107 763 #define ESF_GZ_TX_SEND_VLAN_INSERT_EN_WIDTH 1 764 #define ESF_GZ_TX_SEND_TSTAMP_REQ_LBN 106 765 #define ESF_GZ_TX_SEND_TSTAMP_REQ_WIDTH 1 766 #define ESF_GZ_TX_SEND_CSO_OUTER_L4_LBN 105 767 #define ESF_GZ_TX_SEND_CSO_OUTER_L4_WIDTH 1 768 #define ESF_GZ_TX_SEND_CSO_OUTER_L3_LBN 104 769 #define ESF_GZ_TX_SEND_CSO_OUTER_L3_WIDTH 1 770 #define ESF_GZ_TX_SEND_CSO_INNER_L3_LBN 101 771 #define ESF_GZ_TX_SEND_CSO_INNER_L3_WIDTH 3 772 #define ESF_GZ_TX_SEND_RSVD_LBN 99 773 #define ESF_GZ_TX_SEND_RSVD_WIDTH 2 774 #define ESF_GZ_TX_SEND_CSO_PARTIAL_EN_LBN 97 775 #define ESF_GZ_TX_SEND_CSO_PARTIAL_EN_WIDTH 2 776 #define ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_LBN 92 777 #define ESF_GZ_TX_SEND_CSO_PARTIAL_CSUM_W_WIDTH 5 778 #define ESF_GZ_TX_SEND_CSO_PARTIAL_START_W_LBN 83 779 #define ESF_GZ_TX_SEND_CSO_PARTIAL_START_W_WIDTH 9 780 #define ESF_GZ_TX_SEND_NUM_SEGS_LBN 78 781 #define ESF_GZ_TX_SEND_NUM_SEGS_WIDTH 5 782 #define ESF_GZ_TX_SEND_LEN_LBN 64 783 #define ESF_GZ_TX_SEND_LEN_WIDTH 14 784 #define ESF_GZ_TX_SEND_ADDR_DW0_LBN 0 785 #define ESF_GZ_TX_SEND_ADDR_DW0_WIDTH 32 786 #define ESF_GZ_TX_SEND_ADDR_DW1_LBN 32 787 #define ESF_GZ_TX_SEND_ADDR_DW1_WIDTH 32 788 #define ESF_GZ_TX_SEND_ADDR_LBN 0 789 #define ESF_GZ_TX_SEND_ADDR_WIDTH 64 790 #define ESE_GZ_SF_TX_STD_DSC_FMT_STRUCT_SIZE 124 791 792 793 /* ES_sf_tx_tso_dsc_fmt */ 794 #define ESF_GZ_TX_TSO_VLAN_INSERT_TCI_LBN 108 795 #define ESF_GZ_TX_TSO_VLAN_INSERT_TCI_WIDTH 16 796 #define ESF_GZ_TX_TSO_VLAN_INSERT_EN_LBN 107 797 #define ESF_GZ_TX_TSO_VLAN_INSERT_EN_WIDTH 1 798 #define ESF_GZ_TX_TSO_TSTAMP_REQ_LBN 106 799 #define ESF_GZ_TX_TSO_TSTAMP_REQ_WIDTH 1 800 #define ESF_GZ_TX_TSO_CSO_OUTER_L4_LBN 105 801 #define ESF_GZ_TX_TSO_CSO_OUTER_L4_WIDTH 1 802 #define ESF_GZ_TX_TSO_CSO_OUTER_L3_LBN 104 803 #define ESF_GZ_TX_TSO_CSO_OUTER_L3_WIDTH 1 804 #define ESF_GZ_TX_TSO_CSO_INNER_L3_LBN 101 805 #define ESF_GZ_TX_TSO_CSO_INNER_L3_WIDTH 3 806 #define ESF_GZ_TX_TSO_RSVD_LBN 94 807 #define ESF_GZ_TX_TSO_RSVD_WIDTH 7 808 #define ESF_GZ_TX_TSO_CSO_INNER_L4_LBN 93 809 #define ESF_GZ_TX_TSO_CSO_INNER_L4_WIDTH 1 810 #define ESF_GZ_TX_TSO_INNER_L4_OFF_W_LBN 85 811 #define ESF_GZ_TX_TSO_INNER_L4_OFF_W_WIDTH 8 812 #define ESF_GZ_TX_TSO_INNER_L3_OFF_W_LBN 77 813 #define ESF_GZ_TX_TSO_INNER_L3_OFF_W_WIDTH 8 814 #define ESF_GZ_TX_TSO_OUTER_L4_OFF_W_LBN 69 815 #define ESF_GZ_TX_TSO_OUTER_L4_OFF_W_WIDTH 8 816 #define ESF_GZ_TX_TSO_OUTER_L3_OFF_W_LBN 64 817 #define ESF_GZ_TX_TSO_OUTER_L3_OFF_W_WIDTH 5 818 #define ESF_GZ_TX_TSO_PAYLOAD_LEN_LBN 42 819 #define ESF_GZ_TX_TSO_PAYLOAD_LEN_WIDTH 22 820 #define ESF_GZ_TX_TSO_HDR_LEN_W_LBN 34 821 #define ESF_GZ_TX_TSO_HDR_LEN_W_WIDTH 8 822 #define ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_LBN 33 823 #define ESF_GZ_TX_TSO_ED_OUTER_UDP_LEN_WIDTH 1 824 #define ESF_GZ_TX_TSO_ED_INNER_IP_LEN_LBN 32 825 #define ESF_GZ_TX_TSO_ED_INNER_IP_LEN_WIDTH 1 826 #define ESF_GZ_TX_TSO_ED_OUTER_IP_LEN_LBN 31 827 #define ESF_GZ_TX_TSO_ED_OUTER_IP_LEN_WIDTH 1 828 #define ESF_GZ_TX_TSO_ED_INNER_IP4_ID_LBN 29 829 #define ESF_GZ_TX_TSO_ED_INNER_IP4_ID_WIDTH 2 830 #define ESF_GZ_TX_TSO_ED_OUTER_IP4_ID_LBN 27 831 #define ESF_GZ_TX_TSO_ED_OUTER_IP4_ID_WIDTH 2 832 #define ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_LBN 17 833 #define ESF_GZ_TX_TSO_PAYLOAD_NUM_SEGS_WIDTH 10 834 #define ESF_GZ_TX_TSO_HDR_NUM_SEGS_LBN 14 835 #define ESF_GZ_TX_TSO_HDR_NUM_SEGS_WIDTH 3 836 #define ESF_GZ_TX_TSO_MSS_LBN 0 837 #define ESF_GZ_TX_TSO_MSS_WIDTH 14 838 #define ESE_GZ_SF_TX_TSO_DSC_FMT_STRUCT_SIZE 124 839 840 841 842 /* Enum D2VIO_MSG_OP */ 843 #define ESE_GZ_QUE_JBDNE 3 844 #define ESE_GZ_QUE_EVICT 2 845 #define ESE_GZ_QUE_EMPTY 1 846 #define ESE_GZ_NOP 0 847 848 /* Enum DESIGN_PARAMS */ 849 #define ESE_EF100_DP_GZ_RX_MAX_RUNT 17 850 #define ESE_EF100_DP_GZ_VI_STRIDES 16 851 #define ESE_EF100_DP_GZ_NMMU_PAGE_SIZES 15 852 #define ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS 14 853 #define ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN 13 854 #define ESE_EF100_DP_GZ_COMPAT 12 855 #define ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES 11 856 #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS 10 857 #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN 9 858 #define ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY 8 859 #define ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY 7 860 #define ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS 6 861 #define ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN 5 862 #define ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS 4 863 #define ESE_EF100_DP_GZ_NMMU_GROUP_SIZE 3 864 #define ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS 2 865 #define ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS 1 866 #define ESE_EF100_DP_GZ_PAD 0 867 868 /* Enum DESIGN_PARAM_DEFAULTS */ 869 #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_LEN_DEFAULT 0x3fffff 870 #define ESE_EF100_DP_GZ_TSO_MAX_NUM_FRAMES_DEFAULT 8192 871 #define ESE_EF100_DP_GZ_MEM2MEM_MAX_LEN_DEFAULT 8192 872 #define ESE_EF100_DP_GZ_RX_L4_CSUM_PROTOCOLS_DEFAULT 0x1106 873 #define ESE_EF100_DP_GZ_TSO_MAX_PAYLOAD_NUM_SEGS_DEFAULT 0x3ff 874 #define ESE_EF100_DP_GZ_RX_MAX_RUNT_DEFAULT 640 875 #define ESE_EF100_DP_GZ_EVQ_TIMER_TICK_NANOS_DEFAULT 512 876 #define ESE_EF100_DP_GZ_NMMU_PAGE_SIZES_DEFAULT 512 877 #define ESE_EF100_DP_GZ_TSO_MAX_HDR_LEN_DEFAULT 192 878 #define ESE_EF100_DP_GZ_RXQ_SIZE_GRANULARITY_DEFAULT 64 879 #define ESE_EF100_DP_GZ_TXQ_SIZE_GRANULARITY_DEFAULT 64 880 #define ESE_EF100_DP_GZ_NMMU_GROUP_SIZE_DEFAULT 32 881 #define ESE_EF100_DP_GZ_VI_STRIDES_DEFAULT 16 882 #define ESE_EF100_DP_GZ_EVQ_UNSOL_CREDIT_SEQ_BITS_DEFAULT 7 883 #define ESE_EF100_DP_GZ_TSO_MAX_HDR_NUM_SEGS_DEFAULT 4 884 #define ESE_EF100_DP_GZ_PARTIAL_TSTAMP_SUB_NANO_BITS_DEFAULT 2 885 #define ESE_EF100_DP_GZ_COMPAT_DEFAULT 0 886 887 /* Enum HOST_IF_CONSTANTS */ 888 #define ESE_GZ_FCW_LEN 0x4C 889 #define ESE_GZ_RX_PKT_PREFIX_LEN 22 890 891 /* Enum PCI_CONSTANTS */ 892 #define ESE_GZ_PCI_BASE_CONFIG_SPACE_SIZE 256 893 #define ESE_GZ_PCI_EXPRESS_XCAP_HDR_SIZE 4 894 895 /* Enum RH_DSC_TYPE */ 896 #define ESE_GZ_TX_TOMB 0xF 897 #define ESE_GZ_TX_VIO 0xE 898 #define ESE_GZ_TX_TSO_OVRRD 0x8 899 #define ESE_GZ_TX_D2CMP 0x7 900 #define ESE_GZ_TX_DATA 0x6 901 #define ESE_GZ_TX_D2M 0x5 902 #define ESE_GZ_TX_M2M 0x4 903 #define ESE_GZ_TX_SEG 0x3 904 #define ESE_GZ_TX_TSO 0x2 905 #define ESE_GZ_TX_OVRRD 0x1 906 #define ESE_GZ_TX_SEND 0x0 907 908 /* Enum RH_HCLASS_L2_CLASS */ 909 #define ESE_GZ_RH_HCLASS_L2_CLASS_E2_0123VLAN 1 910 #define ESE_GZ_RH_HCLASS_L2_CLASS_OTHER 0 911 912 /* Enum RH_HCLASS_L2_STATUS */ 913 #define ESE_GZ_RH_HCLASS_L2_STATUS_RESERVED 3 914 #define ESE_GZ_RH_HCLASS_L2_STATUS_FCS_ERR 2 915 #define ESE_GZ_RH_HCLASS_L2_STATUS_LEN_ERR 1 916 #define ESE_GZ_RH_HCLASS_L2_STATUS_OK 0 917 918 /* Enum RH_HCLASS_L3_CLASS */ 919 #define ESE_GZ_RH_HCLASS_L3_CLASS_OTHER 3 920 #define ESE_GZ_RH_HCLASS_L3_CLASS_IP6 2 921 #define ESE_GZ_RH_HCLASS_L3_CLASS_IP4BAD 1 922 #define ESE_GZ_RH_HCLASS_L3_CLASS_IP4GOOD 0 923 924 /* Enum RH_HCLASS_L4_CLASS */ 925 #define ESE_GZ_RH_HCLASS_L4_CLASS_OTHER 3 926 #define ESE_GZ_RH_HCLASS_L4_CLASS_FRAG 2 927 #define ESE_GZ_RH_HCLASS_L4_CLASS_UDP 1 928 #define ESE_GZ_RH_HCLASS_L4_CLASS_TCP 0 929 930 /* Enum RH_HCLASS_L4_CSUM */ 931 #define ESE_GZ_RH_HCLASS_L4_CSUM_GOOD 1 932 #define ESE_GZ_RH_HCLASS_L4_CSUM_BAD_OR_UNKNOWN 0 933 934 /* Enum RH_HCLASS_TUNNEL_CLASS */ 935 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_7 7 936 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_6 6 937 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_5 5 938 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_RESERVED_4 4 939 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_GENEVE 3 940 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NVGRE 2 941 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_VXLAN 1 942 #define ESE_GZ_RH_HCLASS_TUNNEL_CLASS_NONE 0 943 944 /* Enum SF_CTL_EVENT_SUBTYPE */ 945 #define ESE_GZ_EF100_CTL_EV_EVQ_TIMEOUT 0x3 946 #define ESE_GZ_EF100_CTL_EV_FLUSH 0x2 947 #define ESE_GZ_EF100_CTL_EV_TIME_SYNC 0x1 948 #define ESE_GZ_EF100_CTL_EV_UNSOL_OVERFLOW 0x0 949 950 /* Enum SF_EVENT_TYPE */ 951 #define ESE_GZ_EF100_EV_DRIVER 0x5 952 #define ESE_GZ_EF100_EV_MCDI 0x4 953 #define ESE_GZ_EF100_EV_CONTROL 0x3 954 #define ESE_GZ_EF100_EV_TX_TIMESTAMP 0x2 955 #define ESE_GZ_EF100_EV_TX_COMPLETION 0x1 956 #define ESE_GZ_EF100_EV_RX_PKTS 0x0 957 958 /* Enum SF_EW_EVENT_TYPE */ 959 #define ESE_GZ_EF100_EWEV_VIRTQ_DESC 0x2 960 #define ESE_GZ_EF100_EWEV_TXQ_DESC 0x1 961 #define ESE_GZ_EF100_EWEV_64BIT 0x0 962 963 /* Enum TX_DESC_CSO_PARTIAL_EN */ 964 #define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_TCP 2 965 #define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_UDP 1 966 #define ESE_GZ_TX_DESC_CSO_PARTIAL_EN_OFF 0 967 968 /* Enum TX_DESC_CS_INNER_L3 */ 969 #define ESE_GZ_TX_DESC_CS_INNER_L3_GENEVE 3 970 #define ESE_GZ_TX_DESC_CS_INNER_L3_NVGRE 2 971 #define ESE_GZ_TX_DESC_CS_INNER_L3_VXLAN 1 972 #define ESE_GZ_TX_DESC_CS_INNER_L3_OFF 0 973 974 /* Enum TX_DESC_IP4_ID */ 975 #define ESE_GZ_TX_DESC_IP4_ID_INC_MOD16 2 976 #define ESE_GZ_TX_DESC_IP4_ID_INC_MOD15 1 977 #define ESE_GZ_TX_DESC_IP4_ID_NO_OP 0 978 979 /* Enum VIRTIO_NET_HDR_F */ 980 #define ESE_GZ_NEEDS_CSUM 0x1 981 982 /* Enum VIRTIO_NET_HDR_GSO */ 983 #define ESE_GZ_TCPV6 0x4 984 #define ESE_GZ_UDP 0x3 985 #define ESE_GZ_TCPV4 0x1 986 #define ESE_GZ_NONE 0x0 987 /************************************************************************* 988 * NOTE: the comment line above marks the end of the autogenerated section 989 */ 990 991 992 #ifdef __cplusplus 993 } 994 #endif 995 996 #endif /* _SYS_EFX_EF100_REGS_H */ 997