1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2006-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_H 8 #define _SYS_EFX_H 9 10 #include "efx_annote.h" 11 #include "efsys.h" 12 #include "efx_types.h" 13 #include "efx_check.h" 14 #include "efx_phy_ids.h" 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #define EFX_STATIC_ASSERT(_cond) \ 21 ((void)sizeof (char[(_cond) ? 1 : -1])) 22 23 #define EFX_ARRAY_SIZE(_array) \ 24 (sizeof (_array) / sizeof ((_array)[0])) 25 26 #define EFX_FIELD_OFFSET(_type, _field) \ 27 ((size_t)&(((_type *)0)->_field)) 28 29 /* The macro expands divider twice */ 30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) 31 32 /* Round value up to the nearest power of two. */ 33 #define EFX_P2ROUNDUP(_type, _value, _align) \ 34 (-(-(_type)(_value) & -(_type)(_align))) 35 36 /* Align value down to the nearest power of two. */ 37 #define EFX_P2ALIGN(_type, _value, _align) \ 38 ((_type)(_value) & -(_type)(_align)) 39 40 /* Test if value is power of 2 aligned. */ 41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \ 42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0) 43 44 /* Return codes */ 45 46 typedef __success(return == 0) int efx_rc_t; 47 48 49 /* Chip families */ 50 51 typedef enum efx_family_e { 52 EFX_FAMILY_INVALID, 53 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 54 EFX_FAMILY_SIENA, 55 EFX_FAMILY_HUNTINGTON, 56 EFX_FAMILY_MEDFORD, 57 EFX_FAMILY_MEDFORD2, 58 EFX_FAMILY_RIVERHEAD, 59 EFX_FAMILY_NTYPES 60 } efx_family_t; 61 62 typedef enum efx_bar_type_e { 63 EFX_BAR_TYPE_MEM, 64 EFX_BAR_TYPE_IO 65 } efx_bar_type_t; 66 67 typedef struct efx_bar_region_s { 68 efx_bar_type_t ebr_type; 69 int ebr_index; 70 efsys_dma_addr_t ebr_offset; 71 efsys_dma_addr_t ebr_length; 72 } efx_bar_region_t; 73 74 /* The function is deprecated. It is used only if Riverhead is not supported. */ 75 LIBEFX_API 76 extern __checkReturn efx_rc_t 77 efx_family( 78 __in uint16_t venid, 79 __in uint16_t devid, 80 __out efx_family_t *efp, 81 __out unsigned int *membarp); 82 83 #if EFSYS_OPT_PCI 84 85 /* PCIe interface numbers for multi-host configurations. */ 86 typedef enum efx_pcie_interface_e { 87 EFX_PCIE_INTERFACE_CALLER = 1000, 88 EFX_PCIE_INTERFACE_HOST_PRIMARY, 89 EFX_PCIE_INTERFACE_NIC_EMBEDDED, 90 } efx_pcie_interface_t; 91 92 typedef struct efx_pci_ops_s { 93 /* 94 * Function for reading PCIe configuration space. 95 * 96 * espcp System-specific PCIe device handle; 97 * offset Offset inside PCIe configuration space to start reading 98 * from; 99 * edp EFX DWORD structure that should be populated by function 100 * in little-endian order; 101 * 102 * Returns status code, 0 on success, any other value on error. 103 */ 104 efx_rc_t (*epo_config_readd)(efsys_pci_config_t *espcp, 105 uint32_t offset, efx_dword_t *edp); 106 /* 107 * Function for finding PCIe memory bar handle by its index from a PCIe 108 * device handle. The found memory bar is available in read-only mode. 109 * 110 * configp System-specific PCIe device handle; 111 * index Memory bar index; 112 * memp Pointer to the found memory bar handle; 113 * 114 * Returns status code, 0 on success, any other value on error. 115 */ 116 efx_rc_t (*epo_find_mem_bar)(efsys_pci_config_t *configp, 117 int index, efsys_bar_t *memp); 118 } efx_pci_ops_t; 119 120 /* Determine EFX family and perform lookup of the function control window 121 * 122 * The function requires PCI config handle from which all memory bars can 123 * be accessed. 124 * A user of the API must be aware of memory bars indexes (not available 125 * on Windows). 126 */ 127 LIBEFX_API 128 extern __checkReturn efx_rc_t 129 efx_family_probe_bar( 130 __in uint16_t venid, 131 __in uint16_t devid, 132 __in efsys_pci_config_t *espcp, 133 __in const efx_pci_ops_t *epop, 134 __out efx_family_t *efp, 135 __out efx_bar_region_t *ebrp); 136 137 #endif /* EFSYS_OPT_PCI */ 138 139 140 #define EFX_PCI_VENID_SFC 0x1924 141 #define EFX_PCI_VENID_XILINX 0x10EE 142 143 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 144 145 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 146 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 147 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 148 149 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 150 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 151 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 152 153 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 154 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 155 156 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 157 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 158 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 159 160 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13 161 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */ 162 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */ 163 164 #define EFX_PCI_DEVID_RIVERHEAD 0x0100 165 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100 166 167 #define EFX_MEM_BAR_SIENA 2 168 169 #define EFX_MEM_BAR_HUNTINGTON_PF 2 170 #define EFX_MEM_BAR_HUNTINGTON_VF 0 171 172 #define EFX_MEM_BAR_MEDFORD_PF 2 173 #define EFX_MEM_BAR_MEDFORD_VF 0 174 175 #define EFX_MEM_BAR_MEDFORD2 0 176 177 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */ 178 #define EFX_MEM_BAR_RIVERHEAD 2 179 180 181 /* Error codes */ 182 183 enum { 184 EFX_ERR_INVALID, 185 EFX_ERR_SRAM_OOB, 186 EFX_ERR_BUFID_DC_OOB, 187 EFX_ERR_MEM_PERR, 188 EFX_ERR_RBUF_OWN, 189 EFX_ERR_TBUF_OWN, 190 EFX_ERR_RDESQ_OWN, 191 EFX_ERR_TDESQ_OWN, 192 EFX_ERR_EVQ_OWN, 193 EFX_ERR_EVFF_OFLO, 194 EFX_ERR_ILL_ADDR, 195 EFX_ERR_SRAM_PERR, 196 EFX_ERR_NCODES 197 }; 198 199 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 200 LIBEFX_API 201 extern __checkReturn uint32_t 202 efx_crc32_calculate( 203 __in uint32_t crc_init, 204 __in_ecount(length) uint8_t const *input, 205 __in int length); 206 207 208 /* Type prototypes */ 209 210 typedef struct efx_rxq_s efx_rxq_t; 211 212 /* NIC */ 213 214 typedef struct efx_nic_s efx_nic_t; 215 216 LIBEFX_API 217 extern __checkReturn efx_rc_t 218 efx_nic_create( 219 __in efx_family_t family, 220 __in efsys_identifier_t *esip, 221 __in efsys_bar_t *esbp, 222 __in uint32_t fcw_offset, 223 __in efsys_lock_t *eslp, 224 __deref_out efx_nic_t **enpp); 225 226 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */ 227 typedef enum efx_fw_variant_e { 228 EFX_FW_VARIANT_FULL_FEATURED, 229 EFX_FW_VARIANT_LOW_LATENCY, 230 EFX_FW_VARIANT_PACKED_STREAM, 231 EFX_FW_VARIANT_HIGH_TX_RATE, 232 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1, 233 EFX_FW_VARIANT_RULES_ENGINE, 234 EFX_FW_VARIANT_DPDK, 235 EFX_FW_VARIANT_DONT_CARE = 0xffffffff 236 } efx_fw_variant_t; 237 238 LIBEFX_API 239 extern __checkReturn efx_rc_t 240 efx_nic_probe( 241 __in efx_nic_t *enp, 242 __in efx_fw_variant_t efv); 243 244 LIBEFX_API 245 extern __checkReturn efx_rc_t 246 efx_nic_init( 247 __in efx_nic_t *enp); 248 249 LIBEFX_API 250 extern __checkReturn efx_rc_t 251 efx_nic_reset( 252 __in efx_nic_t *enp); 253 254 LIBEFX_API 255 extern __checkReturn boolean_t 256 efx_nic_hw_unavailable( 257 __in efx_nic_t *enp); 258 259 LIBEFX_API 260 extern void 261 efx_nic_set_hw_unavailable( 262 __in efx_nic_t *enp); 263 264 #if EFSYS_OPT_DIAG 265 266 LIBEFX_API 267 extern __checkReturn efx_rc_t 268 efx_nic_register_test( 269 __in efx_nic_t *enp); 270 271 #endif /* EFSYS_OPT_DIAG */ 272 273 LIBEFX_API 274 extern void 275 efx_nic_fini( 276 __in efx_nic_t *enp); 277 278 LIBEFX_API 279 extern void 280 efx_nic_unprobe( 281 __in efx_nic_t *enp); 282 283 LIBEFX_API 284 extern void 285 efx_nic_destroy( 286 __in efx_nic_t *enp); 287 288 #define EFX_PCIE_LINK_SPEED_GEN1 1 289 #define EFX_PCIE_LINK_SPEED_GEN2 2 290 #define EFX_PCIE_LINK_SPEED_GEN3 3 291 292 typedef enum efx_pcie_link_performance_e { 293 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 294 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 295 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 296 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 297 } efx_pcie_link_performance_t; 298 299 LIBEFX_API 300 extern __checkReturn efx_rc_t 301 efx_nic_calculate_pcie_link_bandwidth( 302 __in uint32_t pcie_link_width, 303 __in uint32_t pcie_link_gen, 304 __out uint32_t *bandwidth_mbpsp); 305 306 LIBEFX_API 307 extern __checkReturn efx_rc_t 308 efx_nic_check_pcie_link_speed( 309 __in efx_nic_t *enp, 310 __in uint32_t pcie_link_width, 311 __in uint32_t pcie_link_gen, 312 __out efx_pcie_link_performance_t *resultp); 313 314 #define EFX_MAC_ADDR_LEN 6 315 316 #if EFSYS_OPT_MCDI 317 318 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 319 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */ 320 #define WITH_MCDI_V2 1 321 #endif 322 323 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 324 325 typedef enum efx_mcdi_exception_e { 326 EFX_MCDI_EXCEPTION_MC_REBOOT, 327 EFX_MCDI_EXCEPTION_MC_BADASSERT, 328 } efx_mcdi_exception_t; 329 330 #if EFSYS_OPT_MCDI_LOGGING 331 typedef enum efx_log_msg_e { 332 EFX_LOG_INVALID, 333 EFX_LOG_MCDI_REQUEST, 334 EFX_LOG_MCDI_RESPONSE, 335 } efx_log_msg_t; 336 #endif /* EFSYS_OPT_MCDI_LOGGING */ 337 338 typedef struct efx_mcdi_transport_s { 339 void *emt_context; 340 efsys_mem_t *emt_dma_mem; 341 void (*emt_execute)(void *, efx_mcdi_req_t *); 342 void (*emt_ev_cpl)(void *); 343 void (*emt_exception)(void *, efx_mcdi_exception_t); 344 #if EFSYS_OPT_MCDI_LOGGING 345 void (*emt_logger)(void *, efx_log_msg_t, 346 void *, size_t, void *, size_t); 347 #endif /* EFSYS_OPT_MCDI_LOGGING */ 348 #if EFSYS_OPT_MCDI_PROXY_AUTH 349 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 350 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 351 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 352 void (*emt_ev_proxy_request)(void *, uint32_t); 353 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 354 } efx_mcdi_transport_t; 355 356 LIBEFX_API 357 extern __checkReturn efx_rc_t 358 efx_mcdi_init( 359 __in efx_nic_t *enp, 360 __in const efx_mcdi_transport_t *mtp); 361 362 LIBEFX_API 363 extern __checkReturn efx_rc_t 364 efx_mcdi_reboot( 365 __in efx_nic_t *enp); 366 367 LIBEFX_API 368 extern void 369 efx_mcdi_new_epoch( 370 __in efx_nic_t *enp); 371 372 LIBEFX_API 373 extern void 374 efx_mcdi_get_timeout( 375 __in efx_nic_t *enp, 376 __in efx_mcdi_req_t *emrp, 377 __out uint32_t *usec_timeoutp); 378 379 LIBEFX_API 380 extern void 381 efx_mcdi_request_start( 382 __in efx_nic_t *enp, 383 __in efx_mcdi_req_t *emrp, 384 __in boolean_t ev_cpl); 385 386 LIBEFX_API 387 extern __checkReturn boolean_t 388 efx_mcdi_request_poll( 389 __in efx_nic_t *enp); 390 391 LIBEFX_API 392 extern __checkReturn boolean_t 393 efx_mcdi_request_abort( 394 __in efx_nic_t *enp); 395 396 LIBEFX_API 397 extern __checkReturn efx_rc_t 398 efx_mcdi_get_client_handle( 399 __in efx_nic_t *enp, 400 __in efx_pcie_interface_t intf, 401 __in uint16_t pf, 402 __in uint16_t vf, 403 __out uint32_t *handle); 404 405 LIBEFX_API 406 extern __checkReturn efx_rc_t 407 efx_mcdi_get_own_client_handle( 408 __in efx_nic_t *enp, 409 __out uint32_t *handle); 410 411 LIBEFX_API 412 extern __checkReturn efx_rc_t 413 efx_mcdi_client_mac_addr_get( 414 __in efx_nic_t *enp, 415 __in uint32_t client_handle, 416 __out uint8_t addr_bytes[EFX_MAC_ADDR_LEN]); 417 418 LIBEFX_API 419 extern __checkReturn efx_rc_t 420 efx_mcdi_client_mac_addr_set( 421 __in efx_nic_t *enp, 422 __in uint32_t client_handle, 423 __in const uint8_t addr_bytes[EFX_MAC_ADDR_LEN]); 424 425 LIBEFX_API 426 extern void 427 efx_mcdi_fini( 428 __in efx_nic_t *enp); 429 430 #endif /* EFSYS_OPT_MCDI */ 431 432 /* INTR */ 433 434 #define EFX_NINTR_SIENA 1024 435 436 typedef enum efx_intr_type_e { 437 EFX_INTR_INVALID = 0, 438 EFX_INTR_LINE, 439 EFX_INTR_MESSAGE, 440 EFX_INTR_NTYPES 441 } efx_intr_type_t; 442 443 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 444 445 LIBEFX_API 446 extern __checkReturn efx_rc_t 447 efx_intr_init( 448 __in efx_nic_t *enp, 449 __in efx_intr_type_t type, 450 __in_opt efsys_mem_t *esmp); 451 452 LIBEFX_API 453 extern void 454 efx_intr_enable( 455 __in efx_nic_t *enp); 456 457 LIBEFX_API 458 extern void 459 efx_intr_disable( 460 __in efx_nic_t *enp); 461 462 LIBEFX_API 463 extern void 464 efx_intr_disable_unlocked( 465 __in efx_nic_t *enp); 466 467 #define EFX_INTR_NEVQS 32 468 469 LIBEFX_API 470 extern __checkReturn efx_rc_t 471 efx_intr_trigger( 472 __in efx_nic_t *enp, 473 __in unsigned int level); 474 475 LIBEFX_API 476 extern void 477 efx_intr_status_line( 478 __in efx_nic_t *enp, 479 __out boolean_t *fatalp, 480 __out uint32_t *maskp); 481 482 LIBEFX_API 483 extern void 484 efx_intr_status_message( 485 __in efx_nic_t *enp, 486 __in unsigned int message, 487 __out boolean_t *fatalp); 488 489 LIBEFX_API 490 extern void 491 efx_intr_fatal( 492 __in efx_nic_t *enp); 493 494 LIBEFX_API 495 extern void 496 efx_intr_fini( 497 __in efx_nic_t *enp); 498 499 /* MAC */ 500 501 #if EFSYS_OPT_MAC_STATS 502 503 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */ 504 typedef enum efx_mac_stat_e { 505 EFX_MAC_RX_OCTETS, 506 EFX_MAC_RX_PKTS, 507 EFX_MAC_RX_UNICST_PKTS, 508 EFX_MAC_RX_MULTICST_PKTS, 509 EFX_MAC_RX_BRDCST_PKTS, 510 EFX_MAC_RX_PAUSE_PKTS, 511 EFX_MAC_RX_LE_64_PKTS, 512 EFX_MAC_RX_65_TO_127_PKTS, 513 EFX_MAC_RX_128_TO_255_PKTS, 514 EFX_MAC_RX_256_TO_511_PKTS, 515 EFX_MAC_RX_512_TO_1023_PKTS, 516 EFX_MAC_RX_1024_TO_15XX_PKTS, 517 EFX_MAC_RX_GE_15XX_PKTS, 518 EFX_MAC_RX_ERRORS, 519 EFX_MAC_RX_FCS_ERRORS, 520 EFX_MAC_RX_DROP_EVENTS, 521 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 522 EFX_MAC_RX_SYMBOL_ERRORS, 523 EFX_MAC_RX_ALIGN_ERRORS, 524 EFX_MAC_RX_INTERNAL_ERRORS, 525 EFX_MAC_RX_JABBER_PKTS, 526 EFX_MAC_RX_LANE0_CHAR_ERR, 527 EFX_MAC_RX_LANE1_CHAR_ERR, 528 EFX_MAC_RX_LANE2_CHAR_ERR, 529 EFX_MAC_RX_LANE3_CHAR_ERR, 530 EFX_MAC_RX_LANE0_DISP_ERR, 531 EFX_MAC_RX_LANE1_DISP_ERR, 532 EFX_MAC_RX_LANE2_DISP_ERR, 533 EFX_MAC_RX_LANE3_DISP_ERR, 534 EFX_MAC_RX_MATCH_FAULT, 535 EFX_MAC_RX_NODESC_DROP_CNT, 536 EFX_MAC_TX_OCTETS, 537 EFX_MAC_TX_PKTS, 538 EFX_MAC_TX_UNICST_PKTS, 539 EFX_MAC_TX_MULTICST_PKTS, 540 EFX_MAC_TX_BRDCST_PKTS, 541 EFX_MAC_TX_PAUSE_PKTS, 542 EFX_MAC_TX_LE_64_PKTS, 543 EFX_MAC_TX_65_TO_127_PKTS, 544 EFX_MAC_TX_128_TO_255_PKTS, 545 EFX_MAC_TX_256_TO_511_PKTS, 546 EFX_MAC_TX_512_TO_1023_PKTS, 547 EFX_MAC_TX_1024_TO_15XX_PKTS, 548 EFX_MAC_TX_GE_15XX_PKTS, 549 EFX_MAC_TX_ERRORS, 550 EFX_MAC_TX_SGL_COL_PKTS, 551 EFX_MAC_TX_MULT_COL_PKTS, 552 EFX_MAC_TX_EX_COL_PKTS, 553 EFX_MAC_TX_LATE_COL_PKTS, 554 EFX_MAC_TX_DEF_PKTS, 555 EFX_MAC_TX_EX_DEF_PKTS, 556 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 557 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 558 EFX_MAC_PM_TRUNC_VFIFO_FULL, 559 EFX_MAC_PM_DISCARD_VFIFO_FULL, 560 EFX_MAC_PM_TRUNC_QBB, 561 EFX_MAC_PM_DISCARD_QBB, 562 EFX_MAC_PM_DISCARD_MAPPING, 563 EFX_MAC_RXDP_Q_DISABLED_PKTS, 564 EFX_MAC_RXDP_DI_DROPPED_PKTS, 565 EFX_MAC_RXDP_STREAMING_PKTS, 566 EFX_MAC_RXDP_HLB_FETCH, 567 EFX_MAC_RXDP_HLB_WAIT, 568 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 569 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 570 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 571 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 572 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 573 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 574 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 575 EFX_MAC_VADAPTER_RX_BAD_BYTES, 576 EFX_MAC_VADAPTER_RX_OVERFLOW, 577 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 578 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 579 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 580 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 581 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 582 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 583 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 584 EFX_MAC_VADAPTER_TX_BAD_BYTES, 585 EFX_MAC_VADAPTER_TX_OVERFLOW, 586 EFX_MAC_FEC_UNCORRECTED_ERRORS, 587 EFX_MAC_FEC_CORRECTED_ERRORS, 588 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0, 589 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1, 590 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2, 591 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3, 592 EFX_MAC_CTPIO_VI_BUSY_FALLBACK, 593 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS, 594 EFX_MAC_CTPIO_MISSING_DBELL_FAIL, 595 EFX_MAC_CTPIO_OVERFLOW_FAIL, 596 EFX_MAC_CTPIO_UNDERFLOW_FAIL, 597 EFX_MAC_CTPIO_TIMEOUT_FAIL, 598 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL, 599 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL, 600 EFX_MAC_CTPIO_INVALID_WR_FAIL, 601 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK, 602 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK, 603 EFX_MAC_CTPIO_RUNT_FALLBACK, 604 EFX_MAC_CTPIO_SUCCESS, 605 EFX_MAC_CTPIO_FALLBACK, 606 EFX_MAC_CTPIO_POISON, 607 EFX_MAC_CTPIO_ERASE, 608 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC, 609 EFX_MAC_RXDP_HLB_IDLE, 610 EFX_MAC_RXDP_HLB_TIMEOUT, 611 EFX_MAC_NSTATS 612 } efx_mac_stat_t; 613 614 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 615 616 #endif /* EFSYS_OPT_MAC_STATS */ 617 618 typedef enum efx_link_mode_e { 619 EFX_LINK_UNKNOWN = 0, 620 EFX_LINK_DOWN, 621 EFX_LINK_10HDX, 622 EFX_LINK_10FDX, 623 EFX_LINK_100HDX, 624 EFX_LINK_100FDX, 625 EFX_LINK_1000HDX, 626 EFX_LINK_1000FDX, 627 EFX_LINK_10000FDX, 628 EFX_LINK_40000FDX, 629 EFX_LINK_25000FDX, 630 EFX_LINK_50000FDX, 631 EFX_LINK_100000FDX, 632 EFX_LINK_NMODES 633 } efx_link_mode_t; 634 635 #define EFX_VNI_OR_VSID_LEN 3 636 637 #define EFX_MAC_ADDR_IS_MULTICAST(_address) \ 638 (((const uint8_t *)_address)[0] & 0x01) 639 640 #define EFX_MAC_MULTICAST_LIST_MAX 256 641 642 #define EFX_MAC_SDU_MAX 9202 643 644 #define EFX_MAC_PDU_ADJUSTMENT \ 645 (/* EtherII */ 14 \ 646 + /* VLAN */ 4 \ 647 + /* CRC */ 4 \ 648 + /* bug16011 */ 16) \ 649 650 #define EFX_MAC_PDU(_sdu) \ 651 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 652 653 /* 654 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 655 * the SDU rounded up slightly. 656 */ 657 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 658 659 #define EFX_MAC_PDU_MIN 60 660 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 661 662 LIBEFX_API 663 extern __checkReturn efx_rc_t 664 efx_mac_pdu_get( 665 __in efx_nic_t *enp, 666 __out size_t *pdu); 667 668 LIBEFX_API 669 extern __checkReturn efx_rc_t 670 efx_mac_pdu_set( 671 __in efx_nic_t *enp, 672 __in size_t pdu); 673 674 LIBEFX_API 675 extern __checkReturn efx_rc_t 676 efx_mac_addr_set( 677 __in efx_nic_t *enp, 678 __in uint8_t *addr); 679 680 LIBEFX_API 681 extern __checkReturn efx_rc_t 682 efx_mac_filter_set( 683 __in efx_nic_t *enp, 684 __in boolean_t all_unicst, 685 __in boolean_t mulcst, 686 __in boolean_t all_mulcst, 687 __in boolean_t brdcst); 688 689 LIBEFX_API 690 extern void 691 efx_mac_filter_get_all_ucast_mcast( 692 __in efx_nic_t *enp, 693 __out boolean_t *all_unicst, 694 __out boolean_t *all_mulcst); 695 696 LIBEFX_API 697 extern __checkReturn efx_rc_t 698 efx_mac_multicast_list_set( 699 __in efx_nic_t *enp, 700 __in_ecount(6*count) uint8_t const *addrs, 701 __in int count); 702 703 LIBEFX_API 704 extern __checkReturn efx_rc_t 705 efx_mac_filter_default_rxq_set( 706 __in efx_nic_t *enp, 707 __in efx_rxq_t *erp, 708 __in boolean_t using_rss); 709 710 LIBEFX_API 711 extern void 712 efx_mac_filter_default_rxq_clear( 713 __in efx_nic_t *enp); 714 715 LIBEFX_API 716 extern __checkReturn efx_rc_t 717 efx_mac_drain( 718 __in efx_nic_t *enp, 719 __in boolean_t enabled); 720 721 LIBEFX_API 722 extern __checkReturn efx_rc_t 723 efx_mac_up( 724 __in efx_nic_t *enp, 725 __out boolean_t *mac_upp); 726 727 #define EFX_FCNTL_RESPOND 0x00000001 728 #define EFX_FCNTL_GENERATE 0x00000002 729 730 LIBEFX_API 731 extern __checkReturn efx_rc_t 732 efx_mac_fcntl_set( 733 __in efx_nic_t *enp, 734 __in unsigned int fcntl, 735 __in boolean_t autoneg); 736 737 LIBEFX_API 738 extern void 739 efx_mac_fcntl_get( 740 __in efx_nic_t *enp, 741 __out unsigned int *fcntl_wantedp, 742 __out unsigned int *fcntl_linkp); 743 744 745 #if EFSYS_OPT_MAC_STATS 746 747 #if EFSYS_OPT_NAMES 748 749 LIBEFX_API 750 extern __checkReturn const char * 751 efx_mac_stat_name( 752 __in efx_nic_t *enp, 753 __in unsigned int id); 754 755 #endif /* EFSYS_OPT_NAMES */ 756 757 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 758 759 #define EFX_MAC_STATS_MASK_NPAGES \ 760 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \ 761 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 762 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 763 764 /* 765 * Get mask of MAC statistics supported by the hardware. 766 * 767 * If mask_size is insufficient to return the mask, EINVAL error is 768 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 769 * (which is sizeof (uint32_t)) is sufficient. 770 */ 771 LIBEFX_API 772 extern __checkReturn efx_rc_t 773 efx_mac_stats_get_mask( 774 __in efx_nic_t *enp, 775 __out_bcount(mask_size) uint32_t *maskp, 776 __in size_t mask_size); 777 778 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 779 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 780 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 781 782 783 LIBEFX_API 784 extern __checkReturn efx_rc_t 785 efx_mac_stats_clear( 786 __in efx_nic_t *enp); 787 788 /* 789 * Upload mac statistics supported by the hardware into the given buffer. 790 * 791 * The DMA buffer must be 4Kbyte aligned and sized to hold at least 792 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters. 793 * 794 * The hardware will only DMA statistics that it understands (of course). 795 * Drivers should not make any assumptions about which statistics are 796 * supported, especially when the statistics are generated by firmware. 797 * 798 * Thus, drivers should zero this buffer before use, so that not-understood 799 * statistics read back as zero. 800 */ 801 LIBEFX_API 802 extern __checkReturn efx_rc_t 803 efx_mac_stats_upload( 804 __in efx_nic_t *enp, 805 __in efsys_mem_t *esmp); 806 807 LIBEFX_API 808 extern __checkReturn efx_rc_t 809 efx_mac_stats_periodic( 810 __in efx_nic_t *enp, 811 __in efsys_mem_t *esmp, 812 __in uint16_t period_ms, 813 __in boolean_t events); 814 815 LIBEFX_API 816 extern __checkReturn efx_rc_t 817 efx_mac_stats_update( 818 __in efx_nic_t *enp, 819 __in efsys_mem_t *esmp, 820 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 821 __inout_opt uint32_t *generationp); 822 823 #endif /* EFSYS_OPT_MAC_STATS */ 824 825 /* MON */ 826 827 typedef enum efx_mon_type_e { 828 EFX_MON_INVALID = 0, 829 EFX_MON_SFC90X0, 830 EFX_MON_SFC91X0, 831 EFX_MON_SFC92X0, 832 EFX_MON_NTYPES 833 } efx_mon_type_t; 834 835 #if EFSYS_OPT_NAMES 836 837 LIBEFX_API 838 extern const char * 839 efx_mon_name( 840 __in efx_nic_t *enp); 841 842 #endif /* EFSYS_OPT_NAMES */ 843 844 LIBEFX_API 845 extern __checkReturn efx_rc_t 846 efx_mon_init( 847 __in efx_nic_t *enp); 848 849 #if EFSYS_OPT_MON_STATS 850 851 #define EFX_MON_STATS_PAGE_SIZE 0x100 852 #define EFX_MON_MASK_ELEMENT_SIZE 32 853 854 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */ 855 typedef enum efx_mon_stat_e { 856 EFX_MON_STAT_CONTROLLER_TEMP, 857 EFX_MON_STAT_PHY_COMMON_TEMP, 858 EFX_MON_STAT_CONTROLLER_COOLING, 859 EFX_MON_STAT_PHY0_TEMP, 860 EFX_MON_STAT_PHY0_COOLING, 861 EFX_MON_STAT_PHY1_TEMP, 862 EFX_MON_STAT_PHY1_COOLING, 863 EFX_MON_STAT_IN_1V0, 864 EFX_MON_STAT_IN_1V2, 865 EFX_MON_STAT_IN_1V8, 866 EFX_MON_STAT_IN_2V5, 867 EFX_MON_STAT_IN_3V3, 868 EFX_MON_STAT_IN_12V0, 869 EFX_MON_STAT_IN_1V2A, 870 EFX_MON_STAT_IN_VREF, 871 EFX_MON_STAT_OUT_VAOE, 872 EFX_MON_STAT_AOE_TEMP, 873 EFX_MON_STAT_PSU_AOE_TEMP, 874 EFX_MON_STAT_PSU_TEMP, 875 EFX_MON_STAT_FAN_0, 876 EFX_MON_STAT_FAN_1, 877 EFX_MON_STAT_FAN_2, 878 EFX_MON_STAT_FAN_3, 879 EFX_MON_STAT_FAN_4, 880 EFX_MON_STAT_IN_VAOE, 881 EFX_MON_STAT_OUT_IAOE, 882 EFX_MON_STAT_IN_IAOE, 883 EFX_MON_STAT_NIC_POWER, 884 EFX_MON_STAT_IN_0V9, 885 EFX_MON_STAT_IN_I0V9, 886 EFX_MON_STAT_IN_I1V2, 887 EFX_MON_STAT_IN_0V9_ADC, 888 EFX_MON_STAT_CONTROLLER_2_TEMP, 889 EFX_MON_STAT_VREG_INTERNAL_TEMP, 890 EFX_MON_STAT_VREG_0V9_TEMP, 891 EFX_MON_STAT_VREG_1V2_TEMP, 892 EFX_MON_STAT_CONTROLLER_VPTAT, 893 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP, 894 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC, 895 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC, 896 EFX_MON_STAT_AMBIENT_TEMP, 897 EFX_MON_STAT_AIRFLOW, 898 EFX_MON_STAT_VDD08D_VSS08D_CSR, 899 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 900 EFX_MON_STAT_HOTPOINT_TEMP, 901 EFX_MON_STAT_PHY_POWER_PORT0, 902 EFX_MON_STAT_PHY_POWER_PORT1, 903 EFX_MON_STAT_MUM_VCC, 904 EFX_MON_STAT_IN_0V9_A, 905 EFX_MON_STAT_IN_I0V9_A, 906 EFX_MON_STAT_VREG_0V9_A_TEMP, 907 EFX_MON_STAT_IN_0V9_B, 908 EFX_MON_STAT_IN_I0V9_B, 909 EFX_MON_STAT_VREG_0V9_B_TEMP, 910 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 911 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC, 912 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 913 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC, 914 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 915 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 916 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC, 917 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC, 918 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 919 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 920 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC, 921 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC, 922 EFX_MON_STAT_SODIMM_VOUT, 923 EFX_MON_STAT_SODIMM_0_TEMP, 924 EFX_MON_STAT_SODIMM_1_TEMP, 925 EFX_MON_STAT_PHY0_VCC, 926 EFX_MON_STAT_PHY1_VCC, 927 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 928 EFX_MON_STAT_BOARD_FRONT_TEMP, 929 EFX_MON_STAT_BOARD_BACK_TEMP, 930 EFX_MON_STAT_IN_I1V8, 931 EFX_MON_STAT_IN_I2V5, 932 EFX_MON_STAT_IN_I3V3, 933 EFX_MON_STAT_IN_I12V0, 934 EFX_MON_STAT_IN_1V3, 935 EFX_MON_STAT_IN_I1V3, 936 EFX_MON_NSTATS 937 } efx_mon_stat_t; 938 939 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 940 941 typedef enum efx_mon_stat_state_e { 942 EFX_MON_STAT_STATE_OK = 0, 943 EFX_MON_STAT_STATE_WARNING = 1, 944 EFX_MON_STAT_STATE_FATAL = 2, 945 EFX_MON_STAT_STATE_BROKEN = 3, 946 EFX_MON_STAT_STATE_NO_READING = 4, 947 } efx_mon_stat_state_t; 948 949 typedef enum efx_mon_stat_unit_e { 950 EFX_MON_STAT_UNIT_UNKNOWN = 0, 951 EFX_MON_STAT_UNIT_BOOL, 952 EFX_MON_STAT_UNIT_TEMP_C, 953 EFX_MON_STAT_UNIT_VOLTAGE_MV, 954 EFX_MON_STAT_UNIT_CURRENT_MA, 955 EFX_MON_STAT_UNIT_POWER_W, 956 EFX_MON_STAT_UNIT_RPM, 957 EFX_MON_NUNITS 958 } efx_mon_stat_unit_t; 959 960 typedef struct efx_mon_stat_value_s { 961 uint16_t emsv_value; 962 efx_mon_stat_state_t emsv_state; 963 efx_mon_stat_unit_t emsv_unit; 964 } efx_mon_stat_value_t; 965 966 typedef struct efx_mon_limit_value_s { 967 uint16_t emlv_warning_min; 968 uint16_t emlv_warning_max; 969 uint16_t emlv_fatal_min; 970 uint16_t emlv_fatal_max; 971 } efx_mon_stat_limits_t; 972 973 typedef enum efx_mon_stat_portmask_e { 974 EFX_MON_STAT_PORTMAP_NONE = 0, 975 EFX_MON_STAT_PORTMAP_PORT0 = 1, 976 EFX_MON_STAT_PORTMAP_PORT1 = 2, 977 EFX_MON_STAT_PORTMAP_PORT2 = 3, 978 EFX_MON_STAT_PORTMAP_PORT3 = 4, 979 EFX_MON_STAT_PORTMAP_ALL = (-1), 980 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2) 981 } efx_mon_stat_portmask_t; 982 983 #if EFSYS_OPT_NAMES 984 985 LIBEFX_API 986 extern const char * 987 efx_mon_stat_name( 988 __in efx_nic_t *enp, 989 __in efx_mon_stat_t id); 990 991 LIBEFX_API 992 extern const char * 993 efx_mon_stat_description( 994 __in efx_nic_t *enp, 995 __in efx_mon_stat_t id); 996 997 #endif /* EFSYS_OPT_NAMES */ 998 999 LIBEFX_API 1000 extern __checkReturn boolean_t 1001 efx_mon_mcdi_to_efx_stat( 1002 __in int mcdi_index, 1003 __out efx_mon_stat_t *statp); 1004 1005 LIBEFX_API 1006 extern __checkReturn boolean_t 1007 efx_mon_get_stat_unit( 1008 __in efx_mon_stat_t stat, 1009 __out efx_mon_stat_unit_t *unitp); 1010 1011 LIBEFX_API 1012 extern __checkReturn boolean_t 1013 efx_mon_get_stat_portmap( 1014 __in efx_mon_stat_t stat, 1015 __out efx_mon_stat_portmask_t *maskp); 1016 1017 LIBEFX_API 1018 extern __checkReturn efx_rc_t 1019 efx_mon_stats_update( 1020 __in efx_nic_t *enp, 1021 __in efsys_mem_t *esmp, 1022 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 1023 1024 LIBEFX_API 1025 extern __checkReturn efx_rc_t 1026 efx_mon_limits_update( 1027 __in efx_nic_t *enp, 1028 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values); 1029 1030 #endif /* EFSYS_OPT_MON_STATS */ 1031 1032 LIBEFX_API 1033 extern void 1034 efx_mon_fini( 1035 __in efx_nic_t *enp); 1036 1037 /* PHY */ 1038 1039 LIBEFX_API 1040 extern __checkReturn efx_rc_t 1041 efx_phy_verify( 1042 __in efx_nic_t *enp); 1043 1044 typedef enum efx_phy_led_mode_e { 1045 EFX_PHY_LED_DEFAULT = 0, 1046 EFX_PHY_LED_OFF, 1047 EFX_PHY_LED_ON, 1048 EFX_PHY_LED_FLASH, 1049 EFX_PHY_LED_NMODES 1050 } efx_phy_led_mode_t; 1051 1052 #if EFSYS_OPT_PHY_LED_CONTROL 1053 1054 LIBEFX_API 1055 extern __checkReturn efx_rc_t 1056 efx_phy_led_set( 1057 __in efx_nic_t *enp, 1058 __in efx_phy_led_mode_t mode); 1059 1060 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1061 1062 LIBEFX_API 1063 extern __checkReturn efx_rc_t 1064 efx_port_init( 1065 __in efx_nic_t *enp); 1066 1067 #if EFSYS_OPT_LOOPBACK 1068 1069 typedef enum efx_loopback_type_e { 1070 EFX_LOOPBACK_OFF = 0, 1071 EFX_LOOPBACK_DATA = 1, 1072 EFX_LOOPBACK_GMAC = 2, 1073 EFX_LOOPBACK_XGMII = 3, 1074 EFX_LOOPBACK_XGXS = 4, 1075 EFX_LOOPBACK_XAUI = 5, 1076 EFX_LOOPBACK_GMII = 6, 1077 EFX_LOOPBACK_SGMII = 7, 1078 EFX_LOOPBACK_XGBR = 8, 1079 EFX_LOOPBACK_XFI = 9, 1080 EFX_LOOPBACK_XAUI_FAR = 10, 1081 EFX_LOOPBACK_GMII_FAR = 11, 1082 EFX_LOOPBACK_SGMII_FAR = 12, 1083 EFX_LOOPBACK_XFI_FAR = 13, 1084 EFX_LOOPBACK_GPHY = 14, 1085 EFX_LOOPBACK_PHY_XS = 15, 1086 EFX_LOOPBACK_PCS = 16, 1087 EFX_LOOPBACK_PMA_PMD = 17, 1088 EFX_LOOPBACK_XPORT = 18, 1089 EFX_LOOPBACK_XGMII_WS = 19, 1090 EFX_LOOPBACK_XAUI_WS = 20, 1091 EFX_LOOPBACK_XAUI_WS_FAR = 21, 1092 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 1093 EFX_LOOPBACK_GMII_WS = 23, 1094 EFX_LOOPBACK_XFI_WS = 24, 1095 EFX_LOOPBACK_XFI_WS_FAR = 25, 1096 EFX_LOOPBACK_PHYXS_WS = 26, 1097 EFX_LOOPBACK_PMA_INT = 27, 1098 EFX_LOOPBACK_SD_NEAR = 28, 1099 EFX_LOOPBACK_SD_FAR = 29, 1100 EFX_LOOPBACK_PMA_INT_WS = 30, 1101 EFX_LOOPBACK_SD_FEP2_WS = 31, 1102 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 1103 EFX_LOOPBACK_SD_FEP_WS = 33, 1104 EFX_LOOPBACK_SD_FES_WS = 34, 1105 EFX_LOOPBACK_AOE_INT_NEAR = 35, 1106 EFX_LOOPBACK_DATA_WS = 36, 1107 EFX_LOOPBACK_FORCE_EXT_LINK = 37, 1108 EFX_LOOPBACK_NTYPES 1109 } efx_loopback_type_t; 1110 1111 typedef enum efx_loopback_kind_e { 1112 EFX_LOOPBACK_KIND_OFF = 0, 1113 EFX_LOOPBACK_KIND_ALL, 1114 EFX_LOOPBACK_KIND_MAC, 1115 EFX_LOOPBACK_KIND_PHY, 1116 EFX_LOOPBACK_NKINDS 1117 } efx_loopback_kind_t; 1118 1119 LIBEFX_API 1120 extern void 1121 efx_loopback_mask( 1122 __in efx_loopback_kind_t loopback_kind, 1123 __out efx_qword_t *maskp); 1124 1125 LIBEFX_API 1126 extern __checkReturn efx_rc_t 1127 efx_port_loopback_set( 1128 __in efx_nic_t *enp, 1129 __in efx_link_mode_t link_mode, 1130 __in efx_loopback_type_t type); 1131 1132 #if EFSYS_OPT_NAMES 1133 1134 LIBEFX_API 1135 extern __checkReturn const char * 1136 efx_loopback_type_name( 1137 __in efx_nic_t *enp, 1138 __in efx_loopback_type_t type); 1139 1140 #endif /* EFSYS_OPT_NAMES */ 1141 1142 #endif /* EFSYS_OPT_LOOPBACK */ 1143 1144 LIBEFX_API 1145 extern __checkReturn efx_rc_t 1146 efx_port_poll( 1147 __in efx_nic_t *enp, 1148 __out_opt efx_link_mode_t *link_modep); 1149 1150 LIBEFX_API 1151 extern void 1152 efx_port_fini( 1153 __in efx_nic_t *enp); 1154 1155 typedef enum efx_phy_cap_type_e { 1156 EFX_PHY_CAP_INVALID = 0, 1157 EFX_PHY_CAP_10HDX, 1158 EFX_PHY_CAP_10FDX, 1159 EFX_PHY_CAP_100HDX, 1160 EFX_PHY_CAP_100FDX, 1161 EFX_PHY_CAP_1000HDX, 1162 EFX_PHY_CAP_1000FDX, 1163 EFX_PHY_CAP_10000FDX, 1164 EFX_PHY_CAP_PAUSE, 1165 EFX_PHY_CAP_ASYM, 1166 EFX_PHY_CAP_AN, 1167 EFX_PHY_CAP_40000FDX, 1168 EFX_PHY_CAP_DDM, 1169 EFX_PHY_CAP_100000FDX, 1170 EFX_PHY_CAP_25000FDX, 1171 EFX_PHY_CAP_50000FDX, 1172 EFX_PHY_CAP_BASER_FEC, 1173 EFX_PHY_CAP_BASER_FEC_REQUESTED, 1174 EFX_PHY_CAP_RS_FEC, 1175 EFX_PHY_CAP_RS_FEC_REQUESTED, 1176 EFX_PHY_CAP_25G_BASER_FEC, 1177 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED, 1178 EFX_PHY_CAP_NTYPES 1179 } efx_phy_cap_type_t; 1180 1181 1182 #define EFX_PHY_CAP_CURRENT 0x00000000 1183 #define EFX_PHY_CAP_DEFAULT 0x00000001 1184 #define EFX_PHY_CAP_PERM 0x00000002 1185 1186 LIBEFX_API 1187 extern void 1188 efx_phy_adv_cap_get( 1189 __in efx_nic_t *enp, 1190 __in uint32_t flag, 1191 __out uint32_t *maskp); 1192 1193 LIBEFX_API 1194 extern __checkReturn efx_rc_t 1195 efx_phy_adv_cap_set( 1196 __in efx_nic_t *enp, 1197 __in uint32_t mask); 1198 1199 LIBEFX_API 1200 extern void 1201 efx_phy_lp_cap_get( 1202 __in efx_nic_t *enp, 1203 __out uint32_t *maskp); 1204 1205 LIBEFX_API 1206 extern __checkReturn efx_rc_t 1207 efx_phy_oui_get( 1208 __in efx_nic_t *enp, 1209 __out uint32_t *ouip); 1210 1211 typedef enum efx_phy_media_type_e { 1212 EFX_PHY_MEDIA_INVALID = 0, 1213 EFX_PHY_MEDIA_XAUI, 1214 EFX_PHY_MEDIA_CX4, 1215 EFX_PHY_MEDIA_KX4, 1216 EFX_PHY_MEDIA_XFP, 1217 EFX_PHY_MEDIA_SFP_PLUS, 1218 EFX_PHY_MEDIA_BASE_T, 1219 EFX_PHY_MEDIA_QSFP_PLUS, 1220 EFX_PHY_MEDIA_NTYPES 1221 } efx_phy_media_type_t; 1222 1223 /* 1224 * Get the type of medium currently used. If the board has ports for 1225 * modules, a module is present, and we recognise the media type of 1226 * the module, then this will be the media type of the module. 1227 * Otherwise it will be the media type of the port. 1228 */ 1229 LIBEFX_API 1230 extern void 1231 efx_phy_media_type_get( 1232 __in efx_nic_t *enp, 1233 __out efx_phy_media_type_t *typep); 1234 1235 /* 1236 * 2-wire device address of the base information in accordance with SFF-8472 1237 * Diagnostic Monitoring Interface for Optical Transceivers section 1238 * 4 Memory Organization. 1239 */ 1240 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0 1241 1242 /* 1243 * 2-wire device address of the digital diagnostics monitoring interface 1244 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical 1245 * Transceivers section 4 Memory Organization. 1246 */ 1247 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2 1248 1249 /* 1250 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436 1251 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and 1252 * Operation. 1253 */ 1254 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0 1255 1256 /* 1257 * Maximum accessible data offset for PHY module information. 1258 */ 1259 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100 1260 1261 1262 LIBEFX_API 1263 extern __checkReturn efx_rc_t 1264 efx_phy_module_get_info( 1265 __in efx_nic_t *enp, 1266 __in uint8_t dev_addr, 1267 __in size_t offset, 1268 __in size_t len, 1269 __out_bcount(len) uint8_t *data); 1270 1271 #if EFSYS_OPT_PHY_STATS 1272 1273 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 1274 typedef enum efx_phy_stat_e { 1275 EFX_PHY_STAT_OUI, 1276 EFX_PHY_STAT_PMA_PMD_LINK_UP, 1277 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 1278 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 1279 EFX_PHY_STAT_PMA_PMD_REV_A, 1280 EFX_PHY_STAT_PMA_PMD_REV_B, 1281 EFX_PHY_STAT_PMA_PMD_REV_C, 1282 EFX_PHY_STAT_PMA_PMD_REV_D, 1283 EFX_PHY_STAT_PCS_LINK_UP, 1284 EFX_PHY_STAT_PCS_RX_FAULT, 1285 EFX_PHY_STAT_PCS_TX_FAULT, 1286 EFX_PHY_STAT_PCS_BER, 1287 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 1288 EFX_PHY_STAT_PHY_XS_LINK_UP, 1289 EFX_PHY_STAT_PHY_XS_RX_FAULT, 1290 EFX_PHY_STAT_PHY_XS_TX_FAULT, 1291 EFX_PHY_STAT_PHY_XS_ALIGN, 1292 EFX_PHY_STAT_PHY_XS_SYNC_A, 1293 EFX_PHY_STAT_PHY_XS_SYNC_B, 1294 EFX_PHY_STAT_PHY_XS_SYNC_C, 1295 EFX_PHY_STAT_PHY_XS_SYNC_D, 1296 EFX_PHY_STAT_AN_LINK_UP, 1297 EFX_PHY_STAT_AN_MASTER, 1298 EFX_PHY_STAT_AN_LOCAL_RX_OK, 1299 EFX_PHY_STAT_AN_REMOTE_RX_OK, 1300 EFX_PHY_STAT_CL22EXT_LINK_UP, 1301 EFX_PHY_STAT_SNR_A, 1302 EFX_PHY_STAT_SNR_B, 1303 EFX_PHY_STAT_SNR_C, 1304 EFX_PHY_STAT_SNR_D, 1305 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 1306 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 1307 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 1308 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 1309 EFX_PHY_STAT_AN_COMPLETE, 1310 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 1311 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 1312 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 1313 EFX_PHY_STAT_PCS_FW_VERSION_0, 1314 EFX_PHY_STAT_PCS_FW_VERSION_1, 1315 EFX_PHY_STAT_PCS_FW_VERSION_2, 1316 EFX_PHY_STAT_PCS_FW_VERSION_3, 1317 EFX_PHY_STAT_PCS_FW_BUILD_YY, 1318 EFX_PHY_STAT_PCS_FW_BUILD_MM, 1319 EFX_PHY_STAT_PCS_FW_BUILD_DD, 1320 EFX_PHY_STAT_PCS_OP_MODE, 1321 EFX_PHY_NSTATS 1322 } efx_phy_stat_t; 1323 1324 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 1325 1326 #if EFSYS_OPT_NAMES 1327 1328 LIBEFX_API 1329 extern const char * 1330 efx_phy_stat_name( 1331 __in efx_nic_t *enp, 1332 __in efx_phy_stat_t stat); 1333 1334 #endif /* EFSYS_OPT_NAMES */ 1335 1336 #define EFX_PHY_STATS_SIZE 0x100 1337 1338 LIBEFX_API 1339 extern __checkReturn efx_rc_t 1340 efx_phy_stats_update( 1341 __in efx_nic_t *enp, 1342 __in efsys_mem_t *esmp, 1343 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 1344 1345 #endif /* EFSYS_OPT_PHY_STATS */ 1346 1347 1348 #if EFSYS_OPT_BIST 1349 1350 typedef enum efx_bist_type_e { 1351 EFX_BIST_TYPE_UNKNOWN, 1352 EFX_BIST_TYPE_PHY_NORMAL, 1353 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1354 EFX_BIST_TYPE_PHY_CABLE_LONG, 1355 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1356 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */ 1357 EFX_BIST_TYPE_REG, /* Test the register memories */ 1358 EFX_BIST_TYPE_NTYPES, 1359 } efx_bist_type_t; 1360 1361 typedef enum efx_bist_result_e { 1362 EFX_BIST_RESULT_UNKNOWN, 1363 EFX_BIST_RESULT_RUNNING, 1364 EFX_BIST_RESULT_PASSED, 1365 EFX_BIST_RESULT_FAILED, 1366 } efx_bist_result_t; 1367 1368 typedef enum efx_phy_cable_status_e { 1369 EFX_PHY_CABLE_STATUS_OK, 1370 EFX_PHY_CABLE_STATUS_INVALID, 1371 EFX_PHY_CABLE_STATUS_OPEN, 1372 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1373 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1374 EFX_PHY_CABLE_STATUS_BUSY, 1375 } efx_phy_cable_status_t; 1376 1377 typedef enum efx_bist_value_e { 1378 EFX_BIST_PHY_CABLE_LENGTH_A, 1379 EFX_BIST_PHY_CABLE_LENGTH_B, 1380 EFX_BIST_PHY_CABLE_LENGTH_C, 1381 EFX_BIST_PHY_CABLE_LENGTH_D, 1382 EFX_BIST_PHY_CABLE_STATUS_A, 1383 EFX_BIST_PHY_CABLE_STATUS_B, 1384 EFX_BIST_PHY_CABLE_STATUS_C, 1385 EFX_BIST_PHY_CABLE_STATUS_D, 1386 EFX_BIST_FAULT_CODE, 1387 /* 1388 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1389 * response. 1390 */ 1391 EFX_BIST_MEM_TEST, 1392 EFX_BIST_MEM_ADDR, 1393 EFX_BIST_MEM_BUS, 1394 EFX_BIST_MEM_EXPECT, 1395 EFX_BIST_MEM_ACTUAL, 1396 EFX_BIST_MEM_ECC, 1397 EFX_BIST_MEM_ECC_PARITY, 1398 EFX_BIST_MEM_ECC_FATAL, 1399 EFX_BIST_NVALUES, 1400 } efx_bist_value_t; 1401 1402 LIBEFX_API 1403 extern __checkReturn efx_rc_t 1404 efx_bist_enable_offline( 1405 __in efx_nic_t *enp); 1406 1407 LIBEFX_API 1408 extern __checkReturn efx_rc_t 1409 efx_bist_start( 1410 __in efx_nic_t *enp, 1411 __in efx_bist_type_t type); 1412 1413 LIBEFX_API 1414 extern __checkReturn efx_rc_t 1415 efx_bist_poll( 1416 __in efx_nic_t *enp, 1417 __in efx_bist_type_t type, 1418 __out efx_bist_result_t *resultp, 1419 __out_opt uint32_t *value_maskp, 1420 __out_ecount_opt(count) unsigned long *valuesp, 1421 __in size_t count); 1422 1423 LIBEFX_API 1424 extern void 1425 efx_bist_stop( 1426 __in efx_nic_t *enp, 1427 __in efx_bist_type_t type); 1428 1429 #endif /* EFSYS_OPT_BIST */ 1430 1431 #define EFX_FEATURE_IPV6 0x00000001 1432 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1433 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1434 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1435 #define EFX_FEATURE_MCDI 0x00000020 1436 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1437 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1438 #define EFX_FEATURE_TURBO 0x00000100 1439 #define EFX_FEATURE_MCDI_DMA 0x00000200 1440 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1441 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1442 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1443 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1444 #define EFX_FEATURE_PACKED_STREAM 0x00004000 1445 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000 1446 1447 typedef enum efx_tunnel_protocol_e { 1448 EFX_TUNNEL_PROTOCOL_NONE = 0, 1449 EFX_TUNNEL_PROTOCOL_VXLAN, 1450 EFX_TUNNEL_PROTOCOL_GENEVE, 1451 EFX_TUNNEL_PROTOCOL_NVGRE, 1452 EFX_TUNNEL_NPROTOS 1453 } efx_tunnel_protocol_t; 1454 1455 typedef enum efx_vi_window_shift_e { 1456 EFX_VI_WINDOW_SHIFT_INVALID = 0, 1457 EFX_VI_WINDOW_SHIFT_8K = 13, 1458 EFX_VI_WINDOW_SHIFT_16K = 14, 1459 EFX_VI_WINDOW_SHIFT_64K = 16, 1460 } efx_vi_window_shift_t; 1461 1462 typedef enum efx_nic_dma_mapping_e { 1463 EFX_NIC_DMA_MAPPING_UNKNOWN = 0, 1464 EFX_NIC_DMA_MAPPING_FLAT, 1465 EFX_NIC_DMA_MAPPING_REGIONED, 1466 1467 EFX_NIC_DMA_MAPPING_NTYPES 1468 } efx_nic_dma_mapping_t; 1469 1470 typedef struct efx_nic_cfg_s { 1471 uint32_t enc_board_type; 1472 uint32_t enc_phy_type; 1473 #if EFSYS_OPT_NAMES 1474 char enc_phy_name[21]; 1475 #endif 1476 char enc_phy_revision[21]; 1477 efx_mon_type_t enc_mon_type; 1478 #if EFSYS_OPT_MON_STATS 1479 uint32_t enc_mon_stat_dma_buf_size; 1480 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1481 #endif 1482 unsigned int enc_features; 1483 efx_vi_window_shift_t enc_vi_window_shift; 1484 uint8_t enc_mac_addr[6]; 1485 uint8_t enc_port; /* PHY port number */ 1486 uint32_t enc_intr_vec_base; 1487 uint32_t enc_intr_limit; 1488 uint32_t enc_evq_limit; 1489 uint32_t enc_txq_limit; 1490 uint32_t enc_rxq_limit; 1491 uint32_t enc_evq_max_nevs; 1492 uint32_t enc_evq_min_nevs; 1493 uint32_t enc_rxq_max_ndescs; 1494 uint32_t enc_rxq_min_ndescs; 1495 uint32_t enc_txq_max_ndescs; 1496 uint32_t enc_txq_min_ndescs; 1497 uint32_t enc_buftbl_limit; 1498 uint32_t enc_piobuf_limit; 1499 uint32_t enc_piobuf_size; 1500 uint32_t enc_piobuf_min_alloc_size; 1501 uint32_t enc_evq_timer_quantum_ns; 1502 uint32_t enc_evq_timer_max_us; 1503 uint32_t enc_clk_mult; 1504 uint32_t enc_ev_ew_desc_size; 1505 uint32_t enc_ev_desc_size; 1506 uint32_t enc_rx_desc_size; 1507 uint32_t enc_tx_desc_size; 1508 /* Maximum Rx prefix size if many Rx prefixes are supported */ 1509 uint32_t enc_rx_prefix_size; 1510 uint32_t enc_rx_buf_align_start; 1511 uint32_t enc_rx_buf_align_end; 1512 #if EFSYS_OPT_RX_SCALE 1513 /* 1514 * The limit on how many queues an RSS context in the even spread 1515 * mode can span. When this mode is not supported, the value is 0. 1516 */ 1517 uint32_t enc_rx_scale_even_spread_max_nqueues; 1518 /* 1519 * The limit on how many queues an RSS indirection table can address. 1520 * 1521 * Indirection table entries are offsets relative to a base queue ID. 1522 * This means that the maximum offset has to be less than this value. 1523 */ 1524 uint32_t enc_rx_scale_indirection_max_nqueues; 1525 /* Minimum number of entries an RSS indirection table can contain. */ 1526 uint32_t enc_rx_scale_tbl_min_nentries; 1527 /* Maximum number of entries an RSS indirection table can contain. */ 1528 uint32_t enc_rx_scale_tbl_max_nentries; 1529 uint32_t enc_rx_scale_max_exclusive_contexts; 1530 /* 1531 * Mask of supported hash algorithms. 1532 * Hash algorithm types are used as the bit indices. 1533 */ 1534 uint32_t enc_rx_scale_hash_alg_mask; 1535 /* 1536 * Indicates whether port numbers can be included to the 1537 * input data for hash computation. 1538 */ 1539 boolean_t enc_rx_scale_l4_hash_supported; 1540 boolean_t enc_rx_scale_additional_modes_supported; 1541 /* 1542 * Indicates whether the user can decide how many entries to 1543 * have in the indirection table of an exclusive RSS context. 1544 */ 1545 boolean_t enc_rx_scale_tbl_entry_count_is_selectable; 1546 #endif /* EFSYS_OPT_RX_SCALE */ 1547 #if EFSYS_OPT_LOOPBACK 1548 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1549 #endif /* EFSYS_OPT_LOOPBACK */ 1550 #if EFSYS_OPT_PHY_FLAGS 1551 uint32_t enc_phy_flags_mask; 1552 #endif /* EFSYS_OPT_PHY_FLAGS */ 1553 #if EFSYS_OPT_PHY_LED_CONTROL 1554 uint32_t enc_led_mask; 1555 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1556 #if EFSYS_OPT_PHY_STATS 1557 uint64_t enc_phy_stat_mask; 1558 #endif /* EFSYS_OPT_PHY_STATS */ 1559 #if EFSYS_OPT_MCDI 1560 uint8_t enc_mcdi_mdio_channel; 1561 #if EFSYS_OPT_PHY_STATS 1562 uint32_t enc_mcdi_phy_stat_mask; 1563 #endif /* EFSYS_OPT_PHY_STATS */ 1564 #if EFSYS_OPT_MON_STATS 1565 uint32_t *enc_mcdi_sensor_maskp; 1566 uint32_t enc_mcdi_sensor_mask_size; 1567 #endif /* EFSYS_OPT_MON_STATS */ 1568 #endif /* EFSYS_OPT_MCDI */ 1569 #if EFSYS_OPT_BIST 1570 uint32_t enc_bist_mask; 1571 #endif /* EFSYS_OPT_BIST */ 1572 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1573 efx_pcie_interface_t enc_intf; 1574 uint32_t enc_pf; 1575 uint32_t enc_vf; 1576 uint32_t enc_privilege_mask; 1577 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 1578 boolean_t enc_evq_init_done_ev_supported; 1579 boolean_t enc_bug26807_workaround; 1580 boolean_t enc_bug35388_workaround; 1581 boolean_t enc_bug41750_workaround; 1582 boolean_t enc_bug61265_workaround; 1583 boolean_t enc_bug61297_workaround; 1584 boolean_t enc_rx_batching_enabled; 1585 /* Maximum number of descriptors completed in an rx event. */ 1586 uint32_t enc_rx_batch_max; 1587 /* Number of rx descriptors the hardware requires for a push. */ 1588 uint32_t enc_rx_push_align; 1589 /* Maximum amount of data in DMA descriptor */ 1590 uint32_t enc_rx_dma_desc_size_max; 1591 uint32_t enc_tx_dma_desc_size_max; 1592 /* 1593 * Boundary which DMA descriptor data must not cross or 0 if no 1594 * limitation. 1595 */ 1596 uint32_t enc_tx_dma_desc_boundary; 1597 /* 1598 * Maximum number of bytes into the packet the TCP header can start for 1599 * the hardware to apply TSO packet edits. 1600 */ 1601 uint32_t enc_tx_tso_tcp_header_offset_limit; 1602 /* Maximum number of header DMA descriptors per TSO transaction. */ 1603 uint32_t enc_tx_tso_max_header_ndescs; 1604 /* Maximum header length acceptable by TSO transaction. */ 1605 uint32_t enc_tx_tso_max_header_length; 1606 /* Maximum number of payload DMA descriptors per TSO transaction. */ 1607 uint32_t enc_tx_tso_max_payload_ndescs; 1608 /* Maximum payload length per TSO transaction. */ 1609 uint32_t enc_tx_tso_max_payload_length; 1610 /* Maximum number of frames to be generated per TSO transaction. */ 1611 uint32_t enc_tx_tso_max_nframes; 1612 boolean_t enc_fw_assisted_tso_enabled; 1613 boolean_t enc_fw_assisted_tso_v2_enabled; 1614 boolean_t enc_fw_assisted_tso_v2_encap_enabled; 1615 boolean_t enc_tso_v3_enabled; 1616 /* Number of TSO contexts on the NIC (FATSOv2) */ 1617 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1618 boolean_t enc_hw_tx_insert_vlan_enabled; 1619 /* Number of PFs on the NIC */ 1620 uint32_t enc_hw_pf_count; 1621 /* Datapath firmware vadapter/vport/vswitch support */ 1622 boolean_t enc_datapath_cap_evb; 1623 /* Datapath firmware vport reconfigure support */ 1624 boolean_t enc_vport_reconfigure_supported; 1625 boolean_t enc_rx_disable_scatter_supported; 1626 /* Maximum number of Rx scatter segments supported by HW */ 1627 uint32_t enc_rx_scatter_max; 1628 boolean_t enc_allow_set_mac_with_installed_filters; 1629 boolean_t enc_enhanced_set_mac_supported; 1630 boolean_t enc_init_evq_v2_supported; 1631 boolean_t enc_init_evq_extended_width_supported; 1632 boolean_t enc_no_cont_ev_mode_supported; 1633 boolean_t enc_init_rxq_with_buffer_size; 1634 boolean_t enc_rx_packed_stream_supported; 1635 boolean_t enc_rx_var_packed_stream_supported; 1636 boolean_t enc_rx_es_super_buffer_supported; 1637 boolean_t enc_fw_subvariant_no_tx_csum_supported; 1638 boolean_t enc_pm_and_rxdp_counters; 1639 boolean_t enc_mac_stats_40g_tx_size_bins; 1640 uint32_t enc_tunnel_encapsulations_supported; 1641 /* 1642 * NIC global maximum for unique UDP tunnel ports shared by all 1643 * functions. 1644 */ 1645 uint32_t enc_tunnel_config_udp_entries_max; 1646 /* External port identifier */ 1647 uint8_t enc_external_port; 1648 uint32_t enc_mcdi_max_payload_length; 1649 /* VPD may be per-PF or global */ 1650 boolean_t enc_vpd_is_global; 1651 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1652 uint32_t enc_required_pcie_bandwidth_mbps; 1653 uint32_t enc_max_pcie_link_gen; 1654 /* Firmware verifies integrity of NVRAM updates */ 1655 boolean_t enc_nvram_update_verify_result_supported; 1656 /* Firmware supports polled NVRAM updates on select partitions */ 1657 boolean_t enc_nvram_update_poll_verify_result_supported; 1658 /* Firmware accepts updates via the BUNDLE partition */ 1659 boolean_t enc_nvram_bundle_update_supported; 1660 /* Firmware support for extended MAC_STATS buffer */ 1661 uint32_t enc_mac_stats_nstats; 1662 boolean_t enc_fec_counters; 1663 boolean_t enc_hlb_counters; 1664 /* NIC support for Match-Action Engine (MAE). */ 1665 boolean_t enc_mae_supported; 1666 /* 1667 * NIC is privileged, i.e. it is the MAE admin. 1668 * Only privileged MAE clients can manage MAE flow rules, 1669 * for example, modify, count and route traffic to selected 1670 * destination (a MAE client or network port). 1671 */ 1672 boolean_t enc_mae_admin; 1673 /* NIC support for MAE action set v2 features. */ 1674 boolean_t enc_mae_aset_v2_supported; 1675 /* NIC support for MCDI Table Access API. */ 1676 boolean_t enc_table_api_supported; 1677 /* Firmware support for "FLAG" and "MARK" filter actions */ 1678 boolean_t enc_filter_action_flag_supported; 1679 boolean_t enc_filter_action_mark_supported; 1680 uint32_t enc_filter_action_mark_max; 1681 /* Port assigned to this PCI function */ 1682 uint32_t enc_assigned_port; 1683 /* NIC DMA mapping type */ 1684 efx_nic_dma_mapping_t enc_dma_mapping; 1685 } efx_nic_cfg_t; 1686 1687 #define EFX_PCI_VF_INVALID 0xffff 1688 1689 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \ 1690 ((configp)->evc_function == EFX_PCI_VF_INVALID) 1691 1692 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == EFX_PCI_VF_INVALID) 1693 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != EFX_PCI_VF_INVALID) 1694 1695 #define EFX_PCI_FUNCTION(_encp) \ 1696 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1697 1698 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1699 1700 LIBEFX_API 1701 extern const efx_nic_cfg_t * 1702 efx_nic_cfg_get( 1703 __in const efx_nic_t *enp); 1704 1705 /* RxDPCPU firmware id values by which FW variant can be identified */ 1706 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0 1707 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1 1708 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2 1709 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5 1710 #define EFX_RXDP_DPDK_FW_ID 0x6 1711 1712 typedef struct efx_nic_fw_info_s { 1713 /* Basic FW version information */ 1714 uint16_t enfi_mc_fw_version[4]; 1715 /* 1716 * If datapath capabilities can be detected, 1717 * additional FW information is to be shown 1718 */ 1719 boolean_t enfi_dpcpu_fw_ids_valid; 1720 /* Rx and Tx datapath CPU FW IDs */ 1721 uint16_t enfi_rx_dpcpu_fw_id; 1722 uint16_t enfi_tx_dpcpu_fw_id; 1723 } efx_nic_fw_info_t; 1724 1725 LIBEFX_API 1726 extern __checkReturn efx_rc_t 1727 efx_nic_get_fw_version( 1728 __in efx_nic_t *enp, 1729 __out efx_nic_fw_info_t *enfip); 1730 1731 #define EFX_NIC_BOARD_INFO_SERIAL_LEN (64) 1732 #define EFX_NIC_BOARD_INFO_NAME_LEN (16) 1733 1734 typedef struct efx_nic_board_info_s { 1735 /* The following two fields are NUL-terminated ASCII strings. */ 1736 char enbi_serial[EFX_NIC_BOARD_INFO_SERIAL_LEN]; 1737 char enbi_name[EFX_NIC_BOARD_INFO_NAME_LEN]; 1738 uint32_t enbi_revision; 1739 } efx_nic_board_info_t; 1740 1741 LIBEFX_API 1742 extern __checkReturn efx_rc_t 1743 efx_nic_get_board_info( 1744 __in efx_nic_t *enp, 1745 __out efx_nic_board_info_t *board_infop); 1746 1747 /* Driver resource limits (minimum required/maximum usable). */ 1748 typedef struct efx_drv_limits_s { 1749 uint32_t edl_min_evq_count; 1750 uint32_t edl_max_evq_count; 1751 1752 uint32_t edl_min_rxq_count; 1753 uint32_t edl_max_rxq_count; 1754 1755 uint32_t edl_min_txq_count; 1756 uint32_t edl_max_txq_count; 1757 1758 /* PIO blocks (sub-allocated from piobuf) */ 1759 uint32_t edl_min_pio_alloc_size; 1760 uint32_t edl_max_pio_alloc_count; 1761 } efx_drv_limits_t; 1762 1763 LIBEFX_API 1764 extern __checkReturn efx_rc_t 1765 efx_nic_set_drv_limits( 1766 __inout efx_nic_t *enp, 1767 __in efx_drv_limits_t *edlp); 1768 1769 /* 1770 * Register the OS driver version string for management agents 1771 * (e.g. via NC-SI). The content length is provided (i.e. no 1772 * NUL terminator). Use length 0 to indicate no version string 1773 * should be advertised. It is valid to set the version string 1774 * only before efx_nic_probe() is called. 1775 */ 1776 LIBEFX_API 1777 extern __checkReturn efx_rc_t 1778 efx_nic_set_drv_version( 1779 __inout efx_nic_t *enp, 1780 __in_ecount(length) char const *verp, 1781 __in size_t length); 1782 1783 typedef enum efx_nic_region_e { 1784 EFX_REGION_VI, /* Memory BAR UC mapping */ 1785 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1786 } efx_nic_region_t; 1787 1788 LIBEFX_API 1789 extern __checkReturn efx_rc_t 1790 efx_nic_get_bar_region( 1791 __in efx_nic_t *enp, 1792 __in efx_nic_region_t region, 1793 __out uint32_t *offsetp, 1794 __out size_t *sizep); 1795 1796 LIBEFX_API 1797 extern __checkReturn efx_rc_t 1798 efx_nic_get_vi_pool( 1799 __in efx_nic_t *enp, 1800 __out uint32_t *evq_countp, 1801 __out uint32_t *rxq_countp, 1802 __out uint32_t *txq_countp); 1803 1804 1805 #if EFSYS_OPT_VPD 1806 1807 typedef enum efx_vpd_tag_e { 1808 EFX_VPD_ID = 0x02, 1809 EFX_VPD_END = 0x0f, 1810 EFX_VPD_RO = 0x10, 1811 EFX_VPD_RW = 0x11, 1812 } efx_vpd_tag_t; 1813 1814 typedef uint16_t efx_vpd_keyword_t; 1815 1816 typedef struct efx_vpd_value_s { 1817 efx_vpd_tag_t evv_tag; 1818 efx_vpd_keyword_t evv_keyword; 1819 uint8_t evv_length; 1820 uint8_t evv_value[0x100]; 1821 } efx_vpd_value_t; 1822 1823 1824 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1825 1826 LIBEFX_API 1827 extern __checkReturn efx_rc_t 1828 efx_vpd_init( 1829 __in efx_nic_t *enp); 1830 1831 LIBEFX_API 1832 extern __checkReturn efx_rc_t 1833 efx_vpd_size( 1834 __in efx_nic_t *enp, 1835 __out size_t *sizep); 1836 1837 LIBEFX_API 1838 extern __checkReturn efx_rc_t 1839 efx_vpd_read( 1840 __in efx_nic_t *enp, 1841 __out_bcount(size) caddr_t data, 1842 __in size_t size); 1843 1844 LIBEFX_API 1845 extern __checkReturn efx_rc_t 1846 efx_vpd_verify( 1847 __in efx_nic_t *enp, 1848 __in_bcount(size) caddr_t data, 1849 __in size_t size); 1850 1851 LIBEFX_API 1852 extern __checkReturn efx_rc_t 1853 efx_vpd_reinit( 1854 __in efx_nic_t *enp, 1855 __in_bcount(size) caddr_t data, 1856 __in size_t size); 1857 1858 LIBEFX_API 1859 extern __checkReturn efx_rc_t 1860 efx_vpd_get( 1861 __in efx_nic_t *enp, 1862 __in_bcount(size) caddr_t data, 1863 __in size_t size, 1864 __inout efx_vpd_value_t *evvp); 1865 1866 LIBEFX_API 1867 extern __checkReturn efx_rc_t 1868 efx_vpd_set( 1869 __in efx_nic_t *enp, 1870 __inout_bcount(size) caddr_t data, 1871 __in size_t size, 1872 __in efx_vpd_value_t *evvp); 1873 1874 LIBEFX_API 1875 extern __checkReturn efx_rc_t 1876 efx_vpd_next( 1877 __in efx_nic_t *enp, 1878 __inout_bcount(size) caddr_t data, 1879 __in size_t size, 1880 __out efx_vpd_value_t *evvp, 1881 __inout unsigned int *contp); 1882 1883 LIBEFX_API 1884 extern __checkReturn efx_rc_t 1885 efx_vpd_write( 1886 __in efx_nic_t *enp, 1887 __in_bcount(size) caddr_t data, 1888 __in size_t size); 1889 1890 LIBEFX_API 1891 extern void 1892 efx_vpd_fini( 1893 __in efx_nic_t *enp); 1894 1895 #endif /* EFSYS_OPT_VPD */ 1896 1897 /* NVRAM */ 1898 1899 #if EFSYS_OPT_NVRAM 1900 1901 typedef enum efx_nvram_type_e { 1902 EFX_NVRAM_INVALID = 0, 1903 EFX_NVRAM_BOOTROM, 1904 EFX_NVRAM_BOOTROM_CFG, 1905 EFX_NVRAM_MC_FIRMWARE, 1906 EFX_NVRAM_MC_GOLDEN, 1907 EFX_NVRAM_PHY, 1908 EFX_NVRAM_NULLPHY, 1909 EFX_NVRAM_FPGA, 1910 EFX_NVRAM_FCFW, 1911 EFX_NVRAM_CPLD, 1912 EFX_NVRAM_FPGA_BACKUP, 1913 EFX_NVRAM_DYNAMIC_CFG, 1914 EFX_NVRAM_LICENSE, 1915 EFX_NVRAM_UEFIROM, 1916 EFX_NVRAM_MUM_FIRMWARE, 1917 EFX_NVRAM_DYNCONFIG_DEFAULTS, 1918 EFX_NVRAM_ROMCONFIG_DEFAULTS, 1919 EFX_NVRAM_BUNDLE, 1920 EFX_NVRAM_BUNDLE_METADATA, 1921 EFX_NVRAM_NTYPES, 1922 } efx_nvram_type_t; 1923 1924 typedef struct efx_nvram_info_s { 1925 uint32_t eni_flags; 1926 uint32_t eni_partn_size; 1927 uint32_t eni_address; 1928 uint32_t eni_erase_size; 1929 uint32_t eni_write_size; 1930 } efx_nvram_info_t; 1931 1932 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0) 1933 1934 LIBEFX_API 1935 extern __checkReturn efx_rc_t 1936 efx_nvram_init( 1937 __in efx_nic_t *enp); 1938 1939 #if EFSYS_OPT_DIAG 1940 1941 LIBEFX_API 1942 extern __checkReturn efx_rc_t 1943 efx_nvram_test( 1944 __in efx_nic_t *enp); 1945 1946 #endif /* EFSYS_OPT_DIAG */ 1947 1948 LIBEFX_API 1949 extern __checkReturn efx_rc_t 1950 efx_nvram_size( 1951 __in efx_nic_t *enp, 1952 __in efx_nvram_type_t type, 1953 __out size_t *sizep); 1954 1955 LIBEFX_API 1956 extern __checkReturn efx_rc_t 1957 efx_nvram_info( 1958 __in efx_nic_t *enp, 1959 __in efx_nvram_type_t type, 1960 __out efx_nvram_info_t *enip); 1961 1962 LIBEFX_API 1963 extern __checkReturn efx_rc_t 1964 efx_nvram_rw_start( 1965 __in efx_nic_t *enp, 1966 __in efx_nvram_type_t type, 1967 __out_opt size_t *pref_chunkp); 1968 1969 LIBEFX_API 1970 extern __checkReturn efx_rc_t 1971 efx_nvram_rw_finish( 1972 __in efx_nic_t *enp, 1973 __in efx_nvram_type_t type, 1974 __out_opt uint32_t *verify_resultp); 1975 1976 LIBEFX_API 1977 extern __checkReturn efx_rc_t 1978 efx_nvram_get_version( 1979 __in efx_nic_t *enp, 1980 __in efx_nvram_type_t type, 1981 __out uint32_t *subtypep, 1982 __out_ecount(4) uint16_t version[4]); 1983 1984 LIBEFX_API 1985 extern __checkReturn efx_rc_t 1986 efx_nvram_read_chunk( 1987 __in efx_nic_t *enp, 1988 __in efx_nvram_type_t type, 1989 __in unsigned int offset, 1990 __out_bcount(size) caddr_t data, 1991 __in size_t size); 1992 1993 LIBEFX_API 1994 extern __checkReturn efx_rc_t 1995 efx_nvram_read_backup( 1996 __in efx_nic_t *enp, 1997 __in efx_nvram_type_t type, 1998 __in unsigned int offset, 1999 __out_bcount(size) caddr_t data, 2000 __in size_t size); 2001 2002 LIBEFX_API 2003 extern __checkReturn efx_rc_t 2004 efx_nvram_set_version( 2005 __in efx_nic_t *enp, 2006 __in efx_nvram_type_t type, 2007 __in_ecount(4) uint16_t version[4]); 2008 2009 LIBEFX_API 2010 extern __checkReturn efx_rc_t 2011 efx_nvram_validate( 2012 __in efx_nic_t *enp, 2013 __in efx_nvram_type_t type, 2014 __in_bcount(partn_size) caddr_t partn_data, 2015 __in size_t partn_size); 2016 2017 LIBEFX_API 2018 extern __checkReturn efx_rc_t 2019 efx_nvram_erase( 2020 __in efx_nic_t *enp, 2021 __in efx_nvram_type_t type); 2022 2023 LIBEFX_API 2024 extern __checkReturn efx_rc_t 2025 efx_nvram_write_chunk( 2026 __in efx_nic_t *enp, 2027 __in efx_nvram_type_t type, 2028 __in unsigned int offset, 2029 __in_bcount(size) caddr_t data, 2030 __in size_t size); 2031 2032 LIBEFX_API 2033 extern void 2034 efx_nvram_fini( 2035 __in efx_nic_t *enp); 2036 2037 #endif /* EFSYS_OPT_NVRAM */ 2038 2039 #if EFSYS_OPT_BOOTCFG 2040 2041 /* Report size and offset of bootcfg sector in NVRAM partition. */ 2042 LIBEFX_API 2043 extern __checkReturn efx_rc_t 2044 efx_bootcfg_sector_info( 2045 __in efx_nic_t *enp, 2046 __in uint32_t pf, 2047 __out_opt uint32_t *sector_countp, 2048 __out size_t *offsetp, 2049 __out size_t *max_sizep); 2050 2051 /* 2052 * Copy bootcfg sector data to a target buffer which may differ in size. 2053 * Optionally corrects format errors in source buffer. 2054 */ 2055 LIBEFX_API 2056 extern efx_rc_t 2057 efx_bootcfg_copy_sector( 2058 __in efx_nic_t *enp, 2059 __inout_bcount(sector_length) 2060 uint8_t *sector, 2061 __in size_t sector_length, 2062 __out_bcount(data_size) uint8_t *data, 2063 __in size_t data_size, 2064 __in boolean_t handle_format_errors); 2065 2066 LIBEFX_API 2067 extern efx_rc_t 2068 efx_bootcfg_read( 2069 __in efx_nic_t *enp, 2070 __out_bcount(size) uint8_t *data, 2071 __in size_t size); 2072 2073 LIBEFX_API 2074 extern efx_rc_t 2075 efx_bootcfg_write( 2076 __in efx_nic_t *enp, 2077 __in_bcount(size) uint8_t *data, 2078 __in size_t size); 2079 2080 2081 /* 2082 * Processing routines for buffers arranged in the DHCP/BOOTP option format 2083 * (see https://tools.ietf.org/html/rfc1533) 2084 * 2085 * Summarising the format: the buffer is a sequence of options. All options 2086 * begin with a tag octet, which uniquely identifies the option. Fixed- 2087 * length options without data consist of only a tag octet. Only options PAD 2088 * (0) and END (255) are fixed length. All other options are variable-length 2089 * with a length octet following the tag octet. The value of the length 2090 * octet does not include the two octets specifying the tag and length. The 2091 * length octet is followed by "length" octets of data. 2092 * 2093 * Option data may be a sequence of sub-options in the same format. The data 2094 * content of the encapsulating option is one or more encapsulated sub-options, 2095 * with no terminating END tag is required. 2096 * 2097 * To be valid, the top-level sequence of options should be terminated by an 2098 * END tag. The buffer should be padded with the PAD byte. 2099 * 2100 * When stored to NVRAM, the DHCP option format buffer is preceded by a 2101 * checksum octet. The full buffer (including after the END tag) contributes 2102 * to the checksum, hence the need to fill the buffer to the end with PAD. 2103 */ 2104 2105 #define EFX_DHCP_END ((uint8_t)0xff) 2106 #define EFX_DHCP_PAD ((uint8_t)0) 2107 2108 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \ 2109 (uint16_t)(((encapsulator) << 8) | (encapsulated)) 2110 2111 LIBEFX_API 2112 extern __checkReturn uint8_t 2113 efx_dhcp_csum( 2114 __in_bcount(size) uint8_t const *data, 2115 __in size_t size); 2116 2117 LIBEFX_API 2118 extern __checkReturn efx_rc_t 2119 efx_dhcp_verify( 2120 __in_bcount(size) uint8_t const *data, 2121 __in size_t size, 2122 __out_opt size_t *usedp); 2123 2124 LIBEFX_API 2125 extern __checkReturn efx_rc_t 2126 efx_dhcp_find_tag( 2127 __in_bcount(buffer_length) uint8_t *bufferp, 2128 __in size_t buffer_length, 2129 __in uint16_t opt, 2130 __deref_out uint8_t **valuepp, 2131 __out size_t *value_lengthp); 2132 2133 LIBEFX_API 2134 extern __checkReturn efx_rc_t 2135 efx_dhcp_find_end( 2136 __in_bcount(buffer_length) uint8_t *bufferp, 2137 __in size_t buffer_length, 2138 __deref_out uint8_t **endpp); 2139 2140 2141 LIBEFX_API 2142 extern __checkReturn efx_rc_t 2143 efx_dhcp_delete_tag( 2144 __inout_bcount(buffer_length) uint8_t *bufferp, 2145 __in size_t buffer_length, 2146 __in uint16_t opt); 2147 2148 LIBEFX_API 2149 extern __checkReturn efx_rc_t 2150 efx_dhcp_add_tag( 2151 __inout_bcount(buffer_length) uint8_t *bufferp, 2152 __in size_t buffer_length, 2153 __in uint16_t opt, 2154 __in_bcount_opt(value_length) uint8_t *valuep, 2155 __in size_t value_length); 2156 2157 LIBEFX_API 2158 extern __checkReturn efx_rc_t 2159 efx_dhcp_update_tag( 2160 __inout_bcount(buffer_length) uint8_t *bufferp, 2161 __in size_t buffer_length, 2162 __in uint16_t opt, 2163 __in uint8_t *value_locationp, 2164 __in_bcount_opt(value_length) uint8_t *valuep, 2165 __in size_t value_length); 2166 2167 2168 #endif /* EFSYS_OPT_BOOTCFG */ 2169 2170 #if EFSYS_OPT_IMAGE_LAYOUT 2171 2172 #include "ef10_signed_image_layout.h" 2173 2174 /* 2175 * Image header used in unsigned and signed image layouts (see SF-102785-PS). 2176 * 2177 * NOTE: 2178 * The image header format is extensible. However, older drivers require an 2179 * exact match of image header version and header length when validating and 2180 * writing firmware images. 2181 * 2182 * To avoid breaking backward compatibility, we use the upper bits of the 2183 * controller version fields to contain an extra version number used for 2184 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM 2185 * version). See bug39254 and SF-102785-PS for details. 2186 */ 2187 typedef struct efx_image_header_s { 2188 uint32_t eih_magic; 2189 uint32_t eih_version; 2190 uint32_t eih_type; 2191 uint32_t eih_subtype; 2192 uint32_t eih_code_size; 2193 uint32_t eih_size; 2194 union { 2195 uint32_t eih_controller_version_min; 2196 struct { 2197 uint16_t eih_controller_version_min_short; 2198 uint8_t eih_extra_version_a; 2199 uint8_t eih_extra_version_b; 2200 }; 2201 }; 2202 union { 2203 uint32_t eih_controller_version_max; 2204 struct { 2205 uint16_t eih_controller_version_max_short; 2206 uint8_t eih_extra_version_c; 2207 uint8_t eih_extra_version_d; 2208 }; 2209 }; 2210 uint16_t eih_code_version_a; 2211 uint16_t eih_code_version_b; 2212 uint16_t eih_code_version_c; 2213 uint16_t eih_code_version_d; 2214 } efx_image_header_t; 2215 2216 #define EFX_IMAGE_HEADER_SIZE (40) 2217 #define EFX_IMAGE_HEADER_VERSION (4) 2218 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5) 2219 2220 2221 typedef struct efx_image_trailer_s { 2222 uint32_t eit_crc; 2223 } efx_image_trailer_t; 2224 2225 #define EFX_IMAGE_TRAILER_SIZE (4) 2226 2227 typedef enum efx_image_format_e { 2228 EFX_IMAGE_FORMAT_NO_IMAGE, 2229 EFX_IMAGE_FORMAT_INVALID, 2230 EFX_IMAGE_FORMAT_UNSIGNED, 2231 EFX_IMAGE_FORMAT_SIGNED, 2232 EFX_IMAGE_FORMAT_SIGNED_PACKAGE 2233 } efx_image_format_t; 2234 2235 typedef struct efx_image_info_s { 2236 efx_image_format_t eii_format; 2237 uint8_t * eii_imagep; 2238 size_t eii_image_size; 2239 efx_image_header_t * eii_headerp; 2240 } efx_image_info_t; 2241 2242 LIBEFX_API 2243 extern __checkReturn efx_rc_t 2244 efx_check_reflash_image( 2245 __in void *bufferp, 2246 __in uint32_t buffer_size, 2247 __out efx_image_info_t *infop); 2248 2249 LIBEFX_API 2250 extern __checkReturn efx_rc_t 2251 efx_build_signed_image_write_buffer( 2252 __out_bcount(buffer_size) 2253 uint8_t *bufferp, 2254 __in uint32_t buffer_size, 2255 __in efx_image_info_t *infop, 2256 __out efx_image_header_t **headerpp); 2257 2258 #endif /* EFSYS_OPT_IMAGE_LAYOUT */ 2259 2260 #if EFSYS_OPT_DIAG 2261 2262 typedef enum efx_pattern_type_t { 2263 EFX_PATTERN_BYTE_INCREMENT = 0, 2264 EFX_PATTERN_ALL_THE_SAME, 2265 EFX_PATTERN_BIT_ALTERNATE, 2266 EFX_PATTERN_BYTE_ALTERNATE, 2267 EFX_PATTERN_BYTE_CHANGING, 2268 EFX_PATTERN_BIT_SWEEP, 2269 EFX_PATTERN_NTYPES 2270 } efx_pattern_type_t; 2271 2272 typedef void 2273 (*efx_sram_pattern_fn_t)( 2274 __in size_t row, 2275 __in boolean_t negate, 2276 __out efx_qword_t *eqp); 2277 2278 LIBEFX_API 2279 extern __checkReturn efx_rc_t 2280 efx_sram_test( 2281 __in efx_nic_t *enp, 2282 __in efx_pattern_type_t type); 2283 2284 #endif /* EFSYS_OPT_DIAG */ 2285 2286 LIBEFX_API 2287 extern __checkReturn efx_rc_t 2288 efx_sram_buf_tbl_set( 2289 __in efx_nic_t *enp, 2290 __in uint32_t id, 2291 __in efsys_mem_t *esmp, 2292 __in size_t n); 2293 2294 LIBEFX_API 2295 extern void 2296 efx_sram_buf_tbl_clear( 2297 __in efx_nic_t *enp, 2298 __in uint32_t id, 2299 __in size_t n); 2300 2301 #define EFX_BUF_TBL_SIZE 0x20000 2302 2303 #define EFX_BUF_SIZE 4096 2304 2305 /* EV */ 2306 2307 typedef struct efx_evq_s efx_evq_t; 2308 2309 #if EFSYS_OPT_QSTATS 2310 2311 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */ 2312 typedef enum efx_ev_qstat_e { 2313 EV_ALL, 2314 EV_RX, 2315 EV_RX_OK, 2316 EV_RX_FRM_TRUNC, 2317 EV_RX_TOBE_DISC, 2318 EV_RX_PAUSE_FRM_ERR, 2319 EV_RX_BUF_OWNER_ID_ERR, 2320 EV_RX_IPV4_HDR_CHKSUM_ERR, 2321 EV_RX_TCP_UDP_CHKSUM_ERR, 2322 EV_RX_ETH_CRC_ERR, 2323 EV_RX_IP_FRAG_ERR, 2324 EV_RX_MCAST_PKT, 2325 EV_RX_MCAST_HASH_MATCH, 2326 EV_RX_TCP_IPV4, 2327 EV_RX_TCP_IPV6, 2328 EV_RX_UDP_IPV4, 2329 EV_RX_UDP_IPV6, 2330 EV_RX_OTHER_IPV4, 2331 EV_RX_OTHER_IPV6, 2332 EV_RX_NON_IP, 2333 EV_RX_BATCH, 2334 EV_TX, 2335 EV_TX_WQ_FF_FULL, 2336 EV_TX_PKT_ERR, 2337 EV_TX_PKT_TOO_BIG, 2338 EV_TX_UNEXPECTED, 2339 EV_GLOBAL, 2340 EV_GLOBAL_MNT, 2341 EV_DRIVER, 2342 EV_DRIVER_SRM_UPD_DONE, 2343 EV_DRIVER_TX_DESCQ_FLS_DONE, 2344 EV_DRIVER_RX_DESCQ_FLS_DONE, 2345 EV_DRIVER_RX_DESCQ_FLS_FAILED, 2346 EV_DRIVER_RX_DSC_ERROR, 2347 EV_DRIVER_TX_DSC_ERROR, 2348 EV_DRV_GEN, 2349 EV_MCDI_RESPONSE, 2350 EV_RX_PARSE_INCOMPLETE, 2351 EV_NQSTATS 2352 } efx_ev_qstat_t; 2353 2354 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 2355 2356 #endif /* EFSYS_OPT_QSTATS */ 2357 2358 LIBEFX_API 2359 extern __checkReturn efx_rc_t 2360 efx_ev_init( 2361 __in efx_nic_t *enp); 2362 2363 LIBEFX_API 2364 extern void 2365 efx_ev_fini( 2366 __in efx_nic_t *enp); 2367 2368 LIBEFX_API 2369 extern __checkReturn size_t 2370 efx_evq_size( 2371 __in const efx_nic_t *enp, 2372 __in unsigned int ndescs, 2373 __in uint32_t flags); 2374 2375 LIBEFX_API 2376 extern __checkReturn unsigned int 2377 efx_evq_nbufs( 2378 __in const efx_nic_t *enp, 2379 __in unsigned int ndescs, 2380 __in uint32_t flags); 2381 2382 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 2383 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 2384 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 2385 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 2386 2387 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 2388 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 2389 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 2390 2391 /* 2392 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more 2393 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in 2394 * NO_CONT_EV mode". 2395 * 2396 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set, 2397 * which is the case when an event queue is set to THROUGHPUT mode. 2398 */ 2399 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10) 2400 2401 /* Configure EVQ for extended width events (EF100 only) */ 2402 #define EFX_EVQ_FLAGS_EXTENDED_WIDTH (0x20) 2403 2404 2405 LIBEFX_API 2406 extern __checkReturn efx_rc_t 2407 efx_ev_qcreate( 2408 __in efx_nic_t *enp, 2409 __in unsigned int index, 2410 __in efsys_mem_t *esmp, 2411 __in size_t ndescs, 2412 __in uint32_t id, 2413 __in uint32_t us, 2414 __in uint32_t flags, 2415 __deref_out efx_evq_t **eepp); 2416 2417 LIBEFX_API 2418 extern __checkReturn efx_rc_t 2419 efx_ev_qcreate_irq( 2420 __in efx_nic_t *enp, 2421 __in unsigned int index, 2422 __in efsys_mem_t *esmp, 2423 __in size_t ndescs, 2424 __in uint32_t id, 2425 __in uint32_t us, 2426 __in uint32_t flags, 2427 __in uint32_t irq, 2428 __deref_out efx_evq_t **eepp); 2429 2430 LIBEFX_API 2431 extern void 2432 efx_ev_qpost( 2433 __in efx_evq_t *eep, 2434 __in uint16_t data); 2435 2436 typedef __checkReturn boolean_t 2437 (*efx_initialized_ev_t)( 2438 __in_opt void *arg); 2439 2440 #define EFX_PKT_UNICAST 0x0004 2441 #define EFX_PKT_START 0x0008 2442 2443 #define EFX_PKT_VLAN_TAGGED 0x0010 2444 #define EFX_CKSUM_TCPUDP 0x0020 2445 #define EFX_CKSUM_IPV4 0x0040 2446 #define EFX_PKT_CONT 0x0080 2447 2448 #define EFX_CHECK_VLAN 0x0100 2449 #define EFX_PKT_TCP 0x0200 2450 #define EFX_PKT_UDP 0x0400 2451 #define EFX_PKT_IPV4 0x0800 2452 2453 #define EFX_PKT_IPV6 0x1000 2454 #define EFX_PKT_PREFIX_LEN 0x2000 2455 #define EFX_ADDR_MISMATCH 0x4000 2456 #define EFX_DISCARD 0x8000 2457 2458 /* 2459 * The following flags are used only for packed stream 2460 * mode. The values for the flags are reused to fit into 16 bit, 2461 * since EFX_PKT_START and EFX_PKT_CONT are never used in 2462 * packed stream mode 2463 */ 2464 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START 2465 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT 2466 2467 2468 #define EFX_EV_RX_NLABELS 32 2469 #define EFX_EV_TX_NLABELS 32 2470 2471 typedef __checkReturn boolean_t 2472 (*efx_rx_ev_t)( 2473 __in_opt void *arg, 2474 __in uint32_t label, 2475 __in uint32_t id, 2476 __in uint32_t size, 2477 __in uint16_t flags); 2478 2479 typedef __checkReturn boolean_t 2480 (*efx_rx_packets_ev_t)( 2481 __in_opt void *arg, 2482 __in uint32_t label, 2483 __in unsigned int num_packets, 2484 __in uint32_t flags); 2485 2486 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2487 2488 /* 2489 * Packed stream mode is documented in SF-112241-TC. 2490 * The general idea is that, instead of putting each incoming 2491 * packet into a separate buffer which is specified in a RX 2492 * descriptor, a large buffer is provided to the hardware and 2493 * packets are put there in a continuous stream. 2494 * The main advantage of such an approach is that RX queue refilling 2495 * happens much less frequently. 2496 * 2497 * Equal stride packed stream mode is documented in SF-119419-TC. 2498 * The general idea is to utilize advantages of the packed stream, 2499 * but avoid indirection in packets representation. 2500 * The main advantage of such an approach is that RX queue refilling 2501 * happens much less frequently and packets buffers are independent 2502 * from upper layers point of view. 2503 */ 2504 2505 typedef __checkReturn boolean_t 2506 (*efx_rx_ps_ev_t)( 2507 __in_opt void *arg, 2508 __in uint32_t label, 2509 __in uint32_t id, 2510 __in uint32_t pkt_count, 2511 __in uint16_t flags); 2512 2513 #endif 2514 2515 typedef __checkReturn boolean_t 2516 (*efx_tx_ev_t)( 2517 __in_opt void *arg, 2518 __in uint32_t label, 2519 __in uint32_t id); 2520 2521 typedef __checkReturn boolean_t 2522 (*efx_tx_ndescs_ev_t)( 2523 __in_opt void *arg, 2524 __in uint32_t label, 2525 __in unsigned int ndescs); 2526 2527 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 2528 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 2529 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 2530 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 2531 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 2532 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 2533 #define EFX_EXCEPTION_RX_ERROR 0x00000007 2534 #define EFX_EXCEPTION_TX_ERROR 0x00000008 2535 #define EFX_EXCEPTION_EV_ERROR 0x00000009 2536 2537 typedef __checkReturn boolean_t 2538 (*efx_exception_ev_t)( 2539 __in_opt void *arg, 2540 __in uint32_t label, 2541 __in uint32_t data); 2542 2543 typedef __checkReturn boolean_t 2544 (*efx_rxq_flush_done_ev_t)( 2545 __in_opt void *arg, 2546 __in uint32_t rxq_index); 2547 2548 typedef __checkReturn boolean_t 2549 (*efx_rxq_flush_failed_ev_t)( 2550 __in_opt void *arg, 2551 __in uint32_t rxq_index); 2552 2553 typedef __checkReturn boolean_t 2554 (*efx_txq_flush_done_ev_t)( 2555 __in_opt void *arg, 2556 __in uint32_t txq_index); 2557 2558 typedef __checkReturn boolean_t 2559 (*efx_software_ev_t)( 2560 __in_opt void *arg, 2561 __in uint16_t magic); 2562 2563 typedef __checkReturn boolean_t 2564 (*efx_sram_ev_t)( 2565 __in_opt void *arg, 2566 __in uint32_t code); 2567 2568 #define EFX_SRAM_CLEAR 0 2569 #define EFX_SRAM_UPDATE 1 2570 #define EFX_SRAM_ILLEGAL_CLEAR 2 2571 2572 typedef __checkReturn boolean_t 2573 (*efx_wake_up_ev_t)( 2574 __in_opt void *arg, 2575 __in uint32_t label); 2576 2577 typedef __checkReturn boolean_t 2578 (*efx_timer_ev_t)( 2579 __in_opt void *arg, 2580 __in uint32_t label); 2581 2582 typedef __checkReturn boolean_t 2583 (*efx_link_change_ev_t)( 2584 __in_opt void *arg, 2585 __in efx_link_mode_t link_mode); 2586 2587 #if EFSYS_OPT_MON_STATS 2588 2589 typedef __checkReturn boolean_t 2590 (*efx_monitor_ev_t)( 2591 __in_opt void *arg, 2592 __in efx_mon_stat_t id, 2593 __in efx_mon_stat_value_t value); 2594 2595 #endif /* EFSYS_OPT_MON_STATS */ 2596 2597 #if EFSYS_OPT_MAC_STATS 2598 2599 typedef __checkReturn boolean_t 2600 (*efx_mac_stats_ev_t)( 2601 __in_opt void *arg, 2602 __in uint32_t generation); 2603 2604 #endif /* EFSYS_OPT_MAC_STATS */ 2605 2606 #if EFSYS_OPT_DESC_PROXY 2607 2608 /* 2609 * NOTE: This callback returns the raw descriptor data, which has not been 2610 * converted to host endian. The callback must use the EFX_OWORD macros 2611 * to extract the descriptor fields as host endian values. 2612 */ 2613 typedef __checkReturn boolean_t 2614 (*efx_desc_proxy_txq_desc_ev_t)( 2615 __in_opt void *arg, 2616 __in uint16_t vi_id, 2617 __in efx_oword_t txq_desc); 2618 2619 /* 2620 * NOTE: This callback returns the raw descriptor data, which has not been 2621 * converted to host endian. The callback must use the EFX_OWORD macros 2622 * to extract the descriptor fields as host endian values. 2623 */ 2624 typedef __checkReturn boolean_t 2625 (*efx_desc_proxy_virtq_desc_ev_t)( 2626 __in_opt void *arg, 2627 __in uint16_t vi_id, 2628 __in uint16_t avail, 2629 __in efx_oword_t virtq_desc); 2630 2631 #endif /* EFSYS_OPT_DESC_PROXY */ 2632 2633 typedef struct efx_ev_callbacks_s { 2634 efx_initialized_ev_t eec_initialized; 2635 efx_rx_ev_t eec_rx; 2636 efx_rx_packets_ev_t eec_rx_packets; 2637 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2638 efx_rx_ps_ev_t eec_rx_ps; 2639 #endif 2640 efx_tx_ev_t eec_tx; 2641 efx_tx_ndescs_ev_t eec_tx_ndescs; 2642 efx_exception_ev_t eec_exception; 2643 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 2644 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 2645 efx_txq_flush_done_ev_t eec_txq_flush_done; 2646 efx_software_ev_t eec_software; 2647 efx_sram_ev_t eec_sram; 2648 efx_wake_up_ev_t eec_wake_up; 2649 efx_timer_ev_t eec_timer; 2650 efx_link_change_ev_t eec_link_change; 2651 #if EFSYS_OPT_MON_STATS 2652 efx_monitor_ev_t eec_monitor; 2653 #endif /* EFSYS_OPT_MON_STATS */ 2654 #if EFSYS_OPT_MAC_STATS 2655 efx_mac_stats_ev_t eec_mac_stats; 2656 #endif /* EFSYS_OPT_MAC_STATS */ 2657 #if EFSYS_OPT_DESC_PROXY 2658 efx_desc_proxy_txq_desc_ev_t eec_desc_proxy_txq_desc; 2659 efx_desc_proxy_virtq_desc_ev_t eec_desc_proxy_virtq_desc; 2660 #endif /* EFSYS_OPT_DESC_PROXY */ 2661 2662 } efx_ev_callbacks_t; 2663 2664 LIBEFX_API 2665 extern __checkReturn boolean_t 2666 efx_ev_qpending( 2667 __in efx_evq_t *eep, 2668 __in unsigned int count); 2669 2670 #if EFSYS_OPT_EV_PREFETCH 2671 2672 LIBEFX_API 2673 extern void 2674 efx_ev_qprefetch( 2675 __in efx_evq_t *eep, 2676 __in unsigned int count); 2677 2678 #endif /* EFSYS_OPT_EV_PREFETCH */ 2679 2680 LIBEFX_API 2681 extern void 2682 efx_ev_qcreate_check_init_done( 2683 __in efx_evq_t *eep, 2684 __in const efx_ev_callbacks_t *eecp, 2685 __in_opt void *arg); 2686 2687 LIBEFX_API 2688 extern void 2689 efx_ev_qpoll( 2690 __in efx_evq_t *eep, 2691 __inout unsigned int *countp, 2692 __in const efx_ev_callbacks_t *eecp, 2693 __in_opt void *arg); 2694 2695 LIBEFX_API 2696 extern __checkReturn efx_rc_t 2697 efx_ev_usecs_to_ticks( 2698 __in efx_nic_t *enp, 2699 __in unsigned int usecs, 2700 __out unsigned int *ticksp); 2701 2702 LIBEFX_API 2703 extern __checkReturn efx_rc_t 2704 efx_ev_qmoderate( 2705 __in efx_evq_t *eep, 2706 __in unsigned int us); 2707 2708 LIBEFX_API 2709 extern __checkReturn efx_rc_t 2710 efx_ev_qprime( 2711 __in efx_evq_t *eep, 2712 __in unsigned int count); 2713 2714 #if EFSYS_OPT_QSTATS 2715 2716 #if EFSYS_OPT_NAMES 2717 2718 LIBEFX_API 2719 extern const char * 2720 efx_ev_qstat_name( 2721 __in efx_nic_t *enp, 2722 __in unsigned int id); 2723 2724 #endif /* EFSYS_OPT_NAMES */ 2725 2726 LIBEFX_API 2727 extern void 2728 efx_ev_qstats_update( 2729 __in efx_evq_t *eep, 2730 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 2731 2732 #endif /* EFSYS_OPT_QSTATS */ 2733 2734 LIBEFX_API 2735 extern void 2736 efx_ev_qdestroy( 2737 __in efx_evq_t *eep); 2738 2739 /* RX */ 2740 2741 LIBEFX_API 2742 extern __checkReturn efx_rc_t 2743 efx_rx_init( 2744 __inout efx_nic_t *enp); 2745 2746 LIBEFX_API 2747 extern void 2748 efx_rx_fini( 2749 __in efx_nic_t *enp); 2750 2751 #if EFSYS_OPT_RX_SCATTER 2752 LIBEFX_API 2753 extern __checkReturn efx_rc_t 2754 efx_rx_scatter_enable( 2755 __in efx_nic_t *enp, 2756 __in unsigned int buf_size); 2757 #endif /* EFSYS_OPT_RX_SCATTER */ 2758 2759 /* Handle to represent use of the default RSS context. */ 2760 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff 2761 2762 #if EFSYS_OPT_RX_SCALE 2763 2764 typedef enum efx_rx_hash_alg_e { 2765 EFX_RX_HASHALG_LFSR = 0, 2766 EFX_RX_HASHALG_TOEPLITZ, 2767 EFX_RX_HASHALG_PACKED_STREAM, 2768 EFX_RX_NHASHALGS 2769 } efx_rx_hash_alg_t; 2770 2771 /* 2772 * Legacy hash type flags. 2773 * 2774 * They represent standard tuples for distinct traffic classes. 2775 */ 2776 #define EFX_RX_HASH_IPV4 (1U << 0) 2777 #define EFX_RX_HASH_TCPIPV4 (1U << 1) 2778 #define EFX_RX_HASH_IPV6 (1U << 2) 2779 #define EFX_RX_HASH_TCPIPV6 (1U << 3) 2780 2781 #define EFX_RX_HASH_LEGACY_MASK \ 2782 (EFX_RX_HASH_IPV4 | \ 2783 EFX_RX_HASH_TCPIPV4 | \ 2784 EFX_RX_HASH_IPV6 | \ 2785 EFX_RX_HASH_TCPIPV6) 2786 2787 /* 2788 * The type of the argument used by efx_rx_scale_mode_set() to 2789 * provide a means for the client drivers to configure hashing. 2790 * 2791 * A properly constructed value can either be: 2792 * - a combination of legacy flags 2793 * - a combination of EFX_RX_HASH() flags 2794 */ 2795 typedef uint32_t efx_rx_hash_type_t; 2796 2797 typedef enum efx_rx_hash_support_e { 2798 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 2799 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 2800 } efx_rx_hash_support_t; 2801 2802 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */ 2803 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 2804 #define EFX_MAXRSS 64 /* RX indirection entry range */ 2805 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 2806 2807 typedef enum efx_rx_scale_context_type_e { 2808 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */ 2809 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 2810 EFX_RX_SCALE_SHARED, /* Read-only key/indirection table */ 2811 EFX_RX_SCALE_EVEN_SPREAD, /* No indirection table, writable key */ 2812 } efx_rx_scale_context_type_t; 2813 2814 /* 2815 * Traffic classes eligible for hash computation. 2816 * 2817 * Select packet headers used in computing the receive hash. 2818 * This uses the same encoding as the RSS_MODES field of 2819 * MC_CMD_RSS_CONTEXT_SET_FLAGS. 2820 */ 2821 #define EFX_RX_CLASS_IPV4_TCP_LBN 8 2822 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4 2823 #define EFX_RX_CLASS_IPV4_UDP_LBN 12 2824 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4 2825 #define EFX_RX_CLASS_IPV4_LBN 16 2826 #define EFX_RX_CLASS_IPV4_WIDTH 4 2827 #define EFX_RX_CLASS_IPV6_TCP_LBN 20 2828 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4 2829 #define EFX_RX_CLASS_IPV6_UDP_LBN 24 2830 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4 2831 #define EFX_RX_CLASS_IPV6_LBN 28 2832 #define EFX_RX_CLASS_IPV6_WIDTH 4 2833 2834 #define EFX_RX_NCLASSES 6 2835 2836 /* 2837 * Ancillary flags used to construct generic hash tuples. 2838 * This uses the same encoding as RSS_MODE_HASH_SELECTOR. 2839 */ 2840 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0) 2841 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1) 2842 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2) 2843 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3) 2844 2845 /* 2846 * Generic hash tuples. 2847 * 2848 * They express combinations of packet fields 2849 * which can contribute to the hash value for 2850 * a particular traffic class. 2851 */ 2852 #define EFX_RX_CLASS_HASH_DISABLE 0 2853 2854 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR 2855 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR 2856 2857 #define EFX_RX_CLASS_HASH_2TUPLE \ 2858 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2859 EFX_RX_CLASS_HASH_DST_ADDR) 2860 2861 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \ 2862 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2863 EFX_RX_CLASS_HASH_SRC_PORT) 2864 2865 #define EFX_RX_CLASS_HASH_2TUPLE_DST \ 2866 (EFX_RX_CLASS_HASH_DST_ADDR | \ 2867 EFX_RX_CLASS_HASH_DST_PORT) 2868 2869 #define EFX_RX_CLASS_HASH_4TUPLE \ 2870 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2871 EFX_RX_CLASS_HASH_DST_ADDR | \ 2872 EFX_RX_CLASS_HASH_SRC_PORT | \ 2873 EFX_RX_CLASS_HASH_DST_PORT) 2874 2875 #define EFX_RX_CLASS_HASH_NTUPLES 7 2876 2877 /* 2878 * Hash flag constructor. 2879 * 2880 * Resulting flags encode hash tuples for specific traffic classes. 2881 * The client drivers are encouraged to use these flags to form 2882 * a hash type value. 2883 */ 2884 #define EFX_RX_HASH(_class, _tuple) \ 2885 EFX_INSERT_FIELD_NATIVE32(0, 31, \ 2886 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple) 2887 2888 /* 2889 * The maximum number of EFX_RX_HASH() flags. 2890 */ 2891 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES) 2892 2893 LIBEFX_API 2894 extern __checkReturn efx_rc_t 2895 efx_rx_scale_hash_flags_get( 2896 __in efx_nic_t *enp, 2897 __in efx_rx_hash_alg_t hash_alg, 2898 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp, 2899 __in unsigned int max_nflags, 2900 __out unsigned int *nflagsp); 2901 2902 LIBEFX_API 2903 extern __checkReturn efx_rc_t 2904 efx_rx_hash_default_support_get( 2905 __in efx_nic_t *enp, 2906 __out efx_rx_hash_support_t *supportp); 2907 2908 2909 LIBEFX_API 2910 extern __checkReturn efx_rc_t 2911 efx_rx_scale_default_support_get( 2912 __in efx_nic_t *enp, 2913 __out efx_rx_scale_context_type_t *typep); 2914 2915 LIBEFX_API 2916 extern __checkReturn efx_rc_t 2917 efx_rx_scale_context_alloc( 2918 __in efx_nic_t *enp, 2919 __in efx_rx_scale_context_type_t type, 2920 __in uint32_t num_queues, 2921 __out uint32_t *rss_contextp); 2922 2923 LIBEFX_API 2924 extern __checkReturn efx_rc_t 2925 efx_rx_scale_context_alloc_v2( 2926 __in efx_nic_t *enp, 2927 __in efx_rx_scale_context_type_t type, 2928 __in uint32_t num_queues, 2929 __in uint32_t table_nentries, 2930 __out uint32_t *rss_contextp); 2931 2932 LIBEFX_API 2933 extern __checkReturn efx_rc_t 2934 efx_rx_scale_context_free( 2935 __in efx_nic_t *enp, 2936 __in uint32_t rss_context); 2937 2938 LIBEFX_API 2939 extern __checkReturn efx_rc_t 2940 efx_rx_scale_mode_set( 2941 __in efx_nic_t *enp, 2942 __in uint32_t rss_context, 2943 __in efx_rx_hash_alg_t alg, 2944 __in efx_rx_hash_type_t type, 2945 __in boolean_t insert); 2946 2947 LIBEFX_API 2948 extern __checkReturn efx_rc_t 2949 efx_rx_scale_tbl_set( 2950 __in efx_nic_t *enp, 2951 __in uint32_t rss_context, 2952 __in_ecount(nentries) unsigned int *table, 2953 __in size_t nentries); 2954 2955 LIBEFX_API 2956 extern __checkReturn efx_rc_t 2957 efx_rx_scale_key_set( 2958 __in efx_nic_t *enp, 2959 __in uint32_t rss_context, 2960 __in_ecount(n) uint8_t *key, 2961 __in size_t n); 2962 2963 LIBEFX_API 2964 extern __checkReturn uint32_t 2965 efx_pseudo_hdr_hash_get( 2966 __in efx_rxq_t *erp, 2967 __in efx_rx_hash_alg_t func, 2968 __in uint8_t *buffer); 2969 2970 #endif /* EFSYS_OPT_RX_SCALE */ 2971 2972 LIBEFX_API 2973 extern __checkReturn efx_rc_t 2974 efx_pseudo_hdr_pkt_length_get( 2975 __in efx_rxq_t *erp, 2976 __in uint8_t *buffer, 2977 __out uint16_t *pkt_lengthp); 2978 2979 LIBEFX_API 2980 extern __checkReturn size_t 2981 efx_rxq_size( 2982 __in const efx_nic_t *enp, 2983 __in unsigned int ndescs); 2984 2985 LIBEFX_API 2986 extern __checkReturn unsigned int 2987 efx_rxq_nbufs( 2988 __in const efx_nic_t *enp, 2989 __in unsigned int ndescs); 2990 2991 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2992 2993 /* 2994 * libefx representation of the Rx prefix layout information. 2995 * 2996 * The information may be used inside libefx to implement Rx prefix fields 2997 * accessors and by drivers which process Rx prefix itself. 2998 */ 2999 3000 /* 3001 * All known Rx prefix fields. 3002 * 3003 * An Rx prefix may have a subset of these fields. 3004 */ 3005 typedef enum efx_rx_prefix_field_e { 3006 EFX_RX_PREFIX_FIELD_LENGTH = 0, 3007 EFX_RX_PREFIX_FIELD_ORIG_LENGTH, 3008 EFX_RX_PREFIX_FIELD_CLASS, 3009 EFX_RX_PREFIX_FIELD_RSS_HASH, 3010 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID, 3011 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP, 3012 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI, 3013 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI, 3014 EFX_RX_PREFIX_FIELD_USER_FLAG, 3015 EFX_RX_PREFIX_FIELD_USER_MARK, 3016 EFX_RX_PREFIX_FIELD_USER_MARK_VALID, 3017 EFX_RX_PREFIX_FIELD_CSUM_FRAME, 3018 EFX_RX_PREFIX_FIELD_INGRESS_VPORT, 3019 EFX_RX_PREFIX_FIELD_INGRESS_MPORT = EFX_RX_PREFIX_FIELD_INGRESS_VPORT, 3020 EFX_RX_PREFIX_NFIELDS 3021 } efx_rx_prefix_field_t; 3022 3023 /* 3024 * Location and endianness of a field in Rx prefix. 3025 * 3026 * If width is zero, the field is not present. 3027 */ 3028 typedef struct efx_rx_prefix_field_info_s { 3029 uint16_t erpfi_offset_bits; 3030 uint8_t erpfi_width_bits; 3031 boolean_t erpfi_big_endian; 3032 } efx_rx_prefix_field_info_t; 3033 3034 /* Helper macro to define Rx prefix fields */ 3035 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \ 3036 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \ 3037 .erpfi_offset_bits = EFX_LOW_BIT(_field), \ 3038 .erpfi_width_bits = EFX_WIDTH(_field), \ 3039 .erpfi_big_endian = (_big_endian), \ 3040 } 3041 3042 typedef struct efx_rx_prefix_layout_s { 3043 uint32_t erpl_id; 3044 uint8_t erpl_length; 3045 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS]; 3046 } efx_rx_prefix_layout_t; 3047 3048 /* 3049 * Helper function to find out a bit mask of wanted but not available 3050 * Rx prefix fields. 3051 * 3052 * A field is considered as not available if any parameter mismatch. 3053 */ 3054 LIBEFX_API 3055 extern __checkReturn uint32_t 3056 efx_rx_prefix_layout_check( 3057 __in const efx_rx_prefix_layout_t *available, 3058 __in const efx_rx_prefix_layout_t *wanted); 3059 3060 LIBEFX_API 3061 extern __checkReturn efx_rc_t 3062 efx_rx_prefix_get_layout( 3063 __in const efx_rxq_t *erp, 3064 __out efx_rx_prefix_layout_t *erplp); 3065 3066 typedef enum efx_rxq_type_e { 3067 EFX_RXQ_TYPE_DEFAULT, 3068 EFX_RXQ_TYPE_PACKED_STREAM, 3069 EFX_RXQ_TYPE_ES_SUPER_BUFFER, 3070 EFX_RXQ_NTYPES 3071 } efx_rxq_type_t; 3072 3073 /* 3074 * Dummy flag to be used instead of 0 to make it clear that the argument 3075 * is receive queue flags. 3076 */ 3077 #define EFX_RXQ_FLAG_NONE 0x0 3078 #define EFX_RXQ_FLAG_SCATTER 0x1 3079 /* 3080 * If tunnels are supported and Rx event can provide information about 3081 * either outer or inner packet classes (e.g. SFN8xxx adapters with 3082 * full-feature firmware variant running), outer classes are requested by 3083 * default. However, if the driver supports tunnels, the flag allows to 3084 * request inner classes which are required to be able to interpret inner 3085 * Rx checksum offload results. 3086 */ 3087 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2 3088 /* 3089 * Request delivery of the RSS hash calculated by HW to be used by 3090 * the driver. 3091 */ 3092 #define EFX_RXQ_FLAG_RSS_HASH 0x4 3093 /* 3094 * Request ingress mport field in the Rx prefix of a queue. 3095 */ 3096 #define EFX_RXQ_FLAG_INGRESS_MPORT 0x8 3097 /* 3098 * Request user mark field in the Rx prefix of a queue. 3099 */ 3100 #define EFX_RXQ_FLAG_USER_MARK 0x10 3101 /* 3102 * Request user flag field in the Rx prefix of a queue. 3103 */ 3104 #define EFX_RXQ_FLAG_USER_FLAG 0x20 3105 3106 LIBEFX_API 3107 extern __checkReturn efx_rc_t 3108 efx_rx_qcreate( 3109 __in efx_nic_t *enp, 3110 __in unsigned int index, 3111 __in unsigned int label, 3112 __in efx_rxq_type_t type, 3113 __in size_t buf_size, 3114 __in efsys_mem_t *esmp, 3115 __in size_t ndescs, 3116 __in uint32_t id, 3117 __in unsigned int flags, 3118 __in efx_evq_t *eep, 3119 __deref_out efx_rxq_t **erpp); 3120 3121 #if EFSYS_OPT_RX_PACKED_STREAM 3122 3123 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024) 3124 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024) 3125 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024) 3126 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024) 3127 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024) 3128 3129 LIBEFX_API 3130 extern __checkReturn efx_rc_t 3131 efx_rx_qcreate_packed_stream( 3132 __in efx_nic_t *enp, 3133 __in unsigned int index, 3134 __in unsigned int label, 3135 __in uint32_t ps_buf_size, 3136 __in efsys_mem_t *esmp, 3137 __in size_t ndescs, 3138 __in efx_evq_t *eep, 3139 __deref_out efx_rxq_t **erpp); 3140 3141 #endif 3142 3143 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 3144 3145 /* Maximum head-of-line block timeout in nanoseconds */ 3146 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000) 3147 3148 LIBEFX_API 3149 extern __checkReturn efx_rc_t 3150 efx_rx_qcreate_es_super_buffer( 3151 __in efx_nic_t *enp, 3152 __in unsigned int index, 3153 __in unsigned int label, 3154 __in uint32_t n_bufs_per_desc, 3155 __in uint32_t max_dma_len, 3156 __in uint32_t buf_stride, 3157 __in uint32_t hol_block_timeout, 3158 __in efsys_mem_t *esmp, 3159 __in size_t ndescs, 3160 __in unsigned int flags, 3161 __in efx_evq_t *eep, 3162 __deref_out efx_rxq_t **erpp); 3163 3164 #endif 3165 3166 typedef struct efx_buffer_s { 3167 efsys_dma_addr_t eb_addr; 3168 size_t eb_size; 3169 boolean_t eb_eop; 3170 } efx_buffer_t; 3171 3172 typedef struct efx_desc_s { 3173 efx_qword_t ed_eq; 3174 } efx_desc_t; 3175 3176 LIBEFX_API 3177 extern void 3178 efx_rx_qpost( 3179 __in efx_rxq_t *erp, 3180 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 3181 __in size_t size, 3182 __in unsigned int ndescs, 3183 __in unsigned int completed, 3184 __in unsigned int added); 3185 3186 LIBEFX_API 3187 extern void 3188 efx_rx_qpush( 3189 __in efx_rxq_t *erp, 3190 __in unsigned int added, 3191 __inout unsigned int *pushedp); 3192 3193 #if EFSYS_OPT_RX_PACKED_STREAM 3194 3195 LIBEFX_API 3196 extern void 3197 efx_rx_qpush_ps_credits( 3198 __in efx_rxq_t *erp); 3199 3200 LIBEFX_API 3201 extern __checkReturn uint8_t * 3202 efx_rx_qps_packet_info( 3203 __in efx_rxq_t *erp, 3204 __in uint8_t *buffer, 3205 __in uint32_t buffer_length, 3206 __in uint32_t current_offset, 3207 __out uint16_t *lengthp, 3208 __out uint32_t *next_offsetp, 3209 __out uint32_t *timestamp); 3210 #endif 3211 3212 LIBEFX_API 3213 extern __checkReturn efx_rc_t 3214 efx_rx_qflush( 3215 __in efx_rxq_t *erp); 3216 3217 LIBEFX_API 3218 extern void 3219 efx_rx_qenable( 3220 __in efx_rxq_t *erp); 3221 3222 LIBEFX_API 3223 extern void 3224 efx_rx_qdestroy( 3225 __in efx_rxq_t *erp); 3226 3227 /* TX */ 3228 3229 typedef struct efx_txq_s efx_txq_t; 3230 3231 #if EFSYS_OPT_QSTATS 3232 3233 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 3234 typedef enum efx_tx_qstat_e { 3235 TX_POST, 3236 TX_POST_PIO, 3237 TX_NQSTATS 3238 } efx_tx_qstat_t; 3239 3240 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 3241 3242 #endif /* EFSYS_OPT_QSTATS */ 3243 3244 LIBEFX_API 3245 extern __checkReturn efx_rc_t 3246 efx_tx_init( 3247 __in efx_nic_t *enp); 3248 3249 LIBEFX_API 3250 extern void 3251 efx_tx_fini( 3252 __in efx_nic_t *enp); 3253 3254 LIBEFX_API 3255 extern __checkReturn size_t 3256 efx_txq_size( 3257 __in const efx_nic_t *enp, 3258 __in unsigned int ndescs); 3259 3260 LIBEFX_API 3261 extern __checkReturn unsigned int 3262 efx_txq_nbufs( 3263 __in const efx_nic_t *enp, 3264 __in unsigned int ndescs); 3265 3266 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 3267 3268 #define EFX_TXQ_CKSUM_IPV4 0x0001 3269 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 3270 #define EFX_TXQ_FATSOV2 0x0004 3271 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008 3272 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010 3273 3274 LIBEFX_API 3275 extern __checkReturn efx_rc_t 3276 efx_tx_qcreate( 3277 __in efx_nic_t *enp, 3278 __in unsigned int index, 3279 __in unsigned int label, 3280 __in efsys_mem_t *esmp, 3281 __in size_t n, 3282 __in uint32_t id, 3283 __in uint16_t flags, 3284 __in efx_evq_t *eep, 3285 __deref_out efx_txq_t **etpp, 3286 __out unsigned int *addedp); 3287 3288 LIBEFX_API 3289 extern __checkReturn efx_rc_t 3290 efx_tx_qpost( 3291 __in efx_txq_t *etp, 3292 __in_ecount(ndescs) efx_buffer_t *eb, 3293 __in unsigned int ndescs, 3294 __in unsigned int completed, 3295 __inout unsigned int *addedp); 3296 3297 LIBEFX_API 3298 extern __checkReturn efx_rc_t 3299 efx_tx_qpace( 3300 __in efx_txq_t *etp, 3301 __in unsigned int ns); 3302 3303 LIBEFX_API 3304 extern void 3305 efx_tx_qpush( 3306 __in efx_txq_t *etp, 3307 __in unsigned int added, 3308 __in unsigned int pushed); 3309 3310 LIBEFX_API 3311 extern __checkReturn efx_rc_t 3312 efx_tx_qflush( 3313 __in efx_txq_t *etp); 3314 3315 LIBEFX_API 3316 extern void 3317 efx_tx_qenable( 3318 __in efx_txq_t *etp); 3319 3320 LIBEFX_API 3321 extern __checkReturn efx_rc_t 3322 efx_tx_qpio_enable( 3323 __in efx_txq_t *etp); 3324 3325 LIBEFX_API 3326 extern void 3327 efx_tx_qpio_disable( 3328 __in efx_txq_t *etp); 3329 3330 LIBEFX_API 3331 extern __checkReturn efx_rc_t 3332 efx_tx_qpio_write( 3333 __in efx_txq_t *etp, 3334 __in_ecount(buf_length) uint8_t *buffer, 3335 __in size_t buf_length, 3336 __in size_t pio_buf_offset); 3337 3338 LIBEFX_API 3339 extern __checkReturn efx_rc_t 3340 efx_tx_qpio_post( 3341 __in efx_txq_t *etp, 3342 __in size_t pkt_length, 3343 __in unsigned int completed, 3344 __inout unsigned int *addedp); 3345 3346 LIBEFX_API 3347 extern __checkReturn efx_rc_t 3348 efx_tx_qdesc_post( 3349 __in efx_txq_t *etp, 3350 __in_ecount(n) efx_desc_t *ed, 3351 __in unsigned int n, 3352 __in unsigned int completed, 3353 __inout unsigned int *addedp); 3354 3355 LIBEFX_API 3356 extern void 3357 efx_tx_qdesc_dma_create( 3358 __in efx_txq_t *etp, 3359 __in efsys_dma_addr_t addr, 3360 __in size_t size, 3361 __in boolean_t eop, 3362 __out efx_desc_t *edp); 3363 3364 LIBEFX_API 3365 extern void 3366 efx_tx_qdesc_tso_create( 3367 __in efx_txq_t *etp, 3368 __in uint16_t ipv4_id, 3369 __in uint32_t tcp_seq, 3370 __in uint8_t tcp_flags, 3371 __out efx_desc_t *edp); 3372 3373 /* Number of FATSOv2 option descriptors */ 3374 #define EFX_TX_FATSOV2_OPT_NDESCS 2 3375 3376 /* Maximum number of DMA segments per TSO packet (not superframe) */ 3377 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 3378 3379 LIBEFX_API 3380 extern void 3381 efx_tx_qdesc_tso2_create( 3382 __in efx_txq_t *etp, 3383 __in uint16_t ipv4_id, 3384 __in uint16_t outer_ipv4_id, 3385 __in uint32_t tcp_seq, 3386 __in uint16_t tcp_mss, 3387 __out_ecount(count) efx_desc_t *edp, 3388 __in int count); 3389 3390 LIBEFX_API 3391 extern void 3392 efx_tx_qdesc_vlantci_create( 3393 __in efx_txq_t *etp, 3394 __in uint16_t tci, 3395 __out efx_desc_t *edp); 3396 3397 LIBEFX_API 3398 extern void 3399 efx_tx_qdesc_checksum_create( 3400 __in efx_txq_t *etp, 3401 __in uint16_t flags, 3402 __out efx_desc_t *edp); 3403 3404 #if EFSYS_OPT_QSTATS 3405 3406 #if EFSYS_OPT_NAMES 3407 3408 LIBEFX_API 3409 extern const char * 3410 efx_tx_qstat_name( 3411 __in efx_nic_t *etp, 3412 __in unsigned int id); 3413 3414 #endif /* EFSYS_OPT_NAMES */ 3415 3416 LIBEFX_API 3417 extern void 3418 efx_tx_qstats_update( 3419 __in efx_txq_t *etp, 3420 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 3421 3422 #endif /* EFSYS_OPT_QSTATS */ 3423 3424 LIBEFX_API 3425 extern void 3426 efx_tx_qdestroy( 3427 __in efx_txq_t *etp); 3428 3429 3430 /* FILTER */ 3431 3432 #if EFSYS_OPT_FILTER 3433 3434 #define EFX_ETHER_TYPE_IPV4 0x0800 3435 #define EFX_ETHER_TYPE_IPV6 0x86DD 3436 3437 #define EFX_IPPROTO_TCP 6 3438 #define EFX_IPPROTO_UDP 17 3439 #define EFX_IPPROTO_GRE 47 3440 3441 /* Use RSS to spread across multiple queues */ 3442 #define EFX_FILTER_FLAG_RX_RSS 0x01 3443 /* Enable RX scatter */ 3444 #define EFX_FILTER_FLAG_RX_SCATTER 0x02 3445 /* 3446 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 3447 * May only be set by the filter implementation for each type. 3448 * A removal request will restore the automatic filter in its place. 3449 */ 3450 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 3451 /* Filter is for RX */ 3452 #define EFX_FILTER_FLAG_RX 0x08 3453 /* Filter is for TX */ 3454 #define EFX_FILTER_FLAG_TX 0x10 3455 /* Set match flag on the received packet */ 3456 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20 3457 /* Set match mark on the received packet */ 3458 #define EFX_FILTER_FLAG_ACTION_MARK 0x40 3459 3460 typedef uint8_t efx_filter_flags_t; 3461 3462 /* 3463 * Flags which specify the fields to match on. The values are the same as in the 3464 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands. 3465 */ 3466 3467 /* Match by remote IP host address */ 3468 #define EFX_FILTER_MATCH_REM_HOST 0x00000001 3469 /* Match by local IP host address */ 3470 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002 3471 /* Match by remote MAC address */ 3472 #define EFX_FILTER_MATCH_REM_MAC 0x00000004 3473 /* Match by remote TCP/UDP port */ 3474 #define EFX_FILTER_MATCH_REM_PORT 0x00000008 3475 /* Match by remote TCP/UDP port */ 3476 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010 3477 /* Match by local TCP/UDP port */ 3478 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020 3479 /* Match by Ether-type */ 3480 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040 3481 /* Match by inner VLAN ID */ 3482 #define EFX_FILTER_MATCH_INNER_VID 0x00000080 3483 /* Match by outer VLAN ID */ 3484 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100 3485 /* Match by IP transport protocol */ 3486 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200 3487 /* Match by ingress MPORT */ 3488 #define EFX_FILTER_MATCH_MPORT 0x00000400 3489 /* Match by VNI or VSID */ 3490 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800 3491 /* For encapsulated packets, match by inner frame local MAC address */ 3492 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000 3493 /* For encapsulated packets, match all multicast inner frames */ 3494 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000 3495 /* For encapsulated packets, match all unicast inner frames */ 3496 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000 3497 /* 3498 * Match by encap type, this flag does not correspond to 3499 * the MCDI match flags and any unoccupied value may be used 3500 */ 3501 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000 3502 /* Match otherwise-unmatched multicast and broadcast packets */ 3503 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000 3504 /* Match otherwise-unmatched unicast packets */ 3505 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000 3506 3507 typedef uint32_t efx_filter_match_flags_t; 3508 3509 /* Filter priority from lowest to highest */ 3510 typedef enum efx_filter_priority_s { 3511 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device 3512 * address list or hardware 3513 * requirements. This may only be used 3514 * by the filter implementation for 3515 * each NIC type. */ 3516 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 3517 EFX_FILTER_NPRI, 3518 } efx_filter_priority_t; 3519 3520 /* 3521 * FIXME: All these fields are assumed to be in little-endian byte order. 3522 * It may be better for some to be big-endian. See bug42804. 3523 */ 3524 3525 typedef struct efx_filter_spec_s { 3526 efx_filter_match_flags_t efs_match_flags; 3527 uint8_t efs_priority; 3528 efx_filter_flags_t efs_flags; 3529 uint16_t efs_dmaq_id; 3530 uint32_t efs_rss_context; 3531 uint32_t efs_mark; 3532 /* 3533 * Saved lower-priority filter. If it is set, it is restored on 3534 * filter delete operation. 3535 */ 3536 struct efx_filter_spec_s *efs_overridden_spec; 3537 /* Fields below here are hashed for software filter lookup */ 3538 uint16_t efs_outer_vid; 3539 uint16_t efs_inner_vid; 3540 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 3541 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 3542 uint16_t efs_ether_type; 3543 uint8_t efs_ip_proto; 3544 efx_tunnel_protocol_t efs_encap_type; 3545 uint16_t efs_loc_port; 3546 uint16_t efs_rem_port; 3547 efx_oword_t efs_rem_host; 3548 efx_oword_t efs_loc_host; 3549 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN]; 3550 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN]; 3551 uint32_t efs_ingress_mport; 3552 } efx_filter_spec_t; 3553 3554 3555 /* Default values for use in filter specifications */ 3556 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 3557 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 3558 3559 LIBEFX_API 3560 extern __checkReturn efx_rc_t 3561 efx_filter_init( 3562 __in efx_nic_t *enp); 3563 3564 LIBEFX_API 3565 extern void 3566 efx_filter_fini( 3567 __in efx_nic_t *enp); 3568 3569 LIBEFX_API 3570 extern __checkReturn efx_rc_t 3571 efx_filter_insert( 3572 __in efx_nic_t *enp, 3573 __inout efx_filter_spec_t *spec); 3574 3575 LIBEFX_API 3576 extern __checkReturn efx_rc_t 3577 efx_filter_remove( 3578 __in efx_nic_t *enp, 3579 __inout efx_filter_spec_t *spec); 3580 3581 LIBEFX_API 3582 extern __checkReturn efx_rc_t 3583 efx_filter_restore( 3584 __in efx_nic_t *enp); 3585 3586 LIBEFX_API 3587 extern __checkReturn efx_rc_t 3588 efx_filter_supported_filters( 3589 __in efx_nic_t *enp, 3590 __out_ecount(buffer_length) uint32_t *buffer, 3591 __in size_t buffer_length, 3592 __out size_t *list_lengthp); 3593 3594 LIBEFX_API 3595 extern void 3596 efx_filter_spec_init_rx( 3597 __out efx_filter_spec_t *spec, 3598 __in efx_filter_priority_t priority, 3599 __in efx_filter_flags_t flags, 3600 __in efx_rxq_t *erp); 3601 3602 LIBEFX_API 3603 extern void 3604 efx_filter_spec_init_tx( 3605 __out efx_filter_spec_t *spec, 3606 __in efx_txq_t *etp); 3607 3608 LIBEFX_API 3609 extern __checkReturn efx_rc_t 3610 efx_filter_spec_set_ipv4_local( 3611 __inout efx_filter_spec_t *spec, 3612 __in uint8_t proto, 3613 __in uint32_t host, 3614 __in uint16_t port); 3615 3616 LIBEFX_API 3617 extern __checkReturn efx_rc_t 3618 efx_filter_spec_set_ipv4_full( 3619 __inout efx_filter_spec_t *spec, 3620 __in uint8_t proto, 3621 __in uint32_t lhost, 3622 __in uint16_t lport, 3623 __in uint32_t rhost, 3624 __in uint16_t rport); 3625 3626 LIBEFX_API 3627 extern __checkReturn efx_rc_t 3628 efx_filter_spec_set_eth_local( 3629 __inout efx_filter_spec_t *spec, 3630 __in uint16_t vid, 3631 __in const uint8_t *addr); 3632 3633 LIBEFX_API 3634 extern void 3635 efx_filter_spec_set_ether_type( 3636 __inout efx_filter_spec_t *spec, 3637 __in uint16_t ether_type); 3638 3639 LIBEFX_API 3640 extern __checkReturn efx_rc_t 3641 efx_filter_spec_set_uc_def( 3642 __inout efx_filter_spec_t *spec); 3643 3644 LIBEFX_API 3645 extern __checkReturn efx_rc_t 3646 efx_filter_spec_set_mc_def( 3647 __inout efx_filter_spec_t *spec); 3648 3649 typedef enum efx_filter_inner_frame_match_e { 3650 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0, 3651 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST, 3652 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST 3653 } efx_filter_inner_frame_match_t; 3654 3655 LIBEFX_API 3656 extern __checkReturn efx_rc_t 3657 efx_filter_spec_set_encap_type( 3658 __inout efx_filter_spec_t *spec, 3659 __in efx_tunnel_protocol_t encap_type, 3660 __in efx_filter_inner_frame_match_t inner_frame_match); 3661 3662 LIBEFX_API 3663 extern __checkReturn efx_rc_t 3664 efx_filter_spec_set_vxlan( 3665 __inout efx_filter_spec_t *spec, 3666 __in const uint8_t *vni, 3667 __in const uint8_t *inner_addr, 3668 __in const uint8_t *outer_addr); 3669 3670 LIBEFX_API 3671 extern __checkReturn efx_rc_t 3672 efx_filter_spec_set_geneve( 3673 __inout efx_filter_spec_t *spec, 3674 __in const uint8_t *vni, 3675 __in const uint8_t *inner_addr, 3676 __in const uint8_t *outer_addr); 3677 3678 LIBEFX_API 3679 extern __checkReturn efx_rc_t 3680 efx_filter_spec_set_nvgre( 3681 __inout efx_filter_spec_t *spec, 3682 __in const uint8_t *vsid, 3683 __in const uint8_t *inner_addr, 3684 __in const uint8_t *outer_addr); 3685 3686 #if EFSYS_OPT_RX_SCALE 3687 LIBEFX_API 3688 extern __checkReturn efx_rc_t 3689 efx_filter_spec_set_rss_context( 3690 __inout efx_filter_spec_t *spec, 3691 __in uint32_t rss_context); 3692 #endif 3693 #endif /* EFSYS_OPT_FILTER */ 3694 3695 /* HASH */ 3696 3697 LIBEFX_API 3698 extern __checkReturn uint32_t 3699 efx_hash_dwords( 3700 __in_ecount(count) uint32_t const *input, 3701 __in size_t count, 3702 __in uint32_t init); 3703 3704 LIBEFX_API 3705 extern __checkReturn uint32_t 3706 efx_hash_bytes( 3707 __in_ecount(length) uint8_t const *input, 3708 __in size_t length, 3709 __in uint32_t init); 3710 3711 #if EFSYS_OPT_LICENSING 3712 3713 /* LICENSING */ 3714 3715 typedef struct efx_key_stats_s { 3716 uint32_t eks_valid; 3717 uint32_t eks_invalid; 3718 uint32_t eks_blacklisted; 3719 uint32_t eks_unverifiable; 3720 uint32_t eks_wrong_node; 3721 uint32_t eks_licensed_apps_lo; 3722 uint32_t eks_licensed_apps_hi; 3723 uint32_t eks_licensed_features_lo; 3724 uint32_t eks_licensed_features_hi; 3725 } efx_key_stats_t; 3726 3727 LIBEFX_API 3728 extern __checkReturn efx_rc_t 3729 efx_lic_init( 3730 __in efx_nic_t *enp); 3731 3732 LIBEFX_API 3733 extern void 3734 efx_lic_fini( 3735 __in efx_nic_t *enp); 3736 3737 LIBEFX_API 3738 extern __checkReturn boolean_t 3739 efx_lic_check_support( 3740 __in efx_nic_t *enp); 3741 3742 LIBEFX_API 3743 extern __checkReturn efx_rc_t 3744 efx_lic_update_licenses( 3745 __in efx_nic_t *enp); 3746 3747 LIBEFX_API 3748 extern __checkReturn efx_rc_t 3749 efx_lic_get_key_stats( 3750 __in efx_nic_t *enp, 3751 __out efx_key_stats_t *ksp); 3752 3753 LIBEFX_API 3754 extern __checkReturn efx_rc_t 3755 efx_lic_app_state( 3756 __in efx_nic_t *enp, 3757 __in uint64_t app_id, 3758 __out boolean_t *licensedp); 3759 3760 LIBEFX_API 3761 extern __checkReturn efx_rc_t 3762 efx_lic_get_id( 3763 __in efx_nic_t *enp, 3764 __in size_t buffer_size, 3765 __out uint32_t *typep, 3766 __out size_t *lengthp, 3767 __out_opt uint8_t *bufferp); 3768 3769 3770 LIBEFX_API 3771 extern __checkReturn efx_rc_t 3772 efx_lic_find_start( 3773 __in efx_nic_t *enp, 3774 __in_bcount(buffer_size) 3775 caddr_t bufferp, 3776 __in size_t buffer_size, 3777 __out uint32_t *startp); 3778 3779 LIBEFX_API 3780 extern __checkReturn efx_rc_t 3781 efx_lic_find_end( 3782 __in efx_nic_t *enp, 3783 __in_bcount(buffer_size) 3784 caddr_t bufferp, 3785 __in size_t buffer_size, 3786 __in uint32_t offset, 3787 __out uint32_t *endp); 3788 3789 LIBEFX_API 3790 extern __checkReturn __success(return != B_FALSE) boolean_t 3791 efx_lic_find_key( 3792 __in efx_nic_t *enp, 3793 __in_bcount(buffer_size) 3794 caddr_t bufferp, 3795 __in size_t buffer_size, 3796 __in uint32_t offset, 3797 __out uint32_t *startp, 3798 __out uint32_t *lengthp); 3799 3800 LIBEFX_API 3801 extern __checkReturn __success(return != B_FALSE) boolean_t 3802 efx_lic_validate_key( 3803 __in efx_nic_t *enp, 3804 __in_bcount(length) caddr_t keyp, 3805 __in uint32_t length); 3806 3807 LIBEFX_API 3808 extern __checkReturn efx_rc_t 3809 efx_lic_read_key( 3810 __in efx_nic_t *enp, 3811 __in_bcount(buffer_size) 3812 caddr_t bufferp, 3813 __in size_t buffer_size, 3814 __in uint32_t offset, 3815 __in uint32_t length, 3816 __out_bcount_part(key_max_size, *lengthp) 3817 caddr_t keyp, 3818 __in size_t key_max_size, 3819 __out uint32_t *lengthp); 3820 3821 LIBEFX_API 3822 extern __checkReturn efx_rc_t 3823 efx_lic_write_key( 3824 __in efx_nic_t *enp, 3825 __in_bcount(buffer_size) 3826 caddr_t bufferp, 3827 __in size_t buffer_size, 3828 __in uint32_t offset, 3829 __in_bcount(length) caddr_t keyp, 3830 __in uint32_t length, 3831 __out uint32_t *lengthp); 3832 3833 LIBEFX_API 3834 extern __checkReturn efx_rc_t 3835 efx_lic_delete_key( 3836 __in efx_nic_t *enp, 3837 __in_bcount(buffer_size) 3838 caddr_t bufferp, 3839 __in size_t buffer_size, 3840 __in uint32_t offset, 3841 __in uint32_t length, 3842 __in uint32_t end, 3843 __out uint32_t *deltap); 3844 3845 LIBEFX_API 3846 extern __checkReturn efx_rc_t 3847 efx_lic_create_partition( 3848 __in efx_nic_t *enp, 3849 __in_bcount(buffer_size) 3850 caddr_t bufferp, 3851 __in size_t buffer_size); 3852 3853 extern __checkReturn efx_rc_t 3854 efx_lic_finish_partition( 3855 __in efx_nic_t *enp, 3856 __in_bcount(buffer_size) 3857 caddr_t bufferp, 3858 __in size_t buffer_size); 3859 3860 #endif /* EFSYS_OPT_LICENSING */ 3861 3862 /* TUNNEL */ 3863 3864 #if EFSYS_OPT_TUNNEL 3865 3866 LIBEFX_API 3867 extern __checkReturn efx_rc_t 3868 efx_tunnel_init( 3869 __in efx_nic_t *enp); 3870 3871 LIBEFX_API 3872 extern void 3873 efx_tunnel_fini( 3874 __in efx_nic_t *enp); 3875 3876 /* 3877 * For overlay network encapsulation using UDP, the firmware needs to know 3878 * the configured UDP port for the overlay so it can decode encapsulated 3879 * frames correctly. 3880 * The UDP port/protocol list is global. 3881 */ 3882 3883 LIBEFX_API 3884 extern __checkReturn efx_rc_t 3885 efx_tunnel_config_udp_add( 3886 __in efx_nic_t *enp, 3887 __in uint16_t port /* host/cpu-endian */, 3888 __in efx_tunnel_protocol_t protocol); 3889 3890 /* 3891 * Returns EBUSY if reconfiguration of the port is in progress in other thread. 3892 */ 3893 LIBEFX_API 3894 extern __checkReturn efx_rc_t 3895 efx_tunnel_config_udp_remove( 3896 __in efx_nic_t *enp, 3897 __in uint16_t port /* host/cpu-endian */, 3898 __in efx_tunnel_protocol_t protocol); 3899 3900 /* 3901 * Returns EBUSY if reconfiguration of any of the tunnel entries 3902 * is in progress in other thread. 3903 */ 3904 LIBEFX_API 3905 extern __checkReturn efx_rc_t 3906 efx_tunnel_config_clear( 3907 __in efx_nic_t *enp); 3908 3909 /** 3910 * Apply tunnel UDP ports configuration to hardware. 3911 * 3912 * EAGAIN is returned if hardware will be reset (datapath and managment CPU 3913 * reboot). 3914 */ 3915 LIBEFX_API 3916 extern __checkReturn efx_rc_t 3917 efx_tunnel_reconfigure( 3918 __in efx_nic_t *enp); 3919 3920 #endif /* EFSYS_OPT_TUNNEL */ 3921 3922 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 3923 3924 /** 3925 * Firmware subvariant choice options. 3926 * 3927 * It may be switched to no Tx checksum if attached drivers are either 3928 * preboot or firmware subvariant aware and no VIS are allocated. 3929 * If may be always switched to default explicitly using set request or 3930 * implicitly if unaware driver is attaching. If switching is done when 3931 * a driver is attached, it gets MC_REBOOT event and should recreate its 3932 * datapath. 3933 * 3934 * See SF-119419-TC DPDK Firmware Driver Interface and 3935 * SF-109306-TC EF10 for Driver Writers for details. 3936 */ 3937 typedef enum efx_nic_fw_subvariant_e { 3938 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0, 3939 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1, 3940 EFX_NIC_FW_SUBVARIANT_NTYPES 3941 } efx_nic_fw_subvariant_t; 3942 3943 LIBEFX_API 3944 extern __checkReturn efx_rc_t 3945 efx_nic_get_fw_subvariant( 3946 __in efx_nic_t *enp, 3947 __out efx_nic_fw_subvariant_t *subvariantp); 3948 3949 LIBEFX_API 3950 extern __checkReturn efx_rc_t 3951 efx_nic_set_fw_subvariant( 3952 __in efx_nic_t *enp, 3953 __in efx_nic_fw_subvariant_t subvariant); 3954 3955 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 3956 3957 typedef enum efx_phy_fec_type_e { 3958 EFX_PHY_FEC_NONE = 0, 3959 EFX_PHY_FEC_BASER, 3960 EFX_PHY_FEC_RS 3961 } efx_phy_fec_type_t; 3962 3963 #define EFX_PHY_CAP_FEC_BIT(_fec_bit) (1U << EFX_PHY_CAP_##_fec_bit) 3964 #define EFX_PHY_CAP_FEC_MASK \ 3965 (EFX_PHY_CAP_FEC_BIT(BASER_FEC) | \ 3966 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC) | \ 3967 EFX_PHY_CAP_FEC_BIT(BASER_FEC_REQUESTED) | \ 3968 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC_REQUESTED) | \ 3969 EFX_PHY_CAP_FEC_BIT(RS_FEC) | \ 3970 EFX_PHY_CAP_FEC_BIT(RS_FEC_REQUESTED)) 3971 3972 LIBEFX_API 3973 extern __checkReturn efx_rc_t 3974 efx_phy_fec_type_get( 3975 __in efx_nic_t *enp, 3976 __out efx_phy_fec_type_t *typep); 3977 3978 typedef struct efx_phy_link_state_s { 3979 uint32_t epls_adv_cap_mask; 3980 uint32_t epls_lp_cap_mask; 3981 uint32_t epls_ld_cap_mask; 3982 unsigned int epls_fcntl; 3983 efx_phy_fec_type_t epls_fec; 3984 efx_link_mode_t epls_link_mode; 3985 } efx_phy_link_state_t; 3986 3987 LIBEFX_API 3988 extern __checkReturn efx_rc_t 3989 efx_phy_link_state_get( 3990 __in efx_nic_t *enp, 3991 __out efx_phy_link_state_t *eplsp); 3992 3993 3994 #if EFSYS_OPT_EVB 3995 3996 typedef uint32_t efx_vswitch_id_t; 3997 typedef uint32_t efx_vport_id_t; 3998 3999 typedef enum efx_vswitch_type_e { 4000 EFX_VSWITCH_TYPE_VLAN = 1, 4001 EFX_VSWITCH_TYPE_VEB, 4002 /* VSWITCH_TYPE_VEPA: obsolete */ 4003 EFX_VSWITCH_TYPE_MUX = 4, 4004 } efx_vswitch_type_t; 4005 4006 typedef enum efx_vport_type_e { 4007 EFX_VPORT_TYPE_NORMAL = 4, 4008 EFX_VPORT_TYPE_EXPANSION, 4009 EFX_VPORT_TYPE_TEST, 4010 } efx_vport_type_t; 4011 4012 /* Unspecified VLAN ID to support disabling of VLAN filtering */ 4013 #define EFX_FILTER_VID_UNSPEC 0xffff 4014 #define EFX_DEFAULT_VSWITCH_ID 1 4015 4016 /* Default VF VLAN ID on creation */ 4017 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC 4018 #define EFX_VPORT_ID_INVALID 0 4019 4020 typedef struct efx_vport_config_s { 4021 /* Either VF index or EFX_PCI_VF_INVALID for PF */ 4022 uint16_t evc_function; 4023 /* VLAN ID of the associated function */ 4024 uint16_t evc_vid; 4025 /* vport id shared with client driver */ 4026 efx_vport_id_t evc_vport_id; 4027 /* MAC address of the associated function */ 4028 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN]; 4029 /* 4030 * vports created with this flag set may only transfer traffic on the 4031 * VLANs permitted by the vport. Also, an attempt to install filter with 4032 * VLAN will be refused unless requesting function has VLAN privilege. 4033 */ 4034 boolean_t evc_vlan_restrict; 4035 /* Whether this function is assigned or not */ 4036 boolean_t evc_vport_assigned; 4037 } efx_vport_config_t; 4038 4039 typedef struct efx_vswitch_s efx_vswitch_t; 4040 4041 LIBEFX_API 4042 extern __checkReturn efx_rc_t 4043 efx_evb_init( 4044 __in efx_nic_t *enp); 4045 4046 LIBEFX_API 4047 extern void 4048 efx_evb_fini( 4049 __in efx_nic_t *enp); 4050 4051 LIBEFX_API 4052 extern __checkReturn efx_rc_t 4053 efx_evb_vswitch_create( 4054 __in efx_nic_t *enp, 4055 __in uint32_t num_vports, 4056 __inout_ecount(num_vports) efx_vport_config_t *vport_configp, 4057 __deref_out efx_vswitch_t **evpp); 4058 4059 LIBEFX_API 4060 extern __checkReturn efx_rc_t 4061 efx_evb_vswitch_destroy( 4062 __in efx_nic_t *enp, 4063 __in efx_vswitch_t *evp); 4064 4065 LIBEFX_API 4066 extern __checkReturn efx_rc_t 4067 efx_evb_vport_mac_set( 4068 __in efx_nic_t *enp, 4069 __in efx_vswitch_t *evp, 4070 __in efx_vport_id_t vport_id, 4071 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp); 4072 4073 LIBEFX_API 4074 extern __checkReturn efx_rc_t 4075 efx_evb_vport_vlan_set( 4076 __in efx_nic_t *enp, 4077 __in efx_vswitch_t *evp, 4078 __in efx_vport_id_t vport_id, 4079 __in uint16_t vid); 4080 4081 LIBEFX_API 4082 extern __checkReturn efx_rc_t 4083 efx_evb_vport_reset( 4084 __in efx_nic_t *enp, 4085 __in efx_vswitch_t *evp, 4086 __in efx_vport_id_t vport_id, 4087 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp, 4088 __in uint16_t vid, 4089 __out boolean_t *is_fn_resetp); 4090 4091 LIBEFX_API 4092 extern __checkReturn efx_rc_t 4093 efx_evb_vport_stats( 4094 __in efx_nic_t *enp, 4095 __in efx_vswitch_t *evp, 4096 __in efx_vport_id_t vport_id, 4097 __out efsys_mem_t *stats_bufferp); 4098 4099 #endif /* EFSYS_OPT_EVB */ 4100 4101 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 4102 4103 typedef struct efx_proxy_auth_config_s { 4104 efsys_mem_t *request_bufferp; 4105 efsys_mem_t *response_bufferp; 4106 efsys_mem_t *status_bufferp; 4107 uint32_t block_cnt; 4108 uint32_t *op_listp; 4109 size_t op_count; 4110 uint32_t handled_privileges; 4111 } efx_proxy_auth_config_t; 4112 4113 typedef struct efx_proxy_cmd_params_s { 4114 uint32_t pf_index; 4115 uint32_t vf_index; 4116 uint8_t *request_bufferp; 4117 size_t request_size; 4118 uint8_t *response_bufferp; 4119 size_t response_size; 4120 size_t *response_size_actualp; 4121 } efx_proxy_cmd_params_t; 4122 4123 LIBEFX_API 4124 extern __checkReturn efx_rc_t 4125 efx_proxy_auth_init( 4126 __in efx_nic_t *enp); 4127 4128 LIBEFX_API 4129 extern void 4130 efx_proxy_auth_fini( 4131 __in efx_nic_t *enp); 4132 4133 LIBEFX_API 4134 extern __checkReturn efx_rc_t 4135 efx_proxy_auth_configure( 4136 __in efx_nic_t *enp, 4137 __in efx_proxy_auth_config_t *configp); 4138 4139 LIBEFX_API 4140 extern __checkReturn efx_rc_t 4141 efx_proxy_auth_destroy( 4142 __in efx_nic_t *enp, 4143 __in uint32_t handled_privileges); 4144 4145 LIBEFX_API 4146 extern __checkReturn efx_rc_t 4147 efx_proxy_auth_complete_request( 4148 __in efx_nic_t *enp, 4149 __in uint32_t fn_index, 4150 __in uint32_t proxy_result, 4151 __in uint32_t handle); 4152 4153 LIBEFX_API 4154 extern __checkReturn efx_rc_t 4155 efx_proxy_auth_exec_cmd( 4156 __in efx_nic_t *enp, 4157 __inout efx_proxy_cmd_params_t *paramsp); 4158 4159 LIBEFX_API 4160 extern __checkReturn efx_rc_t 4161 efx_proxy_auth_set_privilege_mask( 4162 __in efx_nic_t *enp, 4163 __in uint32_t vf_index, 4164 __in uint32_t mask, 4165 __in uint32_t value); 4166 4167 LIBEFX_API 4168 extern __checkReturn efx_rc_t 4169 efx_proxy_auth_privilege_mask_get( 4170 __in efx_nic_t *enp, 4171 __in uint32_t pf_index, 4172 __in uint32_t vf_index, 4173 __out uint32_t *maskp); 4174 4175 LIBEFX_API 4176 extern __checkReturn efx_rc_t 4177 efx_proxy_auth_privilege_modify( 4178 __in efx_nic_t *enp, 4179 __in uint32_t pf_index, 4180 __in uint32_t vf_index, 4181 __in uint32_t add_privileges_mask, 4182 __in uint32_t remove_privileges_mask); 4183 4184 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 4185 4186 #if EFSYS_OPT_MAE 4187 4188 LIBEFX_API 4189 extern __checkReturn efx_rc_t 4190 efx_mae_init( 4191 __in efx_nic_t *enp); 4192 4193 LIBEFX_API 4194 extern void 4195 efx_mae_fini( 4196 __in efx_nic_t *enp); 4197 4198 typedef struct efx_mae_limits_s { 4199 uint32_t eml_max_n_action_prios; 4200 uint32_t eml_max_n_outer_prios; 4201 uint32_t eml_encap_types_supported; 4202 uint32_t eml_encap_header_size_limit; 4203 uint32_t eml_max_n_counters; 4204 } efx_mae_limits_t; 4205 4206 LIBEFX_API 4207 extern __checkReturn efx_rc_t 4208 efx_mae_get_limits( 4209 __in efx_nic_t *enp, 4210 __out efx_mae_limits_t *emlp); 4211 4212 typedef enum efx_mae_rule_type_e { 4213 EFX_MAE_RULE_ACTION = 0, 4214 EFX_MAE_RULE_OUTER, 4215 4216 EFX_MAE_RULE_NTYPES 4217 } efx_mae_rule_type_t; 4218 4219 typedef struct efx_mae_match_spec_s efx_mae_match_spec_t; 4220 4221 LIBEFX_API 4222 extern __checkReturn efx_rc_t 4223 efx_mae_match_spec_init( 4224 __in efx_nic_t *enp, 4225 __in efx_mae_rule_type_t type, 4226 __in uint32_t prio, 4227 __out efx_mae_match_spec_t **specp); 4228 4229 LIBEFX_API 4230 extern void 4231 efx_mae_match_spec_fini( 4232 __in efx_nic_t *enp, 4233 __in efx_mae_match_spec_t *spec); 4234 4235 typedef enum efx_mae_field_id_e { 4236 /* 4237 * Fields which can be set by efx_mae_match_spec_field_set() 4238 * or by using dedicated field-specific helper APIs. 4239 */ 4240 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0, 4241 EFX_MAE_FIELD_ETHER_TYPE_BE, 4242 EFX_MAE_FIELD_ETH_SADDR_BE, 4243 EFX_MAE_FIELD_ETH_DADDR_BE, 4244 EFX_MAE_FIELD_VLAN0_TCI_BE, 4245 EFX_MAE_FIELD_VLAN0_PROTO_BE, 4246 EFX_MAE_FIELD_VLAN1_TCI_BE, 4247 EFX_MAE_FIELD_VLAN1_PROTO_BE, 4248 EFX_MAE_FIELD_SRC_IP4_BE, 4249 EFX_MAE_FIELD_DST_IP4_BE, 4250 EFX_MAE_FIELD_IP_PROTO, 4251 EFX_MAE_FIELD_IP_TOS, 4252 EFX_MAE_FIELD_IP_TTL, 4253 EFX_MAE_FIELD_SRC_IP6_BE, 4254 EFX_MAE_FIELD_DST_IP6_BE, 4255 EFX_MAE_FIELD_L4_SPORT_BE, 4256 EFX_MAE_FIELD_L4_DPORT_BE, 4257 EFX_MAE_FIELD_TCP_FLAGS_BE, 4258 EFX_MAE_FIELD_ENC_ETHER_TYPE_BE, 4259 EFX_MAE_FIELD_ENC_ETH_SADDR_BE, 4260 EFX_MAE_FIELD_ENC_ETH_DADDR_BE, 4261 EFX_MAE_FIELD_ENC_VLAN0_TCI_BE, 4262 EFX_MAE_FIELD_ENC_VLAN0_PROTO_BE, 4263 EFX_MAE_FIELD_ENC_VLAN1_TCI_BE, 4264 EFX_MAE_FIELD_ENC_VLAN1_PROTO_BE, 4265 EFX_MAE_FIELD_ENC_SRC_IP4_BE, 4266 EFX_MAE_FIELD_ENC_DST_IP4_BE, 4267 EFX_MAE_FIELD_ENC_IP_PROTO, 4268 EFX_MAE_FIELD_ENC_IP_TOS, 4269 EFX_MAE_FIELD_ENC_IP_TTL, 4270 EFX_MAE_FIELD_ENC_SRC_IP6_BE, 4271 EFX_MAE_FIELD_ENC_DST_IP6_BE, 4272 EFX_MAE_FIELD_ENC_L4_SPORT_BE, 4273 EFX_MAE_FIELD_ENC_L4_DPORT_BE, 4274 EFX_MAE_FIELD_ENC_VNET_ID_BE, 4275 EFX_MAE_FIELD_OUTER_RULE_ID, 4276 4277 /* Single bits which can be set by efx_mae_match_spec_bit_set(). */ 4278 EFX_MAE_FIELD_HAS_OVLAN, 4279 EFX_MAE_FIELD_HAS_IVLAN, 4280 EFX_MAE_FIELD_ENC_HAS_OVLAN, 4281 EFX_MAE_FIELD_ENC_HAS_IVLAN, 4282 4283 /* 4284 * Fields which can be set by efx_mae_match_spec_field_set() 4285 * or by using dedicated field-specific helper APIs. 4286 */ 4287 EFX_MAE_FIELD_RECIRC_ID, 4288 EFX_MAE_FIELD_NIDS 4289 } efx_mae_field_id_t; 4290 4291 /* MPORT selector. Used to refer to MPORTs in match/action rules. */ 4292 typedef struct efx_mport_sel_s { 4293 uint32_t sel; 4294 } efx_mport_sel_t; 4295 4296 /* 4297 * MPORT ID. Used to refer dynamically to a specific MPORT. 4298 * The difference between MPORT selector and MPORT ID is that 4299 * selector can specify an exact MPORT ID or it can specify a 4300 * pattern by which an exact MPORT ID can be selected. For example, 4301 * static MPORT selector can specify MPORT of a current PF, which 4302 * will be translated to the dynamic MPORT ID based on which PF is 4303 * using that MPORT selector. 4304 */ 4305 typedef struct efx_mport_id_s { 4306 uint32_t id; 4307 } efx_mport_id_t; 4308 4309 typedef enum efx_mport_type_e { 4310 EFX_MPORT_TYPE_NET_PORT = 0, 4311 EFX_MPORT_TYPE_ALIAS, 4312 EFX_MPORT_TYPE_VNIC, 4313 } efx_mport_type_t; 4314 4315 typedef enum efx_mport_vnic_client_type_e { 4316 EFX_MPORT_VNIC_CLIENT_FUNCTION = 1, 4317 EFX_MPORT_VNIC_CLIENT_PLUGIN, 4318 } efx_mport_vnic_client_type_t; 4319 4320 typedef struct efx_mport_desc_s { 4321 efx_mport_id_t emd_id; 4322 boolean_t emd_can_receive_on; 4323 boolean_t emd_can_deliver_to; 4324 boolean_t emd_can_delete; 4325 boolean_t emd_zombie; 4326 efx_mport_type_t emd_type; 4327 union { 4328 struct { 4329 uint32_t ep_index; 4330 } emd_net_port; 4331 struct { 4332 efx_mport_id_t ea_target_mport_id; 4333 } emd_alias; 4334 struct { 4335 efx_mport_vnic_client_type_t ev_client_type; 4336 efx_pcie_interface_t ev_intf; 4337 uint16_t ev_pf; 4338 uint16_t ev_vf; 4339 /* MCDI client handle for this VNIC. */ 4340 uint32_t ev_handle; 4341 } emd_vnic; 4342 }; 4343 } efx_mport_desc_t; 4344 4345 #define EFX_MPORT_NULL (0U) 4346 4347 /* 4348 * Generate an invalid MPORT selector. 4349 * 4350 * The resulting MPORT selector is opaque to the caller. Requests 4351 * that attempt to use it will be rejected. 4352 */ 4353 LIBEFX_API 4354 extern __checkReturn efx_rc_t 4355 efx_mae_mport_invalid( 4356 __out efx_mport_sel_t *mportp); 4357 4358 /* 4359 * Get MPORT selector of a physical port. 4360 * 4361 * The resulting MPORT selector is opaque to the caller and can be 4362 * passed as an argument to efx_mae_match_spec_mport_set() 4363 * and efx_mae_action_set_populate_deliver(). 4364 */ 4365 LIBEFX_API 4366 extern __checkReturn efx_rc_t 4367 efx_mae_mport_by_phy_port( 4368 __in uint32_t phy_port, 4369 __out efx_mport_sel_t *mportp); 4370 4371 /* 4372 * Get MPORT selector of a PCIe function. 4373 * 4374 * The resulting MPORT selector is opaque to the caller and can be 4375 * passed as an argument to efx_mae_match_spec_mport_set() 4376 * and efx_mae_action_set_populate_deliver(). 4377 */ 4378 LIBEFX_API 4379 extern __checkReturn efx_rc_t 4380 efx_mae_mport_by_pcie_function( 4381 __in uint32_t pf, 4382 __in uint32_t vf, 4383 __out efx_mport_sel_t *mportp); 4384 4385 /* 4386 * Get MPORT selector of a multi-host PCIe function. 4387 * 4388 * The resulting MPORT selector is opaque to the caller and can be 4389 * passed as an argument to efx_mae_match_spec_mport_set() 4390 * and efx_mae_action_set_populate_deliver(). 4391 */ 4392 LIBEFX_API 4393 extern __checkReturn efx_rc_t 4394 efx_mae_mport_by_pcie_mh_function( 4395 __in efx_pcie_interface_t intf, 4396 __in uint32_t pf, 4397 __in uint32_t vf, 4398 __out efx_mport_sel_t *mportp); 4399 4400 /* 4401 * Get MPORT selector by an MPORT ID 4402 * 4403 * The resulting MPORT selector is opaque to the caller and can be 4404 * passed as an argument to efx_mae_match_spec_mport_set() 4405 * and efx_mae_action_set_populate_deliver(). 4406 */ 4407 LIBEFX_API 4408 extern __checkReturn efx_rc_t 4409 efx_mae_mport_by_id( 4410 __in const efx_mport_id_t *mport_idp, 4411 __out efx_mport_sel_t *mportp); 4412 4413 /* Get MPORT ID by an MPORT selector */ 4414 LIBEFX_API 4415 extern __checkReturn efx_rc_t 4416 efx_mae_mport_id_by_selector( 4417 __in efx_nic_t *enp, 4418 __in const efx_mport_sel_t *mport_selectorp, 4419 __out efx_mport_id_t *mport_idp); 4420 4421 /* 4422 * Fields which have BE postfix in their named constants are expected 4423 * to be passed by callers in big-endian byte order. They will appear 4424 * in the MCDI buffer, which is a part of the match specification, in 4425 * the very same byte order, that is, no conversion will be performed. 4426 * 4427 * Fields which don't have BE postfix in their named constants are in 4428 * host byte order. MCDI expects them to be little-endian, so the API 4429 * will take care to carry out conversion to little-endian byte order. 4430 * At the moment, the only field in host byte order is MPORT selector. 4431 */ 4432 LIBEFX_API 4433 extern __checkReturn efx_rc_t 4434 efx_mae_match_spec_field_set( 4435 __in efx_mae_match_spec_t *spec, 4436 __in efx_mae_field_id_t field_id, 4437 __in size_t value_size, 4438 __in_bcount(value_size) const uint8_t *value, 4439 __in size_t mask_size, 4440 __in_bcount(mask_size) const uint8_t *mask); 4441 4442 /* The corresponding mask will be set to B_TRUE. */ 4443 LIBEFX_API 4444 extern __checkReturn efx_rc_t 4445 efx_mae_match_spec_bit_set( 4446 __in efx_mae_match_spec_t *spec, 4447 __in efx_mae_field_id_t field_id, 4448 __in boolean_t value); 4449 4450 /* If the mask argument is NULL, the API will use full mask by default. */ 4451 LIBEFX_API 4452 extern __checkReturn efx_rc_t 4453 efx_mae_match_spec_mport_set( 4454 __in efx_mae_match_spec_t *spec, 4455 __in const efx_mport_sel_t *valuep, 4456 __in_opt const efx_mport_sel_t *maskp); 4457 4458 LIBEFX_API 4459 extern __checkReturn efx_rc_t 4460 efx_mae_match_spec_recirc_id_set( 4461 __in efx_mae_match_spec_t *spec, 4462 __in uint8_t recirc_id); 4463 4464 LIBEFX_API 4465 extern __checkReturn boolean_t 4466 efx_mae_match_specs_equal( 4467 __in const efx_mae_match_spec_t *left, 4468 __in const efx_mae_match_spec_t *right); 4469 4470 /* 4471 * Make sure that match fields known by EFX have proper masks set 4472 * in the match specification as per requirements of SF-122526-TC. 4473 * 4474 * In the case efx_mae_field_id_t lacks named identifiers for any 4475 * fields which the FW maintains with support status MATCH_ALWAYS, 4476 * the validation result may not be accurate. 4477 */ 4478 LIBEFX_API 4479 extern __checkReturn boolean_t 4480 efx_mae_match_spec_is_valid( 4481 __in efx_nic_t *enp, 4482 __in const efx_mae_match_spec_t *spec); 4483 4484 typedef struct efx_mae_actions_s efx_mae_actions_t; 4485 4486 LIBEFX_API 4487 extern __checkReturn efx_rc_t 4488 efx_mae_action_set_spec_init( 4489 __in efx_nic_t *enp, 4490 __out efx_mae_actions_t **specp); 4491 4492 LIBEFX_API 4493 extern void 4494 efx_mae_action_set_spec_fini( 4495 __in efx_nic_t *enp, 4496 __in efx_mae_actions_t *spec); 4497 4498 LIBEFX_API 4499 extern __checkReturn efx_rc_t 4500 efx_mae_action_set_populate_decap( 4501 __in efx_mae_actions_t *spec); 4502 4503 LIBEFX_API 4504 extern __checkReturn efx_rc_t 4505 efx_mae_action_set_populate_vlan_pop( 4506 __in efx_mae_actions_t *spec); 4507 4508 /* 4509 * This always amends the outermost header. This way, for a tunnel 4510 * packet, if action DECAP is not requested, this will affect the 4511 * outer header; otherwise, the inner header will be updated. 4512 * 4513 * Use efx_mae_action_set_fill_in_dst_mac_id() to set ID of 4514 * the allocated MAC address entry in the specification 4515 * prior to action set allocation. 4516 */ 4517 LIBEFX_API 4518 extern __checkReturn efx_rc_t 4519 efx_mae_action_set_populate_set_dst_mac( 4520 __in efx_mae_actions_t *spec); 4521 4522 /* 4523 * This always amends the outermost header. This way, for a tunnel 4524 * packet, if action DECAP is not requested, this will affect the 4525 * outer header; otherwise, the inner header will be updated. 4526 * 4527 * Use efx_mae_action_set_fill_in_src_mac_id() to set ID of 4528 * the allocated MAC address entry in the specification 4529 * prior to action set allocation. 4530 */ 4531 LIBEFX_API 4532 extern __checkReturn efx_rc_t 4533 efx_mae_action_set_populate_set_src_mac( 4534 __in efx_mae_actions_t *spec); 4535 4536 /* 4537 * This always amends the outermost header. This way, for a tunnel 4538 * packet, if action DECAP is not requested, this will affect the 4539 * outer header; otherwise, the inner header will be updated. 4540 * 4541 * This will also take care to update IPv4 checksum accordingly. 4542 */ 4543 LIBEFX_API 4544 extern __checkReturn efx_rc_t 4545 efx_mae_action_set_populate_decr_ip_ttl( 4546 __in efx_mae_actions_t *spec); 4547 4548 LIBEFX_API 4549 extern __checkReturn efx_rc_t 4550 efx_mae_action_set_populate_vlan_push( 4551 __in efx_mae_actions_t *spec, 4552 __in uint16_t tpid_be, 4553 __in uint16_t tci_be); 4554 4555 /* 4556 * Use efx_mae_action_set_fill_in_eh_id() to set ID of the allocated 4557 * encap. header in the specification prior to action set allocation. 4558 */ 4559 LIBEFX_API 4560 extern __checkReturn efx_rc_t 4561 efx_mae_action_set_populate_encap( 4562 __in efx_mae_actions_t *spec); 4563 4564 /* 4565 * Use efx_mae_action_set_fill_in_counter_id() to set ID of a counter 4566 * in the specification prior to action set allocation. 4567 * 4568 * NOTICE: the HW will conduct action COUNT after actions DECAP, 4569 * VLAN_POP, VLAN_PUSH (if any) have been applied to the packet, 4570 * but, as a workaround, this order is not validated by the API. 4571 * 4572 * The workaround helps to unblock DPDK + Open vSwitch use case. 4573 * In Open vSwitch, this action is always the first to be added, 4574 * in particular, it's known to be inserted before action DECAP, 4575 * so enforcing the right order here would cause runtime errors. 4576 * The existing behaviour in Open vSwitch is unlikely to change 4577 * any time soon, and the workaround is a good solution because 4578 * in fact the real COUNT order is a don't care to Open vSwitch. 4579 */ 4580 LIBEFX_API 4581 extern __checkReturn efx_rc_t 4582 efx_mae_action_set_populate_count( 4583 __in efx_mae_actions_t *spec); 4584 4585 LIBEFX_API 4586 extern __checkReturn efx_rc_t 4587 efx_mae_action_set_populate_flag( 4588 __in efx_mae_actions_t *spec); 4589 4590 LIBEFX_API 4591 extern __checkReturn efx_rc_t 4592 efx_mae_action_set_populate_mark( 4593 __in efx_mae_actions_t *spec, 4594 __in uint32_t mark_value); 4595 4596 /* 4597 * Whilst efx_mae_action_set_populate_mark() can be used to request setting 4598 * a user mark in matching packets and demands that the request come before 4599 * setting the final destination (deliver action), this API can be invoked 4600 * after deliver action has been added in order to request mark reset if 4601 * the user's own mark request has not been added as a result of parsing. 4602 * 4603 * It is useful when the driver chains an outer rule (OR) with an action 4604 * rule (AR) by virtue of a recirculation ID. The OR may set mark from 4605 * this ID to help the driver identify packets that hit the OR and do 4606 * not hit the AR. But, for packets that do hit the AR, the driver 4607 * wants to reset the mark value to avoid confusing recipients. 4608 */ 4609 LIBEFX_API 4610 extern void 4611 efx_mae_action_set_populate_mark_reset( 4612 __in efx_mae_actions_t *spec); 4613 4614 LIBEFX_API 4615 extern __checkReturn efx_rc_t 4616 efx_mae_action_set_populate_deliver( 4617 __in efx_mae_actions_t *spec, 4618 __in const efx_mport_sel_t *mportp); 4619 4620 LIBEFX_API 4621 extern __checkReturn efx_rc_t 4622 efx_mae_action_set_populate_drop( 4623 __in efx_mae_actions_t *spec); 4624 4625 LIBEFX_API 4626 extern __checkReturn boolean_t 4627 efx_mae_action_set_specs_equal( 4628 __in const efx_mae_actions_t *left, 4629 __in const efx_mae_actions_t *right); 4630 4631 /* 4632 * Conduct a comparison to check whether two match specifications 4633 * of equal rule type (action / outer) and priority would map to 4634 * the very same rule class from the firmware's standpoint. 4635 * 4636 * For match specification fields that are not supported by firmware, 4637 * the rule class only matches if the mask/value pairs for that field 4638 * are equal. Clients should use efx_mae_match_spec_is_valid() before 4639 * calling this API to detect usage of unsupported fields. 4640 */ 4641 LIBEFX_API 4642 extern __checkReturn efx_rc_t 4643 efx_mae_match_specs_class_cmp( 4644 __in efx_nic_t *enp, 4645 __in const efx_mae_match_spec_t *left, 4646 __in const efx_mae_match_spec_t *right, 4647 __out boolean_t *have_same_classp); 4648 4649 #define EFX_MAE_RSRC_ID_INVALID UINT32_MAX 4650 4651 /* Rule ID */ 4652 typedef struct efx_mae_rule_id_s { 4653 uint32_t id; 4654 } efx_mae_rule_id_t; 4655 4656 /* 4657 * Set the initial recirculation ID. It goes to action rule (AR) lookup. 4658 * 4659 * To match on this ID in an AR, use efx_mae_match_spec_recirc_id_set(). 4660 */ 4661 LIBEFX_API 4662 extern __checkReturn efx_rc_t 4663 efx_mae_outer_rule_recirc_id_set( 4664 __in efx_mae_match_spec_t *spec, 4665 __in uint8_t recirc_id); 4666 4667 LIBEFX_API 4668 extern __checkReturn efx_rc_t 4669 efx_mae_outer_rule_insert( 4670 __in efx_nic_t *enp, 4671 __in const efx_mae_match_spec_t *spec, 4672 __in efx_tunnel_protocol_t encap_type, 4673 __out efx_mae_rule_id_t *or_idp); 4674 4675 LIBEFX_API 4676 extern __checkReturn efx_rc_t 4677 efx_mae_outer_rule_remove( 4678 __in efx_nic_t *enp, 4679 __in const efx_mae_rule_id_t *or_idp); 4680 4681 LIBEFX_API 4682 extern __checkReturn efx_rc_t 4683 efx_mae_match_spec_outer_rule_id_set( 4684 __in efx_mae_match_spec_t *spec, 4685 __in const efx_mae_rule_id_t *or_idp); 4686 4687 /* MAC address entry ID */ 4688 typedef struct efx_mae_mac_id_s { 4689 uint32_t id; 4690 } efx_mae_mac_id_t; 4691 4692 LIBEFX_API 4693 extern __checkReturn efx_rc_t 4694 efx_mae_mac_addr_alloc( 4695 __in efx_nic_t *enp, 4696 __in uint8_t addr_bytes[EFX_MAC_ADDR_LEN], 4697 __out efx_mae_mac_id_t *mac_idp); 4698 4699 LIBEFX_API 4700 extern __checkReturn efx_rc_t 4701 efx_mae_mac_addr_free( 4702 __in efx_nic_t *enp, 4703 __in const efx_mae_mac_id_t *mac_idp); 4704 4705 /* See description before efx_mae_action_set_populate_set_dst_mac(). */ 4706 LIBEFX_API 4707 extern __checkReturn efx_rc_t 4708 efx_mae_action_set_fill_in_dst_mac_id( 4709 __in efx_mae_actions_t *spec, 4710 __in const efx_mae_mac_id_t *mac_idp); 4711 4712 /* See description before efx_mae_action_set_populate_set_src_mac(). */ 4713 LIBEFX_API 4714 extern __checkReturn efx_rc_t 4715 efx_mae_action_set_fill_in_src_mac_id( 4716 __in efx_mae_actions_t *spec, 4717 __in const efx_mae_mac_id_t *mac_idp); 4718 4719 /* Encap. header ID */ 4720 typedef struct efx_mae_eh_id_s { 4721 uint32_t id; 4722 } efx_mae_eh_id_t; 4723 4724 LIBEFX_API 4725 extern __checkReturn efx_rc_t 4726 efx_mae_encap_header_alloc( 4727 __in efx_nic_t *enp, 4728 __in efx_tunnel_protocol_t encap_type, 4729 __in_bcount(header_size) uint8_t *header_data, 4730 __in size_t header_size, 4731 __out efx_mae_eh_id_t *eh_idp); 4732 4733 LIBEFX_API 4734 extern __checkReturn efx_rc_t 4735 efx_mae_encap_header_free( 4736 __in efx_nic_t *enp, 4737 __in const efx_mae_eh_id_t *eh_idp); 4738 4739 /* See description before efx_mae_action_set_populate_encap(). */ 4740 LIBEFX_API 4741 extern __checkReturn efx_rc_t 4742 efx_mae_action_set_fill_in_eh_id( 4743 __in efx_mae_actions_t *spec, 4744 __in const efx_mae_eh_id_t *eh_idp); 4745 4746 typedef struct efx_counter_s { 4747 uint32_t id; 4748 } efx_counter_t; 4749 4750 LIBEFX_API 4751 extern __checkReturn unsigned int 4752 efx_mae_action_set_get_nb_count( 4753 __in const efx_mae_actions_t *spec); 4754 4755 /* See description before efx_mae_action_set_populate_count(). */ 4756 LIBEFX_API 4757 extern __checkReturn efx_rc_t 4758 efx_mae_action_set_fill_in_counter_id( 4759 __in efx_mae_actions_t *spec, 4760 __in const efx_counter_t *counter_idp); 4761 4762 /* 4763 * Clears dangling FW object IDs (counter ID, for instance) in 4764 * the action set specification. Useful for adapter restarts, 4765 * when all MAE objects need to be reallocated by the driver. 4766 * 4767 * This method only clears the IDs in the specification. 4768 * The driver is still responsible for keeping the IDs 4769 * separately and freeing them when stopping the port. 4770 */ 4771 LIBEFX_API 4772 extern void 4773 efx_mae_action_set_clear_fw_rsrc_ids( 4774 __in efx_mae_actions_t *spec); 4775 4776 /* Action set ID */ 4777 typedef struct efx_mae_aset_id_s { 4778 uint32_t id; 4779 } efx_mae_aset_id_t; 4780 4781 LIBEFX_API 4782 extern __checkReturn efx_rc_t 4783 efx_mae_action_set_alloc( 4784 __in efx_nic_t *enp, 4785 __in const efx_mae_actions_t *spec, 4786 __out efx_mae_aset_id_t *aset_idp); 4787 4788 /* 4789 * Generation count has two purposes: 4790 * 4791 * 1) Distinguish between counter packets that belong to freed counter 4792 * and the packets that belong to reallocated counter (with the same ID); 4793 * 2) Make sure that all packets are received for a counter that was freed; 4794 * 4795 * API users should provide generation count out parameter in allocation 4796 * function if counters can be reallocated and consistent counter values are 4797 * required. 4798 * 4799 * API users that need consistent final counter values after counter 4800 * deallocation or counter stream stop should provide the parameter in 4801 * functions that free the counters and stop the counter stream. 4802 */ 4803 LIBEFX_API 4804 extern __checkReturn efx_rc_t 4805 efx_mae_counters_alloc( 4806 __in efx_nic_t *enp, 4807 __in uint32_t n_counters, 4808 __out uint32_t *n_allocatedp, 4809 __out_ecount(n_counters) efx_counter_t *countersp, 4810 __out_opt uint32_t *gen_countp); 4811 4812 LIBEFX_API 4813 extern __checkReturn efx_rc_t 4814 efx_mae_counters_free( 4815 __in efx_nic_t *enp, 4816 __in uint32_t n_counters, 4817 __out uint32_t *n_freedp, 4818 __in_ecount(n_counters) const efx_counter_t *countersp, 4819 __out_opt uint32_t *gen_countp); 4820 4821 /* When set, include counters with a value of zero */ 4822 #define EFX_MAE_COUNTERS_STREAM_IN_ZERO_SQUASH_DISABLE (1U << 0) 4823 4824 /* 4825 * Set if credit-based flow control is used. In this case the driver 4826 * must call efx_mae_counters_stream_give_credits() to notify the 4827 * packetiser of descriptors written. 4828 */ 4829 #define EFX_MAE_COUNTERS_STREAM_OUT_USES_CREDITS (1U << 0) 4830 4831 LIBEFX_API 4832 extern __checkReturn efx_rc_t 4833 efx_mae_counters_stream_start( 4834 __in efx_nic_t *enp, 4835 __in uint16_t rxq_id, 4836 __in uint16_t packet_size, 4837 __in uint32_t flags_in, 4838 __out uint32_t *flags_out); 4839 4840 LIBEFX_API 4841 extern __checkReturn efx_rc_t 4842 efx_mae_counters_stream_stop( 4843 __in efx_nic_t *enp, 4844 __in uint16_t rxq_id, 4845 __out_opt uint32_t *gen_countp); 4846 4847 LIBEFX_API 4848 extern __checkReturn efx_rc_t 4849 efx_mae_counters_stream_give_credits( 4850 __in efx_nic_t *enp, 4851 __in uint32_t n_credits); 4852 4853 LIBEFX_API 4854 extern __checkReturn efx_rc_t 4855 efx_mae_action_set_free( 4856 __in efx_nic_t *enp, 4857 __in const efx_mae_aset_id_t *aset_idp); 4858 4859 /* Action set list ID */ 4860 typedef struct efx_mae_aset_list_id_s { 4861 uint32_t id; 4862 } efx_mae_aset_list_id_t; 4863 4864 /* 4865 * Either action set list ID or action set ID must be passed to this API, 4866 * but not both. 4867 */ 4868 LIBEFX_API 4869 extern __checkReturn efx_rc_t 4870 efx_mae_action_rule_insert( 4871 __in efx_nic_t *enp, 4872 __in const efx_mae_match_spec_t *spec, 4873 __in const efx_mae_aset_list_id_t *asl_idp, 4874 __in const efx_mae_aset_id_t *as_idp, 4875 __out efx_mae_rule_id_t *ar_idp); 4876 4877 LIBEFX_API 4878 extern __checkReturn efx_rc_t 4879 efx_mae_action_rule_remove( 4880 __in efx_nic_t *enp, 4881 __in const efx_mae_rule_id_t *ar_idp); 4882 4883 LIBEFX_API 4884 extern __checkReturn efx_rc_t 4885 efx_mcdi_mport_alloc_alias( 4886 __in efx_nic_t *enp, 4887 __out efx_mport_id_t *mportp, 4888 __out_opt uint32_t *labelp); 4889 4890 LIBEFX_API 4891 extern __checkReturn efx_rc_t 4892 efx_mae_mport_free( 4893 __in efx_nic_t *enp, 4894 __in const efx_mport_id_t *mportp); 4895 4896 typedef __checkReturn efx_rc_t 4897 (efx_mae_read_mport_journal_cb)( 4898 __in void *cb_datap, 4899 __in efx_mport_desc_t *mportp, 4900 __in size_t mport_len); 4901 4902 /* 4903 * Read mport descriptions from the MAE journal (which describes added and 4904 * removed mports) and pass them to a user-supplied callback. The user gets 4905 * only one chance to process the data it's given. Once the callback function 4906 * finishes, that particular mport description will be gone. 4907 * The journal will be fully repopulated on PCI reset (efx_nic_reset function). 4908 */ 4909 LIBEFX_API 4910 extern __checkReturn efx_rc_t 4911 efx_mae_read_mport_journal( 4912 __in efx_nic_t *enp, 4913 __in efx_mae_read_mport_journal_cb *cbp, 4914 __in void *cb_datap); 4915 4916 #endif /* EFSYS_OPT_MAE */ 4917 4918 #if EFSYS_OPT_VIRTIO 4919 4920 /* A Virtio net device can have one or more pairs of Rx/Tx virtqueues 4921 * while virtio block device has a single virtqueue, 4922 * for further details refer section of 4.2.3 of SF-120734 4923 */ 4924 typedef enum efx_virtio_vq_type_e { 4925 EFX_VIRTIO_VQ_TYPE_NET_RXQ, 4926 EFX_VIRTIO_VQ_TYPE_NET_TXQ, 4927 EFX_VIRTIO_VQ_TYPE_BLOCK, 4928 EFX_VIRTIO_VQ_NTYPES 4929 } efx_virtio_vq_type_t; 4930 4931 typedef struct efx_virtio_vq_dyncfg_s { 4932 /* 4933 * If queue is being created to be migrated then this should be 4934 * the FINAL_AVAIL_IDX value returned by MC_CMD_VIRTIO_FINI_QUEUE 4935 * of the queue being migrated from. Otherwise, it should be zero. 4936 */ 4937 uint32_t evvd_vq_avail_idx; 4938 /* 4939 * If queue is being created to be migrated then this should be 4940 * the FINAL_USED_IDX value returned by MC_CMD_VIRTIO_FINI_QUEUE 4941 * of the queue being migrated from. Otherwise, it should be zero. 4942 */ 4943 uint32_t evvd_vq_used_idx; 4944 } efx_virtio_vq_dyncfg_t; 4945 4946 /* 4947 * Virtqueue size must be a power of 2, maximum size is 32768 4948 * (see VIRTIO v1.1 section 2.6) 4949 */ 4950 #define EFX_VIRTIO_MAX_VQ_SIZE 0x8000 4951 4952 typedef struct efx_virtio_vq_cfg_s { 4953 unsigned int evvc_vq_num; 4954 efx_virtio_vq_type_t evvc_type; 4955 /* 4956 * vDPA as VF : It is target VF number if queue is being created on VF. 4957 * vDPA as PF : If queue to be created on PF then it should be 4958 * EFX_PCI_VF_INVALID. 4959 */ 4960 uint16_t evvc_target_vf; 4961 /* 4962 * Maximum virtqueue size is EFX_VIRTIO_MAX_VQ_SIZE and 4963 * virtqueue size 0 means the queue is unavailable. 4964 */ 4965 uint32_t evvc_vq_size; 4966 efsys_dma_addr_t evvc_desc_tbl_addr; 4967 efsys_dma_addr_t evvc_avail_ring_addr; 4968 efsys_dma_addr_t evvc_used_ring_addr; 4969 /* MSIX vector number for the virtqueue or 0xFFFF if MSIX is not used */ 4970 uint16_t evvc_msix_vector; 4971 /* 4972 * evvc_pas_id contains a PCIe address space identifier if the queue 4973 * uses PASID. 4974 */ 4975 boolean_t evvc_use_pasid; 4976 uint32_t evvc_pas_id; 4977 /* Negotiated virtio features to be applied to this virtqueue */ 4978 uint64_t evcc_features; 4979 } efx_virtio_vq_cfg_t; 4980 4981 typedef struct efx_virtio_vq_s efx_virtio_vq_t; 4982 4983 typedef enum efx_virtio_device_type_e { 4984 EFX_VIRTIO_DEVICE_TYPE_RESERVED, 4985 EFX_VIRTIO_DEVICE_TYPE_NET, 4986 EFX_VIRTIO_DEVICE_TYPE_BLOCK, 4987 EFX_VIRTIO_DEVICE_NTYPES 4988 } efx_virtio_device_type_t; 4989 4990 LIBEFX_API 4991 extern __checkReturn efx_rc_t 4992 efx_virtio_init( 4993 __in efx_nic_t *enp); 4994 4995 LIBEFX_API 4996 extern void 4997 efx_virtio_fini( 4998 __in efx_nic_t *enp); 4999 5000 /* 5001 * When virtio net driver in the guest sets VIRTIO_CONFIG_STATUS_DRIVER_OK bit, 5002 * hypervisor starts configuring all the virtqueues in the device. When the 5003 * vhost_user has received VHOST_USER_SET_VRING_ENABLE for all the virtqueues, 5004 * then it invokes VDPA driver callback dev_conf. APIs qstart and qcreate would 5005 * be invoked from dev_conf callback to create the virtqueues, For further 5006 * details refer SF-122427. 5007 */ 5008 LIBEFX_API 5009 extern __checkReturn efx_rc_t 5010 efx_virtio_qcreate( 5011 __in efx_nic_t *enp, 5012 __deref_out efx_virtio_vq_t **evvpp); 5013 5014 LIBEFX_API 5015 extern __checkReturn efx_rc_t 5016 efx_virtio_qstart( 5017 __in efx_virtio_vq_t *evvp, 5018 __in efx_virtio_vq_cfg_t *evvcp, 5019 __in_opt efx_virtio_vq_dyncfg_t *evvdp); 5020 5021 LIBEFX_API 5022 extern __checkReturn efx_rc_t 5023 efx_virtio_qstop( 5024 __in efx_virtio_vq_t *evvp, 5025 __out_opt efx_virtio_vq_dyncfg_t *evvdp); 5026 5027 LIBEFX_API 5028 extern void 5029 efx_virtio_qdestroy( 5030 __in efx_virtio_vq_t *evvp); 5031 5032 /* 5033 * Get the offset in the BAR of the doorbells for a VI. 5034 * net device : doorbell offset of RX & TX queues 5035 * block device : request doorbell offset in the BAR. 5036 * For further details refer section of 4 of SF-119689 5037 */ 5038 LIBEFX_API 5039 extern __checkReturn efx_rc_t 5040 efx_virtio_get_doorbell_offset( 5041 __in efx_virtio_vq_t *evvp, 5042 __out uint32_t *offsetp); 5043 5044 LIBEFX_API 5045 extern __checkReturn efx_rc_t 5046 efx_virtio_get_features( 5047 __in efx_nic_t *enp, 5048 __in efx_virtio_device_type_t type, 5049 __out uint64_t *featuresp); 5050 5051 LIBEFX_API 5052 extern __checkReturn efx_rc_t 5053 efx_virtio_verify_features( 5054 __in efx_nic_t *enp, 5055 __in efx_virtio_device_type_t type, 5056 __in uint64_t features); 5057 5058 #endif /* EFSYS_OPT_VIRTIO */ 5059 5060 LIBEFX_API 5061 extern __checkReturn efx_rc_t 5062 efx_nic_dma_config_add( 5063 __in efx_nic_t *enp, 5064 __in efsys_dma_addr_t trgt_addr, 5065 __in size_t len, 5066 __out_opt efsys_dma_addr_t *nic_basep, 5067 __out_opt efsys_dma_addr_t *trgt_basep, 5068 __out_opt size_t *map_lenp); 5069 5070 LIBEFX_API 5071 extern __checkReturn efx_rc_t 5072 efx_nic_dma_reconfigure( 5073 __in efx_nic_t *enp); 5074 5075 typedef enum efx_nic_dma_addr_type_e { 5076 EFX_NIC_DMA_ADDR_MCDI_BUF, 5077 EFX_NIC_DMA_ADDR_MAC_STATS_BUF, 5078 EFX_NIC_DMA_ADDR_EVENT_RING, 5079 EFX_NIC_DMA_ADDR_RX_RING, 5080 EFX_NIC_DMA_ADDR_TX_RING, 5081 EFX_NIC_DMA_ADDR_RX_BUF, 5082 EFX_NIC_DMA_ADDR_TX_BUF, 5083 5084 EFX_NIC_DMA_ADDR_NTYPES 5085 } efx_nic_dma_addr_type_t; 5086 5087 LIBEFX_API 5088 extern __checkReturn efx_rc_t 5089 efx_nic_dma_map( 5090 __in efx_nic_t *enp, 5091 __in efx_nic_dma_addr_type_t addr_type, 5092 __in efsys_dma_addr_t tgt_addr, 5093 __in size_t len, 5094 __out efsys_dma_addr_t *nic_addrp); 5095 5096 /* Unique IDs for HW tables */ 5097 typedef enum efx_table_id_e { 5098 EFX_TABLE_ID_CONNTRACK = 0x10300, 5099 } efx_table_id_t; 5100 5101 LIBEFX_API 5102 extern __checkReturn efx_rc_t 5103 efx_table_list( 5104 __in efx_nic_t *enp, 5105 __in uint32_t entry_ofst, 5106 __out_opt unsigned int *total_n_tablesp, 5107 __out_ecount_opt(n_table_ids) efx_table_id_t *table_ids, 5108 __in unsigned int n_table_ids, 5109 __out_opt unsigned int *n_table_ids_writtenp); 5110 5111 LIBEFX_API 5112 extern __checkReturn size_t 5113 efx_table_supported_num_get( 5114 __in void); 5115 5116 LIBEFX_API 5117 extern __checkReturn boolean_t 5118 efx_table_is_supported( 5119 __in efx_table_id_t table_id); 5120 5121 /* Unique IDs for table fields */ 5122 typedef enum efx_table_field_id_e { 5123 EFX_TABLE_FIELD_ID_UNUSED = 0x0, 5124 EFX_TABLE_FIELD_ID_COUNTER_ID = 0xa, 5125 EFX_TABLE_FIELD_ID_ETHER_TYPE = 0x1c, 5126 EFX_TABLE_FIELD_ID_SRC_IP = 0x1d, 5127 EFX_TABLE_FIELD_ID_DST_IP = 0x1e, 5128 EFX_TABLE_FIELD_ID_IP_PROTO = 0x20, 5129 EFX_TABLE_FIELD_ID_SRC_PORT = 0x21, 5130 EFX_TABLE_FIELD_ID_DST_PORT = 0x22, 5131 EFX_TABLE_FIELD_ID_NAT_PORT = 0x7a, 5132 EFX_TABLE_FIELD_ID_NAT_IP = 0x7b, 5133 EFX_TABLE_FIELD_ID_NAT_DIR = 0x7c, 5134 EFX_TABLE_FIELD_ID_CT_MARK = 0x7d, 5135 } efx_table_field_id_t; 5136 5137 /* Table fields mask types */ 5138 typedef enum efx_table_field_mask_type_e { 5139 EFX_TABLE_FIELD_MASK_NEVER = 0x0, 5140 EFX_TABLE_FIELD_MASK_EXACT = 0x1, 5141 } efx_table_field_mask_type_t; 5142 5143 typedef struct efx_table_field_desc_s { 5144 efx_table_field_id_t field_id; 5145 uint16_t lbn; 5146 uint16_t width; 5147 efx_table_field_mask_type_t mask_type; 5148 uint8_t scheme; 5149 } efx_table_field_descriptor_t; 5150 5151 /* Types of HW tables */ 5152 typedef enum efx_table_type_e { 5153 /* Exact match to all key fields of table entry. */ 5154 EFX_TABLE_TYPE_BCAM = 0x2, 5155 } efx_table_type_t; 5156 5157 typedef struct efx_table_descriptor_s { 5158 efx_table_type_t type; 5159 uint16_t key_width; 5160 uint16_t resp_width; 5161 /* Number of key's fields to match data */ 5162 uint16_t n_key_fields; 5163 /* Number of fields in match response */ 5164 uint16_t n_resp_fields; 5165 } efx_table_descriptor_t; 5166 5167 LIBEFX_API 5168 extern __checkReturn efx_rc_t 5169 efx_table_describe( 5170 __in efx_nic_t *enp, 5171 __in efx_table_id_t table_id, 5172 __in uint32_t field_offset, 5173 __out_opt efx_table_descriptor_t *table_descp, 5174 __out_ecount_opt(n_field_descs) efx_table_field_descriptor_t *fields_descs, 5175 __in unsigned int n_field_descs, 5176 __out_opt unsigned int *n_field_descs_writtenp); 5177 5178 /* Maximum possible size of data for manipulation of the tables */ 5179 #define EFX_TABLE_ENTRY_LENGTH_MAX 1008 5180 5181 LIBEFX_API 5182 extern __checkReturn efx_rc_t 5183 efx_table_entry_insert( 5184 __in efx_nic_t *enp, 5185 __in efx_table_id_t table_id, 5186 __in uint16_t priority, 5187 __in uint16_t mask_id, 5188 __in uint16_t key_width, 5189 __in uint16_t mask_width, 5190 __in uint16_t resp_width, 5191 __in_bcount(data_size) uint8_t *entry_datap, 5192 __in unsigned int data_size); 5193 5194 LIBEFX_API 5195 extern __checkReturn efx_rc_t 5196 efx_table_entry_delete( 5197 __in efx_nic_t *enp, 5198 __in efx_table_id_t table_id, 5199 __in uint16_t mask_id, 5200 __in uint16_t key_width, 5201 __in uint16_t mask_width, 5202 __in_bcount(data_size) uint8_t *entry_datap, 5203 __in unsigned int data_size); 5204 5205 #ifdef __cplusplus 5206 } 5207 #endif 5208 5209 #endif /* _SYS_EFX_H */ 5210