1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2021 Xilinx, Inc. 4 * Copyright(c) 2006-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_H 8 #define _SYS_EFX_H 9 10 #include <assert.h> 11 12 #include "efx_annote.h" 13 #include "efsys.h" 14 #include "efx_types.h" 15 #include "efx_check.h" 16 #include "efx_phy_ids.h" 17 18 #ifdef __cplusplus 19 extern "C" { 20 #endif 21 22 /* 23 * Triggers an error at compilation time if the condition is false. 24 * 25 * The { } exists to workaround a bug in clang (#55821) 26 * where it would not handle _Static_assert in a switch case. 27 */ 28 #define EFX_STATIC_ASSERT(_cond) \ 29 { static_assert((_cond), #_cond); } 30 31 #define EFX_ARRAY_SIZE(_array) \ 32 (sizeof (_array) / sizeof ((_array)[0])) 33 34 #define EFX_FIELD_OFFSET(_type, _field) \ 35 offsetof(_type, _field) 36 37 /* The macro expands divider twice */ 38 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) 39 40 /* Round value up to the nearest power of two. */ 41 #define EFX_P2ROUNDUP(_type, _value, _align) \ 42 (-(-(_type)(_value) & -(_type)(_align))) 43 44 /* Align value down to the nearest power of two. */ 45 #define EFX_P2ALIGN(_type, _value, _align) \ 46 ((_type)(_value) & -(_type)(_align)) 47 48 /* Test if value is power of 2 aligned. */ 49 #define EFX_IS_P2ALIGNED(_type, _value, _align) \ 50 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0) 51 52 /* Return codes */ 53 54 typedef __success(return == 0) int efx_rc_t; 55 56 57 /* Chip families */ 58 59 typedef enum efx_family_e { 60 EFX_FAMILY_INVALID, 61 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 62 EFX_FAMILY_SIENA, 63 EFX_FAMILY_HUNTINGTON, 64 EFX_FAMILY_MEDFORD, 65 EFX_FAMILY_MEDFORD2, 66 EFX_FAMILY_RIVERHEAD, 67 EFX_FAMILY_NTYPES 68 } efx_family_t; 69 70 typedef enum efx_bar_type_e { 71 EFX_BAR_TYPE_MEM, 72 EFX_BAR_TYPE_IO 73 } efx_bar_type_t; 74 75 typedef struct efx_bar_region_s { 76 efx_bar_type_t ebr_type; 77 int ebr_index; 78 efsys_dma_addr_t ebr_offset; 79 efsys_dma_addr_t ebr_length; 80 } efx_bar_region_t; 81 82 /* The function is deprecated. It is used only if Riverhead is not supported. */ 83 LIBEFX_API 84 extern __checkReturn efx_rc_t 85 efx_family( 86 __in uint16_t venid, 87 __in uint16_t devid, 88 __out efx_family_t *efp, 89 __out unsigned int *membarp); 90 91 #if EFSYS_OPT_PCI 92 93 /* PCIe interface numbers for multi-host configurations. */ 94 typedef enum efx_pcie_interface_e { 95 EFX_PCIE_INTERFACE_CALLER = 1000, 96 EFX_PCIE_INTERFACE_HOST_PRIMARY, 97 EFX_PCIE_INTERFACE_NIC_EMBEDDED, 98 } efx_pcie_interface_t; 99 100 typedef struct efx_pci_ops_s { 101 /* 102 * Function for reading PCIe configuration space. 103 * 104 * espcp System-specific PCIe device handle; 105 * offset Offset inside PCIe configuration space to start reading 106 * from; 107 * edp EFX DWORD structure that should be populated by function 108 * in little-endian order; 109 * 110 * Returns status code, 0 on success, any other value on error. 111 */ 112 efx_rc_t (*epo_config_readd)(efsys_pci_config_t *espcp, 113 uint32_t offset, efx_dword_t *edp); 114 /* 115 * Function for finding PCIe memory bar handle by its index from a PCIe 116 * device handle. The found memory bar is available in read-only mode. 117 * 118 * configp System-specific PCIe device handle; 119 * index Memory bar index; 120 * memp Pointer to the found memory bar handle; 121 * 122 * Returns status code, 0 on success, any other value on error. 123 */ 124 efx_rc_t (*epo_find_mem_bar)(efsys_pci_config_t *configp, 125 int index, efsys_bar_t *memp); 126 } efx_pci_ops_t; 127 128 /* Determine EFX family and perform lookup of the function control window 129 * 130 * The function requires PCI config handle from which all memory bars can 131 * be accessed. 132 * A user of the API must be aware of memory bars indexes (not available 133 * on Windows). 134 */ 135 LIBEFX_API 136 extern __checkReturn efx_rc_t 137 efx_family_probe_bar( 138 __in uint16_t venid, 139 __in uint16_t devid, 140 __in efsys_pci_config_t *espcp, 141 __in const efx_pci_ops_t *epop, 142 __out efx_family_t *efp, 143 __out efx_bar_region_t *ebrp); 144 145 #endif /* EFSYS_OPT_PCI */ 146 147 148 #define EFX_PCI_VENID_SFC 0x1924 149 #define EFX_PCI_VENID_XILINX 0x10EE 150 151 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 152 153 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 154 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 155 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 156 157 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 158 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 159 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 160 161 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 162 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 163 164 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 165 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 166 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 167 168 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13 169 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */ 170 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */ 171 172 #define EFX_PCI_DEVID_RIVERHEAD 0x0100 173 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100 174 175 #define EFX_MEM_BAR_SIENA 2 176 177 #define EFX_MEM_BAR_HUNTINGTON_PF 2 178 #define EFX_MEM_BAR_HUNTINGTON_VF 0 179 180 #define EFX_MEM_BAR_MEDFORD_PF 2 181 #define EFX_MEM_BAR_MEDFORD_VF 0 182 183 #define EFX_MEM_BAR_MEDFORD2 0 184 185 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */ 186 #define EFX_MEM_BAR_RIVERHEAD 2 187 188 189 /* Error codes */ 190 191 enum { 192 EFX_ERR_INVALID, 193 EFX_ERR_SRAM_OOB, 194 EFX_ERR_BUFID_DC_OOB, 195 EFX_ERR_MEM_PERR, 196 EFX_ERR_RBUF_OWN, 197 EFX_ERR_TBUF_OWN, 198 EFX_ERR_RDESQ_OWN, 199 EFX_ERR_TDESQ_OWN, 200 EFX_ERR_EVQ_OWN, 201 EFX_ERR_EVFF_OFLO, 202 EFX_ERR_ILL_ADDR, 203 EFX_ERR_SRAM_PERR, 204 EFX_ERR_NCODES 205 }; 206 207 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 208 LIBEFX_API 209 extern __checkReturn uint32_t 210 efx_crc32_calculate( 211 __in uint32_t crc_init, 212 __in_ecount(length) uint8_t const *input, 213 __in int length); 214 215 216 /* Type prototypes */ 217 218 typedef struct efx_rxq_s efx_rxq_t; 219 220 /* NIC */ 221 222 typedef struct efx_nic_s efx_nic_t; 223 224 LIBEFX_API 225 extern __checkReturn efx_rc_t 226 efx_nic_create( 227 __in efx_family_t family, 228 __in efsys_identifier_t *esip, 229 __in efsys_bar_t *esbp, 230 __in uint32_t fcw_offset, 231 __in efsys_lock_t *eslp, 232 __deref_out efx_nic_t **enpp); 233 234 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */ 235 typedef enum efx_fw_variant_e { 236 EFX_FW_VARIANT_FULL_FEATURED, 237 EFX_FW_VARIANT_LOW_LATENCY, 238 EFX_FW_VARIANT_PACKED_STREAM, 239 EFX_FW_VARIANT_HIGH_TX_RATE, 240 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1, 241 EFX_FW_VARIANT_RULES_ENGINE, 242 EFX_FW_VARIANT_DPDK, 243 EFX_FW_VARIANT_DONT_CARE = 0xffffffff 244 } efx_fw_variant_t; 245 246 LIBEFX_API 247 extern __checkReturn efx_rc_t 248 efx_nic_probe( 249 __in efx_nic_t *enp, 250 __in efx_fw_variant_t efv); 251 252 LIBEFX_API 253 extern __checkReturn efx_rc_t 254 efx_nic_init( 255 __in efx_nic_t *enp); 256 257 LIBEFX_API 258 extern __checkReturn efx_rc_t 259 efx_nic_reset( 260 __in efx_nic_t *enp); 261 262 LIBEFX_API 263 extern __checkReturn boolean_t 264 efx_nic_hw_unavailable( 265 __in efx_nic_t *enp); 266 267 LIBEFX_API 268 extern void 269 efx_nic_set_hw_unavailable( 270 __in efx_nic_t *enp); 271 272 #if EFSYS_OPT_DIAG 273 274 LIBEFX_API 275 extern __checkReturn efx_rc_t 276 efx_nic_register_test( 277 __in efx_nic_t *enp); 278 279 #endif /* EFSYS_OPT_DIAG */ 280 281 LIBEFX_API 282 extern void 283 efx_nic_fini( 284 __in efx_nic_t *enp); 285 286 LIBEFX_API 287 extern void 288 efx_nic_unprobe( 289 __in efx_nic_t *enp); 290 291 LIBEFX_API 292 extern void 293 efx_nic_destroy( 294 __in efx_nic_t *enp); 295 296 #define EFX_PCIE_LINK_SPEED_GEN1 1 297 #define EFX_PCIE_LINK_SPEED_GEN2 2 298 #define EFX_PCIE_LINK_SPEED_GEN3 3 299 300 typedef enum efx_pcie_link_performance_e { 301 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 302 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 303 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 304 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 305 } efx_pcie_link_performance_t; 306 307 LIBEFX_API 308 extern __checkReturn efx_rc_t 309 efx_nic_calculate_pcie_link_bandwidth( 310 __in uint32_t pcie_link_width, 311 __in uint32_t pcie_link_gen, 312 __out uint32_t *bandwidth_mbpsp); 313 314 LIBEFX_API 315 extern __checkReturn efx_rc_t 316 efx_nic_check_pcie_link_speed( 317 __in efx_nic_t *enp, 318 __in uint32_t pcie_link_width, 319 __in uint32_t pcie_link_gen, 320 __out efx_pcie_link_performance_t *resultp); 321 322 typedef enum efx_port_usage_e { 323 EFX_PORT_USAGE_UNKNOWN = 0, 324 EFX_PORT_USAGE_EXCLUSIVE, /* Port only used by this PF */ 325 EFX_PORT_USAGE_SHARED, /* Port shared with other PFs */ 326 } efx_port_usage_t; 327 328 #define EFX_MAC_ADDR_LEN 6 329 330 #if EFSYS_OPT_MCDI 331 332 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 333 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */ 334 #define WITH_MCDI_V2 1 335 #endif 336 337 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 338 339 typedef enum efx_mcdi_exception_e { 340 EFX_MCDI_EXCEPTION_MC_REBOOT, 341 EFX_MCDI_EXCEPTION_MC_BADASSERT, 342 } efx_mcdi_exception_t; 343 344 #if EFSYS_OPT_MCDI_LOGGING 345 typedef enum efx_log_msg_e { 346 EFX_LOG_INVALID, 347 EFX_LOG_MCDI_REQUEST, 348 EFX_LOG_MCDI_RESPONSE, 349 } efx_log_msg_t; 350 #endif /* EFSYS_OPT_MCDI_LOGGING */ 351 352 typedef struct efx_mcdi_transport_s { 353 void *emt_context; 354 efsys_mem_t *emt_dma_mem; 355 void (*emt_execute)(void *, efx_mcdi_req_t *); 356 void (*emt_ev_cpl)(void *); 357 void (*emt_exception)(void *, efx_mcdi_exception_t); 358 #if EFSYS_OPT_MCDI_LOGGING 359 void (*emt_logger)(void *, efx_log_msg_t, 360 void *, size_t, void *, size_t); 361 #endif /* EFSYS_OPT_MCDI_LOGGING */ 362 #if EFSYS_OPT_MCDI_PROXY_AUTH 363 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 364 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 365 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 366 void (*emt_ev_proxy_request)(void *, uint32_t); 367 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 368 } efx_mcdi_transport_t; 369 370 LIBEFX_API 371 extern __checkReturn efx_rc_t 372 efx_mcdi_init( 373 __in efx_nic_t *enp, 374 __in const efx_mcdi_transport_t *mtp); 375 376 LIBEFX_API 377 extern __checkReturn efx_rc_t 378 efx_mcdi_reboot( 379 __in efx_nic_t *enp); 380 381 LIBEFX_API 382 extern void 383 efx_mcdi_new_epoch( 384 __in efx_nic_t *enp); 385 386 LIBEFX_API 387 extern void 388 efx_mcdi_get_timeout( 389 __in efx_nic_t *enp, 390 __in efx_mcdi_req_t *emrp, 391 __out uint32_t *usec_timeoutp); 392 393 LIBEFX_API 394 extern void 395 efx_mcdi_request_start( 396 __in efx_nic_t *enp, 397 __in efx_mcdi_req_t *emrp, 398 __in boolean_t ev_cpl); 399 400 LIBEFX_API 401 extern __checkReturn boolean_t 402 efx_mcdi_request_poll( 403 __in efx_nic_t *enp); 404 405 LIBEFX_API 406 extern __checkReturn boolean_t 407 efx_mcdi_request_abort( 408 __in efx_nic_t *enp); 409 410 LIBEFX_API 411 extern __checkReturn efx_rc_t 412 efx_mcdi_get_client_handle( 413 __in efx_nic_t *enp, 414 __in efx_pcie_interface_t intf, 415 __in uint16_t pf, 416 __in uint16_t vf, 417 __out uint32_t *handle); 418 419 LIBEFX_API 420 extern __checkReturn efx_rc_t 421 efx_mcdi_get_own_client_handle( 422 __in efx_nic_t *enp, 423 __out uint32_t *handle); 424 425 LIBEFX_API 426 extern __checkReturn efx_rc_t 427 efx_mcdi_client_mac_addr_get( 428 __in efx_nic_t *enp, 429 __in uint32_t client_handle, 430 __out uint8_t addr_bytes[EFX_MAC_ADDR_LEN]); 431 432 LIBEFX_API 433 extern __checkReturn efx_rc_t 434 efx_mcdi_client_mac_addr_set( 435 __in efx_nic_t *enp, 436 __in uint32_t client_handle, 437 __in const uint8_t addr_bytes[EFX_MAC_ADDR_LEN]); 438 439 LIBEFX_API 440 extern void 441 efx_mcdi_fini( 442 __in efx_nic_t *enp); 443 444 #endif /* EFSYS_OPT_MCDI */ 445 446 /* INTR */ 447 448 #define EFX_NINTR_SIENA 1024 449 450 typedef enum efx_intr_type_e { 451 EFX_INTR_INVALID = 0, 452 EFX_INTR_LINE, 453 EFX_INTR_MESSAGE, 454 EFX_INTR_NTYPES 455 } efx_intr_type_t; 456 457 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 458 459 LIBEFX_API 460 extern __checkReturn efx_rc_t 461 efx_intr_init( 462 __in efx_nic_t *enp, 463 __in efx_intr_type_t type, 464 __in_opt efsys_mem_t *esmp); 465 466 LIBEFX_API 467 extern void 468 efx_intr_enable( 469 __in efx_nic_t *enp); 470 471 LIBEFX_API 472 extern void 473 efx_intr_disable( 474 __in efx_nic_t *enp); 475 476 LIBEFX_API 477 extern void 478 efx_intr_disable_unlocked( 479 __in efx_nic_t *enp); 480 481 #define EFX_INTR_NEVQS 32 482 483 LIBEFX_API 484 extern __checkReturn efx_rc_t 485 efx_intr_trigger( 486 __in efx_nic_t *enp, 487 __in unsigned int level); 488 489 LIBEFX_API 490 extern void 491 efx_intr_status_line( 492 __in efx_nic_t *enp, 493 __out boolean_t *fatalp, 494 __out uint32_t *maskp); 495 496 LIBEFX_API 497 extern void 498 efx_intr_status_message( 499 __in efx_nic_t *enp, 500 __in unsigned int message, 501 __out boolean_t *fatalp); 502 503 LIBEFX_API 504 extern void 505 efx_intr_fatal( 506 __in efx_nic_t *enp); 507 508 LIBEFX_API 509 extern void 510 efx_intr_fini( 511 __in efx_nic_t *enp); 512 513 /* MAC */ 514 515 #if EFSYS_OPT_MAC_STATS 516 517 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */ 518 typedef enum efx_mac_stat_e { 519 EFX_MAC_RX_OCTETS, 520 EFX_MAC_RX_PKTS, 521 EFX_MAC_RX_UNICST_PKTS, 522 EFX_MAC_RX_MULTICST_PKTS, 523 EFX_MAC_RX_BRDCST_PKTS, 524 EFX_MAC_RX_PAUSE_PKTS, 525 EFX_MAC_RX_LE_64_PKTS, 526 EFX_MAC_RX_65_TO_127_PKTS, 527 EFX_MAC_RX_128_TO_255_PKTS, 528 EFX_MAC_RX_256_TO_511_PKTS, 529 EFX_MAC_RX_512_TO_1023_PKTS, 530 EFX_MAC_RX_1024_TO_15XX_PKTS, 531 EFX_MAC_RX_GE_15XX_PKTS, 532 EFX_MAC_RX_ERRORS, 533 EFX_MAC_RX_FCS_ERRORS, 534 EFX_MAC_RX_DROP_EVENTS, 535 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 536 EFX_MAC_RX_SYMBOL_ERRORS, 537 EFX_MAC_RX_ALIGN_ERRORS, 538 EFX_MAC_RX_INTERNAL_ERRORS, 539 EFX_MAC_RX_JABBER_PKTS, 540 EFX_MAC_RX_LANE0_CHAR_ERR, 541 EFX_MAC_RX_LANE1_CHAR_ERR, 542 EFX_MAC_RX_LANE2_CHAR_ERR, 543 EFX_MAC_RX_LANE3_CHAR_ERR, 544 EFX_MAC_RX_LANE0_DISP_ERR, 545 EFX_MAC_RX_LANE1_DISP_ERR, 546 EFX_MAC_RX_LANE2_DISP_ERR, 547 EFX_MAC_RX_LANE3_DISP_ERR, 548 EFX_MAC_RX_MATCH_FAULT, 549 EFX_MAC_RX_NODESC_DROP_CNT, 550 EFX_MAC_TX_OCTETS, 551 EFX_MAC_TX_PKTS, 552 EFX_MAC_TX_UNICST_PKTS, 553 EFX_MAC_TX_MULTICST_PKTS, 554 EFX_MAC_TX_BRDCST_PKTS, 555 EFX_MAC_TX_PAUSE_PKTS, 556 EFX_MAC_TX_LE_64_PKTS, 557 EFX_MAC_TX_65_TO_127_PKTS, 558 EFX_MAC_TX_128_TO_255_PKTS, 559 EFX_MAC_TX_256_TO_511_PKTS, 560 EFX_MAC_TX_512_TO_1023_PKTS, 561 EFX_MAC_TX_1024_TO_15XX_PKTS, 562 EFX_MAC_TX_GE_15XX_PKTS, 563 EFX_MAC_TX_ERRORS, 564 EFX_MAC_TX_SGL_COL_PKTS, 565 EFX_MAC_TX_MULT_COL_PKTS, 566 EFX_MAC_TX_EX_COL_PKTS, 567 EFX_MAC_TX_LATE_COL_PKTS, 568 EFX_MAC_TX_DEF_PKTS, 569 EFX_MAC_TX_EX_DEF_PKTS, 570 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 571 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 572 EFX_MAC_PM_TRUNC_VFIFO_FULL, 573 EFX_MAC_PM_DISCARD_VFIFO_FULL, 574 EFX_MAC_PM_TRUNC_QBB, 575 EFX_MAC_PM_DISCARD_QBB, 576 EFX_MAC_PM_DISCARD_MAPPING, 577 EFX_MAC_RXDP_Q_DISABLED_PKTS, 578 EFX_MAC_RXDP_DI_DROPPED_PKTS, 579 EFX_MAC_RXDP_STREAMING_PKTS, 580 EFX_MAC_RXDP_HLB_FETCH, 581 EFX_MAC_RXDP_HLB_WAIT, 582 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 583 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 584 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 585 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 586 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 587 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 588 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 589 EFX_MAC_VADAPTER_RX_BAD_BYTES, 590 EFX_MAC_VADAPTER_RX_OVERFLOW, 591 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 592 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 593 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 594 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 595 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 596 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 597 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 598 EFX_MAC_VADAPTER_TX_BAD_BYTES, 599 EFX_MAC_VADAPTER_TX_OVERFLOW, 600 EFX_MAC_FEC_UNCORRECTED_ERRORS, 601 EFX_MAC_FEC_CORRECTED_ERRORS, 602 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0, 603 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1, 604 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2, 605 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3, 606 EFX_MAC_CTPIO_VI_BUSY_FALLBACK, 607 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS, 608 EFX_MAC_CTPIO_MISSING_DBELL_FAIL, 609 EFX_MAC_CTPIO_OVERFLOW_FAIL, 610 EFX_MAC_CTPIO_UNDERFLOW_FAIL, 611 EFX_MAC_CTPIO_TIMEOUT_FAIL, 612 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL, 613 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL, 614 EFX_MAC_CTPIO_INVALID_WR_FAIL, 615 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK, 616 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK, 617 EFX_MAC_CTPIO_RUNT_FALLBACK, 618 EFX_MAC_CTPIO_SUCCESS, 619 EFX_MAC_CTPIO_FALLBACK, 620 EFX_MAC_CTPIO_POISON, 621 EFX_MAC_CTPIO_ERASE, 622 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC, 623 EFX_MAC_RXDP_HLB_IDLE, 624 EFX_MAC_RXDP_HLB_TIMEOUT, 625 EFX_MAC_NSTATS 626 } efx_mac_stat_t; 627 628 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 629 630 #endif /* EFSYS_OPT_MAC_STATS */ 631 632 typedef enum efx_link_mode_e { 633 EFX_LINK_UNKNOWN = 0, 634 EFX_LINK_DOWN, 635 EFX_LINK_10HDX, 636 EFX_LINK_10FDX, 637 EFX_LINK_100HDX, 638 EFX_LINK_100FDX, 639 EFX_LINK_1000HDX, 640 EFX_LINK_1000FDX, 641 EFX_LINK_10000FDX, 642 EFX_LINK_40000FDX, 643 EFX_LINK_25000FDX, 644 EFX_LINK_50000FDX, 645 EFX_LINK_100000FDX, 646 EFX_LINK_NMODES 647 } efx_link_mode_t; 648 649 #define EFX_VNI_OR_VSID_LEN 3 650 651 #define EFX_MAC_ADDR_IS_MULTICAST(_address) \ 652 (((const uint8_t *)_address)[0] & 0x01) 653 654 #define EFX_MAC_MULTICAST_LIST_MAX 256 655 656 #define EFX_MAC_SDU_MAX 9202 657 658 #define EFX_MAC_PDU_ADJUSTMENT \ 659 (/* EtherII */ 14 \ 660 + /* VLAN */ 4 \ 661 + /* CRC */ 4 \ 662 + /* bug16011 */ 16) \ 663 664 #define EFX_MAC_PDU(_sdu) \ 665 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 666 667 /* 668 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 669 * the SDU rounded up slightly. 670 */ 671 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 672 673 #define EFX_MAC_PDU_MIN 60 674 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 675 676 LIBEFX_API 677 extern __checkReturn efx_rc_t 678 efx_mac_pdu_get( 679 __in efx_nic_t *enp, 680 __out size_t *pdu); 681 682 LIBEFX_API 683 extern __checkReturn efx_rc_t 684 efx_mac_pdu_set( 685 __in efx_nic_t *enp, 686 __in size_t pdu); 687 688 LIBEFX_API 689 extern __checkReturn efx_rc_t 690 efx_mac_addr_set( 691 __in efx_nic_t *enp, 692 __in uint8_t *addr); 693 694 LIBEFX_API 695 extern __checkReturn efx_rc_t 696 efx_mac_filter_set( 697 __in efx_nic_t *enp, 698 __in boolean_t all_unicst, 699 __in boolean_t mulcst, 700 __in boolean_t all_mulcst, 701 __in boolean_t brdcst); 702 703 LIBEFX_API 704 extern void 705 efx_mac_filter_get_all_ucast_mcast( 706 __in efx_nic_t *enp, 707 __out boolean_t *all_unicst, 708 __out boolean_t *all_mulcst); 709 710 LIBEFX_API 711 extern __checkReturn efx_rc_t 712 efx_mac_multicast_list_set( 713 __in efx_nic_t *enp, 714 __in_ecount(6*count) uint8_t const *addrs, 715 __in int count); 716 717 LIBEFX_API 718 extern __checkReturn efx_rc_t 719 efx_mac_filter_default_rxq_set( 720 __in efx_nic_t *enp, 721 __in efx_rxq_t *erp, 722 __in boolean_t using_rss); 723 724 LIBEFX_API 725 extern void 726 efx_mac_filter_default_rxq_clear( 727 __in efx_nic_t *enp); 728 729 LIBEFX_API 730 extern __checkReturn efx_rc_t 731 efx_mac_drain( 732 __in efx_nic_t *enp, 733 __in boolean_t enabled); 734 735 LIBEFX_API 736 extern __checkReturn efx_rc_t 737 efx_mac_up( 738 __in efx_nic_t *enp, 739 __out boolean_t *mac_upp); 740 741 #define EFX_FCNTL_RESPOND 0x00000001 742 #define EFX_FCNTL_GENERATE 0x00000002 743 744 LIBEFX_API 745 extern __checkReturn efx_rc_t 746 efx_mac_fcntl_set( 747 __in efx_nic_t *enp, 748 __in unsigned int fcntl, 749 __in boolean_t autoneg); 750 751 LIBEFX_API 752 extern void 753 efx_mac_fcntl_get( 754 __in efx_nic_t *enp, 755 __out unsigned int *fcntl_wantedp, 756 __out unsigned int *fcntl_linkp); 757 758 LIBEFX_API 759 extern __checkReturn efx_rc_t 760 efx_mac_include_fcs_set( 761 __in efx_nic_t *enp, 762 __in boolean_t enabled); 763 764 #if EFSYS_OPT_MAC_STATS 765 766 #if EFSYS_OPT_NAMES 767 768 LIBEFX_API 769 extern __checkReturn const char * 770 efx_mac_stat_name( 771 __in efx_nic_t *enp, 772 __in unsigned int id); 773 774 #endif /* EFSYS_OPT_NAMES */ 775 776 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 777 778 #define EFX_MAC_STATS_MASK_NPAGES \ 779 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \ 780 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 781 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 782 783 /* 784 * Get mask of MAC statistics supported by the hardware. 785 * 786 * If mask_size is insufficient to return the mask, EINVAL error is 787 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 788 * (which is sizeof (uint32_t)) is sufficient. 789 */ 790 LIBEFX_API 791 extern __checkReturn efx_rc_t 792 efx_mac_stats_get_mask( 793 __in efx_nic_t *enp, 794 __out_bcount(mask_size) uint32_t *maskp, 795 __in size_t mask_size); 796 797 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 798 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 799 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 800 801 802 LIBEFX_API 803 extern __checkReturn efx_rc_t 804 efx_mac_stats_clear( 805 __in efx_nic_t *enp); 806 807 /* 808 * Upload mac statistics supported by the hardware into the given buffer. 809 * 810 * The DMA buffer must be 4Kbyte aligned and sized to hold at least 811 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters. 812 * 813 * The hardware will only DMA statistics that it understands (of course). 814 * Drivers should not make any assumptions about which statistics are 815 * supported, especially when the statistics are generated by firmware. 816 * 817 * Thus, drivers should zero this buffer before use, so that not-understood 818 * statistics read back as zero. 819 */ 820 LIBEFX_API 821 extern __checkReturn efx_rc_t 822 efx_mac_stats_upload( 823 __in efx_nic_t *enp, 824 __in efsys_mem_t *esmp); 825 826 LIBEFX_API 827 extern __checkReturn efx_rc_t 828 efx_mac_stats_periodic( 829 __in efx_nic_t *enp, 830 __in efsys_mem_t *esmp, 831 __in uint16_t period_ms, 832 __in boolean_t events); 833 834 LIBEFX_API 835 extern __checkReturn efx_rc_t 836 efx_mac_stats_update( 837 __in efx_nic_t *enp, 838 __in efsys_mem_t *esmp, 839 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 840 __inout_opt uint32_t *generationp); 841 842 #endif /* EFSYS_OPT_MAC_STATS */ 843 844 /* MON */ 845 846 typedef enum efx_mon_type_e { 847 EFX_MON_INVALID = 0, 848 EFX_MON_SFC90X0, 849 EFX_MON_SFC91X0, 850 EFX_MON_SFC92X0, 851 EFX_MON_NTYPES 852 } efx_mon_type_t; 853 854 #if EFSYS_OPT_NAMES 855 856 LIBEFX_API 857 extern const char * 858 efx_mon_name( 859 __in efx_nic_t *enp); 860 861 #endif /* EFSYS_OPT_NAMES */ 862 863 LIBEFX_API 864 extern __checkReturn efx_rc_t 865 efx_mon_init( 866 __in efx_nic_t *enp); 867 868 #if EFSYS_OPT_MON_STATS 869 870 #define EFX_MON_STATS_PAGE_SIZE 0x100 871 #define EFX_MON_MASK_ELEMENT_SIZE 32 872 873 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */ 874 typedef enum efx_mon_stat_e { 875 EFX_MON_STAT_CONTROLLER_TEMP, 876 EFX_MON_STAT_PHY_COMMON_TEMP, 877 EFX_MON_STAT_CONTROLLER_COOLING, 878 EFX_MON_STAT_PHY0_TEMP, 879 EFX_MON_STAT_PHY0_COOLING, 880 EFX_MON_STAT_PHY1_TEMP, 881 EFX_MON_STAT_PHY1_COOLING, 882 EFX_MON_STAT_IN_1V0, 883 EFX_MON_STAT_IN_1V2, 884 EFX_MON_STAT_IN_1V8, 885 EFX_MON_STAT_IN_2V5, 886 EFX_MON_STAT_IN_3V3, 887 EFX_MON_STAT_IN_12V0, 888 EFX_MON_STAT_IN_1V2A, 889 EFX_MON_STAT_IN_VREF, 890 EFX_MON_STAT_OUT_VAOE, 891 EFX_MON_STAT_AOE_TEMP, 892 EFX_MON_STAT_PSU_AOE_TEMP, 893 EFX_MON_STAT_PSU_TEMP, 894 EFX_MON_STAT_FAN_0, 895 EFX_MON_STAT_FAN_1, 896 EFX_MON_STAT_FAN_2, 897 EFX_MON_STAT_FAN_3, 898 EFX_MON_STAT_FAN_4, 899 EFX_MON_STAT_IN_VAOE, 900 EFX_MON_STAT_OUT_IAOE, 901 EFX_MON_STAT_IN_IAOE, 902 EFX_MON_STAT_NIC_POWER, 903 EFX_MON_STAT_IN_0V9, 904 EFX_MON_STAT_IN_I0V9, 905 EFX_MON_STAT_IN_I1V2, 906 EFX_MON_STAT_IN_0V9_ADC, 907 EFX_MON_STAT_CONTROLLER_2_TEMP, 908 EFX_MON_STAT_VREG_INTERNAL_TEMP, 909 EFX_MON_STAT_VREG_0V9_TEMP, 910 EFX_MON_STAT_VREG_1V2_TEMP, 911 EFX_MON_STAT_CONTROLLER_VPTAT, 912 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP, 913 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC, 914 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC, 915 EFX_MON_STAT_AMBIENT_TEMP, 916 EFX_MON_STAT_AIRFLOW, 917 EFX_MON_STAT_VDD08D_VSS08D_CSR, 918 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 919 EFX_MON_STAT_HOTPOINT_TEMP, 920 EFX_MON_STAT_PHY_POWER_PORT0, 921 EFX_MON_STAT_PHY_POWER_PORT1, 922 EFX_MON_STAT_MUM_VCC, 923 EFX_MON_STAT_IN_0V9_A, 924 EFX_MON_STAT_IN_I0V9_A, 925 EFX_MON_STAT_VREG_0V9_A_TEMP, 926 EFX_MON_STAT_IN_0V9_B, 927 EFX_MON_STAT_IN_I0V9_B, 928 EFX_MON_STAT_VREG_0V9_B_TEMP, 929 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 930 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC, 931 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 932 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC, 933 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 934 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 935 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC, 936 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC, 937 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 938 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 939 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC, 940 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC, 941 EFX_MON_STAT_SODIMM_VOUT, 942 EFX_MON_STAT_SODIMM_0_TEMP, 943 EFX_MON_STAT_SODIMM_1_TEMP, 944 EFX_MON_STAT_PHY0_VCC, 945 EFX_MON_STAT_PHY1_VCC, 946 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 947 EFX_MON_STAT_BOARD_FRONT_TEMP, 948 EFX_MON_STAT_BOARD_BACK_TEMP, 949 EFX_MON_STAT_IN_I1V8, 950 EFX_MON_STAT_IN_I2V5, 951 EFX_MON_STAT_IN_I3V3, 952 EFX_MON_STAT_IN_I12V0, 953 EFX_MON_STAT_IN_1V3, 954 EFX_MON_STAT_IN_I1V3, 955 EFX_MON_NSTATS 956 } efx_mon_stat_t; 957 958 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 959 960 typedef enum efx_mon_stat_state_e { 961 EFX_MON_STAT_STATE_OK = 0, 962 EFX_MON_STAT_STATE_WARNING = 1, 963 EFX_MON_STAT_STATE_FATAL = 2, 964 EFX_MON_STAT_STATE_BROKEN = 3, 965 EFX_MON_STAT_STATE_NO_READING = 4, 966 } efx_mon_stat_state_t; 967 968 typedef enum efx_mon_stat_unit_e { 969 EFX_MON_STAT_UNIT_UNKNOWN = 0, 970 EFX_MON_STAT_UNIT_BOOL, 971 EFX_MON_STAT_UNIT_TEMP_C, 972 EFX_MON_STAT_UNIT_VOLTAGE_MV, 973 EFX_MON_STAT_UNIT_CURRENT_MA, 974 EFX_MON_STAT_UNIT_POWER_W, 975 EFX_MON_STAT_UNIT_RPM, 976 EFX_MON_NUNITS 977 } efx_mon_stat_unit_t; 978 979 typedef struct efx_mon_stat_value_s { 980 uint16_t emsv_value; 981 efx_mon_stat_state_t emsv_state; 982 efx_mon_stat_unit_t emsv_unit; 983 } efx_mon_stat_value_t; 984 985 typedef struct efx_mon_limit_value_s { 986 uint16_t emlv_warning_min; 987 uint16_t emlv_warning_max; 988 uint16_t emlv_fatal_min; 989 uint16_t emlv_fatal_max; 990 } efx_mon_stat_limits_t; 991 992 typedef enum efx_mon_stat_portmask_e { 993 EFX_MON_STAT_PORTMAP_NONE = 0, 994 EFX_MON_STAT_PORTMAP_PORT0 = 1, 995 EFX_MON_STAT_PORTMAP_PORT1 = 2, 996 EFX_MON_STAT_PORTMAP_PORT2 = 3, 997 EFX_MON_STAT_PORTMAP_PORT3 = 4, 998 EFX_MON_STAT_PORTMAP_ALL = (-1), 999 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2) 1000 } efx_mon_stat_portmask_t; 1001 1002 #if EFSYS_OPT_NAMES 1003 1004 LIBEFX_API 1005 extern const char * 1006 efx_mon_stat_name( 1007 __in efx_nic_t *enp, 1008 __in efx_mon_stat_t id); 1009 1010 LIBEFX_API 1011 extern const char * 1012 efx_mon_stat_description( 1013 __in efx_nic_t *enp, 1014 __in efx_mon_stat_t id); 1015 1016 #endif /* EFSYS_OPT_NAMES */ 1017 1018 LIBEFX_API 1019 extern __checkReturn boolean_t 1020 efx_mon_mcdi_to_efx_stat( 1021 __in int mcdi_index, 1022 __out efx_mon_stat_t *statp); 1023 1024 LIBEFX_API 1025 extern __checkReturn boolean_t 1026 efx_mon_get_stat_unit( 1027 __in efx_mon_stat_t stat, 1028 __out efx_mon_stat_unit_t *unitp); 1029 1030 LIBEFX_API 1031 extern __checkReturn boolean_t 1032 efx_mon_get_stat_portmap( 1033 __in efx_mon_stat_t stat, 1034 __out efx_mon_stat_portmask_t *maskp); 1035 1036 LIBEFX_API 1037 extern __checkReturn efx_rc_t 1038 efx_mon_stats_update( 1039 __in efx_nic_t *enp, 1040 __in efsys_mem_t *esmp, 1041 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 1042 1043 LIBEFX_API 1044 extern __checkReturn efx_rc_t 1045 efx_mon_limits_update( 1046 __in efx_nic_t *enp, 1047 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values); 1048 1049 #endif /* EFSYS_OPT_MON_STATS */ 1050 1051 LIBEFX_API 1052 extern void 1053 efx_mon_fini( 1054 __in efx_nic_t *enp); 1055 1056 /* PHY */ 1057 1058 LIBEFX_API 1059 extern __checkReturn efx_rc_t 1060 efx_phy_verify( 1061 __in efx_nic_t *enp); 1062 1063 typedef enum efx_phy_led_mode_e { 1064 EFX_PHY_LED_DEFAULT = 0, 1065 EFX_PHY_LED_OFF, 1066 EFX_PHY_LED_ON, 1067 EFX_PHY_LED_FLASH, 1068 EFX_PHY_LED_NMODES 1069 } efx_phy_led_mode_t; 1070 1071 #if EFSYS_OPT_PHY_LED_CONTROL 1072 1073 LIBEFX_API 1074 extern __checkReturn efx_rc_t 1075 efx_phy_led_set( 1076 __in efx_nic_t *enp, 1077 __in efx_phy_led_mode_t mode); 1078 1079 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1080 1081 LIBEFX_API 1082 extern __checkReturn efx_rc_t 1083 efx_port_init( 1084 __in efx_nic_t *enp); 1085 1086 #if EFSYS_OPT_LOOPBACK 1087 1088 typedef enum efx_loopback_type_e { 1089 EFX_LOOPBACK_OFF = 0, 1090 EFX_LOOPBACK_DATA = 1, 1091 EFX_LOOPBACK_GMAC = 2, 1092 EFX_LOOPBACK_XGMII = 3, 1093 EFX_LOOPBACK_XGXS = 4, 1094 EFX_LOOPBACK_XAUI = 5, 1095 EFX_LOOPBACK_GMII = 6, 1096 EFX_LOOPBACK_SGMII = 7, 1097 EFX_LOOPBACK_XGBR = 8, 1098 EFX_LOOPBACK_XFI = 9, 1099 EFX_LOOPBACK_XAUI_FAR = 10, 1100 EFX_LOOPBACK_GMII_FAR = 11, 1101 EFX_LOOPBACK_SGMII_FAR = 12, 1102 EFX_LOOPBACK_XFI_FAR = 13, 1103 EFX_LOOPBACK_GPHY = 14, 1104 EFX_LOOPBACK_PHY_XS = 15, 1105 EFX_LOOPBACK_PCS = 16, 1106 EFX_LOOPBACK_PMA_PMD = 17, 1107 EFX_LOOPBACK_XPORT = 18, 1108 EFX_LOOPBACK_XGMII_WS = 19, 1109 EFX_LOOPBACK_XAUI_WS = 20, 1110 EFX_LOOPBACK_XAUI_WS_FAR = 21, 1111 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 1112 EFX_LOOPBACK_GMII_WS = 23, 1113 EFX_LOOPBACK_XFI_WS = 24, 1114 EFX_LOOPBACK_XFI_WS_FAR = 25, 1115 EFX_LOOPBACK_PHYXS_WS = 26, 1116 EFX_LOOPBACK_PMA_INT = 27, 1117 EFX_LOOPBACK_SD_NEAR = 28, 1118 EFX_LOOPBACK_SD_FAR = 29, 1119 EFX_LOOPBACK_PMA_INT_WS = 30, 1120 EFX_LOOPBACK_SD_FEP2_WS = 31, 1121 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 1122 EFX_LOOPBACK_SD_FEP_WS = 33, 1123 EFX_LOOPBACK_SD_FES_WS = 34, 1124 EFX_LOOPBACK_AOE_INT_NEAR = 35, 1125 EFX_LOOPBACK_DATA_WS = 36, 1126 EFX_LOOPBACK_FORCE_EXT_LINK = 37, 1127 EFX_LOOPBACK_NTYPES 1128 } efx_loopback_type_t; 1129 1130 typedef enum efx_loopback_kind_e { 1131 EFX_LOOPBACK_KIND_OFF = 0, 1132 EFX_LOOPBACK_KIND_ALL, 1133 EFX_LOOPBACK_KIND_MAC, 1134 EFX_LOOPBACK_KIND_PHY, 1135 EFX_LOOPBACK_NKINDS 1136 } efx_loopback_kind_t; 1137 1138 LIBEFX_API 1139 extern void 1140 efx_loopback_mask( 1141 __in efx_loopback_kind_t loopback_kind, 1142 __out efx_qword_t *maskp); 1143 1144 LIBEFX_API 1145 extern __checkReturn efx_rc_t 1146 efx_port_loopback_set( 1147 __in efx_nic_t *enp, 1148 __in efx_link_mode_t link_mode, 1149 __in efx_loopback_type_t type); 1150 1151 #if EFSYS_OPT_NAMES 1152 1153 LIBEFX_API 1154 extern __checkReturn const char * 1155 efx_loopback_type_name( 1156 __in efx_nic_t *enp, 1157 __in efx_loopback_type_t type); 1158 1159 #endif /* EFSYS_OPT_NAMES */ 1160 1161 #endif /* EFSYS_OPT_LOOPBACK */ 1162 1163 LIBEFX_API 1164 extern __checkReturn efx_rc_t 1165 efx_port_poll( 1166 __in efx_nic_t *enp, 1167 __out_opt efx_link_mode_t *link_modep); 1168 1169 LIBEFX_API 1170 extern __checkReturn efx_rc_t 1171 efx_port_vlan_strip_set( 1172 __in efx_nic_t *enp, 1173 __in boolean_t enabled); 1174 1175 LIBEFX_API 1176 extern void 1177 efx_port_fini( 1178 __in efx_nic_t *enp); 1179 1180 typedef enum efx_phy_cap_type_e { 1181 EFX_PHY_CAP_INVALID = 0, 1182 EFX_PHY_CAP_10HDX, 1183 EFX_PHY_CAP_10FDX, 1184 EFX_PHY_CAP_100HDX, 1185 EFX_PHY_CAP_100FDX, 1186 EFX_PHY_CAP_1000HDX, 1187 EFX_PHY_CAP_1000FDX, 1188 EFX_PHY_CAP_10000FDX, 1189 EFX_PHY_CAP_PAUSE, 1190 EFX_PHY_CAP_ASYM, 1191 EFX_PHY_CAP_AN, 1192 EFX_PHY_CAP_40000FDX, 1193 EFX_PHY_CAP_DDM, 1194 EFX_PHY_CAP_100000FDX, 1195 EFX_PHY_CAP_25000FDX, 1196 EFX_PHY_CAP_50000FDX, 1197 EFX_PHY_CAP_BASER_FEC, 1198 EFX_PHY_CAP_BASER_FEC_REQUESTED, 1199 EFX_PHY_CAP_RS_FEC, 1200 EFX_PHY_CAP_RS_FEC_REQUESTED, 1201 EFX_PHY_CAP_25G_BASER_FEC, 1202 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED, 1203 EFX_PHY_CAP_NTYPES 1204 } efx_phy_cap_type_t; 1205 1206 1207 #define EFX_PHY_CAP_CURRENT 0x00000000 1208 #define EFX_PHY_CAP_DEFAULT 0x00000001 1209 #define EFX_PHY_CAP_PERM 0x00000002 1210 1211 LIBEFX_API 1212 extern void 1213 efx_phy_adv_cap_get( 1214 __in efx_nic_t *enp, 1215 __in uint32_t flag, 1216 __out uint32_t *maskp); 1217 1218 LIBEFX_API 1219 extern __checkReturn efx_rc_t 1220 efx_phy_adv_cap_set( 1221 __in efx_nic_t *enp, 1222 __in uint32_t mask); 1223 1224 LIBEFX_API 1225 extern void 1226 efx_phy_lp_cap_get( 1227 __in efx_nic_t *enp, 1228 __out uint32_t *maskp); 1229 1230 LIBEFX_API 1231 extern __checkReturn efx_rc_t 1232 efx_phy_oui_get( 1233 __in efx_nic_t *enp, 1234 __out uint32_t *ouip); 1235 1236 typedef enum efx_phy_media_type_e { 1237 EFX_PHY_MEDIA_INVALID = 0, 1238 EFX_PHY_MEDIA_XAUI, 1239 EFX_PHY_MEDIA_CX4, 1240 EFX_PHY_MEDIA_KX4, 1241 EFX_PHY_MEDIA_XFP, 1242 EFX_PHY_MEDIA_SFP_PLUS, 1243 EFX_PHY_MEDIA_BASE_T, 1244 EFX_PHY_MEDIA_QSFP_PLUS, 1245 EFX_PHY_MEDIA_NTYPES 1246 } efx_phy_media_type_t; 1247 1248 /* 1249 * Get the type of medium currently used. If the board has ports for 1250 * modules, a module is present, and we recognise the media type of 1251 * the module, then this will be the media type of the module. 1252 * Otherwise it will be the media type of the port. 1253 */ 1254 LIBEFX_API 1255 extern void 1256 efx_phy_media_type_get( 1257 __in efx_nic_t *enp, 1258 __out efx_phy_media_type_t *typep); 1259 1260 /* 1261 * 2-wire device address of the base information in accordance with SFF-8472 1262 * Diagnostic Monitoring Interface for Optical Transceivers section 1263 * 4 Memory Organization. 1264 */ 1265 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0 1266 1267 /* 1268 * 2-wire device address of the digital diagnostics monitoring interface 1269 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical 1270 * Transceivers section 4 Memory Organization. 1271 */ 1272 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2 1273 1274 /* 1275 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436 1276 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and 1277 * Operation. 1278 */ 1279 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0 1280 1281 /* 1282 * Maximum accessible data offset for PHY module information. 1283 */ 1284 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100 1285 1286 1287 LIBEFX_API 1288 extern __checkReturn efx_rc_t 1289 efx_phy_module_get_info( 1290 __in efx_nic_t *enp, 1291 __in uint8_t dev_addr, 1292 __in size_t offset, 1293 __in size_t len, 1294 __out_bcount(len) uint8_t *data); 1295 1296 #if EFSYS_OPT_PHY_STATS 1297 1298 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 1299 typedef enum efx_phy_stat_e { 1300 EFX_PHY_STAT_OUI, 1301 EFX_PHY_STAT_PMA_PMD_LINK_UP, 1302 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 1303 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 1304 EFX_PHY_STAT_PMA_PMD_REV_A, 1305 EFX_PHY_STAT_PMA_PMD_REV_B, 1306 EFX_PHY_STAT_PMA_PMD_REV_C, 1307 EFX_PHY_STAT_PMA_PMD_REV_D, 1308 EFX_PHY_STAT_PCS_LINK_UP, 1309 EFX_PHY_STAT_PCS_RX_FAULT, 1310 EFX_PHY_STAT_PCS_TX_FAULT, 1311 EFX_PHY_STAT_PCS_BER, 1312 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 1313 EFX_PHY_STAT_PHY_XS_LINK_UP, 1314 EFX_PHY_STAT_PHY_XS_RX_FAULT, 1315 EFX_PHY_STAT_PHY_XS_TX_FAULT, 1316 EFX_PHY_STAT_PHY_XS_ALIGN, 1317 EFX_PHY_STAT_PHY_XS_SYNC_A, 1318 EFX_PHY_STAT_PHY_XS_SYNC_B, 1319 EFX_PHY_STAT_PHY_XS_SYNC_C, 1320 EFX_PHY_STAT_PHY_XS_SYNC_D, 1321 EFX_PHY_STAT_AN_LINK_UP, 1322 EFX_PHY_STAT_AN_MASTER, 1323 EFX_PHY_STAT_AN_LOCAL_RX_OK, 1324 EFX_PHY_STAT_AN_REMOTE_RX_OK, 1325 EFX_PHY_STAT_CL22EXT_LINK_UP, 1326 EFX_PHY_STAT_SNR_A, 1327 EFX_PHY_STAT_SNR_B, 1328 EFX_PHY_STAT_SNR_C, 1329 EFX_PHY_STAT_SNR_D, 1330 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 1331 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 1332 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 1333 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 1334 EFX_PHY_STAT_AN_COMPLETE, 1335 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 1336 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 1337 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 1338 EFX_PHY_STAT_PCS_FW_VERSION_0, 1339 EFX_PHY_STAT_PCS_FW_VERSION_1, 1340 EFX_PHY_STAT_PCS_FW_VERSION_2, 1341 EFX_PHY_STAT_PCS_FW_VERSION_3, 1342 EFX_PHY_STAT_PCS_FW_BUILD_YY, 1343 EFX_PHY_STAT_PCS_FW_BUILD_MM, 1344 EFX_PHY_STAT_PCS_FW_BUILD_DD, 1345 EFX_PHY_STAT_PCS_OP_MODE, 1346 EFX_PHY_NSTATS 1347 } efx_phy_stat_t; 1348 1349 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 1350 1351 #if EFSYS_OPT_NAMES 1352 1353 LIBEFX_API 1354 extern const char * 1355 efx_phy_stat_name( 1356 __in efx_nic_t *enp, 1357 __in efx_phy_stat_t stat); 1358 1359 #endif /* EFSYS_OPT_NAMES */ 1360 1361 #define EFX_PHY_STATS_SIZE 0x100 1362 1363 LIBEFX_API 1364 extern __checkReturn efx_rc_t 1365 efx_phy_stats_update( 1366 __in efx_nic_t *enp, 1367 __in efsys_mem_t *esmp, 1368 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 1369 1370 #endif /* EFSYS_OPT_PHY_STATS */ 1371 1372 1373 #if EFSYS_OPT_BIST 1374 1375 typedef enum efx_bist_type_e { 1376 EFX_BIST_TYPE_UNKNOWN, 1377 EFX_BIST_TYPE_PHY_NORMAL, 1378 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1379 EFX_BIST_TYPE_PHY_CABLE_LONG, 1380 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1381 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */ 1382 EFX_BIST_TYPE_REG, /* Test the register memories */ 1383 EFX_BIST_TYPE_NTYPES, 1384 } efx_bist_type_t; 1385 1386 typedef enum efx_bist_result_e { 1387 EFX_BIST_RESULT_UNKNOWN, 1388 EFX_BIST_RESULT_RUNNING, 1389 EFX_BIST_RESULT_PASSED, 1390 EFX_BIST_RESULT_FAILED, 1391 } efx_bist_result_t; 1392 1393 typedef enum efx_phy_cable_status_e { 1394 EFX_PHY_CABLE_STATUS_OK, 1395 EFX_PHY_CABLE_STATUS_INVALID, 1396 EFX_PHY_CABLE_STATUS_OPEN, 1397 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1398 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1399 EFX_PHY_CABLE_STATUS_BUSY, 1400 } efx_phy_cable_status_t; 1401 1402 typedef enum efx_bist_value_e { 1403 EFX_BIST_PHY_CABLE_LENGTH_A, 1404 EFX_BIST_PHY_CABLE_LENGTH_B, 1405 EFX_BIST_PHY_CABLE_LENGTH_C, 1406 EFX_BIST_PHY_CABLE_LENGTH_D, 1407 EFX_BIST_PHY_CABLE_STATUS_A, 1408 EFX_BIST_PHY_CABLE_STATUS_B, 1409 EFX_BIST_PHY_CABLE_STATUS_C, 1410 EFX_BIST_PHY_CABLE_STATUS_D, 1411 EFX_BIST_FAULT_CODE, 1412 /* 1413 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1414 * response. 1415 */ 1416 EFX_BIST_MEM_TEST, 1417 EFX_BIST_MEM_ADDR, 1418 EFX_BIST_MEM_BUS, 1419 EFX_BIST_MEM_EXPECT, 1420 EFX_BIST_MEM_ACTUAL, 1421 EFX_BIST_MEM_ECC, 1422 EFX_BIST_MEM_ECC_PARITY, 1423 EFX_BIST_MEM_ECC_FATAL, 1424 EFX_BIST_NVALUES, 1425 } efx_bist_value_t; 1426 1427 LIBEFX_API 1428 extern __checkReturn efx_rc_t 1429 efx_bist_enable_offline( 1430 __in efx_nic_t *enp); 1431 1432 LIBEFX_API 1433 extern __checkReturn efx_rc_t 1434 efx_bist_start( 1435 __in efx_nic_t *enp, 1436 __in efx_bist_type_t type); 1437 1438 LIBEFX_API 1439 extern __checkReturn efx_rc_t 1440 efx_bist_poll( 1441 __in efx_nic_t *enp, 1442 __in efx_bist_type_t type, 1443 __out efx_bist_result_t *resultp, 1444 __out_opt uint32_t *value_maskp, 1445 __out_ecount_opt(count) unsigned long *valuesp, 1446 __in size_t count); 1447 1448 LIBEFX_API 1449 extern void 1450 efx_bist_stop( 1451 __in efx_nic_t *enp, 1452 __in efx_bist_type_t type); 1453 1454 #endif /* EFSYS_OPT_BIST */ 1455 1456 #define EFX_FEATURE_IPV6 0x00000001 1457 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1458 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1459 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1460 #define EFX_FEATURE_MCDI 0x00000020 1461 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1462 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1463 #define EFX_FEATURE_TURBO 0x00000100 1464 #define EFX_FEATURE_MCDI_DMA 0x00000200 1465 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1466 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1467 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1468 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1469 #define EFX_FEATURE_PACKED_STREAM 0x00004000 1470 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000 1471 1472 typedef enum efx_tunnel_protocol_e { 1473 EFX_TUNNEL_PROTOCOL_NONE = 0, 1474 EFX_TUNNEL_PROTOCOL_VXLAN, 1475 EFX_TUNNEL_PROTOCOL_GENEVE, 1476 EFX_TUNNEL_PROTOCOL_NVGRE, 1477 EFX_TUNNEL_NPROTOS 1478 } efx_tunnel_protocol_t; 1479 1480 typedef enum efx_vi_window_shift_e { 1481 EFX_VI_WINDOW_SHIFT_INVALID = 0, 1482 EFX_VI_WINDOW_SHIFT_8K = 13, 1483 EFX_VI_WINDOW_SHIFT_16K = 14, 1484 EFX_VI_WINDOW_SHIFT_64K = 16, 1485 } efx_vi_window_shift_t; 1486 1487 typedef enum efx_nic_dma_mapping_e { 1488 EFX_NIC_DMA_MAPPING_UNKNOWN = 0, 1489 EFX_NIC_DMA_MAPPING_FLAT, 1490 EFX_NIC_DMA_MAPPING_REGIONED, 1491 1492 EFX_NIC_DMA_MAPPING_NTYPES 1493 } efx_nic_dma_mapping_t; 1494 1495 typedef struct efx_nic_cfg_s { 1496 uint32_t enc_board_type; 1497 uint32_t enc_phy_type; 1498 #if EFSYS_OPT_NAMES 1499 char enc_phy_name[21]; 1500 #endif 1501 char enc_phy_revision[21]; 1502 efx_mon_type_t enc_mon_type; 1503 #if EFSYS_OPT_MON_STATS 1504 uint32_t enc_mon_stat_dma_buf_size; 1505 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1506 #endif 1507 unsigned int enc_features; 1508 efx_vi_window_shift_t enc_vi_window_shift; 1509 uint8_t enc_mac_addr[6]; 1510 uint8_t enc_port; /* PHY port number */ 1511 uint32_t enc_intr_vec_base; 1512 uint32_t enc_intr_limit; 1513 uint32_t enc_evq_limit; 1514 uint32_t enc_txq_limit; 1515 uint32_t enc_rxq_limit; 1516 uint32_t enc_evq_max_nevs; 1517 uint32_t enc_evq_min_nevs; 1518 uint32_t enc_rxq_max_ndescs; 1519 uint32_t enc_rxq_min_ndescs; 1520 uint32_t enc_txq_max_ndescs; 1521 uint32_t enc_txq_min_ndescs; 1522 uint32_t enc_buftbl_limit; 1523 uint32_t enc_piobuf_limit; 1524 uint32_t enc_piobuf_size; 1525 uint32_t enc_piobuf_min_alloc_size; 1526 uint32_t enc_evq_timer_quantum_ns; 1527 uint32_t enc_evq_timer_max_us; 1528 uint32_t enc_clk_mult; 1529 uint32_t enc_ev_ew_desc_size; 1530 uint32_t enc_ev_desc_size; 1531 uint32_t enc_rx_desc_size; 1532 uint32_t enc_tx_desc_size; 1533 /* Maximum Rx prefix size if many Rx prefixes are supported */ 1534 uint32_t enc_rx_prefix_size; 1535 uint32_t enc_rx_buf_align_start; 1536 uint32_t enc_rx_buf_align_end; 1537 #if EFSYS_OPT_RX_SCALE 1538 /* 1539 * The limit on how many queues an RSS context in the even spread 1540 * mode can span. When this mode is not supported, the value is 0. 1541 */ 1542 uint32_t enc_rx_scale_even_spread_max_nqueues; 1543 /* 1544 * The limit on how many queues an RSS indirection table can address. 1545 * 1546 * Indirection table entries are offsets relative to a base queue ID. 1547 * This means that the maximum offset has to be less than this value. 1548 */ 1549 uint32_t enc_rx_scale_indirection_max_nqueues; 1550 /* Minimum number of entries an RSS indirection table can contain. */ 1551 uint32_t enc_rx_scale_tbl_min_nentries; 1552 /* Maximum number of entries an RSS indirection table can contain. */ 1553 uint32_t enc_rx_scale_tbl_max_nentries; 1554 uint32_t enc_rx_scale_max_exclusive_contexts; 1555 /* 1556 * Mask of supported hash algorithms. 1557 * Hash algorithm types are used as the bit indices. 1558 */ 1559 uint32_t enc_rx_scale_hash_alg_mask; 1560 /* 1561 * Indicates whether port numbers can be included to the 1562 * input data for hash computation. 1563 */ 1564 boolean_t enc_rx_scale_l4_hash_supported; 1565 boolean_t enc_rx_scale_additional_modes_supported; 1566 /* 1567 * Indicates whether the user can decide how many entries to 1568 * have in the indirection table of an exclusive RSS context. 1569 */ 1570 boolean_t enc_rx_scale_tbl_entry_count_is_selectable; 1571 #endif /* EFSYS_OPT_RX_SCALE */ 1572 #if EFSYS_OPT_LOOPBACK 1573 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1574 #endif /* EFSYS_OPT_LOOPBACK */ 1575 #if EFSYS_OPT_PHY_FLAGS 1576 uint32_t enc_phy_flags_mask; 1577 #endif /* EFSYS_OPT_PHY_FLAGS */ 1578 #if EFSYS_OPT_PHY_LED_CONTROL 1579 uint32_t enc_led_mask; 1580 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1581 #if EFSYS_OPT_PHY_STATS 1582 uint64_t enc_phy_stat_mask; 1583 #endif /* EFSYS_OPT_PHY_STATS */ 1584 #if EFSYS_OPT_MCDI 1585 uint8_t enc_mcdi_mdio_channel; 1586 #if EFSYS_OPT_PHY_STATS 1587 uint32_t enc_mcdi_phy_stat_mask; 1588 #endif /* EFSYS_OPT_PHY_STATS */ 1589 #if EFSYS_OPT_MON_STATS 1590 uint32_t *enc_mcdi_sensor_maskp; 1591 uint32_t enc_mcdi_sensor_mask_size; 1592 #endif /* EFSYS_OPT_MON_STATS */ 1593 #endif /* EFSYS_OPT_MCDI */ 1594 #if EFSYS_OPT_BIST 1595 uint32_t enc_bist_mask; 1596 #endif /* EFSYS_OPT_BIST */ 1597 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1598 efx_pcie_interface_t enc_intf; 1599 uint32_t enc_pf; 1600 uint32_t enc_vf; 1601 uint32_t enc_privilege_mask; 1602 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 1603 boolean_t enc_evq_init_done_ev_supported; 1604 boolean_t enc_bug26807_workaround; 1605 boolean_t enc_bug35388_workaround; 1606 boolean_t enc_bug41750_workaround; 1607 boolean_t enc_bug61265_workaround; 1608 boolean_t enc_bug61297_workaround; 1609 boolean_t enc_rx_batching_enabled; 1610 /* Maximum number of descriptors completed in an rx event. */ 1611 uint32_t enc_rx_batch_max; 1612 /* Number of rx descriptors the hardware requires for a push. */ 1613 uint32_t enc_rx_push_align; 1614 /* Maximum amount of data in DMA descriptor */ 1615 uint32_t enc_rx_dma_desc_size_max; 1616 uint32_t enc_tx_dma_desc_size_max; 1617 /* 1618 * Boundary which DMA descriptor data must not cross or 0 if no 1619 * limitation. 1620 */ 1621 uint32_t enc_tx_dma_desc_boundary; 1622 /* 1623 * Maximum number of bytes into the packet the TCP header can start for 1624 * the hardware to apply TSO packet edits. 1625 */ 1626 uint32_t enc_tx_tso_tcp_header_offset_limit; 1627 /* Maximum number of header DMA descriptors per TSO transaction. */ 1628 uint32_t enc_tx_tso_max_header_ndescs; 1629 /* Maximum header length acceptable by TSO transaction. */ 1630 uint32_t enc_tx_tso_max_header_length; 1631 /* Maximum number of payload DMA descriptors per TSO transaction. */ 1632 uint32_t enc_tx_tso_max_payload_ndescs; 1633 /* Maximum payload length per TSO transaction. */ 1634 uint32_t enc_tx_tso_max_payload_length; 1635 /* Maximum number of frames to be generated per TSO transaction. */ 1636 uint32_t enc_tx_tso_max_nframes; 1637 boolean_t enc_fw_assisted_tso_enabled; 1638 boolean_t enc_fw_assisted_tso_v2_enabled; 1639 boolean_t enc_fw_assisted_tso_v2_encap_enabled; 1640 boolean_t enc_tso_v3_enabled; 1641 /* Number of TSO contexts on the NIC (FATSOv2) */ 1642 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1643 boolean_t enc_hw_tx_insert_vlan_enabled; 1644 boolean_t enc_rx_vlan_stripping_supported; 1645 /* Number of PFs on the NIC */ 1646 uint32_t enc_hw_pf_count; 1647 /* Datapath firmware vadapter/vport/vswitch support */ 1648 boolean_t enc_datapath_cap_evb; 1649 /* Datapath firmware vport reconfigure support */ 1650 boolean_t enc_vport_reconfigure_supported; 1651 boolean_t enc_rx_disable_scatter_supported; 1652 boolean_t enc_rx_include_fcs_supported; 1653 /* Maximum number of Rx scatter segments supported by HW */ 1654 uint32_t enc_rx_scatter_max; 1655 boolean_t enc_allow_set_mac_with_installed_filters; 1656 boolean_t enc_enhanced_set_mac_supported; 1657 boolean_t enc_init_evq_v2_supported; 1658 boolean_t enc_init_evq_extended_width_supported; 1659 boolean_t enc_no_cont_ev_mode_supported; 1660 boolean_t enc_init_rxq_with_buffer_size; 1661 boolean_t enc_rx_packed_stream_supported; 1662 boolean_t enc_rx_var_packed_stream_supported; 1663 boolean_t enc_rx_es_super_buffer_supported; 1664 boolean_t enc_fw_subvariant_no_tx_csum_supported; 1665 boolean_t enc_pm_and_rxdp_counters; 1666 boolean_t enc_mac_stats_40g_tx_size_bins; 1667 uint32_t enc_tunnel_encapsulations_supported; 1668 /* 1669 * NIC global maximum for unique UDP tunnel ports shared by all 1670 * functions. 1671 */ 1672 uint32_t enc_tunnel_config_udp_entries_max; 1673 /* External port identifier */ 1674 uint8_t enc_external_port; 1675 uint32_t enc_mcdi_max_payload_length; 1676 /* VPD may be per-PF or global */ 1677 boolean_t enc_vpd_is_global; 1678 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1679 uint32_t enc_required_pcie_bandwidth_mbps; 1680 uint32_t enc_max_pcie_link_gen; 1681 /* Firmware verifies integrity of NVRAM updates */ 1682 boolean_t enc_nvram_update_verify_result_supported; 1683 /* Firmware supports polled NVRAM updates on select partitions */ 1684 boolean_t enc_nvram_update_poll_verify_result_supported; 1685 /* Firmware accepts updates via the BUNDLE partition */ 1686 boolean_t enc_nvram_bundle_update_supported; 1687 /* Firmware support for extended MAC_STATS buffer */ 1688 uint32_t enc_mac_stats_nstats; 1689 boolean_t enc_fec_counters; 1690 boolean_t enc_hlb_counters; 1691 /* NIC support for Match-Action Engine (MAE). */ 1692 boolean_t enc_mae_supported; 1693 /* 1694 * NIC is privileged, i.e. it is the MAE admin. 1695 * Only privileged MAE clients can manage MAE flow rules, 1696 * for example, modify, count and route traffic to selected 1697 * destination (a MAE client or network port). 1698 */ 1699 boolean_t enc_mae_admin; 1700 /* NIC support for MAE action set v2 features. */ 1701 boolean_t enc_mae_aset_v2_supported; 1702 /* NIC support for MCDI Table Access API. */ 1703 boolean_t enc_table_api_supported; 1704 /* Firmware support for "FLAG" and "MARK" filter actions */ 1705 boolean_t enc_filter_action_flag_supported; 1706 boolean_t enc_filter_action_mark_supported; 1707 uint32_t enc_filter_action_mark_max; 1708 /* Port assigned to this PCI function */ 1709 uint32_t enc_assigned_port; 1710 /* NIC DMA mapping type */ 1711 efx_nic_dma_mapping_t enc_dma_mapping; 1712 /* Physical ports shared by PFs */ 1713 efx_port_usage_t enc_port_usage; 1714 } efx_nic_cfg_t; 1715 1716 #define EFX_PCI_VF_INVALID 0xffff 1717 1718 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \ 1719 ((configp)->evc_function == EFX_PCI_VF_INVALID) 1720 1721 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == EFX_PCI_VF_INVALID) 1722 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != EFX_PCI_VF_INVALID) 1723 1724 #define EFX_PCI_FUNCTION(_encp) \ 1725 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1726 1727 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1728 1729 LIBEFX_API 1730 extern const efx_nic_cfg_t * 1731 efx_nic_cfg_get( 1732 __in const efx_nic_t *enp); 1733 1734 /* RxDPCPU firmware id values by which FW variant can be identified */ 1735 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0 1736 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1 1737 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2 1738 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5 1739 #define EFX_RXDP_DPDK_FW_ID 0x6 1740 1741 typedef struct efx_nic_fw_info_s { 1742 /* Basic FW version information */ 1743 uint16_t enfi_mc_fw_version[4]; 1744 /* 1745 * If datapath capabilities can be detected, 1746 * additional FW information is to be shown 1747 */ 1748 boolean_t enfi_dpcpu_fw_ids_valid; 1749 /* Rx and Tx datapath CPU FW IDs */ 1750 uint16_t enfi_rx_dpcpu_fw_id; 1751 uint16_t enfi_tx_dpcpu_fw_id; 1752 } efx_nic_fw_info_t; 1753 1754 LIBEFX_API 1755 extern __checkReturn efx_rc_t 1756 efx_nic_get_fw_version( 1757 __in efx_nic_t *enp, 1758 __out efx_nic_fw_info_t *enfip); 1759 1760 #define EFX_NIC_BOARD_INFO_SERIAL_LEN (64) 1761 #define EFX_NIC_BOARD_INFO_NAME_LEN (16) 1762 1763 typedef struct efx_nic_board_info_s { 1764 /* The following two fields are NUL-terminated ASCII strings. */ 1765 char enbi_serial[EFX_NIC_BOARD_INFO_SERIAL_LEN]; 1766 char enbi_name[EFX_NIC_BOARD_INFO_NAME_LEN]; 1767 uint32_t enbi_revision; 1768 } efx_nic_board_info_t; 1769 1770 LIBEFX_API 1771 extern __checkReturn efx_rc_t 1772 efx_nic_get_board_info( 1773 __in efx_nic_t *enp, 1774 __out efx_nic_board_info_t *board_infop); 1775 1776 /* Driver resource limits (minimum required/maximum usable). */ 1777 typedef struct efx_drv_limits_s { 1778 uint32_t edl_min_evq_count; 1779 uint32_t edl_max_evq_count; 1780 1781 uint32_t edl_min_rxq_count; 1782 uint32_t edl_max_rxq_count; 1783 1784 uint32_t edl_min_txq_count; 1785 uint32_t edl_max_txq_count; 1786 1787 /* PIO blocks (sub-allocated from piobuf) */ 1788 uint32_t edl_min_pio_alloc_size; 1789 uint32_t edl_max_pio_alloc_count; 1790 } efx_drv_limits_t; 1791 1792 LIBEFX_API 1793 extern __checkReturn efx_rc_t 1794 efx_nic_set_drv_limits( 1795 __inout efx_nic_t *enp, 1796 __in efx_drv_limits_t *edlp); 1797 1798 /* 1799 * Register the OS driver version string for management agents 1800 * (e.g. via NC-SI). The content length is provided (i.e. no 1801 * NUL terminator). Use length 0 to indicate no version string 1802 * should be advertised. It is valid to set the version string 1803 * only before efx_nic_probe() is called. 1804 */ 1805 LIBEFX_API 1806 extern __checkReturn efx_rc_t 1807 efx_nic_set_drv_version( 1808 __inout efx_nic_t *enp, 1809 __in_ecount(length) char const *verp, 1810 __in size_t length); 1811 1812 typedef enum efx_nic_region_e { 1813 EFX_REGION_VI, /* Memory BAR UC mapping */ 1814 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1815 } efx_nic_region_t; 1816 1817 LIBEFX_API 1818 extern __checkReturn efx_rc_t 1819 efx_nic_get_bar_region( 1820 __in efx_nic_t *enp, 1821 __in efx_nic_region_t region, 1822 __out uint32_t *offsetp, 1823 __out size_t *sizep); 1824 1825 LIBEFX_API 1826 extern __checkReturn efx_rc_t 1827 efx_nic_get_vi_pool( 1828 __in efx_nic_t *enp, 1829 __out uint32_t *evq_countp, 1830 __out uint32_t *rxq_countp, 1831 __out uint32_t *txq_countp); 1832 1833 1834 #if EFSYS_OPT_VPD 1835 1836 typedef enum efx_vpd_tag_e { 1837 EFX_VPD_ID = 0x02, 1838 EFX_VPD_END = 0x0f, 1839 EFX_VPD_RO = 0x10, 1840 EFX_VPD_RW = 0x11, 1841 } efx_vpd_tag_t; 1842 1843 typedef uint16_t efx_vpd_keyword_t; 1844 1845 typedef struct efx_vpd_value_s { 1846 efx_vpd_tag_t evv_tag; 1847 efx_vpd_keyword_t evv_keyword; 1848 uint8_t evv_length; 1849 uint8_t evv_value[0x100]; 1850 } efx_vpd_value_t; 1851 1852 1853 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1854 1855 LIBEFX_API 1856 extern __checkReturn efx_rc_t 1857 efx_vpd_init( 1858 __in efx_nic_t *enp); 1859 1860 LIBEFX_API 1861 extern __checkReturn efx_rc_t 1862 efx_vpd_size( 1863 __in efx_nic_t *enp, 1864 __out size_t *sizep); 1865 1866 LIBEFX_API 1867 extern __checkReturn efx_rc_t 1868 efx_vpd_read( 1869 __in efx_nic_t *enp, 1870 __out_bcount(size) caddr_t data, 1871 __in size_t size); 1872 1873 LIBEFX_API 1874 extern __checkReturn efx_rc_t 1875 efx_vpd_verify( 1876 __in efx_nic_t *enp, 1877 __in_bcount(size) caddr_t data, 1878 __in size_t size); 1879 1880 LIBEFX_API 1881 extern __checkReturn efx_rc_t 1882 efx_vpd_reinit( 1883 __in efx_nic_t *enp, 1884 __in_bcount(size) caddr_t data, 1885 __in size_t size); 1886 1887 LIBEFX_API 1888 extern __checkReturn efx_rc_t 1889 efx_vpd_get( 1890 __in efx_nic_t *enp, 1891 __in_bcount(size) caddr_t data, 1892 __in size_t size, 1893 __inout efx_vpd_value_t *evvp); 1894 1895 LIBEFX_API 1896 extern __checkReturn efx_rc_t 1897 efx_vpd_set( 1898 __in efx_nic_t *enp, 1899 __inout_bcount(size) caddr_t data, 1900 __in size_t size, 1901 __in efx_vpd_value_t *evvp); 1902 1903 LIBEFX_API 1904 extern __checkReturn efx_rc_t 1905 efx_vpd_next( 1906 __in efx_nic_t *enp, 1907 __inout_bcount(size) caddr_t data, 1908 __in size_t size, 1909 __out efx_vpd_value_t *evvp, 1910 __inout unsigned int *contp); 1911 1912 LIBEFX_API 1913 extern __checkReturn efx_rc_t 1914 efx_vpd_write( 1915 __in efx_nic_t *enp, 1916 __in_bcount(size) caddr_t data, 1917 __in size_t size); 1918 1919 LIBEFX_API 1920 extern void 1921 efx_vpd_fini( 1922 __in efx_nic_t *enp); 1923 1924 #endif /* EFSYS_OPT_VPD */ 1925 1926 /* NVRAM */ 1927 1928 #if EFSYS_OPT_NVRAM 1929 1930 typedef enum efx_nvram_type_e { 1931 EFX_NVRAM_INVALID = 0, 1932 EFX_NVRAM_BOOTROM, 1933 EFX_NVRAM_BOOTROM_CFG, 1934 EFX_NVRAM_MC_FIRMWARE, 1935 EFX_NVRAM_MC_GOLDEN, 1936 EFX_NVRAM_PHY, 1937 EFX_NVRAM_NULLPHY, 1938 EFX_NVRAM_FPGA, 1939 EFX_NVRAM_FCFW, 1940 EFX_NVRAM_CPLD, 1941 EFX_NVRAM_FPGA_BACKUP, 1942 EFX_NVRAM_DYNAMIC_CFG, 1943 EFX_NVRAM_LICENSE, 1944 EFX_NVRAM_UEFIROM, 1945 EFX_NVRAM_MUM_FIRMWARE, 1946 EFX_NVRAM_DYNCONFIG_DEFAULTS, 1947 EFX_NVRAM_ROMCONFIG_DEFAULTS, 1948 EFX_NVRAM_BUNDLE, 1949 EFX_NVRAM_BUNDLE_METADATA, 1950 EFX_NVRAM_NTYPES, 1951 } efx_nvram_type_t; 1952 1953 typedef struct efx_nvram_info_s { 1954 uint32_t eni_flags; 1955 uint32_t eni_partn_size; 1956 uint32_t eni_address; 1957 uint32_t eni_erase_size; 1958 uint32_t eni_write_size; 1959 } efx_nvram_info_t; 1960 1961 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0) 1962 1963 LIBEFX_API 1964 extern __checkReturn efx_rc_t 1965 efx_nvram_init( 1966 __in efx_nic_t *enp); 1967 1968 #if EFSYS_OPT_DIAG 1969 1970 LIBEFX_API 1971 extern __checkReturn efx_rc_t 1972 efx_nvram_test( 1973 __in efx_nic_t *enp); 1974 1975 #endif /* EFSYS_OPT_DIAG */ 1976 1977 LIBEFX_API 1978 extern __checkReturn efx_rc_t 1979 efx_nvram_size( 1980 __in efx_nic_t *enp, 1981 __in efx_nvram_type_t type, 1982 __out size_t *sizep); 1983 1984 LIBEFX_API 1985 extern __checkReturn efx_rc_t 1986 efx_nvram_info( 1987 __in efx_nic_t *enp, 1988 __in efx_nvram_type_t type, 1989 __out efx_nvram_info_t *enip); 1990 1991 LIBEFX_API 1992 extern __checkReturn efx_rc_t 1993 efx_nvram_rw_start( 1994 __in efx_nic_t *enp, 1995 __in efx_nvram_type_t type, 1996 __out_opt size_t *pref_chunkp); 1997 1998 LIBEFX_API 1999 extern __checkReturn efx_rc_t 2000 efx_nvram_rw_finish( 2001 __in efx_nic_t *enp, 2002 __in efx_nvram_type_t type, 2003 __out_opt uint32_t *verify_resultp); 2004 2005 LIBEFX_API 2006 extern __checkReturn efx_rc_t 2007 efx_nvram_get_version( 2008 __in efx_nic_t *enp, 2009 __in efx_nvram_type_t type, 2010 __out uint32_t *subtypep, 2011 __out_ecount(4) uint16_t version[4]); 2012 2013 LIBEFX_API 2014 extern __checkReturn efx_rc_t 2015 efx_nvram_read_chunk( 2016 __in efx_nic_t *enp, 2017 __in efx_nvram_type_t type, 2018 __in unsigned int offset, 2019 __out_bcount(size) caddr_t data, 2020 __in size_t size); 2021 2022 LIBEFX_API 2023 extern __checkReturn efx_rc_t 2024 efx_nvram_read_backup( 2025 __in efx_nic_t *enp, 2026 __in efx_nvram_type_t type, 2027 __in unsigned int offset, 2028 __out_bcount(size) caddr_t data, 2029 __in size_t size); 2030 2031 LIBEFX_API 2032 extern __checkReturn efx_rc_t 2033 efx_nvram_set_version( 2034 __in efx_nic_t *enp, 2035 __in efx_nvram_type_t type, 2036 __in_ecount(4) uint16_t version[4]); 2037 2038 LIBEFX_API 2039 extern __checkReturn efx_rc_t 2040 efx_nvram_validate( 2041 __in efx_nic_t *enp, 2042 __in efx_nvram_type_t type, 2043 __in_bcount(partn_size) caddr_t partn_data, 2044 __in size_t partn_size); 2045 2046 LIBEFX_API 2047 extern __checkReturn efx_rc_t 2048 efx_nvram_erase( 2049 __in efx_nic_t *enp, 2050 __in efx_nvram_type_t type); 2051 2052 LIBEFX_API 2053 extern __checkReturn efx_rc_t 2054 efx_nvram_write_chunk( 2055 __in efx_nic_t *enp, 2056 __in efx_nvram_type_t type, 2057 __in unsigned int offset, 2058 __in_bcount(size) caddr_t data, 2059 __in size_t size); 2060 2061 LIBEFX_API 2062 extern void 2063 efx_nvram_fini( 2064 __in efx_nic_t *enp); 2065 2066 #endif /* EFSYS_OPT_NVRAM */ 2067 2068 #if EFSYS_OPT_BOOTCFG 2069 2070 /* Report size and offset of bootcfg sector in NVRAM partition. */ 2071 LIBEFX_API 2072 extern __checkReturn efx_rc_t 2073 efx_bootcfg_sector_info( 2074 __in efx_nic_t *enp, 2075 __in uint32_t pf, 2076 __out_opt uint32_t *sector_countp, 2077 __out size_t *offsetp, 2078 __out size_t *max_sizep); 2079 2080 /* 2081 * Copy bootcfg sector data to a target buffer which may differ in size. 2082 * Optionally corrects format errors in source buffer. 2083 */ 2084 LIBEFX_API 2085 extern efx_rc_t 2086 efx_bootcfg_copy_sector( 2087 __in efx_nic_t *enp, 2088 __inout_bcount(sector_length) 2089 uint8_t *sector, 2090 __in size_t sector_length, 2091 __out_bcount(data_size) uint8_t *data, 2092 __in size_t data_size, 2093 __in boolean_t handle_format_errors); 2094 2095 LIBEFX_API 2096 extern efx_rc_t 2097 efx_bootcfg_read( 2098 __in efx_nic_t *enp, 2099 __out_bcount(size) uint8_t *data, 2100 __in size_t size); 2101 2102 LIBEFX_API 2103 extern efx_rc_t 2104 efx_bootcfg_write( 2105 __in efx_nic_t *enp, 2106 __in_bcount(size) uint8_t *data, 2107 __in size_t size); 2108 2109 2110 /* 2111 * Processing routines for buffers arranged in the DHCP/BOOTP option format 2112 * (see https://tools.ietf.org/html/rfc1533) 2113 * 2114 * Summarising the format: the buffer is a sequence of options. All options 2115 * begin with a tag octet, which uniquely identifies the option. Fixed- 2116 * length options without data consist of only a tag octet. Only options PAD 2117 * (0) and END (255) are fixed length. All other options are variable-length 2118 * with a length octet following the tag octet. The value of the length 2119 * octet does not include the two octets specifying the tag and length. The 2120 * length octet is followed by "length" octets of data. 2121 * 2122 * Option data may be a sequence of sub-options in the same format. The data 2123 * content of the encapsulating option is one or more encapsulated sub-options, 2124 * with no terminating END tag is required. 2125 * 2126 * To be valid, the top-level sequence of options should be terminated by an 2127 * END tag. The buffer should be padded with the PAD byte. 2128 * 2129 * When stored to NVRAM, the DHCP option format buffer is preceded by a 2130 * checksum octet. The full buffer (including after the END tag) contributes 2131 * to the checksum, hence the need to fill the buffer to the end with PAD. 2132 */ 2133 2134 #define EFX_DHCP_END ((uint8_t)0xff) 2135 #define EFX_DHCP_PAD ((uint8_t)0) 2136 2137 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \ 2138 (uint16_t)(((encapsulator) << 8) | (encapsulated)) 2139 2140 LIBEFX_API 2141 extern __checkReturn uint8_t 2142 efx_dhcp_csum( 2143 __in_bcount(size) uint8_t const *data, 2144 __in size_t size); 2145 2146 LIBEFX_API 2147 extern __checkReturn efx_rc_t 2148 efx_dhcp_verify( 2149 __in_bcount(size) uint8_t const *data, 2150 __in size_t size, 2151 __out_opt size_t *usedp); 2152 2153 LIBEFX_API 2154 extern __checkReturn efx_rc_t 2155 efx_dhcp_find_tag( 2156 __in_bcount(buffer_length) uint8_t *bufferp, 2157 __in size_t buffer_length, 2158 __in uint16_t opt, 2159 __deref_out uint8_t **valuepp, 2160 __out size_t *value_lengthp); 2161 2162 LIBEFX_API 2163 extern __checkReturn efx_rc_t 2164 efx_dhcp_find_end( 2165 __in_bcount(buffer_length) uint8_t *bufferp, 2166 __in size_t buffer_length, 2167 __deref_out uint8_t **endpp); 2168 2169 2170 LIBEFX_API 2171 extern __checkReturn efx_rc_t 2172 efx_dhcp_delete_tag( 2173 __inout_bcount(buffer_length) uint8_t *bufferp, 2174 __in size_t buffer_length, 2175 __in uint16_t opt); 2176 2177 LIBEFX_API 2178 extern __checkReturn efx_rc_t 2179 efx_dhcp_add_tag( 2180 __inout_bcount(buffer_length) uint8_t *bufferp, 2181 __in size_t buffer_length, 2182 __in uint16_t opt, 2183 __in_bcount_opt(value_length) uint8_t *valuep, 2184 __in size_t value_length); 2185 2186 LIBEFX_API 2187 extern __checkReturn efx_rc_t 2188 efx_dhcp_update_tag( 2189 __inout_bcount(buffer_length) uint8_t *bufferp, 2190 __in size_t buffer_length, 2191 __in uint16_t opt, 2192 __in uint8_t *value_locationp, 2193 __in_bcount_opt(value_length) uint8_t *valuep, 2194 __in size_t value_length); 2195 2196 2197 #endif /* EFSYS_OPT_BOOTCFG */ 2198 2199 #if EFSYS_OPT_IMAGE_LAYOUT 2200 2201 #include "ef10_signed_image_layout.h" 2202 2203 /* 2204 * Image header used in unsigned and signed image layouts (see SF-102785-PS). 2205 * 2206 * NOTE: 2207 * The image header format is extensible. However, older drivers require an 2208 * exact match of image header version and header length when validating and 2209 * writing firmware images. 2210 * 2211 * To avoid breaking backward compatibility, we use the upper bits of the 2212 * controller version fields to contain an extra version number used for 2213 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM 2214 * version). See bug39254 and SF-102785-PS for details. 2215 */ 2216 typedef struct efx_image_header_s { 2217 uint32_t eih_magic; 2218 uint32_t eih_version; 2219 uint32_t eih_type; 2220 uint32_t eih_subtype; 2221 uint32_t eih_code_size; 2222 uint32_t eih_size; 2223 union { 2224 uint32_t eih_controller_version_min; 2225 struct { 2226 uint16_t eih_controller_version_min_short; 2227 uint8_t eih_extra_version_a; 2228 uint8_t eih_extra_version_b; 2229 }; 2230 }; 2231 union { 2232 uint32_t eih_controller_version_max; 2233 struct { 2234 uint16_t eih_controller_version_max_short; 2235 uint8_t eih_extra_version_c; 2236 uint8_t eih_extra_version_d; 2237 }; 2238 }; 2239 uint16_t eih_code_version_a; 2240 uint16_t eih_code_version_b; 2241 uint16_t eih_code_version_c; 2242 uint16_t eih_code_version_d; 2243 } efx_image_header_t; 2244 2245 #define EFX_IMAGE_HEADER_SIZE (40) 2246 #define EFX_IMAGE_HEADER_VERSION (4) 2247 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5) 2248 2249 2250 typedef struct efx_image_trailer_s { 2251 uint32_t eit_crc; 2252 } efx_image_trailer_t; 2253 2254 #define EFX_IMAGE_TRAILER_SIZE (4) 2255 2256 typedef enum efx_image_format_e { 2257 EFX_IMAGE_FORMAT_NO_IMAGE, 2258 EFX_IMAGE_FORMAT_INVALID, 2259 EFX_IMAGE_FORMAT_UNSIGNED, 2260 EFX_IMAGE_FORMAT_SIGNED, 2261 EFX_IMAGE_FORMAT_SIGNED_PACKAGE 2262 } efx_image_format_t; 2263 2264 typedef struct efx_image_info_s { 2265 efx_image_format_t eii_format; 2266 uint8_t * eii_imagep; 2267 size_t eii_image_size; 2268 efx_image_header_t * eii_headerp; 2269 } efx_image_info_t; 2270 2271 LIBEFX_API 2272 extern __checkReturn efx_rc_t 2273 efx_check_reflash_image( 2274 __in void *bufferp, 2275 __in uint32_t buffer_size, 2276 __out efx_image_info_t *infop); 2277 2278 LIBEFX_API 2279 extern __checkReturn efx_rc_t 2280 efx_build_signed_image_write_buffer( 2281 __out_bcount(buffer_size) 2282 uint8_t *bufferp, 2283 __in uint32_t buffer_size, 2284 __in efx_image_info_t *infop, 2285 __out efx_image_header_t **headerpp); 2286 2287 #endif /* EFSYS_OPT_IMAGE_LAYOUT */ 2288 2289 #if EFSYS_OPT_DIAG 2290 2291 typedef enum efx_pattern_type_t { 2292 EFX_PATTERN_BYTE_INCREMENT = 0, 2293 EFX_PATTERN_ALL_THE_SAME, 2294 EFX_PATTERN_BIT_ALTERNATE, 2295 EFX_PATTERN_BYTE_ALTERNATE, 2296 EFX_PATTERN_BYTE_CHANGING, 2297 EFX_PATTERN_BIT_SWEEP, 2298 EFX_PATTERN_NTYPES 2299 } efx_pattern_type_t; 2300 2301 typedef void 2302 (*efx_sram_pattern_fn_t)( 2303 __in size_t row, 2304 __in boolean_t negate, 2305 __out efx_qword_t *eqp); 2306 2307 LIBEFX_API 2308 extern __checkReturn efx_rc_t 2309 efx_sram_test( 2310 __in efx_nic_t *enp, 2311 __in efx_pattern_type_t type); 2312 2313 #endif /* EFSYS_OPT_DIAG */ 2314 2315 LIBEFX_API 2316 extern __checkReturn efx_rc_t 2317 efx_sram_buf_tbl_set( 2318 __in efx_nic_t *enp, 2319 __in uint32_t id, 2320 __in efsys_mem_t *esmp, 2321 __in size_t n); 2322 2323 LIBEFX_API 2324 extern void 2325 efx_sram_buf_tbl_clear( 2326 __in efx_nic_t *enp, 2327 __in uint32_t id, 2328 __in size_t n); 2329 2330 #define EFX_BUF_TBL_SIZE 0x20000 2331 2332 #define EFX_BUF_SIZE 4096 2333 2334 /* EV */ 2335 2336 typedef struct efx_evq_s efx_evq_t; 2337 2338 #if EFSYS_OPT_QSTATS 2339 2340 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */ 2341 typedef enum efx_ev_qstat_e { 2342 EV_ALL, 2343 EV_RX, 2344 EV_RX_OK, 2345 EV_RX_FRM_TRUNC, 2346 EV_RX_TOBE_DISC, 2347 EV_RX_PAUSE_FRM_ERR, 2348 EV_RX_BUF_OWNER_ID_ERR, 2349 EV_RX_IPV4_HDR_CHKSUM_ERR, 2350 EV_RX_TCP_UDP_CHKSUM_ERR, 2351 EV_RX_ETH_CRC_ERR, 2352 EV_RX_IP_FRAG_ERR, 2353 EV_RX_MCAST_PKT, 2354 EV_RX_MCAST_HASH_MATCH, 2355 EV_RX_TCP_IPV4, 2356 EV_RX_TCP_IPV6, 2357 EV_RX_UDP_IPV4, 2358 EV_RX_UDP_IPV6, 2359 EV_RX_OTHER_IPV4, 2360 EV_RX_OTHER_IPV6, 2361 EV_RX_NON_IP, 2362 EV_RX_BATCH, 2363 EV_TX, 2364 EV_TX_WQ_FF_FULL, 2365 EV_TX_PKT_ERR, 2366 EV_TX_PKT_TOO_BIG, 2367 EV_TX_UNEXPECTED, 2368 EV_GLOBAL, 2369 EV_GLOBAL_MNT, 2370 EV_DRIVER, 2371 EV_DRIVER_SRM_UPD_DONE, 2372 EV_DRIVER_TX_DESCQ_FLS_DONE, 2373 EV_DRIVER_RX_DESCQ_FLS_DONE, 2374 EV_DRIVER_RX_DESCQ_FLS_FAILED, 2375 EV_DRIVER_RX_DSC_ERROR, 2376 EV_DRIVER_TX_DSC_ERROR, 2377 EV_DRV_GEN, 2378 EV_MCDI_RESPONSE, 2379 EV_RX_PARSE_INCOMPLETE, 2380 EV_NQSTATS 2381 } efx_ev_qstat_t; 2382 2383 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 2384 2385 #endif /* EFSYS_OPT_QSTATS */ 2386 2387 LIBEFX_API 2388 extern __checkReturn efx_rc_t 2389 efx_ev_init( 2390 __in efx_nic_t *enp); 2391 2392 LIBEFX_API 2393 extern void 2394 efx_ev_fini( 2395 __in efx_nic_t *enp); 2396 2397 LIBEFX_API 2398 extern __checkReturn size_t 2399 efx_evq_size( 2400 __in const efx_nic_t *enp, 2401 __in unsigned int ndescs, 2402 __in uint32_t flags); 2403 2404 LIBEFX_API 2405 extern __checkReturn unsigned int 2406 efx_evq_nbufs( 2407 __in const efx_nic_t *enp, 2408 __in unsigned int ndescs, 2409 __in uint32_t flags); 2410 2411 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 2412 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 2413 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 2414 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 2415 2416 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 2417 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 2418 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 2419 2420 /* 2421 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more 2422 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in 2423 * NO_CONT_EV mode". 2424 * 2425 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set, 2426 * which is the case when an event queue is set to THROUGHPUT mode. 2427 */ 2428 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10) 2429 2430 /* Configure EVQ for extended width events (EF100 only) */ 2431 #define EFX_EVQ_FLAGS_EXTENDED_WIDTH (0x20) 2432 2433 2434 LIBEFX_API 2435 extern __checkReturn efx_rc_t 2436 efx_ev_qcreate( 2437 __in efx_nic_t *enp, 2438 __in unsigned int index, 2439 __in efsys_mem_t *esmp, 2440 __in size_t ndescs, 2441 __in uint32_t id, 2442 __in uint32_t us, 2443 __in uint32_t flags, 2444 __deref_out efx_evq_t **eepp); 2445 2446 LIBEFX_API 2447 extern __checkReturn efx_rc_t 2448 efx_ev_qcreate_irq( 2449 __in efx_nic_t *enp, 2450 __in unsigned int index, 2451 __in efsys_mem_t *esmp, 2452 __in size_t ndescs, 2453 __in uint32_t id, 2454 __in uint32_t us, 2455 __in uint32_t flags, 2456 __in uint32_t irq, 2457 __deref_out efx_evq_t **eepp); 2458 2459 LIBEFX_API 2460 extern void 2461 efx_ev_qpost( 2462 __in efx_evq_t *eep, 2463 __in uint16_t data); 2464 2465 typedef __checkReturn boolean_t 2466 (*efx_initialized_ev_t)( 2467 __in_opt void *arg); 2468 2469 #define EFX_PKT_UNICAST 0x0004 2470 #define EFX_PKT_START 0x0008 2471 2472 #define EFX_PKT_VLAN_TAGGED 0x0010 2473 #define EFX_CKSUM_TCPUDP 0x0020 2474 #define EFX_CKSUM_IPV4 0x0040 2475 #define EFX_PKT_CONT 0x0080 2476 2477 #define EFX_CHECK_VLAN 0x0100 2478 #define EFX_PKT_TCP 0x0200 2479 #define EFX_PKT_UDP 0x0400 2480 #define EFX_PKT_IPV4 0x0800 2481 2482 #define EFX_PKT_IPV6 0x1000 2483 #define EFX_PKT_PREFIX_LEN 0x2000 2484 #define EFX_ADDR_MISMATCH 0x4000 2485 #define EFX_DISCARD 0x8000 2486 2487 /* 2488 * The following flags are used only for packed stream 2489 * mode. The values for the flags are reused to fit into 16 bit, 2490 * since EFX_PKT_START and EFX_PKT_CONT are never used in 2491 * packed stream mode 2492 */ 2493 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START 2494 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT 2495 2496 2497 #define EFX_EV_RX_NLABELS 32 2498 #define EFX_EV_TX_NLABELS 32 2499 2500 typedef __checkReturn boolean_t 2501 (*efx_rx_ev_t)( 2502 __in_opt void *arg, 2503 __in uint32_t label, 2504 __in uint32_t id, 2505 __in uint32_t size, 2506 __in uint16_t flags); 2507 2508 typedef __checkReturn boolean_t 2509 (*efx_rx_packets_ev_t)( 2510 __in_opt void *arg, 2511 __in uint32_t label, 2512 __in unsigned int num_packets, 2513 __in uint32_t flags); 2514 2515 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2516 2517 /* 2518 * Packed stream mode is documented in SF-112241-TC. 2519 * The general idea is that, instead of putting each incoming 2520 * packet into a separate buffer which is specified in a RX 2521 * descriptor, a large buffer is provided to the hardware and 2522 * packets are put there in a continuous stream. 2523 * The main advantage of such an approach is that RX queue refilling 2524 * happens much less frequently. 2525 * 2526 * Equal stride packed stream mode is documented in SF-119419-TC. 2527 * The general idea is to utilize advantages of the packed stream, 2528 * but avoid indirection in packets representation. 2529 * The main advantage of such an approach is that RX queue refilling 2530 * happens much less frequently and packets buffers are independent 2531 * from upper layers point of view. 2532 */ 2533 2534 typedef __checkReturn boolean_t 2535 (*efx_rx_ps_ev_t)( 2536 __in_opt void *arg, 2537 __in uint32_t label, 2538 __in uint32_t id, 2539 __in uint32_t pkt_count, 2540 __in uint16_t flags); 2541 2542 #endif 2543 2544 typedef __checkReturn boolean_t 2545 (*efx_tx_ev_t)( 2546 __in_opt void *arg, 2547 __in uint32_t label, 2548 __in uint32_t id); 2549 2550 typedef __checkReturn boolean_t 2551 (*efx_tx_ndescs_ev_t)( 2552 __in_opt void *arg, 2553 __in uint32_t label, 2554 __in unsigned int ndescs); 2555 2556 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 2557 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 2558 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 2559 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 2560 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 2561 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 2562 #define EFX_EXCEPTION_RX_ERROR 0x00000007 2563 #define EFX_EXCEPTION_TX_ERROR 0x00000008 2564 #define EFX_EXCEPTION_EV_ERROR 0x00000009 2565 2566 typedef __checkReturn boolean_t 2567 (*efx_exception_ev_t)( 2568 __in_opt void *arg, 2569 __in uint32_t label, 2570 __in uint32_t data); 2571 2572 typedef __checkReturn boolean_t 2573 (*efx_rxq_flush_done_ev_t)( 2574 __in_opt void *arg, 2575 __in uint32_t rxq_index); 2576 2577 typedef __checkReturn boolean_t 2578 (*efx_rxq_flush_failed_ev_t)( 2579 __in_opt void *arg, 2580 __in uint32_t rxq_index); 2581 2582 typedef __checkReturn boolean_t 2583 (*efx_txq_flush_done_ev_t)( 2584 __in_opt void *arg, 2585 __in uint32_t txq_index); 2586 2587 typedef __checkReturn boolean_t 2588 (*efx_software_ev_t)( 2589 __in_opt void *arg, 2590 __in uint16_t magic); 2591 2592 typedef __checkReturn boolean_t 2593 (*efx_sram_ev_t)( 2594 __in_opt void *arg, 2595 __in uint32_t code); 2596 2597 #define EFX_SRAM_CLEAR 0 2598 #define EFX_SRAM_UPDATE 1 2599 #define EFX_SRAM_ILLEGAL_CLEAR 2 2600 2601 typedef __checkReturn boolean_t 2602 (*efx_wake_up_ev_t)( 2603 __in_opt void *arg, 2604 __in uint32_t label); 2605 2606 typedef __checkReturn boolean_t 2607 (*efx_timer_ev_t)( 2608 __in_opt void *arg, 2609 __in uint32_t label); 2610 2611 typedef __checkReturn boolean_t 2612 (*efx_link_change_ev_t)( 2613 __in_opt void *arg, 2614 __in efx_link_mode_t link_mode); 2615 2616 #if EFSYS_OPT_MON_STATS 2617 2618 typedef __checkReturn boolean_t 2619 (*efx_monitor_ev_t)( 2620 __in_opt void *arg, 2621 __in efx_mon_stat_t id, 2622 __in efx_mon_stat_value_t value); 2623 2624 #endif /* EFSYS_OPT_MON_STATS */ 2625 2626 #if EFSYS_OPT_MAC_STATS 2627 2628 typedef __checkReturn boolean_t 2629 (*efx_mac_stats_ev_t)( 2630 __in_opt void *arg, 2631 __in uint32_t generation); 2632 2633 #endif /* EFSYS_OPT_MAC_STATS */ 2634 2635 #if EFSYS_OPT_DESC_PROXY 2636 2637 /* 2638 * NOTE: This callback returns the raw descriptor data, which has not been 2639 * converted to host endian. The callback must use the EFX_OWORD macros 2640 * to extract the descriptor fields as host endian values. 2641 */ 2642 typedef __checkReturn boolean_t 2643 (*efx_desc_proxy_txq_desc_ev_t)( 2644 __in_opt void *arg, 2645 __in uint16_t vi_id, 2646 __in efx_oword_t txq_desc); 2647 2648 /* 2649 * NOTE: This callback returns the raw descriptor data, which has not been 2650 * converted to host endian. The callback must use the EFX_OWORD macros 2651 * to extract the descriptor fields as host endian values. 2652 */ 2653 typedef __checkReturn boolean_t 2654 (*efx_desc_proxy_virtq_desc_ev_t)( 2655 __in_opt void *arg, 2656 __in uint16_t vi_id, 2657 __in uint16_t avail, 2658 __in efx_oword_t virtq_desc); 2659 2660 #endif /* EFSYS_OPT_DESC_PROXY */ 2661 2662 typedef struct efx_ev_callbacks_s { 2663 efx_initialized_ev_t eec_initialized; 2664 efx_rx_ev_t eec_rx; 2665 efx_rx_packets_ev_t eec_rx_packets; 2666 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2667 efx_rx_ps_ev_t eec_rx_ps; 2668 #endif 2669 efx_tx_ev_t eec_tx; 2670 efx_tx_ndescs_ev_t eec_tx_ndescs; 2671 efx_exception_ev_t eec_exception; 2672 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 2673 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 2674 efx_txq_flush_done_ev_t eec_txq_flush_done; 2675 efx_software_ev_t eec_software; 2676 efx_sram_ev_t eec_sram; 2677 efx_wake_up_ev_t eec_wake_up; 2678 efx_timer_ev_t eec_timer; 2679 efx_link_change_ev_t eec_link_change; 2680 #if EFSYS_OPT_MON_STATS 2681 efx_monitor_ev_t eec_monitor; 2682 #endif /* EFSYS_OPT_MON_STATS */ 2683 #if EFSYS_OPT_MAC_STATS 2684 efx_mac_stats_ev_t eec_mac_stats; 2685 #endif /* EFSYS_OPT_MAC_STATS */ 2686 #if EFSYS_OPT_DESC_PROXY 2687 efx_desc_proxy_txq_desc_ev_t eec_desc_proxy_txq_desc; 2688 efx_desc_proxy_virtq_desc_ev_t eec_desc_proxy_virtq_desc; 2689 #endif /* EFSYS_OPT_DESC_PROXY */ 2690 2691 } efx_ev_callbacks_t; 2692 2693 LIBEFX_API 2694 extern __checkReturn boolean_t 2695 efx_ev_qpending( 2696 __in efx_evq_t *eep, 2697 __in unsigned int count); 2698 2699 #if EFSYS_OPT_EV_PREFETCH 2700 2701 LIBEFX_API 2702 extern void 2703 efx_ev_qprefetch( 2704 __in efx_evq_t *eep, 2705 __in unsigned int count); 2706 2707 #endif /* EFSYS_OPT_EV_PREFETCH */ 2708 2709 LIBEFX_API 2710 extern void 2711 efx_ev_qcreate_check_init_done( 2712 __in efx_evq_t *eep, 2713 __in const efx_ev_callbacks_t *eecp, 2714 __in_opt void *arg); 2715 2716 LIBEFX_API 2717 extern void 2718 efx_ev_qpoll( 2719 __in efx_evq_t *eep, 2720 __inout unsigned int *countp, 2721 __in const efx_ev_callbacks_t *eecp, 2722 __in_opt void *arg); 2723 2724 LIBEFX_API 2725 extern __checkReturn efx_rc_t 2726 efx_ev_usecs_to_ticks( 2727 __in efx_nic_t *enp, 2728 __in unsigned int usecs, 2729 __out unsigned int *ticksp); 2730 2731 LIBEFX_API 2732 extern __checkReturn efx_rc_t 2733 efx_ev_qmoderate( 2734 __in efx_evq_t *eep, 2735 __in unsigned int us); 2736 2737 LIBEFX_API 2738 extern __checkReturn efx_rc_t 2739 efx_ev_qprime( 2740 __in efx_evq_t *eep, 2741 __in unsigned int count); 2742 2743 #if EFSYS_OPT_QSTATS 2744 2745 #if EFSYS_OPT_NAMES 2746 2747 LIBEFX_API 2748 extern const char * 2749 efx_ev_qstat_name( 2750 __in efx_nic_t *enp, 2751 __in unsigned int id); 2752 2753 #endif /* EFSYS_OPT_NAMES */ 2754 2755 LIBEFX_API 2756 extern void 2757 efx_ev_qstats_update( 2758 __in efx_evq_t *eep, 2759 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 2760 2761 #endif /* EFSYS_OPT_QSTATS */ 2762 2763 LIBEFX_API 2764 extern void 2765 efx_ev_qdestroy( 2766 __in efx_evq_t *eep); 2767 2768 /* RX */ 2769 2770 LIBEFX_API 2771 extern __checkReturn efx_rc_t 2772 efx_rx_init( 2773 __inout efx_nic_t *enp); 2774 2775 LIBEFX_API 2776 extern void 2777 efx_rx_fini( 2778 __in efx_nic_t *enp); 2779 2780 #if EFSYS_OPT_RX_SCATTER 2781 LIBEFX_API 2782 extern __checkReturn efx_rc_t 2783 efx_rx_scatter_enable( 2784 __in efx_nic_t *enp, 2785 __in unsigned int buf_size); 2786 #endif /* EFSYS_OPT_RX_SCATTER */ 2787 2788 /* Handle to represent use of the default RSS context. */ 2789 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff 2790 2791 #if EFSYS_OPT_RX_SCALE 2792 2793 typedef enum efx_rx_hash_alg_e { 2794 EFX_RX_HASHALG_LFSR = 0, 2795 EFX_RX_HASHALG_TOEPLITZ, 2796 EFX_RX_HASHALG_PACKED_STREAM, 2797 EFX_RX_NHASHALGS 2798 } efx_rx_hash_alg_t; 2799 2800 /* 2801 * Legacy hash type flags. 2802 * 2803 * They represent standard tuples for distinct traffic classes. 2804 */ 2805 #define EFX_RX_HASH_IPV4 (1U << 0) 2806 #define EFX_RX_HASH_TCPIPV4 (1U << 1) 2807 #define EFX_RX_HASH_IPV6 (1U << 2) 2808 #define EFX_RX_HASH_TCPIPV6 (1U << 3) 2809 2810 #define EFX_RX_HASH_LEGACY_MASK \ 2811 (EFX_RX_HASH_IPV4 | \ 2812 EFX_RX_HASH_TCPIPV4 | \ 2813 EFX_RX_HASH_IPV6 | \ 2814 EFX_RX_HASH_TCPIPV6) 2815 2816 /* 2817 * The type of the argument used by efx_rx_scale_mode_set() to 2818 * provide a means for the client drivers to configure hashing. 2819 * 2820 * A properly constructed value can either be: 2821 * - a combination of legacy flags 2822 * - a combination of EFX_RX_HASH() flags 2823 */ 2824 typedef uint32_t efx_rx_hash_type_t; 2825 2826 typedef enum efx_rx_hash_support_e { 2827 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 2828 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 2829 } efx_rx_hash_support_t; 2830 2831 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */ 2832 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 2833 #define EFX_MAXRSS 64 /* RX indirection entry range */ 2834 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 2835 2836 typedef enum efx_rx_scale_context_type_e { 2837 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */ 2838 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 2839 EFX_RX_SCALE_SHARED, /* Read-only key/indirection table */ 2840 EFX_RX_SCALE_EVEN_SPREAD, /* No indirection table, writable key */ 2841 } efx_rx_scale_context_type_t; 2842 2843 /* 2844 * Traffic classes eligible for hash computation. 2845 * 2846 * Select packet headers used in computing the receive hash. 2847 * This uses the same encoding as the RSS_MODES field of 2848 * MC_CMD_RSS_CONTEXT_SET_FLAGS. 2849 */ 2850 #define EFX_RX_CLASS_IPV4_TCP_LBN 8 2851 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4 2852 #define EFX_RX_CLASS_IPV4_UDP_LBN 12 2853 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4 2854 #define EFX_RX_CLASS_IPV4_LBN 16 2855 #define EFX_RX_CLASS_IPV4_WIDTH 4 2856 #define EFX_RX_CLASS_IPV6_TCP_LBN 20 2857 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4 2858 #define EFX_RX_CLASS_IPV6_UDP_LBN 24 2859 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4 2860 #define EFX_RX_CLASS_IPV6_LBN 28 2861 #define EFX_RX_CLASS_IPV6_WIDTH 4 2862 2863 #define EFX_RX_NCLASSES 6 2864 2865 /* 2866 * Ancillary flags used to construct generic hash tuples. 2867 * This uses the same encoding as RSS_MODE_HASH_SELECTOR. 2868 */ 2869 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0) 2870 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1) 2871 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2) 2872 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3) 2873 2874 /* 2875 * Generic hash tuples. 2876 * 2877 * They express combinations of packet fields 2878 * which can contribute to the hash value for 2879 * a particular traffic class. 2880 */ 2881 #define EFX_RX_CLASS_HASH_DISABLE 0 2882 2883 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR 2884 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR 2885 2886 #define EFX_RX_CLASS_HASH_2TUPLE \ 2887 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2888 EFX_RX_CLASS_HASH_DST_ADDR) 2889 2890 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \ 2891 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2892 EFX_RX_CLASS_HASH_SRC_PORT) 2893 2894 #define EFX_RX_CLASS_HASH_2TUPLE_DST \ 2895 (EFX_RX_CLASS_HASH_DST_ADDR | \ 2896 EFX_RX_CLASS_HASH_DST_PORT) 2897 2898 #define EFX_RX_CLASS_HASH_4TUPLE \ 2899 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2900 EFX_RX_CLASS_HASH_DST_ADDR | \ 2901 EFX_RX_CLASS_HASH_SRC_PORT | \ 2902 EFX_RX_CLASS_HASH_DST_PORT) 2903 2904 #define EFX_RX_CLASS_HASH_NTUPLES 7 2905 2906 /* 2907 * Hash flag constructor. 2908 * 2909 * Resulting flags encode hash tuples for specific traffic classes. 2910 * The client drivers are encouraged to use these flags to form 2911 * a hash type value. 2912 */ 2913 #define EFX_RX_HASH(_class, _tuple) \ 2914 EFX_INSERT_FIELD_NATIVE32(0, 31, \ 2915 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple) 2916 2917 /* 2918 * The maximum number of EFX_RX_HASH() flags. 2919 */ 2920 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES) 2921 2922 LIBEFX_API 2923 extern __checkReturn efx_rc_t 2924 efx_rx_scale_hash_flags_get( 2925 __in efx_nic_t *enp, 2926 __in efx_rx_hash_alg_t hash_alg, 2927 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp, 2928 __in unsigned int max_nflags, 2929 __out unsigned int *nflagsp); 2930 2931 LIBEFX_API 2932 extern __checkReturn efx_rc_t 2933 efx_rx_hash_default_support_get( 2934 __in efx_nic_t *enp, 2935 __out efx_rx_hash_support_t *supportp); 2936 2937 2938 LIBEFX_API 2939 extern __checkReturn efx_rc_t 2940 efx_rx_scale_default_support_get( 2941 __in efx_nic_t *enp, 2942 __out efx_rx_scale_context_type_t *typep); 2943 2944 LIBEFX_API 2945 extern __checkReturn efx_rc_t 2946 efx_rx_scale_context_alloc( 2947 __in efx_nic_t *enp, 2948 __in efx_rx_scale_context_type_t type, 2949 __in uint32_t num_queues, 2950 __out uint32_t *rss_contextp); 2951 2952 LIBEFX_API 2953 extern __checkReturn efx_rc_t 2954 efx_rx_scale_context_alloc_v2( 2955 __in efx_nic_t *enp, 2956 __in efx_rx_scale_context_type_t type, 2957 __in uint32_t num_queues, 2958 __in uint32_t table_nentries, 2959 __out uint32_t *rss_contextp); 2960 2961 LIBEFX_API 2962 extern __checkReturn efx_rc_t 2963 efx_rx_scale_context_free( 2964 __in efx_nic_t *enp, 2965 __in uint32_t rss_context); 2966 2967 LIBEFX_API 2968 extern __checkReturn efx_rc_t 2969 efx_rx_scale_mode_set( 2970 __in efx_nic_t *enp, 2971 __in uint32_t rss_context, 2972 __in efx_rx_hash_alg_t alg, 2973 __in efx_rx_hash_type_t type, 2974 __in boolean_t insert); 2975 2976 LIBEFX_API 2977 extern __checkReturn efx_rc_t 2978 efx_rx_scale_tbl_set( 2979 __in efx_nic_t *enp, 2980 __in uint32_t rss_context, 2981 __in_ecount(nentries) unsigned int *table, 2982 __in size_t nentries); 2983 2984 LIBEFX_API 2985 extern __checkReturn efx_rc_t 2986 efx_rx_scale_key_set( 2987 __in efx_nic_t *enp, 2988 __in uint32_t rss_context, 2989 __in_ecount(n) uint8_t *key, 2990 __in size_t n); 2991 2992 LIBEFX_API 2993 extern __checkReturn uint32_t 2994 efx_pseudo_hdr_hash_get( 2995 __in efx_rxq_t *erp, 2996 __in efx_rx_hash_alg_t func, 2997 __in uint8_t *buffer); 2998 2999 #endif /* EFSYS_OPT_RX_SCALE */ 3000 3001 LIBEFX_API 3002 extern __checkReturn efx_rc_t 3003 efx_pseudo_hdr_pkt_length_get( 3004 __in efx_rxq_t *erp, 3005 __in uint8_t *buffer, 3006 __out uint16_t *pkt_lengthp); 3007 3008 LIBEFX_API 3009 extern __checkReturn size_t 3010 efx_rxq_size( 3011 __in const efx_nic_t *enp, 3012 __in unsigned int ndescs); 3013 3014 LIBEFX_API 3015 extern __checkReturn unsigned int 3016 efx_rxq_nbufs( 3017 __in const efx_nic_t *enp, 3018 __in unsigned int ndescs); 3019 3020 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 3021 3022 /* 3023 * libefx representation of the Rx prefix layout information. 3024 * 3025 * The information may be used inside libefx to implement Rx prefix fields 3026 * accessors and by drivers which process Rx prefix itself. 3027 */ 3028 3029 /* 3030 * All known Rx prefix fields. 3031 * 3032 * An Rx prefix may have a subset of these fields. 3033 */ 3034 typedef enum efx_rx_prefix_field_e { 3035 EFX_RX_PREFIX_FIELD_LENGTH = 0, 3036 EFX_RX_PREFIX_FIELD_ORIG_LENGTH, 3037 EFX_RX_PREFIX_FIELD_CLASS, 3038 EFX_RX_PREFIX_FIELD_RSS_HASH, 3039 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID, 3040 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP, 3041 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI, 3042 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI, 3043 EFX_RX_PREFIX_FIELD_USER_FLAG, 3044 EFX_RX_PREFIX_FIELD_USER_MARK, 3045 EFX_RX_PREFIX_FIELD_USER_MARK_VALID, 3046 EFX_RX_PREFIX_FIELD_CSUM_FRAME, 3047 EFX_RX_PREFIX_FIELD_INGRESS_VPORT, 3048 EFX_RX_PREFIX_FIELD_INGRESS_MPORT = EFX_RX_PREFIX_FIELD_INGRESS_VPORT, 3049 EFX_RX_PREFIX_NFIELDS 3050 } efx_rx_prefix_field_t; 3051 3052 /* 3053 * Location and endianness of a field in Rx prefix. 3054 * 3055 * If width is zero, the field is not present. 3056 */ 3057 typedef struct efx_rx_prefix_field_info_s { 3058 uint16_t erpfi_offset_bits; 3059 uint8_t erpfi_width_bits; 3060 boolean_t erpfi_big_endian; 3061 } efx_rx_prefix_field_info_t; 3062 3063 /* Helper macro to define Rx prefix fields */ 3064 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \ 3065 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \ 3066 .erpfi_offset_bits = EFX_LOW_BIT(_field), \ 3067 .erpfi_width_bits = EFX_WIDTH(_field), \ 3068 .erpfi_big_endian = (_big_endian), \ 3069 } 3070 3071 typedef struct efx_rx_prefix_layout_s { 3072 uint32_t erpl_id; 3073 uint8_t erpl_length; 3074 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS]; 3075 } efx_rx_prefix_layout_t; 3076 3077 /* 3078 * Helper function to find out a bit mask of wanted but not available 3079 * Rx prefix fields. 3080 * 3081 * A field is considered as not available if any parameter mismatch. 3082 */ 3083 LIBEFX_API 3084 extern __checkReturn uint32_t 3085 efx_rx_prefix_layout_check( 3086 __in const efx_rx_prefix_layout_t *available, 3087 __in const efx_rx_prefix_layout_t *wanted); 3088 3089 LIBEFX_API 3090 extern __checkReturn efx_rc_t 3091 efx_rx_prefix_get_layout( 3092 __in const efx_rxq_t *erp, 3093 __out efx_rx_prefix_layout_t *erplp); 3094 3095 typedef enum efx_rxq_type_e { 3096 EFX_RXQ_TYPE_DEFAULT, 3097 EFX_RXQ_TYPE_PACKED_STREAM, 3098 EFX_RXQ_TYPE_ES_SUPER_BUFFER, 3099 EFX_RXQ_NTYPES 3100 } efx_rxq_type_t; 3101 3102 /* 3103 * Dummy flag to be used instead of 0 to make it clear that the argument 3104 * is receive queue flags. 3105 */ 3106 #define EFX_RXQ_FLAG_NONE 0x0 3107 #define EFX_RXQ_FLAG_SCATTER 0x1 3108 /* 3109 * If tunnels are supported and Rx event can provide information about 3110 * either outer or inner packet classes (e.g. SFN8xxx adapters with 3111 * full-feature firmware variant running), outer classes are requested by 3112 * default. However, if the driver supports tunnels, the flag allows to 3113 * request inner classes which are required to be able to interpret inner 3114 * Rx checksum offload results. 3115 */ 3116 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2 3117 /* 3118 * Request delivery of the RSS hash calculated by HW to be used by 3119 * the driver. 3120 */ 3121 #define EFX_RXQ_FLAG_RSS_HASH 0x4 3122 /* 3123 * Request ingress mport field in the Rx prefix of a queue. 3124 */ 3125 #define EFX_RXQ_FLAG_INGRESS_MPORT 0x8 3126 /* 3127 * Request user mark field in the Rx prefix of a queue. 3128 */ 3129 #define EFX_RXQ_FLAG_USER_MARK 0x10 3130 /* 3131 * Request user flag field in the Rx prefix of a queue. 3132 */ 3133 #define EFX_RXQ_FLAG_USER_FLAG 0x20 3134 /* 3135 * Request VLAN TCI field in the Rx prefix. The flag just 3136 * controls delivery of the stripped VLAN TCI if VLAN stripping 3137 * is enabled and done. 3138 */ 3139 #define EFX_RXQ_FLAG_VLAN_STRIPPED_TCI 0x40 3140 3141 LIBEFX_API 3142 extern __checkReturn efx_rc_t 3143 efx_rx_qcreate( 3144 __in efx_nic_t *enp, 3145 __in unsigned int index, 3146 __in unsigned int label, 3147 __in efx_rxq_type_t type, 3148 __in size_t buf_size, 3149 __in efsys_mem_t *esmp, 3150 __in size_t ndescs, 3151 __in uint32_t id, 3152 __in unsigned int flags, 3153 __in efx_evq_t *eep, 3154 __deref_out efx_rxq_t **erpp); 3155 3156 #if EFSYS_OPT_RX_PACKED_STREAM 3157 3158 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024) 3159 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024) 3160 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024) 3161 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024) 3162 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024) 3163 3164 LIBEFX_API 3165 extern __checkReturn efx_rc_t 3166 efx_rx_qcreate_packed_stream( 3167 __in efx_nic_t *enp, 3168 __in unsigned int index, 3169 __in unsigned int label, 3170 __in uint32_t ps_buf_size, 3171 __in efsys_mem_t *esmp, 3172 __in size_t ndescs, 3173 __in efx_evq_t *eep, 3174 __deref_out efx_rxq_t **erpp); 3175 3176 #endif 3177 3178 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 3179 3180 /* Maximum head-of-line block timeout in nanoseconds */ 3181 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000) 3182 3183 LIBEFX_API 3184 extern __checkReturn efx_rc_t 3185 efx_rx_qcreate_es_super_buffer( 3186 __in efx_nic_t *enp, 3187 __in unsigned int index, 3188 __in unsigned int label, 3189 __in uint32_t n_bufs_per_desc, 3190 __in uint32_t max_dma_len, 3191 __in uint32_t buf_stride, 3192 __in uint32_t hol_block_timeout, 3193 __in efsys_mem_t *esmp, 3194 __in size_t ndescs, 3195 __in unsigned int flags, 3196 __in efx_evq_t *eep, 3197 __deref_out efx_rxq_t **erpp); 3198 3199 #endif 3200 3201 typedef struct efx_buffer_s { 3202 efsys_dma_addr_t eb_addr; 3203 size_t eb_size; 3204 boolean_t eb_eop; 3205 } efx_buffer_t; 3206 3207 typedef struct efx_desc_s { 3208 efx_qword_t ed_eq; 3209 } efx_desc_t; 3210 3211 LIBEFX_API 3212 extern void 3213 efx_rx_qpost( 3214 __in efx_rxq_t *erp, 3215 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 3216 __in size_t size, 3217 __in unsigned int ndescs, 3218 __in unsigned int completed, 3219 __in unsigned int added); 3220 3221 LIBEFX_API 3222 extern void 3223 efx_rx_qpush( 3224 __in efx_rxq_t *erp, 3225 __in unsigned int added, 3226 __inout unsigned int *pushedp); 3227 3228 #if EFSYS_OPT_RX_PACKED_STREAM 3229 3230 LIBEFX_API 3231 extern void 3232 efx_rx_qpush_ps_credits( 3233 __in efx_rxq_t *erp); 3234 3235 LIBEFX_API 3236 extern __checkReturn uint8_t * 3237 efx_rx_qps_packet_info( 3238 __in efx_rxq_t *erp, 3239 __in uint8_t *buffer, 3240 __in uint32_t buffer_length, 3241 __in uint32_t current_offset, 3242 __out uint16_t *lengthp, 3243 __out uint32_t *next_offsetp, 3244 __out uint32_t *timestamp); 3245 #endif 3246 3247 LIBEFX_API 3248 extern __checkReturn efx_rc_t 3249 efx_rx_qflush( 3250 __in efx_rxq_t *erp); 3251 3252 LIBEFX_API 3253 extern void 3254 efx_rx_qenable( 3255 __in efx_rxq_t *erp); 3256 3257 LIBEFX_API 3258 extern void 3259 efx_rx_qdestroy( 3260 __in efx_rxq_t *erp); 3261 3262 /* TX */ 3263 3264 typedef struct efx_txq_s efx_txq_t; 3265 3266 #if EFSYS_OPT_QSTATS 3267 3268 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 3269 typedef enum efx_tx_qstat_e { 3270 TX_POST, 3271 TX_POST_PIO, 3272 TX_NQSTATS 3273 } efx_tx_qstat_t; 3274 3275 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 3276 3277 #endif /* EFSYS_OPT_QSTATS */ 3278 3279 LIBEFX_API 3280 extern __checkReturn efx_rc_t 3281 efx_tx_init( 3282 __in efx_nic_t *enp); 3283 3284 LIBEFX_API 3285 extern void 3286 efx_tx_fini( 3287 __in efx_nic_t *enp); 3288 3289 LIBEFX_API 3290 extern __checkReturn size_t 3291 efx_txq_size( 3292 __in const efx_nic_t *enp, 3293 __in unsigned int ndescs); 3294 3295 LIBEFX_API 3296 extern __checkReturn unsigned int 3297 efx_txq_nbufs( 3298 __in const efx_nic_t *enp, 3299 __in unsigned int ndescs); 3300 3301 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 3302 3303 #define EFX_TXQ_CKSUM_IPV4 0x0001 3304 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 3305 #define EFX_TXQ_FATSOV2 0x0004 3306 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008 3307 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010 3308 3309 LIBEFX_API 3310 extern __checkReturn efx_rc_t 3311 efx_tx_qcreate( 3312 __in efx_nic_t *enp, 3313 __in unsigned int index, 3314 __in unsigned int label, 3315 __in efsys_mem_t *esmp, 3316 __in size_t n, 3317 __in uint32_t id, 3318 __in uint16_t flags, 3319 __in efx_evq_t *eep, 3320 __deref_out efx_txq_t **etpp, 3321 __out unsigned int *addedp); 3322 3323 LIBEFX_API 3324 extern __checkReturn efx_rc_t 3325 efx_tx_qpost( 3326 __in efx_txq_t *etp, 3327 __in_ecount(ndescs) efx_buffer_t *eb, 3328 __in unsigned int ndescs, 3329 __in unsigned int completed, 3330 __inout unsigned int *addedp); 3331 3332 LIBEFX_API 3333 extern __checkReturn efx_rc_t 3334 efx_tx_qpace( 3335 __in efx_txq_t *etp, 3336 __in unsigned int ns); 3337 3338 LIBEFX_API 3339 extern void 3340 efx_tx_qpush( 3341 __in efx_txq_t *etp, 3342 __in unsigned int added, 3343 __in unsigned int pushed); 3344 3345 LIBEFX_API 3346 extern __checkReturn efx_rc_t 3347 efx_tx_qflush( 3348 __in efx_txq_t *etp); 3349 3350 LIBEFX_API 3351 extern void 3352 efx_tx_qenable( 3353 __in efx_txq_t *etp); 3354 3355 LIBEFX_API 3356 extern __checkReturn efx_rc_t 3357 efx_tx_qpio_enable( 3358 __in efx_txq_t *etp); 3359 3360 LIBEFX_API 3361 extern void 3362 efx_tx_qpio_disable( 3363 __in efx_txq_t *etp); 3364 3365 LIBEFX_API 3366 extern __checkReturn efx_rc_t 3367 efx_tx_qpio_write( 3368 __in efx_txq_t *etp, 3369 __in_ecount(buf_length) uint8_t *buffer, 3370 __in size_t buf_length, 3371 __in size_t pio_buf_offset); 3372 3373 LIBEFX_API 3374 extern __checkReturn efx_rc_t 3375 efx_tx_qpio_post( 3376 __in efx_txq_t *etp, 3377 __in size_t pkt_length, 3378 __in unsigned int completed, 3379 __inout unsigned int *addedp); 3380 3381 LIBEFX_API 3382 extern __checkReturn efx_rc_t 3383 efx_tx_qdesc_post( 3384 __in efx_txq_t *etp, 3385 __in_ecount(n) efx_desc_t *ed, 3386 __in unsigned int n, 3387 __in unsigned int completed, 3388 __inout unsigned int *addedp); 3389 3390 LIBEFX_API 3391 extern void 3392 efx_tx_qdesc_dma_create( 3393 __in efx_txq_t *etp, 3394 __in efsys_dma_addr_t addr, 3395 __in size_t size, 3396 __in boolean_t eop, 3397 __out efx_desc_t *edp); 3398 3399 LIBEFX_API 3400 extern void 3401 efx_tx_qdesc_tso_create( 3402 __in efx_txq_t *etp, 3403 __in uint16_t ipv4_id, 3404 __in uint32_t tcp_seq, 3405 __in uint8_t tcp_flags, 3406 __out efx_desc_t *edp); 3407 3408 /* Number of FATSOv2 option descriptors */ 3409 #define EFX_TX_FATSOV2_OPT_NDESCS 2 3410 3411 /* Maximum number of DMA segments per TSO packet (not superframe) */ 3412 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 3413 3414 LIBEFX_API 3415 extern void 3416 efx_tx_qdesc_tso2_create( 3417 __in efx_txq_t *etp, 3418 __in uint16_t ipv4_id, 3419 __in uint16_t outer_ipv4_id, 3420 __in uint32_t tcp_seq, 3421 __in uint16_t tcp_mss, 3422 __out_ecount(count) efx_desc_t *edp, 3423 __in int count); 3424 3425 LIBEFX_API 3426 extern void 3427 efx_tx_qdesc_vlantci_create( 3428 __in efx_txq_t *etp, 3429 __in uint16_t tci, 3430 __out efx_desc_t *edp); 3431 3432 LIBEFX_API 3433 extern void 3434 efx_tx_qdesc_checksum_create( 3435 __in efx_txq_t *etp, 3436 __in uint16_t flags, 3437 __out efx_desc_t *edp); 3438 3439 #if EFSYS_OPT_QSTATS 3440 3441 #if EFSYS_OPT_NAMES 3442 3443 LIBEFX_API 3444 extern const char * 3445 efx_tx_qstat_name( 3446 __in efx_nic_t *etp, 3447 __in unsigned int id); 3448 3449 #endif /* EFSYS_OPT_NAMES */ 3450 3451 LIBEFX_API 3452 extern void 3453 efx_tx_qstats_update( 3454 __in efx_txq_t *etp, 3455 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 3456 3457 #endif /* EFSYS_OPT_QSTATS */ 3458 3459 LIBEFX_API 3460 extern void 3461 efx_tx_qdestroy( 3462 __in efx_txq_t *etp); 3463 3464 3465 /* FILTER */ 3466 3467 #if EFSYS_OPT_FILTER 3468 3469 #define EFX_ETHER_TYPE_IPV4 0x0800 3470 #define EFX_ETHER_TYPE_IPV6 0x86DD 3471 3472 #define EFX_IPPROTO_TCP 6 3473 #define EFX_IPPROTO_UDP 17 3474 #define EFX_IPPROTO_GRE 47 3475 3476 /* Use RSS to spread across multiple queues */ 3477 #define EFX_FILTER_FLAG_RX_RSS 0x01 3478 /* Enable RX scatter */ 3479 #define EFX_FILTER_FLAG_RX_SCATTER 0x02 3480 /* 3481 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 3482 * May only be set by the filter implementation for each type. 3483 * A removal request will restore the automatic filter in its place. 3484 */ 3485 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 3486 /* Filter is for RX */ 3487 #define EFX_FILTER_FLAG_RX 0x08 3488 /* Filter is for TX */ 3489 #define EFX_FILTER_FLAG_TX 0x10 3490 /* Set match flag on the received packet */ 3491 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20 3492 /* Set match mark on the received packet */ 3493 #define EFX_FILTER_FLAG_ACTION_MARK 0x40 3494 3495 typedef uint8_t efx_filter_flags_t; 3496 3497 /* 3498 * Flags which specify the fields to match on. The values are the same as in the 3499 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands. 3500 */ 3501 3502 /* Match by remote IP host address */ 3503 #define EFX_FILTER_MATCH_REM_HOST 0x00000001 3504 /* Match by local IP host address */ 3505 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002 3506 /* Match by remote MAC address */ 3507 #define EFX_FILTER_MATCH_REM_MAC 0x00000004 3508 /* Match by remote TCP/UDP port */ 3509 #define EFX_FILTER_MATCH_REM_PORT 0x00000008 3510 /* Match by remote TCP/UDP port */ 3511 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010 3512 /* Match by local TCP/UDP port */ 3513 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020 3514 /* Match by Ether-type */ 3515 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040 3516 /* Match by inner VLAN ID */ 3517 #define EFX_FILTER_MATCH_INNER_VID 0x00000080 3518 /* Match by outer VLAN ID */ 3519 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100 3520 /* Match by IP transport protocol */ 3521 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200 3522 /* Match by ingress MPORT */ 3523 #define EFX_FILTER_MATCH_MPORT 0x00000400 3524 /* Match by VNI or VSID */ 3525 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800 3526 /* For encapsulated packets, match by inner frame local MAC address */ 3527 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000 3528 /* For encapsulated packets, match all multicast inner frames */ 3529 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000 3530 /* For encapsulated packets, match all unicast inner frames */ 3531 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000 3532 /* 3533 * Match by encap type, this flag does not correspond to 3534 * the MCDI match flags and any unoccupied value may be used 3535 */ 3536 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000 3537 /* Match otherwise-unmatched multicast and broadcast packets */ 3538 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000 3539 /* Match otherwise-unmatched unicast packets */ 3540 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000 3541 3542 typedef uint32_t efx_filter_match_flags_t; 3543 3544 /* Filter priority from lowest to highest */ 3545 typedef enum efx_filter_priority_s { 3546 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device 3547 * address list or hardware 3548 * requirements. This may only be used 3549 * by the filter implementation for 3550 * each NIC type. */ 3551 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 3552 EFX_FILTER_NPRI, 3553 } efx_filter_priority_t; 3554 3555 /* 3556 * FIXME: All these fields are assumed to be in little-endian byte order. 3557 * It may be better for some to be big-endian. See bug42804. 3558 */ 3559 3560 typedef struct efx_filter_spec_s { 3561 efx_filter_match_flags_t efs_match_flags; 3562 uint8_t efs_priority; 3563 efx_filter_flags_t efs_flags; 3564 uint16_t efs_dmaq_id; 3565 uint32_t efs_rss_context; 3566 uint32_t efs_mark; 3567 /* 3568 * Saved lower-priority filter. If it is set, it is restored on 3569 * filter delete operation. 3570 */ 3571 struct efx_filter_spec_s *efs_overridden_spec; 3572 /* Fields below here are hashed for software filter lookup */ 3573 uint16_t efs_outer_vid; 3574 uint16_t efs_inner_vid; 3575 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 3576 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 3577 uint16_t efs_ether_type; 3578 uint8_t efs_ip_proto; 3579 efx_tunnel_protocol_t efs_encap_type; 3580 uint16_t efs_loc_port; 3581 uint16_t efs_rem_port; 3582 efx_oword_t efs_rem_host; 3583 efx_oword_t efs_loc_host; 3584 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN]; 3585 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN]; 3586 uint32_t efs_ingress_mport; 3587 } efx_filter_spec_t; 3588 3589 3590 /* Default values for use in filter specifications */ 3591 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 3592 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 3593 3594 LIBEFX_API 3595 extern __checkReturn efx_rc_t 3596 efx_filter_init( 3597 __in efx_nic_t *enp); 3598 3599 LIBEFX_API 3600 extern void 3601 efx_filter_fini( 3602 __in efx_nic_t *enp); 3603 3604 LIBEFX_API 3605 extern __checkReturn efx_rc_t 3606 efx_filter_insert( 3607 __in efx_nic_t *enp, 3608 __inout efx_filter_spec_t *spec); 3609 3610 LIBEFX_API 3611 extern __checkReturn efx_rc_t 3612 efx_filter_remove( 3613 __in efx_nic_t *enp, 3614 __inout efx_filter_spec_t *spec); 3615 3616 LIBEFX_API 3617 extern __checkReturn efx_rc_t 3618 efx_filter_restore( 3619 __in efx_nic_t *enp); 3620 3621 LIBEFX_API 3622 extern __checkReturn efx_rc_t 3623 efx_filter_supported_filters( 3624 __in efx_nic_t *enp, 3625 __out_ecount(buffer_length) uint32_t *buffer, 3626 __in size_t buffer_length, 3627 __out size_t *list_lengthp); 3628 3629 LIBEFX_API 3630 extern void 3631 efx_filter_spec_init_rx( 3632 __out efx_filter_spec_t *spec, 3633 __in efx_filter_priority_t priority, 3634 __in efx_filter_flags_t flags, 3635 __in efx_rxq_t *erp); 3636 3637 LIBEFX_API 3638 extern void 3639 efx_filter_spec_init_tx( 3640 __out efx_filter_spec_t *spec, 3641 __in efx_txq_t *etp); 3642 3643 LIBEFX_API 3644 extern __checkReturn efx_rc_t 3645 efx_filter_spec_set_ipv4_local( 3646 __inout efx_filter_spec_t *spec, 3647 __in uint8_t proto, 3648 __in uint32_t host, 3649 __in uint16_t port); 3650 3651 LIBEFX_API 3652 extern __checkReturn efx_rc_t 3653 efx_filter_spec_set_ipv4_full( 3654 __inout efx_filter_spec_t *spec, 3655 __in uint8_t proto, 3656 __in uint32_t lhost, 3657 __in uint16_t lport, 3658 __in uint32_t rhost, 3659 __in uint16_t rport); 3660 3661 LIBEFX_API 3662 extern __checkReturn efx_rc_t 3663 efx_filter_spec_set_eth_local( 3664 __inout efx_filter_spec_t *spec, 3665 __in uint16_t vid, 3666 __in const uint8_t *addr); 3667 3668 LIBEFX_API 3669 extern void 3670 efx_filter_spec_set_ether_type( 3671 __inout efx_filter_spec_t *spec, 3672 __in uint16_t ether_type); 3673 3674 LIBEFX_API 3675 extern __checkReturn efx_rc_t 3676 efx_filter_spec_set_uc_def( 3677 __inout efx_filter_spec_t *spec); 3678 3679 LIBEFX_API 3680 extern __checkReturn efx_rc_t 3681 efx_filter_spec_set_mc_def( 3682 __inout efx_filter_spec_t *spec); 3683 3684 typedef enum efx_filter_inner_frame_match_e { 3685 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0, 3686 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST, 3687 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST 3688 } efx_filter_inner_frame_match_t; 3689 3690 LIBEFX_API 3691 extern __checkReturn efx_rc_t 3692 efx_filter_spec_set_encap_type( 3693 __inout efx_filter_spec_t *spec, 3694 __in efx_tunnel_protocol_t encap_type, 3695 __in efx_filter_inner_frame_match_t inner_frame_match); 3696 3697 LIBEFX_API 3698 extern __checkReturn efx_rc_t 3699 efx_filter_spec_set_vxlan( 3700 __inout efx_filter_spec_t *spec, 3701 __in const uint8_t *vni, 3702 __in const uint8_t *inner_addr, 3703 __in const uint8_t *outer_addr); 3704 3705 LIBEFX_API 3706 extern __checkReturn efx_rc_t 3707 efx_filter_spec_set_geneve( 3708 __inout efx_filter_spec_t *spec, 3709 __in const uint8_t *vni, 3710 __in const uint8_t *inner_addr, 3711 __in const uint8_t *outer_addr); 3712 3713 LIBEFX_API 3714 extern __checkReturn efx_rc_t 3715 efx_filter_spec_set_nvgre( 3716 __inout efx_filter_spec_t *spec, 3717 __in const uint8_t *vsid, 3718 __in const uint8_t *inner_addr, 3719 __in const uint8_t *outer_addr); 3720 3721 #if EFSYS_OPT_RX_SCALE 3722 LIBEFX_API 3723 extern __checkReturn efx_rc_t 3724 efx_filter_spec_set_rss_context( 3725 __inout efx_filter_spec_t *spec, 3726 __in uint32_t rss_context); 3727 #endif 3728 #endif /* EFSYS_OPT_FILTER */ 3729 3730 /* HASH */ 3731 3732 LIBEFX_API 3733 extern __checkReturn uint32_t 3734 efx_hash_dwords( 3735 __in_ecount(count) uint32_t const *input, 3736 __in size_t count, 3737 __in uint32_t init); 3738 3739 LIBEFX_API 3740 extern __checkReturn uint32_t 3741 efx_hash_bytes( 3742 __in_ecount(length) uint8_t const *input, 3743 __in size_t length, 3744 __in uint32_t init); 3745 3746 #if EFSYS_OPT_LICENSING 3747 3748 /* LICENSING */ 3749 3750 typedef struct efx_key_stats_s { 3751 uint32_t eks_valid; 3752 uint32_t eks_invalid; 3753 uint32_t eks_blacklisted; 3754 uint32_t eks_unverifiable; 3755 uint32_t eks_wrong_node; 3756 uint32_t eks_licensed_apps_lo; 3757 uint32_t eks_licensed_apps_hi; 3758 uint32_t eks_licensed_features_lo; 3759 uint32_t eks_licensed_features_hi; 3760 } efx_key_stats_t; 3761 3762 LIBEFX_API 3763 extern __checkReturn efx_rc_t 3764 efx_lic_init( 3765 __in efx_nic_t *enp); 3766 3767 LIBEFX_API 3768 extern void 3769 efx_lic_fini( 3770 __in efx_nic_t *enp); 3771 3772 LIBEFX_API 3773 extern __checkReturn boolean_t 3774 efx_lic_check_support( 3775 __in efx_nic_t *enp); 3776 3777 LIBEFX_API 3778 extern __checkReturn efx_rc_t 3779 efx_lic_update_licenses( 3780 __in efx_nic_t *enp); 3781 3782 LIBEFX_API 3783 extern __checkReturn efx_rc_t 3784 efx_lic_get_key_stats( 3785 __in efx_nic_t *enp, 3786 __out efx_key_stats_t *ksp); 3787 3788 LIBEFX_API 3789 extern __checkReturn efx_rc_t 3790 efx_lic_app_state( 3791 __in efx_nic_t *enp, 3792 __in uint64_t app_id, 3793 __out boolean_t *licensedp); 3794 3795 LIBEFX_API 3796 extern __checkReturn efx_rc_t 3797 efx_lic_get_id( 3798 __in efx_nic_t *enp, 3799 __in size_t buffer_size, 3800 __out uint32_t *typep, 3801 __out size_t *lengthp, 3802 __out_opt uint8_t *bufferp); 3803 3804 3805 LIBEFX_API 3806 extern __checkReturn efx_rc_t 3807 efx_lic_find_start( 3808 __in efx_nic_t *enp, 3809 __in_bcount(buffer_size) 3810 caddr_t bufferp, 3811 __in size_t buffer_size, 3812 __out uint32_t *startp); 3813 3814 LIBEFX_API 3815 extern __checkReturn efx_rc_t 3816 efx_lic_find_end( 3817 __in efx_nic_t *enp, 3818 __in_bcount(buffer_size) 3819 caddr_t bufferp, 3820 __in size_t buffer_size, 3821 __in uint32_t offset, 3822 __out uint32_t *endp); 3823 3824 LIBEFX_API 3825 extern __checkReturn __success(return != B_FALSE) boolean_t 3826 efx_lic_find_key( 3827 __in efx_nic_t *enp, 3828 __in_bcount(buffer_size) 3829 caddr_t bufferp, 3830 __in size_t buffer_size, 3831 __in uint32_t offset, 3832 __out uint32_t *startp, 3833 __out uint32_t *lengthp); 3834 3835 LIBEFX_API 3836 extern __checkReturn __success(return != B_FALSE) boolean_t 3837 efx_lic_validate_key( 3838 __in efx_nic_t *enp, 3839 __in_bcount(length) caddr_t keyp, 3840 __in uint32_t length); 3841 3842 LIBEFX_API 3843 extern __checkReturn efx_rc_t 3844 efx_lic_read_key( 3845 __in efx_nic_t *enp, 3846 __in_bcount(buffer_size) 3847 caddr_t bufferp, 3848 __in size_t buffer_size, 3849 __in uint32_t offset, 3850 __in uint32_t length, 3851 __out_bcount_part(key_max_size, *lengthp) 3852 caddr_t keyp, 3853 __in size_t key_max_size, 3854 __out uint32_t *lengthp); 3855 3856 LIBEFX_API 3857 extern __checkReturn efx_rc_t 3858 efx_lic_write_key( 3859 __in efx_nic_t *enp, 3860 __in_bcount(buffer_size) 3861 caddr_t bufferp, 3862 __in size_t buffer_size, 3863 __in uint32_t offset, 3864 __in_bcount(length) caddr_t keyp, 3865 __in uint32_t length, 3866 __out uint32_t *lengthp); 3867 3868 LIBEFX_API 3869 extern __checkReturn efx_rc_t 3870 efx_lic_delete_key( 3871 __in efx_nic_t *enp, 3872 __in_bcount(buffer_size) 3873 caddr_t bufferp, 3874 __in size_t buffer_size, 3875 __in uint32_t offset, 3876 __in uint32_t length, 3877 __in uint32_t end, 3878 __out uint32_t *deltap); 3879 3880 LIBEFX_API 3881 extern __checkReturn efx_rc_t 3882 efx_lic_create_partition( 3883 __in efx_nic_t *enp, 3884 __in_bcount(buffer_size) 3885 caddr_t bufferp, 3886 __in size_t buffer_size); 3887 3888 extern __checkReturn efx_rc_t 3889 efx_lic_finish_partition( 3890 __in efx_nic_t *enp, 3891 __in_bcount(buffer_size) 3892 caddr_t bufferp, 3893 __in size_t buffer_size); 3894 3895 #endif /* EFSYS_OPT_LICENSING */ 3896 3897 /* TUNNEL */ 3898 3899 #if EFSYS_OPT_TUNNEL 3900 3901 LIBEFX_API 3902 extern __checkReturn efx_rc_t 3903 efx_tunnel_init( 3904 __in efx_nic_t *enp); 3905 3906 LIBEFX_API 3907 extern void 3908 efx_tunnel_fini( 3909 __in efx_nic_t *enp); 3910 3911 /* 3912 * For overlay network encapsulation using UDP, the firmware needs to know 3913 * the configured UDP port for the overlay so it can decode encapsulated 3914 * frames correctly. 3915 * The UDP port/protocol list is global. 3916 */ 3917 3918 LIBEFX_API 3919 extern __checkReturn efx_rc_t 3920 efx_tunnel_config_udp_add( 3921 __in efx_nic_t *enp, 3922 __in uint16_t port /* host/cpu-endian */, 3923 __in efx_tunnel_protocol_t protocol); 3924 3925 /* 3926 * Returns EBUSY if reconfiguration of the port is in progress in other thread. 3927 */ 3928 LIBEFX_API 3929 extern __checkReturn efx_rc_t 3930 efx_tunnel_config_udp_remove( 3931 __in efx_nic_t *enp, 3932 __in uint16_t port /* host/cpu-endian */, 3933 __in efx_tunnel_protocol_t protocol); 3934 3935 /* 3936 * Returns EBUSY if reconfiguration of any of the tunnel entries 3937 * is in progress in other thread. 3938 */ 3939 LIBEFX_API 3940 extern __checkReturn efx_rc_t 3941 efx_tunnel_config_clear( 3942 __in efx_nic_t *enp); 3943 3944 /** 3945 * Apply tunnel UDP ports configuration to hardware. 3946 * 3947 * EAGAIN is returned if hardware will be reset (datapath and managment CPU 3948 * reboot). 3949 */ 3950 LIBEFX_API 3951 extern __checkReturn efx_rc_t 3952 efx_tunnel_reconfigure( 3953 __in efx_nic_t *enp); 3954 3955 #endif /* EFSYS_OPT_TUNNEL */ 3956 3957 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 3958 3959 /** 3960 * Firmware subvariant choice options. 3961 * 3962 * It may be switched to no Tx checksum if attached drivers are either 3963 * preboot or firmware subvariant aware and no VIS are allocated. 3964 * If may be always switched to default explicitly using set request or 3965 * implicitly if unaware driver is attaching. If switching is done when 3966 * a driver is attached, it gets MC_REBOOT event and should recreate its 3967 * datapath. 3968 * 3969 * See SF-119419-TC DPDK Firmware Driver Interface and 3970 * SF-109306-TC EF10 for Driver Writers for details. 3971 */ 3972 typedef enum efx_nic_fw_subvariant_e { 3973 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0, 3974 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1, 3975 EFX_NIC_FW_SUBVARIANT_NTYPES 3976 } efx_nic_fw_subvariant_t; 3977 3978 LIBEFX_API 3979 extern __checkReturn efx_rc_t 3980 efx_nic_get_fw_subvariant( 3981 __in efx_nic_t *enp, 3982 __out efx_nic_fw_subvariant_t *subvariantp); 3983 3984 LIBEFX_API 3985 extern __checkReturn efx_rc_t 3986 efx_nic_set_fw_subvariant( 3987 __in efx_nic_t *enp, 3988 __in efx_nic_fw_subvariant_t subvariant); 3989 3990 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 3991 3992 typedef enum efx_phy_fec_type_e { 3993 EFX_PHY_FEC_NONE = 0, 3994 EFX_PHY_FEC_BASER, 3995 EFX_PHY_FEC_RS 3996 } efx_phy_fec_type_t; 3997 3998 #define EFX_PHY_CAP_FEC_BIT(_fec_bit) (1U << EFX_PHY_CAP_##_fec_bit) 3999 #define EFX_PHY_CAP_FEC_MASK \ 4000 (EFX_PHY_CAP_FEC_BIT(BASER_FEC) | \ 4001 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC) | \ 4002 EFX_PHY_CAP_FEC_BIT(BASER_FEC_REQUESTED) | \ 4003 EFX_PHY_CAP_FEC_BIT(25G_BASER_FEC_REQUESTED) | \ 4004 EFX_PHY_CAP_FEC_BIT(RS_FEC) | \ 4005 EFX_PHY_CAP_FEC_BIT(RS_FEC_REQUESTED)) 4006 4007 LIBEFX_API 4008 extern __checkReturn efx_rc_t 4009 efx_phy_fec_type_get( 4010 __in efx_nic_t *enp, 4011 __out efx_phy_fec_type_t *typep); 4012 4013 typedef struct efx_phy_link_state_s { 4014 uint32_t epls_adv_cap_mask; 4015 uint32_t epls_lp_cap_mask; 4016 uint32_t epls_ld_cap_mask; 4017 unsigned int epls_fcntl; 4018 efx_phy_fec_type_t epls_fec; 4019 efx_link_mode_t epls_link_mode; 4020 } efx_phy_link_state_t; 4021 4022 LIBEFX_API 4023 extern __checkReturn efx_rc_t 4024 efx_phy_link_state_get( 4025 __in efx_nic_t *enp, 4026 __out efx_phy_link_state_t *eplsp); 4027 4028 4029 #if EFSYS_OPT_EVB 4030 4031 typedef uint32_t efx_vswitch_id_t; 4032 typedef uint32_t efx_vport_id_t; 4033 4034 typedef enum efx_vswitch_type_e { 4035 EFX_VSWITCH_TYPE_VLAN = 1, 4036 EFX_VSWITCH_TYPE_VEB, 4037 /* VSWITCH_TYPE_VEPA: obsolete */ 4038 EFX_VSWITCH_TYPE_MUX = 4, 4039 } efx_vswitch_type_t; 4040 4041 typedef enum efx_vport_type_e { 4042 EFX_VPORT_TYPE_NORMAL = 4, 4043 EFX_VPORT_TYPE_EXPANSION, 4044 EFX_VPORT_TYPE_TEST, 4045 } efx_vport_type_t; 4046 4047 /* Unspecified VLAN ID to support disabling of VLAN filtering */ 4048 #define EFX_FILTER_VID_UNSPEC 0xffff 4049 #define EFX_DEFAULT_VSWITCH_ID 1 4050 4051 /* Default VF VLAN ID on creation */ 4052 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC 4053 #define EFX_VPORT_ID_INVALID 0 4054 4055 typedef struct efx_vport_config_s { 4056 /* Either VF index or EFX_PCI_VF_INVALID for PF */ 4057 uint16_t evc_function; 4058 /* VLAN ID of the associated function */ 4059 uint16_t evc_vid; 4060 /* vport id shared with client driver */ 4061 efx_vport_id_t evc_vport_id; 4062 /* MAC address of the associated function */ 4063 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN]; 4064 /* 4065 * vports created with this flag set may only transfer traffic on the 4066 * VLANs permitted by the vport. Also, an attempt to install filter with 4067 * VLAN will be refused unless requesting function has VLAN privilege. 4068 */ 4069 boolean_t evc_vlan_restrict; 4070 /* Whether this function is assigned or not */ 4071 boolean_t evc_vport_assigned; 4072 } efx_vport_config_t; 4073 4074 typedef struct efx_vswitch_s efx_vswitch_t; 4075 4076 LIBEFX_API 4077 extern __checkReturn efx_rc_t 4078 efx_evb_init( 4079 __in efx_nic_t *enp); 4080 4081 LIBEFX_API 4082 extern void 4083 efx_evb_fini( 4084 __in efx_nic_t *enp); 4085 4086 LIBEFX_API 4087 extern __checkReturn efx_rc_t 4088 efx_evb_vswitch_create( 4089 __in efx_nic_t *enp, 4090 __in uint32_t num_vports, 4091 __inout_ecount(num_vports) efx_vport_config_t *vport_configp, 4092 __deref_out efx_vswitch_t **evpp); 4093 4094 LIBEFX_API 4095 extern __checkReturn efx_rc_t 4096 efx_evb_vswitch_destroy( 4097 __in efx_nic_t *enp, 4098 __in efx_vswitch_t *evp); 4099 4100 LIBEFX_API 4101 extern __checkReturn efx_rc_t 4102 efx_evb_vport_mac_set( 4103 __in efx_nic_t *enp, 4104 __in efx_vswitch_t *evp, 4105 __in efx_vport_id_t vport_id, 4106 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp); 4107 4108 LIBEFX_API 4109 extern __checkReturn efx_rc_t 4110 efx_evb_vport_vlan_set( 4111 __in efx_nic_t *enp, 4112 __in efx_vswitch_t *evp, 4113 __in efx_vport_id_t vport_id, 4114 __in uint16_t vid); 4115 4116 LIBEFX_API 4117 extern __checkReturn efx_rc_t 4118 efx_evb_vport_reset( 4119 __in efx_nic_t *enp, 4120 __in efx_vswitch_t *evp, 4121 __in efx_vport_id_t vport_id, 4122 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp, 4123 __in uint16_t vid, 4124 __out boolean_t *is_fn_resetp); 4125 4126 LIBEFX_API 4127 extern __checkReturn efx_rc_t 4128 efx_evb_vport_stats( 4129 __in efx_nic_t *enp, 4130 __in efx_vswitch_t *evp, 4131 __in efx_vport_id_t vport_id, 4132 __out efsys_mem_t *stats_bufferp); 4133 4134 #endif /* EFSYS_OPT_EVB */ 4135 4136 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 4137 4138 typedef struct efx_proxy_auth_config_s { 4139 efsys_mem_t *request_bufferp; 4140 efsys_mem_t *response_bufferp; 4141 efsys_mem_t *status_bufferp; 4142 uint32_t block_cnt; 4143 uint32_t *op_listp; 4144 size_t op_count; 4145 uint32_t handled_privileges; 4146 } efx_proxy_auth_config_t; 4147 4148 typedef struct efx_proxy_cmd_params_s { 4149 uint32_t pf_index; 4150 uint32_t vf_index; 4151 uint8_t *request_bufferp; 4152 size_t request_size; 4153 uint8_t *response_bufferp; 4154 size_t response_size; 4155 size_t *response_size_actualp; 4156 } efx_proxy_cmd_params_t; 4157 4158 LIBEFX_API 4159 extern __checkReturn efx_rc_t 4160 efx_proxy_auth_init( 4161 __in efx_nic_t *enp); 4162 4163 LIBEFX_API 4164 extern void 4165 efx_proxy_auth_fini( 4166 __in efx_nic_t *enp); 4167 4168 LIBEFX_API 4169 extern __checkReturn efx_rc_t 4170 efx_proxy_auth_configure( 4171 __in efx_nic_t *enp, 4172 __in efx_proxy_auth_config_t *configp); 4173 4174 LIBEFX_API 4175 extern __checkReturn efx_rc_t 4176 efx_proxy_auth_destroy( 4177 __in efx_nic_t *enp, 4178 __in uint32_t handled_privileges); 4179 4180 LIBEFX_API 4181 extern __checkReturn efx_rc_t 4182 efx_proxy_auth_complete_request( 4183 __in efx_nic_t *enp, 4184 __in uint32_t fn_index, 4185 __in uint32_t proxy_result, 4186 __in uint32_t handle); 4187 4188 LIBEFX_API 4189 extern __checkReturn efx_rc_t 4190 efx_proxy_auth_exec_cmd( 4191 __in efx_nic_t *enp, 4192 __inout efx_proxy_cmd_params_t *paramsp); 4193 4194 LIBEFX_API 4195 extern __checkReturn efx_rc_t 4196 efx_proxy_auth_set_privilege_mask( 4197 __in efx_nic_t *enp, 4198 __in uint32_t vf_index, 4199 __in uint32_t mask, 4200 __in uint32_t value); 4201 4202 LIBEFX_API 4203 extern __checkReturn efx_rc_t 4204 efx_proxy_auth_privilege_mask_get( 4205 __in efx_nic_t *enp, 4206 __in uint32_t pf_index, 4207 __in uint32_t vf_index, 4208 __out uint32_t *maskp); 4209 4210 LIBEFX_API 4211 extern __checkReturn efx_rc_t 4212 efx_proxy_auth_privilege_modify( 4213 __in efx_nic_t *enp, 4214 __in uint32_t pf_index, 4215 __in uint32_t vf_index, 4216 __in uint32_t add_privileges_mask, 4217 __in uint32_t remove_privileges_mask); 4218 4219 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 4220 4221 #if EFSYS_OPT_MAE 4222 4223 LIBEFX_API 4224 extern __checkReturn efx_rc_t 4225 efx_mae_init( 4226 __in efx_nic_t *enp); 4227 4228 LIBEFX_API 4229 extern void 4230 efx_mae_fini( 4231 __in efx_nic_t *enp); 4232 4233 typedef struct efx_mae_limits_s { 4234 uint32_t eml_max_n_action_prios; 4235 uint32_t eml_max_n_outer_prios; 4236 uint32_t eml_encap_types_supported; 4237 uint32_t eml_encap_header_size_limit; 4238 union { 4239 uint32_t eml_max_n_counters; 4240 uint32_t eml_max_n_action_counters; 4241 }; 4242 uint32_t eml_max_n_conntrack_counters; 4243 } efx_mae_limits_t; 4244 4245 LIBEFX_API 4246 extern __checkReturn efx_rc_t 4247 efx_mae_get_limits( 4248 __in efx_nic_t *enp, 4249 __out efx_mae_limits_t *emlp); 4250 4251 typedef enum efx_mae_rule_type_e { 4252 EFX_MAE_RULE_ACTION = 0, 4253 EFX_MAE_RULE_OUTER, 4254 4255 EFX_MAE_RULE_NTYPES 4256 } efx_mae_rule_type_t; 4257 4258 typedef struct efx_mae_match_spec_s efx_mae_match_spec_t; 4259 4260 LIBEFX_API 4261 extern __checkReturn efx_rc_t 4262 efx_mae_match_spec_init( 4263 __in efx_nic_t *enp, 4264 __in efx_mae_rule_type_t type, 4265 __in uint32_t prio, 4266 __out efx_mae_match_spec_t **specp); 4267 4268 LIBEFX_API 4269 extern void 4270 efx_mae_match_spec_fini( 4271 __in efx_nic_t *enp, 4272 __in efx_mae_match_spec_t *spec); 4273 4274 typedef enum efx_mae_field_id_e { 4275 /* 4276 * Fields which can be set by efx_mae_match_spec_field_set() 4277 * or by using dedicated field-specific helper APIs. 4278 */ 4279 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0, 4280 EFX_MAE_FIELD_ETHER_TYPE_BE, 4281 EFX_MAE_FIELD_ETH_SADDR_BE, 4282 EFX_MAE_FIELD_ETH_DADDR_BE, 4283 EFX_MAE_FIELD_VLAN0_TCI_BE, 4284 EFX_MAE_FIELD_VLAN0_PROTO_BE, 4285 EFX_MAE_FIELD_VLAN1_TCI_BE, 4286 EFX_MAE_FIELD_VLAN1_PROTO_BE, 4287 EFX_MAE_FIELD_SRC_IP4_BE, 4288 EFX_MAE_FIELD_DST_IP4_BE, 4289 EFX_MAE_FIELD_IP_PROTO, 4290 EFX_MAE_FIELD_IP_TOS, 4291 EFX_MAE_FIELD_IP_TTL, 4292 EFX_MAE_FIELD_SRC_IP6_BE, 4293 EFX_MAE_FIELD_DST_IP6_BE, 4294 EFX_MAE_FIELD_L4_SPORT_BE, 4295 EFX_MAE_FIELD_L4_DPORT_BE, 4296 EFX_MAE_FIELD_TCP_FLAGS_BE, 4297 EFX_MAE_FIELD_ENC_ETHER_TYPE_BE, 4298 EFX_MAE_FIELD_ENC_ETH_SADDR_BE, 4299 EFX_MAE_FIELD_ENC_ETH_DADDR_BE, 4300 EFX_MAE_FIELD_ENC_VLAN0_TCI_BE, 4301 EFX_MAE_FIELD_ENC_VLAN0_PROTO_BE, 4302 EFX_MAE_FIELD_ENC_VLAN1_TCI_BE, 4303 EFX_MAE_FIELD_ENC_VLAN1_PROTO_BE, 4304 EFX_MAE_FIELD_ENC_SRC_IP4_BE, 4305 EFX_MAE_FIELD_ENC_DST_IP4_BE, 4306 EFX_MAE_FIELD_ENC_IP_PROTO, 4307 EFX_MAE_FIELD_ENC_IP_TOS, 4308 EFX_MAE_FIELD_ENC_IP_TTL, 4309 EFX_MAE_FIELD_ENC_SRC_IP6_BE, 4310 EFX_MAE_FIELD_ENC_DST_IP6_BE, 4311 EFX_MAE_FIELD_ENC_L4_SPORT_BE, 4312 EFX_MAE_FIELD_ENC_L4_DPORT_BE, 4313 EFX_MAE_FIELD_ENC_VNET_ID_BE, 4314 EFX_MAE_FIELD_OUTER_RULE_ID, 4315 4316 /* Single bits which can be set by efx_mae_match_spec_bit_set(). */ 4317 EFX_MAE_FIELD_HAS_OVLAN, 4318 EFX_MAE_FIELD_HAS_IVLAN, 4319 EFX_MAE_FIELD_ENC_HAS_OVLAN, 4320 EFX_MAE_FIELD_ENC_HAS_IVLAN, 4321 4322 /* 4323 * Fields which can be set by efx_mae_match_spec_field_set() 4324 * or by using dedicated field-specific helper APIs. 4325 */ 4326 EFX_MAE_FIELD_RECIRC_ID, 4327 EFX_MAE_FIELD_CT_MARK, 4328 4329 /* Single bits which can be set by efx_mae_match_spec_bit_set(). */ 4330 EFX_MAE_FIELD_IS_IP_FRAG, 4331 EFX_MAE_FIELD_IP_FIRST_FRAG, 4332 EFX_MAE_FIELD_NIDS 4333 } efx_mae_field_id_t; 4334 4335 /* MPORT selector. Used to refer to MPORTs in match/action rules. */ 4336 typedef struct efx_mport_sel_s { 4337 uint32_t sel; 4338 } efx_mport_sel_t; 4339 4340 /* 4341 * MPORT ID. Used to refer dynamically to a specific MPORT. 4342 * The difference between MPORT selector and MPORT ID is that 4343 * selector can specify an exact MPORT ID or it can specify a 4344 * pattern by which an exact MPORT ID can be selected. For example, 4345 * static MPORT selector can specify MPORT of a current PF, which 4346 * will be translated to the dynamic MPORT ID based on which PF is 4347 * using that MPORT selector. 4348 */ 4349 typedef struct efx_mport_id_s { 4350 uint32_t id; 4351 } efx_mport_id_t; 4352 4353 typedef enum efx_mport_type_e { 4354 EFX_MPORT_TYPE_NET_PORT = 0, 4355 EFX_MPORT_TYPE_ALIAS, 4356 EFX_MPORT_TYPE_VNIC, 4357 } efx_mport_type_t; 4358 4359 typedef enum efx_mport_vnic_client_type_e { 4360 EFX_MPORT_VNIC_CLIENT_FUNCTION = 1, 4361 EFX_MPORT_VNIC_CLIENT_PLUGIN, 4362 } efx_mport_vnic_client_type_t; 4363 4364 typedef struct efx_mport_desc_s { 4365 efx_mport_id_t emd_id; 4366 boolean_t emd_can_receive_on; 4367 boolean_t emd_can_deliver_to; 4368 boolean_t emd_can_delete; 4369 boolean_t emd_zombie; 4370 efx_mport_type_t emd_type; 4371 union { 4372 struct { 4373 uint32_t ep_index; 4374 } emd_net_port; 4375 struct { 4376 efx_mport_id_t ea_target_mport_id; 4377 } emd_alias; 4378 struct { 4379 efx_mport_vnic_client_type_t ev_client_type; 4380 efx_pcie_interface_t ev_intf; 4381 uint16_t ev_pf; 4382 uint16_t ev_vf; 4383 /* MCDI client handle for this VNIC. */ 4384 uint32_t ev_handle; 4385 } emd_vnic; 4386 }; 4387 } efx_mport_desc_t; 4388 4389 #define EFX_MPORT_NULL (0U) 4390 4391 /* 4392 * Generate an invalid MPORT selector. 4393 * 4394 * The resulting MPORT selector is opaque to the caller. Requests 4395 * that attempt to use it will be rejected. 4396 */ 4397 LIBEFX_API 4398 extern __checkReturn efx_rc_t 4399 efx_mae_mport_invalid( 4400 __out efx_mport_sel_t *mportp); 4401 4402 /* 4403 * Get MPORT selector of a physical port. 4404 * 4405 * The resulting MPORT selector is opaque to the caller and can be 4406 * passed as an argument to efx_mae_match_spec_mport_set() 4407 * and efx_mae_action_set_populate_deliver(). 4408 */ 4409 LIBEFX_API 4410 extern __checkReturn efx_rc_t 4411 efx_mae_mport_by_phy_port( 4412 __in uint32_t phy_port, 4413 __out efx_mport_sel_t *mportp); 4414 4415 /* 4416 * Get MPORT selector of a PCIe function. 4417 * 4418 * The resulting MPORT selector is opaque to the caller and can be 4419 * passed as an argument to efx_mae_match_spec_mport_set() 4420 * and efx_mae_action_set_populate_deliver(). 4421 */ 4422 LIBEFX_API 4423 extern __checkReturn efx_rc_t 4424 efx_mae_mport_by_pcie_function( 4425 __in uint32_t pf, 4426 __in uint32_t vf, 4427 __out efx_mport_sel_t *mportp); 4428 4429 /* 4430 * Get MPORT selector of a multi-host PCIe function. 4431 * 4432 * The resulting MPORT selector is opaque to the caller and can be 4433 * passed as an argument to efx_mae_match_spec_mport_set() 4434 * and efx_mae_action_set_populate_deliver(). 4435 */ 4436 LIBEFX_API 4437 extern __checkReturn efx_rc_t 4438 efx_mae_mport_by_pcie_mh_function( 4439 __in efx_pcie_interface_t intf, 4440 __in uint32_t pf, 4441 __in uint32_t vf, 4442 __out efx_mport_sel_t *mportp); 4443 4444 /* 4445 * Get MPORT selector by an MPORT ID 4446 * 4447 * The resulting MPORT selector is opaque to the caller and can be 4448 * passed as an argument to efx_mae_match_spec_mport_set() 4449 * and efx_mae_action_set_populate_deliver(). 4450 */ 4451 LIBEFX_API 4452 extern __checkReturn efx_rc_t 4453 efx_mae_mport_by_id( 4454 __in const efx_mport_id_t *mport_idp, 4455 __out efx_mport_sel_t *mportp); 4456 4457 /* Get MPORT ID by an MPORT selector */ 4458 LIBEFX_API 4459 extern __checkReturn efx_rc_t 4460 efx_mae_mport_id_by_selector( 4461 __in efx_nic_t *enp, 4462 __in const efx_mport_sel_t *mport_selectorp, 4463 __out efx_mport_id_t *mport_idp); 4464 4465 /* 4466 * Fields which have BE postfix in their named constants are expected 4467 * to be passed by callers in big-endian byte order. They will appear 4468 * in the MCDI buffer, which is a part of the match specification, in 4469 * the very same byte order, that is, no conversion will be performed. 4470 * 4471 * Fields which don't have BE postfix in their named constants are in 4472 * host byte order. MCDI expects them to be little-endian, so the API 4473 * will take care to carry out conversion to little-endian byte order. 4474 * At the moment, the only field in host byte order is MPORT selector. 4475 */ 4476 LIBEFX_API 4477 extern __checkReturn efx_rc_t 4478 efx_mae_match_spec_field_set( 4479 __in efx_mae_match_spec_t *spec, 4480 __in efx_mae_field_id_t field_id, 4481 __in size_t value_size, 4482 __in_bcount(value_size) const uint8_t *value, 4483 __in size_t mask_size, 4484 __in_bcount(mask_size) const uint8_t *mask); 4485 4486 LIBEFX_API 4487 extern __checkReturn efx_rc_t 4488 efx_mae_match_spec_field_get( 4489 __in const efx_mae_match_spec_t *spec, 4490 __in efx_mae_field_id_t field_id, 4491 __in size_t value_size, 4492 __out_bcount_opt(value_size) uint8_t *value, 4493 __in size_t mask_size, 4494 __out_bcount_opt(mask_size) uint8_t *mask); 4495 4496 /* The corresponding mask will be set to B_TRUE. */ 4497 LIBEFX_API 4498 extern __checkReturn efx_rc_t 4499 efx_mae_match_spec_bit_set( 4500 __in efx_mae_match_spec_t *spec, 4501 __in efx_mae_field_id_t field_id, 4502 __in boolean_t value); 4503 4504 /* If the mask argument is NULL, the API will use full mask by default. */ 4505 LIBEFX_API 4506 extern __checkReturn efx_rc_t 4507 efx_mae_match_spec_mport_set( 4508 __in efx_mae_match_spec_t *spec, 4509 __in const efx_mport_sel_t *valuep, 4510 __in_opt const efx_mport_sel_t *maskp); 4511 4512 LIBEFX_API 4513 extern __checkReturn efx_rc_t 4514 efx_mae_match_spec_recirc_id_set( 4515 __in efx_mae_match_spec_t *spec, 4516 __in uint8_t recirc_id); 4517 4518 LIBEFX_API 4519 extern __checkReturn efx_rc_t 4520 efx_mae_match_spec_ct_mark_set( 4521 __in efx_mae_match_spec_t *spec, 4522 __in uint32_t ct_mark); 4523 4524 LIBEFX_API 4525 extern __checkReturn efx_rc_t 4526 efx_mae_match_spec_clone( 4527 __in efx_nic_t *enp, 4528 __in efx_mae_match_spec_t *orig, 4529 __out efx_mae_match_spec_t **clonep); 4530 4531 LIBEFX_API 4532 extern __checkReturn boolean_t 4533 efx_mae_match_specs_equal( 4534 __in const efx_mae_match_spec_t *left, 4535 __in const efx_mae_match_spec_t *right); 4536 4537 /* 4538 * Make sure that match fields known by EFX have proper masks set 4539 * in the match specification as per requirements of SF-122526-TC. 4540 * 4541 * In the case efx_mae_field_id_t lacks named identifiers for any 4542 * fields which the FW maintains with support status MATCH_ALWAYS, 4543 * the validation result may not be accurate. 4544 */ 4545 LIBEFX_API 4546 extern __checkReturn boolean_t 4547 efx_mae_match_spec_is_valid( 4548 __in efx_nic_t *enp, 4549 __in const efx_mae_match_spec_t *spec); 4550 4551 typedef struct efx_mae_actions_s efx_mae_actions_t; 4552 4553 LIBEFX_API 4554 extern __checkReturn efx_rc_t 4555 efx_mae_action_set_spec_init( 4556 __in efx_nic_t *enp, 4557 __out efx_mae_actions_t **specp); 4558 4559 LIBEFX_API 4560 extern void 4561 efx_mae_action_set_spec_fini( 4562 __in efx_nic_t *enp, 4563 __in efx_mae_actions_t *spec); 4564 4565 LIBEFX_API 4566 extern __checkReturn efx_rc_t 4567 efx_mae_action_set_populate_decap( 4568 __in efx_mae_actions_t *spec); 4569 4570 LIBEFX_API 4571 extern __checkReturn efx_rc_t 4572 efx_mae_action_set_populate_vlan_pop( 4573 __in efx_mae_actions_t *spec); 4574 4575 /* 4576 * This always amends the outermost header. This way, for a tunnel 4577 * packet, if action DECAP is not requested, this will affect the 4578 * outer header; otherwise, the inner header will be updated. 4579 * 4580 * Use efx_mae_action_set_fill_in_dst_mac_id() to set ID of 4581 * the allocated MAC address entry in the specification 4582 * prior to action set allocation. 4583 */ 4584 LIBEFX_API 4585 extern __checkReturn efx_rc_t 4586 efx_mae_action_set_populate_set_dst_mac( 4587 __in efx_mae_actions_t *spec); 4588 4589 /* 4590 * This always amends the outermost header. This way, for a tunnel 4591 * packet, if action DECAP is not requested, this will affect the 4592 * outer header; otherwise, the inner header will be updated. 4593 * 4594 * Use efx_mae_action_set_fill_in_src_mac_id() to set ID of 4595 * the allocated MAC address entry in the specification 4596 * prior to action set allocation. 4597 */ 4598 LIBEFX_API 4599 extern __checkReturn efx_rc_t 4600 efx_mae_action_set_populate_set_src_mac( 4601 __in efx_mae_actions_t *spec); 4602 4603 /* 4604 * This always amends the outermost header. This way, for a tunnel 4605 * packet, if action DECAP is not requested, this will affect the 4606 * outer header; otherwise, the inner header will be updated. 4607 * 4608 * This will also take care to update IPv4 checksum accordingly. 4609 */ 4610 LIBEFX_API 4611 extern __checkReturn efx_rc_t 4612 efx_mae_action_set_populate_decr_ip_ttl( 4613 __in efx_mae_actions_t *spec); 4614 4615 /* 4616 * This only requests NAT action. The replacement IP address and 4617 * L4 port number, as well as the edit direction (DST/SRC), come 4618 * from the response to a hit in the conntrack assistance table. 4619 * 4620 * The action amends the outermost frame. In the case of prior 4621 * decapsulation, that maps to the (originally) inner frame. 4622 */ 4623 LIBEFX_API 4624 extern __checkReturn efx_rc_t 4625 efx_mae_action_set_populate_nat( 4626 __in efx_mae_actions_t *spec); 4627 4628 LIBEFX_API 4629 extern __checkReturn efx_rc_t 4630 efx_mae_action_set_populate_vlan_push( 4631 __in efx_mae_actions_t *spec, 4632 __in uint16_t tpid_be, 4633 __in uint16_t tci_be); 4634 4635 /* 4636 * Use efx_mae_action_set_fill_in_eh_id() to set ID of the allocated 4637 * encap. header in the specification prior to action set allocation. 4638 */ 4639 LIBEFX_API 4640 extern __checkReturn efx_rc_t 4641 efx_mae_action_set_populate_encap( 4642 __in efx_mae_actions_t *spec); 4643 4644 /* 4645 * Use efx_mae_action_set_fill_in_counter_id() to set ID of a counter 4646 * in the specification prior to action set allocation. 4647 * 4648 * NOTICE: the HW will conduct action COUNT after actions DECAP, 4649 * VLAN_POP, VLAN_PUSH (if any) have been applied to the packet, 4650 * but, as a workaround, this order is not validated by the API. 4651 * 4652 * The workaround helps to unblock DPDK + Open vSwitch use case. 4653 * In Open vSwitch, this action is always the first to be added, 4654 * in particular, it's known to be inserted before action DECAP, 4655 * so enforcing the right order here would cause runtime errors. 4656 * The existing behaviour in Open vSwitch is unlikely to change 4657 * any time soon, and the workaround is a good solution because 4658 * in fact the real COUNT order is a don't care to Open vSwitch. 4659 */ 4660 LIBEFX_API 4661 extern __checkReturn efx_rc_t 4662 efx_mae_action_set_populate_count( 4663 __in efx_mae_actions_t *spec); 4664 4665 LIBEFX_API 4666 extern __checkReturn efx_rc_t 4667 efx_mae_action_set_populate_flag( 4668 __in efx_mae_actions_t *spec); 4669 4670 LIBEFX_API 4671 extern __checkReturn efx_rc_t 4672 efx_mae_action_set_populate_mark( 4673 __in efx_mae_actions_t *spec, 4674 __in uint32_t mark_value); 4675 4676 /* 4677 * Whilst efx_mae_action_set_populate_mark() can be used to request setting 4678 * a user mark in matching packets and demands that the request come before 4679 * setting the final destination (deliver action), this API can be invoked 4680 * after deliver action has been added in order to request mark reset if 4681 * the user's own mark request has not been added as a result of parsing. 4682 * 4683 * It is useful when the driver chains an outer rule (OR) with an action 4684 * rule (AR) by virtue of a recirculation ID. The OR may set mark from 4685 * this ID to help the driver identify packets that hit the OR and do 4686 * not hit the AR. But, for packets that do hit the AR, the driver 4687 * wants to reset the mark value to avoid confusing recipients. 4688 */ 4689 LIBEFX_API 4690 extern void 4691 efx_mae_action_set_populate_mark_reset( 4692 __in efx_mae_actions_t *spec); 4693 4694 LIBEFX_API 4695 extern __checkReturn efx_rc_t 4696 efx_mae_action_set_populate_deliver( 4697 __in efx_mae_actions_t *spec, 4698 __in const efx_mport_sel_t *mportp); 4699 4700 LIBEFX_API 4701 extern __checkReturn efx_rc_t 4702 efx_mae_action_set_populate_drop( 4703 __in efx_mae_actions_t *spec); 4704 4705 LIBEFX_API 4706 extern __checkReturn boolean_t 4707 efx_mae_action_set_specs_equal( 4708 __in const efx_mae_actions_t *left, 4709 __in const efx_mae_actions_t *right); 4710 4711 /* 4712 * Conduct a comparison to check whether two match specifications 4713 * of equal rule type (action / outer) and priority would map to 4714 * the very same rule class from the firmware's standpoint. 4715 * 4716 * For match specification fields that are not supported by firmware, 4717 * the rule class only matches if the mask/value pairs for that field 4718 * are equal. Clients should use efx_mae_match_spec_is_valid() before 4719 * calling this API to detect usage of unsupported fields. 4720 */ 4721 LIBEFX_API 4722 extern __checkReturn efx_rc_t 4723 efx_mae_match_specs_class_cmp( 4724 __in efx_nic_t *enp, 4725 __in const efx_mae_match_spec_t *left, 4726 __in const efx_mae_match_spec_t *right, 4727 __out boolean_t *have_same_classp); 4728 4729 #define EFX_MAE_RSRC_ID_INVALID UINT32_MAX 4730 4731 /* Rule ID */ 4732 typedef struct efx_mae_rule_id_s { 4733 uint32_t id; 4734 } efx_mae_rule_id_t; 4735 4736 /* 4737 * Set the initial recirculation ID. It goes to action rule (AR) lookup. 4738 * 4739 * To match on this ID in an AR, use efx_mae_match_spec_recirc_id_set(). 4740 */ 4741 LIBEFX_API 4742 extern __checkReturn efx_rc_t 4743 efx_mae_outer_rule_recirc_id_set( 4744 __in efx_mae_match_spec_t *spec, 4745 __in uint8_t recirc_id); 4746 4747 /* 4748 * Request that packets hitting this rule be submitted 4749 * for a lookup in the conntrack assistance table. 4750 */ 4751 LIBEFX_API 4752 extern __checkReturn efx_rc_t 4753 efx_mae_outer_rule_do_ct_set( 4754 __in efx_mae_match_spec_t *spec); 4755 4756 LIBEFX_API 4757 extern __checkReturn efx_rc_t 4758 efx_mae_outer_rule_insert( 4759 __in efx_nic_t *enp, 4760 __in const efx_mae_match_spec_t *spec, 4761 __in efx_tunnel_protocol_t encap_type, 4762 __out efx_mae_rule_id_t *or_idp); 4763 4764 LIBEFX_API 4765 extern __checkReturn efx_rc_t 4766 efx_mae_outer_rule_remove( 4767 __in efx_nic_t *enp, 4768 __in const efx_mae_rule_id_t *or_idp); 4769 4770 LIBEFX_API 4771 extern __checkReturn efx_rc_t 4772 efx_mae_match_spec_outer_rule_id_set( 4773 __in efx_mae_match_spec_t *spec, 4774 __in const efx_mae_rule_id_t *or_idp); 4775 4776 /* MAC address entry ID */ 4777 typedef struct efx_mae_mac_id_s { 4778 uint32_t id; 4779 } efx_mae_mac_id_t; 4780 4781 LIBEFX_API 4782 extern __checkReturn efx_rc_t 4783 efx_mae_mac_addr_alloc( 4784 __in efx_nic_t *enp, 4785 __in uint8_t addr_bytes[EFX_MAC_ADDR_LEN], 4786 __out efx_mae_mac_id_t *mac_idp); 4787 4788 LIBEFX_API 4789 extern __checkReturn efx_rc_t 4790 efx_mae_mac_addr_free( 4791 __in efx_nic_t *enp, 4792 __in const efx_mae_mac_id_t *mac_idp); 4793 4794 /* See description before efx_mae_action_set_populate_set_dst_mac(). */ 4795 LIBEFX_API 4796 extern __checkReturn efx_rc_t 4797 efx_mae_action_set_fill_in_dst_mac_id( 4798 __in efx_mae_actions_t *spec, 4799 __in const efx_mae_mac_id_t *mac_idp); 4800 4801 /* See description before efx_mae_action_set_populate_set_src_mac(). */ 4802 LIBEFX_API 4803 extern __checkReturn efx_rc_t 4804 efx_mae_action_set_fill_in_src_mac_id( 4805 __in efx_mae_actions_t *spec, 4806 __in const efx_mae_mac_id_t *mac_idp); 4807 4808 /* Encap. header ID */ 4809 typedef struct efx_mae_eh_id_s { 4810 uint32_t id; 4811 } efx_mae_eh_id_t; 4812 4813 LIBEFX_API 4814 extern __checkReturn efx_rc_t 4815 efx_mae_encap_header_alloc( 4816 __in efx_nic_t *enp, 4817 __in efx_tunnel_protocol_t encap_type, 4818 __in_bcount(header_size) uint8_t *header_data, 4819 __in size_t header_size, 4820 __out efx_mae_eh_id_t *eh_idp); 4821 4822 LIBEFX_API 4823 extern __checkReturn efx_rc_t 4824 efx_mae_encap_header_update( 4825 __in efx_nic_t *enp, 4826 __in efx_mae_eh_id_t *eh_idp, 4827 __in efx_tunnel_protocol_t encap_type, 4828 __in_bcount(header_size) const uint8_t *header_data, 4829 __in size_t header_size); 4830 4831 LIBEFX_API 4832 extern __checkReturn efx_rc_t 4833 efx_mae_encap_header_free( 4834 __in efx_nic_t *enp, 4835 __in const efx_mae_eh_id_t *eh_idp); 4836 4837 /* See description before efx_mae_action_set_populate_encap(). */ 4838 LIBEFX_API 4839 extern __checkReturn efx_rc_t 4840 efx_mae_action_set_fill_in_eh_id( 4841 __in efx_mae_actions_t *spec, 4842 __in const efx_mae_eh_id_t *eh_idp); 4843 4844 /* 4845 * Counter types that may be supported by the match-action engine. 4846 * Each counter type maintains its own counter ID namespace in FW. 4847 */ 4848 typedef enum efx_counter_type_e { 4849 EFX_COUNTER_TYPE_ACTION = 0, 4850 EFX_COUNTER_TYPE_CONNTRACK, 4851 } efx_counter_type_t; 4852 4853 typedef struct efx_counter_s { 4854 uint32_t id; 4855 } efx_counter_t; 4856 4857 LIBEFX_API 4858 extern __checkReturn unsigned int 4859 efx_mae_action_set_get_nb_count( 4860 __in const efx_mae_actions_t *spec); 4861 4862 /* See description before efx_mae_action_set_populate_count(). */ 4863 LIBEFX_API 4864 extern __checkReturn efx_rc_t 4865 efx_mae_action_set_fill_in_counter_id( 4866 __in efx_mae_actions_t *spec, 4867 __in const efx_counter_t *counter_idp); 4868 4869 /* 4870 * Clears dangling FW object IDs (counter ID, for instance) in 4871 * the action set specification. Useful for adapter restarts, 4872 * when all MAE objects need to be reallocated by the driver. 4873 * 4874 * This method only clears the IDs in the specification. 4875 * The driver is still responsible for keeping the IDs 4876 * separately and freeing them when stopping the port. 4877 */ 4878 LIBEFX_API 4879 extern void 4880 efx_mae_action_set_clear_fw_rsrc_ids( 4881 __in efx_mae_actions_t *spec); 4882 4883 /* Action set ID */ 4884 typedef struct efx_mae_aset_id_s { 4885 uint32_t id; 4886 } efx_mae_aset_id_t; 4887 4888 LIBEFX_API 4889 extern __checkReturn efx_rc_t 4890 efx_mae_action_set_alloc( 4891 __in efx_nic_t *enp, 4892 __in const efx_mae_actions_t *spec, 4893 __out efx_mae_aset_id_t *aset_idp); 4894 4895 /* 4896 * Allocates MAE counter(s) of type EFX_COUNTER_TYPE_ACTION. 4897 * 4898 * Generation count has two purposes: 4899 * 4900 * 1) Distinguish between counter packets that belong to freed counter 4901 * and the packets that belong to reallocated counter (with the same ID); 4902 * 2) Make sure that all packets are received for a counter that was freed; 4903 * 4904 * API users should provide generation count out parameter in allocation 4905 * function if counters can be reallocated and consistent counter values are 4906 * required. 4907 * 4908 * API users that need consistent final counter values after counter 4909 * deallocation or counter stream stop should provide the parameter in 4910 * functions that free the counters and stop the counter stream. 4911 */ 4912 LIBEFX_API 4913 extern __checkReturn efx_rc_t 4914 efx_mae_counters_alloc( 4915 __in efx_nic_t *enp, 4916 __in uint32_t n_counters, 4917 __out uint32_t *n_allocatedp, 4918 __out_ecount(n_counters) efx_counter_t *countersp, 4919 __out_opt uint32_t *gen_countp); 4920 4921 /* 4922 * Allocates MAE counter(s) of the specified type. Other 4923 * than that, behaves like efx_mae_counters_alloc(). 4924 */ 4925 LIBEFX_API 4926 extern __checkReturn efx_rc_t 4927 efx_mae_counters_alloc_type( 4928 __in efx_nic_t *enp, 4929 __in efx_counter_type_t type, 4930 __in uint32_t n_counters, 4931 __out uint32_t *n_allocatedp, 4932 __out_ecount(n_counters) efx_counter_t *countersp, 4933 __out_opt uint32_t *gen_countp); 4934 4935 LIBEFX_API 4936 extern __checkReturn efx_rc_t 4937 efx_mae_counters_free( 4938 __in efx_nic_t *enp, 4939 __in uint32_t n_counters, 4940 __out uint32_t *n_freedp, 4941 __in_ecount(n_counters) const efx_counter_t *countersp, 4942 __out_opt uint32_t *gen_countp); 4943 4944 LIBEFX_API 4945 extern __checkReturn efx_rc_t 4946 efx_mae_counters_free_type( 4947 __in efx_nic_t *enp, 4948 __in efx_counter_type_t type, 4949 __in uint32_t n_counters, 4950 __out uint32_t *n_freedp, 4951 __in_ecount(n_counters) const efx_counter_t *countersp, 4952 __out_opt uint32_t *gen_countp); 4953 4954 /* When set, include counters with a value of zero */ 4955 #define EFX_MAE_COUNTERS_STREAM_IN_ZERO_SQUASH_DISABLE (1U << 0) 4956 4957 /* 4958 * Set if credit-based flow control is used. In this case the driver 4959 * must call efx_mae_counters_stream_give_credits() to notify the 4960 * packetiser of descriptors written. 4961 */ 4962 #define EFX_MAE_COUNTERS_STREAM_OUT_USES_CREDITS (1U << 0) 4963 4964 LIBEFX_API 4965 extern __checkReturn efx_rc_t 4966 efx_mae_counters_stream_start( 4967 __in efx_nic_t *enp, 4968 __in uint16_t rxq_id, 4969 __in uint16_t packet_size, 4970 __in uint32_t flags_in, 4971 __out uint32_t *flags_out); 4972 4973 LIBEFX_API 4974 extern __checkReturn efx_rc_t 4975 efx_mae_counters_stream_stop( 4976 __in efx_nic_t *enp, 4977 __in uint16_t rxq_id, 4978 __out_opt uint32_t *gen_countp); 4979 4980 LIBEFX_API 4981 extern __checkReturn efx_rc_t 4982 efx_mae_counters_stream_give_credits( 4983 __in efx_nic_t *enp, 4984 __in uint32_t n_credits); 4985 4986 LIBEFX_API 4987 extern __checkReturn efx_rc_t 4988 efx_mae_action_set_free( 4989 __in efx_nic_t *enp, 4990 __in const efx_mae_aset_id_t *aset_idp); 4991 4992 /* Action set list ID */ 4993 typedef struct efx_mae_aset_list_id_s { 4994 uint32_t id; 4995 } efx_mae_aset_list_id_t; 4996 4997 /* 4998 * Either action set list ID or action set ID must be passed to this API, 4999 * but not both. 5000 */ 5001 LIBEFX_API 5002 extern __checkReturn efx_rc_t 5003 efx_mae_action_rule_insert( 5004 __in efx_nic_t *enp, 5005 __in const efx_mae_match_spec_t *spec, 5006 __in const efx_mae_aset_list_id_t *asl_idp, 5007 __in const efx_mae_aset_id_t *as_idp, 5008 __out efx_mae_rule_id_t *ar_idp); 5009 5010 LIBEFX_API 5011 extern __checkReturn efx_rc_t 5012 efx_mae_action_rule_remove( 5013 __in efx_nic_t *enp, 5014 __in const efx_mae_rule_id_t *ar_idp); 5015 5016 LIBEFX_API 5017 extern __checkReturn efx_rc_t 5018 efx_mcdi_mport_alloc_alias( 5019 __in efx_nic_t *enp, 5020 __out efx_mport_id_t *mportp, 5021 __out_opt uint32_t *labelp); 5022 5023 LIBEFX_API 5024 extern __checkReturn efx_rc_t 5025 efx_mae_mport_free( 5026 __in efx_nic_t *enp, 5027 __in const efx_mport_id_t *mportp); 5028 5029 typedef __checkReturn efx_rc_t 5030 (efx_mae_read_mport_journal_cb)( 5031 __in void *cb_datap, 5032 __in efx_mport_desc_t *mportp, 5033 __in size_t mport_len); 5034 5035 /* 5036 * Read mport descriptions from the MAE journal (which describes added and 5037 * removed mports) and pass them to a user-supplied callback. The user gets 5038 * only one chance to process the data it's given. Once the callback function 5039 * finishes, that particular mport description will be gone. 5040 * The journal will be fully repopulated on PCI reset (efx_nic_reset function). 5041 */ 5042 LIBEFX_API 5043 extern __checkReturn efx_rc_t 5044 efx_mae_read_mport_journal( 5045 __in efx_nic_t *enp, 5046 __in efx_mae_read_mport_journal_cb *cbp, 5047 __in void *cb_datap); 5048 5049 #endif /* EFSYS_OPT_MAE */ 5050 5051 #if EFSYS_OPT_VIRTIO 5052 5053 /* A Virtio net device can have one or more pairs of Rx/Tx virtqueues 5054 * while virtio block device has a single virtqueue, 5055 * for further details refer section of 4.2.3 of SF-120734 5056 */ 5057 typedef enum efx_virtio_vq_type_e { 5058 EFX_VIRTIO_VQ_TYPE_NET_RXQ, 5059 EFX_VIRTIO_VQ_TYPE_NET_TXQ, 5060 EFX_VIRTIO_VQ_TYPE_BLOCK, 5061 EFX_VIRTIO_VQ_NTYPES 5062 } efx_virtio_vq_type_t; 5063 5064 typedef struct efx_virtio_vq_dyncfg_s { 5065 /* 5066 * If queue is being created to be migrated then this should be 5067 * the FINAL_AVAIL_IDX value returned by MC_CMD_VIRTIO_FINI_QUEUE 5068 * of the queue being migrated from. Otherwise, it should be zero. 5069 */ 5070 uint32_t evvd_vq_avail_idx; 5071 /* 5072 * If queue is being created to be migrated then this should be 5073 * the FINAL_USED_IDX value returned by MC_CMD_VIRTIO_FINI_QUEUE 5074 * of the queue being migrated from. Otherwise, it should be zero. 5075 */ 5076 uint32_t evvd_vq_used_idx; 5077 } efx_virtio_vq_dyncfg_t; 5078 5079 /* 5080 * Virtqueue size must be a power of 2, maximum size is 32768 5081 * (see VIRTIO v1.1 section 2.6) 5082 */ 5083 #define EFX_VIRTIO_MAX_VQ_SIZE 0x8000 5084 5085 typedef struct efx_virtio_vq_cfg_s { 5086 unsigned int evvc_vq_num; 5087 efx_virtio_vq_type_t evvc_type; 5088 /* 5089 * vDPA as VF : It is target VF number if queue is being created on VF. 5090 * vDPA as PF : If queue to be created on PF then it should be 5091 * EFX_PCI_VF_INVALID. 5092 */ 5093 uint16_t evvc_target_vf; 5094 /* 5095 * Maximum virtqueue size is EFX_VIRTIO_MAX_VQ_SIZE and 5096 * virtqueue size 0 means the queue is unavailable. 5097 */ 5098 uint32_t evvc_vq_size; 5099 efsys_dma_addr_t evvc_desc_tbl_addr; 5100 efsys_dma_addr_t evvc_avail_ring_addr; 5101 efsys_dma_addr_t evvc_used_ring_addr; 5102 /* MSIX vector number for the virtqueue or 0xFFFF if MSIX is not used */ 5103 uint16_t evvc_msix_vector; 5104 /* 5105 * evvc_pas_id contains a PCIe address space identifier if the queue 5106 * uses PASID. 5107 */ 5108 boolean_t evvc_use_pasid; 5109 uint32_t evvc_pas_id; 5110 /* Negotiated virtio features to be applied to this virtqueue */ 5111 uint64_t evcc_features; 5112 } efx_virtio_vq_cfg_t; 5113 5114 typedef struct efx_virtio_vq_s efx_virtio_vq_t; 5115 5116 typedef enum efx_virtio_device_type_e { 5117 EFX_VIRTIO_DEVICE_TYPE_RESERVED, 5118 EFX_VIRTIO_DEVICE_TYPE_NET, 5119 EFX_VIRTIO_DEVICE_TYPE_BLOCK, 5120 EFX_VIRTIO_DEVICE_NTYPES 5121 } efx_virtio_device_type_t; 5122 5123 LIBEFX_API 5124 extern __checkReturn efx_rc_t 5125 efx_virtio_init( 5126 __in efx_nic_t *enp); 5127 5128 LIBEFX_API 5129 extern void 5130 efx_virtio_fini( 5131 __in efx_nic_t *enp); 5132 5133 /* 5134 * When virtio net driver in the guest sets VIRTIO_CONFIG_STATUS_DRIVER_OK bit, 5135 * hypervisor starts configuring all the virtqueues in the device. When the 5136 * vhost_user has received VHOST_USER_SET_VRING_ENABLE for all the virtqueues, 5137 * then it invokes VDPA driver callback dev_conf. APIs qstart and qcreate would 5138 * be invoked from dev_conf callback to create the virtqueues, For further 5139 * details refer SF-122427. 5140 */ 5141 LIBEFX_API 5142 extern __checkReturn efx_rc_t 5143 efx_virtio_qcreate( 5144 __in efx_nic_t *enp, 5145 __deref_out efx_virtio_vq_t **evvpp); 5146 5147 LIBEFX_API 5148 extern __checkReturn efx_rc_t 5149 efx_virtio_qstart( 5150 __in efx_virtio_vq_t *evvp, 5151 __in efx_virtio_vq_cfg_t *evvcp, 5152 __in_opt efx_virtio_vq_dyncfg_t *evvdp); 5153 5154 LIBEFX_API 5155 extern __checkReturn efx_rc_t 5156 efx_virtio_qstop( 5157 __in efx_virtio_vq_t *evvp, 5158 __out_opt efx_virtio_vq_dyncfg_t *evvdp); 5159 5160 LIBEFX_API 5161 extern void 5162 efx_virtio_qdestroy( 5163 __in efx_virtio_vq_t *evvp); 5164 5165 /* 5166 * Get the offset in the BAR of the doorbells for a VI. 5167 * net device : doorbell offset of RX & TX queues 5168 * block device : request doorbell offset in the BAR. 5169 * For further details refer section of 4 of SF-119689 5170 */ 5171 LIBEFX_API 5172 extern __checkReturn efx_rc_t 5173 efx_virtio_get_doorbell_offset( 5174 __in efx_virtio_vq_t *evvp, 5175 __out uint32_t *offsetp); 5176 5177 LIBEFX_API 5178 extern __checkReturn efx_rc_t 5179 efx_virtio_get_features( 5180 __in efx_nic_t *enp, 5181 __in efx_virtio_device_type_t type, 5182 __out uint64_t *featuresp); 5183 5184 LIBEFX_API 5185 extern __checkReturn efx_rc_t 5186 efx_virtio_verify_features( 5187 __in efx_nic_t *enp, 5188 __in efx_virtio_device_type_t type, 5189 __in uint64_t features); 5190 5191 #endif /* EFSYS_OPT_VIRTIO */ 5192 5193 LIBEFX_API 5194 extern __checkReturn efx_rc_t 5195 efx_nic_dma_config_add( 5196 __in efx_nic_t *enp, 5197 __in efsys_dma_addr_t trgt_addr, 5198 __in size_t len, 5199 __out_opt efsys_dma_addr_t *nic_basep, 5200 __out_opt efsys_dma_addr_t *trgt_basep, 5201 __out_opt size_t *map_lenp); 5202 5203 LIBEFX_API 5204 extern __checkReturn efx_rc_t 5205 efx_nic_dma_reconfigure( 5206 __in efx_nic_t *enp); 5207 5208 typedef enum efx_nic_dma_addr_type_e { 5209 EFX_NIC_DMA_ADDR_MCDI_BUF, 5210 EFX_NIC_DMA_ADDR_MAC_STATS_BUF, 5211 EFX_NIC_DMA_ADDR_EVENT_RING, 5212 EFX_NIC_DMA_ADDR_RX_RING, 5213 EFX_NIC_DMA_ADDR_TX_RING, 5214 EFX_NIC_DMA_ADDR_RX_BUF, 5215 EFX_NIC_DMA_ADDR_TX_BUF, 5216 5217 EFX_NIC_DMA_ADDR_NTYPES 5218 } efx_nic_dma_addr_type_t; 5219 5220 LIBEFX_API 5221 extern __checkReturn efx_rc_t 5222 efx_nic_dma_map( 5223 __in efx_nic_t *enp, 5224 __in efx_nic_dma_addr_type_t addr_type, 5225 __in efsys_dma_addr_t tgt_addr, 5226 __in size_t len, 5227 __out efsys_dma_addr_t *nic_addrp); 5228 5229 /* Unique IDs for HW tables */ 5230 typedef enum efx_table_id_e { 5231 EFX_TABLE_ID_CONNTRACK = 0x10300, 5232 } efx_table_id_t; 5233 5234 LIBEFX_API 5235 extern __checkReturn efx_rc_t 5236 efx_table_list( 5237 __in efx_nic_t *enp, 5238 __in uint32_t entry_ofst, 5239 __out_opt unsigned int *total_n_tablesp, 5240 __out_ecount_opt(n_table_ids) efx_table_id_t *table_ids, 5241 __in unsigned int n_table_ids, 5242 __out_opt unsigned int *n_table_ids_writtenp); 5243 5244 LIBEFX_API 5245 extern __checkReturn size_t 5246 efx_table_supported_num_get( 5247 __in void); 5248 5249 LIBEFX_API 5250 extern __checkReturn boolean_t 5251 efx_table_is_supported( 5252 __in efx_table_id_t table_id); 5253 5254 /* Unique IDs for table fields */ 5255 typedef enum efx_table_field_id_e { 5256 EFX_TABLE_FIELD_ID_UNUSED = 0x0, 5257 EFX_TABLE_FIELD_ID_COUNTER_ID = 0xa, 5258 EFX_TABLE_FIELD_ID_ETHER_TYPE = 0x1c, 5259 EFX_TABLE_FIELD_ID_SRC_IP = 0x1d, 5260 EFX_TABLE_FIELD_ID_DST_IP = 0x1e, 5261 EFX_TABLE_FIELD_ID_IP_PROTO = 0x20, 5262 EFX_TABLE_FIELD_ID_SRC_PORT = 0x21, 5263 EFX_TABLE_FIELD_ID_DST_PORT = 0x22, 5264 EFX_TABLE_FIELD_ID_NAT_PORT = 0x7a, 5265 EFX_TABLE_FIELD_ID_NAT_IP = 0x7b, 5266 EFX_TABLE_FIELD_ID_NAT_DIR = 0x7c, 5267 EFX_TABLE_FIELD_ID_CT_MARK = 0x7d, 5268 } efx_table_field_id_t; 5269 5270 /* Table fields mask types */ 5271 typedef enum efx_table_field_mask_type_e { 5272 EFX_TABLE_FIELD_MASK_NEVER = 0x0, 5273 EFX_TABLE_FIELD_MASK_EXACT = 0x1, 5274 } efx_table_field_mask_type_t; 5275 5276 typedef struct efx_table_field_desc_s { 5277 efx_table_field_id_t field_id; 5278 uint16_t lbn; 5279 uint16_t width; 5280 efx_table_field_mask_type_t mask_type; 5281 uint8_t scheme; 5282 } efx_table_field_descriptor_t; 5283 5284 /* Types of HW tables */ 5285 typedef enum efx_table_type_e { 5286 /* Exact match to all key fields of table entry. */ 5287 EFX_TABLE_TYPE_BCAM = 0x2, 5288 } efx_table_type_t; 5289 5290 typedef struct efx_table_descriptor_s { 5291 efx_table_type_t type; 5292 uint16_t key_width; 5293 uint16_t resp_width; 5294 /* Number of key's fields to match data */ 5295 uint16_t n_key_fields; 5296 /* Number of fields in match response */ 5297 uint16_t n_resp_fields; 5298 } efx_table_descriptor_t; 5299 5300 LIBEFX_API 5301 extern __checkReturn efx_rc_t 5302 efx_table_describe( 5303 __in efx_nic_t *enp, 5304 __in efx_table_id_t table_id, 5305 __in uint32_t field_offset, 5306 __out_opt efx_table_descriptor_t *table_descp, 5307 __out_ecount_opt(n_field_descs) efx_table_field_descriptor_t *fields_descs, 5308 __in unsigned int n_field_descs, 5309 __out_opt unsigned int *n_field_descs_writtenp); 5310 5311 /* Maximum possible size of data for manipulation of the tables */ 5312 #define EFX_TABLE_ENTRY_LENGTH_MAX 1008 5313 5314 LIBEFX_API 5315 extern __checkReturn efx_rc_t 5316 efx_table_entry_insert( 5317 __in efx_nic_t *enp, 5318 __in efx_table_id_t table_id, 5319 __in uint16_t priority, 5320 __in uint16_t mask_id, 5321 __in uint16_t key_width, 5322 __in uint16_t mask_width, 5323 __in uint16_t resp_width, 5324 __in_bcount(data_size) uint8_t *entry_datap, 5325 __in unsigned int data_size); 5326 5327 LIBEFX_API 5328 extern __checkReturn efx_rc_t 5329 efx_table_entry_delete( 5330 __in efx_nic_t *enp, 5331 __in efx_table_id_t table_id, 5332 __in uint16_t mask_id, 5333 __in uint16_t key_width, 5334 __in uint16_t mask_width, 5335 __in_bcount(data_size) uint8_t *entry_datap, 5336 __in unsigned int data_size); 5337 5338 /* 5339 * Clone the given MAE action set specification 5340 * and drop actions COUNT and DELIVER from it. 5341 */ 5342 LIBEFX_API 5343 extern __checkReturn efx_rc_t 5344 efx_mae_action_set_replay( 5345 __in efx_nic_t *enp, 5346 __in const efx_mae_actions_t *spec_orig, 5347 __out efx_mae_actions_t **spec_clonep); 5348 5349 /* 5350 * The actual limit may be lower than this. 5351 * This define merely limits the number of 5352 * entries in a single allocation request. 5353 */ 5354 #define EFX_MAE_ACTION_SET_LIST_MAX_NENTRIES 254 5355 5356 LIBEFX_API 5357 extern __checkReturn efx_rc_t 5358 efx_mae_action_set_list_alloc( 5359 __in efx_nic_t *enp, 5360 __in unsigned int n_asets, 5361 __in_ecount(n_asets) const efx_mae_aset_id_t *aset_ids, 5362 __out efx_mae_aset_list_id_t *aset_list_idp); 5363 5364 LIBEFX_API 5365 extern __checkReturn efx_rc_t 5366 efx_mae_action_set_list_free( 5367 __in efx_nic_t *enp, 5368 __in const efx_mae_aset_list_id_t *aset_list_idp); 5369 5370 #ifdef __cplusplus 5371 } 5372 #endif 5373 5374 #endif /* _SYS_EFX_H */ 5375