1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2019-2020 Xilinx, Inc. 4 * Copyright(c) 2006-2019 Solarflare Communications Inc. 5 */ 6 7 #ifndef _SYS_EFX_H 8 #define _SYS_EFX_H 9 10 #include "efx_annote.h" 11 #include "efsys.h" 12 #include "efx_types.h" 13 #include "efx_check.h" 14 #include "efx_phy_ids.h" 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #define EFX_STATIC_ASSERT(_cond) \ 21 ((void)sizeof (char[(_cond) ? 1 : -1])) 22 23 #define EFX_ARRAY_SIZE(_array) \ 24 (sizeof (_array) / sizeof ((_array)[0])) 25 26 #define EFX_FIELD_OFFSET(_type, _field) \ 27 ((size_t)&(((_type *)0)->_field)) 28 29 /* The macro expands divider twice */ 30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d)) 31 32 /* Round value up to the nearest power of two. */ 33 #define EFX_P2ROUNDUP(_type, _value, _align) \ 34 (-(-(_type)(_value) & -(_type)(_align))) 35 36 /* Align value down to the nearest power of two. */ 37 #define EFX_P2ALIGN(_type, _value, _align) \ 38 ((_type)(_value) & -(_type)(_align)) 39 40 /* Test if value is power of 2 aligned. */ 41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \ 42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0) 43 44 /* Return codes */ 45 46 typedef __success(return == 0) int efx_rc_t; 47 48 49 /* Chip families */ 50 51 typedef enum efx_family_e { 52 EFX_FAMILY_INVALID, 53 EFX_FAMILY_FALCON, /* Obsolete and not supported */ 54 EFX_FAMILY_SIENA, 55 EFX_FAMILY_HUNTINGTON, 56 EFX_FAMILY_MEDFORD, 57 EFX_FAMILY_MEDFORD2, 58 EFX_FAMILY_RIVERHEAD, 59 EFX_FAMILY_NTYPES 60 } efx_family_t; 61 62 typedef enum efx_bar_type_e { 63 EFX_BAR_TYPE_MEM, 64 EFX_BAR_TYPE_IO 65 } efx_bar_type_t; 66 67 typedef struct efx_bar_region_s { 68 efx_bar_type_t ebr_type; 69 int ebr_index; 70 efsys_dma_addr_t ebr_offset; 71 efsys_dma_addr_t ebr_length; 72 } efx_bar_region_t; 73 74 /* The function is deprecated. It is used only if Riverhead is not supported. */ 75 LIBEFX_API 76 extern __checkReturn efx_rc_t 77 efx_family( 78 __in uint16_t venid, 79 __in uint16_t devid, 80 __out efx_family_t *efp, 81 __out unsigned int *membarp); 82 83 #if EFSYS_OPT_PCI 84 85 typedef struct efx_pci_ops_s { 86 /* 87 * Function for reading PCIe configuration space. 88 * 89 * espcp System-specific PCIe device handle; 90 * offset Offset inside PCIe configuration space to start reading 91 * from; 92 * edp EFX DWORD structure that should be populated by function 93 * in little-endian order; 94 * 95 * Returns status code, 0 on success, any other value on error. 96 */ 97 efx_rc_t (*epo_config_readd)(efsys_pci_config_t *espcp, 98 uint32_t offset, efx_dword_t *edp); 99 /* 100 * Function for finding PCIe memory bar handle by its index from a PCIe 101 * device handle. The found memory bar is available in read-only mode. 102 * 103 * configp System-specific PCIe device handle; 104 * index Memory bar index; 105 * memp Pointer to the found memory bar handle; 106 * 107 * Returns status code, 0 on success, any other value on error. 108 */ 109 efx_rc_t (*epo_find_mem_bar)(efsys_pci_config_t *configp, 110 int index, efsys_bar_t *memp); 111 } efx_pci_ops_t; 112 113 /* Determine EFX family and perform lookup of the function control window 114 * 115 * The function requires PCI config handle from which all memory bars can 116 * be accessed. 117 * A user of the API must be aware of memory bars indexes (not available 118 * on Windows). 119 */ 120 LIBEFX_API 121 extern __checkReturn efx_rc_t 122 efx_family_probe_bar( 123 __in uint16_t venid, 124 __in uint16_t devid, 125 __in efsys_pci_config_t *espcp, 126 __in const efx_pci_ops_t *epop, 127 __out efx_family_t *efp, 128 __out efx_bar_region_t *ebrp); 129 130 #endif /* EFSYS_OPT_PCI */ 131 132 133 #define EFX_PCI_VENID_SFC 0x1924 134 #define EFX_PCI_VENID_XILINX 0x10EE 135 136 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */ 137 138 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */ 139 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */ 140 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810 141 142 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901 143 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */ 144 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */ 145 146 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */ 147 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */ 148 149 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913 150 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */ 151 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */ 152 153 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13 154 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */ 155 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */ 156 157 #define EFX_PCI_DEVID_RIVERHEAD 0x0100 158 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100 159 160 #define EFX_MEM_BAR_SIENA 2 161 162 #define EFX_MEM_BAR_HUNTINGTON_PF 2 163 #define EFX_MEM_BAR_HUNTINGTON_VF 0 164 165 #define EFX_MEM_BAR_MEDFORD_PF 2 166 #define EFX_MEM_BAR_MEDFORD_VF 0 167 168 #define EFX_MEM_BAR_MEDFORD2 0 169 170 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */ 171 #define EFX_MEM_BAR_RIVERHEAD 2 172 173 174 /* Error codes */ 175 176 enum { 177 EFX_ERR_INVALID, 178 EFX_ERR_SRAM_OOB, 179 EFX_ERR_BUFID_DC_OOB, 180 EFX_ERR_MEM_PERR, 181 EFX_ERR_RBUF_OWN, 182 EFX_ERR_TBUF_OWN, 183 EFX_ERR_RDESQ_OWN, 184 EFX_ERR_TDESQ_OWN, 185 EFX_ERR_EVQ_OWN, 186 EFX_ERR_EVFF_OFLO, 187 EFX_ERR_ILL_ADDR, 188 EFX_ERR_SRAM_PERR, 189 EFX_ERR_NCODES 190 }; 191 192 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */ 193 LIBEFX_API 194 extern __checkReturn uint32_t 195 efx_crc32_calculate( 196 __in uint32_t crc_init, 197 __in_ecount(length) uint8_t const *input, 198 __in int length); 199 200 201 /* Type prototypes */ 202 203 typedef struct efx_rxq_s efx_rxq_t; 204 205 /* NIC */ 206 207 typedef struct efx_nic_s efx_nic_t; 208 209 LIBEFX_API 210 extern __checkReturn efx_rc_t 211 efx_nic_create( 212 __in efx_family_t family, 213 __in efsys_identifier_t *esip, 214 __in efsys_bar_t *esbp, 215 __in uint32_t fcw_offset, 216 __in efsys_lock_t *eslp, 217 __deref_out efx_nic_t **enpp); 218 219 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */ 220 typedef enum efx_fw_variant_e { 221 EFX_FW_VARIANT_FULL_FEATURED, 222 EFX_FW_VARIANT_LOW_LATENCY, 223 EFX_FW_VARIANT_PACKED_STREAM, 224 EFX_FW_VARIANT_HIGH_TX_RATE, 225 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1, 226 EFX_FW_VARIANT_RULES_ENGINE, 227 EFX_FW_VARIANT_DPDK, 228 EFX_FW_VARIANT_DONT_CARE = 0xffffffff 229 } efx_fw_variant_t; 230 231 LIBEFX_API 232 extern __checkReturn efx_rc_t 233 efx_nic_probe( 234 __in efx_nic_t *enp, 235 __in efx_fw_variant_t efv); 236 237 LIBEFX_API 238 extern __checkReturn efx_rc_t 239 efx_nic_init( 240 __in efx_nic_t *enp); 241 242 LIBEFX_API 243 extern __checkReturn efx_rc_t 244 efx_nic_reset( 245 __in efx_nic_t *enp); 246 247 LIBEFX_API 248 extern __checkReturn boolean_t 249 efx_nic_hw_unavailable( 250 __in efx_nic_t *enp); 251 252 LIBEFX_API 253 extern void 254 efx_nic_set_hw_unavailable( 255 __in efx_nic_t *enp); 256 257 #if EFSYS_OPT_DIAG 258 259 LIBEFX_API 260 extern __checkReturn efx_rc_t 261 efx_nic_register_test( 262 __in efx_nic_t *enp); 263 264 #endif /* EFSYS_OPT_DIAG */ 265 266 LIBEFX_API 267 extern void 268 efx_nic_fini( 269 __in efx_nic_t *enp); 270 271 LIBEFX_API 272 extern void 273 efx_nic_unprobe( 274 __in efx_nic_t *enp); 275 276 LIBEFX_API 277 extern void 278 efx_nic_destroy( 279 __in efx_nic_t *enp); 280 281 #define EFX_PCIE_LINK_SPEED_GEN1 1 282 #define EFX_PCIE_LINK_SPEED_GEN2 2 283 #define EFX_PCIE_LINK_SPEED_GEN3 3 284 285 typedef enum efx_pcie_link_performance_e { 286 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH, 287 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH, 288 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY, 289 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL 290 } efx_pcie_link_performance_t; 291 292 LIBEFX_API 293 extern __checkReturn efx_rc_t 294 efx_nic_calculate_pcie_link_bandwidth( 295 __in uint32_t pcie_link_width, 296 __in uint32_t pcie_link_gen, 297 __out uint32_t *bandwidth_mbpsp); 298 299 LIBEFX_API 300 extern __checkReturn efx_rc_t 301 efx_nic_check_pcie_link_speed( 302 __in efx_nic_t *enp, 303 __in uint32_t pcie_link_width, 304 __in uint32_t pcie_link_gen, 305 __out efx_pcie_link_performance_t *resultp); 306 307 #if EFSYS_OPT_MCDI 308 309 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 310 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */ 311 #define WITH_MCDI_V2 1 312 #endif 313 314 typedef struct efx_mcdi_req_s efx_mcdi_req_t; 315 316 typedef enum efx_mcdi_exception_e { 317 EFX_MCDI_EXCEPTION_MC_REBOOT, 318 EFX_MCDI_EXCEPTION_MC_BADASSERT, 319 } efx_mcdi_exception_t; 320 321 #if EFSYS_OPT_MCDI_LOGGING 322 typedef enum efx_log_msg_e { 323 EFX_LOG_INVALID, 324 EFX_LOG_MCDI_REQUEST, 325 EFX_LOG_MCDI_RESPONSE, 326 } efx_log_msg_t; 327 #endif /* EFSYS_OPT_MCDI_LOGGING */ 328 329 typedef struct efx_mcdi_transport_s { 330 void *emt_context; 331 efsys_mem_t *emt_dma_mem; 332 void (*emt_execute)(void *, efx_mcdi_req_t *); 333 void (*emt_ev_cpl)(void *); 334 void (*emt_exception)(void *, efx_mcdi_exception_t); 335 #if EFSYS_OPT_MCDI_LOGGING 336 void (*emt_logger)(void *, efx_log_msg_t, 337 void *, size_t, void *, size_t); 338 #endif /* EFSYS_OPT_MCDI_LOGGING */ 339 #if EFSYS_OPT_MCDI_PROXY_AUTH 340 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t); 341 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */ 342 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 343 void (*emt_ev_proxy_request)(void *, uint32_t); 344 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 345 } efx_mcdi_transport_t; 346 347 LIBEFX_API 348 extern __checkReturn efx_rc_t 349 efx_mcdi_init( 350 __in efx_nic_t *enp, 351 __in const efx_mcdi_transport_t *mtp); 352 353 LIBEFX_API 354 extern __checkReturn efx_rc_t 355 efx_mcdi_reboot( 356 __in efx_nic_t *enp); 357 358 LIBEFX_API 359 extern void 360 efx_mcdi_new_epoch( 361 __in efx_nic_t *enp); 362 363 LIBEFX_API 364 extern void 365 efx_mcdi_get_timeout( 366 __in efx_nic_t *enp, 367 __in efx_mcdi_req_t *emrp, 368 __out uint32_t *usec_timeoutp); 369 370 LIBEFX_API 371 extern void 372 efx_mcdi_request_start( 373 __in efx_nic_t *enp, 374 __in efx_mcdi_req_t *emrp, 375 __in boolean_t ev_cpl); 376 377 LIBEFX_API 378 extern __checkReturn boolean_t 379 efx_mcdi_request_poll( 380 __in efx_nic_t *enp); 381 382 LIBEFX_API 383 extern __checkReturn boolean_t 384 efx_mcdi_request_abort( 385 __in efx_nic_t *enp); 386 387 LIBEFX_API 388 extern void 389 efx_mcdi_fini( 390 __in efx_nic_t *enp); 391 392 #endif /* EFSYS_OPT_MCDI */ 393 394 /* INTR */ 395 396 #define EFX_NINTR_SIENA 1024 397 398 typedef enum efx_intr_type_e { 399 EFX_INTR_INVALID = 0, 400 EFX_INTR_LINE, 401 EFX_INTR_MESSAGE, 402 EFX_INTR_NTYPES 403 } efx_intr_type_t; 404 405 #define EFX_INTR_SIZE (sizeof (efx_oword_t)) 406 407 LIBEFX_API 408 extern __checkReturn efx_rc_t 409 efx_intr_init( 410 __in efx_nic_t *enp, 411 __in efx_intr_type_t type, 412 __in_opt efsys_mem_t *esmp); 413 414 LIBEFX_API 415 extern void 416 efx_intr_enable( 417 __in efx_nic_t *enp); 418 419 LIBEFX_API 420 extern void 421 efx_intr_disable( 422 __in efx_nic_t *enp); 423 424 LIBEFX_API 425 extern void 426 efx_intr_disable_unlocked( 427 __in efx_nic_t *enp); 428 429 #define EFX_INTR_NEVQS 32 430 431 LIBEFX_API 432 extern __checkReturn efx_rc_t 433 efx_intr_trigger( 434 __in efx_nic_t *enp, 435 __in unsigned int level); 436 437 LIBEFX_API 438 extern void 439 efx_intr_status_line( 440 __in efx_nic_t *enp, 441 __out boolean_t *fatalp, 442 __out uint32_t *maskp); 443 444 LIBEFX_API 445 extern void 446 efx_intr_status_message( 447 __in efx_nic_t *enp, 448 __in unsigned int message, 449 __out boolean_t *fatalp); 450 451 LIBEFX_API 452 extern void 453 efx_intr_fatal( 454 __in efx_nic_t *enp); 455 456 LIBEFX_API 457 extern void 458 efx_intr_fini( 459 __in efx_nic_t *enp); 460 461 /* MAC */ 462 463 #if EFSYS_OPT_MAC_STATS 464 465 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */ 466 typedef enum efx_mac_stat_e { 467 EFX_MAC_RX_OCTETS, 468 EFX_MAC_RX_PKTS, 469 EFX_MAC_RX_UNICST_PKTS, 470 EFX_MAC_RX_MULTICST_PKTS, 471 EFX_MAC_RX_BRDCST_PKTS, 472 EFX_MAC_RX_PAUSE_PKTS, 473 EFX_MAC_RX_LE_64_PKTS, 474 EFX_MAC_RX_65_TO_127_PKTS, 475 EFX_MAC_RX_128_TO_255_PKTS, 476 EFX_MAC_RX_256_TO_511_PKTS, 477 EFX_MAC_RX_512_TO_1023_PKTS, 478 EFX_MAC_RX_1024_TO_15XX_PKTS, 479 EFX_MAC_RX_GE_15XX_PKTS, 480 EFX_MAC_RX_ERRORS, 481 EFX_MAC_RX_FCS_ERRORS, 482 EFX_MAC_RX_DROP_EVENTS, 483 EFX_MAC_RX_FALSE_CARRIER_ERRORS, 484 EFX_MAC_RX_SYMBOL_ERRORS, 485 EFX_MAC_RX_ALIGN_ERRORS, 486 EFX_MAC_RX_INTERNAL_ERRORS, 487 EFX_MAC_RX_JABBER_PKTS, 488 EFX_MAC_RX_LANE0_CHAR_ERR, 489 EFX_MAC_RX_LANE1_CHAR_ERR, 490 EFX_MAC_RX_LANE2_CHAR_ERR, 491 EFX_MAC_RX_LANE3_CHAR_ERR, 492 EFX_MAC_RX_LANE0_DISP_ERR, 493 EFX_MAC_RX_LANE1_DISP_ERR, 494 EFX_MAC_RX_LANE2_DISP_ERR, 495 EFX_MAC_RX_LANE3_DISP_ERR, 496 EFX_MAC_RX_MATCH_FAULT, 497 EFX_MAC_RX_NODESC_DROP_CNT, 498 EFX_MAC_TX_OCTETS, 499 EFX_MAC_TX_PKTS, 500 EFX_MAC_TX_UNICST_PKTS, 501 EFX_MAC_TX_MULTICST_PKTS, 502 EFX_MAC_TX_BRDCST_PKTS, 503 EFX_MAC_TX_PAUSE_PKTS, 504 EFX_MAC_TX_LE_64_PKTS, 505 EFX_MAC_TX_65_TO_127_PKTS, 506 EFX_MAC_TX_128_TO_255_PKTS, 507 EFX_MAC_TX_256_TO_511_PKTS, 508 EFX_MAC_TX_512_TO_1023_PKTS, 509 EFX_MAC_TX_1024_TO_15XX_PKTS, 510 EFX_MAC_TX_GE_15XX_PKTS, 511 EFX_MAC_TX_ERRORS, 512 EFX_MAC_TX_SGL_COL_PKTS, 513 EFX_MAC_TX_MULT_COL_PKTS, 514 EFX_MAC_TX_EX_COL_PKTS, 515 EFX_MAC_TX_LATE_COL_PKTS, 516 EFX_MAC_TX_DEF_PKTS, 517 EFX_MAC_TX_EX_DEF_PKTS, 518 EFX_MAC_PM_TRUNC_BB_OVERFLOW, 519 EFX_MAC_PM_DISCARD_BB_OVERFLOW, 520 EFX_MAC_PM_TRUNC_VFIFO_FULL, 521 EFX_MAC_PM_DISCARD_VFIFO_FULL, 522 EFX_MAC_PM_TRUNC_QBB, 523 EFX_MAC_PM_DISCARD_QBB, 524 EFX_MAC_PM_DISCARD_MAPPING, 525 EFX_MAC_RXDP_Q_DISABLED_PKTS, 526 EFX_MAC_RXDP_DI_DROPPED_PKTS, 527 EFX_MAC_RXDP_STREAMING_PKTS, 528 EFX_MAC_RXDP_HLB_FETCH, 529 EFX_MAC_RXDP_HLB_WAIT, 530 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS, 531 EFX_MAC_VADAPTER_RX_UNICAST_BYTES, 532 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS, 533 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES, 534 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS, 535 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES, 536 EFX_MAC_VADAPTER_RX_BAD_PACKETS, 537 EFX_MAC_VADAPTER_RX_BAD_BYTES, 538 EFX_MAC_VADAPTER_RX_OVERFLOW, 539 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS, 540 EFX_MAC_VADAPTER_TX_UNICAST_BYTES, 541 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS, 542 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES, 543 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS, 544 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES, 545 EFX_MAC_VADAPTER_TX_BAD_PACKETS, 546 EFX_MAC_VADAPTER_TX_BAD_BYTES, 547 EFX_MAC_VADAPTER_TX_OVERFLOW, 548 EFX_MAC_FEC_UNCORRECTED_ERRORS, 549 EFX_MAC_FEC_CORRECTED_ERRORS, 550 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0, 551 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1, 552 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2, 553 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3, 554 EFX_MAC_CTPIO_VI_BUSY_FALLBACK, 555 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS, 556 EFX_MAC_CTPIO_MISSING_DBELL_FAIL, 557 EFX_MAC_CTPIO_OVERFLOW_FAIL, 558 EFX_MAC_CTPIO_UNDERFLOW_FAIL, 559 EFX_MAC_CTPIO_TIMEOUT_FAIL, 560 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL, 561 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL, 562 EFX_MAC_CTPIO_INVALID_WR_FAIL, 563 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK, 564 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK, 565 EFX_MAC_CTPIO_RUNT_FALLBACK, 566 EFX_MAC_CTPIO_SUCCESS, 567 EFX_MAC_CTPIO_FALLBACK, 568 EFX_MAC_CTPIO_POISON, 569 EFX_MAC_CTPIO_ERASE, 570 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC, 571 EFX_MAC_RXDP_HLB_IDLE, 572 EFX_MAC_RXDP_HLB_TIMEOUT, 573 EFX_MAC_NSTATS 574 } efx_mac_stat_t; 575 576 /* END MKCONFIG GENERATED EfxHeaderMacBlock */ 577 578 #endif /* EFSYS_OPT_MAC_STATS */ 579 580 typedef enum efx_link_mode_e { 581 EFX_LINK_UNKNOWN = 0, 582 EFX_LINK_DOWN, 583 EFX_LINK_10HDX, 584 EFX_LINK_10FDX, 585 EFX_LINK_100HDX, 586 EFX_LINK_100FDX, 587 EFX_LINK_1000HDX, 588 EFX_LINK_1000FDX, 589 EFX_LINK_10000FDX, 590 EFX_LINK_40000FDX, 591 EFX_LINK_25000FDX, 592 EFX_LINK_50000FDX, 593 EFX_LINK_100000FDX, 594 EFX_LINK_NMODES 595 } efx_link_mode_t; 596 597 #define EFX_MAC_ADDR_LEN 6 598 599 #define EFX_VNI_OR_VSID_LEN 3 600 601 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01) 602 603 #define EFX_MAC_MULTICAST_LIST_MAX 256 604 605 #define EFX_MAC_SDU_MAX 9202 606 607 #define EFX_MAC_PDU_ADJUSTMENT \ 608 (/* EtherII */ 14 \ 609 + /* VLAN */ 4 \ 610 + /* CRC */ 4 \ 611 + /* bug16011 */ 16) \ 612 613 #define EFX_MAC_PDU(_sdu) \ 614 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8) 615 616 /* 617 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give 618 * the SDU rounded up slightly. 619 */ 620 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT) 621 622 #define EFX_MAC_PDU_MIN 60 623 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX) 624 625 LIBEFX_API 626 extern __checkReturn efx_rc_t 627 efx_mac_pdu_get( 628 __in efx_nic_t *enp, 629 __out size_t *pdu); 630 631 LIBEFX_API 632 extern __checkReturn efx_rc_t 633 efx_mac_pdu_set( 634 __in efx_nic_t *enp, 635 __in size_t pdu); 636 637 LIBEFX_API 638 extern __checkReturn efx_rc_t 639 efx_mac_addr_set( 640 __in efx_nic_t *enp, 641 __in uint8_t *addr); 642 643 LIBEFX_API 644 extern __checkReturn efx_rc_t 645 efx_mac_filter_set( 646 __in efx_nic_t *enp, 647 __in boolean_t all_unicst, 648 __in boolean_t mulcst, 649 __in boolean_t all_mulcst, 650 __in boolean_t brdcst); 651 652 LIBEFX_API 653 extern void 654 efx_mac_filter_get_all_ucast_mcast( 655 __in efx_nic_t *enp, 656 __out boolean_t *all_unicst, 657 __out boolean_t *all_mulcst); 658 659 LIBEFX_API 660 extern __checkReturn efx_rc_t 661 efx_mac_multicast_list_set( 662 __in efx_nic_t *enp, 663 __in_ecount(6*count) uint8_t const *addrs, 664 __in int count); 665 666 LIBEFX_API 667 extern __checkReturn efx_rc_t 668 efx_mac_filter_default_rxq_set( 669 __in efx_nic_t *enp, 670 __in efx_rxq_t *erp, 671 __in boolean_t using_rss); 672 673 LIBEFX_API 674 extern void 675 efx_mac_filter_default_rxq_clear( 676 __in efx_nic_t *enp); 677 678 LIBEFX_API 679 extern __checkReturn efx_rc_t 680 efx_mac_drain( 681 __in efx_nic_t *enp, 682 __in boolean_t enabled); 683 684 LIBEFX_API 685 extern __checkReturn efx_rc_t 686 efx_mac_up( 687 __in efx_nic_t *enp, 688 __out boolean_t *mac_upp); 689 690 #define EFX_FCNTL_RESPOND 0x00000001 691 #define EFX_FCNTL_GENERATE 0x00000002 692 693 LIBEFX_API 694 extern __checkReturn efx_rc_t 695 efx_mac_fcntl_set( 696 __in efx_nic_t *enp, 697 __in unsigned int fcntl, 698 __in boolean_t autoneg); 699 700 LIBEFX_API 701 extern void 702 efx_mac_fcntl_get( 703 __in efx_nic_t *enp, 704 __out unsigned int *fcntl_wantedp, 705 __out unsigned int *fcntl_linkp); 706 707 708 #if EFSYS_OPT_MAC_STATS 709 710 #if EFSYS_OPT_NAMES 711 712 LIBEFX_API 713 extern __checkReturn const char * 714 efx_mac_stat_name( 715 __in efx_nic_t *enp, 716 __in unsigned int id); 717 718 #endif /* EFSYS_OPT_NAMES */ 719 720 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t)) 721 722 #define EFX_MAC_STATS_MASK_NPAGES \ 723 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \ 724 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \ 725 EFX_MAC_STATS_MASK_BITS_PER_PAGE) 726 727 /* 728 * Get mask of MAC statistics supported by the hardware. 729 * 730 * If mask_size is insufficient to return the mask, EINVAL error is 731 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page 732 * (which is sizeof (uint32_t)) is sufficient. 733 */ 734 LIBEFX_API 735 extern __checkReturn efx_rc_t 736 efx_mac_stats_get_mask( 737 __in efx_nic_t *enp, 738 __out_bcount(mask_size) uint32_t *maskp, 739 __in size_t mask_size); 740 741 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \ 742 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \ 743 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1)))) 744 745 746 LIBEFX_API 747 extern __checkReturn efx_rc_t 748 efx_mac_stats_clear( 749 __in efx_nic_t *enp); 750 751 /* 752 * Upload mac statistics supported by the hardware into the given buffer. 753 * 754 * The DMA buffer must be 4Kbyte aligned and sized to hold at least 755 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters. 756 * 757 * The hardware will only DMA statistics that it understands (of course). 758 * Drivers should not make any assumptions about which statistics are 759 * supported, especially when the statistics are generated by firmware. 760 * 761 * Thus, drivers should zero this buffer before use, so that not-understood 762 * statistics read back as zero. 763 */ 764 LIBEFX_API 765 extern __checkReturn efx_rc_t 766 efx_mac_stats_upload( 767 __in efx_nic_t *enp, 768 __in efsys_mem_t *esmp); 769 770 LIBEFX_API 771 extern __checkReturn efx_rc_t 772 efx_mac_stats_periodic( 773 __in efx_nic_t *enp, 774 __in efsys_mem_t *esmp, 775 __in uint16_t period_ms, 776 __in boolean_t events); 777 778 LIBEFX_API 779 extern __checkReturn efx_rc_t 780 efx_mac_stats_update( 781 __in efx_nic_t *enp, 782 __in efsys_mem_t *esmp, 783 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 784 __inout_opt uint32_t *generationp); 785 786 #endif /* EFSYS_OPT_MAC_STATS */ 787 788 /* MON */ 789 790 typedef enum efx_mon_type_e { 791 EFX_MON_INVALID = 0, 792 EFX_MON_SFC90X0, 793 EFX_MON_SFC91X0, 794 EFX_MON_SFC92X0, 795 EFX_MON_NTYPES 796 } efx_mon_type_t; 797 798 #if EFSYS_OPT_NAMES 799 800 LIBEFX_API 801 extern const char * 802 efx_mon_name( 803 __in efx_nic_t *enp); 804 805 #endif /* EFSYS_OPT_NAMES */ 806 807 LIBEFX_API 808 extern __checkReturn efx_rc_t 809 efx_mon_init( 810 __in efx_nic_t *enp); 811 812 #if EFSYS_OPT_MON_STATS 813 814 #define EFX_MON_STATS_PAGE_SIZE 0x100 815 #define EFX_MON_MASK_ELEMENT_SIZE 32 816 817 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */ 818 typedef enum efx_mon_stat_e { 819 EFX_MON_STAT_CONTROLLER_TEMP, 820 EFX_MON_STAT_PHY_COMMON_TEMP, 821 EFX_MON_STAT_CONTROLLER_COOLING, 822 EFX_MON_STAT_PHY0_TEMP, 823 EFX_MON_STAT_PHY0_COOLING, 824 EFX_MON_STAT_PHY1_TEMP, 825 EFX_MON_STAT_PHY1_COOLING, 826 EFX_MON_STAT_IN_1V0, 827 EFX_MON_STAT_IN_1V2, 828 EFX_MON_STAT_IN_1V8, 829 EFX_MON_STAT_IN_2V5, 830 EFX_MON_STAT_IN_3V3, 831 EFX_MON_STAT_IN_12V0, 832 EFX_MON_STAT_IN_1V2A, 833 EFX_MON_STAT_IN_VREF, 834 EFX_MON_STAT_OUT_VAOE, 835 EFX_MON_STAT_AOE_TEMP, 836 EFX_MON_STAT_PSU_AOE_TEMP, 837 EFX_MON_STAT_PSU_TEMP, 838 EFX_MON_STAT_FAN_0, 839 EFX_MON_STAT_FAN_1, 840 EFX_MON_STAT_FAN_2, 841 EFX_MON_STAT_FAN_3, 842 EFX_MON_STAT_FAN_4, 843 EFX_MON_STAT_IN_VAOE, 844 EFX_MON_STAT_OUT_IAOE, 845 EFX_MON_STAT_IN_IAOE, 846 EFX_MON_STAT_NIC_POWER, 847 EFX_MON_STAT_IN_0V9, 848 EFX_MON_STAT_IN_I0V9, 849 EFX_MON_STAT_IN_I1V2, 850 EFX_MON_STAT_IN_0V9_ADC, 851 EFX_MON_STAT_CONTROLLER_2_TEMP, 852 EFX_MON_STAT_VREG_INTERNAL_TEMP, 853 EFX_MON_STAT_VREG_0V9_TEMP, 854 EFX_MON_STAT_VREG_1V2_TEMP, 855 EFX_MON_STAT_CONTROLLER_VPTAT, 856 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP, 857 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC, 858 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC, 859 EFX_MON_STAT_AMBIENT_TEMP, 860 EFX_MON_STAT_AIRFLOW, 861 EFX_MON_STAT_VDD08D_VSS08D_CSR, 862 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC, 863 EFX_MON_STAT_HOTPOINT_TEMP, 864 EFX_MON_STAT_PHY_POWER_PORT0, 865 EFX_MON_STAT_PHY_POWER_PORT1, 866 EFX_MON_STAT_MUM_VCC, 867 EFX_MON_STAT_IN_0V9_A, 868 EFX_MON_STAT_IN_I0V9_A, 869 EFX_MON_STAT_VREG_0V9_A_TEMP, 870 EFX_MON_STAT_IN_0V9_B, 871 EFX_MON_STAT_IN_I0V9_B, 872 EFX_MON_STAT_VREG_0V9_B_TEMP, 873 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY, 874 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC, 875 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY, 876 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC, 877 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT, 878 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP, 879 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC, 880 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC, 881 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT, 882 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP, 883 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC, 884 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC, 885 EFX_MON_STAT_SODIMM_VOUT, 886 EFX_MON_STAT_SODIMM_0_TEMP, 887 EFX_MON_STAT_SODIMM_1_TEMP, 888 EFX_MON_STAT_PHY0_VCC, 889 EFX_MON_STAT_PHY1_VCC, 890 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP, 891 EFX_MON_STAT_BOARD_FRONT_TEMP, 892 EFX_MON_STAT_BOARD_BACK_TEMP, 893 EFX_MON_STAT_IN_I1V8, 894 EFX_MON_STAT_IN_I2V5, 895 EFX_MON_STAT_IN_I3V3, 896 EFX_MON_STAT_IN_I12V0, 897 EFX_MON_STAT_IN_1V3, 898 EFX_MON_STAT_IN_I1V3, 899 EFX_MON_NSTATS 900 } efx_mon_stat_t; 901 902 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */ 903 904 typedef enum efx_mon_stat_state_e { 905 EFX_MON_STAT_STATE_OK = 0, 906 EFX_MON_STAT_STATE_WARNING = 1, 907 EFX_MON_STAT_STATE_FATAL = 2, 908 EFX_MON_STAT_STATE_BROKEN = 3, 909 EFX_MON_STAT_STATE_NO_READING = 4, 910 } efx_mon_stat_state_t; 911 912 typedef enum efx_mon_stat_unit_e { 913 EFX_MON_STAT_UNIT_UNKNOWN = 0, 914 EFX_MON_STAT_UNIT_BOOL, 915 EFX_MON_STAT_UNIT_TEMP_C, 916 EFX_MON_STAT_UNIT_VOLTAGE_MV, 917 EFX_MON_STAT_UNIT_CURRENT_MA, 918 EFX_MON_STAT_UNIT_POWER_W, 919 EFX_MON_STAT_UNIT_RPM, 920 EFX_MON_NUNITS 921 } efx_mon_stat_unit_t; 922 923 typedef struct efx_mon_stat_value_s { 924 uint16_t emsv_value; 925 efx_mon_stat_state_t emsv_state; 926 efx_mon_stat_unit_t emsv_unit; 927 } efx_mon_stat_value_t; 928 929 typedef struct efx_mon_limit_value_s { 930 uint16_t emlv_warning_min; 931 uint16_t emlv_warning_max; 932 uint16_t emlv_fatal_min; 933 uint16_t emlv_fatal_max; 934 } efx_mon_stat_limits_t; 935 936 typedef enum efx_mon_stat_portmask_e { 937 EFX_MON_STAT_PORTMAP_NONE = 0, 938 EFX_MON_STAT_PORTMAP_PORT0 = 1, 939 EFX_MON_STAT_PORTMAP_PORT1 = 2, 940 EFX_MON_STAT_PORTMAP_PORT2 = 3, 941 EFX_MON_STAT_PORTMAP_PORT3 = 4, 942 EFX_MON_STAT_PORTMAP_ALL = (-1), 943 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2) 944 } efx_mon_stat_portmask_t; 945 946 #if EFSYS_OPT_NAMES 947 948 LIBEFX_API 949 extern const char * 950 efx_mon_stat_name( 951 __in efx_nic_t *enp, 952 __in efx_mon_stat_t id); 953 954 LIBEFX_API 955 extern const char * 956 efx_mon_stat_description( 957 __in efx_nic_t *enp, 958 __in efx_mon_stat_t id); 959 960 #endif /* EFSYS_OPT_NAMES */ 961 962 LIBEFX_API 963 extern __checkReturn boolean_t 964 efx_mon_mcdi_to_efx_stat( 965 __in int mcdi_index, 966 __out efx_mon_stat_t *statp); 967 968 LIBEFX_API 969 extern __checkReturn boolean_t 970 efx_mon_get_stat_unit( 971 __in efx_mon_stat_t stat, 972 __out efx_mon_stat_unit_t *unitp); 973 974 LIBEFX_API 975 extern __checkReturn boolean_t 976 efx_mon_get_stat_portmap( 977 __in efx_mon_stat_t stat, 978 __out efx_mon_stat_portmask_t *maskp); 979 980 LIBEFX_API 981 extern __checkReturn efx_rc_t 982 efx_mon_stats_update( 983 __in efx_nic_t *enp, 984 __in efsys_mem_t *esmp, 985 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values); 986 987 LIBEFX_API 988 extern __checkReturn efx_rc_t 989 efx_mon_limits_update( 990 __in efx_nic_t *enp, 991 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values); 992 993 #endif /* EFSYS_OPT_MON_STATS */ 994 995 LIBEFX_API 996 extern void 997 efx_mon_fini( 998 __in efx_nic_t *enp); 999 1000 /* PHY */ 1001 1002 LIBEFX_API 1003 extern __checkReturn efx_rc_t 1004 efx_phy_verify( 1005 __in efx_nic_t *enp); 1006 1007 typedef enum efx_phy_led_mode_e { 1008 EFX_PHY_LED_DEFAULT = 0, 1009 EFX_PHY_LED_OFF, 1010 EFX_PHY_LED_ON, 1011 EFX_PHY_LED_FLASH, 1012 EFX_PHY_LED_NMODES 1013 } efx_phy_led_mode_t; 1014 1015 #if EFSYS_OPT_PHY_LED_CONTROL 1016 1017 LIBEFX_API 1018 extern __checkReturn efx_rc_t 1019 efx_phy_led_set( 1020 __in efx_nic_t *enp, 1021 __in efx_phy_led_mode_t mode); 1022 1023 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1024 1025 LIBEFX_API 1026 extern __checkReturn efx_rc_t 1027 efx_port_init( 1028 __in efx_nic_t *enp); 1029 1030 #if EFSYS_OPT_LOOPBACK 1031 1032 typedef enum efx_loopback_type_e { 1033 EFX_LOOPBACK_OFF = 0, 1034 EFX_LOOPBACK_DATA = 1, 1035 EFX_LOOPBACK_GMAC = 2, 1036 EFX_LOOPBACK_XGMII = 3, 1037 EFX_LOOPBACK_XGXS = 4, 1038 EFX_LOOPBACK_XAUI = 5, 1039 EFX_LOOPBACK_GMII = 6, 1040 EFX_LOOPBACK_SGMII = 7, 1041 EFX_LOOPBACK_XGBR = 8, 1042 EFX_LOOPBACK_XFI = 9, 1043 EFX_LOOPBACK_XAUI_FAR = 10, 1044 EFX_LOOPBACK_GMII_FAR = 11, 1045 EFX_LOOPBACK_SGMII_FAR = 12, 1046 EFX_LOOPBACK_XFI_FAR = 13, 1047 EFX_LOOPBACK_GPHY = 14, 1048 EFX_LOOPBACK_PHY_XS = 15, 1049 EFX_LOOPBACK_PCS = 16, 1050 EFX_LOOPBACK_PMA_PMD = 17, 1051 EFX_LOOPBACK_XPORT = 18, 1052 EFX_LOOPBACK_XGMII_WS = 19, 1053 EFX_LOOPBACK_XAUI_WS = 20, 1054 EFX_LOOPBACK_XAUI_WS_FAR = 21, 1055 EFX_LOOPBACK_XAUI_WS_NEAR = 22, 1056 EFX_LOOPBACK_GMII_WS = 23, 1057 EFX_LOOPBACK_XFI_WS = 24, 1058 EFX_LOOPBACK_XFI_WS_FAR = 25, 1059 EFX_LOOPBACK_PHYXS_WS = 26, 1060 EFX_LOOPBACK_PMA_INT = 27, 1061 EFX_LOOPBACK_SD_NEAR = 28, 1062 EFX_LOOPBACK_SD_FAR = 29, 1063 EFX_LOOPBACK_PMA_INT_WS = 30, 1064 EFX_LOOPBACK_SD_FEP2_WS = 31, 1065 EFX_LOOPBACK_SD_FEP1_5_WS = 32, 1066 EFX_LOOPBACK_SD_FEP_WS = 33, 1067 EFX_LOOPBACK_SD_FES_WS = 34, 1068 EFX_LOOPBACK_AOE_INT_NEAR = 35, 1069 EFX_LOOPBACK_DATA_WS = 36, 1070 EFX_LOOPBACK_FORCE_EXT_LINK = 37, 1071 EFX_LOOPBACK_NTYPES 1072 } efx_loopback_type_t; 1073 1074 typedef enum efx_loopback_kind_e { 1075 EFX_LOOPBACK_KIND_OFF = 0, 1076 EFX_LOOPBACK_KIND_ALL, 1077 EFX_LOOPBACK_KIND_MAC, 1078 EFX_LOOPBACK_KIND_PHY, 1079 EFX_LOOPBACK_NKINDS 1080 } efx_loopback_kind_t; 1081 1082 LIBEFX_API 1083 extern void 1084 efx_loopback_mask( 1085 __in efx_loopback_kind_t loopback_kind, 1086 __out efx_qword_t *maskp); 1087 1088 LIBEFX_API 1089 extern __checkReturn efx_rc_t 1090 efx_port_loopback_set( 1091 __in efx_nic_t *enp, 1092 __in efx_link_mode_t link_mode, 1093 __in efx_loopback_type_t type); 1094 1095 #if EFSYS_OPT_NAMES 1096 1097 LIBEFX_API 1098 extern __checkReturn const char * 1099 efx_loopback_type_name( 1100 __in efx_nic_t *enp, 1101 __in efx_loopback_type_t type); 1102 1103 #endif /* EFSYS_OPT_NAMES */ 1104 1105 #endif /* EFSYS_OPT_LOOPBACK */ 1106 1107 LIBEFX_API 1108 extern __checkReturn efx_rc_t 1109 efx_port_poll( 1110 __in efx_nic_t *enp, 1111 __out_opt efx_link_mode_t *link_modep); 1112 1113 LIBEFX_API 1114 extern void 1115 efx_port_fini( 1116 __in efx_nic_t *enp); 1117 1118 typedef enum efx_phy_cap_type_e { 1119 EFX_PHY_CAP_INVALID = 0, 1120 EFX_PHY_CAP_10HDX, 1121 EFX_PHY_CAP_10FDX, 1122 EFX_PHY_CAP_100HDX, 1123 EFX_PHY_CAP_100FDX, 1124 EFX_PHY_CAP_1000HDX, 1125 EFX_PHY_CAP_1000FDX, 1126 EFX_PHY_CAP_10000FDX, 1127 EFX_PHY_CAP_PAUSE, 1128 EFX_PHY_CAP_ASYM, 1129 EFX_PHY_CAP_AN, 1130 EFX_PHY_CAP_40000FDX, 1131 EFX_PHY_CAP_DDM, 1132 EFX_PHY_CAP_100000FDX, 1133 EFX_PHY_CAP_25000FDX, 1134 EFX_PHY_CAP_50000FDX, 1135 EFX_PHY_CAP_BASER_FEC, 1136 EFX_PHY_CAP_BASER_FEC_REQUESTED, 1137 EFX_PHY_CAP_RS_FEC, 1138 EFX_PHY_CAP_RS_FEC_REQUESTED, 1139 EFX_PHY_CAP_25G_BASER_FEC, 1140 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED, 1141 EFX_PHY_CAP_NTYPES 1142 } efx_phy_cap_type_t; 1143 1144 1145 #define EFX_PHY_CAP_CURRENT 0x00000000 1146 #define EFX_PHY_CAP_DEFAULT 0x00000001 1147 #define EFX_PHY_CAP_PERM 0x00000002 1148 1149 LIBEFX_API 1150 extern void 1151 efx_phy_adv_cap_get( 1152 __in efx_nic_t *enp, 1153 __in uint32_t flag, 1154 __out uint32_t *maskp); 1155 1156 LIBEFX_API 1157 extern __checkReturn efx_rc_t 1158 efx_phy_adv_cap_set( 1159 __in efx_nic_t *enp, 1160 __in uint32_t mask); 1161 1162 LIBEFX_API 1163 extern void 1164 efx_phy_lp_cap_get( 1165 __in efx_nic_t *enp, 1166 __out uint32_t *maskp); 1167 1168 LIBEFX_API 1169 extern __checkReturn efx_rc_t 1170 efx_phy_oui_get( 1171 __in efx_nic_t *enp, 1172 __out uint32_t *ouip); 1173 1174 typedef enum efx_phy_media_type_e { 1175 EFX_PHY_MEDIA_INVALID = 0, 1176 EFX_PHY_MEDIA_XAUI, 1177 EFX_PHY_MEDIA_CX4, 1178 EFX_PHY_MEDIA_KX4, 1179 EFX_PHY_MEDIA_XFP, 1180 EFX_PHY_MEDIA_SFP_PLUS, 1181 EFX_PHY_MEDIA_BASE_T, 1182 EFX_PHY_MEDIA_QSFP_PLUS, 1183 EFX_PHY_MEDIA_NTYPES 1184 } efx_phy_media_type_t; 1185 1186 /* 1187 * Get the type of medium currently used. If the board has ports for 1188 * modules, a module is present, and we recognise the media type of 1189 * the module, then this will be the media type of the module. 1190 * Otherwise it will be the media type of the port. 1191 */ 1192 LIBEFX_API 1193 extern void 1194 efx_phy_media_type_get( 1195 __in efx_nic_t *enp, 1196 __out efx_phy_media_type_t *typep); 1197 1198 /* 1199 * 2-wire device address of the base information in accordance with SFF-8472 1200 * Diagnostic Monitoring Interface for Optical Transceivers section 1201 * 4 Memory Organization. 1202 */ 1203 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0 1204 1205 /* 1206 * 2-wire device address of the digital diagnostics monitoring interface 1207 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical 1208 * Transceivers section 4 Memory Organization. 1209 */ 1210 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2 1211 1212 /* 1213 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436 1214 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and 1215 * Operation. 1216 */ 1217 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0 1218 1219 /* 1220 * Maximum accessible data offset for PHY module information. 1221 */ 1222 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100 1223 1224 1225 LIBEFX_API 1226 extern __checkReturn efx_rc_t 1227 efx_phy_module_get_info( 1228 __in efx_nic_t *enp, 1229 __in uint8_t dev_addr, 1230 __in size_t offset, 1231 __in size_t len, 1232 __out_bcount(len) uint8_t *data); 1233 1234 #if EFSYS_OPT_PHY_STATS 1235 1236 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */ 1237 typedef enum efx_phy_stat_e { 1238 EFX_PHY_STAT_OUI, 1239 EFX_PHY_STAT_PMA_PMD_LINK_UP, 1240 EFX_PHY_STAT_PMA_PMD_RX_FAULT, 1241 EFX_PHY_STAT_PMA_PMD_TX_FAULT, 1242 EFX_PHY_STAT_PMA_PMD_REV_A, 1243 EFX_PHY_STAT_PMA_PMD_REV_B, 1244 EFX_PHY_STAT_PMA_PMD_REV_C, 1245 EFX_PHY_STAT_PMA_PMD_REV_D, 1246 EFX_PHY_STAT_PCS_LINK_UP, 1247 EFX_PHY_STAT_PCS_RX_FAULT, 1248 EFX_PHY_STAT_PCS_TX_FAULT, 1249 EFX_PHY_STAT_PCS_BER, 1250 EFX_PHY_STAT_PCS_BLOCK_ERRORS, 1251 EFX_PHY_STAT_PHY_XS_LINK_UP, 1252 EFX_PHY_STAT_PHY_XS_RX_FAULT, 1253 EFX_PHY_STAT_PHY_XS_TX_FAULT, 1254 EFX_PHY_STAT_PHY_XS_ALIGN, 1255 EFX_PHY_STAT_PHY_XS_SYNC_A, 1256 EFX_PHY_STAT_PHY_XS_SYNC_B, 1257 EFX_PHY_STAT_PHY_XS_SYNC_C, 1258 EFX_PHY_STAT_PHY_XS_SYNC_D, 1259 EFX_PHY_STAT_AN_LINK_UP, 1260 EFX_PHY_STAT_AN_MASTER, 1261 EFX_PHY_STAT_AN_LOCAL_RX_OK, 1262 EFX_PHY_STAT_AN_REMOTE_RX_OK, 1263 EFX_PHY_STAT_CL22EXT_LINK_UP, 1264 EFX_PHY_STAT_SNR_A, 1265 EFX_PHY_STAT_SNR_B, 1266 EFX_PHY_STAT_SNR_C, 1267 EFX_PHY_STAT_SNR_D, 1268 EFX_PHY_STAT_PMA_PMD_SIGNAL_A, 1269 EFX_PHY_STAT_PMA_PMD_SIGNAL_B, 1270 EFX_PHY_STAT_PMA_PMD_SIGNAL_C, 1271 EFX_PHY_STAT_PMA_PMD_SIGNAL_D, 1272 EFX_PHY_STAT_AN_COMPLETE, 1273 EFX_PHY_STAT_PMA_PMD_REV_MAJOR, 1274 EFX_PHY_STAT_PMA_PMD_REV_MINOR, 1275 EFX_PHY_STAT_PMA_PMD_REV_MICRO, 1276 EFX_PHY_STAT_PCS_FW_VERSION_0, 1277 EFX_PHY_STAT_PCS_FW_VERSION_1, 1278 EFX_PHY_STAT_PCS_FW_VERSION_2, 1279 EFX_PHY_STAT_PCS_FW_VERSION_3, 1280 EFX_PHY_STAT_PCS_FW_BUILD_YY, 1281 EFX_PHY_STAT_PCS_FW_BUILD_MM, 1282 EFX_PHY_STAT_PCS_FW_BUILD_DD, 1283 EFX_PHY_STAT_PCS_OP_MODE, 1284 EFX_PHY_NSTATS 1285 } efx_phy_stat_t; 1286 1287 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */ 1288 1289 #if EFSYS_OPT_NAMES 1290 1291 LIBEFX_API 1292 extern const char * 1293 efx_phy_stat_name( 1294 __in efx_nic_t *enp, 1295 __in efx_phy_stat_t stat); 1296 1297 #endif /* EFSYS_OPT_NAMES */ 1298 1299 #define EFX_PHY_STATS_SIZE 0x100 1300 1301 LIBEFX_API 1302 extern __checkReturn efx_rc_t 1303 efx_phy_stats_update( 1304 __in efx_nic_t *enp, 1305 __in efsys_mem_t *esmp, 1306 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat); 1307 1308 #endif /* EFSYS_OPT_PHY_STATS */ 1309 1310 1311 #if EFSYS_OPT_BIST 1312 1313 typedef enum efx_bist_type_e { 1314 EFX_BIST_TYPE_UNKNOWN, 1315 EFX_BIST_TYPE_PHY_NORMAL, 1316 EFX_BIST_TYPE_PHY_CABLE_SHORT, 1317 EFX_BIST_TYPE_PHY_CABLE_LONG, 1318 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */ 1319 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */ 1320 EFX_BIST_TYPE_REG, /* Test the register memories */ 1321 EFX_BIST_TYPE_NTYPES, 1322 } efx_bist_type_t; 1323 1324 typedef enum efx_bist_result_e { 1325 EFX_BIST_RESULT_UNKNOWN, 1326 EFX_BIST_RESULT_RUNNING, 1327 EFX_BIST_RESULT_PASSED, 1328 EFX_BIST_RESULT_FAILED, 1329 } efx_bist_result_t; 1330 1331 typedef enum efx_phy_cable_status_e { 1332 EFX_PHY_CABLE_STATUS_OK, 1333 EFX_PHY_CABLE_STATUS_INVALID, 1334 EFX_PHY_CABLE_STATUS_OPEN, 1335 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT, 1336 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT, 1337 EFX_PHY_CABLE_STATUS_BUSY, 1338 } efx_phy_cable_status_t; 1339 1340 typedef enum efx_bist_value_e { 1341 EFX_BIST_PHY_CABLE_LENGTH_A, 1342 EFX_BIST_PHY_CABLE_LENGTH_B, 1343 EFX_BIST_PHY_CABLE_LENGTH_C, 1344 EFX_BIST_PHY_CABLE_LENGTH_D, 1345 EFX_BIST_PHY_CABLE_STATUS_A, 1346 EFX_BIST_PHY_CABLE_STATUS_B, 1347 EFX_BIST_PHY_CABLE_STATUS_C, 1348 EFX_BIST_PHY_CABLE_STATUS_D, 1349 EFX_BIST_FAULT_CODE, 1350 /* 1351 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL 1352 * response. 1353 */ 1354 EFX_BIST_MEM_TEST, 1355 EFX_BIST_MEM_ADDR, 1356 EFX_BIST_MEM_BUS, 1357 EFX_BIST_MEM_EXPECT, 1358 EFX_BIST_MEM_ACTUAL, 1359 EFX_BIST_MEM_ECC, 1360 EFX_BIST_MEM_ECC_PARITY, 1361 EFX_BIST_MEM_ECC_FATAL, 1362 EFX_BIST_NVALUES, 1363 } efx_bist_value_t; 1364 1365 LIBEFX_API 1366 extern __checkReturn efx_rc_t 1367 efx_bist_enable_offline( 1368 __in efx_nic_t *enp); 1369 1370 LIBEFX_API 1371 extern __checkReturn efx_rc_t 1372 efx_bist_start( 1373 __in efx_nic_t *enp, 1374 __in efx_bist_type_t type); 1375 1376 LIBEFX_API 1377 extern __checkReturn efx_rc_t 1378 efx_bist_poll( 1379 __in efx_nic_t *enp, 1380 __in efx_bist_type_t type, 1381 __out efx_bist_result_t *resultp, 1382 __out_opt uint32_t *value_maskp, 1383 __out_ecount_opt(count) unsigned long *valuesp, 1384 __in size_t count); 1385 1386 LIBEFX_API 1387 extern void 1388 efx_bist_stop( 1389 __in efx_nic_t *enp, 1390 __in efx_bist_type_t type); 1391 1392 #endif /* EFSYS_OPT_BIST */ 1393 1394 #define EFX_FEATURE_IPV6 0x00000001 1395 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002 1396 #define EFX_FEATURE_LINK_EVENTS 0x00000004 1397 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008 1398 #define EFX_FEATURE_MCDI 0x00000020 1399 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040 1400 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080 1401 #define EFX_FEATURE_TURBO 0x00000100 1402 #define EFX_FEATURE_MCDI_DMA 0x00000200 1403 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400 1404 #define EFX_FEATURE_PIO_BUFFERS 0x00000800 1405 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000 1406 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000 1407 #define EFX_FEATURE_PACKED_STREAM 0x00004000 1408 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000 1409 1410 typedef enum efx_tunnel_protocol_e { 1411 EFX_TUNNEL_PROTOCOL_NONE = 0, 1412 EFX_TUNNEL_PROTOCOL_VXLAN, 1413 EFX_TUNNEL_PROTOCOL_GENEVE, 1414 EFX_TUNNEL_PROTOCOL_NVGRE, 1415 EFX_TUNNEL_NPROTOS 1416 } efx_tunnel_protocol_t; 1417 1418 typedef enum efx_vi_window_shift_e { 1419 EFX_VI_WINDOW_SHIFT_INVALID = 0, 1420 EFX_VI_WINDOW_SHIFT_8K = 13, 1421 EFX_VI_WINDOW_SHIFT_16K = 14, 1422 EFX_VI_WINDOW_SHIFT_64K = 16, 1423 } efx_vi_window_shift_t; 1424 1425 typedef struct efx_nic_cfg_s { 1426 uint32_t enc_board_type; 1427 uint32_t enc_phy_type; 1428 #if EFSYS_OPT_NAMES 1429 char enc_phy_name[21]; 1430 #endif 1431 char enc_phy_revision[21]; 1432 efx_mon_type_t enc_mon_type; 1433 #if EFSYS_OPT_MON_STATS 1434 uint32_t enc_mon_stat_dma_buf_size; 1435 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32]; 1436 #endif 1437 unsigned int enc_features; 1438 efx_vi_window_shift_t enc_vi_window_shift; 1439 uint8_t enc_mac_addr[6]; 1440 uint8_t enc_port; /* PHY port number */ 1441 uint32_t enc_intr_vec_base; 1442 uint32_t enc_intr_limit; 1443 uint32_t enc_evq_limit; 1444 uint32_t enc_txq_limit; 1445 uint32_t enc_rxq_limit; 1446 uint32_t enc_evq_max_nevs; 1447 uint32_t enc_evq_min_nevs; 1448 uint32_t enc_rxq_max_ndescs; 1449 uint32_t enc_rxq_min_ndescs; 1450 uint32_t enc_txq_max_ndescs; 1451 uint32_t enc_txq_min_ndescs; 1452 uint32_t enc_buftbl_limit; 1453 uint32_t enc_piobuf_limit; 1454 uint32_t enc_piobuf_size; 1455 uint32_t enc_piobuf_min_alloc_size; 1456 uint32_t enc_evq_timer_quantum_ns; 1457 uint32_t enc_evq_timer_max_us; 1458 uint32_t enc_clk_mult; 1459 uint32_t enc_ev_ew_desc_size; 1460 uint32_t enc_ev_desc_size; 1461 uint32_t enc_rx_desc_size; 1462 uint32_t enc_tx_desc_size; 1463 /* Maximum Rx prefix size if many Rx prefixes are supported */ 1464 uint32_t enc_rx_prefix_size; 1465 uint32_t enc_rx_buf_align_start; 1466 uint32_t enc_rx_buf_align_end; 1467 #if EFSYS_OPT_RX_SCALE 1468 uint32_t enc_rx_scale_max_exclusive_contexts; 1469 /* 1470 * Mask of supported hash algorithms. 1471 * Hash algorithm types are used as the bit indices. 1472 */ 1473 uint32_t enc_rx_scale_hash_alg_mask; 1474 /* 1475 * Indicates whether port numbers can be included to the 1476 * input data for hash computation. 1477 */ 1478 boolean_t enc_rx_scale_l4_hash_supported; 1479 boolean_t enc_rx_scale_additional_modes_supported; 1480 #endif /* EFSYS_OPT_RX_SCALE */ 1481 #if EFSYS_OPT_LOOPBACK 1482 efx_qword_t enc_loopback_types[EFX_LINK_NMODES]; 1483 #endif /* EFSYS_OPT_LOOPBACK */ 1484 #if EFSYS_OPT_PHY_FLAGS 1485 uint32_t enc_phy_flags_mask; 1486 #endif /* EFSYS_OPT_PHY_FLAGS */ 1487 #if EFSYS_OPT_PHY_LED_CONTROL 1488 uint32_t enc_led_mask; 1489 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 1490 #if EFSYS_OPT_PHY_STATS 1491 uint64_t enc_phy_stat_mask; 1492 #endif /* EFSYS_OPT_PHY_STATS */ 1493 #if EFSYS_OPT_MCDI 1494 uint8_t enc_mcdi_mdio_channel; 1495 #if EFSYS_OPT_PHY_STATS 1496 uint32_t enc_mcdi_phy_stat_mask; 1497 #endif /* EFSYS_OPT_PHY_STATS */ 1498 #if EFSYS_OPT_MON_STATS 1499 uint32_t *enc_mcdi_sensor_maskp; 1500 uint32_t enc_mcdi_sensor_mask_size; 1501 #endif /* EFSYS_OPT_MON_STATS */ 1502 #endif /* EFSYS_OPT_MCDI */ 1503 #if EFSYS_OPT_BIST 1504 uint32_t enc_bist_mask; 1505 #endif /* EFSYS_OPT_BIST */ 1506 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() 1507 uint32_t enc_pf; 1508 uint32_t enc_vf; 1509 uint32_t enc_privilege_mask; 1510 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */ 1511 boolean_t enc_evq_init_done_ev_supported; 1512 boolean_t enc_bug26807_workaround; 1513 boolean_t enc_bug35388_workaround; 1514 boolean_t enc_bug41750_workaround; 1515 boolean_t enc_bug61265_workaround; 1516 boolean_t enc_bug61297_workaround; 1517 boolean_t enc_rx_batching_enabled; 1518 /* Maximum number of descriptors completed in an rx event. */ 1519 uint32_t enc_rx_batch_max; 1520 /* Number of rx descriptors the hardware requires for a push. */ 1521 uint32_t enc_rx_push_align; 1522 /* Maximum amount of data in DMA descriptor */ 1523 uint32_t enc_tx_dma_desc_size_max; 1524 /* 1525 * Boundary which DMA descriptor data must not cross or 0 if no 1526 * limitation. 1527 */ 1528 uint32_t enc_tx_dma_desc_boundary; 1529 /* 1530 * Maximum number of bytes into the packet the TCP header can start for 1531 * the hardware to apply TSO packet edits. 1532 */ 1533 uint32_t enc_tx_tso_tcp_header_offset_limit; 1534 /* Maximum number of header DMA descriptors per TSO transaction. */ 1535 uint32_t enc_tx_tso_max_header_ndescs; 1536 /* Maximum header length acceptable by TSO transaction. */ 1537 uint32_t enc_tx_tso_max_header_length; 1538 /* Maximum number of payload DMA descriptors per TSO transaction. */ 1539 uint32_t enc_tx_tso_max_payload_ndescs; 1540 /* Maximum payload length per TSO transaction. */ 1541 uint32_t enc_tx_tso_max_payload_length; 1542 /* Maximum number of frames to be generated per TSO transaction. */ 1543 uint32_t enc_tx_tso_max_nframes; 1544 boolean_t enc_fw_assisted_tso_enabled; 1545 boolean_t enc_fw_assisted_tso_v2_enabled; 1546 boolean_t enc_fw_assisted_tso_v2_encap_enabled; 1547 boolean_t enc_tso_v3_enabled; 1548 /* Number of TSO contexts on the NIC (FATSOv2) */ 1549 uint32_t enc_fw_assisted_tso_v2_n_contexts; 1550 boolean_t enc_hw_tx_insert_vlan_enabled; 1551 /* Number of PFs on the NIC */ 1552 uint32_t enc_hw_pf_count; 1553 /* Datapath firmware vadapter/vport/vswitch support */ 1554 boolean_t enc_datapath_cap_evb; 1555 /* Datapath firmware vport reconfigure support */ 1556 boolean_t enc_vport_reconfigure_supported; 1557 boolean_t enc_rx_disable_scatter_supported; 1558 /* Maximum number of Rx scatter segments supported by HW */ 1559 uint32_t enc_rx_scatter_max; 1560 boolean_t enc_allow_set_mac_with_installed_filters; 1561 boolean_t enc_enhanced_set_mac_supported; 1562 boolean_t enc_init_evq_v2_supported; 1563 boolean_t enc_init_evq_extended_width_supported; 1564 boolean_t enc_no_cont_ev_mode_supported; 1565 boolean_t enc_init_rxq_with_buffer_size; 1566 boolean_t enc_rx_packed_stream_supported; 1567 boolean_t enc_rx_var_packed_stream_supported; 1568 boolean_t enc_rx_es_super_buffer_supported; 1569 boolean_t enc_fw_subvariant_no_tx_csum_supported; 1570 boolean_t enc_pm_and_rxdp_counters; 1571 boolean_t enc_mac_stats_40g_tx_size_bins; 1572 uint32_t enc_tunnel_encapsulations_supported; 1573 /* 1574 * NIC global maximum for unique UDP tunnel ports shared by all 1575 * functions. 1576 */ 1577 uint32_t enc_tunnel_config_udp_entries_max; 1578 /* External port identifier */ 1579 uint8_t enc_external_port; 1580 uint32_t enc_mcdi_max_payload_length; 1581 /* VPD may be per-PF or global */ 1582 boolean_t enc_vpd_is_global; 1583 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */ 1584 uint32_t enc_required_pcie_bandwidth_mbps; 1585 uint32_t enc_max_pcie_link_gen; 1586 /* Firmware verifies integrity of NVRAM updates */ 1587 boolean_t enc_nvram_update_verify_result_supported; 1588 /* Firmware supports polled NVRAM updates on select partitions */ 1589 boolean_t enc_nvram_update_poll_verify_result_supported; 1590 /* Firmware accepts updates via the BUNDLE partition */ 1591 boolean_t enc_nvram_bundle_update_supported; 1592 /* Firmware support for extended MAC_STATS buffer */ 1593 uint32_t enc_mac_stats_nstats; 1594 boolean_t enc_fec_counters; 1595 boolean_t enc_hlb_counters; 1596 /* Firmware support for "FLAG" and "MARK" filter actions */ 1597 boolean_t enc_filter_action_flag_supported; 1598 boolean_t enc_filter_action_mark_supported; 1599 uint32_t enc_filter_action_mark_max; 1600 /* Port assigned to this PCI function */ 1601 uint32_t enc_assigned_port; 1602 } efx_nic_cfg_t; 1603 1604 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \ 1605 ((configp)->evc_function == 0xffff) 1606 1607 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff) 1608 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff) 1609 1610 #define EFX_PCI_FUNCTION(_encp) \ 1611 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf) 1612 1613 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf) 1614 1615 LIBEFX_API 1616 extern const efx_nic_cfg_t * 1617 efx_nic_cfg_get( 1618 __in const efx_nic_t *enp); 1619 1620 /* RxDPCPU firmware id values by which FW variant can be identified */ 1621 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0 1622 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1 1623 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2 1624 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5 1625 #define EFX_RXDP_DPDK_FW_ID 0x6 1626 1627 typedef struct efx_nic_fw_info_s { 1628 /* Basic FW version information */ 1629 uint16_t enfi_mc_fw_version[4]; 1630 /* 1631 * If datapath capabilities can be detected, 1632 * additional FW information is to be shown 1633 */ 1634 boolean_t enfi_dpcpu_fw_ids_valid; 1635 /* Rx and Tx datapath CPU FW IDs */ 1636 uint16_t enfi_rx_dpcpu_fw_id; 1637 uint16_t enfi_tx_dpcpu_fw_id; 1638 } efx_nic_fw_info_t; 1639 1640 LIBEFX_API 1641 extern __checkReturn efx_rc_t 1642 efx_nic_get_fw_version( 1643 __in efx_nic_t *enp, 1644 __out efx_nic_fw_info_t *enfip); 1645 1646 /* Driver resource limits (minimum required/maximum usable). */ 1647 typedef struct efx_drv_limits_s { 1648 uint32_t edl_min_evq_count; 1649 uint32_t edl_max_evq_count; 1650 1651 uint32_t edl_min_rxq_count; 1652 uint32_t edl_max_rxq_count; 1653 1654 uint32_t edl_min_txq_count; 1655 uint32_t edl_max_txq_count; 1656 1657 /* PIO blocks (sub-allocated from piobuf) */ 1658 uint32_t edl_min_pio_alloc_size; 1659 uint32_t edl_max_pio_alloc_count; 1660 } efx_drv_limits_t; 1661 1662 LIBEFX_API 1663 extern __checkReturn efx_rc_t 1664 efx_nic_set_drv_limits( 1665 __inout efx_nic_t *enp, 1666 __in efx_drv_limits_t *edlp); 1667 1668 /* 1669 * Register the OS driver version string for management agents 1670 * (e.g. via NC-SI). The content length is provided (i.e. no 1671 * NUL terminator). Use length 0 to indicate no version string 1672 * should be advertised. It is valid to set the version string 1673 * only before efx_nic_probe() is called. 1674 */ 1675 LIBEFX_API 1676 extern __checkReturn efx_rc_t 1677 efx_nic_set_drv_version( 1678 __inout efx_nic_t *enp, 1679 __in_ecount(length) char const *verp, 1680 __in size_t length); 1681 1682 typedef enum efx_nic_region_e { 1683 EFX_REGION_VI, /* Memory BAR UC mapping */ 1684 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */ 1685 } efx_nic_region_t; 1686 1687 LIBEFX_API 1688 extern __checkReturn efx_rc_t 1689 efx_nic_get_bar_region( 1690 __in efx_nic_t *enp, 1691 __in efx_nic_region_t region, 1692 __out uint32_t *offsetp, 1693 __out size_t *sizep); 1694 1695 LIBEFX_API 1696 extern __checkReturn efx_rc_t 1697 efx_nic_get_vi_pool( 1698 __in efx_nic_t *enp, 1699 __out uint32_t *evq_countp, 1700 __out uint32_t *rxq_countp, 1701 __out uint32_t *txq_countp); 1702 1703 1704 #if EFSYS_OPT_VPD 1705 1706 typedef enum efx_vpd_tag_e { 1707 EFX_VPD_ID = 0x02, 1708 EFX_VPD_END = 0x0f, 1709 EFX_VPD_RO = 0x10, 1710 EFX_VPD_RW = 0x11, 1711 } efx_vpd_tag_t; 1712 1713 typedef uint16_t efx_vpd_keyword_t; 1714 1715 typedef struct efx_vpd_value_s { 1716 efx_vpd_tag_t evv_tag; 1717 efx_vpd_keyword_t evv_keyword; 1718 uint8_t evv_length; 1719 uint8_t evv_value[0x100]; 1720 } efx_vpd_value_t; 1721 1722 1723 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8)) 1724 1725 LIBEFX_API 1726 extern __checkReturn efx_rc_t 1727 efx_vpd_init( 1728 __in efx_nic_t *enp); 1729 1730 LIBEFX_API 1731 extern __checkReturn efx_rc_t 1732 efx_vpd_size( 1733 __in efx_nic_t *enp, 1734 __out size_t *sizep); 1735 1736 LIBEFX_API 1737 extern __checkReturn efx_rc_t 1738 efx_vpd_read( 1739 __in efx_nic_t *enp, 1740 __out_bcount(size) caddr_t data, 1741 __in size_t size); 1742 1743 LIBEFX_API 1744 extern __checkReturn efx_rc_t 1745 efx_vpd_verify( 1746 __in efx_nic_t *enp, 1747 __in_bcount(size) caddr_t data, 1748 __in size_t size); 1749 1750 LIBEFX_API 1751 extern __checkReturn efx_rc_t 1752 efx_vpd_reinit( 1753 __in efx_nic_t *enp, 1754 __in_bcount(size) caddr_t data, 1755 __in size_t size); 1756 1757 LIBEFX_API 1758 extern __checkReturn efx_rc_t 1759 efx_vpd_get( 1760 __in efx_nic_t *enp, 1761 __in_bcount(size) caddr_t data, 1762 __in size_t size, 1763 __inout efx_vpd_value_t *evvp); 1764 1765 LIBEFX_API 1766 extern __checkReturn efx_rc_t 1767 efx_vpd_set( 1768 __in efx_nic_t *enp, 1769 __inout_bcount(size) caddr_t data, 1770 __in size_t size, 1771 __in efx_vpd_value_t *evvp); 1772 1773 LIBEFX_API 1774 extern __checkReturn efx_rc_t 1775 efx_vpd_next( 1776 __in efx_nic_t *enp, 1777 __inout_bcount(size) caddr_t data, 1778 __in size_t size, 1779 __out efx_vpd_value_t *evvp, 1780 __inout unsigned int *contp); 1781 1782 LIBEFX_API 1783 extern __checkReturn efx_rc_t 1784 efx_vpd_write( 1785 __in efx_nic_t *enp, 1786 __in_bcount(size) caddr_t data, 1787 __in size_t size); 1788 1789 LIBEFX_API 1790 extern void 1791 efx_vpd_fini( 1792 __in efx_nic_t *enp); 1793 1794 #endif /* EFSYS_OPT_VPD */ 1795 1796 /* NVRAM */ 1797 1798 #if EFSYS_OPT_NVRAM 1799 1800 typedef enum efx_nvram_type_e { 1801 EFX_NVRAM_INVALID = 0, 1802 EFX_NVRAM_BOOTROM, 1803 EFX_NVRAM_BOOTROM_CFG, 1804 EFX_NVRAM_MC_FIRMWARE, 1805 EFX_NVRAM_MC_GOLDEN, 1806 EFX_NVRAM_PHY, 1807 EFX_NVRAM_NULLPHY, 1808 EFX_NVRAM_FPGA, 1809 EFX_NVRAM_FCFW, 1810 EFX_NVRAM_CPLD, 1811 EFX_NVRAM_FPGA_BACKUP, 1812 EFX_NVRAM_DYNAMIC_CFG, 1813 EFX_NVRAM_LICENSE, 1814 EFX_NVRAM_UEFIROM, 1815 EFX_NVRAM_MUM_FIRMWARE, 1816 EFX_NVRAM_DYNCONFIG_DEFAULTS, 1817 EFX_NVRAM_ROMCONFIG_DEFAULTS, 1818 EFX_NVRAM_BUNDLE, 1819 EFX_NVRAM_BUNDLE_METADATA, 1820 EFX_NVRAM_NTYPES, 1821 } efx_nvram_type_t; 1822 1823 typedef struct efx_nvram_info_s { 1824 uint32_t eni_flags; 1825 uint32_t eni_partn_size; 1826 uint32_t eni_address; 1827 uint32_t eni_erase_size; 1828 uint32_t eni_write_size; 1829 } efx_nvram_info_t; 1830 1831 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0) 1832 1833 LIBEFX_API 1834 extern __checkReturn efx_rc_t 1835 efx_nvram_init( 1836 __in efx_nic_t *enp); 1837 1838 #if EFSYS_OPT_DIAG 1839 1840 LIBEFX_API 1841 extern __checkReturn efx_rc_t 1842 efx_nvram_test( 1843 __in efx_nic_t *enp); 1844 1845 #endif /* EFSYS_OPT_DIAG */ 1846 1847 LIBEFX_API 1848 extern __checkReturn efx_rc_t 1849 efx_nvram_size( 1850 __in efx_nic_t *enp, 1851 __in efx_nvram_type_t type, 1852 __out size_t *sizep); 1853 1854 LIBEFX_API 1855 extern __checkReturn efx_rc_t 1856 efx_nvram_info( 1857 __in efx_nic_t *enp, 1858 __in efx_nvram_type_t type, 1859 __out efx_nvram_info_t *enip); 1860 1861 LIBEFX_API 1862 extern __checkReturn efx_rc_t 1863 efx_nvram_rw_start( 1864 __in efx_nic_t *enp, 1865 __in efx_nvram_type_t type, 1866 __out_opt size_t *pref_chunkp); 1867 1868 LIBEFX_API 1869 extern __checkReturn efx_rc_t 1870 efx_nvram_rw_finish( 1871 __in efx_nic_t *enp, 1872 __in efx_nvram_type_t type, 1873 __out_opt uint32_t *verify_resultp); 1874 1875 LIBEFX_API 1876 extern __checkReturn efx_rc_t 1877 efx_nvram_get_version( 1878 __in efx_nic_t *enp, 1879 __in efx_nvram_type_t type, 1880 __out uint32_t *subtypep, 1881 __out_ecount(4) uint16_t version[4]); 1882 1883 LIBEFX_API 1884 extern __checkReturn efx_rc_t 1885 efx_nvram_read_chunk( 1886 __in efx_nic_t *enp, 1887 __in efx_nvram_type_t type, 1888 __in unsigned int offset, 1889 __out_bcount(size) caddr_t data, 1890 __in size_t size); 1891 1892 LIBEFX_API 1893 extern __checkReturn efx_rc_t 1894 efx_nvram_read_backup( 1895 __in efx_nic_t *enp, 1896 __in efx_nvram_type_t type, 1897 __in unsigned int offset, 1898 __out_bcount(size) caddr_t data, 1899 __in size_t size); 1900 1901 LIBEFX_API 1902 extern __checkReturn efx_rc_t 1903 efx_nvram_set_version( 1904 __in efx_nic_t *enp, 1905 __in efx_nvram_type_t type, 1906 __in_ecount(4) uint16_t version[4]); 1907 1908 LIBEFX_API 1909 extern __checkReturn efx_rc_t 1910 efx_nvram_validate( 1911 __in efx_nic_t *enp, 1912 __in efx_nvram_type_t type, 1913 __in_bcount(partn_size) caddr_t partn_data, 1914 __in size_t partn_size); 1915 1916 LIBEFX_API 1917 extern __checkReturn efx_rc_t 1918 efx_nvram_erase( 1919 __in efx_nic_t *enp, 1920 __in efx_nvram_type_t type); 1921 1922 LIBEFX_API 1923 extern __checkReturn efx_rc_t 1924 efx_nvram_write_chunk( 1925 __in efx_nic_t *enp, 1926 __in efx_nvram_type_t type, 1927 __in unsigned int offset, 1928 __in_bcount(size) caddr_t data, 1929 __in size_t size); 1930 1931 LIBEFX_API 1932 extern void 1933 efx_nvram_fini( 1934 __in efx_nic_t *enp); 1935 1936 #endif /* EFSYS_OPT_NVRAM */ 1937 1938 #if EFSYS_OPT_BOOTCFG 1939 1940 /* Report size and offset of bootcfg sector in NVRAM partition. */ 1941 LIBEFX_API 1942 extern __checkReturn efx_rc_t 1943 efx_bootcfg_sector_info( 1944 __in efx_nic_t *enp, 1945 __in uint32_t pf, 1946 __out_opt uint32_t *sector_countp, 1947 __out size_t *offsetp, 1948 __out size_t *max_sizep); 1949 1950 /* 1951 * Copy bootcfg sector data to a target buffer which may differ in size. 1952 * Optionally corrects format errors in source buffer. 1953 */ 1954 LIBEFX_API 1955 extern efx_rc_t 1956 efx_bootcfg_copy_sector( 1957 __in efx_nic_t *enp, 1958 __inout_bcount(sector_length) 1959 uint8_t *sector, 1960 __in size_t sector_length, 1961 __out_bcount(data_size) uint8_t *data, 1962 __in size_t data_size, 1963 __in boolean_t handle_format_errors); 1964 1965 LIBEFX_API 1966 extern efx_rc_t 1967 efx_bootcfg_read( 1968 __in efx_nic_t *enp, 1969 __out_bcount(size) uint8_t *data, 1970 __in size_t size); 1971 1972 LIBEFX_API 1973 extern efx_rc_t 1974 efx_bootcfg_write( 1975 __in efx_nic_t *enp, 1976 __in_bcount(size) uint8_t *data, 1977 __in size_t size); 1978 1979 1980 /* 1981 * Processing routines for buffers arranged in the DHCP/BOOTP option format 1982 * (see https://tools.ietf.org/html/rfc1533) 1983 * 1984 * Summarising the format: the buffer is a sequence of options. All options 1985 * begin with a tag octet, which uniquely identifies the option. Fixed- 1986 * length options without data consist of only a tag octet. Only options PAD 1987 * (0) and END (255) are fixed length. All other options are variable-length 1988 * with a length octet following the tag octet. The value of the length 1989 * octet does not include the two octets specifying the tag and length. The 1990 * length octet is followed by "length" octets of data. 1991 * 1992 * Option data may be a sequence of sub-options in the same format. The data 1993 * content of the encapsulating option is one or more encapsulated sub-options, 1994 * with no terminating END tag is required. 1995 * 1996 * To be valid, the top-level sequence of options should be terminated by an 1997 * END tag. The buffer should be padded with the PAD byte. 1998 * 1999 * When stored to NVRAM, the DHCP option format buffer is preceded by a 2000 * checksum octet. The full buffer (including after the END tag) contributes 2001 * to the checksum, hence the need to fill the buffer to the end with PAD. 2002 */ 2003 2004 #define EFX_DHCP_END ((uint8_t)0xff) 2005 #define EFX_DHCP_PAD ((uint8_t)0) 2006 2007 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \ 2008 (uint16_t)(((encapsulator) << 8) | (encapsulated)) 2009 2010 LIBEFX_API 2011 extern __checkReturn uint8_t 2012 efx_dhcp_csum( 2013 __in_bcount(size) uint8_t const *data, 2014 __in size_t size); 2015 2016 LIBEFX_API 2017 extern __checkReturn efx_rc_t 2018 efx_dhcp_verify( 2019 __in_bcount(size) uint8_t const *data, 2020 __in size_t size, 2021 __out_opt size_t *usedp); 2022 2023 LIBEFX_API 2024 extern __checkReturn efx_rc_t 2025 efx_dhcp_find_tag( 2026 __in_bcount(buffer_length) uint8_t *bufferp, 2027 __in size_t buffer_length, 2028 __in uint16_t opt, 2029 __deref_out uint8_t **valuepp, 2030 __out size_t *value_lengthp); 2031 2032 LIBEFX_API 2033 extern __checkReturn efx_rc_t 2034 efx_dhcp_find_end( 2035 __in_bcount(buffer_length) uint8_t *bufferp, 2036 __in size_t buffer_length, 2037 __deref_out uint8_t **endpp); 2038 2039 2040 LIBEFX_API 2041 extern __checkReturn efx_rc_t 2042 efx_dhcp_delete_tag( 2043 __inout_bcount(buffer_length) uint8_t *bufferp, 2044 __in size_t buffer_length, 2045 __in uint16_t opt); 2046 2047 LIBEFX_API 2048 extern __checkReturn efx_rc_t 2049 efx_dhcp_add_tag( 2050 __inout_bcount(buffer_length) uint8_t *bufferp, 2051 __in size_t buffer_length, 2052 __in uint16_t opt, 2053 __in_bcount_opt(value_length) uint8_t *valuep, 2054 __in size_t value_length); 2055 2056 LIBEFX_API 2057 extern __checkReturn efx_rc_t 2058 efx_dhcp_update_tag( 2059 __inout_bcount(buffer_length) uint8_t *bufferp, 2060 __in size_t buffer_length, 2061 __in uint16_t opt, 2062 __in uint8_t *value_locationp, 2063 __in_bcount_opt(value_length) uint8_t *valuep, 2064 __in size_t value_length); 2065 2066 2067 #endif /* EFSYS_OPT_BOOTCFG */ 2068 2069 #if EFSYS_OPT_IMAGE_LAYOUT 2070 2071 #include "ef10_signed_image_layout.h" 2072 2073 /* 2074 * Image header used in unsigned and signed image layouts (see SF-102785-PS). 2075 * 2076 * NOTE: 2077 * The image header format is extensible. However, older drivers require an 2078 * exact match of image header version and header length when validating and 2079 * writing firmware images. 2080 * 2081 * To avoid breaking backward compatibility, we use the upper bits of the 2082 * controller version fields to contain an extra version number used for 2083 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM 2084 * version). See bug39254 and SF-102785-PS for details. 2085 */ 2086 typedef struct efx_image_header_s { 2087 uint32_t eih_magic; 2088 uint32_t eih_version; 2089 uint32_t eih_type; 2090 uint32_t eih_subtype; 2091 uint32_t eih_code_size; 2092 uint32_t eih_size; 2093 union { 2094 uint32_t eih_controller_version_min; 2095 struct { 2096 uint16_t eih_controller_version_min_short; 2097 uint8_t eih_extra_version_a; 2098 uint8_t eih_extra_version_b; 2099 }; 2100 }; 2101 union { 2102 uint32_t eih_controller_version_max; 2103 struct { 2104 uint16_t eih_controller_version_max_short; 2105 uint8_t eih_extra_version_c; 2106 uint8_t eih_extra_version_d; 2107 }; 2108 }; 2109 uint16_t eih_code_version_a; 2110 uint16_t eih_code_version_b; 2111 uint16_t eih_code_version_c; 2112 uint16_t eih_code_version_d; 2113 } efx_image_header_t; 2114 2115 #define EFX_IMAGE_HEADER_SIZE (40) 2116 #define EFX_IMAGE_HEADER_VERSION (4) 2117 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5) 2118 2119 2120 typedef struct efx_image_trailer_s { 2121 uint32_t eit_crc; 2122 } efx_image_trailer_t; 2123 2124 #define EFX_IMAGE_TRAILER_SIZE (4) 2125 2126 typedef enum efx_image_format_e { 2127 EFX_IMAGE_FORMAT_NO_IMAGE, 2128 EFX_IMAGE_FORMAT_INVALID, 2129 EFX_IMAGE_FORMAT_UNSIGNED, 2130 EFX_IMAGE_FORMAT_SIGNED, 2131 EFX_IMAGE_FORMAT_SIGNED_PACKAGE 2132 } efx_image_format_t; 2133 2134 typedef struct efx_image_info_s { 2135 efx_image_format_t eii_format; 2136 uint8_t * eii_imagep; 2137 size_t eii_image_size; 2138 efx_image_header_t * eii_headerp; 2139 } efx_image_info_t; 2140 2141 LIBEFX_API 2142 extern __checkReturn efx_rc_t 2143 efx_check_reflash_image( 2144 __in void *bufferp, 2145 __in uint32_t buffer_size, 2146 __out efx_image_info_t *infop); 2147 2148 LIBEFX_API 2149 extern __checkReturn efx_rc_t 2150 efx_build_signed_image_write_buffer( 2151 __out_bcount(buffer_size) 2152 uint8_t *bufferp, 2153 __in uint32_t buffer_size, 2154 __in efx_image_info_t *infop, 2155 __out efx_image_header_t **headerpp); 2156 2157 #endif /* EFSYS_OPT_IMAGE_LAYOUT */ 2158 2159 #if EFSYS_OPT_DIAG 2160 2161 typedef enum efx_pattern_type_t { 2162 EFX_PATTERN_BYTE_INCREMENT = 0, 2163 EFX_PATTERN_ALL_THE_SAME, 2164 EFX_PATTERN_BIT_ALTERNATE, 2165 EFX_PATTERN_BYTE_ALTERNATE, 2166 EFX_PATTERN_BYTE_CHANGING, 2167 EFX_PATTERN_BIT_SWEEP, 2168 EFX_PATTERN_NTYPES 2169 } efx_pattern_type_t; 2170 2171 typedef void 2172 (*efx_sram_pattern_fn_t)( 2173 __in size_t row, 2174 __in boolean_t negate, 2175 __out efx_qword_t *eqp); 2176 2177 LIBEFX_API 2178 extern __checkReturn efx_rc_t 2179 efx_sram_test( 2180 __in efx_nic_t *enp, 2181 __in efx_pattern_type_t type); 2182 2183 #endif /* EFSYS_OPT_DIAG */ 2184 2185 LIBEFX_API 2186 extern __checkReturn efx_rc_t 2187 efx_sram_buf_tbl_set( 2188 __in efx_nic_t *enp, 2189 __in uint32_t id, 2190 __in efsys_mem_t *esmp, 2191 __in size_t n); 2192 2193 LIBEFX_API 2194 extern void 2195 efx_sram_buf_tbl_clear( 2196 __in efx_nic_t *enp, 2197 __in uint32_t id, 2198 __in size_t n); 2199 2200 #define EFX_BUF_TBL_SIZE 0x20000 2201 2202 #define EFX_BUF_SIZE 4096 2203 2204 /* EV */ 2205 2206 typedef struct efx_evq_s efx_evq_t; 2207 2208 #if EFSYS_OPT_QSTATS 2209 2210 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */ 2211 typedef enum efx_ev_qstat_e { 2212 EV_ALL, 2213 EV_RX, 2214 EV_RX_OK, 2215 EV_RX_FRM_TRUNC, 2216 EV_RX_TOBE_DISC, 2217 EV_RX_PAUSE_FRM_ERR, 2218 EV_RX_BUF_OWNER_ID_ERR, 2219 EV_RX_IPV4_HDR_CHKSUM_ERR, 2220 EV_RX_TCP_UDP_CHKSUM_ERR, 2221 EV_RX_ETH_CRC_ERR, 2222 EV_RX_IP_FRAG_ERR, 2223 EV_RX_MCAST_PKT, 2224 EV_RX_MCAST_HASH_MATCH, 2225 EV_RX_TCP_IPV4, 2226 EV_RX_TCP_IPV6, 2227 EV_RX_UDP_IPV4, 2228 EV_RX_UDP_IPV6, 2229 EV_RX_OTHER_IPV4, 2230 EV_RX_OTHER_IPV6, 2231 EV_RX_NON_IP, 2232 EV_RX_BATCH, 2233 EV_TX, 2234 EV_TX_WQ_FF_FULL, 2235 EV_TX_PKT_ERR, 2236 EV_TX_PKT_TOO_BIG, 2237 EV_TX_UNEXPECTED, 2238 EV_GLOBAL, 2239 EV_GLOBAL_MNT, 2240 EV_DRIVER, 2241 EV_DRIVER_SRM_UPD_DONE, 2242 EV_DRIVER_TX_DESCQ_FLS_DONE, 2243 EV_DRIVER_RX_DESCQ_FLS_DONE, 2244 EV_DRIVER_RX_DESCQ_FLS_FAILED, 2245 EV_DRIVER_RX_DSC_ERROR, 2246 EV_DRIVER_TX_DSC_ERROR, 2247 EV_DRV_GEN, 2248 EV_MCDI_RESPONSE, 2249 EV_RX_PARSE_INCOMPLETE, 2250 EV_NQSTATS 2251 } efx_ev_qstat_t; 2252 2253 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */ 2254 2255 #endif /* EFSYS_OPT_QSTATS */ 2256 2257 LIBEFX_API 2258 extern __checkReturn efx_rc_t 2259 efx_ev_init( 2260 __in efx_nic_t *enp); 2261 2262 LIBEFX_API 2263 extern void 2264 efx_ev_fini( 2265 __in efx_nic_t *enp); 2266 2267 LIBEFX_API 2268 extern __checkReturn size_t 2269 efx_evq_size( 2270 __in const efx_nic_t *enp, 2271 __in unsigned int ndescs, 2272 __in uint32_t flags); 2273 2274 LIBEFX_API 2275 extern __checkReturn unsigned int 2276 efx_evq_nbufs( 2277 __in const efx_nic_t *enp, 2278 __in unsigned int ndescs, 2279 __in uint32_t flags); 2280 2281 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3) 2282 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0) 2283 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1) 2284 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2) 2285 2286 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC) 2287 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */ 2288 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */ 2289 2290 /* 2291 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more 2292 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in 2293 * NO_CONT_EV mode". 2294 * 2295 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set, 2296 * which is the case when an event queue is set to THROUGHPUT mode. 2297 */ 2298 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10) 2299 2300 /* Configure EVQ for extended width events (EF100 only) */ 2301 #define EFX_EVQ_FLAGS_EXTENDED_WIDTH (0x20) 2302 2303 2304 LIBEFX_API 2305 extern __checkReturn efx_rc_t 2306 efx_ev_qcreate( 2307 __in efx_nic_t *enp, 2308 __in unsigned int index, 2309 __in efsys_mem_t *esmp, 2310 __in size_t ndescs, 2311 __in uint32_t id, 2312 __in uint32_t us, 2313 __in uint32_t flags, 2314 __deref_out efx_evq_t **eepp); 2315 2316 LIBEFX_API 2317 extern void 2318 efx_ev_qpost( 2319 __in efx_evq_t *eep, 2320 __in uint16_t data); 2321 2322 typedef __checkReturn boolean_t 2323 (*efx_initialized_ev_t)( 2324 __in_opt void *arg); 2325 2326 #define EFX_PKT_UNICAST 0x0004 2327 #define EFX_PKT_START 0x0008 2328 2329 #define EFX_PKT_VLAN_TAGGED 0x0010 2330 #define EFX_CKSUM_TCPUDP 0x0020 2331 #define EFX_CKSUM_IPV4 0x0040 2332 #define EFX_PKT_CONT 0x0080 2333 2334 #define EFX_CHECK_VLAN 0x0100 2335 #define EFX_PKT_TCP 0x0200 2336 #define EFX_PKT_UDP 0x0400 2337 #define EFX_PKT_IPV4 0x0800 2338 2339 #define EFX_PKT_IPV6 0x1000 2340 #define EFX_PKT_PREFIX_LEN 0x2000 2341 #define EFX_ADDR_MISMATCH 0x4000 2342 #define EFX_DISCARD 0x8000 2343 2344 /* 2345 * The following flags are used only for packed stream 2346 * mode. The values for the flags are reused to fit into 16 bit, 2347 * since EFX_PKT_START and EFX_PKT_CONT are never used in 2348 * packed stream mode 2349 */ 2350 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START 2351 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT 2352 2353 2354 #define EFX_EV_RX_NLABELS 32 2355 #define EFX_EV_TX_NLABELS 32 2356 2357 typedef __checkReturn boolean_t 2358 (*efx_rx_ev_t)( 2359 __in_opt void *arg, 2360 __in uint32_t label, 2361 __in uint32_t id, 2362 __in uint32_t size, 2363 __in uint16_t flags); 2364 2365 typedef __checkReturn boolean_t 2366 (*efx_rx_packets_ev_t)( 2367 __in_opt void *arg, 2368 __in uint32_t label, 2369 __in unsigned int num_packets, 2370 __in uint32_t flags); 2371 2372 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2373 2374 /* 2375 * Packed stream mode is documented in SF-112241-TC. 2376 * The general idea is that, instead of putting each incoming 2377 * packet into a separate buffer which is specified in a RX 2378 * descriptor, a large buffer is provided to the hardware and 2379 * packets are put there in a continuous stream. 2380 * The main advantage of such an approach is that RX queue refilling 2381 * happens much less frequently. 2382 * 2383 * Equal stride packed stream mode is documented in SF-119419-TC. 2384 * The general idea is to utilize advantages of the packed stream, 2385 * but avoid indirection in packets representation. 2386 * The main advantage of such an approach is that RX queue refilling 2387 * happens much less frequently and packets buffers are independent 2388 * from upper layers point of view. 2389 */ 2390 2391 typedef __checkReturn boolean_t 2392 (*efx_rx_ps_ev_t)( 2393 __in_opt void *arg, 2394 __in uint32_t label, 2395 __in uint32_t id, 2396 __in uint32_t pkt_count, 2397 __in uint16_t flags); 2398 2399 #endif 2400 2401 typedef __checkReturn boolean_t 2402 (*efx_tx_ev_t)( 2403 __in_opt void *arg, 2404 __in uint32_t label, 2405 __in uint32_t id); 2406 2407 typedef __checkReturn boolean_t 2408 (*efx_tx_ndescs_ev_t)( 2409 __in_opt void *arg, 2410 __in uint32_t label, 2411 __in unsigned int ndescs); 2412 2413 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001 2414 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002 2415 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003 2416 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004 2417 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005 2418 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006 2419 #define EFX_EXCEPTION_RX_ERROR 0x00000007 2420 #define EFX_EXCEPTION_TX_ERROR 0x00000008 2421 #define EFX_EXCEPTION_EV_ERROR 0x00000009 2422 2423 typedef __checkReturn boolean_t 2424 (*efx_exception_ev_t)( 2425 __in_opt void *arg, 2426 __in uint32_t label, 2427 __in uint32_t data); 2428 2429 typedef __checkReturn boolean_t 2430 (*efx_rxq_flush_done_ev_t)( 2431 __in_opt void *arg, 2432 __in uint32_t rxq_index); 2433 2434 typedef __checkReturn boolean_t 2435 (*efx_rxq_flush_failed_ev_t)( 2436 __in_opt void *arg, 2437 __in uint32_t rxq_index); 2438 2439 typedef __checkReturn boolean_t 2440 (*efx_txq_flush_done_ev_t)( 2441 __in_opt void *arg, 2442 __in uint32_t txq_index); 2443 2444 typedef __checkReturn boolean_t 2445 (*efx_software_ev_t)( 2446 __in_opt void *arg, 2447 __in uint16_t magic); 2448 2449 typedef __checkReturn boolean_t 2450 (*efx_sram_ev_t)( 2451 __in_opt void *arg, 2452 __in uint32_t code); 2453 2454 #define EFX_SRAM_CLEAR 0 2455 #define EFX_SRAM_UPDATE 1 2456 #define EFX_SRAM_ILLEGAL_CLEAR 2 2457 2458 typedef __checkReturn boolean_t 2459 (*efx_wake_up_ev_t)( 2460 __in_opt void *arg, 2461 __in uint32_t label); 2462 2463 typedef __checkReturn boolean_t 2464 (*efx_timer_ev_t)( 2465 __in_opt void *arg, 2466 __in uint32_t label); 2467 2468 typedef __checkReturn boolean_t 2469 (*efx_link_change_ev_t)( 2470 __in_opt void *arg, 2471 __in efx_link_mode_t link_mode); 2472 2473 #if EFSYS_OPT_MON_STATS 2474 2475 typedef __checkReturn boolean_t 2476 (*efx_monitor_ev_t)( 2477 __in_opt void *arg, 2478 __in efx_mon_stat_t id, 2479 __in efx_mon_stat_value_t value); 2480 2481 #endif /* EFSYS_OPT_MON_STATS */ 2482 2483 #if EFSYS_OPT_MAC_STATS 2484 2485 typedef __checkReturn boolean_t 2486 (*efx_mac_stats_ev_t)( 2487 __in_opt void *arg, 2488 __in uint32_t generation); 2489 2490 #endif /* EFSYS_OPT_MAC_STATS */ 2491 2492 #if EFSYS_OPT_DESC_PROXY 2493 2494 /* 2495 * NOTE: This callback returns the raw descriptor data, which has not been 2496 * converted to host endian. The callback must use the EFX_OWORD macros 2497 * to extract the descriptor fields as host endian values. 2498 */ 2499 typedef __checkReturn boolean_t 2500 (*efx_desc_proxy_txq_desc_ev_t)( 2501 __in_opt void *arg, 2502 __in uint16_t vi_id, 2503 __in efx_oword_t txq_desc); 2504 2505 /* 2506 * NOTE: This callback returns the raw descriptor data, which has not been 2507 * converted to host endian. The callback must use the EFX_OWORD macros 2508 * to extract the descriptor fields as host endian values. 2509 */ 2510 typedef __checkReturn boolean_t 2511 (*efx_desc_proxy_virtq_desc_ev_t)( 2512 __in_opt void *arg, 2513 __in uint16_t vi_id, 2514 __in uint16_t avail, 2515 __in efx_oword_t virtq_desc); 2516 2517 #endif /* EFSYS_OPT_DESC_PROXY */ 2518 2519 typedef struct efx_ev_callbacks_s { 2520 efx_initialized_ev_t eec_initialized; 2521 efx_rx_ev_t eec_rx; 2522 efx_rx_packets_ev_t eec_rx_packets; 2523 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER 2524 efx_rx_ps_ev_t eec_rx_ps; 2525 #endif 2526 efx_tx_ev_t eec_tx; 2527 efx_tx_ndescs_ev_t eec_tx_ndescs; 2528 efx_exception_ev_t eec_exception; 2529 efx_rxq_flush_done_ev_t eec_rxq_flush_done; 2530 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed; 2531 efx_txq_flush_done_ev_t eec_txq_flush_done; 2532 efx_software_ev_t eec_software; 2533 efx_sram_ev_t eec_sram; 2534 efx_wake_up_ev_t eec_wake_up; 2535 efx_timer_ev_t eec_timer; 2536 efx_link_change_ev_t eec_link_change; 2537 #if EFSYS_OPT_MON_STATS 2538 efx_monitor_ev_t eec_monitor; 2539 #endif /* EFSYS_OPT_MON_STATS */ 2540 #if EFSYS_OPT_MAC_STATS 2541 efx_mac_stats_ev_t eec_mac_stats; 2542 #endif /* EFSYS_OPT_MAC_STATS */ 2543 #if EFSYS_OPT_DESC_PROXY 2544 efx_desc_proxy_txq_desc_ev_t eec_desc_proxy_txq_desc; 2545 efx_desc_proxy_virtq_desc_ev_t eec_desc_proxy_virtq_desc; 2546 #endif /* EFSYS_OPT_DESC_PROXY */ 2547 2548 } efx_ev_callbacks_t; 2549 2550 LIBEFX_API 2551 extern __checkReturn boolean_t 2552 efx_ev_qpending( 2553 __in efx_evq_t *eep, 2554 __in unsigned int count); 2555 2556 #if EFSYS_OPT_EV_PREFETCH 2557 2558 LIBEFX_API 2559 extern void 2560 efx_ev_qprefetch( 2561 __in efx_evq_t *eep, 2562 __in unsigned int count); 2563 2564 #endif /* EFSYS_OPT_EV_PREFETCH */ 2565 2566 LIBEFX_API 2567 extern void 2568 efx_ev_qcreate_check_init_done( 2569 __in efx_evq_t *eep, 2570 __in const efx_ev_callbacks_t *eecp, 2571 __in_opt void *arg); 2572 2573 LIBEFX_API 2574 extern void 2575 efx_ev_qpoll( 2576 __in efx_evq_t *eep, 2577 __inout unsigned int *countp, 2578 __in const efx_ev_callbacks_t *eecp, 2579 __in_opt void *arg); 2580 2581 LIBEFX_API 2582 extern __checkReturn efx_rc_t 2583 efx_ev_usecs_to_ticks( 2584 __in efx_nic_t *enp, 2585 __in unsigned int usecs, 2586 __out unsigned int *ticksp); 2587 2588 LIBEFX_API 2589 extern __checkReturn efx_rc_t 2590 efx_ev_qmoderate( 2591 __in efx_evq_t *eep, 2592 __in unsigned int us); 2593 2594 LIBEFX_API 2595 extern __checkReturn efx_rc_t 2596 efx_ev_qprime( 2597 __in efx_evq_t *eep, 2598 __in unsigned int count); 2599 2600 #if EFSYS_OPT_QSTATS 2601 2602 #if EFSYS_OPT_NAMES 2603 2604 LIBEFX_API 2605 extern const char * 2606 efx_ev_qstat_name( 2607 __in efx_nic_t *enp, 2608 __in unsigned int id); 2609 2610 #endif /* EFSYS_OPT_NAMES */ 2611 2612 LIBEFX_API 2613 extern void 2614 efx_ev_qstats_update( 2615 __in efx_evq_t *eep, 2616 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat); 2617 2618 #endif /* EFSYS_OPT_QSTATS */ 2619 2620 LIBEFX_API 2621 extern void 2622 efx_ev_qdestroy( 2623 __in efx_evq_t *eep); 2624 2625 /* RX */ 2626 2627 LIBEFX_API 2628 extern __checkReturn efx_rc_t 2629 efx_rx_init( 2630 __inout efx_nic_t *enp); 2631 2632 LIBEFX_API 2633 extern void 2634 efx_rx_fini( 2635 __in efx_nic_t *enp); 2636 2637 #if EFSYS_OPT_RX_SCATTER 2638 LIBEFX_API 2639 extern __checkReturn efx_rc_t 2640 efx_rx_scatter_enable( 2641 __in efx_nic_t *enp, 2642 __in unsigned int buf_size); 2643 #endif /* EFSYS_OPT_RX_SCATTER */ 2644 2645 /* Handle to represent use of the default RSS context. */ 2646 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff 2647 2648 #if EFSYS_OPT_RX_SCALE 2649 2650 typedef enum efx_rx_hash_alg_e { 2651 EFX_RX_HASHALG_LFSR = 0, 2652 EFX_RX_HASHALG_TOEPLITZ, 2653 EFX_RX_HASHALG_PACKED_STREAM, 2654 EFX_RX_NHASHALGS 2655 } efx_rx_hash_alg_t; 2656 2657 /* 2658 * Legacy hash type flags. 2659 * 2660 * They represent standard tuples for distinct traffic classes. 2661 */ 2662 #define EFX_RX_HASH_IPV4 (1U << 0) 2663 #define EFX_RX_HASH_TCPIPV4 (1U << 1) 2664 #define EFX_RX_HASH_IPV6 (1U << 2) 2665 #define EFX_RX_HASH_TCPIPV6 (1U << 3) 2666 2667 #define EFX_RX_HASH_LEGACY_MASK \ 2668 (EFX_RX_HASH_IPV4 | \ 2669 EFX_RX_HASH_TCPIPV4 | \ 2670 EFX_RX_HASH_IPV6 | \ 2671 EFX_RX_HASH_TCPIPV6) 2672 2673 /* 2674 * The type of the argument used by efx_rx_scale_mode_set() to 2675 * provide a means for the client drivers to configure hashing. 2676 * 2677 * A properly constructed value can either be: 2678 * - a combination of legacy flags 2679 * - a combination of EFX_RX_HASH() flags 2680 */ 2681 typedef uint32_t efx_rx_hash_type_t; 2682 2683 typedef enum efx_rx_hash_support_e { 2684 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */ 2685 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */ 2686 } efx_rx_hash_support_t; 2687 2688 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */ 2689 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */ 2690 #define EFX_MAXRSS 64 /* RX indirection entry range */ 2691 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */ 2692 2693 typedef enum efx_rx_scale_context_type_e { 2694 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */ 2695 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */ 2696 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */ 2697 } efx_rx_scale_context_type_t; 2698 2699 /* 2700 * Traffic classes eligible for hash computation. 2701 * 2702 * Select packet headers used in computing the receive hash. 2703 * This uses the same encoding as the RSS_MODES field of 2704 * MC_CMD_RSS_CONTEXT_SET_FLAGS. 2705 */ 2706 #define EFX_RX_CLASS_IPV4_TCP_LBN 8 2707 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4 2708 #define EFX_RX_CLASS_IPV4_UDP_LBN 12 2709 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4 2710 #define EFX_RX_CLASS_IPV4_LBN 16 2711 #define EFX_RX_CLASS_IPV4_WIDTH 4 2712 #define EFX_RX_CLASS_IPV6_TCP_LBN 20 2713 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4 2714 #define EFX_RX_CLASS_IPV6_UDP_LBN 24 2715 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4 2716 #define EFX_RX_CLASS_IPV6_LBN 28 2717 #define EFX_RX_CLASS_IPV6_WIDTH 4 2718 2719 #define EFX_RX_NCLASSES 6 2720 2721 /* 2722 * Ancillary flags used to construct generic hash tuples. 2723 * This uses the same encoding as RSS_MODE_HASH_SELECTOR. 2724 */ 2725 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0) 2726 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1) 2727 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2) 2728 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3) 2729 2730 /* 2731 * Generic hash tuples. 2732 * 2733 * They express combinations of packet fields 2734 * which can contribute to the hash value for 2735 * a particular traffic class. 2736 */ 2737 #define EFX_RX_CLASS_HASH_DISABLE 0 2738 2739 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR 2740 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR 2741 2742 #define EFX_RX_CLASS_HASH_2TUPLE \ 2743 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2744 EFX_RX_CLASS_HASH_DST_ADDR) 2745 2746 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \ 2747 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2748 EFX_RX_CLASS_HASH_SRC_PORT) 2749 2750 #define EFX_RX_CLASS_HASH_2TUPLE_DST \ 2751 (EFX_RX_CLASS_HASH_DST_ADDR | \ 2752 EFX_RX_CLASS_HASH_DST_PORT) 2753 2754 #define EFX_RX_CLASS_HASH_4TUPLE \ 2755 (EFX_RX_CLASS_HASH_SRC_ADDR | \ 2756 EFX_RX_CLASS_HASH_DST_ADDR | \ 2757 EFX_RX_CLASS_HASH_SRC_PORT | \ 2758 EFX_RX_CLASS_HASH_DST_PORT) 2759 2760 #define EFX_RX_CLASS_HASH_NTUPLES 7 2761 2762 /* 2763 * Hash flag constructor. 2764 * 2765 * Resulting flags encode hash tuples for specific traffic classes. 2766 * The client drivers are encouraged to use these flags to form 2767 * a hash type value. 2768 */ 2769 #define EFX_RX_HASH(_class, _tuple) \ 2770 EFX_INSERT_FIELD_NATIVE32(0, 31, \ 2771 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple) 2772 2773 /* 2774 * The maximum number of EFX_RX_HASH() flags. 2775 */ 2776 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES) 2777 2778 LIBEFX_API 2779 extern __checkReturn efx_rc_t 2780 efx_rx_scale_hash_flags_get( 2781 __in efx_nic_t *enp, 2782 __in efx_rx_hash_alg_t hash_alg, 2783 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp, 2784 __in unsigned int max_nflags, 2785 __out unsigned int *nflagsp); 2786 2787 LIBEFX_API 2788 extern __checkReturn efx_rc_t 2789 efx_rx_hash_default_support_get( 2790 __in efx_nic_t *enp, 2791 __out efx_rx_hash_support_t *supportp); 2792 2793 2794 LIBEFX_API 2795 extern __checkReturn efx_rc_t 2796 efx_rx_scale_default_support_get( 2797 __in efx_nic_t *enp, 2798 __out efx_rx_scale_context_type_t *typep); 2799 2800 LIBEFX_API 2801 extern __checkReturn efx_rc_t 2802 efx_rx_scale_context_alloc( 2803 __in efx_nic_t *enp, 2804 __in efx_rx_scale_context_type_t type, 2805 __in uint32_t num_queues, 2806 __out uint32_t *rss_contextp); 2807 2808 LIBEFX_API 2809 extern __checkReturn efx_rc_t 2810 efx_rx_scale_context_free( 2811 __in efx_nic_t *enp, 2812 __in uint32_t rss_context); 2813 2814 LIBEFX_API 2815 extern __checkReturn efx_rc_t 2816 efx_rx_scale_mode_set( 2817 __in efx_nic_t *enp, 2818 __in uint32_t rss_context, 2819 __in efx_rx_hash_alg_t alg, 2820 __in efx_rx_hash_type_t type, 2821 __in boolean_t insert); 2822 2823 LIBEFX_API 2824 extern __checkReturn efx_rc_t 2825 efx_rx_scale_tbl_set( 2826 __in efx_nic_t *enp, 2827 __in uint32_t rss_context, 2828 __in_ecount(n) unsigned int *table, 2829 __in size_t n); 2830 2831 LIBEFX_API 2832 extern __checkReturn efx_rc_t 2833 efx_rx_scale_key_set( 2834 __in efx_nic_t *enp, 2835 __in uint32_t rss_context, 2836 __in_ecount(n) uint8_t *key, 2837 __in size_t n); 2838 2839 LIBEFX_API 2840 extern __checkReturn uint32_t 2841 efx_pseudo_hdr_hash_get( 2842 __in efx_rxq_t *erp, 2843 __in efx_rx_hash_alg_t func, 2844 __in uint8_t *buffer); 2845 2846 #endif /* EFSYS_OPT_RX_SCALE */ 2847 2848 LIBEFX_API 2849 extern __checkReturn efx_rc_t 2850 efx_pseudo_hdr_pkt_length_get( 2851 __in efx_rxq_t *erp, 2852 __in uint8_t *buffer, 2853 __out uint16_t *pkt_lengthp); 2854 2855 LIBEFX_API 2856 extern __checkReturn size_t 2857 efx_rxq_size( 2858 __in const efx_nic_t *enp, 2859 __in unsigned int ndescs); 2860 2861 LIBEFX_API 2862 extern __checkReturn unsigned int 2863 efx_rxq_nbufs( 2864 __in const efx_nic_t *enp, 2865 __in unsigned int ndescs); 2866 2867 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16) 2868 2869 /* 2870 * libefx representation of the Rx prefix layout information. 2871 * 2872 * The information may be used inside libefx to implement Rx prefix fields 2873 * accessors and by drivers which process Rx prefix itself. 2874 */ 2875 2876 /* 2877 * All known Rx prefix fields. 2878 * 2879 * An Rx prefix may have a subset of these fields. 2880 */ 2881 typedef enum efx_rx_prefix_field_e { 2882 EFX_RX_PREFIX_FIELD_LENGTH = 0, 2883 EFX_RX_PREFIX_FIELD_ORIG_LENGTH, 2884 EFX_RX_PREFIX_FIELD_CLASS, 2885 EFX_RX_PREFIX_FIELD_RSS_HASH, 2886 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID, 2887 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP, 2888 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI, 2889 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI, 2890 EFX_RX_PREFIX_FIELD_USER_FLAG, 2891 EFX_RX_PREFIX_FIELD_USER_MARK, 2892 EFX_RX_PREFIX_FIELD_USER_MARK_VALID, 2893 EFX_RX_PREFIX_FIELD_CSUM_FRAME, 2894 EFX_RX_PREFIX_FIELD_INGRESS_VPORT, 2895 EFX_RX_PREFIX_NFIELDS 2896 } efx_rx_prefix_field_t; 2897 2898 /* 2899 * Location and endianness of a field in Rx prefix. 2900 * 2901 * If width is zero, the field is not present. 2902 */ 2903 typedef struct efx_rx_prefix_field_info_s { 2904 uint16_t erpfi_offset_bits; 2905 uint8_t erpfi_width_bits; 2906 boolean_t erpfi_big_endian; 2907 } efx_rx_prefix_field_info_t; 2908 2909 /* Helper macro to define Rx prefix fields */ 2910 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \ 2911 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \ 2912 .erpfi_offset_bits = EFX_LOW_BIT(_field), \ 2913 .erpfi_width_bits = EFX_WIDTH(_field), \ 2914 .erpfi_big_endian = (_big_endian), \ 2915 } 2916 2917 typedef struct efx_rx_prefix_layout_s { 2918 uint32_t erpl_id; 2919 uint8_t erpl_length; 2920 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS]; 2921 } efx_rx_prefix_layout_t; 2922 2923 /* 2924 * Helper function to find out a bit mask of wanted but not available 2925 * Rx prefix fields. 2926 * 2927 * A field is considered as not available if any parameter mismatch. 2928 */ 2929 LIBEFX_API 2930 extern __checkReturn uint32_t 2931 efx_rx_prefix_layout_check( 2932 __in const efx_rx_prefix_layout_t *available, 2933 __in const efx_rx_prefix_layout_t *wanted); 2934 2935 LIBEFX_API 2936 extern __checkReturn efx_rc_t 2937 efx_rx_prefix_get_layout( 2938 __in const efx_rxq_t *erp, 2939 __out efx_rx_prefix_layout_t *erplp); 2940 2941 typedef enum efx_rxq_type_e { 2942 EFX_RXQ_TYPE_DEFAULT, 2943 EFX_RXQ_TYPE_PACKED_STREAM, 2944 EFX_RXQ_TYPE_ES_SUPER_BUFFER, 2945 EFX_RXQ_NTYPES 2946 } efx_rxq_type_t; 2947 2948 /* 2949 * Dummy flag to be used instead of 0 to make it clear that the argument 2950 * is receive queue flags. 2951 */ 2952 #define EFX_RXQ_FLAG_NONE 0x0 2953 #define EFX_RXQ_FLAG_SCATTER 0x1 2954 /* 2955 * If tunnels are supported and Rx event can provide information about 2956 * either outer or inner packet classes (e.g. SFN8xxx adapters with 2957 * full-feature firmware variant running), outer classes are requested by 2958 * default. However, if the driver supports tunnels, the flag allows to 2959 * request inner classes which are required to be able to interpret inner 2960 * Rx checksum offload results. 2961 */ 2962 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2 2963 /* 2964 * Request delivery of the RSS hash calculated by HW to be used by 2965 * the driver. 2966 */ 2967 #define EFX_RXQ_FLAG_RSS_HASH 0x4 2968 2969 LIBEFX_API 2970 extern __checkReturn efx_rc_t 2971 efx_rx_qcreate( 2972 __in efx_nic_t *enp, 2973 __in unsigned int index, 2974 __in unsigned int label, 2975 __in efx_rxq_type_t type, 2976 __in size_t buf_size, 2977 __in efsys_mem_t *esmp, 2978 __in size_t ndescs, 2979 __in uint32_t id, 2980 __in unsigned int flags, 2981 __in efx_evq_t *eep, 2982 __deref_out efx_rxq_t **erpp); 2983 2984 #if EFSYS_OPT_RX_PACKED_STREAM 2985 2986 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024) 2987 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024) 2988 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024) 2989 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024) 2990 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024) 2991 2992 LIBEFX_API 2993 extern __checkReturn efx_rc_t 2994 efx_rx_qcreate_packed_stream( 2995 __in efx_nic_t *enp, 2996 __in unsigned int index, 2997 __in unsigned int label, 2998 __in uint32_t ps_buf_size, 2999 __in efsys_mem_t *esmp, 3000 __in size_t ndescs, 3001 __in efx_evq_t *eep, 3002 __deref_out efx_rxq_t **erpp); 3003 3004 #endif 3005 3006 #if EFSYS_OPT_RX_ES_SUPER_BUFFER 3007 3008 /* Maximum head-of-line block timeout in nanoseconds */ 3009 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000) 3010 3011 LIBEFX_API 3012 extern __checkReturn efx_rc_t 3013 efx_rx_qcreate_es_super_buffer( 3014 __in efx_nic_t *enp, 3015 __in unsigned int index, 3016 __in unsigned int label, 3017 __in uint32_t n_bufs_per_desc, 3018 __in uint32_t max_dma_len, 3019 __in uint32_t buf_stride, 3020 __in uint32_t hol_block_timeout, 3021 __in efsys_mem_t *esmp, 3022 __in size_t ndescs, 3023 __in unsigned int flags, 3024 __in efx_evq_t *eep, 3025 __deref_out efx_rxq_t **erpp); 3026 3027 #endif 3028 3029 typedef struct efx_buffer_s { 3030 efsys_dma_addr_t eb_addr; 3031 size_t eb_size; 3032 boolean_t eb_eop; 3033 } efx_buffer_t; 3034 3035 typedef struct efx_desc_s { 3036 efx_qword_t ed_eq; 3037 } efx_desc_t; 3038 3039 LIBEFX_API 3040 extern void 3041 efx_rx_qpost( 3042 __in efx_rxq_t *erp, 3043 __in_ecount(ndescs) efsys_dma_addr_t *addrp, 3044 __in size_t size, 3045 __in unsigned int ndescs, 3046 __in unsigned int completed, 3047 __in unsigned int added); 3048 3049 LIBEFX_API 3050 extern void 3051 efx_rx_qpush( 3052 __in efx_rxq_t *erp, 3053 __in unsigned int added, 3054 __inout unsigned int *pushedp); 3055 3056 #if EFSYS_OPT_RX_PACKED_STREAM 3057 3058 LIBEFX_API 3059 extern void 3060 efx_rx_qpush_ps_credits( 3061 __in efx_rxq_t *erp); 3062 3063 LIBEFX_API 3064 extern __checkReturn uint8_t * 3065 efx_rx_qps_packet_info( 3066 __in efx_rxq_t *erp, 3067 __in uint8_t *buffer, 3068 __in uint32_t buffer_length, 3069 __in uint32_t current_offset, 3070 __out uint16_t *lengthp, 3071 __out uint32_t *next_offsetp, 3072 __out uint32_t *timestamp); 3073 #endif 3074 3075 LIBEFX_API 3076 extern __checkReturn efx_rc_t 3077 efx_rx_qflush( 3078 __in efx_rxq_t *erp); 3079 3080 LIBEFX_API 3081 extern void 3082 efx_rx_qenable( 3083 __in efx_rxq_t *erp); 3084 3085 LIBEFX_API 3086 extern void 3087 efx_rx_qdestroy( 3088 __in efx_rxq_t *erp); 3089 3090 /* TX */ 3091 3092 typedef struct efx_txq_s efx_txq_t; 3093 3094 #if EFSYS_OPT_QSTATS 3095 3096 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */ 3097 typedef enum efx_tx_qstat_e { 3098 TX_POST, 3099 TX_POST_PIO, 3100 TX_NQSTATS 3101 } efx_tx_qstat_t; 3102 3103 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */ 3104 3105 #endif /* EFSYS_OPT_QSTATS */ 3106 3107 LIBEFX_API 3108 extern __checkReturn efx_rc_t 3109 efx_tx_init( 3110 __in efx_nic_t *enp); 3111 3112 LIBEFX_API 3113 extern void 3114 efx_tx_fini( 3115 __in efx_nic_t *enp); 3116 3117 LIBEFX_API 3118 extern __checkReturn size_t 3119 efx_txq_size( 3120 __in const efx_nic_t *enp, 3121 __in unsigned int ndescs); 3122 3123 LIBEFX_API 3124 extern __checkReturn unsigned int 3125 efx_txq_nbufs( 3126 __in const efx_nic_t *enp, 3127 __in unsigned int ndescs); 3128 3129 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16) 3130 3131 #define EFX_TXQ_CKSUM_IPV4 0x0001 3132 #define EFX_TXQ_CKSUM_TCPUDP 0x0002 3133 #define EFX_TXQ_FATSOV2 0x0004 3134 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008 3135 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010 3136 3137 LIBEFX_API 3138 extern __checkReturn efx_rc_t 3139 efx_tx_qcreate( 3140 __in efx_nic_t *enp, 3141 __in unsigned int index, 3142 __in unsigned int label, 3143 __in efsys_mem_t *esmp, 3144 __in size_t n, 3145 __in uint32_t id, 3146 __in uint16_t flags, 3147 __in efx_evq_t *eep, 3148 __deref_out efx_txq_t **etpp, 3149 __out unsigned int *addedp); 3150 3151 LIBEFX_API 3152 extern __checkReturn efx_rc_t 3153 efx_tx_qpost( 3154 __in efx_txq_t *etp, 3155 __in_ecount(ndescs) efx_buffer_t *eb, 3156 __in unsigned int ndescs, 3157 __in unsigned int completed, 3158 __inout unsigned int *addedp); 3159 3160 LIBEFX_API 3161 extern __checkReturn efx_rc_t 3162 efx_tx_qpace( 3163 __in efx_txq_t *etp, 3164 __in unsigned int ns); 3165 3166 LIBEFX_API 3167 extern void 3168 efx_tx_qpush( 3169 __in efx_txq_t *etp, 3170 __in unsigned int added, 3171 __in unsigned int pushed); 3172 3173 LIBEFX_API 3174 extern __checkReturn efx_rc_t 3175 efx_tx_qflush( 3176 __in efx_txq_t *etp); 3177 3178 LIBEFX_API 3179 extern void 3180 efx_tx_qenable( 3181 __in efx_txq_t *etp); 3182 3183 LIBEFX_API 3184 extern __checkReturn efx_rc_t 3185 efx_tx_qpio_enable( 3186 __in efx_txq_t *etp); 3187 3188 LIBEFX_API 3189 extern void 3190 efx_tx_qpio_disable( 3191 __in efx_txq_t *etp); 3192 3193 LIBEFX_API 3194 extern __checkReturn efx_rc_t 3195 efx_tx_qpio_write( 3196 __in efx_txq_t *etp, 3197 __in_ecount(buf_length) uint8_t *buffer, 3198 __in size_t buf_length, 3199 __in size_t pio_buf_offset); 3200 3201 LIBEFX_API 3202 extern __checkReturn efx_rc_t 3203 efx_tx_qpio_post( 3204 __in efx_txq_t *etp, 3205 __in size_t pkt_length, 3206 __in unsigned int completed, 3207 __inout unsigned int *addedp); 3208 3209 LIBEFX_API 3210 extern __checkReturn efx_rc_t 3211 efx_tx_qdesc_post( 3212 __in efx_txq_t *etp, 3213 __in_ecount(n) efx_desc_t *ed, 3214 __in unsigned int n, 3215 __in unsigned int completed, 3216 __inout unsigned int *addedp); 3217 3218 LIBEFX_API 3219 extern void 3220 efx_tx_qdesc_dma_create( 3221 __in efx_txq_t *etp, 3222 __in efsys_dma_addr_t addr, 3223 __in size_t size, 3224 __in boolean_t eop, 3225 __out efx_desc_t *edp); 3226 3227 LIBEFX_API 3228 extern void 3229 efx_tx_qdesc_tso_create( 3230 __in efx_txq_t *etp, 3231 __in uint16_t ipv4_id, 3232 __in uint32_t tcp_seq, 3233 __in uint8_t tcp_flags, 3234 __out efx_desc_t *edp); 3235 3236 /* Number of FATSOv2 option descriptors */ 3237 #define EFX_TX_FATSOV2_OPT_NDESCS 2 3238 3239 /* Maximum number of DMA segments per TSO packet (not superframe) */ 3240 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24 3241 3242 LIBEFX_API 3243 extern void 3244 efx_tx_qdesc_tso2_create( 3245 __in efx_txq_t *etp, 3246 __in uint16_t ipv4_id, 3247 __in uint16_t outer_ipv4_id, 3248 __in uint32_t tcp_seq, 3249 __in uint16_t tcp_mss, 3250 __out_ecount(count) efx_desc_t *edp, 3251 __in int count); 3252 3253 LIBEFX_API 3254 extern void 3255 efx_tx_qdesc_vlantci_create( 3256 __in efx_txq_t *etp, 3257 __in uint16_t tci, 3258 __out efx_desc_t *edp); 3259 3260 LIBEFX_API 3261 extern void 3262 efx_tx_qdesc_checksum_create( 3263 __in efx_txq_t *etp, 3264 __in uint16_t flags, 3265 __out efx_desc_t *edp); 3266 3267 #if EFSYS_OPT_QSTATS 3268 3269 #if EFSYS_OPT_NAMES 3270 3271 LIBEFX_API 3272 extern const char * 3273 efx_tx_qstat_name( 3274 __in efx_nic_t *etp, 3275 __in unsigned int id); 3276 3277 #endif /* EFSYS_OPT_NAMES */ 3278 3279 LIBEFX_API 3280 extern void 3281 efx_tx_qstats_update( 3282 __in efx_txq_t *etp, 3283 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat); 3284 3285 #endif /* EFSYS_OPT_QSTATS */ 3286 3287 LIBEFX_API 3288 extern void 3289 efx_tx_qdestroy( 3290 __in efx_txq_t *etp); 3291 3292 3293 /* FILTER */ 3294 3295 #if EFSYS_OPT_FILTER 3296 3297 #define EFX_ETHER_TYPE_IPV4 0x0800 3298 #define EFX_ETHER_TYPE_IPV6 0x86DD 3299 3300 #define EFX_IPPROTO_TCP 6 3301 #define EFX_IPPROTO_UDP 17 3302 #define EFX_IPPROTO_GRE 47 3303 3304 /* Use RSS to spread across multiple queues */ 3305 #define EFX_FILTER_FLAG_RX_RSS 0x01 3306 /* Enable RX scatter */ 3307 #define EFX_FILTER_FLAG_RX_SCATTER 0x02 3308 /* 3309 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO). 3310 * May only be set by the filter implementation for each type. 3311 * A removal request will restore the automatic filter in its place. 3312 */ 3313 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04 3314 /* Filter is for RX */ 3315 #define EFX_FILTER_FLAG_RX 0x08 3316 /* Filter is for TX */ 3317 #define EFX_FILTER_FLAG_TX 0x10 3318 /* Set match flag on the received packet */ 3319 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20 3320 /* Set match mark on the received packet */ 3321 #define EFX_FILTER_FLAG_ACTION_MARK 0x40 3322 3323 typedef uint8_t efx_filter_flags_t; 3324 3325 /* 3326 * Flags which specify the fields to match on. The values are the same as in the 3327 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands. 3328 */ 3329 3330 /* Match by remote IP host address */ 3331 #define EFX_FILTER_MATCH_REM_HOST 0x00000001 3332 /* Match by local IP host address */ 3333 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002 3334 /* Match by remote MAC address */ 3335 #define EFX_FILTER_MATCH_REM_MAC 0x00000004 3336 /* Match by remote TCP/UDP port */ 3337 #define EFX_FILTER_MATCH_REM_PORT 0x00000008 3338 /* Match by remote TCP/UDP port */ 3339 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010 3340 /* Match by local TCP/UDP port */ 3341 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020 3342 /* Match by Ether-type */ 3343 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040 3344 /* Match by inner VLAN ID */ 3345 #define EFX_FILTER_MATCH_INNER_VID 0x00000080 3346 /* Match by outer VLAN ID */ 3347 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100 3348 /* Match by IP transport protocol */ 3349 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200 3350 /* Match by VNI or VSID */ 3351 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800 3352 /* For encapsulated packets, match by inner frame local MAC address */ 3353 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000 3354 /* For encapsulated packets, match all multicast inner frames */ 3355 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000 3356 /* For encapsulated packets, match all unicast inner frames */ 3357 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000 3358 /* 3359 * Match by encap type, this flag does not correspond to 3360 * the MCDI match flags and any unoccupied value may be used 3361 */ 3362 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000 3363 /* Match otherwise-unmatched multicast and broadcast packets */ 3364 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000 3365 /* Match otherwise-unmatched unicast packets */ 3366 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000 3367 3368 typedef uint32_t efx_filter_match_flags_t; 3369 3370 /* Filter priority from lowest to highest */ 3371 typedef enum efx_filter_priority_s { 3372 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device 3373 * address list or hardware 3374 * requirements. This may only be used 3375 * by the filter implementation for 3376 * each NIC type. */ 3377 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */ 3378 EFX_FILTER_NPRI, 3379 } efx_filter_priority_t; 3380 3381 /* 3382 * FIXME: All these fields are assumed to be in little-endian byte order. 3383 * It may be better for some to be big-endian. See bug42804. 3384 */ 3385 3386 typedef struct efx_filter_spec_s { 3387 efx_filter_match_flags_t efs_match_flags; 3388 uint8_t efs_priority; 3389 efx_filter_flags_t efs_flags; 3390 uint16_t efs_dmaq_id; 3391 uint32_t efs_rss_context; 3392 uint32_t efs_mark; 3393 /* 3394 * Saved lower-priority filter. If it is set, it is restored on 3395 * filter delete operation. 3396 */ 3397 struct efx_filter_spec_s *efs_overridden_spec; 3398 /* Fields below here are hashed for software filter lookup */ 3399 uint16_t efs_outer_vid; 3400 uint16_t efs_inner_vid; 3401 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN]; 3402 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN]; 3403 uint16_t efs_ether_type; 3404 uint8_t efs_ip_proto; 3405 efx_tunnel_protocol_t efs_encap_type; 3406 uint16_t efs_loc_port; 3407 uint16_t efs_rem_port; 3408 efx_oword_t efs_rem_host; 3409 efx_oword_t efs_loc_host; 3410 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN]; 3411 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN]; 3412 } efx_filter_spec_t; 3413 3414 3415 /* Default values for use in filter specifications */ 3416 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff 3417 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff 3418 3419 LIBEFX_API 3420 extern __checkReturn efx_rc_t 3421 efx_filter_init( 3422 __in efx_nic_t *enp); 3423 3424 LIBEFX_API 3425 extern void 3426 efx_filter_fini( 3427 __in efx_nic_t *enp); 3428 3429 LIBEFX_API 3430 extern __checkReturn efx_rc_t 3431 efx_filter_insert( 3432 __in efx_nic_t *enp, 3433 __inout efx_filter_spec_t *spec); 3434 3435 LIBEFX_API 3436 extern __checkReturn efx_rc_t 3437 efx_filter_remove( 3438 __in efx_nic_t *enp, 3439 __inout efx_filter_spec_t *spec); 3440 3441 LIBEFX_API 3442 extern __checkReturn efx_rc_t 3443 efx_filter_restore( 3444 __in efx_nic_t *enp); 3445 3446 LIBEFX_API 3447 extern __checkReturn efx_rc_t 3448 efx_filter_supported_filters( 3449 __in efx_nic_t *enp, 3450 __out_ecount(buffer_length) uint32_t *buffer, 3451 __in size_t buffer_length, 3452 __out size_t *list_lengthp); 3453 3454 LIBEFX_API 3455 extern void 3456 efx_filter_spec_init_rx( 3457 __out efx_filter_spec_t *spec, 3458 __in efx_filter_priority_t priority, 3459 __in efx_filter_flags_t flags, 3460 __in efx_rxq_t *erp); 3461 3462 LIBEFX_API 3463 extern void 3464 efx_filter_spec_init_tx( 3465 __out efx_filter_spec_t *spec, 3466 __in efx_txq_t *etp); 3467 3468 LIBEFX_API 3469 extern __checkReturn efx_rc_t 3470 efx_filter_spec_set_ipv4_local( 3471 __inout efx_filter_spec_t *spec, 3472 __in uint8_t proto, 3473 __in uint32_t host, 3474 __in uint16_t port); 3475 3476 LIBEFX_API 3477 extern __checkReturn efx_rc_t 3478 efx_filter_spec_set_ipv4_full( 3479 __inout efx_filter_spec_t *spec, 3480 __in uint8_t proto, 3481 __in uint32_t lhost, 3482 __in uint16_t lport, 3483 __in uint32_t rhost, 3484 __in uint16_t rport); 3485 3486 LIBEFX_API 3487 extern __checkReturn efx_rc_t 3488 efx_filter_spec_set_eth_local( 3489 __inout efx_filter_spec_t *spec, 3490 __in uint16_t vid, 3491 __in const uint8_t *addr); 3492 3493 LIBEFX_API 3494 extern void 3495 efx_filter_spec_set_ether_type( 3496 __inout efx_filter_spec_t *spec, 3497 __in uint16_t ether_type); 3498 3499 LIBEFX_API 3500 extern __checkReturn efx_rc_t 3501 efx_filter_spec_set_uc_def( 3502 __inout efx_filter_spec_t *spec); 3503 3504 LIBEFX_API 3505 extern __checkReturn efx_rc_t 3506 efx_filter_spec_set_mc_def( 3507 __inout efx_filter_spec_t *spec); 3508 3509 typedef enum efx_filter_inner_frame_match_e { 3510 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0, 3511 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST, 3512 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST 3513 } efx_filter_inner_frame_match_t; 3514 3515 LIBEFX_API 3516 extern __checkReturn efx_rc_t 3517 efx_filter_spec_set_encap_type( 3518 __inout efx_filter_spec_t *spec, 3519 __in efx_tunnel_protocol_t encap_type, 3520 __in efx_filter_inner_frame_match_t inner_frame_match); 3521 3522 LIBEFX_API 3523 extern __checkReturn efx_rc_t 3524 efx_filter_spec_set_vxlan( 3525 __inout efx_filter_spec_t *spec, 3526 __in const uint8_t *vni, 3527 __in const uint8_t *inner_addr, 3528 __in const uint8_t *outer_addr); 3529 3530 LIBEFX_API 3531 extern __checkReturn efx_rc_t 3532 efx_filter_spec_set_geneve( 3533 __inout efx_filter_spec_t *spec, 3534 __in const uint8_t *vni, 3535 __in const uint8_t *inner_addr, 3536 __in const uint8_t *outer_addr); 3537 3538 LIBEFX_API 3539 extern __checkReturn efx_rc_t 3540 efx_filter_spec_set_nvgre( 3541 __inout efx_filter_spec_t *spec, 3542 __in const uint8_t *vsid, 3543 __in const uint8_t *inner_addr, 3544 __in const uint8_t *outer_addr); 3545 3546 #if EFSYS_OPT_RX_SCALE 3547 LIBEFX_API 3548 extern __checkReturn efx_rc_t 3549 efx_filter_spec_set_rss_context( 3550 __inout efx_filter_spec_t *spec, 3551 __in uint32_t rss_context); 3552 #endif 3553 #endif /* EFSYS_OPT_FILTER */ 3554 3555 /* HASH */ 3556 3557 LIBEFX_API 3558 extern __checkReturn uint32_t 3559 efx_hash_dwords( 3560 __in_ecount(count) uint32_t const *input, 3561 __in size_t count, 3562 __in uint32_t init); 3563 3564 LIBEFX_API 3565 extern __checkReturn uint32_t 3566 efx_hash_bytes( 3567 __in_ecount(length) uint8_t const *input, 3568 __in size_t length, 3569 __in uint32_t init); 3570 3571 #if EFSYS_OPT_LICENSING 3572 3573 /* LICENSING */ 3574 3575 typedef struct efx_key_stats_s { 3576 uint32_t eks_valid; 3577 uint32_t eks_invalid; 3578 uint32_t eks_blacklisted; 3579 uint32_t eks_unverifiable; 3580 uint32_t eks_wrong_node; 3581 uint32_t eks_licensed_apps_lo; 3582 uint32_t eks_licensed_apps_hi; 3583 uint32_t eks_licensed_features_lo; 3584 uint32_t eks_licensed_features_hi; 3585 } efx_key_stats_t; 3586 3587 LIBEFX_API 3588 extern __checkReturn efx_rc_t 3589 efx_lic_init( 3590 __in efx_nic_t *enp); 3591 3592 LIBEFX_API 3593 extern void 3594 efx_lic_fini( 3595 __in efx_nic_t *enp); 3596 3597 LIBEFX_API 3598 extern __checkReturn boolean_t 3599 efx_lic_check_support( 3600 __in efx_nic_t *enp); 3601 3602 LIBEFX_API 3603 extern __checkReturn efx_rc_t 3604 efx_lic_update_licenses( 3605 __in efx_nic_t *enp); 3606 3607 LIBEFX_API 3608 extern __checkReturn efx_rc_t 3609 efx_lic_get_key_stats( 3610 __in efx_nic_t *enp, 3611 __out efx_key_stats_t *ksp); 3612 3613 LIBEFX_API 3614 extern __checkReturn efx_rc_t 3615 efx_lic_app_state( 3616 __in efx_nic_t *enp, 3617 __in uint64_t app_id, 3618 __out boolean_t *licensedp); 3619 3620 LIBEFX_API 3621 extern __checkReturn efx_rc_t 3622 efx_lic_get_id( 3623 __in efx_nic_t *enp, 3624 __in size_t buffer_size, 3625 __out uint32_t *typep, 3626 __out size_t *lengthp, 3627 __out_opt uint8_t *bufferp); 3628 3629 3630 LIBEFX_API 3631 extern __checkReturn efx_rc_t 3632 efx_lic_find_start( 3633 __in efx_nic_t *enp, 3634 __in_bcount(buffer_size) 3635 caddr_t bufferp, 3636 __in size_t buffer_size, 3637 __out uint32_t *startp); 3638 3639 LIBEFX_API 3640 extern __checkReturn efx_rc_t 3641 efx_lic_find_end( 3642 __in efx_nic_t *enp, 3643 __in_bcount(buffer_size) 3644 caddr_t bufferp, 3645 __in size_t buffer_size, 3646 __in uint32_t offset, 3647 __out uint32_t *endp); 3648 3649 LIBEFX_API 3650 extern __checkReturn __success(return != B_FALSE) boolean_t 3651 efx_lic_find_key( 3652 __in efx_nic_t *enp, 3653 __in_bcount(buffer_size) 3654 caddr_t bufferp, 3655 __in size_t buffer_size, 3656 __in uint32_t offset, 3657 __out uint32_t *startp, 3658 __out uint32_t *lengthp); 3659 3660 LIBEFX_API 3661 extern __checkReturn __success(return != B_FALSE) boolean_t 3662 efx_lic_validate_key( 3663 __in efx_nic_t *enp, 3664 __in_bcount(length) caddr_t keyp, 3665 __in uint32_t length); 3666 3667 LIBEFX_API 3668 extern __checkReturn efx_rc_t 3669 efx_lic_read_key( 3670 __in efx_nic_t *enp, 3671 __in_bcount(buffer_size) 3672 caddr_t bufferp, 3673 __in size_t buffer_size, 3674 __in uint32_t offset, 3675 __in uint32_t length, 3676 __out_bcount_part(key_max_size, *lengthp) 3677 caddr_t keyp, 3678 __in size_t key_max_size, 3679 __out uint32_t *lengthp); 3680 3681 LIBEFX_API 3682 extern __checkReturn efx_rc_t 3683 efx_lic_write_key( 3684 __in efx_nic_t *enp, 3685 __in_bcount(buffer_size) 3686 caddr_t bufferp, 3687 __in size_t buffer_size, 3688 __in uint32_t offset, 3689 __in_bcount(length) caddr_t keyp, 3690 __in uint32_t length, 3691 __out uint32_t *lengthp); 3692 3693 LIBEFX_API 3694 extern __checkReturn efx_rc_t 3695 efx_lic_delete_key( 3696 __in efx_nic_t *enp, 3697 __in_bcount(buffer_size) 3698 caddr_t bufferp, 3699 __in size_t buffer_size, 3700 __in uint32_t offset, 3701 __in uint32_t length, 3702 __in uint32_t end, 3703 __out uint32_t *deltap); 3704 3705 LIBEFX_API 3706 extern __checkReturn efx_rc_t 3707 efx_lic_create_partition( 3708 __in efx_nic_t *enp, 3709 __in_bcount(buffer_size) 3710 caddr_t bufferp, 3711 __in size_t buffer_size); 3712 3713 extern __checkReturn efx_rc_t 3714 efx_lic_finish_partition( 3715 __in efx_nic_t *enp, 3716 __in_bcount(buffer_size) 3717 caddr_t bufferp, 3718 __in size_t buffer_size); 3719 3720 #endif /* EFSYS_OPT_LICENSING */ 3721 3722 /* TUNNEL */ 3723 3724 #if EFSYS_OPT_TUNNEL 3725 3726 LIBEFX_API 3727 extern __checkReturn efx_rc_t 3728 efx_tunnel_init( 3729 __in efx_nic_t *enp); 3730 3731 LIBEFX_API 3732 extern void 3733 efx_tunnel_fini( 3734 __in efx_nic_t *enp); 3735 3736 /* 3737 * For overlay network encapsulation using UDP, the firmware needs to know 3738 * the configured UDP port for the overlay so it can decode encapsulated 3739 * frames correctly. 3740 * The UDP port/protocol list is global. 3741 */ 3742 3743 LIBEFX_API 3744 extern __checkReturn efx_rc_t 3745 efx_tunnel_config_udp_add( 3746 __in efx_nic_t *enp, 3747 __in uint16_t port /* host/cpu-endian */, 3748 __in efx_tunnel_protocol_t protocol); 3749 3750 /* 3751 * Returns EBUSY if reconfiguration of the port is in progress in other thread. 3752 */ 3753 LIBEFX_API 3754 extern __checkReturn efx_rc_t 3755 efx_tunnel_config_udp_remove( 3756 __in efx_nic_t *enp, 3757 __in uint16_t port /* host/cpu-endian */, 3758 __in efx_tunnel_protocol_t protocol); 3759 3760 /* 3761 * Returns EBUSY if reconfiguration of any of the tunnel entries 3762 * is in progress in other thread. 3763 */ 3764 LIBEFX_API 3765 extern __checkReturn efx_rc_t 3766 efx_tunnel_config_clear( 3767 __in efx_nic_t *enp); 3768 3769 /** 3770 * Apply tunnel UDP ports configuration to hardware. 3771 * 3772 * EAGAIN is returned if hardware will be reset (datapath and managment CPU 3773 * reboot). 3774 */ 3775 LIBEFX_API 3776 extern __checkReturn efx_rc_t 3777 efx_tunnel_reconfigure( 3778 __in efx_nic_t *enp); 3779 3780 #endif /* EFSYS_OPT_TUNNEL */ 3781 3782 #if EFSYS_OPT_FW_SUBVARIANT_AWARE 3783 3784 /** 3785 * Firmware subvariant choice options. 3786 * 3787 * It may be switched to no Tx checksum if attached drivers are either 3788 * preboot or firmware subvariant aware and no VIS are allocated. 3789 * If may be always switched to default explicitly using set request or 3790 * implicitly if unaware driver is attaching. If switching is done when 3791 * a driver is attached, it gets MC_REBOOT event and should recreate its 3792 * datapath. 3793 * 3794 * See SF-119419-TC DPDK Firmware Driver Interface and 3795 * SF-109306-TC EF10 for Driver Writers for details. 3796 */ 3797 typedef enum efx_nic_fw_subvariant_e { 3798 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0, 3799 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1, 3800 EFX_NIC_FW_SUBVARIANT_NTYPES 3801 } efx_nic_fw_subvariant_t; 3802 3803 LIBEFX_API 3804 extern __checkReturn efx_rc_t 3805 efx_nic_get_fw_subvariant( 3806 __in efx_nic_t *enp, 3807 __out efx_nic_fw_subvariant_t *subvariantp); 3808 3809 LIBEFX_API 3810 extern __checkReturn efx_rc_t 3811 efx_nic_set_fw_subvariant( 3812 __in efx_nic_t *enp, 3813 __in efx_nic_fw_subvariant_t subvariant); 3814 3815 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */ 3816 3817 typedef enum efx_phy_fec_type_e { 3818 EFX_PHY_FEC_NONE = 0, 3819 EFX_PHY_FEC_BASER, 3820 EFX_PHY_FEC_RS 3821 } efx_phy_fec_type_t; 3822 3823 LIBEFX_API 3824 extern __checkReturn efx_rc_t 3825 efx_phy_fec_type_get( 3826 __in efx_nic_t *enp, 3827 __out efx_phy_fec_type_t *typep); 3828 3829 typedef struct efx_phy_link_state_s { 3830 uint32_t epls_adv_cap_mask; 3831 uint32_t epls_lp_cap_mask; 3832 uint32_t epls_ld_cap_mask; 3833 unsigned int epls_fcntl; 3834 efx_phy_fec_type_t epls_fec; 3835 efx_link_mode_t epls_link_mode; 3836 } efx_phy_link_state_t; 3837 3838 LIBEFX_API 3839 extern __checkReturn efx_rc_t 3840 efx_phy_link_state_get( 3841 __in efx_nic_t *enp, 3842 __out efx_phy_link_state_t *eplsp); 3843 3844 3845 #if EFSYS_OPT_EVB 3846 3847 typedef uint32_t efx_vswitch_id_t; 3848 typedef uint32_t efx_vport_id_t; 3849 3850 typedef enum efx_vswitch_type_e { 3851 EFX_VSWITCH_TYPE_VLAN = 1, 3852 EFX_VSWITCH_TYPE_VEB, 3853 /* VSWITCH_TYPE_VEPA: obsolete */ 3854 EFX_VSWITCH_TYPE_MUX = 4, 3855 } efx_vswitch_type_t; 3856 3857 typedef enum efx_vport_type_e { 3858 EFX_VPORT_TYPE_NORMAL = 4, 3859 EFX_VPORT_TYPE_EXPANSION, 3860 EFX_VPORT_TYPE_TEST, 3861 } efx_vport_type_t; 3862 3863 /* Unspecified VLAN ID to support disabling of VLAN filtering */ 3864 #define EFX_FILTER_VID_UNSPEC 0xffff 3865 #define EFX_DEFAULT_VSWITCH_ID 1 3866 3867 /* Default VF VLAN ID on creation */ 3868 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC 3869 #define EFX_VPORT_ID_INVALID 0 3870 3871 typedef struct efx_vport_config_s { 3872 /* Either VF index or 0xffff for PF */ 3873 uint16_t evc_function; 3874 /* VLAN ID of the associated function */ 3875 uint16_t evc_vid; 3876 /* vport id shared with client driver */ 3877 efx_vport_id_t evc_vport_id; 3878 /* MAC address of the associated function */ 3879 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN]; 3880 /* 3881 * vports created with this flag set may only transfer traffic on the 3882 * VLANs permitted by the vport. Also, an attempt to install filter with 3883 * VLAN will be refused unless requesting function has VLAN privilege. 3884 */ 3885 boolean_t evc_vlan_restrict; 3886 /* Whether this function is assigned or not */ 3887 boolean_t evc_vport_assigned; 3888 } efx_vport_config_t; 3889 3890 typedef struct efx_vswitch_s efx_vswitch_t; 3891 3892 LIBEFX_API 3893 extern __checkReturn efx_rc_t 3894 efx_evb_init( 3895 __in efx_nic_t *enp); 3896 3897 LIBEFX_API 3898 extern void 3899 efx_evb_fini( 3900 __in efx_nic_t *enp); 3901 3902 LIBEFX_API 3903 extern __checkReturn efx_rc_t 3904 efx_evb_vswitch_create( 3905 __in efx_nic_t *enp, 3906 __in uint32_t num_vports, 3907 __inout_ecount(num_vports) efx_vport_config_t *vport_configp, 3908 __deref_out efx_vswitch_t **evpp); 3909 3910 LIBEFX_API 3911 extern __checkReturn efx_rc_t 3912 efx_evb_vswitch_destroy( 3913 __in efx_nic_t *enp, 3914 __in efx_vswitch_t *evp); 3915 3916 LIBEFX_API 3917 extern __checkReturn efx_rc_t 3918 efx_evb_vport_mac_set( 3919 __in efx_nic_t *enp, 3920 __in efx_vswitch_t *evp, 3921 __in efx_vport_id_t vport_id, 3922 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp); 3923 3924 LIBEFX_API 3925 extern __checkReturn efx_rc_t 3926 efx_evb_vport_vlan_set( 3927 __in efx_nic_t *enp, 3928 __in efx_vswitch_t *evp, 3929 __in efx_vport_id_t vport_id, 3930 __in uint16_t vid); 3931 3932 LIBEFX_API 3933 extern __checkReturn efx_rc_t 3934 efx_evb_vport_reset( 3935 __in efx_nic_t *enp, 3936 __in efx_vswitch_t *evp, 3937 __in efx_vport_id_t vport_id, 3938 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp, 3939 __in uint16_t vid, 3940 __out boolean_t *is_fn_resetp); 3941 3942 LIBEFX_API 3943 extern __checkReturn efx_rc_t 3944 efx_evb_vport_stats( 3945 __in efx_nic_t *enp, 3946 __in efx_vswitch_t *evp, 3947 __in efx_vport_id_t vport_id, 3948 __out efsys_mem_t *stats_bufferp); 3949 3950 #endif /* EFSYS_OPT_EVB */ 3951 3952 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER 3953 3954 typedef struct efx_proxy_auth_config_s { 3955 efsys_mem_t *request_bufferp; 3956 efsys_mem_t *response_bufferp; 3957 efsys_mem_t *status_bufferp; 3958 uint32_t block_cnt; 3959 uint32_t *op_listp; 3960 size_t op_count; 3961 uint32_t handled_privileges; 3962 } efx_proxy_auth_config_t; 3963 3964 typedef struct efx_proxy_cmd_params_s { 3965 uint32_t pf_index; 3966 uint32_t vf_index; 3967 uint8_t *request_bufferp; 3968 size_t request_size; 3969 uint8_t *response_bufferp; 3970 size_t response_size; 3971 size_t *response_size_actualp; 3972 } efx_proxy_cmd_params_t; 3973 3974 LIBEFX_API 3975 extern __checkReturn efx_rc_t 3976 efx_proxy_auth_init( 3977 __in efx_nic_t *enp); 3978 3979 LIBEFX_API 3980 extern void 3981 efx_proxy_auth_fini( 3982 __in efx_nic_t *enp); 3983 3984 LIBEFX_API 3985 extern __checkReturn efx_rc_t 3986 efx_proxy_auth_configure( 3987 __in efx_nic_t *enp, 3988 __in efx_proxy_auth_config_t *configp); 3989 3990 LIBEFX_API 3991 extern __checkReturn efx_rc_t 3992 efx_proxy_auth_destroy( 3993 __in efx_nic_t *enp, 3994 __in uint32_t handled_privileges); 3995 3996 LIBEFX_API 3997 extern __checkReturn efx_rc_t 3998 efx_proxy_auth_complete_request( 3999 __in efx_nic_t *enp, 4000 __in uint32_t fn_index, 4001 __in uint32_t proxy_result, 4002 __in uint32_t handle); 4003 4004 LIBEFX_API 4005 extern __checkReturn efx_rc_t 4006 efx_proxy_auth_exec_cmd( 4007 __in efx_nic_t *enp, 4008 __inout efx_proxy_cmd_params_t *paramsp); 4009 4010 LIBEFX_API 4011 extern __checkReturn efx_rc_t 4012 efx_proxy_auth_set_privilege_mask( 4013 __in efx_nic_t *enp, 4014 __in uint32_t vf_index, 4015 __in uint32_t mask, 4016 __in uint32_t value); 4017 4018 LIBEFX_API 4019 extern __checkReturn efx_rc_t 4020 efx_proxy_auth_privilege_mask_get( 4021 __in efx_nic_t *enp, 4022 __in uint32_t pf_index, 4023 __in uint32_t vf_index, 4024 __out uint32_t *maskp); 4025 4026 LIBEFX_API 4027 extern __checkReturn efx_rc_t 4028 efx_proxy_auth_privilege_modify( 4029 __in efx_nic_t *enp, 4030 __in uint32_t pf_index, 4031 __in uint32_t vf_index, 4032 __in uint32_t add_privileges_mask, 4033 __in uint32_t remove_privileges_mask); 4034 4035 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */ 4036 4037 #ifdef __cplusplus 4038 } 4039 #endif 4040 4041 #endif /* _SYS_EFX_H */ 4042