1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2012-2019 Solarflare Communications Inc.
5 */
6
7 #include "efx.h"
8 #include "efx_impl.h"
9
10
11 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
12
13 __checkReturn efx_rc_t
ef10_mac_poll(__in efx_nic_t * enp,__out efx_link_mode_t * link_modep)14 ef10_mac_poll(
15 __in efx_nic_t *enp,
16 __out efx_link_mode_t *link_modep)
17 {
18 efx_port_t *epp = &(enp->en_port);
19 ef10_link_state_t els;
20 efx_rc_t rc;
21
22 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
23 goto fail1;
24
25 epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
26 epp->ep_fcntl = els.epls.epls_fcntl;
27
28 *link_modep = els.epls.epls_link_mode;
29
30 return (0);
31
32 fail1:
33 EFSYS_PROBE1(fail1, efx_rc_t, rc);
34
35 *link_modep = EFX_LINK_UNKNOWN;
36
37 return (rc);
38 }
39
40 __checkReturn efx_rc_t
ef10_mac_up(__in efx_nic_t * enp,__out boolean_t * mac_upp)41 ef10_mac_up(
42 __in efx_nic_t *enp,
43 __out boolean_t *mac_upp)
44 {
45 ef10_link_state_t els;
46 efx_rc_t rc;
47
48 /*
49 * Because EF10 doesn't *require* polling, we can't rely on
50 * ef10_mac_poll() being executed to populate epp->ep_mac_up.
51 */
52 if ((rc = ef10_phy_get_link(enp, &els)) != 0)
53 goto fail1;
54
55 *mac_upp = els.els_mac_up;
56
57 return (0);
58
59 fail1:
60 EFSYS_PROBE1(fail1, efx_rc_t, rc);
61
62 return (rc);
63 }
64
65 /*
66 * EF10 adapters use MC_CMD_VADAPTOR_SET_MAC to set the
67 * MAC address; the address field in MC_CMD_SET_MAC has no
68 * effect.
69 * MC_CMD_VADAPTOR_SET_MAC requires mac-spoofing privilege and
70 * the port to have no filters or queues active.
71 */
72 static __checkReturn efx_rc_t
efx_mcdi_vadapter_set_mac(__in efx_nic_t * enp)73 efx_mcdi_vadapter_set_mac(
74 __in efx_nic_t *enp)
75 {
76 efx_port_t *epp = &(enp->en_port);
77 efx_mcdi_req_t req;
78 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_VADAPTOR_SET_MAC_IN_LEN,
79 MC_CMD_VADAPTOR_SET_MAC_OUT_LEN);
80 efx_rc_t rc;
81
82 req.emr_cmd = MC_CMD_VADAPTOR_SET_MAC;
83 req.emr_in_buf = payload;
84 req.emr_in_length = MC_CMD_VADAPTOR_SET_MAC_IN_LEN;
85 req.emr_out_buf = payload;
86 req.emr_out_length = MC_CMD_VADAPTOR_SET_MAC_OUT_LEN;
87
88 MCDI_IN_SET_DWORD(req, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
89 enp->en_vport_id);
90 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, VADAPTOR_SET_MAC_IN_MACADDR),
91 epp->ep_mac_addr);
92
93 efx_mcdi_execute(enp, &req);
94
95 if (req.emr_rc != 0) {
96 rc = req.emr_rc;
97 goto fail1;
98 }
99
100 return (0);
101
102 fail1:
103 EFSYS_PROBE1(fail1, efx_rc_t, rc);
104
105 return (rc);
106 }
107
108 __checkReturn efx_rc_t
ef10_mac_addr_set(__in efx_nic_t * enp)109 ef10_mac_addr_set(
110 __in efx_nic_t *enp)
111 {
112 efx_rc_t rc;
113
114 if ((rc = efx_mcdi_vadapter_set_mac(enp)) != 0) {
115 if (rc != ENOTSUP)
116 goto fail1;
117
118 /*
119 * Fallback for older Huntington firmware without Vadapter
120 * support.
121 */
122 if ((rc = ef10_mac_reconfigure(enp)) != 0)
123 goto fail2;
124 }
125
126 return (0);
127
128 fail2:
129 EFSYS_PROBE(fail2);
130
131 fail1:
132 EFSYS_PROBE1(fail1, efx_rc_t, rc);
133
134 return (rc);
135 }
136
137 static __checkReturn efx_rc_t
efx_mcdi_mtu_set(__in efx_nic_t * enp,__in uint32_t mtu)138 efx_mcdi_mtu_set(
139 __in efx_nic_t *enp,
140 __in uint32_t mtu)
141 {
142 efx_mcdi_req_t req;
143 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_MAC_EXT_IN_LEN,
144 MC_CMD_SET_MAC_OUT_LEN);
145 efx_rc_t rc;
146
147 req.emr_cmd = MC_CMD_SET_MAC;
148 req.emr_in_buf = payload;
149 req.emr_in_length = MC_CMD_SET_MAC_EXT_IN_LEN;
150 req.emr_out_buf = payload;
151 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN;
152
153 /* Only configure the MTU in this call to MC_CMD_SET_MAC */
154 MCDI_IN_SET_DWORD(req, SET_MAC_EXT_IN_MTU, mtu);
155 MCDI_IN_POPULATE_DWORD_1(req, SET_MAC_EXT_IN_CONTROL,
156 SET_MAC_EXT_IN_CFG_MTU, 1);
157
158 efx_mcdi_execute(enp, &req);
159
160 if (req.emr_rc != 0) {
161 rc = req.emr_rc;
162 goto fail1;
163 }
164
165 return (0);
166
167 fail1:
168 EFSYS_PROBE1(fail1, efx_rc_t, rc);
169
170 return (rc);
171 }
172
173 static __checkReturn efx_rc_t
efx_mcdi_mtu_get(__in efx_nic_t * enp,__out size_t * mtu)174 efx_mcdi_mtu_get(
175 __in efx_nic_t *enp,
176 __out size_t *mtu)
177 {
178 efx_mcdi_req_t req;
179 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_MAC_EXT_IN_LEN,
180 MC_CMD_SET_MAC_V2_OUT_LEN);
181 efx_rc_t rc;
182
183 req.emr_cmd = MC_CMD_SET_MAC;
184 req.emr_in_buf = payload;
185 req.emr_in_length = MC_CMD_SET_MAC_EXT_IN_LEN;
186 req.emr_out_buf = payload;
187 req.emr_out_length = MC_CMD_SET_MAC_V2_OUT_LEN;
188
189 /*
190 * With MC_CMD_SET_MAC_EXT_IN_CONTROL set to 0, this just queries the
191 * MTU. This should always be supported on Medford, but it is not
192 * supported on older Huntington firmware.
193 */
194 MCDI_IN_SET_DWORD(req, SET_MAC_EXT_IN_CONTROL, 0);
195
196 efx_mcdi_execute(enp, &req);
197
198 if (req.emr_rc != 0) {
199 rc = req.emr_rc;
200 goto fail1;
201 }
202 if (req.emr_out_length_used < MC_CMD_SET_MAC_V2_OUT_MTU_OFST + 4) {
203 rc = EMSGSIZE;
204 goto fail2;
205 }
206
207 *mtu = MCDI_OUT_DWORD(req, SET_MAC_V2_OUT_MTU);
208
209 return (0);
210
211 fail2:
212 EFSYS_PROBE(fail2);
213 fail1:
214 EFSYS_PROBE1(fail1, efx_rc_t, rc);
215
216 return (rc);
217 }
218
219 __checkReturn efx_rc_t
ef10_mac_pdu_set(__in efx_nic_t * enp)220 ef10_mac_pdu_set(
221 __in efx_nic_t *enp)
222 {
223 efx_port_t *epp = &(enp->en_port);
224 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
225 efx_rc_t rc;
226
227 if (encp->enc_enhanced_set_mac_supported) {
228 if ((rc = efx_mcdi_mtu_set(enp, epp->ep_mac_pdu)) != 0)
229 goto fail1;
230 } else {
231 /*
232 * Fallback for older Huntington firmware, which always
233 * configure all of the parameters to MC_CMD_SET_MAC. This isn't
234 * suitable for setting the MTU on unpriviliged functions.
235 */
236 if ((rc = ef10_mac_reconfigure(enp)) != 0)
237 goto fail2;
238 }
239
240 return (0);
241
242 fail2:
243 EFSYS_PROBE(fail2);
244 fail1:
245 EFSYS_PROBE1(fail1, efx_rc_t, rc);
246
247 return (rc);
248 }
249
250 __checkReturn efx_rc_t
ef10_mac_pdu_get(__in efx_nic_t * enp,__out size_t * pdu)251 ef10_mac_pdu_get(
252 __in efx_nic_t *enp,
253 __out size_t *pdu)
254 {
255 efx_rc_t rc;
256
257 if ((rc = efx_mcdi_mtu_get(enp, pdu)) != 0)
258 goto fail1;
259
260 return (0);
261
262 fail1:
263 EFSYS_PROBE1(fail1, efx_rc_t, rc);
264
265 return (rc);
266 }
267
268 __checkReturn efx_rc_t
ef10_mac_reconfigure(__in efx_nic_t * enp)269 ef10_mac_reconfigure(
270 __in efx_nic_t *enp)
271 {
272 efx_port_t *epp = &(enp->en_port);
273 efx_mcdi_req_t req;
274 EFX_MCDI_DECLARE_BUF(payload, MC_CMD_SET_MAC_IN_LEN,
275 MC_CMD_SET_MAC_OUT_LEN);
276 efx_rc_t rc;
277
278 req.emr_cmd = MC_CMD_SET_MAC;
279 req.emr_in_buf = payload;
280 req.emr_in_length = MC_CMD_SET_MAC_IN_LEN;
281 req.emr_out_buf = payload;
282 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN;
283
284 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu);
285 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0);
286 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR),
287 epp->ep_mac_addr);
288
289 /*
290 * Note: The Huntington MAC does not support REJECT_BRDCST.
291 * The REJECT_UNCST flag will also prevent multicast traffic
292 * from reaching the filters. As Huntington filters drop any
293 * traffic that does not match a filter it is ok to leave the
294 * MAC running in promiscuous mode. See bug41141.
295 *
296 * FIXME: Does REJECT_UNCST behave the same way on Medford?
297 */
298 MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT,
299 SET_MAC_IN_REJECT_UNCST, 0,
300 SET_MAC_IN_REJECT_BRDCST, 0);
301
302 /*
303 * Flow control, whether it is auto-negotiated or not,
304 * is set via the PHY advertised capabilities. When set to
305 * automatic the MAC will use the PHY settings to determine
306 * the flow control settings.
307 */
308 MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, MC_CMD_FCNTL_AUTO);
309
310 /* Include the Ethernet frame checksum in RX packets if it's required */
311 MCDI_IN_POPULATE_DWORD_1(req, SET_MAC_IN_FLAGS,
312 SET_MAC_IN_FLAG_INCLUDE_FCS,
313 epp->ep_include_fcs ? 1 : 0);
314
315 efx_mcdi_execute_quiet(enp, &req);
316
317 if (req.emr_rc != 0) {
318 /*
319 * Unprivileged functions cannot control link state,
320 * but still need to configure filters.
321 */
322 if (req.emr_rc != EACCES) {
323 rc = req.emr_rc;
324 goto fail1;
325 }
326 }
327
328 /*
329 * Apply the filters for the MAC configuration.
330 * If the NIC isn't ready to accept filters this may
331 * return success without setting anything.
332 */
333 rc = efx_filter_reconfigure(enp, epp->ep_mac_addr,
334 epp->ep_all_unicst, epp->ep_mulcst,
335 epp->ep_all_mulcst, epp->ep_brdcst,
336 epp->ep_mulcst_addr_list,
337 epp->ep_mulcst_addr_count);
338
339 return (0);
340
341 fail1:
342 EFSYS_PROBE1(fail1, efx_rc_t, rc);
343
344 return (rc);
345 }
346
347 __checkReturn efx_rc_t
ef10_mac_multicast_list_set(__in efx_nic_t * enp)348 ef10_mac_multicast_list_set(
349 __in efx_nic_t *enp)
350 {
351 efx_port_t *epp = &(enp->en_port);
352 const efx_mac_ops_t *emop = epp->ep_emop;
353 efx_rc_t rc;
354
355 EFSYS_ASSERT(EFX_FAMILY_IS_EF100(enp) || EFX_FAMILY_IS_EF10(enp));
356
357 if ((rc = emop->emo_reconfigure(enp)) != 0)
358 goto fail1;
359
360 return (0);
361
362 fail1:
363 EFSYS_PROBE1(fail1, efx_rc_t, rc);
364
365 return (rc);
366 }
367
368 __checkReturn efx_rc_t
ef10_mac_filter_default_rxq_set(__in efx_nic_t * enp,__in efx_rxq_t * erp,__in boolean_t using_rss)369 ef10_mac_filter_default_rxq_set(
370 __in efx_nic_t *enp,
371 __in efx_rxq_t *erp,
372 __in boolean_t using_rss)
373 {
374 efx_port_t *epp = &(enp->en_port);
375 efx_rxq_t *old_rxq;
376 boolean_t old_using_rss;
377 efx_rc_t rc;
378
379 ef10_filter_get_default_rxq(enp, &old_rxq, &old_using_rss);
380
381 ef10_filter_default_rxq_set(enp, erp, using_rss);
382
383 rc = efx_filter_reconfigure(enp, epp->ep_mac_addr,
384 epp->ep_all_unicst, epp->ep_mulcst,
385 epp->ep_all_mulcst, epp->ep_brdcst,
386 epp->ep_mulcst_addr_list,
387 epp->ep_mulcst_addr_count);
388
389 if (rc != 0)
390 goto fail1;
391
392 return (0);
393
394 fail1:
395 EFSYS_PROBE1(fail1, efx_rc_t, rc);
396
397 ef10_filter_default_rxq_set(enp, old_rxq, old_using_rss);
398
399 return (rc);
400 }
401
402 void
ef10_mac_filter_default_rxq_clear(__in efx_nic_t * enp)403 ef10_mac_filter_default_rxq_clear(
404 __in efx_nic_t *enp)
405 {
406 efx_port_t *epp = &(enp->en_port);
407
408 ef10_filter_default_rxq_clear(enp);
409
410 (void) efx_filter_reconfigure(enp, epp->ep_mac_addr,
411 epp->ep_all_unicst, epp->ep_mulcst,
412 epp->ep_all_mulcst, epp->ep_brdcst,
413 epp->ep_mulcst_addr_list,
414 epp->ep_mulcst_addr_count);
415 }
416
417
418 #if EFSYS_OPT_LOOPBACK
419
420 __checkReturn efx_rc_t
ef10_mac_loopback_set(__in efx_nic_t * enp,__in efx_link_mode_t link_mode,__in efx_loopback_type_t loopback_type)421 ef10_mac_loopback_set(
422 __in efx_nic_t *enp,
423 __in efx_link_mode_t link_mode,
424 __in efx_loopback_type_t loopback_type)
425 {
426 efx_port_t *epp = &(enp->en_port);
427 const efx_phy_ops_t *epop = epp->ep_epop;
428 efx_loopback_type_t old_loopback_type;
429 efx_link_mode_t old_loopback_link_mode;
430 efx_rc_t rc;
431
432 /* The PHY object handles this on EF10 */
433 old_loopback_type = epp->ep_loopback_type;
434 old_loopback_link_mode = epp->ep_loopback_link_mode;
435 epp->ep_loopback_type = loopback_type;
436 epp->ep_loopback_link_mode = link_mode;
437
438 if ((rc = epop->epo_reconfigure(enp)) != 0)
439 goto fail1;
440
441 return (0);
442
443 fail1:
444 EFSYS_PROBE1(fail1, efx_rc_t, rc);
445
446 epp->ep_loopback_type = old_loopback_type;
447 epp->ep_loopback_link_mode = old_loopback_link_mode;
448
449 return (rc);
450 }
451
452 #endif /* EFSYS_OPT_LOOPBACK */
453
454 #if EFSYS_OPT_MAC_STATS
455
456 __checkReturn efx_rc_t
ef10_mac_stats_get_mask(__in efx_nic_t * enp,__inout_bcount (mask_size)uint32_t * maskp,__in size_t mask_size)457 ef10_mac_stats_get_mask(
458 __in efx_nic_t *enp,
459 __inout_bcount(mask_size) uint32_t *maskp,
460 __in size_t mask_size)
461 {
462 const struct efx_mac_stats_range ef10_common[] = {
463 { EFX_MAC_RX_OCTETS, EFX_MAC_RX_GE_15XX_PKTS },
464 { EFX_MAC_RX_FCS_ERRORS, EFX_MAC_RX_DROP_EVENTS },
465 { EFX_MAC_RX_JABBER_PKTS, EFX_MAC_RX_JABBER_PKTS },
466 { EFX_MAC_RX_NODESC_DROP_CNT, EFX_MAC_TX_PAUSE_PKTS },
467 };
468 const struct efx_mac_stats_range ef10_tx_size_bins[] = {
469 { EFX_MAC_TX_LE_64_PKTS, EFX_MAC_TX_GE_15XX_PKTS },
470 };
471 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
472 efx_port_t *epp = &(enp->en_port);
473 efx_rc_t rc;
474
475 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
476 ef10_common, EFX_ARRAY_SIZE(ef10_common))) != 0)
477 goto fail1;
478
479 if (epp->ep_phy_cap_mask & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) {
480 const struct efx_mac_stats_range ef10_40g_extra[] = {
481 { EFX_MAC_RX_ALIGN_ERRORS, EFX_MAC_RX_ALIGN_ERRORS },
482 };
483
484 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
485 ef10_40g_extra, EFX_ARRAY_SIZE(ef10_40g_extra))) != 0)
486 goto fail2;
487
488 if (encp->enc_mac_stats_40g_tx_size_bins) {
489 if ((rc = efx_mac_stats_mask_add_ranges(maskp,
490 mask_size, ef10_tx_size_bins,
491 EFX_ARRAY_SIZE(ef10_tx_size_bins))) != 0)
492 goto fail3;
493 }
494 } else {
495 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
496 ef10_tx_size_bins, EFX_ARRAY_SIZE(ef10_tx_size_bins))) != 0)
497 goto fail4;
498 }
499
500 if (encp->enc_pm_and_rxdp_counters) {
501 const struct efx_mac_stats_range ef10_pm_and_rxdp[] = {
502 { EFX_MAC_PM_TRUNC_BB_OVERFLOW, EFX_MAC_RXDP_HLB_WAIT },
503 };
504
505 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
506 ef10_pm_and_rxdp, EFX_ARRAY_SIZE(ef10_pm_and_rxdp))) != 0)
507 goto fail5;
508 }
509
510 if (encp->enc_datapath_cap_evb) {
511 const struct efx_mac_stats_range ef10_vadaptor[] = {
512 { EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
513 EFX_MAC_VADAPTER_TX_OVERFLOW },
514 };
515
516 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
517 ef10_vadaptor, EFX_ARRAY_SIZE(ef10_vadaptor))) != 0)
518 goto fail6;
519 }
520
521 if (encp->enc_fec_counters) {
522 const struct efx_mac_stats_range ef10_fec[] = {
523 { EFX_MAC_FEC_UNCORRECTED_ERRORS,
524 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3 },
525 };
526 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
527 ef10_fec, EFX_ARRAY_SIZE(ef10_fec))) != 0)
528 goto fail7;
529 }
530
531 if (encp->enc_mac_stats_nstats >= MC_CMD_MAC_NSTATS_V4) {
532 const struct efx_mac_stats_range ef10_rxdp_sdt[] = {
533 { EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
534 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC },
535 };
536
537 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
538 ef10_rxdp_sdt, EFX_ARRAY_SIZE(ef10_rxdp_sdt))) != 0)
539 goto fail8;
540 }
541
542 if (encp->enc_hlb_counters) {
543 const struct efx_mac_stats_range ef10_hlb[] = {
544 { EFX_MAC_RXDP_HLB_IDLE, EFX_MAC_RXDP_HLB_TIMEOUT },
545 };
546 if ((rc = efx_mac_stats_mask_add_ranges(maskp, mask_size,
547 ef10_hlb, EFX_ARRAY_SIZE(ef10_hlb))) != 0)
548 goto fail9;
549 }
550
551 return (0);
552
553 fail9:
554 EFSYS_PROBE(fail9);
555 fail8:
556 EFSYS_PROBE(fail8);
557 fail7:
558 EFSYS_PROBE(fail7);
559 fail6:
560 EFSYS_PROBE(fail6);
561 fail5:
562 EFSYS_PROBE(fail5);
563 fail4:
564 EFSYS_PROBE(fail4);
565 fail3:
566 EFSYS_PROBE(fail3);
567 fail2:
568 EFSYS_PROBE(fail2);
569 fail1:
570 EFSYS_PROBE1(fail1, efx_rc_t, rc);
571
572 return (rc);
573 }
574
575 #define EF10_MAC_STAT_READ(_esmp, _field, _eqp) \
576 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp)
577
578
579 __checkReturn efx_rc_t
ef10_mac_stats_update(__in efx_nic_t * enp,__in efsys_mem_t * esmp,__inout_ecount (EFX_MAC_NSTATS)efsys_stat_t * stat,__inout_opt uint32_t * generationp)580 ef10_mac_stats_update(
581 __in efx_nic_t *enp,
582 __in efsys_mem_t *esmp,
583 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
584 __inout_opt uint32_t *generationp)
585 {
586 const efx_nic_cfg_t *encp = &enp->en_nic_cfg;
587 efx_qword_t generation_start;
588 efx_qword_t generation_end;
589 efx_qword_t value;
590 efx_rc_t rc;
591
592 /*
593 * The MAC_STATS contain start and end generation counters used to
594 * detect when the DMA buffer has been updated during stats decode.
595 * All stats counters are 64bit unsigned values.
596 *
597 * Siena-compatible MAC stats contain MC_CMD_MAC_NSTATS 64bit counters.
598 * The generation end counter is at index MC_CMD_MAC_GENERATION_END
599 * (same as MC_CMD_MAC_NSTATS-1).
600 *
601 * Medford2 and later use a larger DMA buffer: MAC_STATS_NUM_STATS from
602 * MC_CMD_GET_CAPABILITIES_V4_OUT reports the number of 64bit counters.
603 *
604 * Firmware writes the generation end counter as the last counter in the
605 * DMA buffer. Do not use MC_CMD_MAC_GENERATION_END, as that is only
606 * correct for legacy Siena-compatible MAC stats.
607 */
608
609 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS) {
610 /* MAC stats count too small for legacy MAC stats */
611 rc = ENOSPC;
612 goto fail1;
613 }
614 if (EFSYS_MEM_SIZE(esmp) <
615 (encp->enc_mac_stats_nstats * sizeof (efx_qword_t))) {
616 /* DMA buffer too small */
617 rc = ENOSPC;
618 goto fail2;
619 }
620
621 /* Read END first so we don't race with the MC */
622 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
623 EF10_MAC_STAT_READ(esmp, (encp->enc_mac_stats_nstats - 1),
624 &generation_end);
625 EFSYS_MEM_READ_BARRIER();
626
627 /* TX */
628 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value);
629 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
630
631 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value);
632 EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value);
633
634 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value);
635 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value);
636
637 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value);
638 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value);
639
640 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value);
641 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value);
642
643 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value);
644 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value);
645
646 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value);
647 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value);
648
649 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value);
650 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
651 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value);
652 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value);
653
654 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value);
655 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value);
656
657 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value);
658 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value);
659
660 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value);
661 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value);
662
663 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value);
664 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value);
665
666 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value);
667 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value);
668
669 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value);
670 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
671 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value);
672 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value);
673
674 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value);
675 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value);
676
677 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value);
678 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value);
679
680 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS,
681 &value);
682 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value);
683
684 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS,
685 &value);
686 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value);
687
688 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value);
689 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value);
690
691 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value);
692 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value);
693
694 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS,
695 &value);
696 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value);
697
698 /* RX */
699 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value);
700 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value);
701
702 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value);
703 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value);
704
705 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value);
706 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value);
707
708 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value);
709 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value);
710
711 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value);
712 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value);
713
714 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value);
715 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value);
716
717 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value);
718 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
719 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value);
720 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value);
721
722 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value);
723 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value);
724
725 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value);
726 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value);
727
728 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value);
729 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value);
730
731 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value);
732 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value);
733
734 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value);
735 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value);
736
737 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value);
738 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
739 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value);
740 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value);
741
742 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value);
743 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value);
744
745 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value);
746 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value);
747
748 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value);
749 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value);
750
751 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value);
752 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value);
753
754 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value);
755 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value);
756
757 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value);
758 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value);
759
760 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value);
761 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value);
762
763 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value);
764 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]),
765 &(value.eq_dword[0]));
766 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]),
767 &(value.eq_dword[1]));
768
769 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value);
770 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]),
771 &(value.eq_dword[0]));
772 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]),
773 &(value.eq_dword[1]));
774
775 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value);
776 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]),
777 &(value.eq_dword[0]));
778 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]),
779 &(value.eq_dword[1]));
780
781 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value);
782 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]),
783 &(value.eq_dword[0]));
784 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]),
785 &(value.eq_dword[1]));
786
787 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value);
788 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value);
789
790 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value);
791 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value);
792
793 /* Packet memory (EF10 only) */
794 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW, &value);
795 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_BB_OVERFLOW]), &value);
796
797 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW, &value);
798 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_BB_OVERFLOW]), &value);
799
800 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_VFIFO_FULL, &value);
801 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_VFIFO_FULL]), &value);
802
803 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_VFIFO_FULL, &value);
804 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_VFIFO_FULL]), &value);
805
806 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_TRUNC_QBB, &value);
807 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_TRUNC_QBB]), &value);
808
809 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_QBB, &value);
810 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_QBB]), &value);
811
812 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_PM_DISCARD_MAPPING, &value);
813 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_PM_DISCARD_MAPPING]), &value);
814
815 /* RX datapath */
816 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_Q_DISABLED_PKTS, &value);
817 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_Q_DISABLED_PKTS]), &value);
818
819 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_DI_DROPPED_PKTS, &value);
820 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_DI_DROPPED_PKTS]), &value);
821
822 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_STREAMING_PKTS, &value);
823 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_STREAMING_PKTS]), &value);
824
825 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS, &value);
826 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_FETCH]), &value);
827
828 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS, &value);
829 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_WAIT]), &value);
830
831
832 /* VADAPTER RX */
833 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS,
834 &value);
835 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_UNICAST_PACKETS]),
836 &value);
837
838 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES,
839 &value);
840 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_UNICAST_BYTES]),
841 &value);
842
843 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS,
844 &value);
845 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS]),
846 &value);
847
848 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES,
849 &value);
850 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_MULTICAST_BYTES]),
851 &value);
852
853 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS,
854 &value);
855 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS]),
856 &value);
857
858 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES,
859 &value);
860 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BROADCAST_BYTES]),
861 &value);
862
863 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS,
864 &value);
865 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BAD_PACKETS]),
866 &value);
867
868 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_BAD_BYTES, &value);
869 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_BAD_BYTES]), &value);
870
871 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_RX_OVERFLOW, &value);
872 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_RX_OVERFLOW]), &value);
873
874 /* VADAPTER TX */
875 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS,
876 &value);
877 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_UNICAST_PACKETS]),
878 &value);
879
880 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES,
881 &value);
882 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_UNICAST_BYTES]),
883 &value);
884
885 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS,
886 &value);
887 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS]),
888 &value);
889
890 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES,
891 &value);
892 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_MULTICAST_BYTES]),
893 &value);
894
895 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS,
896 &value);
897 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS]),
898 &value);
899
900 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES,
901 &value);
902 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BROADCAST_BYTES]),
903 &value);
904
905 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS, &value);
906 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BAD_PACKETS]), &value);
907
908 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_BAD_BYTES, &value);
909 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_BAD_BYTES]), &value);
910
911 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_VADAPTER_TX_OVERFLOW, &value);
912 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_VADAPTER_TX_OVERFLOW]), &value);
913
914
915 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS_V2)
916 goto done;
917
918 /* FEC */
919 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_UNCORRECTED_ERRORS, &value);
920 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_UNCORRECTED_ERRORS]), &value);
921
922 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_ERRORS, &value);
923 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_ERRORS]), &value);
924
925 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
926 &value);
927 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0]),
928 &value);
929
930 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
931 &value);
932 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1]),
933 &value);
934
935 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
936 &value);
937 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2]),
938 &value);
939
940 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
941 &value);
942 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3]),
943 &value);
944
945 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS_V3)
946 goto done;
947
948 /* CTPIO exceptions */
949 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK, &value);
950 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_VI_BUSY_FALLBACK]), &value);
951
952 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS, &value);
953 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_LONG_WRITE_SUCCESS]), &value);
954
955 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL, &value);
956 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_MISSING_DBELL_FAIL]), &value);
957
958 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_OVERFLOW_FAIL, &value);
959 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_OVERFLOW_FAIL]), &value);
960
961 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL, &value);
962 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_UNDERFLOW_FAIL]), &value);
963
964 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_TIMEOUT_FAIL, &value);
965 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_TIMEOUT_FAIL]), &value);
966
967 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL, &value);
968 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_NONCONTIG_WR_FAIL]), &value);
969
970 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL, &value);
971 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_FRM_CLOBBER_FAIL]), &value);
972
973 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_INVALID_WR_FAIL, &value);
974 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_INVALID_WR_FAIL]), &value);
975
976 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK, &value);
977 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK]),
978 &value);
979
980 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK, &value);
981 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK]),
982 &value);
983
984 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_RUNT_FALLBACK, &value);
985 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_RUNT_FALLBACK]), &value);
986
987 /* CTPIO per-port stats */
988 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_SUCCESS, &value);
989 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_SUCCESS]), &value);
990
991 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_FALLBACK, &value);
992 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_FALLBACK]), &value);
993
994 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_POISON, &value);
995 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_POISON]), &value);
996
997 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_CTPIO_ERASE, &value);
998 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_CTPIO_ERASE]), &value);
999
1000 if (encp->enc_mac_stats_nstats < MC_CMD_MAC_NSTATS_V4)
1001 goto done;
1002
1003 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC,
1004 &value);
1005 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC]),
1006 &value);
1007
1008 /* Head-of-line blocking */
1009 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_IDLE, &value);
1010 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_IDLE]), &value);
1011
1012 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_RXDP_HLB_TIMEOUT, &value);
1013 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RXDP_HLB_TIMEOUT]), &value);
1014
1015 done:
1016 /* Read START generation counter */
1017 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFSYS_MEM_SIZE(esmp));
1018 EFSYS_MEM_READ_BARRIER();
1019 EF10_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START,
1020 &generation_start);
1021
1022 /* Check that we didn't read the stats in the middle of a DMA */
1023 /* Not a good enough check ? */
1024 if (memcmp(&generation_start, &generation_end,
1025 sizeof (generation_start)))
1026 return (EAGAIN);
1027
1028 if (generationp)
1029 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0);
1030
1031 return (0);
1032
1033 fail2:
1034 EFSYS_PROBE(fail2);
1035 fail1:
1036 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1037
1038 return (rc);
1039 }
1040
1041 #endif /* EFSYS_OPT_MAC_STATS */
1042
1043 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1044