198c4a35cSTomasz Jozwiak /* SPDX-License-Identifier: BSD-3-Clause 298c4a35cSTomasz Jozwiak * Copyright(c) 2018 Intel Corporation 398c4a35cSTomasz Jozwiak */ 498c4a35cSTomasz Jozwiak #ifndef _QAT_COMMON_H_ 598c4a35cSTomasz Jozwiak #define _QAT_COMMON_H_ 698c4a35cSTomasz Jozwiak 798c4a35cSTomasz Jozwiak #include <stdint.h> 898c4a35cSTomasz Jozwiak 998c4a35cSTomasz Jozwiak #include <rte_mbuf.h> 1098c4a35cSTomasz Jozwiak 1198c4a35cSTomasz Jozwiak /**< Intel(R) QAT device name for PCI registration */ 1298c4a35cSTomasz Jozwiak #define QAT_PCI_NAME qat 1398c4a35cSTomasz Jozwiak #define QAT_64_BTYE_ALIGN_MASK (~0x3f) 1498c4a35cSTomasz Jozwiak 1598c4a35cSTomasz Jozwiak /* Intel(R) QuickAssist Technology device generation is enumerated 164c6912d3SFan Zhang * from one according to the generation of the device. 174c6912d3SFan Zhang * QAT_GEN* is used as the index to find all devices 1898c4a35cSTomasz Jozwiak */ 1999ab2806SArkadiusz Kusztal 2099ab2806SArkadiusz Kusztal extern const char *const *qat_cmdline_defines[]; 2199ab2806SArkadiusz Kusztal 22b7bd72d8SArkadiusz Kusztal struct qat_options { 23b7bd72d8SArkadiusz Kusztal uint32_t slice_map; 24b7bd72d8SArkadiusz Kusztal /**< Map of the crypto and compression slices */ 25b7bd72d8SArkadiusz Kusztal uint16_t has_wireless_slice; 26b7bd72d8SArkadiusz Kusztal /**< Wireless Slices supported */ 27b7bd72d8SArkadiusz Kusztal uint8_t legacy_alg; 28b7bd72d8SArkadiusz Kusztal /**< are legacy algorithm supported */ 29b7bd72d8SArkadiusz Kusztal }; 30b7bd72d8SArkadiusz Kusztal 3198c4a35cSTomasz Jozwiak enum qat_device_gen { 3204dd78d1SFan Zhang QAT_GEN1, 331f5e4053SFiona Trahe QAT_GEN2, 348f393c4fSArek Kusztal QAT_GEN3, 3504dd78d1SFan Zhang QAT_GEN4, 3659cda512SCiara Power QAT_GEN5, 37e9271821SNishikant Nayak QAT_GEN_LCE, 382e98e808SArkadiusz Kusztal QAT_VQAT, 3904dd78d1SFan Zhang QAT_N_GENS 4098c4a35cSTomasz Jozwiak }; 4198c4a35cSTomasz Jozwiak 4298c4a35cSTomasz Jozwiak enum qat_service_type { 4304dd78d1SFan Zhang QAT_SERVICE_ASYMMETRIC, 4498c4a35cSTomasz Jozwiak QAT_SERVICE_SYMMETRIC, 4598c4a35cSTomasz Jozwiak QAT_SERVICE_COMPRESSION, 4604dd78d1SFan Zhang QAT_MAX_SERVICES 4798c4a35cSTomasz Jozwiak }; 48944027acSFiona Trahe 4904dd78d1SFan Zhang #define QAT_SERVICE_INVALID (QAT_MAX_SERVICES) 5004dd78d1SFan Zhang 51960ff4d6SArek Kusztal enum qat_svc_list { 52960ff4d6SArek Kusztal QAT_SVC_UNUSED = 0, 53960ff4d6SArek Kusztal QAT_SVC_CRYPTO = 1, 54960ff4d6SArek Kusztal QAT_SVC_COMPRESSION = 2, 55960ff4d6SArek Kusztal QAT_SVC_SYM = 3, 56960ff4d6SArek Kusztal QAT_SVC_ASYM = 4, 57960ff4d6SArek Kusztal }; 58960ff4d6SArek Kusztal 5998c4a35cSTomasz Jozwiak /**< Common struct for scatter-gather list operations */ 60*e7750639SAndre Muezerie struct __rte_packed_begin qat_flat_buf { 6198c4a35cSTomasz Jozwiak uint32_t len; 6298c4a35cSTomasz Jozwiak uint32_t resrvd; 6398c4a35cSTomasz Jozwiak uint64_t addr; 64*e7750639SAndre Muezerie } __rte_packed_end; 6598c4a35cSTomasz Jozwiak 66944027acSFiona Trahe #define qat_sgl_hdr struct { \ 67944027acSFiona Trahe uint64_t resrvd; \ 68944027acSFiona Trahe uint32_t num_bufs; \ 69944027acSFiona Trahe uint32_t num_mapped_bufs; \ 70944027acSFiona Trahe } 71944027acSFiona Trahe 72944027acSFiona Trahe __extension__ 73*e7750639SAndre Muezerie struct __rte_cache_aligned __rte_packed_begin qat_sgl { 74944027acSFiona Trahe qat_sgl_hdr; 75944027acSFiona Trahe /* flexible array of flat buffers*/ 76944027acSFiona Trahe struct qat_flat_buf buffers[0]; 77*e7750639SAndre Muezerie } __rte_packed_end; 7898c4a35cSTomasz Jozwiak 7998c4a35cSTomasz Jozwiak /** Common, i.e. not service-specific, statistics */ 8098c4a35cSTomasz Jozwiak struct qat_common_stats { 8198c4a35cSTomasz Jozwiak uint64_t enqueued_count; 8298c4a35cSTomasz Jozwiak /**< Count of all operations enqueued */ 8398c4a35cSTomasz Jozwiak uint64_t dequeued_count; 8498c4a35cSTomasz Jozwiak /**< Count of all operations dequeued */ 8598c4a35cSTomasz Jozwiak 8698c4a35cSTomasz Jozwiak uint64_t enqueue_err_count; 8798c4a35cSTomasz Jozwiak /**< Total error count on operations enqueued */ 8898c4a35cSTomasz Jozwiak uint64_t dequeue_err_count; 8998c4a35cSTomasz Jozwiak /**< Total error count on operations dequeued */ 9047c3f7a4SArek Kusztal uint64_t threshold_hit_count; 9147c3f7a4SArek Kusztal /**< Total number of times min qp threshold condition was fulfilled */ 9247c3f7a4SArek Kusztal 9398c4a35cSTomasz Jozwiak }; 9498c4a35cSTomasz Jozwiak 9598c4a35cSTomasz Jozwiak struct qat_pci_device; 9698c4a35cSTomasz Jozwiak 9798c4a35cSTomasz Jozwiak int 98b30aa891STomasz Jozwiak qat_sgl_fill_array(struct rte_mbuf *buf, int64_t offset, 99944027acSFiona Trahe void *list_in, uint32_t data_len, 100944027acSFiona Trahe const uint16_t max_segs); 10198c4a35cSTomasz Jozwiak void 10298c4a35cSTomasz Jozwiak qat_stats_get(struct qat_pci_device *dev, 10398c4a35cSTomasz Jozwiak struct qat_common_stats *stats, 10498c4a35cSTomasz Jozwiak enum qat_service_type service); 10598c4a35cSTomasz Jozwiak void 10698c4a35cSTomasz Jozwiak qat_stats_reset(struct qat_pci_device *dev, 10798c4a35cSTomasz Jozwiak enum qat_service_type service); 10898c4a35cSTomasz Jozwiak 109f0f369a6SFan Zhang const char * 110f0f369a6SFan Zhang qat_service_get_str(enum qat_service_type type); 111f0f369a6SFan Zhang 11298c4a35cSTomasz Jozwiak #endif /* _QAT_COMMON_H_ */ 113