1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Intel Corporation 3 */ 4 #ifndef _QAT_COMMON_H_ 5 #define _QAT_COMMON_H_ 6 7 #include <stdint.h> 8 9 #include <rte_mbuf.h> 10 11 /**< Intel(R) QAT device name for PCI registration */ 12 #define QAT_PCI_NAME qat 13 #define QAT_64_BTYE_ALIGN_MASK (~0x3f) 14 15 /* Intel(R) QuickAssist Technology device generation is enumerated 16 * from one according to the generation of the device. 17 * QAT_GEN* is used as the index to find all devices 18 */ 19 20 extern const char *const *qat_cmdline_defines[]; 21 22 struct qat_options { 23 uint32_t slice_map; 24 /**< Map of the crypto and compression slices */ 25 uint16_t has_wireless_slice; 26 /**< Wireless Slices supported */ 27 uint8_t legacy_alg; 28 /**< are legacy algorithm supported */ 29 }; 30 31 enum qat_device_gen { 32 QAT_GEN1, 33 QAT_GEN2, 34 QAT_GEN3, 35 QAT_GEN4, 36 QAT_GEN5, 37 QAT_GEN_LCE, 38 QAT_VQAT, 39 QAT_N_GENS 40 }; 41 42 enum qat_service_type { 43 QAT_SERVICE_ASYMMETRIC, 44 QAT_SERVICE_SYMMETRIC, 45 QAT_SERVICE_COMPRESSION, 46 QAT_MAX_SERVICES 47 }; 48 49 #define QAT_SERVICE_INVALID (QAT_MAX_SERVICES) 50 51 enum qat_svc_list { 52 QAT_SVC_UNUSED = 0, 53 QAT_SVC_CRYPTO = 1, 54 QAT_SVC_COMPRESSION = 2, 55 QAT_SVC_SYM = 3, 56 QAT_SVC_ASYM = 4, 57 }; 58 59 /**< Common struct for scatter-gather list operations */ 60 struct __rte_packed_begin qat_flat_buf { 61 uint32_t len; 62 uint32_t resrvd; 63 uint64_t addr; 64 } __rte_packed_end; 65 66 #define qat_sgl_hdr struct { \ 67 uint64_t resrvd; \ 68 uint32_t num_bufs; \ 69 uint32_t num_mapped_bufs; \ 70 } 71 72 __extension__ 73 struct __rte_cache_aligned __rte_packed_begin qat_sgl { 74 qat_sgl_hdr; 75 /* flexible array of flat buffers*/ 76 struct qat_flat_buf buffers[0]; 77 } __rte_packed_end; 78 79 /** Common, i.e. not service-specific, statistics */ 80 struct qat_common_stats { 81 uint64_t enqueued_count; 82 /**< Count of all operations enqueued */ 83 uint64_t dequeued_count; 84 /**< Count of all operations dequeued */ 85 86 uint64_t enqueue_err_count; 87 /**< Total error count on operations enqueued */ 88 uint64_t dequeue_err_count; 89 /**< Total error count on operations dequeued */ 90 uint64_t threshold_hit_count; 91 /**< Total number of times min qp threshold condition was fulfilled */ 92 93 }; 94 95 struct qat_pci_device; 96 97 int 98 qat_sgl_fill_array(struct rte_mbuf *buf, int64_t offset, 99 void *list_in, uint32_t data_len, 100 const uint16_t max_segs); 101 void 102 qat_stats_get(struct qat_pci_device *dev, 103 struct qat_common_stats *stats, 104 enum qat_service_type service); 105 void 106 qat_stats_reset(struct qat_pci_device *dev, 107 enum qat_service_type service); 108 109 const char * 110 qat_service_get_str(enum qat_service_type type); 111 112 #endif /* _QAT_COMMON_H_ */ 113