1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2015-2018 Intel Corporation
3 */
4 #ifndef _ICP_QAT_HW_H_
5 #define _ICP_QAT_HW_H_
6
7 #include "icp_qat_fw.h"
8
9 #define ADF_C4XXXIOV_VFLEGFUSES_OFFSET 0x4C
10 #define ADF1_C4XXXIOV_VFLEGFUSES_LEN 4
11
12 /* Definition of virtual QAT subsystem ID*/
13 #define ADF_VQAT_SYM_PCI_SUBSYSTEM_ID 0x00
14 #define ADF_VQAT_ASYM_PCI_SUBSYSTEM_ID 0x01
15 #define ADF_VQAT_DC_PCI_SUBSYSTEM_ID 0x02
16
17 enum icp_qat_slice_mask {
18 ICP_ACCEL_MASK_CIPHER_SLICE = 0x01,
19 ICP_ACCEL_MASK_AUTH_SLICE = 0x02,
20 ICP_ACCEL_MASK_PKE_SLICE = 0x04,
21 ICP_ACCEL_MASK_COMPRESS_SLICE = 0x08,
22 ICP_ACCEL_MASK_DEPRECATED = 0x10,
23 ICP_ACCEL_MASK_EIA3_SLICE = 0x20,
24 ICP_ACCEL_MASK_SHA3_SLICE = 0x40,
25 ICP_ACCEL_MASK_CRYPTO0_SLICE = 0x80,
26 ICP_ACCEL_MASK_CRYPTO1_SLICE = 0x100,
27 ICP_ACCEL_MASK_CRYPTO2_SLICE = 0x200,
28 ICP_ACCEL_MASK_SM3_SLICE = 0x400,
29 ICP_ACCEL_MASK_SM4_SLICE = 0x800,
30 ICP_ACCEL_MASK_ZUC_256_SLICE = 0x2000,
31 };
32
33 enum icp_qat_hw_ae_id {
34 ICP_QAT_HW_AE_0 = 0,
35 ICP_QAT_HW_AE_1 = 1,
36 ICP_QAT_HW_AE_2 = 2,
37 ICP_QAT_HW_AE_3 = 3,
38 ICP_QAT_HW_AE_4 = 4,
39 ICP_QAT_HW_AE_5 = 5,
40 ICP_QAT_HW_AE_6 = 6,
41 ICP_QAT_HW_AE_7 = 7,
42 ICP_QAT_HW_AE_8 = 8,
43 ICP_QAT_HW_AE_9 = 9,
44 ICP_QAT_HW_AE_10 = 10,
45 ICP_QAT_HW_AE_11 = 11,
46 ICP_QAT_HW_AE_DELIMITER = 12
47 };
48
49 enum icp_qat_hw_qat_id {
50 ICP_QAT_HW_QAT_0 = 0,
51 ICP_QAT_HW_QAT_1 = 1,
52 ICP_QAT_HW_QAT_2 = 2,
53 ICP_QAT_HW_QAT_3 = 3,
54 ICP_QAT_HW_QAT_4 = 4,
55 ICP_QAT_HW_QAT_5 = 5,
56 ICP_QAT_HW_QAT_DELIMITER = 6
57 };
58
59 enum icp_qat_hw_auth_algo {
60 ICP_QAT_HW_AUTH_ALGO_NULL = 0,
61 ICP_QAT_HW_AUTH_ALGO_SHA1 = 1,
62 ICP_QAT_HW_AUTH_ALGO_MD5 = 2,
63 ICP_QAT_HW_AUTH_ALGO_SHA224 = 3,
64 ICP_QAT_HW_AUTH_ALGO_SHA256 = 4,
65 ICP_QAT_HW_AUTH_ALGO_SHA384 = 5,
66 ICP_QAT_HW_AUTH_ALGO_SHA512 = 6,
67 ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7,
68 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,
69 ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9,
70 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10,
71 ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11,
72 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
73 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
74 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
75 ICP_QAT_HW_AUTH_ALGO_SM3 = 15,
76 ICP_QAT_HW_AUTH_ALGO_SHA3_224 = 16,
77 ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
78 ICP_QAT_HW_AUTH_ALGO_SHA3_384 = 18,
79 ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,
80 ICP_QAT_HW_AUTH_ALGO_RESERVED = 20,
81 ICP_QAT_HW_AUTH_ALGO_RESERVED1 = 21,
82 ICP_QAT_HW_AUTH_ALGO_RESERVED2 = 22,
83 ICP_QAT_HW_AUTH_ALGO_AES_128_CMAC = 22,
84 ICP_QAT_HW_AUTH_ALGO_RESERVED4 = 23,
85 ICP_QAT_HW_AUTH_ALGO_RESERVED5 = 24,
86 ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32 = 25,
87 ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64 = 26,
88 ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128 = 27,
89 ICP_QAT_HW_AUTH_ALGO_DELIMITER = 28
90 };
91
92 enum icp_qat_hw_auth_mode {
93 ICP_QAT_HW_AUTH_MODE0 = 0,
94 ICP_QAT_HW_AUTH_MODE1 = 1,
95 ICP_QAT_HW_AUTH_MODE2 = 2,
96 ICP_QAT_HW_AUTH_MODE_DELIMITER = 3
97 };
98
99 struct icp_qat_hw_auth_config {
100 uint32_t config;
101 uint32_t reserved;
102 };
103
104 #define QAT_AUTH_MODE_BITPOS 4
105 #define QAT_AUTH_MODE_MASK 0xF
106 #define QAT_AUTH_ALGO_BITPOS 0
107 #define QAT_AUTH_ALGO_MASK 0xF
108 #define QAT_AUTH_CMP_BITPOS 8
109 #define QAT_AUTH_CMP_MASK 0x7F
110 #define QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS 16
111 #define QAT_AUTH_SHA3_PADDING_DISABLE_MASK 0x1
112 #define QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS 17
113 #define QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK 0x1
114 #define QAT_AUTH_ALGO_SHA3_BITPOS 22
115 #define QAT_AUTH_ALGO_SHA3_MASK 0x3
116 #define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS 16
117 #define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK 0xF
118 #define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS 24
119 #define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK 0xFF
120 #define QAT_AUTH_SHA3_HW_PADDING_ENABLE 0
121 #define QAT_AUTH_SHA3_HW_PADDING_DISABLE 1
122 #define QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT 0
123 #define QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT 0
124 #define QAT_AUTH_SHA3_PADDING_OVERRIDE_PROGRAMMABLE 1
125 #define QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED 0
126 #define QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED 0
127
128 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
129 ((((mode) & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
130 (((algo) & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
131 (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) \
132 << QAT_AUTH_ALGO_SHA3_BITPOS) | \
133 (((QAT_AUTH_SHA3_PADDING_DISABLE_USE_DEFAULT) & \
134 QAT_AUTH_SHA3_PADDING_DISABLE_MASK) \
135 << QAT_AUTH_SHA3_PADDING_DISABLE_BITPOS) | \
136 (((QAT_AUTH_SHA3_PADDING_OVERRIDE_USE_DEFAULT) & \
137 QAT_AUTH_SHA3_PADDING_OVERRIDE_MASK) \
138 << QAT_AUTH_SHA3_PADDING_OVERRIDE_BITPOS) | \
139 (((cmp_len) & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
140
141 #define ICP_QAT_HW_AUTH_CONFIG_BUILD_UPPER \
142 ((((QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_RESERVED) & \
143 QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_MASK) \
144 << QAT_AUTH_SHA3_PROG_PADDING_POSTFIX_BITPOS) | \
145 (((QAT_AUTH_SHA3_PROG_PADDING_PREFIX_RESERVED) & \
146 QAT_AUTH_SHA3_PROG_PADDING_PREFIX_MASK) \
147 << QAT_AUTH_SHA3_PROG_PADDING_PREFIX_BITPOS))
148
149 struct icp_qat_hw_auth_counter {
150 uint32_t counter;
151 uint32_t reserved;
152 };
153
154 #define QAT_AUTH_COUNT_MASK 0xFFFFFFFF
155 #define QAT_AUTH_COUNT_BITPOS 0
156 #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \
157 (((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS)
158
159 struct icp_qat_hw_auth_setup {
160 struct icp_qat_hw_auth_config auth_config;
161 struct icp_qat_hw_auth_counter auth_counter;
162 };
163
164 #define QAT_HW_DEFAULT_ALIGNMENT 8
165 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1)))
166 #define ICP_QAT_HW_NULL_STATE1_SZ 32
167 #define ICP_QAT_HW_MD5_STATE1_SZ 16
168 #define ICP_QAT_HW_SHA1_STATE1_SZ 20
169 #define ICP_QAT_HW_SHA224_STATE1_SZ 32
170 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
171 #define ICP_QAT_HW_SHA256_STATE1_SZ 32
172 #define ICP_QAT_HW_SM3_STATE1_SZ 32
173 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
174 #define ICP_QAT_HW_SHA384_STATE1_SZ 64
175 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
176 #define ICP_QAT_HW_SHA512_STATE1_SZ 64
177 #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
178 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
179 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
180 #define ICP_QAT_HW_AES_F9_STATE1_SZ 32
181 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16
182 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
183 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
184 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
185 #define ICP_QAT_HW_ZUC_256_MAC_32_STATE1_SZ 8
186 #define ICP_QAT_HW_ZUC_256_MAC_64_STATE1_SZ 8
187 #define ICP_QAT_HW_ZUC_256_MAC_128_STATE1_SZ 16
188 #define ICP_QAT_HW_AES_CMAC_STATE1_SZ 16
189
190 #define ICP_QAT_HW_NULL_STATE2_SZ 32
191 #define ICP_QAT_HW_MD5_STATE2_SZ 16
192 #define ICP_QAT_HW_SHA1_STATE2_SZ 20
193 #define ICP_QAT_HW_SHA224_STATE2_SZ 32
194 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
195 #define ICP_QAT_HW_SHA256_STATE2_SZ 32
196 #define ICP_QAT_HW_SM3_STATE2_SZ 32
197 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
198 #define ICP_QAT_HW_SHA384_STATE2_SZ 64
199 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
200 #define ICP_QAT_HW_SHA512_STATE2_SZ 64
201 #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
202 #define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48
203 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
204 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
205 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16
206 #define ICP_QAT_HW_F9_IK_SZ 16
207 #define ICP_QAT_HW_F9_FK_SZ 16
208 #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \
209 ICP_QAT_HW_F9_FK_SZ)
210 #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ
211 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24
212 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32
213 #define ICP_QAT_HW_ZUC_256_STATE2_SZ 56
214 #define ICP_QAT_HW_GALOIS_H_SZ 16
215 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8
216 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16
217 #define ICP_QAT_HW_AES_128_CMAC_STATE2_SZ 16
218
219 struct icp_qat_hw_auth_sha512 {
220 struct icp_qat_hw_auth_setup inner_setup;
221 uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ];
222 struct icp_qat_hw_auth_setup outer_setup;
223 uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
224 };
225
226 struct icp_qat_hw_auth_sha3_512 {
227 struct icp_qat_hw_auth_setup inner_setup;
228 uint8_t state1[ICP_QAT_HW_SHA3_512_STATE1_SZ];
229 struct icp_qat_hw_auth_setup outer_setup;
230 };
231
232 struct icp_qat_hw_auth_algo_blk {
233 struct icp_qat_hw_auth_sha512 sha;
234 };
235
236 #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0
237 #define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF
238
239 enum icp_qat_hw_cipher_algo {
240 ICP_QAT_HW_CIPHER_ALGO_NULL = 0,
241 ICP_QAT_HW_CIPHER_ALGO_DES = 1,
242 ICP_QAT_HW_CIPHER_ALGO_3DES = 2,
243 ICP_QAT_HW_CIPHER_ALGO_AES128 = 3,
244 ICP_QAT_HW_CIPHER_ALGO_AES192 = 4,
245 ICP_QAT_HW_CIPHER_ALGO_AES256 = 5,
246 ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6,
247 ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,
248 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,
249 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,
250 ICP_QAT_HW_CIPHER_ALGO_SM4 = 10,
251 ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305 = 11,
252 ICP_QAT_HW_CIPHER_ALGO_ZUC_256 = 12,
253 ICP_QAT_HW_CIPHER_DELIMITER = 13
254 };
255
256 enum icp_qat_hw_cipher_mode {
257 ICP_QAT_HW_CIPHER_ECB_MODE = 0,
258 ICP_QAT_HW_CIPHER_CBC_MODE = 1,
259 ICP_QAT_HW_CIPHER_CTR_MODE = 2,
260 ICP_QAT_HW_CIPHER_F8_MODE = 3,
261 ICP_QAT_HW_CIPHER_AEAD_MODE = 4,
262 ICP_QAT_HW_CIPHER_XTS_MODE = 6,
263 ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7
264 };
265
266 struct icp_qat_hw_cipher_config {
267 uint32_t val;
268 uint32_t reserved;
269 };
270
271 enum icp_qat_hw_cipher_dir {
272 ICP_QAT_HW_CIPHER_ENCRYPT = 0,
273 ICP_QAT_HW_CIPHER_DECRYPT = 1,
274 };
275
276 enum icp_qat_hw_auth_op {
277 ICP_QAT_HW_AUTH_VERIFY = 0,
278 ICP_QAT_HW_AUTH_GENERATE = 1,
279 };
280
281 enum icp_qat_hw_cipher_convert {
282 ICP_QAT_HW_CIPHER_NO_CONVERT = 0,
283 ICP_QAT_HW_CIPHER_KEY_CONVERT = 1,
284 };
285
286 #define QAT_CIPHER_MODE_BITPOS 4
287 #define QAT_CIPHER_MODE_LE_BITPOS 28
288 #define QAT_CIPHER_MODE_MASK 0xF
289 #define QAT_CIPHER_ALGO_BITPOS 0
290 #define QAT_CIPHER_ALGO_LE_BITPOS 24
291 #define QAT_CIPHER_ALGO_MASK 0xF
292 #define QAT_CIPHER_CONVERT_BITPOS 9
293 #define QAT_CIPHER_CONVERT_LE_BITPOS 17
294 #define QAT_CIPHER_CONVERT_MASK 0x1
295 #define QAT_CIPHER_DIR_BITPOS 8
296 #define QAT_CIPHER_DIR_LE_BITPOS 16
297 #define QAT_CIPHER_DIR_MASK 0x1
298 #define QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS 10
299 #define QAT_CIPHER_AEAD_HASH_CMP_LEN_LE_BITPOS 18
300 #define QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK 0x1F
301 #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2
302 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2
303 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \
304 (((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \
305 ((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \
306 ((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \
307 ((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS))
308
309 #define QAT_CIPHER_AEAD_AAD_LOWER_SHIFT 24
310 #define QAT_CIPHER_AEAD_AAD_UPPER_SHIFT 8
311 #define QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK 0xFF
312 #define QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK 0x3F
313 #define QAT_CIPHER_AEAD_AAD_SIZE_MASK 0x3FFF
314 #define QAT_CIPHER_AEAD_AAD_SIZE_BITPOS 16
315 #define QAT_CIPHER_AEAD_AAD_SIZE_LE_BITPOS 0
316 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(aad_size) \
317 __extension__ ({ \
318 typeof(aad_size) aad_size1 = aad_size; \
319 (((((aad_size1) >> QAT_CIPHER_AEAD_AAD_UPPER_SHIFT) & \
320 QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK) << \
321 QAT_CIPHER_AEAD_AAD_SIZE_BITPOS) | \
322 (((aad_size1) & QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK) << \
323 QAT_CIPHER_AEAD_AAD_LOWER_SHIFT)); \
324 })
325
326 #define ICP_QAT_HW_DES_BLK_SZ 8
327 #define ICP_QAT_HW_3DES_BLK_SZ 8
328 #define ICP_QAT_HW_NULL_BLK_SZ 8
329 #define ICP_QAT_HW_AES_BLK_SZ 16
330 #define ICP_QAT_HW_KASUMI_BLK_SZ 8
331 #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8
332 #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8
333 #define ICP_QAT_HW_ZUC_256_BLK_SZ 8
334 #define ICP_QAT_HW_NULL_KEY_SZ 256
335 #define ICP_QAT_HW_DES_KEY_SZ 8
336 #define ICP_QAT_HW_3DES_KEY_SZ 24
337 #define ICP_QAT_HW_AES_128_KEY_SZ 16
338 #define ICP_QAT_HW_AES_192_KEY_SZ 24
339 #define ICP_QAT_HW_AES_256_KEY_SZ 32
340 #define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
341 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
342 #define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \
343 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
344 #define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
345 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
346 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
347 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
348 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
349 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
350 #define ICP_QAT_HW_KASUMI_KEY_SZ 16
351 #define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \
352 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
353 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
354 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
355 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
356 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
357 #define ICP_QAT_HW_ARC4_KEY_SZ 256
358 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16
359 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16
360 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16
361 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16
362 #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2
363 #define ICP_QAT_HW_CHACHAPOLY_KEY_SZ 32
364 #define ICP_QAT_HW_CHACHAPOLY_IV_SZ 12
365 #define ICP_QAT_HW_CHACHAPOLY_BLK_SZ 64
366 #define ICP_QAT_HW_SPC_CTR_SZ 16
367 #define ICP_QAT_HW_CHACHAPOLY_ICV_SZ 16
368 #define ICP_QAT_HW_CHACHAPOLY_AAD_MAX_LOG 14
369 #define ICP_QAT_HW_ZUC_256_KEY_SZ 32
370 #define ICP_QAT_HW_ZUC_256_IV_SZ 24
371
372 #define ICP_QAT_HW_CIPHER_MAX_KEY_SZ ICP_QAT_HW_AES_256_F8_KEY_SZ
373
374 /* These defines describe position of the bit-fields
375 * in the flags byte in B0
376 */
377 #define ICP_QAT_HW_CCM_B0_FLAGS_ADATA_SHIFT 6
378 #define ICP_QAT_HW_CCM_B0_FLAGS_T_SHIFT 3
379
380 #define ICP_QAT_HW_CCM_BUILD_B0_FLAGS(Adata, t, q) \
381 ((((Adata) > 0 ? 1 : 0) << ICP_QAT_HW_CCM_B0_FLAGS_ADATA_SHIFT) \
382 | ((((t) - 2) >> 1) << ICP_QAT_HW_CCM_B0_FLAGS_T_SHIFT) \
383 | ((q) - 1))
384
385 #define ICP_QAT_HW_CCM_NQ_CONST 15
386 #define ICP_QAT_HW_CCM_AAD_B0_LEN 16
387 #define ICP_QAT_HW_CCM_AAD_LEN_INFO 2
388 #define ICP_QAT_HW_CCM_AAD_DATA_OFFSET (ICP_QAT_HW_CCM_AAD_B0_LEN + \
389 ICP_QAT_HW_CCM_AAD_LEN_INFO)
390 #define ICP_QAT_HW_CCM_AAD_ALIGNMENT 16
391 #define ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE 4
392 #define ICP_QAT_HW_CCM_NONCE_OFFSET 1
393
394 struct __rte_cache_aligned icp_qat_hw_cipher_algo_blk {
395 struct icp_qat_hw_cipher_config cipher_config;
396 uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
397 };
398
399 struct icp_qat_hw_gen2_crc_cd {
400 uint32_t flags;
401 uint32_t reserved1[5];
402 uint32_t initial_crc;
403 uint32_t reserved2[3];
404 };
405
406 #define QAT_GEN3_COMP_REFLECT_IN_BITPOS 17
407 #define QAT_GEN3_COMP_REFLECT_IN_MASK 0x1
408 #define QAT_GEN3_COMP_REFLECT_OUT_BITPOS 18
409 #define QAT_GEN3_COMP_REFLECT_OUT_MASK 0x1
410
411 struct icp_qat_hw_gen3_crc_cd {
412 uint32_t flags;
413 uint32_t reserved1[3];
414 uint32_t polynomial;
415 uint32_t xor_val;
416 uint32_t reserved2[2];
417 uint32_t initial_crc;
418 uint32_t reserved3;
419 };
420
421 struct icp_qat_hw_ucs_cipher_config {
422 uint32_t val;
423 uint32_t reserved[3];
424 };
425
426 struct __rte_cache_aligned icp_qat_hw_cipher_algo_blk20 {
427 struct icp_qat_hw_ucs_cipher_config cipher_config;
428 uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
429 };
430
431 enum icp_qat_hw_ucs_cipher_reflect_out {
432 ICP_QAT_HW_CIPHER_UCS_REFLECT_OUT_DISABLED = 0,
433 ICP_QAT_HW_CIPHER_UCS_REFLECT_OUT_ENABLED = 1,
434 };
435
436 enum icp_qat_hw_ucs_cipher_reflect_in {
437 ICP_QAT_HW_CIPHER_UCS_REFLECT_IN_DISABLED = 0,
438 ICP_QAT_HW_CIPHER_UCS_REFLECT_IN_ENABLED = 1,
439 };
440
441 enum icp_qat_hw_ucs_cipher_crc_encoding {
442 ICP_QAT_HW_CIPHER_UCS_CRC_NOT_REQUIRED = 0,
443 ICP_QAT_HW_CIPHER_UCS_CRC32 = 1,
444 ICP_QAT_HW_CIPHER_UCS_CRC64 = 2,
445 };
446
447 #define QAT_CIPHER_UCS_REFLECT_OUT_LE_BITPOS 17
448 #define QAT_CIPHER_UCS_REFLECT_OUT_MASK 0x1
449 #define QAT_CIPHER_UCS_REFLECT_IN_LE_BITPOS 16
450 #define QAT_CIPHER_UCS_REFLECT_IN_MASK 0x1
451 #define QAT_CIPHER_UCS_CRC_ENCODING_LE_BITPOS 14
452 #define QAT_CIPHER_UCS_CRC_ENCODING_MASK 0x3
453
454 struct icp_qat_fw_ucs_slice_cipher_config {
455 enum icp_qat_hw_cipher_mode mode;
456 enum icp_qat_hw_cipher_algo algo;
457 uint16_t hash_cmp_val;
458 enum icp_qat_hw_cipher_dir dir;
459 uint16_t associated_data_len_in_bytes;
460 enum icp_qat_hw_ucs_cipher_reflect_out crc_reflect_out;
461 enum icp_qat_hw_ucs_cipher_reflect_in crc_reflect_in;
462 enum icp_qat_hw_ucs_cipher_crc_encoding crc_encoding;
463 };
464
465 struct icp_qat_hw_gen4_crc_cd {
466 uint32_t ucs_config[4];
467 uint32_t polynomial;
468 uint32_t reserved1;
469 uint32_t xor_val;
470 uint32_t reserved2;
471 uint32_t initial_crc;
472 uint32_t reserved3;
473 };
474
475 static inline uint32_t
ICP_QAT_HW_UCS_CIPHER_GEN4_BUILD_CONFIG_LOWER(struct icp_qat_fw_ucs_slice_cipher_config csr)476 ICP_QAT_HW_UCS_CIPHER_GEN4_BUILD_CONFIG_LOWER(
477 struct icp_qat_fw_ucs_slice_cipher_config csr)
478 {
479 uint32_t val32 = 0;
480
481 QAT_FIELD_SET(val32,
482 csr.mode,
483 QAT_CIPHER_MODE_LE_BITPOS,
484 QAT_CIPHER_MODE_MASK);
485
486 QAT_FIELD_SET(val32,
487 csr.algo,
488 QAT_CIPHER_ALGO_LE_BITPOS,
489 QAT_CIPHER_ALGO_MASK);
490
491 QAT_FIELD_SET(val32,
492 csr.hash_cmp_val,
493 QAT_CIPHER_AEAD_HASH_CMP_LEN_LE_BITPOS,
494 QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK);
495
496 QAT_FIELD_SET(val32,
497 csr.dir,
498 QAT_CIPHER_DIR_LE_BITPOS,
499 QAT_CIPHER_DIR_MASK);
500
501 return rte_bswap32(val32);
502 }
503
504 static inline uint32_t
ICP_QAT_HW_UCS_CIPHER_GEN4_BUILD_CONFIG_UPPER(struct icp_qat_fw_ucs_slice_cipher_config csr)505 ICP_QAT_HW_UCS_CIPHER_GEN4_BUILD_CONFIG_UPPER(
506 struct icp_qat_fw_ucs_slice_cipher_config csr)
507 {
508 uint32_t val32 = 0;
509
510 QAT_FIELD_SET(val32,
511 csr.associated_data_len_in_bytes,
512 QAT_CIPHER_AEAD_AAD_SIZE_LE_BITPOS,
513 QAT_CIPHER_AEAD_AAD_SIZE_MASK);
514
515 QAT_FIELD_SET(val32,
516 csr.crc_reflect_out,
517 QAT_CIPHER_UCS_REFLECT_OUT_LE_BITPOS,
518 QAT_CIPHER_UCS_REFLECT_OUT_MASK);
519
520 QAT_FIELD_SET(val32,
521 csr.crc_reflect_in,
522 QAT_CIPHER_UCS_REFLECT_IN_LE_BITPOS,
523 QAT_CIPHER_UCS_REFLECT_IN_MASK);
524
525 QAT_FIELD_SET(val32,
526 csr.crc_encoding,
527 QAT_CIPHER_UCS_CRC_ENCODING_LE_BITPOS,
528 QAT_CIPHER_UCS_CRC_ENCODING_MASK);
529
530 return rte_bswap32(val32);
531 }
532
533 /* ========================================================================= */
534 /* COMPRESSION SLICE */
535 /* ========================================================================= */
536
537 enum icp_qat_hw_compression_direction {
538 ICP_QAT_HW_COMPRESSION_DIR_COMPRESS = 0,
539 ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS = 1,
540 ICP_QAT_HW_COMPRESSION_DIR_DELIMITER = 2
541 };
542
543 enum icp_qat_hw_compression_delayed_match {
544 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED = 0,
545 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_ENABLED = 1,
546 ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DELIMITER = 2
547 };
548
549 enum icp_qat_hw_compression_algo {
550 ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE = 0,
551 ICP_QAT_HW_COMPRESSION_ALGO_LZS = 1,
552 ICP_QAT_HW_COMPRESSION_ALGO_DELIMITER = 2
553 };
554
555
556 enum icp_qat_hw_compression_depth {
557 ICP_QAT_HW_COMPRESSION_DEPTH_1 = 0,
558 ICP_QAT_HW_COMPRESSION_DEPTH_4 = 1,
559 ICP_QAT_HW_COMPRESSION_DEPTH_8 = 2,
560 ICP_QAT_HW_COMPRESSION_DEPTH_16 = 3,
561 ICP_QAT_HW_COMPRESSION_DEPTH_DELIMITER = 4
562 };
563
564 enum icp_qat_hw_compression_file_type {
565 ICP_QAT_HW_COMPRESSION_FILE_TYPE_0 = 0,
566 ICP_QAT_HW_COMPRESSION_FILE_TYPE_1 = 1,
567 ICP_QAT_HW_COMPRESSION_FILE_TYPE_2 = 2,
568 ICP_QAT_HW_COMPRESSION_FILE_TYPE_3 = 3,
569 ICP_QAT_HW_COMPRESSION_FILE_TYPE_4 = 4,
570 ICP_QAT_HW_COMPRESSION_FILE_TYPE_DELIMITER = 5
571 };
572
573 struct icp_qat_hw_compression_config {
574 uint32_t val;
575 uint32_t reserved;
576 };
577
578 #define QAT_COMPRESSION_DIR_BITPOS 4
579 #define QAT_COMPRESSION_DIR_MASK 0x7
580 #define QAT_COMPRESSION_DELAYED_MATCH_BITPOS 16
581 #define QAT_COMPRESSION_DELAYED_MATCH_MASK 0x1
582 #define QAT_COMPRESSION_ALGO_BITPOS 31
583 #define QAT_COMPRESSION_ALGO_MASK 0x1
584 #define QAT_COMPRESSION_DEPTH_BITPOS 28
585 #define QAT_COMPRESSION_DEPTH_MASK 0x7
586 #define QAT_COMPRESSION_FILE_TYPE_BITPOS 24
587 #define QAT_COMPRESSION_FILE_TYPE_MASK 0xF
588
589 #define ICP_QAT_HW_COMPRESSION_CONFIG_BUILD( \
590 dir, delayed, algo, depth, filetype) \
591 ((((dir) & QAT_COMPRESSION_DIR_MASK) << QAT_COMPRESSION_DIR_BITPOS) | \
592 (((delayed) & QAT_COMPRESSION_DELAYED_MATCH_MASK) \
593 << QAT_COMPRESSION_DELAYED_MATCH_BITPOS) | \
594 (((algo) & QAT_COMPRESSION_ALGO_MASK) \
595 << QAT_COMPRESSION_ALGO_BITPOS) | \
596 (((depth) & QAT_COMPRESSION_DEPTH_MASK) \
597 << QAT_COMPRESSION_DEPTH_BITPOS) | \
598 (((filetype) & QAT_COMPRESSION_FILE_TYPE_MASK) \
599 << QAT_COMPRESSION_FILE_TYPE_BITPOS))
600
601 #endif
602