1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2015-2019 Intel Corporation 3 */ 4 #ifndef _ICP_QAT_FW_LA_H_ 5 #define _ICP_QAT_FW_LA_H_ 6 #include "icp_qat_fw.h" 7 8 enum icp_qat_fw_la_cmd_id { 9 ICP_QAT_FW_LA_CMD_CIPHER = 0, 10 ICP_QAT_FW_LA_CMD_AUTH = 1, 11 ICP_QAT_FW_LA_CMD_CIPHER_HASH = 2, 12 ICP_QAT_FW_LA_CMD_HASH_CIPHER = 3, 13 ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM = 4, 14 ICP_QAT_FW_LA_CMD_TRNG_TEST = 5, 15 ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE = 6, 16 ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE = 7, 17 ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE = 8, 18 ICP_QAT_FW_LA_CMD_MGF1 = 9, 19 ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP = 10, 20 ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP = 11, 21 ICP_QAT_FW_LA_CMD_CIPHER_CRC = 17, 22 ICP_QAT_FW_LA_CMD_DELIMITER = 18 23 }; 24 25 /* In GEN_LCE Command ID 4 corresponds to AEAD */ 26 #define ICP_QAT_FW_LA_CMD_AEAD 4 27 28 #define ICP_QAT_FW_LA_ICV_VER_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK 29 #define ICP_QAT_FW_LA_ICV_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 30 #define ICP_QAT_FW_LA_TRNG_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK 31 #define ICP_QAT_FW_LA_TRNG_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 32 33 /* GEN_LCE Hash, HMAC and GCM Verification Status */ 34 #define ICP_QAT_FW_LA_VER_STATUS_FAIL ICP_QAT_FW_COMN_GEN_LCE_STATUS_FLAG_ERROR 35 36 37 struct icp_qat_fw_la_bulk_req { 38 struct icp_qat_fw_comn_req_hdr comn_hdr; 39 union { 40 struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars; 41 struct lce_key_buff_desc key_buff; 42 }; 43 struct icp_qat_fw_comn_req_mid comn_mid; 44 struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars; 45 struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl; 46 }; 47 48 #define QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_BITPOS 13 49 #define ICP_QAT_FW_LA_SINGLE_PASS_PROTO 1 50 #define QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_MASK 0x1 51 #define ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS 1 52 #define ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS 0 53 #define QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS 12 54 #define ICP_QAT_FW_LA_ZUC_3G_PROTO 1 55 #define QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK 0x1 56 #define QAT_LA_GCM_IV_LEN_FLAG_BITPOS 11 57 #define QAT_LA_GCM_IV_LEN_FLAG_MASK 0x1 58 #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER 1 59 #define ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER 0 60 #define QAT_LA_DIGEST_IN_BUFFER_BITPOS 10 61 #define QAT_LA_DIGEST_IN_BUFFER_MASK 0x1 62 #define ICP_QAT_FW_LA_SNOW_3G_PROTO 4 63 #define ICP_QAT_FW_LA_GCM_PROTO 2 64 #define ICP_QAT_FW_LA_CCM_PROTO 1 65 #define ICP_QAT_FW_LA_NO_PROTO 0 66 #define QAT_LA_PROTO_BITPOS 7 67 #define QAT_LA_PROTO_MASK 0x7 68 #define ICP_QAT_FW_LA_CMP_AUTH_RES 1 69 #define ICP_QAT_FW_LA_NO_CMP_AUTH_RES 0 70 #define QAT_LA_CMP_AUTH_RES_BITPOS 6 71 #define QAT_LA_CMP_AUTH_RES_MASK 0x1 72 #define ICP_QAT_FW_LA_RET_AUTH_RES 1 73 #define ICP_QAT_FW_LA_NO_RET_AUTH_RES 0 74 #define QAT_LA_RET_AUTH_RES_BITPOS 5 75 #define QAT_LA_RET_AUTH_RES_MASK 0x1 76 #define ICP_QAT_FW_LA_UPDATE_STATE 1 77 #define ICP_QAT_FW_LA_NO_UPDATE_STATE 0 78 #define QAT_LA_UPDATE_STATE_BITPOS 4 79 #define QAT_LA_UPDATE_STATE_MASK 0x1 80 #define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_CD_SETUP 0 81 #define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_SHRAM_CP 1 82 #define QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS 3 83 #define QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK 0x1 84 #define ICP_QAT_FW_CIPH_IV_64BIT_PTR 0 85 #define ICP_QAT_FW_CIPH_IV_16BYTE_DATA 1 86 #define QAT_LA_CIPH_IV_FLD_BITPOS 2 87 #define QAT_LA_CIPH_IV_FLD_MASK 0x1 88 #define ICP_QAT_FW_LA_PARTIAL_NONE 0 89 #define ICP_QAT_FW_LA_PARTIAL_START 1 90 #define ICP_QAT_FW_LA_PARTIAL_MID 3 91 #define ICP_QAT_FW_LA_PARTIAL_END 2 92 #define QAT_LA_PARTIAL_BITPOS 0 93 #define QAT_LA_PARTIAL_MASK 0x3 94 #define QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS_BITPOS 0 95 #define QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS 1 96 #define QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS_MASK 0x1 97 #define QAT_LA_USE_WCP_SLICE 1 98 #define QAT_LA_USE_WCP_SLICE_BITPOS 2 99 #define QAT_LA_USE_WCP_SLICE_MASK 0x1 100 #define QAT_LA_USE_WAT_SLICE_BITPOS 3 101 #define QAT_LA_USE_WAT_SLICE 1 102 #define QAT_LA_USE_WAT_SLICE_MASK 0x1 103 104 /* GEN_LCE specific Crypto Flags fields */ 105 #define ICP_QAT_FW_SYM_AEAD_ALGO_BITPOS 6 106 #define ICP_QAT_FW_SYM_AEAD_ALGO_MASK 0x3 107 #define ICP_QAT_FW_SYM_IV_SIZE_BITPOS 9 108 #define ICP_QAT_FW_SYM_IV_SIZE_MASK 0x3 109 #define ICP_QAT_FW_SYM_IV_IN_DESC_BITPOS 11 110 #define ICP_QAT_FW_SYM_IV_IN_DESC_MASK 0x1 111 #define ICP_QAT_FW_SYM_IV_IN_DESC_VALID 1 112 #define ICP_QAT_FW_SYM_DIRECTION_BITPOS 15 113 #define ICP_QAT_FW_SYM_DIRECTION_MASK 0x1 114 #define ICP_QAT_FW_SYM_COMM_ADDR_SGL 1 115 116 /* In GEN_LCE AEAD AES GCM Algorithm has ID 0 */ 117 #define QAT_LA_CRYPTO_AEAD_AES_GCM_GEN_LCE 0 118 119 #define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \ 120 cmp_auth, ret_auth, update_state, \ 121 ciph_iv, ciphcfg, partial) \ 122 (((zuc_proto & QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) << \ 123 QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS) | \ 124 ((gcm_iv_len & QAT_LA_GCM_IV_LEN_FLAG_MASK) << \ 125 QAT_LA_GCM_IV_LEN_FLAG_BITPOS) | \ 126 ((auth_rslt & QAT_LA_DIGEST_IN_BUFFER_MASK) << \ 127 QAT_LA_DIGEST_IN_BUFFER_BITPOS) | \ 128 ((proto & QAT_LA_PROTO_MASK) << \ 129 QAT_LA_PROTO_BITPOS) | \ 130 ((cmp_auth & QAT_LA_CMP_AUTH_RES_MASK) << \ 131 QAT_LA_CMP_AUTH_RES_BITPOS) | \ 132 ((ret_auth & QAT_LA_RET_AUTH_RES_MASK) << \ 133 QAT_LA_RET_AUTH_RES_BITPOS) | \ 134 ((update_state & QAT_LA_UPDATE_STATE_MASK) << \ 135 QAT_LA_UPDATE_STATE_BITPOS) | \ 136 ((ciph_iv & QAT_LA_CIPH_IV_FLD_MASK) << \ 137 QAT_LA_CIPH_IV_FLD_BITPOS) | \ 138 ((ciphcfg & QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) << \ 139 QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS) | \ 140 ((partial & QAT_LA_PARTIAL_MASK) << \ 141 QAT_LA_PARTIAL_BITPOS)) 142 143 #define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_GET(flags) \ 144 QAT_FIELD_GET(flags, QAT_LA_CIPH_IV_FLD_BITPOS, \ 145 QAT_LA_CIPH_IV_FLD_MASK) 146 147 #define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_GET(flags) \ 148 QAT_FIELD_GET(flags, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \ 149 QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) 150 151 #define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_GET(flags) \ 152 QAT_FIELD_GET(flags, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \ 153 QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) 154 155 #define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_GET(flags) \ 156 QAT_FIELD_GET(flags, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \ 157 QAT_LA_GCM_IV_LEN_FLAG_MASK) 158 159 #define ICP_QAT_FW_LA_PROTO_GET(flags) \ 160 QAT_FIELD_GET(flags, QAT_LA_PROTO_BITPOS, QAT_LA_PROTO_MASK) 161 162 #define ICP_QAT_FW_LA_CMP_AUTH_GET(flags) \ 163 QAT_FIELD_GET(flags, QAT_LA_CMP_AUTH_RES_BITPOS, \ 164 QAT_LA_CMP_AUTH_RES_MASK) 165 166 #define ICP_QAT_FW_LA_RET_AUTH_GET(flags) \ 167 QAT_FIELD_GET(flags, QAT_LA_RET_AUTH_RES_BITPOS, \ 168 QAT_LA_RET_AUTH_RES_MASK) 169 170 #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_GET(flags) \ 171 QAT_FIELD_GET(flags, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \ 172 QAT_LA_DIGEST_IN_BUFFER_MASK) 173 174 #define ICP_QAT_FW_LA_UPDATE_STATE_GET(flags) \ 175 QAT_FIELD_GET(flags, QAT_LA_UPDATE_STATE_BITPOS, \ 176 QAT_LA_UPDATE_STATE_MASK) 177 178 #define ICP_QAT_FW_LA_PARTIAL_GET(flags) \ 179 QAT_FIELD_GET(flags, QAT_LA_PARTIAL_BITPOS, \ 180 QAT_LA_PARTIAL_MASK) 181 182 #define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(flags, val) \ 183 QAT_FIELD_SET(flags, val, QAT_LA_CIPH_IV_FLD_BITPOS, \ 184 QAT_LA_CIPH_IV_FLD_MASK) 185 186 #define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_SET(flags, val) \ 187 QAT_FIELD_SET(flags, val, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \ 188 QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) 189 190 #define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(flags, val) \ 191 QAT_FIELD_SET(flags, val, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \ 192 QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) 193 194 #define ICP_QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_SET(flags, val) \ 195 QAT_FIELD_SET(flags, val, QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_BITPOS, \ 196 QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_MASK) 197 198 #define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(flags, val) \ 199 QAT_FIELD_SET(flags, val, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \ 200 QAT_LA_GCM_IV_LEN_FLAG_MASK) 201 202 #define ICP_QAT_FW_LA_PROTO_SET(flags, val) \ 203 QAT_FIELD_SET(flags, val, QAT_LA_PROTO_BITPOS, \ 204 QAT_LA_PROTO_MASK) 205 206 #define ICP_QAT_FW_LA_CMP_AUTH_SET(flags, val) \ 207 QAT_FIELD_SET(flags, val, QAT_LA_CMP_AUTH_RES_BITPOS, \ 208 QAT_LA_CMP_AUTH_RES_MASK) 209 210 #define ICP_QAT_FW_LA_RET_AUTH_SET(flags, val) \ 211 QAT_FIELD_SET(flags, val, QAT_LA_RET_AUTH_RES_BITPOS, \ 212 QAT_LA_RET_AUTH_RES_MASK) 213 214 #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(flags, val) \ 215 QAT_FIELD_SET(flags, val, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \ 216 QAT_LA_DIGEST_IN_BUFFER_MASK) 217 218 #define ICP_QAT_FW_LA_UPDATE_STATE_SET(flags, val) \ 219 QAT_FIELD_SET(flags, val, QAT_LA_UPDATE_STATE_BITPOS, \ 220 QAT_LA_UPDATE_STATE_MASK) 221 222 #define ICP_QAT_FW_LA_PARTIAL_SET(flags, val) \ 223 QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \ 224 QAT_LA_PARTIAL_MASK) 225 226 #define ICP_QAT_FW_USE_EXTENDED_PROTOCOL_FLAGS_SET(flags, val) \ 227 QAT_FIELD_SET(flags, val, \ 228 QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS_BITPOS, \ 229 QAT_LA_USE_EXTENDED_PROTOCOL_FLAGS_MASK) 230 231 #define ICP_QAT_FW_USE_WCP_SLICE_SET(flags, val) \ 232 QAT_FIELD_SET(flags, val, \ 233 QAT_LA_USE_WCP_SLICE_BITPOS, \ 234 QAT_LA_USE_WCP_SLICE_MASK) 235 236 #define ICP_QAT_FW_USE_WAT_SLICE_SET(flags, val) \ 237 QAT_FIELD_SET(flags, val, \ 238 QAT_LA_USE_WAT_SLICE_BITPOS, \ 239 QAT_LA_USE_WAT_SLICE_MASK) 240 241 /* GEN_LCE specific Crypto Flags operations */ 242 #define ICP_QAT_FW_SYM_AEAD_ALGO_SET(flags, val) \ 243 QAT_FIELD_SET(flags, val, ICP_QAT_FW_SYM_AEAD_ALGO_BITPOS, \ 244 ICP_QAT_FW_SYM_AEAD_ALGO_MASK) 245 246 #define ICP_QAT_FW_SYM_IV_SIZE_SET(flags, val) \ 247 QAT_FIELD_SET(flags, val, ICP_QAT_FW_SYM_IV_SIZE_BITPOS, \ 248 ICP_QAT_FW_SYM_IV_SIZE_MASK) 249 250 #define ICP_QAT_FW_SYM_IV_IN_DESC_FLAG_SET(flags, val) \ 251 QAT_FIELD_SET(flags, val, ICP_QAT_FW_SYM_IV_IN_DESC_BITPOS, \ 252 ICP_QAT_FW_SYM_IV_IN_DESC_MASK) 253 254 #define ICP_QAT_FW_SYM_DIR_FLAG_SET(flags, val) \ 255 QAT_FIELD_SET(flags, val, ICP_QAT_FW_SYM_DIRECTION_BITPOS, \ 256 ICP_QAT_FW_SYM_DIRECTION_MASK) 257 258 #define QAT_FW_LA_MODE2 1 259 #define QAT_FW_LA_NO_MODE2 0 260 #define QAT_FW_LA_MODE2_MASK 0x1 261 #define QAT_FW_LA_MODE2_BITPOS 5 262 #define ICP_QAT_FW_HASH_FLAG_MODE2_SET(flags, val) \ 263 QAT_FIELD_SET(flags, \ 264 val, \ 265 QAT_FW_LA_MODE2_BITPOS, \ 266 QAT_FW_LA_MODE2_MASK) 267 268 struct icp_qat_fw_cipher_req_hdr_cd_pars { 269 union { 270 struct { 271 uint64_t content_desc_addr; 272 uint16_t content_desc_resrvd1; 273 uint8_t content_desc_params_sz; 274 uint8_t content_desc_hdr_resrvd2; 275 uint32_t content_desc_resrvd3; 276 } s; 277 struct { 278 uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4]; 279 } s1; 280 } u; 281 }; 282 283 struct icp_qat_fw_cipher_auth_req_hdr_cd_pars { 284 union { 285 struct { 286 uint64_t content_desc_addr; 287 uint16_t content_desc_resrvd1; 288 uint8_t content_desc_params_sz; 289 uint8_t content_desc_hdr_resrvd2; 290 uint32_t content_desc_resrvd3; 291 } s; 292 struct { 293 uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4]; 294 } sl; 295 } u; 296 }; 297 298 struct icp_qat_fw_cipher_cd_ctrl_hdr { 299 uint8_t cipher_state_sz; 300 uint8_t cipher_key_sz; 301 uint8_t cipher_cfg_offset; 302 uint8_t next_curr_id; 303 uint8_t cipher_padding_sz; 304 uint8_t resrvd1; 305 uint16_t resrvd2; 306 uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3]; 307 }; 308 309 struct icp_qat_fw_auth_cd_ctrl_hdr { 310 uint32_t resrvd1; 311 uint8_t resrvd2; 312 uint8_t hash_flags; 313 uint8_t hash_cfg_offset; 314 uint8_t next_curr_id; 315 uint8_t resrvd3; 316 uint8_t outer_prefix_sz; 317 uint8_t final_sz; 318 uint8_t inner_res_sz; 319 uint8_t resrvd4; 320 uint8_t inner_state1_sz; 321 uint8_t inner_state2_offset; 322 uint8_t inner_state2_sz; 323 uint8_t outer_config_offset; 324 uint8_t outer_state1_sz; 325 uint8_t outer_res_sz; 326 uint8_t outer_prefix_offset; 327 }; 328 329 struct icp_qat_fw_cipher_auth_cd_ctrl_hdr { 330 uint8_t cipher_state_sz; 331 uint8_t cipher_key_sz; 332 uint8_t cipher_cfg_offset; 333 uint8_t next_curr_id_cipher; 334 uint8_t cipher_padding_sz; 335 uint8_t hash_flags; 336 uint8_t hash_cfg_offset; 337 uint8_t next_curr_id_auth; 338 uint8_t resrvd1; 339 uint8_t outer_prefix_sz; 340 uint8_t final_sz; 341 uint8_t inner_res_sz; 342 uint8_t resrvd2; 343 uint8_t inner_state1_sz; 344 uint8_t inner_state2_offset; 345 uint8_t inner_state2_sz; 346 uint8_t outer_config_offset; 347 uint8_t outer_state1_sz; 348 uint8_t outer_res_sz; 349 uint8_t outer_prefix_offset; 350 }; 351 352 #define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1 353 #define ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED 0 354 #define ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS 3 355 #define ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS 4 356 #define ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX 240 357 #define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET 24 358 #define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0) 359 360 struct __rte_packed_begin icp_qat_fw_la_cipher_req_params { 361 uint32_t cipher_offset; 362 uint32_t cipher_length; 363 union { 364 uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4]; 365 struct { 366 uint64_t cipher_IV_ptr; 367 uint64_t resrvd1; 368 } s; 369 } u; 370 uint64_t spc_aad_addr; 371 uint64_t spc_auth_res_addr; 372 uint16_t spc_aad_sz; 373 uint8_t reserved; 374 uint8_t spc_auth_res_sz; 375 } __rte_packed_end; 376 377 struct __rte_packed_begin icp_qat_fw_la_auth_req_params { 378 uint32_t auth_off; 379 uint32_t auth_len; 380 union { 381 uint64_t auth_partial_st_prefix; 382 uint64_t aad_adr; 383 } u1; 384 uint64_t auth_res_addr; 385 union { 386 uint8_t inner_prefix_sz; 387 uint8_t aad_sz; 388 } u2; 389 uint8_t resrvd1; 390 uint8_t hash_state_sz; 391 uint8_t auth_res_sz; 392 } __rte_packed_end; 393 394 struct icp_qat_fw_la_auth_req_params_resrvd_flds { 395 uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_6]; 396 union { 397 uint8_t inner_prefix_sz; 398 uint8_t aad_sz; 399 } u2; 400 uint8_t resrvd1; 401 uint16_t resrvd2; 402 }; 403 404 struct icp_qat_fw_la_resp { 405 struct icp_qat_fw_comn_resp_hdr comn_resp; 406 uint64_t opaque_data; 407 uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4]; 408 }; 409 410 #define ICP_QAT_FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t) \ 411 ((((cd_ctrl_hdr_t)->next_curr_id_cipher) & \ 412 ICP_QAT_FW_COMN_NEXT_ID_MASK) >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS)) 413 414 #define ICP_QAT_FW_CIPHER_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ 415 { (cd_ctrl_hdr_t)->next_curr_id_cipher = \ 416 ((((cd_ctrl_hdr_t)->next_curr_id_cipher) \ 417 & ICP_QAT_FW_COMN_CURR_ID_MASK) | \ 418 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \ 419 & ICP_QAT_FW_COMN_NEXT_ID_MASK)) } 420 421 #define ICP_QAT_FW_CIPHER_CURR_ID_GET(cd_ctrl_hdr_t) \ 422 (((cd_ctrl_hdr_t)->next_curr_id_cipher) \ 423 & ICP_QAT_FW_COMN_CURR_ID_MASK) 424 425 #define ICP_QAT_FW_CIPHER_CURR_ID_SET(cd_ctrl_hdr_t, val) \ 426 { (cd_ctrl_hdr_t)->next_curr_id_cipher = \ 427 ((((cd_ctrl_hdr_t)->next_curr_id_cipher) \ 428 & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ 429 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) } 430 431 #define ICP_QAT_FW_AUTH_NEXT_ID_GET(cd_ctrl_hdr_t) \ 432 ((((cd_ctrl_hdr_t)->next_curr_id_auth) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \ 433 >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS)) 434 435 #define ICP_QAT_FW_AUTH_NEXT_ID_SET(cd_ctrl_hdr_t, val) \ 436 { (cd_ctrl_hdr_t)->next_curr_id_auth = \ 437 ((((cd_ctrl_hdr_t)->next_curr_id_auth) \ 438 & ICP_QAT_FW_COMN_CURR_ID_MASK) | \ 439 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \ 440 & ICP_QAT_FW_COMN_NEXT_ID_MASK)) } 441 442 #define ICP_QAT_FW_AUTH_CURR_ID_GET(cd_ctrl_hdr_t) \ 443 (((cd_ctrl_hdr_t)->next_curr_id_auth) \ 444 & ICP_QAT_FW_COMN_CURR_ID_MASK) 445 446 #define ICP_QAT_FW_AUTH_CURR_ID_SET(cd_ctrl_hdr_t, val) \ 447 { (cd_ctrl_hdr_t)->next_curr_id_auth = \ 448 ((((cd_ctrl_hdr_t)->next_curr_id_auth) \ 449 & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ 450 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) } 451 452 #define ICP_QAT_FW_LA_USE_WIRELESS_SLICE_TYPE 2 453 #define ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE 1 454 #define ICP_QAT_FW_LA_USE_LEGACY_SLICE_TYPE 0 455 #define QAT_LA_SLICE_TYPE_BITPOS 14 456 #define QAT_LA_SLICE_TYPE_MASK 0x3 457 #define ICP_QAT_FW_LA_SLICE_TYPE_SET(flags, val) \ 458 QAT_FIELD_SET(flags, val, QAT_LA_SLICE_TYPE_BITPOS, \ 459 QAT_LA_SLICE_TYPE_MASK) 460 461 struct icp_qat_fw_la_cipher_20_req_params { 462 uint32_t cipher_offset; 463 uint32_t cipher_length; 464 union { 465 uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4]; 466 struct { 467 uint64_t cipher_IV_ptr; 468 uint64_t resrvd1; 469 } s; 470 471 } u; 472 uint32_t spc_aad_offset; 473 uint32_t spc_aad_sz; 474 uint64_t spc_aad_addr; 475 uint64_t spc_auth_res_addr; 476 uint8_t reserved[3]; 477 uint8_t spc_auth_res_sz; 478 }; 479 480 struct icp_qat_fw_la_cipher_30_req_params { 481 uint32_t spc_aad_sz; 482 uint8_t cipher_length; 483 uint8_t reserved[2]; 484 uint8_t spc_auth_res_sz; 485 union { 486 uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4]; 487 struct { 488 uint64_t cipher_IV_ptr; 489 uint64_t resrvd1; 490 } s; 491 492 } u; 493 }; 494 495 #endif 496