1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2021 Intel Corporation 3 */ 4 5 #ifndef ADF_TRANSPORT_ACCESS_MACROS_GEN4VF_H 6 #define ADF_TRANSPORT_ACCESS_MACROS_GEN4VF_H 7 8 #include "adf_transport_access_macros.h" 9 #include "adf_transport_access_macros_gen4.h" 10 11 #define ADF_RING_CSR_ADDR_OFFSET_GEN4VF 0x0 12 13 #define WRITE_CSR_RING_BASE_GEN4VF(csr_base_addr, bank, ring, value) \ 14 do { \ 15 uint32_t l_base = 0, u_base = 0; \ 16 l_base = (uint32_t)(value & 0xFFFFFFFF); \ 17 u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \ 18 ADF_CSR_WR(csr_base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN4VF, \ 19 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + \ 20 ADF_RING_CSR_RING_LBASE_GEN4 + (ring << 2), \ 21 l_base); \ 22 ADF_CSR_WR(csr_base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN4VF, \ 23 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + \ 24 ADF_RING_CSR_RING_UBASE_GEN4 + (ring << 2), \ 25 u_base); \ 26 } while (0) 27 28 #define WRITE_CSR_RING_CONFIG_GEN4VF(csr_base_addr, bank, ring, value) \ 29 ADF_CSR_WR(csr_base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN4VF, \ 30 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + \ 31 ADF_RING_CSR_RING_CONFIG_GEN4 + (ring << 2), value) 32 33 #define WRITE_CSR_RING_TAIL_GEN4VF(csr_base_addr, bank, ring, value) \ 34 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_GEN4VF, \ 35 (ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 36 ADF_RING_CSR_RING_TAIL + ((ring) << 2), (value)) 37 38 #define WRITE_CSR_RING_HEAD_GEN4VF(csr_base_addr, bank, ring, value) \ 39 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_GEN4VF, \ 40 (ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 41 ADF_RING_CSR_RING_HEAD + ((ring) << 2), (value)) 42 43 #define WRITE_CSR_RING_SRV_ARB_EN_GEN4VF(csr_base_addr, bank, value) \ 44 ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_GEN4VF, \ 45 (ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \ 46 ADF_RING_CSR_RING_SRV_ARB_EN, (value)) 47 48 #endif 49