xref: /dpdk/drivers/common/nitrox/nitrox_csr.h (revision 751ea2c0f7580a7c51c7d12fc5220405ddcc9ca6)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2019 Marvell International Ltd.
3  */
4 
5 #ifndef _NITROX_CSR_H_
6 #define _NITROX_CSR_H_
7 
8 #include <rte_common.h>
9 #include <rte_io.h>
10 
11 #define CSR_DELAY	30
12 #define NITROX_CSR_ADDR(bar_addr, offset) (bar_addr + (offset))
13 
14 /* NPS packet registers */
15 #define NPS_PKT_IN_INSTR_CTLX(_i)	(0x10060UL + ((_i) * 0x40000UL))
16 #define NPS_PKT_IN_INSTR_BADDRX(_i)	(0x10068UL + ((_i) * 0x40000UL))
17 #define NPS_PKT_IN_INSTR_RSIZEX(_i)	(0x10070UL + ((_i) * 0x40000UL))
18 #define NPS_PKT_IN_DONE_CNTSX(_i)	(0x10080UL + ((_i) * 0x40000UL))
19 #define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i)	(0x10078UL + ((_i) * 0x40000UL))
20 #define NPS_PKT_IN_INT_LEVELSX(_i)		(0x10088UL + ((_i) * 0x40000UL))
21 #define NPS_PKT_SLC_CTLX(_i)		(0x10000UL + ((_i) * 0x40000UL))
22 #define NPS_PKT_SLC_CNTSX(_i)		(0x10008UL + ((_i) * 0x40000UL))
23 #define NPS_PKT_SLC_INT_LEVELSX(_i)	(0x10010UL + ((_i) * 0x40000UL))
24 
25 /* AQM Virtual Function Registers */
26 #define AQMQ_QSZX(_i)			(0x20008UL + ((_i) * 0x40000UL))
27 
28 /* ZQM virtual function registers */
29 #define ZQMQ_DRBLX(_i)			(0x30000UL + ((_i) * 0x40000UL))
30 #define ZQMQ_QSZX(_i)			(0x30008UL + ((_i) * 0x40000UL))
31 #define ZQMQ_BADRX(_i)			(0x30010UL + ((_i) * 0x40000UL))
32 #define ZQMQ_NXT_CMDX(_i)		(0x30018UL + ((_i) * 0x40000UL))
33 #define ZQMQ_CMD_CNTX(_i)		(0x30020UL + ((_i) * 0x40000UL))
34 #define ZQMQ_CMP_THRX(_i)		(0x30028UL + ((_i) * 0x40000UL))
35 #define ZQMQ_CMP_CNTX(_i)		(0x30030UL + ((_i) * 0x40000UL))
36 #define ZQMQ_TIMER_LDX(_i)		(0x30038UL + ((_i) * 0x40000UL))
37 #define ZQMQ_ENX(_i)			(0x30048UL + ((_i) * 0x40000UL))
38 #define ZQMQ_ACTIVITY_STATX(_i)		(0x30050UL + ((_i) * 0x40000UL))
39 
40 static inline uint64_t
nitrox_read_csr(uint8_t * bar_addr,uint64_t offset)41 nitrox_read_csr(uint8_t *bar_addr, uint64_t offset)
42 {
43 	return rte_read64(bar_addr + offset);
44 }
45 
46 static inline void
nitrox_write_csr(uint8_t * bar_addr,uint64_t offset,uint64_t value)47 nitrox_write_csr(uint8_t *bar_addr, uint64_t offset, uint64_t value)
48 {
49 	rte_write64(value, (bar_addr + offset));
50 }
51 
52 #endif /* _NITROX_CSR_H_ */
53