1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (C) Mellanox Technologies, Ltd. 2001-2020. 3 */ 4 5 #ifndef MLX5_WIN_DEFS_H 6 #define MLX5_WIN_DEFS_H 7 8 #include <rte_bitops.h> 9 10 enum { 11 MLX5_CQE_OWNER_MASK = 1, 12 MLX5_CQE_REQ = 0, 13 MLX5_CQE_RESP_WR_IMM = 1, 14 MLX5_CQE_RESP_SEND = 2, 15 MLX5_CQE_RESP_SEND_IMM = 3, 16 MLX5_CQE_RESP_SEND_INV = 4, 17 MLX5_CQE_RESIZE_CQ = 5, 18 MLX5_CQE_NO_PACKET = 6, 19 MLX5_CQE_REQ_ERR = 13, 20 MLX5_CQE_RESP_ERR = 14, 21 MLX5_CQE_INVALID = 15, 22 }; 23 24 enum { 25 MLX5_OPCODE_NOP = 0x00, 26 MLX5_OPCODE_SEND_INVAL = 0x01, 27 MLX5_OPCODE_RDMA_WRITE = 0x08, 28 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 29 MLX5_OPCODE_SEND = 0x0a, 30 MLX5_OPCODE_SEND_IMM = 0x0b, 31 MLX5_OPCODE_TSO = 0x0e, 32 MLX5_OPCODE_RDMA_READ = 0x10, 33 MLX5_OPCODE_ATOMIC_CS = 0x11, 34 MLX5_OPCODE_ATOMIC_FA = 0x12, 35 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 36 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 37 MLX5_OPCODE_FMR = 0x19, 38 MLX5_OPCODE_LOCAL_INVAL = 0x1b, 39 MLX5_OPCODE_CONFIG_CMD = 0x1f, 40 MLX5_OPCODE_UMR = 0x25, 41 MLX5_OPCODE_TAG_MATCHING = 0x28 42 }; 43 44 enum mlx5dv_cq_init_attr_mask { 45 MLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE = RTE_BIT32(0), 46 MLX5DV_CQ_INIT_ATTR_MASK_FLAG = RTE_BIT32(1), 47 MLX5DV_CQ_INIT_ATTR_MASK_CQE_SIZE = RTE_BIT32(2), 48 }; 49 50 enum mlx5dv_cqe_comp_res_format { 51 MLX5DV_CQE_RES_FORMAT_HASH = RTE_BIT32(0), 52 MLX5DV_CQE_RES_FORMAT_CSUM = RTE_BIT32(1), 53 MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX = RTE_BIT32(2), 54 }; 55 56 enum ibv_access_flags { 57 IBV_ACCESS_LOCAL_WRITE = RTE_BIT32(0), 58 IBV_ACCESS_REMOTE_WRITE = RTE_BIT32(1), 59 IBV_ACCESS_REMOTE_READ = RTE_BIT32(2), 60 IBV_ACCESS_REMOTE_ATOMIC = RTE_BIT32(3), 61 IBV_ACCESS_MW_BIND = RTE_BIT32(4), 62 IBV_ACCESS_ZERO_BASED = RTE_BIT32(5), 63 IBV_ACCESS_ON_DEMAND = RTE_BIT32(6), 64 }; 65 66 enum mlx5_ib_uapi_devx_create_event_channel_flags { 67 MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA = RTE_BIT32(0), 68 }; 69 70 #define MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA \ 71 MLX5_IB_UAPI_DEVX_CR_EV_CH_FLAGS_OMIT_DATA 72 73 enum { 74 MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01, 75 MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02, 76 MLX5_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04, 77 MLX5_CQE_SYNDROME_WR_FLUSH_ERR = 0x05, 78 MLX5_CQE_SYNDROME_MW_BIND_ERR = 0x06, 79 MLX5_CQE_SYNDROME_BAD_RESP_ERR = 0x10, 80 MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11, 81 MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12, 82 MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13, 83 MLX5_CQE_SYNDROME_REMOTE_OP_ERR = 0x14, 84 MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15, 85 MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16, 86 MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22, 87 }; 88 89 enum { 90 MLX5_ETH_WQE_L3_CSUM = RTE_BIT32(6), 91 MLX5_ETH_WQE_L4_CSUM = RTE_BIT32(7), 92 }; 93 94 enum { 95 MLX5_WQE_CTRL_SOLICITED = RTE_BIT32(1), 96 MLX5_WQE_CTRL_CQ_UPDATE = RTE_BIT32(3), 97 MLX5_WQE_CTRL_INITIATOR_SMALL_FENCE = RTE_BIT32(5), 98 MLX5_WQE_CTRL_FENCE = RTE_BIT32(7), 99 }; 100 101 enum { 102 MLX5_SEND_WQE_BB = 64, 103 MLX5_SEND_WQE_SHIFT = 6, 104 }; 105 106 /* Verbs headers do not support -pedantic. */ 107 #ifdef PEDANTIC 108 #pragma GCC diagnostic ignored "-Wpedantic" 109 #endif 110 111 /* 112 * RX Hash fields enable to set which incoming packet's field should 113 * participates in RX Hash. Each flag represent certain packet's field, 114 * when the flag is set the field that is represented by the flag will 115 * participate in RX Hash calculation. 116 * Note: IPV4 and IPV6 flags can't be enabled together on the same QP, 117 * TCP and UDP flags can't be enabled together on the same QP. 118 */ 119 enum ibv_rx_hash_fields { 120 IBV_RX_HASH_SRC_IPV4 = RTE_BIT32(0), 121 IBV_RX_HASH_DST_IPV4 = RTE_BIT32(1), 122 IBV_RX_HASH_SRC_IPV6 = RTE_BIT32(2), 123 IBV_RX_HASH_DST_IPV6 = RTE_BIT32(3), 124 IBV_RX_HASH_SRC_PORT_TCP = RTE_BIT32(4), 125 IBV_RX_HASH_DST_PORT_TCP = RTE_BIT32(5), 126 IBV_RX_HASH_SRC_PORT_UDP = RTE_BIT32(6), 127 IBV_RX_HASH_DST_PORT_UDP = RTE_BIT32(7), 128 IBV_RX_HASH_IPSEC_SPI = RTE_BIT32(8), 129 IBV_RX_HASH_INNER = RTE_BIT32(31), 130 }; 131 132 #ifdef PEDANTIC 133 #pragma GCC diagnostic error "-Wpedantic" 134 #endif 135 136 enum { 137 MLX5_RCV_DBR = 0, 138 MLX5_SND_DBR = 1, 139 }; 140 141 #ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 142 #define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 0x0 143 #endif 144 #ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL 145 #define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL 0x1 146 #endif 147 #ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 148 #define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 0x2 149 #endif 150 #ifndef MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL 151 #define MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL 0x3 152 #endif 153 154 enum ibv_flow_flags { 155 IBV_FLOW_ATTR_FLAGS_ALLOW_LOOP_BACK = RTE_BIT32(0), 156 IBV_FLOW_ATTR_FLAGS_DONT_TRAP = RTE_BIT32(1), 157 IBV_FLOW_ATTR_FLAGS_EGRESS = RTE_BIT32(2), 158 }; 159 160 enum ibv_flow_attr_type { 161 /* Steering according to rule specifications. */ 162 IBV_FLOW_ATTR_NORMAL = 0x0, 163 /* 164 * Default unicast and multicast rule - 165 * receive all Eth traffic which isn't steered to any QP. 166 */ 167 IBV_FLOW_ATTR_ALL_DEFAULT = 0x1, 168 /* 169 * Default multicast rule - 170 * receive all Eth multicast traffic which isn't steered to any QP. 171 */ 172 IBV_FLOW_ATTR_MC_DEFAULT = 0x2, 173 /* Sniffer rule - receive all port traffic. */ 174 IBV_FLOW_ATTR_SNIFFER = 0x3, 175 }; 176 177 enum mlx5dv_flow_table_type { 178 MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_RX = 0x0, 179 MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_TX = 0x1, 180 MLX5_IB_UAPI_FLOW_TABLE_TYPE_FDB = 0x2, 181 MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_RX = 0x3, 182 }; 183 184 #define MLX5DV_FLOW_TABLE_TYPE_NIC_RX MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_RX 185 #define MLX5DV_FLOW_TABLE_TYPE_NIC_TX MLX5_IB_UAPI_FLOW_TABLE_TYPE_NIC_TX 186 #define MLX5DV_FLOW_TABLE_TYPE_FDB MLX5_IB_UAPI_FLOW_TABLE_TYPE_FDB 187 #define MLX5DV_FLOW_TABLE_TYPE_RDMA_RX MLX5_IB_UAPI_FLOW_TABLE_TYPE_RDMA_RX 188 189 struct mlx5dv_flow_match_parameters { 190 size_t match_sz; 191 uint64_t match_buf[]; /* Device spec format */ 192 }; 193 194 struct mlx5dv_flow_matcher_attr { 195 enum ibv_flow_attr_type type; 196 uint32_t flags; /* From enum ibv_flow_flags. */ 197 uint16_t priority; 198 uint8_t match_criteria_enable; /* Device spec format. */ 199 struct mlx5dv_flow_match_parameters *match_mask; 200 uint64_t comp_mask; /* Use mlx5dv_flow_matcher_attr_mask. */ 201 enum mlx5dv_flow_table_type ft_type; 202 }; 203 204 /* Windows specific mlx5_matcher. */ 205 struct mlx5_matcher { 206 void *ctx; 207 struct mlx5dv_flow_matcher_attr attr; 208 uint64_t match_buf[]; 209 }; 210 211 /* 212 * Windows mlx5_action. This struct is the 213 * equivalent of rdma-core struct mlx5dv_dr_action. 214 */ 215 struct mlx5_action { 216 int type; 217 struct { 218 uint32_t id; 219 } dest_tir; 220 }; 221 222 struct mlx5_wqe_srq_next_seg { 223 uint8_t rsvd0[2]; 224 rte_be16_t next_wqe_index; 225 uint8_t signature; 226 uint8_t rsvd1[11]; 227 }; 228 229 enum ibv_wq_state { 230 IBV_WQS_RESET, 231 IBV_WQS_RDY, 232 IBV_WQS_ERR, 233 IBV_WQS_UNKNOWN 234 }; 235 236 struct mlx5_wqe_data_seg { 237 rte_be32_t byte_count; 238 rte_be32_t lkey; 239 rte_be64_t addr; 240 }; 241 242 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP RTE_BIT32(4) 243 #define IBV_DEVICE_RAW_IP_CSUM RTE_BIT32(26) 244 #define IBV_RAW_PACKET_CAP_CVLAN_STRIPPING RTE_BIT32(0) 245 #define IBV_RAW_PACKET_CAP_SCATTER_FCS RTE_BIT32(1) 246 #define IBV_QPT_RAW_PACKET 8 247 248 enum { 249 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0x0, 250 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 0x1, 251 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 0x2, 252 MLX5_FLOW_CONTEXT_DEST_TYPE_QP = 0x3, 253 }; 254 255 enum { 256 MLX5_MATCH_OUTER_HEADERS = RTE_BIT32(0), 257 MLX5_MATCH_MISC_PARAMETERS = RTE_BIT32(1), 258 MLX5_MATCH_INNER_HEADERS = RTE_BIT32(2), 259 }; 260 261 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 262 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 263 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 264 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 265 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 266 #define IB_QPT_RAW_PACKET 8 267 268 #endif /* MLX5_WIN_DEFS_H */ 269