1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_PRM_H_ 7 #define RTE_PMD_MLX5_PRM_H_ 8 9 #include <unistd.h> 10 11 #include <rte_vect.h> 12 #include <rte_byteorder.h> 13 14 #include <mlx5_glue.h> 15 #include "mlx5_autoconf.h" 16 17 /* RSS hash key size. */ 18 #define MLX5_RSS_HASH_KEY_LEN 40 19 20 /* Get CQE owner bit. */ 21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK) 22 23 /* Get CQE format. */ 24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2) 25 26 /* Get CQE opcode. */ 27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4) 28 29 /* Get CQE number of mini CQEs. */ 30 #define MLX5_CQE_NUM_MINIS(op_own) (((op_own) & 0xf0) >> 4) 31 32 /* Get CQE solicited event. */ 33 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1) 34 35 /* Invalidate a CQE. */ 36 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4) 37 38 /* Initialize CQE validity iteration count. */ 39 #define MLX5_CQE_VIC_INIT 0xffu 40 41 /* Hardware index widths. */ 42 #define MLX5_CQ_INDEX_WIDTH 24 43 #define MLX5_WQ_INDEX_WIDTH 16 44 45 /* WQE Segment sizes in bytes. */ 46 #define MLX5_WSEG_SIZE 16u 47 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg) 48 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg) 49 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg) 50 51 /* WQE/WQEBB size in bytes. */ 52 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe) 53 54 /* 55 * Max size of a WQE session. 56 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments, 57 * the WQE size field in Control Segment is 6 bits wide. 58 */ 59 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE) 60 61 /* 62 * Default minimum number of Tx queues for inlining packets. 63 * If there are less queues as specified we assume we have 64 * no enough CPU resources (cycles) to perform inlining, 65 * the PCIe throughput is not supposed as bottleneck and 66 * inlining is disabled. 67 */ 68 #define MLX5_INLINE_MAX_TXQS 8u 69 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u 70 71 /* 72 * Default packet length threshold to be inlined with 73 * enhanced MPW. If packet length exceeds the threshold 74 * the data are not inlined. Should be aligned in WQEBB 75 * boundary with accounting the title Control and Ethernet 76 * segments. 77 */ 78 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \ 79 MLX5_DSEG_MIN_INLINE_SIZE) 80 /* 81 * Maximal inline data length sent with enhanced MPW. 82 * Is based on maximal WQE size. 83 */ 84 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 85 MLX5_WQE_CSEG_SIZE - \ 86 MLX5_WQE_ESEG_SIZE - \ 87 MLX5_WQE_DSEG_SIZE + \ 88 MLX5_DSEG_MIN_INLINE_SIZE) 89 /* 90 * Minimal amount of packets to be sent with EMPW. 91 * This limits the minimal required size of sent EMPW. 92 * If there are no enough resources to built minimal 93 * EMPW the sending loop exits. 94 */ 95 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u) 96 /* 97 * Maximal amount of packets to be sent with EMPW. 98 * This value is not recommended to exceed MLX5_TX_COMP_THRESH, 99 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs 100 * without CQE generation request, being multiplied by 101 * MLX5_TX_COMP_MAX_CQE it may cause significant latency 102 * in tx burst routine at the moment of freeing multiple mbufs. 103 */ 104 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH 105 #define MLX5_MPW_MAX_PACKETS 6 106 #define MLX5_MPW_INLINE_MAX_PACKETS 6 107 108 /* 109 * Default packet length threshold to be inlined with 110 * ordinary SEND. Inlining saves the MR key search 111 * and extra PCIe data fetch transaction, but eats the 112 * CPU cycles. 113 */ 114 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \ 115 MLX5_ESEG_MIN_INLINE_SIZE - \ 116 MLX5_WQE_CSEG_SIZE - \ 117 MLX5_WQE_ESEG_SIZE - \ 118 MLX5_WQE_DSEG_SIZE) 119 /* 120 * Maximal inline data length sent with ordinary SEND. 121 * Is based on maximal WQE size. 122 */ 123 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 124 MLX5_WQE_CSEG_SIZE - \ 125 MLX5_WQE_ESEG_SIZE - \ 126 MLX5_WQE_DSEG_SIZE + \ 127 MLX5_ESEG_MIN_INLINE_SIZE) 128 129 /* Missed in mlx5dv.h, should define here. */ 130 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW 131 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u 132 #endif 133 134 #ifndef HAVE_MLX5_OPCODE_SEND_EN 135 #define MLX5_OPCODE_SEND_EN 0x17u 136 #endif 137 138 #ifndef HAVE_MLX5_OPCODE_WAIT 139 #define MLX5_OPCODE_WAIT 0x0fu 140 #endif 141 142 #define MLX5_OPC_MOD_WAIT_CQ_PI 0u 143 #define MLX5_OPC_MOD_WAIT_DATA 1u 144 #define MLX5_OPC_MOD_WAIT_TIME 2u 145 146 147 #define MLX5_WAIT_COND_INVERT 0x10u 148 #define MLX5_WAIT_COND_ALWAYS_TRUE 0u 149 #define MLX5_WAIT_COND_EQUAL 1u 150 #define MLX5_WAIT_COND_BIGGER 2u 151 #define MLX5_WAIT_COND_SMALLER 3u 152 #define MLX5_WAIT_COND_CYCLIC_BIGGER 4u 153 #define MLX5_WAIT_COND_CYCLIC_SMALLER 5u 154 155 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO 156 #define MLX5_OPCODE_ACCESS_ASO 0x2du 157 #endif 158 159 /* CQE value to inform that VLAN is stripped. */ 160 #define MLX5_CQE_VLAN_STRIPPED (1u << 0) 161 162 /* IPv4 options. */ 163 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1) 164 165 /* IPv6 packet. */ 166 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2) 167 168 /* IPv4 packet. */ 169 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3) 170 171 /* TCP packet. */ 172 #define MLX5_CQE_RX_TCP_PACKET (1u << 4) 173 174 /* UDP packet. */ 175 #define MLX5_CQE_RX_UDP_PACKET (1u << 5) 176 177 /* IP is fragmented. */ 178 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7) 179 180 /* L2 header is valid. */ 181 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8) 182 183 /* L3 header is valid. */ 184 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9) 185 186 /* L4 header is valid. */ 187 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10) 188 189 /* Outer packet, 0 IPv4, 1 IPv6. */ 190 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1) 191 192 /* Tunnel packet bit in the CQE. */ 193 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0) 194 195 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */ 196 #define MLX5_CQE_LRO_PUSH_MASK 0x40 197 198 /* Mask for L4 type in the CQE hdr_type_etc field. */ 199 #define MLX5_CQE_L4_TYPE_MASK 0x70 200 201 /* The bit index of L4 type in CQE hdr_type_etc field. */ 202 #define MLX5_CQE_L4_TYPE_SHIFT 0x4 203 204 /* L4 type to indicate TCP packet without acknowledgment. */ 205 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3 206 207 /* L4 type to indicate TCP packet with acknowledgment. */ 208 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4 209 210 /* Inner L3 checksum offload (Tunneled packets only). */ 211 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4) 212 213 /* Inner L4 checksum offload (Tunneled packets only). */ 214 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5) 215 216 /* Outer L4 type is TCP. */ 217 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5) 218 219 /* Outer L4 type is UDP. */ 220 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5) 221 222 /* Outer L3 type is IPV4. */ 223 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4) 224 225 /* Outer L3 type is IPV6. */ 226 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4) 227 228 /* Inner L4 type is TCP. */ 229 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1) 230 231 /* Inner L4 type is UDP. */ 232 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1) 233 234 /* Inner L3 type is IPV4. */ 235 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0) 236 237 /* Inner L3 type is IPV6. */ 238 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0) 239 240 /* VLAN insertion flag. */ 241 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31) 242 243 /* Data inline segment flag. */ 244 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31) 245 246 /* Is flow mark valid. */ 247 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 248 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00) 249 #else 250 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff) 251 #endif 252 253 /* INVALID is used by packets matching no flow rules. */ 254 #define MLX5_FLOW_MARK_INVALID 0 255 256 /* Maximum allowed value to mark a packet. */ 257 #define MLX5_FLOW_MARK_MAX 0xfffff0 258 259 /* Default mark value used when none is provided. */ 260 #define MLX5_FLOW_MARK_DEFAULT 0xffffff 261 262 /* Default mark mask for metadata legacy mode. */ 263 #define MLX5_FLOW_MARK_MASK 0xffffff 264 265 /* Byte length mask when mark is enable in miniCQE */ 266 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00 267 268 /* Maximum number of DS in WQE. Limited by 6-bit field. */ 269 #define MLX5_DSEG_MAX 63 270 271 /* The 32 bit syndrome offset in struct mlx5_err_cqe. */ 272 #define MLX5_ERROR_CQE_SYNDROME_OFFSET 52 273 274 /* The completion mode offset in the WQE control segment line 2. */ 275 #define MLX5_COMP_MODE_OFFSET 2 276 277 /* Amount of data bytes in minimal inline data segment. */ 278 #define MLX5_DSEG_MIN_INLINE_SIZE 12u 279 280 /* Amount of data bytes in minimal inline eth segment. */ 281 #define MLX5_ESEG_MIN_INLINE_SIZE 18u 282 283 /* Amount of data bytes after eth data segment. */ 284 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u 285 286 /* The maximum log value of segments per RQ WQE. */ 287 #define MLX5_MAX_LOG_RQ_SEGS 5u 288 289 /* Log 2 of the default size of a WQE for Multi-Packet RQ. */ 290 #define MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE 14U 291 292 /* The alignment needed for WQ buffer. */ 293 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size() 294 295 /* The alignment needed for CQ buffer. */ 296 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size() 297 298 #define MAX_ACTIONS_DATA_IN_HEADER_MODIFY 512 299 300 /* Alias FT id passed to the ALLOW_OTHER_VHCA_ACCESS & CREATE_GENERAL_OBJECT 301 * commands should have the following format: 302 * {table_type: 8bits, table_id: 24bits}. 303 */ 304 #define FT_ID_FT_TYPE_OFFSET 24 305 306 /* Completion mode. */ 307 enum mlx5_completion_mode { 308 MLX5_COMP_ONLY_ERR = 0x0, 309 MLX5_COMP_ONLY_FIRST_ERR = 0x1, 310 MLX5_COMP_ALWAYS = 0x2, 311 MLX5_COMP_CQE_AND_EQE = 0x3, 312 }; 313 314 /* MPW mode. */ 315 enum mlx5_mpw_mode { 316 MLX5_MPW_DISABLED, 317 MLX5_MPW, 318 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */ 319 }; 320 321 /* WQE Control segment. */ 322 struct mlx5_wqe_cseg { 323 uint32_t opcode; 324 uint32_t sq_ds; 325 uint32_t flags; 326 uint32_t misc; 327 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE); 328 329 /* 330 * WQE CSEG opcode field size is 32 bits, divided: 331 * Bits 31:24 OPC_MOD 332 * Bits 23:8 wqe_index 333 * Bits 7:0 OPCODE 334 */ 335 #define WQE_CSEG_OPC_MOD_OFFSET 24 336 #define WQE_CSEG_WQE_INDEX_OFFSET 8 337 338 /* Header of data segment. Minimal size Data Segment */ 339 struct mlx5_wqe_dseg { 340 uint32_t bcount; 341 union { 342 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE]; 343 struct { 344 uint32_t lkey; 345 uint64_t pbuf; 346 } __rte_packed; 347 }; 348 } __rte_packed; 349 350 /* Subset of struct WQE Ethernet Segment. */ 351 struct mlx5_wqe_eseg { 352 union { 353 struct { 354 uint32_t swp_offs; 355 uint8_t cs_flags; 356 uint8_t swp_flags; 357 uint16_t mss; 358 uint32_t metadata; 359 uint16_t inline_hdr_sz; 360 union { 361 uint16_t inline_data; 362 uint16_t vlan_tag; 363 }; 364 } __rte_packed; 365 struct { 366 uint32_t offsets; 367 uint32_t flags; 368 uint32_t flow_metadata; 369 uint32_t inline_hdr; 370 } __rte_packed; 371 }; 372 } __rte_packed; 373 374 struct mlx5_wqe_qseg { 375 uint32_t reserved0; 376 uint32_t reserved1; 377 uint32_t max_index; 378 uint32_t qpn_cqn; 379 } __rte_packed; 380 381 struct mlx5_wqe_wseg { 382 uint32_t operation; 383 uint32_t lkey; 384 uint32_t va_high; 385 uint32_t va_low; 386 uint64_t value; 387 uint64_t mask; 388 } __rte_packed; 389 390 /* The title WQEBB, header of WQE. */ 391 struct mlx5_wqe { 392 union { 393 struct mlx5_wqe_cseg cseg; 394 uint32_t ctrl[4]; 395 }; 396 struct mlx5_wqe_eseg eseg; 397 union { 398 struct mlx5_wqe_dseg dseg[2]; 399 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE]; 400 }; 401 } __rte_packed; 402 403 /* WQE for Multi-Packet RQ. */ 404 struct mlx5_wqe_mprq { 405 struct mlx5_wqe_srq_next_seg next_seg; 406 struct mlx5_wqe_data_seg dseg; 407 }; 408 409 #define MLX5_MPRQ_LEN_MASK 0x000ffff 410 #define MLX5_MPRQ_LEN_SHIFT 0 411 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000 412 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16 413 #define MLX5_MPRQ_FILLER_MASK 0x80000000 414 #define MLX5_MPRQ_FILLER_SHIFT 31 415 416 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2 417 418 /* CQ element structure - should be equal to the cache line size */ 419 struct mlx5_cqe { 420 #if (RTE_CACHE_LINE_SIZE == 128) 421 uint8_t padding[64]; 422 #endif 423 uint8_t pkt_info; 424 uint8_t rsvd0; 425 uint16_t wqe_id; 426 uint8_t lro_tcppsh_abort_dupack; 427 uint8_t lro_min_ttl; 428 uint16_t lro_tcp_win; 429 uint32_t lro_ack_seq_num; 430 uint32_t rx_hash_res; 431 uint8_t rx_hash_type; 432 uint8_t rsvd1[3]; 433 uint16_t csum; 434 uint8_t rsvd2[6]; 435 uint16_t hdr_type_etc; 436 uint16_t vlan_info; 437 uint8_t lro_num_seg; 438 union { 439 uint8_t user_index_bytes[3]; 440 struct { 441 uint8_t user_index_hi; 442 uint16_t user_index_low; 443 } __rte_packed; 444 }; 445 uint32_t flow_table_metadata; 446 uint8_t rsvd4[4]; 447 uint32_t byte_cnt; 448 uint64_t timestamp; 449 uint32_t sop_drop_qpn; 450 uint16_t wqe_counter; 451 uint8_t validity_iteration_count; 452 uint8_t op_own; 453 }; 454 455 struct mlx5_cqe_ts { 456 uint64_t timestamp; 457 uint32_t sop_drop_qpn; 458 uint16_t wqe_counter; 459 uint8_t validity_iteration_count; 460 uint8_t op_own; 461 }; 462 463 struct mlx5_wqe_rseg { 464 uint64_t raddr; 465 uint32_t rkey; 466 uint32_t reserved; 467 } __rte_packed; 468 469 #define MLX5_UMRC_IF_OFFSET 31u 470 #define MLX5_UMRC_KO_OFFSET 16u 471 #define MLX5_UMRC_TO_BS_OFFSET 0u 472 473 /* 474 * As PRM describes, the address of the UMR pointer must be 475 * aligned to 2KB. 476 */ 477 #define MLX5_UMR_KLM_PTR_ALIGN (1 << 11) 478 479 #define MLX5_UMR_KLM_NUM_ALIGN \ 480 (MLX5_UMR_KLM_PTR_ALIGN / sizeof(struct mlx5_klm)) 481 482 struct mlx5_wqe_umr_cseg { 483 uint32_t if_cf_toe_cq_res; 484 uint32_t ko_to_bs; 485 uint64_t mkey_mask; 486 uint32_t rsvd1[8]; 487 } __rte_packed; 488 489 struct mlx5_wqe_mkey_cseg { 490 uint32_t fr_res_af_sf; 491 uint32_t qpn_mkey; 492 uint32_t reserved2; 493 uint32_t flags_pd; 494 uint64_t start_addr; 495 uint64_t len; 496 uint32_t bsf_octword_size; 497 uint32_t reserved3[4]; 498 uint32_t translations_octword_size; 499 uint32_t res4_lps; 500 uint32_t reserved; 501 } __rte_packed; 502 503 enum { 504 MLX5_BSF_SIZE_16B = 0x0, 505 MLX5_BSF_SIZE_32B = 0x1, 506 MLX5_BSF_SIZE_64B = 0x2, 507 MLX5_BSF_SIZE_128B = 0x3, 508 }; 509 510 enum { 511 MLX5_BSF_P_TYPE_SIGNATURE = 0x0, 512 MLX5_BSF_P_TYPE_CRYPTO = 0x1, 513 }; 514 515 enum { 516 MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, 517 MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, 518 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, 519 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, 520 }; 521 522 enum { 523 MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, 524 }; 525 526 enum { 527 MLX5_BLOCK_SIZE_512B = 0x1, 528 MLX5_BLOCK_SIZE_520B = 0x2, 529 MLX5_BLOCK_SIZE_4096B = 0x3, 530 MLX5_BLOCK_SIZE_4160B = 0x4, 531 MLX5_BLOCK_SIZE_1MB = 0x5, 532 MLX5_BLOCK_SIZE_4048B = 0x6, 533 }; 534 535 enum { 536 MLX5_ENCRYPTION_TYPE_AES_GCM = 0x3, 537 }; 538 539 enum { 540 MLX5_CRYPTO_OP_TYPE_ENCRYPTION = 0x0, 541 MLX5_CRYPTO_OP_TYPE_DECRYPTION = 0x1, 542 }; 543 544 #define MLX5_BSF_SIZE_OFFSET 30 545 #define MLX5_BSF_P_TYPE_OFFSET 24 546 #define MLX5_ENCRYPTION_ORDER_OFFSET 16 547 #define MLX5_BLOCK_SIZE_OFFSET 24 548 549 #define MLX5_CRYPTO_MMO_TYPE_OFFSET 24 550 #define MLX5_CRYPTO_MMO_OP_OFFSET 20 551 552 struct mlx5_wqe_umr_bsf_seg { 553 /* 554 * bs_bpt_eo_es contains: 555 * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET 556 * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET 557 * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET 558 * es encryption_standard 4 bits at offset 0 559 */ 560 uint32_t bs_bpt_eo_es; 561 uint32_t raw_data_size; 562 /* 563 * bsp_res contains: 564 * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET 565 * res reserved 24 bits 566 */ 567 uint32_t bsp_res; 568 uint32_t reserved0; 569 uint8_t xts_initial_tweak[16]; 570 /* 571 * res_dp contains: 572 * res reserved 8 bits 573 * dp dek_pointer 24 bits at offset 0 574 */ 575 uint32_t res_dp; 576 uint32_t reserved1; 577 uint64_t keytag; 578 uint32_t reserved2[4]; 579 } __rte_packed; 580 581 #ifdef PEDANTIC 582 #pragma GCC diagnostic ignored "-Wpedantic" 583 #endif 584 585 struct mlx5_umr_wqe { 586 struct mlx5_wqe_cseg ctr; 587 struct mlx5_wqe_umr_cseg ucseg; 588 struct mlx5_wqe_mkey_cseg mkc; 589 union { 590 struct mlx5_wqe_dseg kseg[0]; 591 struct mlx5_wqe_umr_bsf_seg bsf[0]; 592 }; 593 } __rte_packed; 594 595 struct mlx5_rdma_write_wqe { 596 struct mlx5_wqe_cseg ctr; 597 struct mlx5_wqe_rseg rseg; 598 struct mlx5_wqe_dseg dseg[]; 599 } __rte_packed; 600 601 struct mlx5_wqe_send_en_seg { 602 uint32_t reserve[2]; 603 uint32_t sqnpc; 604 uint32_t qpn; 605 } __rte_packed; 606 607 struct mlx5_wqe_send_en_wqe { 608 struct mlx5_wqe_cseg ctr; 609 struct mlx5_wqe_send_en_seg sseg; 610 } __rte_packed; 611 612 #ifdef PEDANTIC 613 #pragma GCC diagnostic error "-Wpedantic" 614 #endif 615 616 /* GGA */ 617 /* MMO metadata segment */ 618 619 #define MLX5_OPCODE_MMO 0x2fu 620 #define MLX5_OPC_MOD_MMO_CRYPTO 0x6u 621 #define MLX5_OPC_MOD_MMO_REGEX 0x4u 622 #define MLX5_OPC_MOD_MMO_COMP 0x2u 623 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u 624 #define MLX5_OPC_MOD_MMO_DMA 0x1u 625 626 #define WQE_GGA_DECOMP_DEFLATE 0x0u 627 #define WQE_GGA_DECOMP_LZ4 0x2u 628 629 #define MLX5_GGA_DECOMP_LZ4_BLOCK_WITHOUT_CHECKSUM 0x1u 630 #define MLX5_GGA_DECOMP_LZ4_BLOCK_WITH_CHECKSUM 0x2u 631 632 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u 633 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u 634 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u 635 #define WQE_GGA_DECOMP_PARAMS_OFFSET 20u 636 #define WQE_GGA_DECOMP_TYPE_OFFSET 8u 637 #define WQE_GGA_DECOMP_BLOCK_INDEPENDENT_OFFSET 22u 638 639 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u 640 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) 641 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u 642 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u 643 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u 644 #define MLX5_GGA_COMP_OUT_OF_SPACE_SYNDROME_BE 0x29D0084 645 #define MLX5_GGA_COMP_MISSING_BFINAL_SYNDROME_BE 0x29D0011 646 647 struct mlx5_wqe_metadata_seg { 648 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */ 649 uint32_t lkey; 650 uint64_t addr; 651 }; 652 653 struct mlx5_gga_wqe { 654 uint32_t opcode; 655 uint32_t sq_ds; 656 uint32_t flags; 657 uint32_t gga_ctrl1; 658 uint32_t gga_ctrl2; 659 uint32_t opaque_lkey; 660 uint64_t opaque_vaddr; 661 struct mlx5_wqe_dseg gather; 662 struct mlx5_wqe_dseg scatter; 663 } __rte_packed; 664 665 union mlx5_gga_compress_opaque { 666 struct { 667 uint32_t syndrome; 668 uint32_t reserved0; 669 uint32_t scattered_length; 670 union { 671 struct { 672 uint32_t reserved1[5]; 673 uint32_t crc32; 674 uint32_t adler32; 675 } v1 __rte_packed; 676 struct { 677 uint32_t crc32; 678 uint32_t adler32; 679 uint32_t crc32c; 680 uint32_t xxh32; 681 } v2 __rte_packed; 682 }; 683 } __rte_packed; 684 uint32_t data[64]; 685 }; 686 687 union mlx5_gga_crypto_opaque { 688 struct { 689 uint32_t syndrome; 690 uint32_t reserved0[2]; 691 struct { 692 uint32_t iv[3]; 693 uint32_t tag_size; 694 uint32_t aad_size; 695 } cp __rte_packed; 696 } __rte_packed; 697 uint8_t data[64]; 698 }; 699 700 struct mlx5_ifc_regexp_mmo_control_bits { 701 uint8_t reserved_at_31[0x2]; 702 uint8_t le[0x1]; 703 uint8_t reserved_at_28[0x1]; 704 uint8_t subset_id_0[0xc]; 705 uint8_t reserved_at_16[0x4]; 706 uint8_t subset_id_1[0xc]; 707 uint8_t ctrl[0x4]; 708 uint8_t subset_id_2[0xc]; 709 uint8_t reserved_at_16_1[0x4]; 710 uint8_t subset_id_3[0xc]; 711 }; 712 713 struct mlx5_ifc_regexp_metadata_bits { 714 uint8_t rof_version[0x10]; 715 uint8_t latency_count[0x10]; 716 uint8_t instruction_count[0x10]; 717 uint8_t primary_thread_count[0x10]; 718 uint8_t match_count[0x8]; 719 uint8_t detected_match_count[0x8]; 720 uint8_t status[0x10]; 721 uint8_t job_id[0x20]; 722 uint8_t reserved[0x80]; 723 }; 724 725 struct mlx5_ifc_regexp_match_tuple_bits { 726 uint8_t length[0x10]; 727 uint8_t start_ptr[0x10]; 728 uint8_t rule_id[0x20]; 729 }; 730 731 /* Adding direct verbs to data-path. */ 732 733 /* CQ sequence number mask. */ 734 #define MLX5_CQ_SQN_MASK 0x3 735 736 /* CQ sequence number index. */ 737 #define MLX5_CQ_SQN_OFFSET 28 738 739 /* CQ doorbell index mask. */ 740 #define MLX5_CI_MASK 0xffffff 741 742 /* CQ doorbell offset. */ 743 #define MLX5_CQ_ARM_DB 1 744 745 /* CQ doorbell offset*/ 746 #define MLX5_CQ_DOORBELL 0x20 747 748 /* CQE format value. */ 749 #define MLX5_COMPRESSED 0x3 750 751 /* CQ doorbell cmd types. */ 752 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24) 753 #define MLX5_CQ_DBR_CMD_ALL (0 << 24) 754 755 /* Action type of header modification. */ 756 enum { 757 MLX5_MODIFICATION_TYPE_SET = 0x1, 758 MLX5_MODIFICATION_TYPE_ADD = 0x2, 759 MLX5_MODIFICATION_TYPE_COPY = 0x3, 760 MLX5_MODIFICATION_TYPE_INSERT = 0x4, 761 MLX5_MODIFICATION_TYPE_REMOVE = 0x5, 762 MLX5_MODIFICATION_TYPE_NOP = 0x6, 763 MLX5_MODIFICATION_TYPE_REMOVE_WORDS = 0x7, 764 MLX5_MODIFICATION_TYPE_ADD_FIELD = 0x8, 765 MLX5_MODIFICATION_TYPE_MAX, 766 }; 767 768 /* The field of packet to be modified. */ 769 enum mlx5_modification_field { 770 MLX5_MODI_OUT_NONE = -1, 771 MLX5_MODI_OUT_SMAC_47_16 = 1, 772 MLX5_MODI_OUT_SMAC_15_0, 773 MLX5_MODI_OUT_ETHERTYPE, 774 MLX5_MODI_OUT_DMAC_47_16, 775 MLX5_MODI_OUT_DMAC_15_0, 776 MLX5_MODI_OUT_IP_DSCP, 777 MLX5_MODI_OUT_TCP_FLAGS, 778 MLX5_MODI_OUT_TCP_SPORT, 779 MLX5_MODI_OUT_TCP_DPORT, 780 MLX5_MODI_OUT_IPV4_TTL, 781 MLX5_MODI_OUT_UDP_SPORT, 782 MLX5_MODI_OUT_UDP_DPORT, 783 MLX5_MODI_OUT_SIPV6_127_96, 784 MLX5_MODI_OUT_SIPV6_95_64, 785 MLX5_MODI_OUT_SIPV6_63_32, 786 MLX5_MODI_OUT_SIPV6_31_0, 787 MLX5_MODI_OUT_DIPV6_127_96, 788 MLX5_MODI_OUT_DIPV6_95_64, 789 MLX5_MODI_OUT_DIPV6_63_32, 790 MLX5_MODI_OUT_DIPV6_31_0, 791 MLX5_MODI_OUT_SIPV4, 792 MLX5_MODI_OUT_DIPV4, 793 MLX5_MODI_OUT_FIRST_VID, 794 MLX5_MODI_IN_SMAC_47_16 = 0x31, 795 MLX5_MODI_IN_SMAC_15_0, 796 MLX5_MODI_IN_ETHERTYPE, 797 MLX5_MODI_IN_DMAC_47_16, 798 MLX5_MODI_IN_DMAC_15_0, 799 MLX5_MODI_IN_IP_DSCP, 800 MLX5_MODI_IN_TCP_FLAGS, 801 MLX5_MODI_IN_TCP_SPORT, 802 MLX5_MODI_IN_TCP_DPORT, 803 MLX5_MODI_IN_IPV4_TTL, 804 MLX5_MODI_IN_UDP_SPORT, 805 MLX5_MODI_IN_UDP_DPORT, 806 MLX5_MODI_IN_SIPV6_127_96, 807 MLX5_MODI_IN_SIPV6_95_64, 808 MLX5_MODI_IN_SIPV6_63_32, 809 MLX5_MODI_IN_SIPV6_31_0, 810 MLX5_MODI_IN_DIPV6_127_96, 811 MLX5_MODI_IN_DIPV6_95_64, 812 MLX5_MODI_IN_DIPV6_63_32, 813 MLX5_MODI_IN_DIPV6_31_0, 814 MLX5_MODI_IN_SIPV4, 815 MLX5_MODI_IN_DIPV4, 816 MLX5_MODI_OUT_IPV6_HOPLIMIT, 817 MLX5_MODI_IN_IPV6_HOPLIMIT, 818 MLX5_MODI_META_DATA_REG_A, 819 MLX5_MODI_META_DATA_REG_B = 0x50, 820 MLX5_MODI_META_REG_C_0, 821 MLX5_MODI_META_REG_C_1, 822 MLX5_MODI_META_REG_C_2, 823 MLX5_MODI_META_REG_C_3, 824 MLX5_MODI_META_REG_C_4, 825 MLX5_MODI_META_REG_C_5, 826 MLX5_MODI_META_REG_C_6, 827 MLX5_MODI_META_REG_C_7, 828 MLX5_MODI_OUT_TCP_SEQ_NUM, 829 MLX5_MODI_IN_TCP_SEQ_NUM, 830 MLX5_MODI_OUT_TCP_ACK_NUM, 831 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C, 832 MLX5_MODI_GTP_TEID = 0x6E, 833 MLX5_MODI_OUT_IP_ECN = 0x73, 834 MLX5_MODI_TUNNEL_HDR_DW_1 = 0x75, 835 MLX5_MODI_GTPU_FIRST_EXT_DW_0 = 0x76, 836 MLX5_MODI_HASH_RESULT = 0x81, 837 MLX5_MODI_IN_MPLS_LABEL_0 = 0x8a, 838 MLX5_MODI_IN_MPLS_LABEL_1, 839 MLX5_MODI_IN_MPLS_LABEL_2, 840 MLX5_MODI_IN_MPLS_LABEL_3, 841 MLX5_MODI_IN_MPLS_LABEL_4, 842 MLX5_MODI_OUT_IP_PROTOCOL = 0x4A, 843 MLX5_MODI_OUT_IPV6_NEXT_HDR = 0x4A, 844 MLX5_MODI_META_REG_C_8 = 0x8F, 845 MLX5_MODI_META_REG_C_9 = 0x90, 846 MLX5_MODI_META_REG_C_10 = 0x91, 847 MLX5_MODI_META_REG_C_11 = 0x92, 848 MLX5_MODI_META_REG_C_12 = 0x93, 849 MLX5_MODI_META_REG_C_13 = 0x94, 850 MLX5_MODI_META_REG_C_14 = 0x95, 851 MLX5_MODI_META_REG_C_15 = 0x96, 852 MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS = 0x11C, 853 MLX5_MODI_OUT_IPV4_TOTAL_LEN = 0x11D, 854 MLX5_MODI_OUT_IPV6_PAYLOAD_LEN = 0x11E, 855 MLX5_MODI_OUT_IPV4_IHL = 0x11F, 856 MLX5_MODI_OUT_TCP_DATA_OFFSET = 0x120, 857 MLX5_MODI_OUT_ESP_SPI = 0x5E, 858 MLX5_MODI_OUT_ESP_SEQ_NUM = 0x82, 859 MLX5_MODI_OUT_IPSEC_NEXT_HDR = 0x126, 860 MLX5_MODI_INVALID = INT_MAX, 861 }; 862 863 /* Total number of metadata reg_c's. */ 864 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1) 865 866 enum modify_reg { 867 REG_NON = 0, 868 REG_A, 869 REG_B, 870 REG_C_0, 871 REG_C_1, 872 REG_C_2, 873 REG_C_3, 874 REG_C_4, 875 REG_C_5, 876 REG_C_6, 877 REG_C_7, 878 REG_C_8, 879 REG_C_9, 880 REG_C_10, 881 REG_C_11, 882 }; 883 884 static __rte_always_inline uint8_t 885 mlx5_regc_index(enum modify_reg regc_val) 886 { 887 return (uint8_t)(regc_val - REG_C_0); 888 } 889 890 static __rte_always_inline enum modify_reg 891 mlx5_regc_value(uint8_t regc_ix) 892 { 893 return REG_C_0 + regc_ix; 894 } 895 896 /* Modification sub command. */ 897 struct mlx5_modification_cmd { 898 union { 899 uint32_t data0; 900 struct { 901 unsigned int length:5; 902 unsigned int rsvd0:3; 903 unsigned int offset:5; 904 unsigned int rsvd1:3; 905 unsigned int field:12; 906 unsigned int action_type:4; 907 }; 908 }; 909 union { 910 uint32_t data1; 911 uint8_t data[4]; 912 struct { 913 unsigned int rsvd2:8; 914 unsigned int dst_offset:5; 915 unsigned int rsvd3:3; 916 unsigned int dst_field:12; 917 unsigned int rsvd4:4; 918 }; 919 }; 920 }; 921 922 typedef uint64_t u64; 923 typedef uint32_t u32; 924 typedef uint16_t u16; 925 typedef uint8_t u8; 926 927 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 928 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 929 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \ 930 (&(__mlx5_nullp(typ)->fld))) 931 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \ 932 (__mlx5_bit_off(typ, fld) & 0x1f)) 933 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 934 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 935 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \ 936 __mlx5_dw_bit_off(typ, fld)) 937 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 938 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 939 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \ 940 (__mlx5_bit_off(typ, fld) & 0xf)) 941 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 942 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \ 943 __mlx5_16_bit_off(typ, fld)) 944 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 945 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 946 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 947 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 948 949 /* insert a value to a struct */ 950 #define MLX5_SET(typ, p, fld, v) \ 951 do { \ 952 u32 _v = v; \ 953 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \ 954 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \ 955 __mlx5_dw_off(typ, fld))) & \ 956 (~__mlx5_dw_mask(typ, fld))) | \ 957 (((_v) & __mlx5_mask(typ, fld)) << \ 958 __mlx5_dw_bit_off(typ, fld))); \ 959 } while (0) 960 961 #define MLX5_SET64(typ, p, fld, v) \ 962 do { \ 963 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \ 964 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \ 965 rte_cpu_to_be_64(v); \ 966 } while (0) 967 968 #define MLX5_SET16(typ, p, fld, v) \ 969 do { \ 970 u16 _v = v; \ 971 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \ 972 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 973 __mlx5_16_off(typ, fld))) & \ 974 (~__mlx5_16_mask(typ, fld))) | \ 975 (((_v) & __mlx5_mask16(typ, fld)) << \ 976 __mlx5_16_bit_off(typ, fld))); \ 977 } while (0) 978 979 #define MLX5_GET_VOLATILE(typ, p, fld) \ 980 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\ 981 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 982 __mlx5_mask(typ, fld)) 983 #define MLX5_GET(typ, p, fld) \ 984 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\ 985 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 986 __mlx5_mask(typ, fld)) 987 #define MLX5_GET16(typ, p, fld) \ 988 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 989 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 990 __mlx5_mask16(typ, fld)) 991 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \ 992 __mlx5_64_off(typ, fld))) 993 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 994 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 995 996 struct mlx5_ifc_fte_match_set_misc_bits { 997 u8 gre_c_present[0x1]; 998 u8 reserved_at_1[0x1]; 999 u8 gre_k_present[0x1]; 1000 u8 gre_s_present[0x1]; 1001 u8 source_vhci_port[0x4]; 1002 u8 source_sqn[0x18]; 1003 u8 reserved_at_20[0x10]; 1004 u8 source_port[0x10]; 1005 u8 outer_second_prio[0x3]; 1006 u8 outer_second_cfi[0x1]; 1007 u8 outer_second_vid[0xc]; 1008 u8 inner_second_prio[0x3]; 1009 u8 inner_second_cfi[0x1]; 1010 u8 inner_second_vid[0xc]; 1011 u8 outer_second_cvlan_tag[0x1]; 1012 u8 inner_second_cvlan_tag[0x1]; 1013 u8 outer_second_svlan_tag[0x1]; 1014 u8 inner_second_svlan_tag[0x1]; 1015 u8 reserved_at_64[0xc]; 1016 u8 gre_protocol[0x10]; 1017 u8 gre_key_h[0x18]; 1018 u8 gre_key_l[0x8]; 1019 u8 vxlan_vni[0x18]; 1020 u8 bth_opcode[0x8]; 1021 u8 geneve_vni[0x18]; 1022 u8 lag_rx_port_affinity[0x4]; 1023 u8 reserved_at_e8[0x2]; 1024 u8 geneve_tlv_option_0_exist[0x1]; 1025 u8 geneve_oam[0x1]; 1026 u8 reserved_at_e0[0xc]; 1027 u8 outer_ipv6_flow_label[0x14]; 1028 u8 reserved_at_100[0xc]; 1029 u8 inner_ipv6_flow_label[0x14]; 1030 u8 reserved_at_120[0xa]; 1031 u8 geneve_opt_len[0x6]; 1032 u8 geneve_protocol_type[0x10]; 1033 u8 reserved_at_140[0x8]; 1034 u8 bth_dst_qp[0x18]; 1035 u8 inner_esp_spi[0x20]; 1036 u8 outer_esp_spi[0x20]; 1037 u8 reserved_at_1a0[0x60]; 1038 }; 1039 1040 struct mlx5_ifc_ipv4_layout_bits { 1041 u8 reserved_at_0[0x60]; 1042 u8 ipv4[0x20]; 1043 }; 1044 1045 struct mlx5_ifc_ipv6_layout_bits { 1046 u8 ipv6[16][0x8]; 1047 }; 1048 1049 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 1050 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 1051 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 1052 u8 reserved_at_0[0x80]; 1053 }; 1054 1055 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 1056 u8 smac_47_16[0x20]; 1057 u8 smac_15_0[0x10]; 1058 u8 ethertype[0x10]; 1059 u8 dmac_47_16[0x20]; 1060 u8 dmac_15_0[0x10]; 1061 u8 first_prio[0x3]; 1062 u8 first_cfi[0x1]; 1063 u8 first_vid[0xc]; 1064 u8 ip_protocol[0x8]; 1065 u8 ip_dscp[0x6]; 1066 u8 ip_ecn[0x2]; 1067 u8 cvlan_tag[0x1]; 1068 u8 svlan_tag[0x1]; 1069 u8 frag[0x1]; 1070 u8 ip_version[0x4]; 1071 u8 tcp_flags[0x9]; 1072 u8 tcp_sport[0x10]; 1073 u8 tcp_dport[0x10]; 1074 u8 reserved_at_c0[0x10]; 1075 u8 ipv4_ihl[0x4]; 1076 u8 l3_ok[0x1]; 1077 u8 l4_ok[0x1]; 1078 u8 ipv4_checksum_ok[0x1]; 1079 u8 l4_checksum_ok[0x1]; 1080 u8 ip_ttl_hoplimit[0x8]; 1081 u8 udp_sport[0x10]; 1082 u8 udp_dport[0x10]; 1083 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 1084 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 1085 }; 1086 1087 struct mlx5_ifc_fte_match_mpls_bits { 1088 u8 mpls_label[0x14]; 1089 u8 mpls_exp[0x3]; 1090 u8 mpls_s_bos[0x1]; 1091 u8 mpls_ttl[0x8]; 1092 }; 1093 1094 struct mlx5_ifc_fte_match_set_misc2_bits { 1095 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 1096 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 1097 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 1098 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 1099 u8 metadata_reg_c_7[0x20]; 1100 u8 metadata_reg_c_6[0x20]; 1101 u8 metadata_reg_c_5[0x20]; 1102 u8 metadata_reg_c_4[0x20]; 1103 u8 metadata_reg_c_3[0x20]; 1104 u8 metadata_reg_c_2[0x20]; 1105 u8 metadata_reg_c_1[0x20]; 1106 u8 metadata_reg_c_0[0x20]; 1107 u8 metadata_reg_a[0x20]; 1108 u8 metadata_reg_b[0x20]; 1109 u8 reserved_at_1c0[0x40]; 1110 }; 1111 1112 struct mlx5_ifc_fte_match_set_misc3_bits { 1113 u8 inner_tcp_seq_num[0x20]; 1114 u8 outer_tcp_seq_num[0x20]; 1115 u8 inner_tcp_ack_num[0x20]; 1116 u8 outer_tcp_ack_num[0x20]; 1117 u8 reserved_at_auto1[0x8]; 1118 u8 outer_vxlan_gpe_vni[0x18]; 1119 u8 outer_vxlan_gpe_next_protocol[0x8]; 1120 u8 outer_vxlan_gpe_flags[0x8]; 1121 u8 reserved_at_a8[0x10]; 1122 u8 icmp_header_data[0x20]; 1123 u8 icmpv6_header_data[0x20]; 1124 u8 icmp_type[0x8]; 1125 u8 icmp_code[0x8]; 1126 u8 icmpv6_type[0x8]; 1127 u8 icmpv6_code[0x8]; 1128 u8 geneve_tlv_option_0_data[0x20]; 1129 u8 gtpu_teid[0x20]; 1130 u8 gtpu_msg_type[0x08]; 1131 u8 gtpu_msg_flags[0x08]; 1132 u8 reserved_at_170[0x10]; 1133 u8 gtpu_dw_2[0x20]; 1134 u8 gtpu_first_ext_dw_0[0x20]; 1135 u8 gtpu_dw_0[0x20]; 1136 u8 reserved_at_240[0x20]; 1137 1138 }; 1139 1140 struct mlx5_ifc_fte_match_set_misc4_bits { 1141 u8 prog_sample_field_value_0[0x20]; 1142 u8 prog_sample_field_id_0[0x20]; 1143 u8 prog_sample_field_value_1[0x20]; 1144 u8 prog_sample_field_id_1[0x20]; 1145 u8 prog_sample_field_value_2[0x20]; 1146 u8 prog_sample_field_id_2[0x20]; 1147 u8 prog_sample_field_value_3[0x20]; 1148 u8 prog_sample_field_id_3[0x20]; 1149 u8 prog_sample_field_value_4[0x20]; 1150 u8 prog_sample_field_id_4[0x20]; 1151 u8 prog_sample_field_value_5[0x20]; 1152 u8 prog_sample_field_id_5[0x20]; 1153 u8 prog_sample_field_value_6[0x20]; 1154 u8 prog_sample_field_id_6[0x20]; 1155 u8 prog_sample_field_value_7[0x20]; 1156 u8 prog_sample_field_id_7[0x20]; 1157 }; 1158 1159 struct mlx5_ifc_fte_match_set_misc5_bits { 1160 u8 macsec_tag_0[0x20]; 1161 u8 macsec_tag_1[0x20]; 1162 u8 macsec_tag_2[0x20]; 1163 u8 macsec_tag_3[0x20]; 1164 u8 tunnel_header_0[0x20]; 1165 u8 tunnel_header_1[0x20]; 1166 u8 tunnel_header_2[0x20]; 1167 u8 tunnel_header_3[0x20]; 1168 u8 reserved[0x100]; 1169 }; 1170 1171 /* Flow matcher. */ 1172 struct mlx5_ifc_fte_match_param_bits { 1173 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1174 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1175 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1176 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1177 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1178 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1179 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1180 /* 1181 * Add reserved bit to match the struct size with the size defined in PRM. 1182 * This extension is not required in Linux. 1183 */ 1184 #ifndef HAVE_INFINIBAND_VERBS_H 1185 u8 reserved_0[0x200]; 1186 #endif 1187 }; 1188 1189 struct mlx5_ifc_dest_format_struct_bits { 1190 u8 destination_type[0x8]; 1191 u8 destination_id[0x18]; 1192 u8 reserved_0[0x20]; 1193 }; 1194 1195 enum { 1196 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 1197 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT, 1198 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT, 1199 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT, 1200 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT, 1201 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT, 1202 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT, 1203 }; 1204 1205 enum { 1206 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 1207 MLX5_CMD_OP_CREATE_MKEY = 0x200, 1208 MLX5_CMD_OP_CREATE_CQ = 0x400, 1209 MLX5_CMD_OP_CREATE_QP = 0x500, 1210 MLX5_CMD_OP_RST2INIT_QP = 0x502, 1211 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 1212 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 1213 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 1214 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 1215 MLX5_CMD_OP_QP_2ERR = 0x507, 1216 MLX5_CMD_OP_QP_2RST = 0x50A, 1217 MLX5_CMD_OP_QUERY_QP = 0x50B, 1218 MLX5_CMD_OP_SQD2RTS_QP = 0x50C, 1219 MLX5_CMD_OP_INIT2INIT_QP = 0x50E, 1220 MLX5_CMD_OP_SUSPEND_QP = 0x50F, 1221 MLX5_CMD_OP_RESUME_QP = 0x510, 1222 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 1223 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 1224 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 1225 MLX5_CMD_OP_ALLOC_PD = 0x800, 1226 MLX5_CMD_OP_DEALLOC_PD = 0x801, 1227 MLX5_CMD_OP_ACCESS_REGISTER = 0x805, 1228 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 1229 MLX5_CMD_OP_QUERY_LAG = 0x842, 1230 MLX5_CMD_OP_CREATE_TIR = 0x900, 1231 MLX5_CMD_OP_MODIFY_TIR = 0x901, 1232 MLX5_CMD_OP_CREATE_SQ = 0X904, 1233 MLX5_CMD_OP_MODIFY_SQ = 0X905, 1234 MLX5_CMD_OP_CREATE_RQ = 0x908, 1235 MLX5_CMD_OP_MODIFY_RQ = 0x909, 1236 MLX5_CMD_OP_QUERY_RQ = 0x90b, 1237 MLX5_CMD_OP_CREATE_RMP = 0x90c, 1238 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 1239 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 1240 MLX5_CMD_OP_QUERY_RMP = 0x90f, 1241 MLX5_CMD_OP_CREATE_TIS = 0x912, 1242 MLX5_CMD_OP_QUERY_TIS = 0x915, 1243 MLX5_CMD_OP_CREATE_RQT = 0x916, 1244 MLX5_CMD_OP_MODIFY_RQT = 0x917, 1245 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 1246 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 1247 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 1248 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 1249 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 1250 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 1251 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 1252 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 1253 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 1254 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 1255 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 1256 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 1257 MLX5_CMD_SET_REGEX_PARAMS = 0xb04, 1258 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05, 1259 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06, 1260 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07, 1261 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c, 1262 MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO = 0xb13, 1263 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 1264 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 1265 }; 1266 1267 enum { 1268 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 1269 MLX5_MKC_ACCESS_MODE_KLM = 0x2, 1270 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3, 1271 }; 1272 1273 #define MLX5_ADAPTER_PAGE_SHIFT 12 1274 #define MLX5_LOG_RQ_STRIDE_SHIFT 4 1275 /** 1276 * The batch counter dcs id starts from 0x800000 and none batch counter 1277 * starts from 0. As currently, the counter is changed to be indexed by 1278 * pool index and the offset of the counter in the pool counters_raw array. 1279 * It means now the counter index is same for batch and none batch counter. 1280 * Add the 0x800000 batch counter offset to the batch counter index helps 1281 * indicate the counter index is from batch or none batch container pool. 1282 */ 1283 #define MLX5_CNT_BATCH_OFFSET 0x800000 1284 1285 /* The counter batch query requires ID align with 4. */ 1286 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4 1287 1288 /* Flow counters. */ 1289 struct mlx5_ifc_alloc_flow_counter_out_bits { 1290 u8 status[0x8]; 1291 u8 reserved_at_8[0x18]; 1292 u8 syndrome[0x20]; 1293 u8 flow_counter_id[0x20]; 1294 u8 reserved_at_60[0x20]; 1295 }; 1296 1297 struct mlx5_ifc_alloc_flow_counter_in_bits { 1298 u8 opcode[0x10]; 1299 u8 reserved_at_10[0x10]; 1300 u8 reserved_at_20[0x10]; 1301 u8 op_mod[0x10]; 1302 u8 reserved_at_40[0x8]; 1303 u8 pd[0x18]; 1304 u8 reserved_at_60[0x13]; 1305 u8 flow_counter_bulk_log_size[0x5]; 1306 u8 flow_counter_bulk[0x8]; 1307 }; 1308 1309 struct mlx5_ifc_dealloc_flow_counter_out_bits { 1310 u8 status[0x8]; 1311 u8 reserved_at_8[0x18]; 1312 u8 syndrome[0x20]; 1313 u8 reserved_at_40[0x40]; 1314 }; 1315 1316 struct mlx5_ifc_dealloc_flow_counter_in_bits { 1317 u8 opcode[0x10]; 1318 u8 reserved_at_10[0x10]; 1319 u8 reserved_at_20[0x10]; 1320 u8 op_mod[0x10]; 1321 u8 flow_counter_id[0x20]; 1322 u8 reserved_at_60[0x20]; 1323 }; 1324 1325 struct mlx5_ifc_traffic_counter_bits { 1326 u8 packets[0x40]; 1327 u8 octets[0x40]; 1328 }; 1329 1330 struct mlx5_ifc_query_flow_counter_out_bits { 1331 u8 status[0x8]; 1332 u8 reserved_at_8[0x18]; 1333 u8 syndrome[0x20]; 1334 u8 reserved_at_40[0x40]; 1335 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 1336 }; 1337 1338 struct mlx5_ifc_query_flow_counter_in_bits { 1339 u8 opcode[0x10]; 1340 u8 reserved_at_10[0x10]; 1341 u8 reserved_at_20[0x10]; 1342 u8 op_mod[0x10]; 1343 u8 reserved_at_40[0x20]; 1344 u8 mkey[0x20]; 1345 u8 address[0x40]; 1346 u8 clear[0x1]; 1347 u8 dump_to_memory[0x1]; 1348 u8 num_of_counters[0x1e]; 1349 u8 flow_counter_id[0x20]; 1350 }; 1351 1352 struct mlx5_ifc_query_match_sample_info_out_bits { 1353 u8 status[0x8]; 1354 u8 reserved_at_8[0x18]; 1355 u8 syndrome[0x20]; 1356 u8 reserved_at_40[0x40]; 1357 u8 reserved_at_80[0x4]; 1358 u8 modify_field_id[0xc]; 1359 u8 ok_bit_format_select_dw[0x8]; 1360 u8 field_format_select_dw[0x8]; 1361 u8 reserved_at_a0[0x3]; 1362 u8 ok_bit_offset[0x5]; 1363 u8 reserved_at_a8[0x18]; 1364 u8 reserved_at_c0[0x40]; 1365 }; 1366 1367 struct mlx5_ifc_query_match_sample_info_in_bits { 1368 u8 opcode[0x10]; 1369 u8 uid[0x10]; 1370 u8 reserved_at_20[0x10]; 1371 u8 op_mod[0x10]; 1372 u8 reserved_at_40[0x60]; 1373 u8 sample_field_id[0x20]; 1374 u8 reserved_at_c0[0x140]; 1375 }; 1376 1377 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u 1378 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u 1379 1380 struct mlx5_ifc_klm_bits { 1381 u8 byte_count[0x20]; 1382 u8 mkey[0x20]; 1383 u8 address[0x40]; 1384 }; 1385 1386 struct mlx5_ifc_mkc_bits { 1387 u8 reserved_at_0[0x1]; 1388 u8 free[0x1]; 1389 u8 reserved_at_2[0x1]; 1390 u8 access_mode_4_2[0x3]; 1391 u8 reserved_at_6[0x7]; 1392 u8 relaxed_ordering_write[0x1]; 1393 u8 reserved_at_e[0x1]; 1394 u8 small_fence_on_rdma_read_response[0x1]; 1395 u8 umr_en[0x1]; 1396 u8 a[0x1]; 1397 u8 rw[0x1]; 1398 u8 rr[0x1]; 1399 u8 lw[0x1]; 1400 u8 lr[0x1]; 1401 u8 access_mode_1_0[0x2]; 1402 u8 reserved_at_18[0x8]; 1403 u8 qpn[0x18]; 1404 u8 mkey_7_0[0x8]; 1405 u8 reserved_at_40[0x20]; 1406 u8 length64[0x1]; 1407 u8 bsf_en[0x1]; 1408 u8 sync_umr[0x1]; 1409 u8 reserved_at_63[0x2]; 1410 u8 expected_sigerr_count[0x1]; 1411 u8 reserved_at_66[0x1]; 1412 u8 en_rinval[0x1]; 1413 u8 pd[0x18]; 1414 u8 start_addr[0x40]; 1415 u8 len[0x40]; 1416 u8 bsf_octword_size[0x20]; 1417 u8 reserved_at_120[0x80]; 1418 u8 translations_octword_size[0x20]; 1419 u8 reserved_at_1c0[0x19]; 1420 u8 relaxed_ordering_read[0x1]; 1421 u8 reserved_at_1da[0x1]; 1422 u8 log_page_size[0x5]; 1423 u8 reserved_at_1e0[0x3]; 1424 u8 crypto_en[0x2]; 1425 u8 reserved_at_1e5[0x1b]; 1426 }; 1427 1428 /* Range of values for MKEY context crypto_en field. */ 1429 enum { 1430 MLX5_MKEY_CRYPTO_DISABLED = 0x0, 1431 MLX5_MKEY_CRYPTO_ENABLED = 0x1, 1432 }; 1433 1434 struct mlx5_ifc_create_mkey_out_bits { 1435 u8 status[0x8]; 1436 u8 reserved_at_8[0x18]; 1437 u8 syndrome[0x20]; 1438 u8 reserved_at_40[0x8]; 1439 u8 mkey_index[0x18]; 1440 u8 reserved_at_60[0x20]; 1441 }; 1442 1443 struct mlx5_ifc_create_mkey_in_bits { 1444 u8 opcode[0x10]; 1445 u8 reserved_at_10[0x10]; 1446 u8 reserved_at_20[0x10]; 1447 u8 op_mod[0x10]; 1448 u8 reserved_at_40[0x20]; 1449 u8 pg_access[0x1]; 1450 u8 reserved_at_61[0x1f]; 1451 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 1452 u8 reserved_at_280[0x80]; 1453 u8 translations_octword_actual_size[0x20]; 1454 u8 mkey_umem_id[0x20]; 1455 u8 mkey_umem_offset[0x40]; 1456 u8 reserved_at_380[0x500]; 1457 u8 klm_pas_mtt[][0x20]; 1458 }; 1459 1460 enum { 1461 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, 1462 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, 1463 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1, 1464 MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, 1465 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, 1466 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE = 0x8 << 1, 1467 MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1, 1468 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, 1469 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO = 0x1A << 1, 1470 MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE = 0x1B << 1, 1471 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1, 1472 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, 1473 }; 1474 1475 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \ 1476 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ) 1477 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \ 1478 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS) 1479 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \ 1480 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH) 1481 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \ 1482 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO) 1483 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \ 1484 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO) 1485 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ 1486 (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT) 1487 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \ 1488 (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD) 1489 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEFINER \ 1490 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEFINER) 1491 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \ 1492 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK) 1493 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \ 1494 (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK) 1495 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \ 1496 (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL) 1497 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \ 1498 (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN) 1499 1500 enum { 1501 MLX5_HCA_CAP_OPMOD_GET_MAX = 0, 1502 MLX5_HCA_CAP_OPMOD_GET_CUR = 1, 1503 }; 1504 1505 enum { 1506 MLX5_CAP_INLINE_MODE_L2, 1507 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT, 1508 MLX5_CAP_INLINE_MODE_NOT_REQUIRED, 1509 }; 1510 1511 enum { 1512 MLX5_INLINE_MODE_NONE, 1513 MLX5_INLINE_MODE_L2, 1514 MLX5_INLINE_MODE_IP, 1515 MLX5_INLINE_MODE_TCP_UDP, 1516 MLX5_INLINE_MODE_RESERVED4, 1517 MLX5_INLINE_MODE_INNER_L2, 1518 MLX5_INLINE_MODE_INNER_IP, 1519 MLX5_INLINE_MODE_INNER_TCP_UDP, 1520 }; 1521 1522 /* The supported timestamp formats reported in HCA attributes. */ 1523 enum { 1524 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0, 1525 MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1, 1526 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2, 1527 }; 1528 1529 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */ 1530 enum { 1531 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 1532 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 1533 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 1534 }; 1535 1536 /* HCA bit masks indicating which Flex parser protocols are already enabled. */ 1537 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0) 1538 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1) 1539 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2) 1540 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3) 1541 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4) 1542 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5) 1543 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6) 1544 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7) 1545 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8) 1546 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9) 1547 #define MLX5_HCA_FLEX_GTPU_ENABLED (1UL << 11) 1548 #define MLX5_HCA_FLEX_GTPU_DW_2_ENABLED (1UL << 16) 1549 #define MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED (1UL << 17) 1550 #define MLX5_HCA_FLEX_GTPU_DW_0_ENABLED (1UL << 18) 1551 #define MLX5_HCA_FLEX_GTPU_TEID_ENABLED (1UL << 19) 1552 1553 /* The device steering logic format. */ 1554 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0 1555 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1 1556 1557 struct mlx5_ifc_cmd_hca_cap_bits { 1558 u8 access_other_hca_roce[0x1]; 1559 u8 alloc_flow_counter_pd[0x1]; 1560 u8 flow_counter_access_aso[0x1]; 1561 u8 query_match_sample_info[0x1]; 1562 u8 reserved_at_4[0x4]; 1563 u8 flow_access_aso_opc_mod[0x8]; 1564 u8 reserved_at_10[0xf]; 1565 u8 vhca_resource_manager[0x1]; 1566 u8 hca_cap_2[0x1]; 1567 u8 reserved_at_21[0xf]; 1568 u8 vhca_id[0x10]; 1569 u8 reserved_at_40[0x20]; 1570 u8 reserved_at_60[0x3]; 1571 u8 log_regexp_scatter_gather_size[0x5]; 1572 u8 reserved_at_68[0x3]; 1573 u8 log_dma_mmo_size[0x5]; 1574 u8 reserved_at_70[0x3]; 1575 u8 log_compress_mmo_size[0x5]; 1576 u8 decompress_lz4_data_only_v2[0x1]; 1577 u8 decompress_lz4_no_checksum_v2[0x1]; 1578 u8 decompress_lz4_checksum_v2[0x1]; 1579 u8 log_decompress_mmo_size[0x5]; 1580 u8 log_max_srq_sz[0x8]; 1581 u8 log_max_qp_sz[0x8]; 1582 u8 reserved_at_90[0x9]; 1583 u8 wqe_index_ignore_cap[0x1]; 1584 u8 dynamic_qp_allocation[0x1]; 1585 u8 log_max_qp[0x5]; 1586 u8 reserved_at_a0[0x4]; 1587 u8 regexp_num_of_engines[0x4]; 1588 u8 reserved_at_a8[0x1]; 1589 u8 reg_c_preserve[0x1]; 1590 u8 reserved_at_aa[0x1]; 1591 u8 log_max_srq[0x5]; 1592 u8 reserved_at_b0[0xb]; 1593 u8 scatter_fcs_w_decap_disable[0x1]; 1594 u8 reserved_at_bc[0x4]; 1595 u8 reserved_at_c0[0x8]; 1596 u8 log_max_cq_sz[0x8]; 1597 u8 reserved_at_d0[0x2]; 1598 u8 access_register_user[0x1]; 1599 u8 reserved_at_d3[0x8]; 1600 u8 log_max_cq[0x5]; 1601 u8 log_max_eq_sz[0x8]; 1602 u8 relaxed_ordering_write[0x1]; 1603 u8 relaxed_ordering_read[0x1]; 1604 u8 log_max_mkey[0x6]; 1605 u8 reserved_at_f0[0x8]; 1606 u8 dump_fill_mkey[0x1]; 1607 u8 reserved_at_f9[0x3]; 1608 u8 log_max_eq[0x4]; 1609 u8 max_indirection[0x8]; 1610 u8 fixed_buffer_size[0x1]; 1611 u8 log_max_mrw_sz[0x7]; 1612 u8 force_teardown[0x1]; 1613 u8 reserved_at_111[0x1]; 1614 u8 log_max_bsf_list_size[0x6]; 1615 u8 umr_extended_translation_offset[0x1]; 1616 u8 null_mkey[0x1]; 1617 u8 log_maxklm_list_size[0x6]; 1618 u8 non_wire_sq[0x1]; 1619 u8 reserved_at_121[0x9]; 1620 u8 log_max_ra_req_dc[0x6]; 1621 u8 reserved_at_130[0x3]; 1622 u8 log_max_static_sq_wq[0x5]; 1623 u8 reserved_at_138[0x2]; 1624 u8 log_max_ra_res_dc[0x6]; 1625 u8 reserved_at_140[0xa]; 1626 u8 log_max_ra_req_qp[0x6]; 1627 u8 rtr2rts_qp_counters_set_id[0x1]; 1628 u8 rts2rts_udp_sport[0x1]; 1629 u8 rts2rts_lag_tx_port_affinity[0x1]; 1630 u8 dma_mmo_sq[0x1]; 1631 u8 compress_min_block_size[0x4]; 1632 u8 compress_mmo_sq[0x1]; 1633 u8 decompress_mmo_sq[0x1]; 1634 u8 log_max_ra_res_qp[0x6]; 1635 u8 end_pad[0x1]; 1636 u8 cc_query_allowed[0x1]; 1637 u8 cc_modify_allowed[0x1]; 1638 u8 start_pad[0x1]; 1639 u8 cache_line_128byte[0x1]; 1640 u8 reserved_at_165[0xa]; 1641 u8 qcam_reg[0x1]; 1642 u8 gid_table_size[0x10]; 1643 u8 out_of_seq_cnt[0x1]; 1644 u8 vport_counters[0x1]; 1645 u8 retransmission_q_counters[0x1]; 1646 u8 debug[0x1]; 1647 u8 modify_rq_counter_set_id[0x1]; 1648 u8 rq_delay_drop[0x1]; 1649 u8 max_qp_cnt[0xa]; 1650 u8 pkey_table_size[0x10]; 1651 u8 vport_group_manager[0x1]; 1652 u8 vhca_group_manager[0x1]; 1653 u8 ib_virt[0x1]; 1654 u8 eth_virt[0x1]; 1655 u8 vnic_env_queue_counters[0x1]; 1656 u8 ets[0x1]; 1657 u8 nic_flow_table[0x1]; 1658 u8 eswitch_manager[0x1]; 1659 u8 device_memory[0x1]; 1660 u8 mcam_reg[0x1]; 1661 u8 pcam_reg[0x1]; 1662 u8 local_ca_ack_delay[0x5]; 1663 u8 port_module_event[0x1]; 1664 u8 enhanced_error_q_counters[0x1]; 1665 u8 ports_check[0x1]; 1666 u8 reserved_at_1b3[0x1]; 1667 u8 disable_link_up[0x1]; 1668 u8 beacon_led[0x1]; 1669 u8 port_type[0x2]; 1670 u8 num_ports[0x8]; 1671 u8 reserved_at_1c0[0x1]; 1672 u8 pps[0x1]; 1673 u8 pps_modify[0x1]; 1674 u8 log_max_msg[0x5]; 1675 u8 reserved_at_1c8[0x4]; 1676 u8 max_tc[0x4]; 1677 u8 temp_warn_event[0x1]; 1678 u8 dcbx[0x1]; 1679 u8 general_notification_event[0x1]; 1680 u8 reserved_at_1d3[0x2]; 1681 u8 fpga[0x1]; 1682 u8 rol_s[0x1]; 1683 u8 rol_g[0x1]; 1684 u8 reserved_at_1d8[0x1]; 1685 u8 wol_s[0x1]; 1686 u8 wol_g[0x1]; 1687 u8 wol_a[0x1]; 1688 u8 wol_b[0x1]; 1689 u8 wol_m[0x1]; 1690 u8 wol_u[0x1]; 1691 u8 wol_p[0x1]; 1692 u8 stat_rate_support[0x10]; 1693 u8 reserved_at_1ef[0xb]; 1694 u8 wqe_based_flow_table_update_cap[0x1]; 1695 u8 cqe_version[0x4]; 1696 u8 compact_address_vector[0x1]; 1697 u8 striding_rq[0x1]; 1698 u8 reserved_at_202[0x1]; 1699 u8 ipoib_enhanced_offloads[0x1]; 1700 u8 ipoib_basic_offloads[0x1]; 1701 u8 reserved_at_205[0x1]; 1702 u8 repeated_block_disabled[0x1]; 1703 u8 umr_modify_entity_size_disabled[0x1]; 1704 u8 umr_modify_atomic_disabled[0x1]; 1705 u8 umr_indirect_mkey_disabled[0x1]; 1706 u8 umr_fence[0x2]; 1707 u8 reserved_at_20c[0x3]; 1708 u8 drain_sigerr[0x1]; 1709 u8 cmdif_checksum[0x2]; 1710 u8 sigerr_cqe[0x1]; 1711 u8 reserved_at_213[0x1]; 1712 u8 wq_signature[0x1]; 1713 u8 sctr_data_cqe[0x1]; 1714 u8 reserved_at_216[0x1]; 1715 u8 sho[0x1]; 1716 u8 tph[0x1]; 1717 u8 rf[0x1]; 1718 u8 dct[0x1]; 1719 u8 qos[0x1]; 1720 u8 eth_net_offloads[0x1]; 1721 u8 roce[0x1]; 1722 u8 atomic[0x1]; 1723 u8 reserved_at_21f[0x1]; 1724 u8 cq_oi[0x1]; 1725 u8 cq_resize[0x1]; 1726 u8 cq_moderation[0x1]; 1727 u8 reserved_at_223[0x3]; 1728 u8 cq_eq_remap[0x1]; 1729 u8 pg[0x1]; 1730 u8 block_lb_mc[0x1]; 1731 u8 reserved_at_229[0x1]; 1732 u8 scqe_break_moderation[0x1]; 1733 u8 cq_period_start_from_cqe[0x1]; 1734 u8 cd[0x1]; 1735 u8 reserved_at_22d[0x1]; 1736 u8 apm[0x1]; 1737 u8 vector_calc[0x1]; 1738 u8 umr_ptr_rlky[0x1]; 1739 u8 imaicl[0x1]; 1740 u8 reserved_at_232[0x4]; 1741 u8 qkv[0x1]; 1742 u8 pkv[0x1]; 1743 u8 set_deth_sqpn[0x1]; 1744 u8 reserved_at_239[0x3]; 1745 u8 xrc[0x1]; 1746 u8 ud[0x1]; 1747 u8 uc[0x1]; 1748 u8 rc[0x1]; 1749 u8 uar_4k[0x1]; 1750 u8 reserved_at_241[0x8]; 1751 u8 regexp_params[0x1]; 1752 u8 uar_sz[0x6]; 1753 u8 port_selection_cap[0x1]; 1754 u8 reserved_at_251[0x7]; 1755 u8 log_pg_sz[0x8]; 1756 u8 bf[0x1]; 1757 u8 driver_version[0x1]; 1758 u8 pad_tx_eth_packet[0x1]; 1759 u8 reserved_at_263[0x8]; 1760 u8 log_bf_reg_size[0x5]; 1761 u8 reserved_at_270[0xb]; 1762 u8 lag_master[0x1]; 1763 u8 num_lag_ports[0x4]; 1764 u8 reserved_at_280[0x10]; 1765 u8 max_wqe_sz_sq[0x10]; 1766 u8 reserved_at_2a0[0xc]; 1767 u8 regexp_mmo_sq[0x1]; 1768 u8 regexp_version[0x3]; 1769 u8 max_wqe_sz_rq[0x10]; 1770 u8 max_flow_counter_31_16[0x10]; 1771 u8 max_wqe_sz_sq_dc[0x10]; 1772 u8 reserved_at_2e0[0x7]; 1773 u8 max_qp_mcg[0x19]; 1774 u8 reserved_at_300[0x10]; 1775 u8 flow_counter_bulk_alloc[0x08]; 1776 u8 log_max_mcg[0x8]; 1777 u8 reserved_at_320[0x3]; 1778 u8 log_max_transport_domain[0x5]; 1779 u8 reserved_at_328[0x3]; 1780 u8 log_max_pd[0x5]; 1781 u8 reserved_at_330[0xb]; 1782 u8 log_max_xrcd[0x5]; 1783 u8 nic_receive_steering_discard[0x1]; 1784 u8 receive_discard_vport_down[0x1]; 1785 u8 transmit_discard_vport_down[0x1]; 1786 u8 reserved_at_343[0x5]; 1787 u8 log_max_flow_counter_bulk[0x8]; 1788 u8 max_flow_counter_15_0[0x10]; 1789 u8 modify_tis[0x1]; 1790 u8 flow_counters_dump[0x1]; 1791 u8 reserved_at_360[0x1]; 1792 u8 log_max_rq[0x5]; 1793 u8 reserved_at_368[0x3]; 1794 u8 log_max_sq[0x5]; 1795 u8 reserved_at_370[0x3]; 1796 u8 log_max_tir[0x5]; 1797 u8 reserved_at_378[0x3]; 1798 u8 log_max_tis[0x5]; 1799 u8 basic_cyclic_rcv_wqe[0x1]; 1800 u8 reserved_at_381[0x1]; 1801 u8 mem_rq_rmp[0x1]; 1802 u8 log_max_rmp[0x5]; 1803 u8 reserved_at_388[0x3]; 1804 u8 log_max_rqt[0x5]; 1805 u8 reserved_at_390[0x3]; 1806 u8 log_max_rqt_size[0x5]; 1807 u8 reserved_at_398[0x3]; 1808 u8 log_max_tis_per_sq[0x5]; 1809 u8 ext_stride_num_range[0x1]; 1810 u8 reserved_at_3a1[0x2]; 1811 u8 log_max_stride_sz_rq[0x5]; 1812 u8 reserved_at_3a8[0x3]; 1813 u8 log_min_stride_sz_rq[0x5]; 1814 u8 reserved_at_3b0[0x3]; 1815 u8 log_max_stride_sz_sq[0x5]; 1816 u8 reserved_at_3b8[0x3]; 1817 u8 log_min_stride_sz_sq[0x5]; 1818 u8 hairpin[0x1]; 1819 u8 reserved_at_3c1[0x2]; 1820 u8 log_max_hairpin_queues[0x5]; 1821 u8 reserved_at_3c8[0x3]; 1822 u8 log_max_hairpin_wq_data_sz[0x5]; 1823 u8 reserved_at_3d0[0x3]; 1824 u8 log_max_hairpin_num_packets[0x5]; 1825 u8 reserved_at_3d8[0x3]; 1826 u8 log_max_wq_sz[0x5]; 1827 u8 nic_vport_change_event[0x1]; 1828 u8 disable_local_lb_uc[0x1]; 1829 u8 disable_local_lb_mc[0x1]; 1830 u8 log_min_hairpin_wq_data_sz[0x5]; 1831 u8 reserved_at_3e8[0x3]; 1832 u8 log_max_vlan_list[0x5]; 1833 u8 reserved_at_3f0[0x1]; 1834 u8 aes_xts_single_block_le_tweak[1]; 1835 u8 aes_xts_multi_block_be_tweak[1]; 1836 u8 log_max_current_mc_list[0x5]; 1837 u8 reserved_at_3f8[0x3]; 1838 u8 log_max_current_uc_list[0x5]; 1839 u8 general_obj_types[0x40]; 1840 u8 sq_ts_format[0x2]; 1841 u8 rq_ts_format[0x2]; 1842 u8 steering_format_version[0x4]; 1843 u8 reserved_at_448[0x18]; 1844 u8 reserved_at_460[0x8]; 1845 u8 aes_xts[0x1]; 1846 u8 crypto[0x1]; 1847 u8 ipsec_offload[0x1]; 1848 u8 reserved_at_46b[0x5]; 1849 u8 max_num_eqs[0x10]; 1850 u8 reserved_at_480[0x3]; 1851 u8 log_max_l2_table[0x5]; 1852 u8 reserved_at_488[0x8]; 1853 u8 log_uar_page_sz[0x10]; 1854 u8 reserved_at_4a0[0x20]; 1855 u8 device_frequency_mhz[0x20]; 1856 u8 device_frequency_khz[0x20]; 1857 u8 reserved_at_500[0x20]; 1858 u8 num_of_uars_per_page[0x20]; 1859 u8 flex_parser_protocols[0x20]; 1860 u8 max_geneve_tlv_options[0x8]; 1861 u8 geneve_tlv_sample[0x1]; 1862 u8 geneve_tlv_option_offset[0x1]; 1863 u8 reserved_at_56a[0x1]; 1864 u8 max_geneve_tlv_option_data_len[0x5]; 1865 u8 flex_parser_header_modify[0x1]; 1866 u8 reserved_at_571[0x2]; 1867 u8 log_max_guaranteed_connections[0x5]; 1868 u8 driver_version_before_init_hca[0x1]; 1869 u8 adv_virtualization[0x1]; 1870 u8 reserved_at_57a[0x1]; 1871 u8 log_max_dct_connections[0x5]; 1872 u8 log_max_atomic_size_qp[0x8]; 1873 u8 reserved_at_587[0x3]; 1874 u8 log_max_dci_stream_channels[0x5]; 1875 u8 reserved_at_58f[0x3]; 1876 u8 log_max_dci_errored_streams[0x5]; 1877 u8 log_max_atomic_dize_dc[0x8]; 1878 u8 max_multi_user_ggroup_size[0x10]; 1879 u8 enhanced_cqe_compression[0x1]; 1880 u8 reserved_at_5b0[0x1]; 1881 u8 crossing_vhca_mkey[0x1]; 1882 u8 log_max_dek[0x5]; 1883 u8 reserved_at_5b7[0x1]; 1884 u8 mini_cqe_resp_l3_l4_tag[0x1]; 1885 u8 mini_cqe_resp_flow_tag[0x1]; 1886 u8 reserved_at_5ba[0x1]; 1887 u8 mini_cqe_resp_stride_index[0x1]; 1888 u8 cqe_128_always[0x1]; 1889 u8 cqe_compression_128[0x1]; 1890 u8 cqe_compression[0x1]; 1891 u8 cqe_compression_timeout[0x10]; 1892 u8 cqe_compression_max_num[0x10]; 1893 u8 reserved_at_5e0[0x8]; 1894 u8 flex_parser_id_gtpu_dw_0[0x4]; 1895 u8 reserved_at_5ec[0x4]; 1896 u8 tag_matching[0x1]; 1897 u8 rndv_offload_rc[0x1]; 1898 u8 rndv_offload_dc[0x1]; 1899 u8 log_tag_matching_list_sz[0x5]; 1900 u8 reserved_at_5f8[0x3]; 1901 u8 log_max_xrq[0x5]; 1902 u8 affiliate_nic_vport_criteria[0x8]; 1903 u8 native_port_num[0x8]; 1904 u8 num_vhca_ports[0x8]; 1905 u8 flex_parser_id_gtpu_teid[0x4]; 1906 u8 reserved_at_61c[0x2]; 1907 u8 sw_owner_id[0x1]; 1908 u8 reserved_at_61f[0x6C]; 1909 u8 wait_on_data[0x1]; 1910 u8 wait_on_time[0x1]; 1911 u8 reserved_at_68d[0x37]; 1912 u8 flex_parser_id_geneve_opt_0[0x4]; 1913 u8 flex_parser_id_icmp_dw1[0x4]; 1914 u8 flex_parser_id_icmp_dw0[0x4]; 1915 u8 flex_parser_id_icmpv6_dw1[0x4]; 1916 u8 flex_parser_id_icmpv6_dw0[0x4]; 1917 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1918 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1919 u8 reserved_at_6e0[0x20]; 1920 u8 flex_parser_id_gtpu_dw_2[0x4]; 1921 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1922 u8 reserved_at_708[0x40]; 1923 u8 dma_mmo_qp[0x1]; 1924 u8 regexp_mmo_qp[0x1]; 1925 u8 compress_mmo_qp[0x1]; 1926 u8 decompress_deflate_v1[0x1]; 1927 u8 reserved_at_74c[0x4]; 1928 u8 decompress_deflate_v2[0x1]; 1929 u8 reserved_at_751[0xf]; 1930 u8 reserved_at_760[0x3]; 1931 u8 log_max_num_header_modify_argument[0x5]; 1932 u8 log_header_modify_argument_granularity_offset[0x4]; 1933 u8 log_header_modify_argument_granularity[0x4]; 1934 u8 reserved_at_770[0x3]; 1935 u8 log_header_modify_argument_max_alloc[0x5]; 1936 u8 reserved_at_778[0x8]; 1937 u8 reserved_at_780[0x40]; 1938 u8 match_definer_format_supported[0x40]; 1939 }; 1940 1941 struct mlx5_ifc_qos_cap_bits { 1942 u8 packet_pacing[0x1]; 1943 u8 esw_scheduling[0x1]; 1944 u8 esw_bw_share[0x1]; 1945 u8 esw_rate_limit[0x1]; 1946 u8 reserved_at_4[0x1]; 1947 u8 packet_pacing_burst_bound[0x1]; 1948 u8 packet_pacing_typical_size[0x1]; 1949 u8 flow_meter_old[0x1]; 1950 u8 reserved_at_8[0x8]; 1951 u8 log_max_flow_meter[0x8]; 1952 u8 flow_meter_reg_id[0x8]; 1953 u8 wqe_rate_pp[0x1]; 1954 u8 reserved_at_25[0x7]; 1955 u8 flow_meter[0x1]; 1956 u8 reserved_at_2e[0x17]; 1957 u8 packet_pacing_max_rate[0x20]; 1958 u8 packet_pacing_min_rate[0x20]; 1959 u8 reserved_at_80[0x10]; 1960 u8 packet_pacing_rate_table_size[0x10]; 1961 u8 esw_element_type[0x10]; 1962 u8 esw_tsar_type[0x10]; 1963 u8 reserved_at_c0[0x10]; 1964 u8 max_qos_para_vport[0x10]; 1965 u8 max_tsar_bw_share[0x20]; 1966 u8 nic_element_type[0x10]; 1967 u8 nic_tsar_type[0x10]; 1968 u8 reserved_at_120[0x3]; 1969 u8 log_meter_aso_granularity[0x5]; 1970 u8 reserved_at_128[0x3]; 1971 u8 log_meter_aso_max_alloc[0x5]; 1972 u8 reserved_at_130[0x3]; 1973 u8 log_max_num_meter_aso[0x5]; 1974 u8 reserved_at_138[0x6b0]; 1975 }; 1976 1977 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1978 u8 csum_cap[0x1]; 1979 u8 vlan_cap[0x1]; 1980 u8 lro_cap[0x1]; 1981 u8 lro_psh_flag[0x1]; 1982 u8 lro_time_stamp[0x1]; 1983 u8 lro_max_msg_sz_mode[0x2]; 1984 u8 wqe_vlan_insert[0x1]; 1985 u8 self_lb_en_modifiable[0x1]; 1986 u8 self_lb_mc[0x1]; 1987 u8 self_lb_uc[0x1]; 1988 u8 max_lso_cap[0x5]; 1989 u8 multi_pkt_send_wqe[0x2]; 1990 u8 wqe_inline_mode[0x2]; 1991 u8 rss_ind_tbl_cap[0x4]; 1992 u8 reg_umr_sq[0x1]; 1993 u8 scatter_fcs[0x1]; 1994 u8 enhanced_multi_pkt_send_wqe[0x1]; 1995 u8 tunnel_lso_const_out_ip_id[0x1]; 1996 u8 tunnel_lro_gre[0x1]; 1997 u8 tunnel_lro_vxlan[0x1]; 1998 u8 tunnel_stateless_gre[0x1]; 1999 u8 tunnel_stateless_vxlan[0x1]; 2000 u8 swp[0x1]; 2001 u8 swp_csum[0x1]; 2002 u8 swp_lso[0x1]; 2003 u8 reserved_at_23[0x8]; 2004 u8 tunnel_stateless_gtp[0x1]; 2005 u8 reserved_at_25[0x2]; 2006 u8 tunnel_stateless_vxlan_gpe_nsh[0x1]; 2007 u8 reserved_at_28[0x1]; 2008 u8 max_vxlan_udp_ports[0x8]; 2009 u8 reserved_at_38[0x6]; 2010 u8 max_geneve_opt_len[0x1]; 2011 u8 tunnel_stateless_geneve_rx[0x1]; 2012 u8 reserved_at_40[0x10]; 2013 u8 lro_min_mss_size[0x10]; 2014 u8 reserved_at_60[0x120]; 2015 u8 lro_timer_supported_periods[4][0x20]; 2016 u8 reserved_at_200[0x600]; 2017 }; 2018 2019 enum { 2020 MLX5_VIRTQ_TYPE_SPLIT = 0, 2021 MLX5_VIRTQ_TYPE_PACKED = 1, 2022 }; 2023 2024 enum { 2025 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0, 2026 MLX5_VIRTQ_EVENT_MODE_QP = 1, 2027 MLX5_VIRTQ_EVENT_MODE_MSIX = 2, 2028 }; 2029 2030 struct mlx5_ifc_virtio_emulation_cap_bits { 2031 u8 desc_tunnel_offload_type[0x1]; 2032 u8 eth_frame_offload_type[0x1]; 2033 u8 virtio_version_1_0[0x1]; 2034 u8 tso_ipv4[0x1]; 2035 u8 tso_ipv6[0x1]; 2036 u8 tx_csum[0x1]; 2037 u8 rx_csum[0x1]; 2038 u8 reserved_at_7[0x1][0x9]; 2039 u8 event_mode[0x8]; 2040 u8 virtio_queue_type[0x8]; 2041 u8 reserved_at_20[0x13]; 2042 u8 log_doorbell_stride[0x5]; 2043 u8 vnet_modify_ext[0x1]; 2044 u8 virtio_net_q_addr_modify[0x1]; 2045 u8 virtio_q_index_modify[0x1]; 2046 u8 log_doorbell_bar_size[0x5]; 2047 u8 doorbell_bar_offset[0x40]; 2048 u8 reserved_at_80[0x8]; 2049 u8 max_num_virtio_queues[0x18]; 2050 u8 reserved_at_a0[0x60]; 2051 u8 umem_1_buffer_param_a[0x20]; 2052 u8 umem_1_buffer_param_b[0x20]; 2053 u8 umem_2_buffer_param_a[0x20]; 2054 u8 umem_2_buffer_param_b[0x20]; 2055 u8 umem_3_buffer_param_a[0x20]; 2056 u8 umem_3_buffer_param_b[0x20]; 2057 u8 reserved_at_1c0[0x620]; 2058 }; 2059 2060 /** 2061 * PARSE_GRAPH_NODE Capabilities Field Descriptions 2062 */ 2063 struct mlx5_ifc_parse_graph_node_cap_bits { 2064 u8 node_in[0x20]; 2065 u8 node_out[0x20]; 2066 u8 header_length_mode[0x10]; 2067 u8 sample_offset_mode[0x10]; 2068 u8 max_num_arc_in[0x08]; 2069 u8 max_num_arc_out[0x08]; 2070 u8 max_num_sample[0x08]; 2071 u8 reserved_at_78[0x03]; 2072 u8 parse_graph_anchor[0x1]; 2073 u8 reserved_at_7c[0x01]; 2074 u8 sample_tunnel_inner2[0x1]; 2075 u8 zero_size_supported[0x1]; 2076 u8 sample_id_in_out[0x1]; 2077 u8 max_base_header_length[0x10]; 2078 u8 reserved_at_90[0x08]; 2079 u8 max_sample_base_offset[0x08]; 2080 u8 max_next_header_offset[0x10]; 2081 u8 reserved_at_b0[0x08]; 2082 u8 header_length_mask_width[0x08]; 2083 }; 2084 2085 struct mlx5_ifc_flow_table_prop_layout_bits { 2086 u8 ft_support[0x1]; 2087 u8 flow_tag[0x1]; 2088 u8 flow_counter[0x1]; 2089 u8 flow_modify_en[0x1]; 2090 u8 modify_root[0x1]; 2091 u8 identified_miss_table[0x1]; 2092 u8 flow_table_modify[0x1]; 2093 u8 reformat[0x1]; 2094 u8 decap[0x1]; 2095 u8 reset_root_to_default[0x1]; 2096 u8 pop_vlan[0x1]; 2097 u8 push_vlan[0x1]; 2098 u8 fpga_vendor_acceleration[0x1]; 2099 u8 pop_vlan_2[0x1]; 2100 u8 push_vlan_2[0x1]; 2101 u8 reformat_and_vlan_action[0x1]; 2102 u8 modify_and_vlan_action[0x1]; 2103 u8 sw_owner[0x1]; 2104 u8 reformat_l3_tunnel_to_l2[0x1]; 2105 u8 reformat_l2_to_l3_tunnel[0x1]; 2106 u8 reformat_and_modify_action[0x1]; 2107 u8 reserved_at_15[0x9]; 2108 u8 sw_owner_v2[0x1]; 2109 u8 reserved_at_1f[0x1]; 2110 u8 reserved_at_20[0x2]; 2111 u8 log_max_ft_size[0x6]; 2112 u8 log_max_modify_header_context[0x8]; 2113 u8 max_modify_header_actions[0x8]; 2114 u8 max_ft_level[0x8]; 2115 u8 reserved_at_40[0x8]; 2116 u8 log_max_ft_sampler_num[8]; 2117 u8 metadata_reg_b_width[0x8]; 2118 u8 metadata_reg_a_width[0x8]; 2119 u8 reserved_at_60[0xa]; 2120 u8 reparse[0x1]; 2121 u8 reserved_at_6b[0x1]; 2122 u8 cross_vhca_object[0x1]; 2123 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 2124 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 2125 u8 ignore_flow_level_rtc_valid[0x1]; 2126 u8 reserved_at_70[0x8]; 2127 u8 log_max_ft_num[0x8]; 2128 u8 reserved_at_80[0x10]; 2129 u8 log_max_flow_counter[0x8]; 2130 u8 log_max_destination[0x8]; 2131 u8 reserved_at_a0[0x18]; 2132 u8 log_max_flow[0x8]; 2133 u8 reserved_at_c0[0x140]; 2134 }; 2135 2136 struct mlx5_ifc_roce_caps_bits { 2137 u8 reserved_0[0x1e]; 2138 u8 qp_ts_format[0x2]; 2139 u8 reserved_at_20[0xa0]; 2140 u8 r_roce_max_src_udp_port[0x10]; 2141 u8 r_roce_min_src_udp_port[0x10]; 2142 u8 reserved_at_e0[0x720]; 2143 }; 2144 2145 struct mlx5_ifc_ft_fields_support_bits { 2146 /* set_action_field_support */ 2147 u8 outer_dmac[0x1]; 2148 u8 outer_smac[0x1]; 2149 u8 outer_ether_type[0x1]; 2150 u8 reserved_at_3[0x1]; 2151 u8 outer_first_prio[0x1]; 2152 u8 outer_first_cfi[0x1]; 2153 u8 outer_first_vid[0x1]; 2154 u8 reserved_at_7[0x1]; 2155 u8 outer_second_prio[0x1]; 2156 u8 outer_second_cfi[0x1]; 2157 u8 outer_second_vid[0x1]; 2158 u8 reserved_at_b[0x1]; 2159 u8 outer_sip[0x1]; 2160 u8 outer_dip[0x1]; 2161 u8 outer_frag[0x1]; 2162 u8 outer_ip_protocol[0x1]; 2163 u8 outer_ip_ecn[0x1]; 2164 u8 outer_ip_dscp[0x1]; 2165 u8 outer_udp_sport[0x1]; 2166 u8 outer_udp_dport[0x1]; 2167 u8 outer_tcp_sport[0x1]; 2168 u8 outer_tcp_dport[0x1]; 2169 u8 outer_tcp_flags[0x1]; 2170 u8 outer_gre_protocol[0x1]; 2171 u8 outer_gre_key[0x1]; 2172 u8 outer_vxlan_vni[0x1]; 2173 u8 reserved_at_1a[0x5]; 2174 u8 source_eswitch_port[0x1]; /* end of DW0 */ 2175 u8 inner_dmac[0x1]; 2176 u8 inner_smac[0x1]; 2177 u8 inner_ether_type[0x1]; 2178 u8 reserved_at_23[0x1]; 2179 u8 inner_first_prio[0x1]; 2180 u8 inner_first_cfi[0x1]; 2181 u8 inner_first_vid[0x1]; 2182 u8 reserved_at_27[0x1]; 2183 u8 inner_second_prio[0x1]; 2184 u8 inner_second_cfi[0x1]; 2185 u8 inner_second_vid[0x1]; 2186 u8 reserved_at_2b[0x1]; 2187 u8 inner_sip[0x1]; 2188 u8 inner_dip[0x1]; 2189 u8 inner_frag[0x1]; 2190 u8 inner_ip_protocol[0x1]; 2191 u8 inner_ip_ecn[0x1]; 2192 u8 inner_ip_dscp[0x1]; 2193 u8 inner_udp_sport[0x1]; 2194 u8 inner_udp_dport[0x1]; 2195 u8 inner_tcp_sport[0x1]; 2196 u8 inner_tcp_dport[0x1]; 2197 u8 inner_tcp_flags[0x1]; 2198 u8 reserved_at_37[0x9]; /* end of DW1 */ 2199 u8 reserved_at_40[0x20]; /* end of DW2 */ 2200 u8 reserved_at_60[0x18]; 2201 union { 2202 struct { 2203 u8 metadata_reg_c_7[0x1]; 2204 u8 metadata_reg_c_6[0x1]; 2205 u8 metadata_reg_c_5[0x1]; 2206 u8 metadata_reg_c_4[0x1]; 2207 u8 metadata_reg_c_3[0x1]; 2208 u8 metadata_reg_c_2[0x1]; 2209 u8 metadata_reg_c_1[0x1]; 2210 u8 metadata_reg_c_0[0x1]; 2211 }; 2212 u8 metadata_reg_c_x[0x8]; 2213 }; /* end of DW3 */ 2214 /* set_action_field_support_2 */ 2215 u8 reserved_at_80[0x37]; 2216 u8 outer_ipv6_traffic_class[0x1]; 2217 u8 reserved_at_B8[0x48]; 2218 /* add_action_field_support */ 2219 u8 reserved_at_100[0x80]; 2220 /* add_action_field_support_2 */ 2221 u8 reserved_at_180[0x80]; 2222 /* copy_action_field_support */ 2223 u8 reserved_at_200[0x80]; 2224 /* copy_action_field_support_2 */ 2225 u8 reserved_at_280[0x80]; 2226 u8 reserved_at_300[0x100]; 2227 }; 2228 2229 /* 2230 * Table 1872 - Flow Table Fields Supported 2 Format 2231 */ 2232 struct mlx5_ifc_ft_fields_support_2_bits { 2233 u8 reserved_at_0[0xa]; 2234 u8 lag_rx_port_affinity[0x1]; 2235 u8 reserved_at_c[0x2]; 2236 u8 hash_result[0x1]; 2237 u8 reserved_at_e[0x1]; 2238 u8 tunnel_header_2_3[0x1]; 2239 u8 tunnel_header_0_1[0x1]; 2240 u8 macsec_syndrome[0x1]; 2241 u8 macsec_tag[0x1]; 2242 u8 outer_lrh_sl[0x1]; 2243 u8 inner_ipv4_ihl[0x1]; 2244 u8 outer_ipv4_ihl[0x1]; 2245 u8 psp_syndrome[0x1]; 2246 u8 inner_l3_ok[0x1]; 2247 u8 inner_l4_ok[0x1]; 2248 u8 outer_l3_ok[0x1]; 2249 u8 outer_l4_ok[0x1]; 2250 u8 psp_header[0x1]; 2251 u8 inner_ipv4_checksum_ok[0x1]; 2252 u8 inner_l4_checksum_ok[0x1]; 2253 u8 outer_ipv4_checksum_ok[0x1]; 2254 u8 outer_l4_checksum_ok[0x1]; /* end of DW0 */ 2255 u8 reserved_at_20[0x17]; 2256 u8 outer_ipv6_traffic_class[0x1]; 2257 union { 2258 struct { 2259 u8 metadata_reg_c_15[0x1]; 2260 u8 metadata_reg_c_14[0x1]; 2261 u8 metadata_reg_c_13[0x1]; 2262 u8 metadata_reg_c_12[0x1]; 2263 u8 metadata_reg_c_11[0x1]; 2264 u8 metadata_reg_c_10[0x1]; 2265 u8 metadata_reg_c_9[0x1]; 2266 u8 metadata_reg_c_8[0x1]; 2267 }; 2268 u8 metadata_reg_c_8_15[0x8]; 2269 }; /* end of DW1 */ 2270 u8 reserved_at_40[0x40]; 2271 }; 2272 2273 struct mlx5_ifc_flow_table_nic_cap_bits { 2274 u8 reserved_at_0[0x200]; 2275 struct mlx5_ifc_flow_table_prop_layout_bits 2276 flow_table_properties_nic_receive; 2277 struct mlx5_ifc_flow_table_prop_layout_bits 2278 flow_table_properties_nic_receive_rdma; 2279 struct mlx5_ifc_flow_table_prop_layout_bits 2280 flow_table_properties_nic_receive_sniffer; 2281 struct mlx5_ifc_flow_table_prop_layout_bits 2282 flow_table_properties_nic_transmit; 2283 struct mlx5_ifc_flow_table_prop_layout_bits 2284 flow_table_properties_nic_transmit_rdma; 2285 struct mlx5_ifc_flow_table_prop_layout_bits 2286 flow_table_properties_nic_transmit_sniffer; 2287 u8 reserved_at_e00[0x200]; 2288 struct mlx5_ifc_ft_fields_support_bits 2289 ft_header_modify_nic_receive; 2290 struct mlx5_ifc_ft_fields_support_2_bits 2291 ft_field_support_2_nic_receive; 2292 u8 reserved_at_1480[0x280]; 2293 struct mlx5_ifc_ft_fields_support_2_bits 2294 ft_field_support_2_nic_transmit; 2295 u8 reserved_at_1780[0x480]; 2296 struct mlx5_ifc_ft_fields_support_bits 2297 ft_header_modify_nic_transmit; 2298 u8 reserved_at_2000[0x6000]; 2299 }; 2300 2301 struct mlx5_ifc_flow_table_esw_cap_bits { 2302 u8 reserved_at_0[0x800]; 2303 struct mlx5_ifc_ft_fields_support_bits ft_header_modify_esw_fdb; 2304 u8 reserved_at_C00[0x800]; 2305 struct mlx5_ifc_ft_fields_support_2_bits 2306 ft_field_support_2_esw_fdb; 2307 u8 reserved_at_1480[0x6b80]; 2308 }; 2309 2310 enum mlx5_ifc_cross_vhca_object_to_object_supported_types { 2311 MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR = 1 << 10, 2312 MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT = 1 << 11, 2313 MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT = 1 << 12, 2314 MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC = 1 << 13, 2315 }; 2316 2317 enum mlx5_ifc_cross_vhca_allowed_objects_types { 2318 MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR = 1 << 0x8, 2319 MLX5_CROSS_VHCA_ALLOWED_OBJS_FT = 1 << 0x9, 2320 MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC = 1 << 0xa, 2321 }; 2322 2323 enum { 2324 MLX5_GENERATE_WQE_TYPE_FLOW_UPDATE = 1 << 1, 2325 }; 2326 2327 enum { 2328 MLX5_FLOW_TABLE_HASH_TYPE_CRC32, 2329 }; 2330 /* 2331 * HCA Capabilities 2 2332 */ 2333 struct mlx5_ifc_cmd_hca_cap_2_bits { 2334 u8 reserved_at_0[0x80]; /* End of DW4. */ 2335 u8 reserved_at_80[0x3]; 2336 u8 max_num_prog_sample_field[0x5]; 2337 u8 reserved_at_88[0x3]; 2338 u8 log_max_num_reserved_qpn[0x5]; 2339 u8 reserved_at_90[0x3]; 2340 u8 log_reserved_qpn_granularity[0x5]; 2341 u8 reserved_at_98[0x3]; 2342 u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */ 2343 u8 max_reformat_insert_size[0x8]; 2344 u8 max_reformat_insert_offset[0x8]; 2345 u8 max_reformat_remove_size[0x8]; 2346 u8 max_reformat_remove_offset[0x8]; /* End of DW6. */ 2347 u8 reserved_at_c0[0x3]; 2348 u8 log_min_stride_wqe_sz[0x5]; 2349 u8 reserved_at_c8[0x3]; 2350 u8 log_conn_track_granularity[0x5]; 2351 u8 reserved_at_d0[0x3]; 2352 u8 log_conn_track_max_alloc[0x5]; 2353 u8 reserved_at_d8[0x3]; 2354 u8 log_max_conn_track_offload[0x5]; 2355 u8 cross_vhca_object_to_object_supported[0x20]; /* End of DW7. */ 2356 u8 allowed_object_for_other_vhca_access_high[0x20]; 2357 u8 allowed_object_for_other_vhca_access[0x20]; 2358 u8 reserved_at_140[0x20]; 2359 u8 reserved_at_160[0x3]; 2360 u8 hairpin_sq_wqe_bb_size[0x5]; 2361 u8 hairpin_sq_wq_in_host_mem[0x1]; 2362 u8 hairpin_data_buffer_locked[0x1]; 2363 u8 reserved_at_16a[0x16]; 2364 u8 reserved_at_180[0x20]; 2365 u8 reserved_at_1a0[0xa]; 2366 u8 format_select_dw_8_6_ext[0x1]; 2367 u8 reserved_at_1ac[0x15]; 2368 u8 general_obj_types_127_64[0x40]; 2369 u8 reserved_at_200[0x53]; 2370 u8 flow_counter_bulk_log_max_alloc[0x5]; 2371 u8 reserved_at_258[0x3]; 2372 u8 flow_counter_bulk_log_granularity[0x5]; 2373 u8 reserved_at_260[0x20]; 2374 u8 format_select_dw_gtpu_dw_0[0x8]; 2375 u8 format_select_dw_gtpu_dw_1[0x8]; 2376 u8 format_select_dw_gtpu_dw_2[0x8]; 2377 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2378 u8 generate_wqe_type[0x20]; 2379 u8 reserved_at_2c0[0x160]; 2380 u8 reserved_at_420[0x18]; 2381 u8 encap_entropy_hash_type[0x4]; 2382 u8 flow_table_hash_type[0x4]; 2383 u8 reserved_at_440[0x3c0]; 2384 }; 2385 2386 struct mlx5_ifc_esw_cap_bits { 2387 u8 reserved_at_0[0x1d]; 2388 u8 merged_eswitch[0x1]; 2389 u8 reserved_at_1e[0x2]; 2390 2391 u8 reserved_at_20[0x40]; 2392 2393 u8 esw_manager_vport_number_valid[0x1]; 2394 u8 reserved_at_61[0xf]; 2395 u8 esw_manager_vport_number[0x10]; 2396 2397 u8 reserved_at_80[0x780]; 2398 }; 2399 2400 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 2401 u8 reserved_at_0[0x3]; 2402 u8 log_max_num_ste[0x5]; 2403 u8 reserved_at_8[0x3]; 2404 u8 log_max_num_stc[0x5]; 2405 u8 reserved_at_10[0x3]; 2406 u8 log_max_num_rtc[0x5]; 2407 u8 reserved_at_18[0x3]; 2408 u8 log_max_num_header_modify_pattern[0x5]; 2409 u8 rtc_hash_split_table[0x1]; 2410 u8 rtc_linear_lookup_table[0x1]; 2411 u8 reserved_at_22[0x1]; 2412 u8 stc_alloc_log_granularity[0x5]; 2413 u8 reserved_at_28[0x3]; 2414 u8 stc_alloc_log_max[0x5]; 2415 u8 reserved_at_30[0x3]; 2416 u8 ste_alloc_log_granularity[0x5]; 2417 u8 reserved_at_38[0x3]; 2418 u8 ste_alloc_log_max[0x5]; 2419 u8 reserved_at_40[0xb]; 2420 u8 rtc_reparse_mode[0x5]; 2421 u8 reserved_at_50[0x3]; 2422 u8 rtc_index_mode[0x5]; 2423 u8 reserved_at_58[0x3]; 2424 u8 rtc_log_depth_max[0x5]; 2425 u8 reserved_at_60[0x8]; 2426 u8 max_header_modify_pattern_length[0x8]; 2427 u8 ste_format[0x10]; 2428 u8 stc_action_type[0x80]; 2429 u8 header_insert_type[0x10]; 2430 u8 header_remove_type[0x10]; 2431 u8 trivial_match_definer[0x20]; 2432 u8 reserved_at_140[0x1b]; 2433 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 2434 u8 reserved_at_160[0x18]; 2435 u8 access_index_mode[0x8]; 2436 u8 reserved_at_180[0x10]; 2437 u8 ste_format_gen_wqe[0x10]; 2438 u8 linear_match_definer_reg_c3[0x20]; 2439 u8 fdb_jump_to_tir_stc[0x1]; 2440 u8 reserved_at_1c1[0x1f]; 2441 }; 2442 2443 union mlx5_ifc_hca_cap_union_bits { 2444 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2445 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 2446 struct mlx5_ifc_per_protocol_networking_offload_caps_bits 2447 per_protocol_networking_offload_caps; 2448 struct mlx5_ifc_qos_cap_bits qos_cap; 2449 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps; 2450 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2451 struct mlx5_ifc_flow_table_esw_cap_bits flow_table_esw_cap; 2452 struct mlx5_ifc_esw_cap_bits esw_cap; 2453 struct mlx5_ifc_roce_caps_bits roce_caps; 2454 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 2455 u8 reserved_at_0[0x8000]; 2456 }; 2457 2458 struct mlx5_ifc_set_action_in_bits { 2459 u8 action_type[0x4]; 2460 u8 field[0xc]; 2461 u8 reserved_at_10[0x3]; 2462 u8 offset[0x5]; 2463 u8 reserved_at_18[0x3]; 2464 u8 length[0x5]; 2465 u8 data[0x20]; 2466 }; 2467 2468 struct mlx5_ifc_copy_action_in_bits { 2469 u8 action_type[0x4]; 2470 u8 src_field[0xc]; 2471 u8 reserved_at_10[0x3]; 2472 u8 src_offset[0x5]; 2473 u8 reserved_at_18[0x3]; 2474 u8 length[0x5]; 2475 u8 reserved_at_20[0x4]; 2476 u8 dst_field[0xc]; 2477 u8 reserved_at_30[0x3]; 2478 u8 dst_offset[0x5]; 2479 u8 reserved_at_38[0x8]; 2480 }; 2481 2482 struct mlx5_ifc_query_hca_cap_out_bits { 2483 u8 status[0x8]; 2484 u8 reserved_at_8[0x18]; 2485 u8 syndrome[0x20]; 2486 u8 reserved_at_40[0x40]; 2487 union mlx5_ifc_hca_cap_union_bits capability; 2488 }; 2489 2490 struct mlx5_ifc_query_hca_cap_in_bits { 2491 u8 opcode[0x10]; 2492 u8 reserved_at_10[0x10]; 2493 u8 reserved_at_20[0x10]; 2494 u8 op_mod[0x10]; 2495 u8 reserved_at_40[0x40]; 2496 }; 2497 2498 struct mlx5_ifc_mac_address_layout_bits { 2499 u8 reserved_at_0[0x10]; 2500 u8 mac_addr_47_32[0x10]; 2501 u8 mac_addr_31_0[0x20]; 2502 }; 2503 2504 struct mlx5_ifc_nic_vport_context_bits { 2505 u8 reserved_at_0[0x5]; 2506 u8 min_wqe_inline_mode[0x3]; 2507 u8 reserved_at_8[0x15]; 2508 u8 disable_mc_local_lb[0x1]; 2509 u8 disable_uc_local_lb[0x1]; 2510 u8 roce_en[0x1]; 2511 u8 arm_change_event[0x1]; 2512 u8 reserved_at_21[0x1a]; 2513 u8 event_on_mtu[0x1]; 2514 u8 event_on_promisc_change[0x1]; 2515 u8 event_on_vlan_change[0x1]; 2516 u8 event_on_mc_address_change[0x1]; 2517 u8 event_on_uc_address_change[0x1]; 2518 u8 reserved_at_40[0xc]; 2519 u8 affiliation_criteria[0x4]; 2520 u8 affiliated_vhca_id[0x10]; 2521 u8 reserved_at_60[0xd0]; 2522 u8 mtu[0x10]; 2523 u8 system_image_guid[0x40]; 2524 u8 port_guid[0x40]; 2525 u8 node_guid[0x40]; 2526 u8 reserved_at_200[0x140]; 2527 u8 qkey_violation_counter[0x10]; 2528 u8 reserved_at_350[0x430]; 2529 u8 promisc_uc[0x1]; 2530 u8 promisc_mc[0x1]; 2531 u8 promisc_all[0x1]; 2532 u8 reserved_at_783[0x2]; 2533 u8 allowed_list_type[0x3]; 2534 u8 reserved_at_788[0xc]; 2535 u8 allowed_list_size[0xc]; 2536 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2537 u8 reserved_at_7e0[0x20]; 2538 }; 2539 2540 struct mlx5_ifc_query_nic_vport_context_out_bits { 2541 u8 status[0x8]; 2542 u8 reserved_at_8[0x18]; 2543 u8 syndrome[0x20]; 2544 u8 reserved_at_40[0x40]; 2545 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 2546 }; 2547 2548 struct mlx5_ifc_query_nic_vport_context_in_bits { 2549 u8 opcode[0x10]; 2550 u8 reserved_at_10[0x10]; 2551 u8 reserved_at_20[0x10]; 2552 u8 op_mod[0x10]; 2553 u8 other_vport[0x1]; 2554 u8 reserved_at_41[0xf]; 2555 u8 vport_number[0x10]; 2556 u8 reserved_at_60[0x5]; 2557 u8 allowed_list_type[0x3]; 2558 u8 reserved_at_68[0x18]; 2559 }; 2560 2561 struct mlx5_ifc_tisc_bits { 2562 u8 strict_lag_tx_port_affinity[0x1]; 2563 u8 reserved_at_1[0x3]; 2564 u8 lag_tx_port_affinity[0x04]; 2565 u8 reserved_at_8[0x4]; 2566 u8 prio[0x4]; 2567 u8 reserved_at_10[0x10]; 2568 u8 reserved_at_20[0x100]; 2569 u8 reserved_at_120[0x8]; 2570 u8 transport_domain[0x18]; 2571 u8 reserved_at_140[0x8]; 2572 u8 underlay_qpn[0x18]; 2573 u8 reserved_at_160[0x3a0]; 2574 }; 2575 2576 struct mlx5_ifc_query_tis_out_bits { 2577 u8 status[0x8]; 2578 u8 reserved_at_8[0x18]; 2579 u8 syndrome[0x20]; 2580 u8 reserved_at_40[0x40]; 2581 struct mlx5_ifc_tisc_bits tis_context; 2582 }; 2583 2584 struct mlx5_ifc_query_tis_in_bits { 2585 u8 opcode[0x10]; 2586 u8 reserved_at_10[0x10]; 2587 u8 reserved_at_20[0x10]; 2588 u8 op_mod[0x10]; 2589 u8 reserved_at_40[0x8]; 2590 u8 tisn[0x18]; 2591 u8 reserved_at_60[0x20]; 2592 }; 2593 2594 /* port_select_mode definition. */ 2595 enum mlx5_lag_mode_type { 2596 MLX5_LAG_MODE_TIS = 0, 2597 MLX5_LAG_MODE_HASH = 1, 2598 }; 2599 2600 struct mlx5_ifc_lag_context_bits { 2601 u8 fdb_selection_mode[0x1]; 2602 u8 reserved_at_1[0x14]; 2603 u8 port_select_mode[0x3]; 2604 u8 reserved_at_18[0x5]; 2605 u8 lag_state[0x3]; 2606 u8 reserved_at_20[0x14]; 2607 u8 tx_remap_affinity_2[0x4]; 2608 u8 reserved_at_38[0x4]; 2609 u8 tx_remap_affinity_1[0x4]; 2610 }; 2611 2612 struct mlx5_ifc_query_lag_in_bits { 2613 u8 opcode[0x10]; 2614 u8 uid[0x10]; 2615 u8 reserved_at_20[0x10]; 2616 u8 op_mod[0x10]; 2617 u8 reserved_at_40[0x40]; 2618 }; 2619 2620 struct mlx5_ifc_query_lag_out_bits { 2621 u8 status[0x8]; 2622 u8 reserved_at_8[0x18]; 2623 u8 syndrome[0x20]; 2624 struct mlx5_ifc_lag_context_bits context; 2625 }; 2626 2627 struct mlx5_ifc_alloc_transport_domain_out_bits { 2628 u8 status[0x8]; 2629 u8 reserved_at_8[0x18]; 2630 u8 syndrome[0x20]; 2631 u8 reserved_at_40[0x8]; 2632 u8 transport_domain[0x18]; 2633 u8 reserved_at_60[0x20]; 2634 }; 2635 2636 struct mlx5_ifc_alloc_transport_domain_in_bits { 2637 u8 opcode[0x10]; 2638 u8 reserved_at_10[0x10]; 2639 u8 reserved_at_20[0x10]; 2640 u8 op_mod[0x10]; 2641 u8 reserved_at_40[0x40]; 2642 }; 2643 2644 enum { 2645 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 2646 MLX5_WQ_TYPE_CYCLIC = 0x1, 2647 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 2648 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 2649 }; 2650 2651 enum { 2652 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 2653 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 2654 }; 2655 2656 struct mlx5_ifc_wq_bits { 2657 u8 wq_type[0x4]; 2658 u8 wq_signature[0x1]; 2659 u8 end_padding_mode[0x2]; 2660 u8 cd_slave[0x1]; 2661 u8 reserved_at_8[0x18]; 2662 u8 hds_skip_first_sge[0x1]; 2663 u8 log2_hds_buf_size[0x3]; 2664 u8 reserved_at_24[0x7]; 2665 u8 page_offset[0x5]; 2666 u8 lwm[0x10]; 2667 u8 reserved_at_40[0x8]; 2668 u8 pd[0x18]; 2669 u8 reserved_at_60[0x8]; 2670 u8 uar_page[0x18]; 2671 u8 dbr_addr[0x40]; 2672 u8 hw_counter[0x20]; 2673 u8 sw_counter[0x20]; 2674 u8 reserved_at_100[0xc]; 2675 u8 log_wq_stride[0x4]; 2676 u8 reserved_at_110[0x3]; 2677 u8 log_wq_pg_sz[0x5]; 2678 u8 reserved_at_118[0x3]; 2679 u8 log_wq_sz[0x5]; 2680 u8 dbr_umem_valid[0x1]; 2681 u8 wq_umem_valid[0x1]; 2682 u8 reserved_at_122[0x1]; 2683 u8 log_hairpin_num_packets[0x5]; 2684 u8 reserved_at_128[0x3]; 2685 u8 log_hairpin_data_sz[0x5]; 2686 u8 reserved_at_130[0x4]; 2687 u8 single_wqe_log_num_of_strides[0x4]; 2688 u8 two_byte_shift_en[0x1]; 2689 u8 reserved_at_139[0x4]; 2690 u8 single_stride_log_num_of_bytes[0x3]; 2691 u8 dbr_umem_id[0x20]; 2692 u8 wq_umem_id[0x20]; 2693 u8 wq_umem_offset[0x40]; 2694 u8 reserved_at_1c0[0x440]; 2695 }; 2696 2697 enum { 2698 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2699 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2700 }; 2701 2702 enum { 2703 MLX5_RQC_STATE_RST = 0x0, 2704 MLX5_RQC_STATE_RDY = 0x1, 2705 MLX5_RQC_STATE_ERR = 0x3, 2706 }; 2707 2708 struct mlx5_ifc_rqc_bits { 2709 u8 rlky[0x1]; 2710 u8 delay_drop_en[0x1]; 2711 u8 scatter_fcs[0x1]; 2712 u8 vsd[0x1]; 2713 u8 mem_rq_type[0x4]; 2714 u8 state[0x4]; 2715 u8 reserved_at_c[0x1]; 2716 u8 flush_in_error_en[0x1]; 2717 u8 hairpin[0x1]; 2718 u8 reserved_at_f[0x6]; 2719 u8 hairpin_data_buffer_type[0x3]; 2720 u8 reserved_at_a8[0x2]; 2721 u8 ts_format[0x02]; 2722 u8 reserved_at_1c[0x4]; 2723 u8 reserved_at_20[0x8]; 2724 u8 user_index[0x18]; 2725 u8 reserved_at_40[0x8]; 2726 u8 cqn[0x18]; 2727 u8 counter_set_id[0x8]; 2728 u8 reserved_at_68[0x18]; 2729 u8 reserved_at_80[0x8]; 2730 u8 rmpn[0x18]; 2731 u8 reserved_at_a0[0x8]; 2732 u8 hairpin_peer_sq[0x18]; 2733 u8 reserved_at_c0[0x10]; 2734 u8 hairpin_peer_vhca[0x10]; 2735 u8 reserved_at_e0[0xa0]; 2736 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */ 2737 }; 2738 2739 struct mlx5_ifc_create_rq_out_bits { 2740 u8 status[0x8]; 2741 u8 reserved_at_8[0x18]; 2742 u8 syndrome[0x20]; 2743 u8 reserved_at_40[0x8]; 2744 u8 rqn[0x18]; 2745 u8 reserved_at_60[0x20]; 2746 }; 2747 2748 struct mlx5_ifc_create_rq_in_bits { 2749 u8 opcode[0x10]; 2750 u8 uid[0x10]; 2751 u8 reserved_at_20[0x10]; 2752 u8 op_mod[0x10]; 2753 u8 reserved_at_40[0xc0]; 2754 struct mlx5_ifc_rqc_bits ctx; 2755 }; 2756 2757 struct mlx5_ifc_modify_rq_out_bits { 2758 u8 status[0x8]; 2759 u8 reserved_at_8[0x18]; 2760 u8 syndrome[0x20]; 2761 u8 reserved_at_40[0x40]; 2762 }; 2763 2764 struct mlx5_ifc_query_rq_out_bits { 2765 u8 status[0x8]; 2766 u8 reserved_at_8[0x18]; 2767 u8 syndrome[0x20]; 2768 u8 reserved_at_40[0xc0]; 2769 struct mlx5_ifc_rqc_bits rq_context; 2770 }; 2771 2772 struct mlx5_ifc_query_rq_in_bits { 2773 u8 opcode[0x10]; 2774 u8 reserved_at_10[0x10]; 2775 u8 reserved_at_20[0x10]; 2776 u8 op_mod[0x10]; 2777 u8 reserved_at_40[0x8]; 2778 u8 rqn[0x18]; 2779 u8 reserved_at_60[0x20]; 2780 }; 2781 2782 enum { 2783 MLX5_RMPC_STATE_RDY = 0x1, 2784 MLX5_RMPC_STATE_ERR = 0x3, 2785 }; 2786 2787 struct mlx5_ifc_rmpc_bits { 2788 u8 reserved_at_0[0x8]; 2789 u8 state[0x4]; 2790 u8 reserved_at_c[0x14]; 2791 u8 basic_cyclic_rcv_wqe[0x1]; 2792 u8 reserved_at_21[0x1f]; 2793 u8 reserved_at_40[0x140]; 2794 struct mlx5_ifc_wq_bits wq; 2795 }; 2796 2797 struct mlx5_ifc_query_rmp_out_bits { 2798 u8 status[0x8]; 2799 u8 reserved_at_8[0x18]; 2800 u8 syndrome[0x20]; 2801 u8 reserved_at_40[0xc0]; 2802 struct mlx5_ifc_rmpc_bits rmp_context; 2803 }; 2804 2805 struct mlx5_ifc_query_rmp_in_bits { 2806 u8 opcode[0x10]; 2807 u8 reserved_at_10[0x10]; 2808 u8 reserved_at_20[0x10]; 2809 u8 op_mod[0x10]; 2810 u8 reserved_at_40[0x8]; 2811 u8 rmpn[0x18]; 2812 u8 reserved_at_60[0x20]; 2813 }; 2814 2815 struct mlx5_ifc_modify_rmp_out_bits { 2816 u8 status[0x8]; 2817 u8 reserved_at_8[0x18]; 2818 u8 syndrome[0x20]; 2819 u8 reserved_at_40[0x40]; 2820 }; 2821 2822 struct mlx5_ifc_rmp_bitmask_bits { 2823 u8 reserved_at_0[0x20]; 2824 u8 reserved_at_20[0x1f]; 2825 u8 lwm[0x1]; 2826 }; 2827 2828 struct mlx5_ifc_modify_rmp_in_bits { 2829 u8 opcode[0x10]; 2830 u8 uid[0x10]; 2831 u8 reserved_at_20[0x10]; 2832 u8 op_mod[0x10]; 2833 u8 rmp_state[0x4]; 2834 u8 reserved_at_44[0x4]; 2835 u8 rmpn[0x18]; 2836 u8 reserved_at_60[0x20]; 2837 struct mlx5_ifc_rmp_bitmask_bits bitmask; 2838 u8 reserved_at_c0[0x40]; 2839 struct mlx5_ifc_rmpc_bits ctx; 2840 }; 2841 2842 struct mlx5_ifc_create_rmp_out_bits { 2843 u8 status[0x8]; 2844 u8 reserved_at_8[0x18]; 2845 u8 syndrome[0x20]; 2846 u8 reserved_at_40[0x8]; 2847 u8 rmpn[0x18]; 2848 u8 reserved_at_60[0x20]; 2849 }; 2850 2851 struct mlx5_ifc_create_rmp_in_bits { 2852 u8 opcode[0x10]; 2853 u8 uid[0x10]; 2854 u8 reserved_at_20[0x10]; 2855 u8 op_mod[0x10]; 2856 u8 reserved_at_40[0xc0]; 2857 struct mlx5_ifc_rmpc_bits ctx; 2858 }; 2859 2860 struct mlx5_ifc_create_tis_out_bits { 2861 u8 status[0x8]; 2862 u8 reserved_at_8[0x18]; 2863 u8 syndrome[0x20]; 2864 u8 reserved_at_40[0x8]; 2865 u8 tisn[0x18]; 2866 u8 reserved_at_60[0x20]; 2867 }; 2868 2869 struct mlx5_ifc_create_tis_in_bits { 2870 u8 opcode[0x10]; 2871 u8 uid[0x10]; 2872 u8 reserved_at_20[0x10]; 2873 u8 op_mod[0x10]; 2874 u8 reserved_at_40[0xc0]; 2875 struct mlx5_ifc_tisc_bits ctx; 2876 }; 2877 2878 enum { 2879 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0, 2880 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 2881 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 2882 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 2883 }; 2884 2885 struct mlx5_ifc_modify_rq_in_bits { 2886 u8 opcode[0x10]; 2887 u8 uid[0x10]; 2888 u8 reserved_at_20[0x10]; 2889 u8 op_mod[0x10]; 2890 u8 rq_state[0x4]; 2891 u8 reserved_at_44[0x4]; 2892 u8 rqn[0x18]; 2893 u8 reserved_at_60[0x20]; 2894 u8 modify_bitmask[0x40]; 2895 u8 reserved_at_c0[0x40]; 2896 struct mlx5_ifc_rqc_bits ctx; 2897 }; 2898 2899 enum { 2900 MLX5_L3_PROT_TYPE_IPV4 = 0, 2901 MLX5_L3_PROT_TYPE_IPV6 = 1, 2902 }; 2903 2904 enum { 2905 MLX5_L4_PROT_TYPE_TCP = 0, 2906 MLX5_L4_PROT_TYPE_UDP = 1, 2907 }; 2908 2909 enum { 2910 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2911 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2912 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2913 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2914 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2915 }; 2916 2917 struct mlx5_ifc_rx_hash_field_select_bits { 2918 u8 l3_prot_type[0x1]; 2919 u8 l4_prot_type[0x1]; 2920 u8 selected_fields[0x1e]; 2921 }; 2922 2923 enum { 2924 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2925 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2926 }; 2927 2928 enum { 2929 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2930 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2931 }; 2932 2933 enum { 2934 MLX5_RX_HASH_FN_NONE = 0x0, 2935 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2936 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2937 }; 2938 2939 enum { 2940 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2941 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2942 }; 2943 2944 enum { 2945 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0, 2946 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1, 2947 }; 2948 2949 struct mlx5_ifc_tirc_bits { 2950 u8 reserved_at_0[0x20]; 2951 u8 disp_type[0x4]; 2952 u8 reserved_at_24[0x1c]; 2953 u8 reserved_at_40[0x40]; 2954 u8 reserved_at_80[0x4]; 2955 u8 lro_timeout_period_usecs[0x10]; 2956 u8 lro_enable_mask[0x4]; 2957 u8 lro_max_msg_sz[0x8]; 2958 u8 reserved_at_a0[0x40]; 2959 u8 reserved_at_e0[0x8]; 2960 u8 inline_rqn[0x18]; 2961 u8 rx_hash_symmetric[0x1]; 2962 u8 reserved_at_101[0x1]; 2963 u8 tunneled_offload_en[0x1]; 2964 u8 reserved_at_103[0x5]; 2965 u8 indirect_table[0x18]; 2966 u8 rx_hash_fn[0x4]; 2967 u8 reserved_at_124[0x2]; 2968 u8 self_lb_block[0x2]; 2969 u8 transport_domain[0x18]; 2970 u8 rx_hash_toeplitz_key[10][0x20]; 2971 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2972 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2973 u8 reserved_at_2c0[0x4c0]; 2974 }; 2975 2976 struct mlx5_ifc_create_tir_out_bits { 2977 u8 status[0x8]; 2978 u8 reserved_at_8[0x18]; 2979 u8 syndrome[0x20]; 2980 u8 reserved_at_40[0x8]; 2981 u8 tirn[0x18]; 2982 u8 reserved_at_60[0x20]; 2983 }; 2984 2985 struct mlx5_ifc_create_tir_in_bits { 2986 u8 opcode[0x10]; 2987 u8 uid[0x10]; 2988 u8 reserved_at_20[0x10]; 2989 u8 op_mod[0x10]; 2990 u8 reserved_at_40[0xc0]; 2991 struct mlx5_ifc_tirc_bits ctx; 2992 }; 2993 2994 enum { 2995 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0, 2996 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1, 2997 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2, 2998 /* bit 3 - tunneled_offload_en modify not supported. */ 2999 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4, 3000 }; 3001 3002 struct mlx5_ifc_modify_tir_out_bits { 3003 u8 status[0x8]; 3004 u8 reserved_at_8[0x18]; 3005 u8 syndrome[0x20]; 3006 u8 reserved_at_40[0x40]; 3007 }; 3008 3009 struct mlx5_ifc_modify_tir_in_bits { 3010 u8 opcode[0x10]; 3011 u8 uid[0x10]; 3012 u8 reserved_at_20[0x10]; 3013 u8 op_mod[0x10]; 3014 u8 reserved_at_40[0x8]; 3015 u8 tirn[0x18]; 3016 u8 reserved_at_60[0x20]; 3017 u8 modify_bitmask[0x40]; 3018 u8 reserved_at_c0[0x40]; 3019 struct mlx5_ifc_tirc_bits ctx; 3020 }; 3021 3022 enum { 3023 MLX5_INLINE_Q_TYPE_RQ = 0x0, 3024 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1, 3025 }; 3026 3027 struct mlx5_ifc_rq_num_bits { 3028 u8 reserved_at_0[0x8]; 3029 u8 rq_num[0x18]; 3030 }; 3031 3032 struct mlx5_ifc_rqtc_bits { 3033 u8 reserved_at_0[0xa5]; 3034 u8 list_q_type[0x3]; 3035 u8 reserved_at_a8[0x8]; 3036 u8 rqt_max_size[0x10]; 3037 u8 reserved_at_c0[0x10]; 3038 u8 rqt_actual_size[0x10]; 3039 u8 reserved_at_e0[0x6a0]; 3040 struct mlx5_ifc_rq_num_bits rq_num[]; 3041 }; 3042 3043 struct mlx5_ifc_create_rqt_out_bits { 3044 u8 status[0x8]; 3045 u8 reserved_at_8[0x18]; 3046 u8 syndrome[0x20]; 3047 u8 reserved_at_40[0x8]; 3048 u8 rqtn[0x18]; 3049 u8 reserved_at_60[0x20]; 3050 }; 3051 3052 #ifdef PEDANTIC 3053 #pragma GCC diagnostic ignored "-Wpedantic" 3054 #endif 3055 struct mlx5_ifc_create_rqt_in_bits { 3056 u8 opcode[0x10]; 3057 u8 uid[0x10]; 3058 u8 reserved_at_20[0x10]; 3059 u8 op_mod[0x10]; 3060 u8 reserved_at_40[0xc0]; 3061 struct mlx5_ifc_rqtc_bits rqt_context; 3062 }; 3063 3064 struct mlx5_ifc_modify_rqt_in_bits { 3065 u8 opcode[0x10]; 3066 u8 uid[0x10]; 3067 u8 reserved_at_20[0x10]; 3068 u8 op_mod[0x10]; 3069 u8 reserved_at_40[0x8]; 3070 u8 rqtn[0x18]; 3071 u8 reserved_at_60[0x20]; 3072 u8 modify_bitmask[0x40]; 3073 u8 reserved_at_c0[0x40]; 3074 struct mlx5_ifc_rqtc_bits rqt_context; 3075 }; 3076 #ifdef PEDANTIC 3077 #pragma GCC diagnostic error "-Wpedantic" 3078 #endif 3079 3080 struct mlx5_ifc_modify_rqt_out_bits { 3081 u8 status[0x8]; 3082 u8 reserved_at_8[0x18]; 3083 u8 syndrome[0x20]; 3084 u8 reserved_at_40[0x40]; 3085 }; 3086 3087 enum { 3088 MLX5_SQC_STATE_RST = 0x0, 3089 MLX5_SQC_STATE_RDY = 0x1, 3090 MLX5_SQC_STATE_ERR = 0x3, 3091 }; 3092 3093 enum { 3094 MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER = 0x0, 3095 MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY = 0x1, 3096 }; 3097 3098 struct mlx5_ifc_sqc_bits { 3099 u8 rlky[0x1]; 3100 u8 cd_master[0x1]; 3101 u8 fre[0x1]; 3102 u8 flush_in_error_en[0x1]; 3103 u8 allow_multi_pkt_send_wqe[0x1]; 3104 u8 min_wqe_inline_mode[0x3]; 3105 u8 state[0x4]; 3106 u8 reg_umr[0x1]; 3107 u8 allow_swp[0x1]; 3108 u8 hairpin[0x1]; 3109 u8 non_wire[0x1]; 3110 u8 static_sq_wq[0x1]; 3111 u8 reserved_at_11[0x4]; 3112 u8 hairpin_wq_buffer_type[0x3]; 3113 u8 reserved_at_18[0x2]; 3114 u8 ts_format[0x02]; 3115 u8 reserved_at_1c[0x4]; 3116 u8 reserved_at_20[0x8]; 3117 u8 user_index[0x18]; 3118 u8 reserved_at_40[0x8]; 3119 u8 cqn[0x18]; 3120 u8 reserved_at_60[0x8]; 3121 u8 hairpin_peer_rq[0x18]; 3122 u8 reserved_at_80[0x10]; 3123 u8 hairpin_peer_vhca[0x10]; 3124 u8 reserved_at_a0[0x50]; 3125 u8 packet_pacing_rate_limit_index[0x10]; 3126 u8 tis_lst_sz[0x10]; 3127 u8 reserved_at_110[0x10]; 3128 u8 reserved_at_120[0x40]; 3129 u8 reserved_at_160[0x8]; 3130 u8 tis_num_0[0x18]; 3131 struct mlx5_ifc_wq_bits wq; 3132 }; 3133 3134 struct mlx5_ifc_query_sq_in_bits { 3135 u8 opcode[0x10]; 3136 u8 reserved_at_10[0x10]; 3137 u8 reserved_at_20[0x10]; 3138 u8 op_mod[0x10]; 3139 u8 reserved_at_40[0x8]; 3140 u8 sqn[0x18]; 3141 u8 reserved_at_60[0x20]; 3142 }; 3143 3144 struct mlx5_ifc_modify_sq_out_bits { 3145 u8 status[0x8]; 3146 u8 reserved_at_8[0x18]; 3147 u8 syndrome[0x20]; 3148 u8 reserved_at_40[0x40]; 3149 }; 3150 3151 struct mlx5_ifc_modify_sq_in_bits { 3152 u8 opcode[0x10]; 3153 u8 uid[0x10]; 3154 u8 reserved_at_20[0x10]; 3155 u8 op_mod[0x10]; 3156 u8 sq_state[0x4]; 3157 u8 reserved_at_44[0x4]; 3158 u8 sqn[0x18]; 3159 u8 reserved_at_60[0x20]; 3160 u8 modify_bitmask[0x40]; 3161 u8 reserved_at_c0[0x40]; 3162 struct mlx5_ifc_sqc_bits ctx; 3163 }; 3164 3165 struct mlx5_ifc_create_sq_out_bits { 3166 u8 status[0x8]; 3167 u8 reserved_at_8[0x18]; 3168 u8 syndrome[0x20]; 3169 u8 reserved_at_40[0x8]; 3170 u8 sqn[0x18]; 3171 u8 reserved_at_60[0x20]; 3172 }; 3173 3174 struct mlx5_ifc_create_sq_in_bits { 3175 u8 opcode[0x10]; 3176 u8 uid[0x10]; 3177 u8 reserved_at_20[0x10]; 3178 u8 op_mod[0x10]; 3179 u8 reserved_at_40[0xc0]; 3180 struct mlx5_ifc_sqc_bits ctx; 3181 }; 3182 3183 enum { 3184 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0), 3185 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1), 3186 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2), 3187 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3), 3188 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4), 3189 }; 3190 3191 struct mlx5_ifc_flow_meter_parameters_bits { 3192 u8 valid[0x1]; 3193 u8 bucket_overflow[0x1]; 3194 u8 start_color[0x2]; 3195 u8 both_buckets_on_green[0x1]; 3196 u8 meter_mode[0x2]; 3197 u8 reserved_at_1[0x19]; 3198 u8 reserved_at_2[0x20]; 3199 u8 reserved_at_3[0x3]; 3200 u8 cbs_exponent[0x5]; 3201 u8 cbs_mantissa[0x8]; 3202 u8 reserved_at_4[0x3]; 3203 u8 cir_exponent[0x5]; 3204 u8 cir_mantissa[0x8]; 3205 u8 reserved_at_5[0x20]; 3206 u8 reserved_at_6[0x3]; 3207 u8 ebs_exponent[0x5]; 3208 u8 ebs_mantissa[0x8]; 3209 u8 reserved_at_7[0x3]; 3210 u8 eir_exponent[0x5]; 3211 u8 eir_mantissa[0x8]; 3212 u8 reserved_at_8[0x60]; 3213 }; 3214 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF) 3215 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8 3216 3217 enum { 3218 MLX5_METER_MODE_IP_LEN = 0x0, 3219 MLX5_METER_MODE_L2_LEN = 0x1, 3220 MLX5_METER_MODE_L2_IPG_LEN = 0x2, 3221 MLX5_METER_MODE_PKT = 0x3, 3222 }; 3223 3224 enum { 3225 MLX5_CQE_SIZE_64B = 0x0, 3226 MLX5_CQE_SIZE_128B = 0x1, 3227 }; 3228 3229 enum { 3230 MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER = 0x0, 3231 MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER = 0x1, 3232 }; 3233 3234 struct mlx5_ifc_cqc_bits { 3235 u8 status[0x4]; 3236 u8 as_notify[0x1]; 3237 u8 initiator_src_dct[0x1]; 3238 u8 dbr_umem_valid[0x1]; 3239 u8 ext_element[0x1]; 3240 u8 cqe_sz[0x3]; 3241 u8 cc[0x1]; 3242 u8 reserved_at_c[0x1]; 3243 u8 scqe_break_moderation_en[0x1]; 3244 u8 oi[0x1]; 3245 u8 cq_period_mode[0x2]; 3246 u8 cqe_comp_en[0x1]; 3247 u8 mini_cqe_res_format[0x2]; 3248 u8 st[0x4]; 3249 u8 always_armed_cq[0x1]; 3250 u8 ext_element_type[0x3]; 3251 u8 reserved_at_1c[0x2]; 3252 u8 cqe_comp_layout[0x2]; 3253 u8 dbr_umem_id[0x20]; 3254 u8 reserved_at_40[0x14]; 3255 u8 page_offset[0x6]; 3256 u8 reserved_at_5a[0x2]; 3257 u8 mini_cqe_res_format_ext[0x2]; 3258 u8 cq_timestamp_format[0x2]; 3259 u8 reserved_at_60[0x3]; 3260 u8 log_cq_size[0x5]; 3261 u8 uar_page[0x18]; 3262 u8 reserved_at_80[0x4]; 3263 u8 cq_period[0xc]; 3264 u8 cq_max_count[0x10]; 3265 u8 reserved_at_a0[0x18]; 3266 u8 c_eqn[0x8]; 3267 u8 reserved_at_c0[0x3]; 3268 u8 log_page_size[0x5]; 3269 u8 reserved_at_c8[0x18]; 3270 u8 reserved_at_e0[0x20]; 3271 u8 reserved_at_100[0x8]; 3272 u8 last_notified_index[0x18]; 3273 u8 reserved_at_120[0x8]; 3274 u8 last_solicit_index[0x18]; 3275 u8 reserved_at_140[0x8]; 3276 u8 consumer_counter[0x18]; 3277 u8 reserved_at_160[0x8]; 3278 u8 producer_counter[0x18]; 3279 u8 local_partition_id[0xc]; 3280 u8 process_id[0x14]; 3281 u8 reserved_at_1A0[0x20]; 3282 u8 dbr_addr[0x40]; 3283 }; 3284 3285 struct mlx5_ifc_health_buffer_bits { 3286 u8 reserved_0[0x100]; 3287 u8 assert_existptr[0x20]; 3288 u8 assert_callra[0x20]; 3289 u8 reserved_1[0x40]; 3290 u8 fw_version[0x20]; 3291 u8 hw_id[0x20]; 3292 u8 reserved_2[0x20]; 3293 u8 irisc_index[0x8]; 3294 u8 synd[0x8]; 3295 u8 ext_synd[0x10]; 3296 }; 3297 3298 /* HCA PCI BAR resource structure. */ 3299 struct mlx5_ifc_initial_seg_bits { 3300 u8 fw_rev_minor[0x10]; 3301 u8 fw_rev_major[0x10]; 3302 u8 cmd_interface_rev[0x10]; 3303 u8 fw_rev_subminor[0x10]; 3304 u8 reserved_0[0x40]; 3305 u8 cmdq_phy_addr_63_32[0x20]; 3306 u8 cmdq_phy_addr_31_12[0x14]; 3307 u8 reserved_1[0x2]; 3308 u8 nic_interface[0x2]; 3309 u8 log_cmdq_size[0x4]; 3310 u8 log_cmdq_stride[0x4]; 3311 u8 command_doorbell_vector[0x20]; 3312 u8 reserved_2[0xf00]; 3313 u8 initializing[0x1]; 3314 u8 nic_interface_supported[0x7]; 3315 u8 reserved_4[0x18]; 3316 struct mlx5_ifc_health_buffer_bits health_buffer; 3317 u8 no_dram_nic_offset[0x20]; 3318 u8 reserved_5[0x6de0]; 3319 u8 internal_timer_h[0x20]; 3320 u8 internal_timer_l[0x20]; 3321 u8 reserved_6[0x20]; 3322 u8 reserved_7[0x1f]; 3323 u8 clear_int[0x1]; 3324 u8 health_syndrome[0x8]; 3325 u8 health_counter[0x18]; 3326 u8 reserved_8[0x160]; 3327 u8 real_time[0x40]; 3328 u8 reserved_9[0x17e20]; 3329 }; 3330 3331 struct mlx5_ifc_create_cq_out_bits { 3332 u8 status[0x8]; 3333 u8 reserved_at_8[0x18]; 3334 u8 syndrome[0x20]; 3335 u8 reserved_at_40[0x8]; 3336 u8 cqn[0x18]; 3337 u8 reserved_at_60[0x20]; 3338 }; 3339 3340 struct mlx5_ifc_create_cq_in_bits { 3341 u8 opcode[0x10]; 3342 u8 uid[0x10]; 3343 u8 reserved_at_20[0x10]; 3344 u8 op_mod[0x10]; 3345 u8 reserved_at_40[0x40]; 3346 struct mlx5_ifc_cqc_bits cq_context; 3347 u8 cq_umem_offset[0x40]; 3348 u8 cq_umem_id[0x20]; 3349 u8 cq_umem_valid[0x1]; 3350 u8 reserved_at_2e1[0x1f]; 3351 u8 reserved_at_300[0x580]; 3352 u8 pas[]; 3353 }; 3354 3355 enum { 3356 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 3357 MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c, 3358 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, 3359 MLX5_GENERAL_OBJ_TYPE_DEFINER = 0x0018, 3360 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 3361 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d, 3362 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e, 3363 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f, 3364 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, 3365 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, 3366 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, 3367 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031, 3368 MLX5_GENERAL_OBJ_TYPE_ARG = 0x0023, 3369 MLX5_GENERAL_OBJ_TYPE_STC = 0x0040, 3370 MLX5_GENERAL_OBJ_TYPE_RTC = 0x0041, 3371 MLX5_GENERAL_OBJ_TYPE_STE = 0x0042, 3372 MLX5_GENERAL_OBJ_TYPE_MODIFY_HEADER_PATTERN = 0x0043, 3373 MLX5_GENERAL_OBJ_TYPE_FT_ALIAS = 0xff15, 3374 MLX5_GENERAL_OBJ_TYPE_TIR_ALIAS = 0xff16, 3375 }; 3376 3377 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 3378 u8 opcode[0x10]; 3379 u8 reserved_at_10[0x20]; 3380 u8 obj_type[0x10]; 3381 u8 obj_id[0x20]; 3382 union { 3383 struct { 3384 u8 alias_object[0x1]; 3385 u8 reserved_at_61[0x2]; 3386 u8 log_obj_range[0x5]; 3387 u8 reserved_at_68[0x18]; 3388 }; 3389 u8 obj_offset[0x20]; 3390 }; 3391 }; 3392 3393 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 3394 u8 status[0x8]; 3395 u8 reserved_at_8[0x18]; 3396 u8 syndrome[0x20]; 3397 u8 obj_id[0x20]; 3398 u8 reserved_at_60[0x20]; 3399 }; 3400 3401 struct mlx5_ifc_allow_other_vhca_access_in_bits { 3402 u8 opcode[0x10]; 3403 u8 uid[0x10]; 3404 u8 reserved_at_20[0x10]; 3405 u8 op_mod[0x10]; 3406 u8 reserved_at_40[0x50]; 3407 u8 object_type_to_be_accessed[0x10]; 3408 u8 object_id_to_be_accessed[0x20]; 3409 u8 reserved_at_c0[0x40]; 3410 union { 3411 u8 access_key_raw[0x100]; 3412 u8 access_key[8][0x20]; 3413 }; 3414 }; 3415 3416 struct mlx5_ifc_allow_other_vhca_access_out_bits { 3417 u8 status[0x8]; 3418 u8 reserved_at_8[0x18]; 3419 u8 syndrome[0x20]; 3420 u8 reserved_at_40[0x40]; 3421 }; 3422 3423 struct mlx5_ifc_virtio_q_counters_bits { 3424 u8 modify_field_select[0x40]; 3425 u8 reserved_at_40[0x40]; 3426 u8 received_desc[0x40]; 3427 u8 completed_desc[0x40]; 3428 u8 error_cqes[0x20]; 3429 u8 bad_desc_errors[0x20]; 3430 u8 exceed_max_chain[0x20]; 3431 u8 invalid_buffer[0x20]; 3432 u8 reserved_at_180[0x50]; 3433 }; 3434 3435 struct mlx5_ifc_geneve_tlv_option_bits { 3436 u8 modify_field_select[0x40]; 3437 u8 reserved_at_40[0x8]; 3438 u8 sample_offset[0x8]; 3439 u8 sample_id_valid[0x1]; 3440 u8 sample_offset_valid[0x1]; 3441 u8 option_class_ignore[0x1]; 3442 u8 reserved_at_53[0x5]; 3443 u8 geneve_option_fte_index[0x8]; 3444 u8 option_class[0x10]; 3445 u8 option_type[0x8]; 3446 u8 reserved_at_78[0x3]; 3447 u8 option_data_length[0x5]; 3448 u8 geneve_sample_field_id[0x20]; 3449 u8 reserved_at_a0[0x160]; 3450 }; 3451 3452 enum mlx5_ifc_rtc_update_mode { 3453 MLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH = 0x0, 3454 MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET = 0x1, 3455 }; 3456 3457 enum mlx5_ifc_rtc_access_mode { 3458 MLX5_IFC_RTC_STE_ACCESS_MODE_BY_HASH = 0x0, 3459 MLX5_IFC_RTC_STE_ACCESS_MODE_LINEAR = 0x1, 3460 }; 3461 3462 enum mlx5_ifc_rtc_ste_format { 3463 MLX5_IFC_RTC_STE_FORMAT_8DW = 0x4, 3464 MLX5_IFC_RTC_STE_FORMAT_11DW = 0x5, 3465 MLX5_IFC_RTC_STE_FORMAT_RANGE = 0x7, 3466 }; 3467 3468 enum mlx5_ifc_rtc_reparse_mode { 3469 MLX5_IFC_RTC_REPARSE_NEVER = 0x0, 3470 MLX5_IFC_RTC_REPARSE_ALWAYS = 0x1, 3471 MLX5_IFC_RTC_REPARSE_BY_STC = 0x2, 3472 }; 3473 3474 #define MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX 16 3475 3476 struct mlx5_ifc_rtc_bits { 3477 u8 modify_field_select[0x40]; 3478 u8 reserved_at_40[0x40]; 3479 u8 update_index_mode[0x2]; 3480 u8 reparse_mode[0x2]; 3481 u8 num_match_ste[0x4]; 3482 u8 pd[0x18]; 3483 u8 reserved_at_a0[0x9]; 3484 u8 access_index_mode[0x3]; 3485 u8 num_hash_definer[0x4]; 3486 u8 update_method[0x1]; 3487 u8 reserved_at_b1[0x2]; 3488 u8 log_depth[0x5]; 3489 u8 log_hash_size[0x8]; 3490 u8 ste_format_0[0x8]; 3491 u8 table_type[0x8]; 3492 u8 ste_format_1[0x8]; 3493 u8 reserved_at_d8[0x8]; 3494 u8 match_definer_0[0x20]; 3495 u8 stc_id[0x20]; 3496 u8 ste_table_base_id[0x20]; 3497 u8 ste_table_offset[0x20]; 3498 u8 reserved_at_160[0x8]; 3499 u8 miss_flow_table_id[0x18]; 3500 u8 match_definer_1[0x20]; 3501 u8 reserved_at_1a0[0x260]; 3502 }; 3503 3504 struct mlx5_ifc_alias_context_bits { 3505 u8 vhca_id_to_be_accessed[0x10]; 3506 u8 reserved_at_10[0xd]; 3507 u8 status[0x3]; 3508 u8 object_id_to_be_accessed[0x20]; 3509 u8 reserved_at_40[0x40]; 3510 union { 3511 u8 access_key_raw[0x100]; 3512 u8 access_key[8][0x20]; 3513 }; 3514 u8 metadata[0x80]; 3515 }; 3516 3517 enum mlx5_ifc_stc_action_type { 3518 MLX5_IFC_STC_ACTION_TYPE_NOP = 0x00, 3519 MLX5_IFC_STC_ACTION_TYPE_COPY = 0x05, 3520 MLX5_IFC_STC_ACTION_TYPE_SET = 0x06, 3521 MLX5_IFC_STC_ACTION_TYPE_ADD = 0x07, 3522 MLX5_IFC_STC_ACTION_TYPE_REMOVE_WORDS = 0x08, 3523 MLX5_IFC_STC_ACTION_TYPE_HEADER_REMOVE = 0x09, 3524 MLX5_IFC_STC_ACTION_TYPE_HEADER_INSERT = 0x0b, 3525 MLX5_IFC_STC_ACTION_TYPE_TAG = 0x0c, 3526 MLX5_IFC_STC_ACTION_TYPE_ACC_MODIFY_LIST = 0x0e, 3527 MLX5_IFC_STC_ACTION_TYPE_ASO = 0x12, 3528 MLX5_IFC_STC_ACTION_TYPE_COUNTER = 0x14, 3529 MLX5_IFC_STC_ACTION_TYPE_ADD_FIELD = 0x1b, 3530 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_STE_TABLE = 0x80, 3531 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_TIR = 0x81, 3532 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_FT = 0x82, 3533 MLX5_IFC_STC_ACTION_TYPE_DROP = 0x83, 3534 MLX5_IFC_STC_ACTION_TYPE_ALLOW = 0x84, 3535 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT = 0x85, 3536 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_UPLINK = 0x86, 3537 }; 3538 3539 enum mlx5_ifc_stc_reparse_mode { 3540 MLX5_IFC_STC_REPARSE_IGNORE = 0x0, 3541 MLX5_IFC_STC_REPARSE_NEVER = 0x1, 3542 MLX5_IFC_STC_REPARSE_ALWAYS = 0x2, 3543 }; 3544 3545 struct mlx5_ifc_stc_ste_param_ste_table_bits { 3546 u8 ste_obj_id[0x20]; 3547 u8 match_definer_id[0x20]; 3548 u8 reserved_at_40[0x3]; 3549 u8 log_hash_size[0x5]; 3550 u8 reserved_at_48[0x38]; 3551 }; 3552 3553 struct mlx5_ifc_stc_ste_param_tir_bits { 3554 u8 reserved_at_0[0x8]; 3555 u8 tirn[0x18]; 3556 u8 reserved_at_20[0x60]; 3557 }; 3558 3559 struct mlx5_ifc_stc_ste_param_table_bits { 3560 u8 reserved_at_0[0x8]; 3561 u8 table_id[0x18]; 3562 u8 reserved_at_20[0x60]; 3563 }; 3564 3565 struct mlx5_ifc_stc_ste_param_flow_counter_bits { 3566 u8 flow_counter_id[0x20]; 3567 }; 3568 3569 enum { 3570 MLX5_ASO_CT_NUM_PER_OBJ = 1, 3571 MLX5_ASO_METER_NUM_PER_OBJ = 2, 3572 }; 3573 3574 struct mlx5_ifc_stc_ste_param_execute_aso_bits { 3575 u8 aso_object_id[0x20]; 3576 u8 return_reg_id[0x4]; 3577 u8 aso_type[0x4]; 3578 u8 reserved_at_28[0x18]; 3579 }; 3580 3581 struct mlx5_ifc_stc_ste_param_header_modify_list_bits { 3582 u8 header_modify_pattern_id[0x20]; 3583 u8 header_modify_argument_id[0x20]; 3584 }; 3585 3586 enum mlx5_ifc_header_anchors { 3587 MLX5_HEADER_ANCHOR_PACKET_START = 0x0, 3588 MLX5_HEADER_ANCHOR_FIRST_VLAN_START = 0x2, 3589 MLX5_HEADER_ANCHOR_IPV6_IPV4 = 0x07, 3590 MLX5_HEADER_ANCHOR_TCP_UDP = 0x09, 3591 MLX5_HEADER_ANCHOR_INNER_MAC = 0x13, 3592 MLX5_HEADER_ANCHOR_INNER_IPV6_IPV4 = 0x19, 3593 }; 3594 3595 struct mlx5_ifc_stc_ste_param_remove_bits { 3596 u8 action_type[0x4]; 3597 u8 decap[0x1]; 3598 u8 reserved_at_5[0x5]; 3599 u8 remove_start_anchor[0x6]; 3600 u8 reserved_at_10[0x2]; 3601 u8 remove_end_anchor[0x6]; 3602 u8 reserved_at_18[0x8]; 3603 }; 3604 3605 struct mlx5_ifc_stc_ste_param_remove_words_bits { 3606 u8 action_type[0x4]; 3607 u8 reserved_at_4[0x6]; 3608 u8 remove_start_anchor[0x6]; 3609 u8 reserved_at_10[0x1]; 3610 u8 remove_offset[0x7]; 3611 u8 reserved_at_18[0x2]; 3612 u8 remove_size[0x6]; 3613 }; 3614 3615 struct mlx5_ifc_stc_ste_param_insert_bits { 3616 u8 action_type[0x4]; 3617 u8 encap[0x1]; 3618 u8 inline_data[0x1]; 3619 u8 reserved_at_6[0x4]; 3620 u8 insert_anchor[0x6]; 3621 u8 reserved_at_10[0x1]; 3622 u8 insert_offset[0x7]; 3623 u8 reserved_at_18[0x1]; 3624 u8 insert_size[0x7]; 3625 u8 insert_argument[0x20]; 3626 }; 3627 3628 struct mlx5_ifc_stc_ste_param_vport_bits { 3629 u8 eswitch_owner_vhca_id[0x10]; 3630 u8 vport_number[0x10]; 3631 u8 eswitch_owner_vhca_id_valid[0x1]; 3632 u8 reserved_at_21[0x59]; 3633 }; 3634 3635 union mlx5_ifc_stc_param_bits { 3636 struct mlx5_ifc_stc_ste_param_ste_table_bits ste_table; 3637 struct mlx5_ifc_stc_ste_param_tir_bits tir; 3638 struct mlx5_ifc_stc_ste_param_table_bits table; 3639 struct mlx5_ifc_stc_ste_param_flow_counter_bits counter; 3640 struct mlx5_ifc_stc_ste_param_header_modify_list_bits modify_header; 3641 struct mlx5_ifc_stc_ste_param_execute_aso_bits aso; 3642 struct mlx5_ifc_stc_ste_param_remove_bits remove_header; 3643 struct mlx5_ifc_stc_ste_param_insert_bits insert_header; 3644 struct mlx5_ifc_set_action_in_bits add; 3645 struct mlx5_ifc_set_action_in_bits set; 3646 struct mlx5_ifc_copy_action_in_bits copy; 3647 struct mlx5_ifc_stc_ste_param_vport_bits vport; 3648 u8 reserved_at_0[0x80]; 3649 }; 3650 3651 enum { 3652 MLX5_IFC_MODIFY_STC_FIELD_SELECT_NEW_STC = 1 << 0, 3653 }; 3654 3655 struct mlx5_ifc_stc_bits { 3656 u8 modify_field_select[0x40]; 3657 u8 reserved_at_40[0x46]; 3658 u8 reparse_mode[0x2]; 3659 u8 table_type[0x8]; 3660 u8 ste_action_offset[0x8]; 3661 u8 action_type[0x8]; 3662 u8 reserved_at_a0[0x60]; 3663 union mlx5_ifc_stc_param_bits stc_param; 3664 u8 reserved_at_180[0x280]; 3665 }; 3666 3667 struct mlx5_ifc_ste_bits { 3668 u8 modify_field_select[0x40]; 3669 u8 reserved_at_40[0x48]; 3670 u8 table_type[0x8]; 3671 u8 reserved_at_90[0x370]; 3672 }; 3673 3674 enum { 3675 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 3676 }; 3677 3678 struct mlx5_ifc_definer_bits { 3679 u8 modify_field_select[0x40]; 3680 u8 reserved_at_40[0x50]; 3681 u8 format_id[0x10]; 3682 u8 reserved_at_60[0x60]; 3683 u8 format_select_dw3[0x8]; 3684 u8 format_select_dw2[0x8]; 3685 u8 format_select_dw1[0x8]; 3686 u8 format_select_dw0[0x8]; 3687 u8 format_select_dw7[0x8]; 3688 u8 format_select_dw6[0x8]; 3689 u8 format_select_dw5[0x8]; 3690 u8 format_select_dw4[0x8]; 3691 u8 reserved_at_100[0x18]; 3692 u8 format_select_dw8[0x8]; 3693 u8 reserved_at_120[0x20]; 3694 u8 format_select_byte3[0x8]; 3695 u8 format_select_byte2[0x8]; 3696 u8 format_select_byte1[0x8]; 3697 u8 format_select_byte0[0x8]; 3698 u8 format_select_byte7[0x8]; 3699 u8 format_select_byte6[0x8]; 3700 u8 format_select_byte5[0x8]; 3701 u8 format_select_byte4[0x8]; 3702 u8 reserved_at_180[0x40]; 3703 u8 ctrl[0xa0]; 3704 u8 match_mask[0x160]; 3705 }; 3706 3707 struct mlx5_ifc_arg_bits { 3708 u8 rsvd0[0x88]; 3709 u8 access_pd[0x18]; 3710 }; 3711 3712 struct mlx5_ifc_header_modify_pattern_in_bits { 3713 u8 modify_field_select[0x40]; 3714 3715 u8 reserved_at_40[0x40]; 3716 3717 u8 pattern_length[0x8]; 3718 u8 reserved_at_88[0x18]; 3719 3720 u8 reserved_at_a0[0x60]; 3721 3722 u8 pattern_data[MAX_ACTIONS_DATA_IN_HEADER_MODIFY * 8]; 3723 }; 3724 3725 struct mlx5_ifc_create_virtio_q_counters_in_bits { 3726 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3727 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 3728 }; 3729 3730 struct mlx5_ifc_query_virtio_q_counters_out_bits { 3731 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3732 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 3733 }; 3734 3735 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 3736 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3737 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 3738 }; 3739 3740 struct mlx5_ifc_query_geneve_tlv_option_out_bits { 3741 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3742 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 3743 }; 3744 3745 struct mlx5_ifc_create_rtc_in_bits { 3746 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3747 struct mlx5_ifc_rtc_bits rtc; 3748 }; 3749 3750 struct mlx5_ifc_create_stc_in_bits { 3751 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3752 struct mlx5_ifc_stc_bits stc; 3753 }; 3754 3755 struct mlx5_ifc_create_ste_in_bits { 3756 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3757 struct mlx5_ifc_ste_bits ste; 3758 }; 3759 3760 struct mlx5_ifc_create_definer_in_bits { 3761 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3762 struct mlx5_ifc_definer_bits definer; 3763 }; 3764 3765 struct mlx5_ifc_create_arg_in_bits { 3766 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3767 struct mlx5_ifc_arg_bits arg; 3768 }; 3769 3770 struct mlx5_ifc_create_header_modify_pattern_in_bits { 3771 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3772 struct mlx5_ifc_header_modify_pattern_in_bits pattern; 3773 }; 3774 3775 struct mlx5_ifc_create_alias_obj_in_bits { 3776 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3777 struct mlx5_ifc_alias_context_bits alias_ctx; 3778 }; 3779 3780 struct mlx5_ifc_generate_wqe_in_bits { 3781 u8 opcode[0x10]; 3782 u8 uid[0x10]; 3783 u8 reserved_at_20[0x10]; 3784 u8 op_mode[0x10]; 3785 u8 reserved_at_40[0x40]; 3786 u8 reserved_at_80[0x8]; 3787 u8 pdn[0x18]; 3788 u8 reserved_at_a0[0x160]; 3789 u8 wqe_ctrl[0x80]; 3790 u8 wqe_gta_ctrl[0x180]; 3791 u8 wqe_gta_data_0[0x200]; 3792 u8 wqe_gta_data_1[0x200]; 3793 }; 3794 3795 struct mlx5_ifc_generate_wqe_out_bits { 3796 u8 status[0x8]; 3797 u8 reserved_at_8[0x18]; 3798 u8 syndrome[0x20]; 3799 u8 reserved_at_40[0x1c0]; 3800 u8 cqe_data[0x200]; 3801 }; 3802 3803 enum { 3804 MLX5_CRYPTO_KEY_SIZE_128b = 0x0, 3805 MLX5_CRYPTO_KEY_SIZE_256b = 0x1, 3806 }; 3807 3808 enum { 3809 MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1, 3810 MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2, 3811 MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3, 3812 MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4, 3813 MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5, 3814 MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6, 3815 }; 3816 3817 struct mlx5_ifc_dek_bits { 3818 u8 modify_field_select[0x40]; 3819 u8 state[0x8]; 3820 u8 reserved_at_48[0xc]; 3821 u8 key_size[0x4]; 3822 u8 has_keytag[0x1]; 3823 u8 reserved_at_59[0x3]; 3824 u8 key_purpose[0x4]; 3825 u8 reserved_at_60[0x8]; 3826 u8 pd[0x18]; 3827 u8 reserved_at_80[0x100]; 3828 u8 opaque[0x40]; 3829 u8 reserved_at_1c0[0x40]; 3830 u8 key[0x400]; 3831 u8 reserved_at_600[0x200]; 3832 }; 3833 3834 struct mlx5_ifc_create_dek_in_bits { 3835 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3836 struct mlx5_ifc_dek_bits dek; 3837 }; 3838 3839 struct mlx5_ifc_import_kek_bits { 3840 u8 modify_field_select[0x40]; 3841 u8 state[0x8]; 3842 u8 reserved_at_48[0xc]; 3843 u8 key_size[0x4]; 3844 u8 reserved_at_58[0x1a8]; 3845 u8 key[0x400]; 3846 u8 reserved_at_600[0x200]; 3847 }; 3848 3849 struct mlx5_ifc_create_import_kek_in_bits { 3850 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3851 struct mlx5_ifc_import_kek_bits import_kek; 3852 }; 3853 3854 enum { 3855 MLX5_CREDENTIAL_ROLE_OFFICER = 0x0, 3856 MLX5_CREDENTIAL_ROLE_USER = 0x1, 3857 }; 3858 3859 struct mlx5_ifc_credential_bits { 3860 u8 modify_field_select[0x40]; 3861 u8 state[0x8]; 3862 u8 reserved_at_48[0x10]; 3863 u8 credential_role[0x8]; 3864 u8 reserved_at_60[0x1a0]; 3865 u8 credential[0x180]; 3866 u8 reserved_at_380[0x480]; 3867 }; 3868 3869 struct mlx5_ifc_create_credential_in_bits { 3870 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3871 struct mlx5_ifc_credential_bits credential; 3872 }; 3873 3874 struct mlx5_ifc_crypto_login_bits { 3875 u8 modify_field_select[0x40]; 3876 u8 reserved_at_40[0x48]; 3877 u8 credential_pointer[0x18]; 3878 u8 reserved_at_a0[0x8]; 3879 u8 session_import_kek_ptr[0x18]; 3880 u8 reserved_at_c0[0x140]; 3881 u8 credential[0x180]; 3882 u8 reserved_at_380[0x480]; 3883 }; 3884 3885 struct mlx5_ifc_create_crypto_login_in_bits { 3886 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3887 struct mlx5_ifc_crypto_login_bits crypto_login; 3888 }; 3889 3890 enum { 3891 MLX5_VIRTQ_STATE_INIT = 0, 3892 MLX5_VIRTQ_STATE_RDY = 1, 3893 MLX5_VIRTQ_STATE_SUSPEND = 2, 3894 MLX5_VIRTQ_STATE_ERROR = 3, 3895 }; 3896 3897 enum { 3898 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0), 3899 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3), 3900 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4), 3901 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD = (1UL << 5), 3902 MLX5_VIRTQ_MODIFY_TYPE_ADDR = (1UL << 6), 3903 MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX = (1UL << 7), 3904 MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX = (1UL << 8), 3905 MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE = (1UL << 9), 3906 MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0 = (1UL << 10), 3907 MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY = (1UL << 11), 3908 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK = (1UL << 12), 3909 MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE = (1UL << 13), 3910 }; 3911 3912 struct mlx5_ifc_virtio_q_bits { 3913 u8 virtio_q_type[0x8]; 3914 u8 reserved_at_8[0x5]; 3915 u8 event_mode[0x3]; 3916 u8 queue_index[0x10]; 3917 u8 full_emulation[0x1]; 3918 u8 virtio_version_1_0[0x1]; 3919 u8 reserved_at_22[0x2]; 3920 u8 offload_type[0x4]; 3921 u8 event_qpn_or_msix[0x18]; 3922 u8 doorbell_stride_idx[0x10]; 3923 u8 queue_size[0x10]; 3924 u8 device_emulation_id[0x20]; 3925 u8 desc_addr[0x40]; 3926 u8 used_addr[0x40]; 3927 u8 available_addr[0x40]; 3928 u8 virtio_q_mkey[0x20]; 3929 u8 reserved_at_160[0x18]; 3930 u8 error_type[0x8]; 3931 u8 umem_1_id[0x20]; 3932 u8 umem_1_size[0x20]; 3933 u8 umem_1_offset[0x40]; 3934 u8 umem_2_id[0x20]; 3935 u8 umem_2_size[0x20]; 3936 u8 umem_2_offset[0x40]; 3937 u8 umem_3_id[0x20]; 3938 u8 umem_3_size[0x20]; 3939 u8 umem_3_offset[0x40]; 3940 u8 counter_set_id[0x20]; 3941 u8 reserved_at_320[0x8]; 3942 u8 pd[0x18]; 3943 u8 reserved_at_340[0x2]; 3944 u8 queue_period_mode[0x2]; 3945 u8 queue_period_us[0xc]; 3946 u8 queue_max_count[0x10]; 3947 u8 reserved_at_360[0xa0]; 3948 }; 3949 3950 struct mlx5_ifc_virtio_net_q_bits { 3951 u8 modify_field_select[0x40]; 3952 u8 reserved_at_40[0x40]; 3953 u8 tso_ipv4[0x1]; 3954 u8 tso_ipv6[0x1]; 3955 u8 tx_csum[0x1]; 3956 u8 rx_csum[0x1]; 3957 u8 reserved_at_84[0x6]; 3958 u8 dirty_bitmap_dump_enable[0x1]; 3959 u8 vhost_log_page[0x5]; 3960 u8 reserved_at_90[0xc]; 3961 u8 state[0x4]; 3962 u8 reserved_at_a0[0x8]; 3963 u8 tisn_or_qpn[0x18]; 3964 u8 dirty_bitmap_mkey[0x20]; 3965 u8 dirty_bitmap_size[0x20]; 3966 u8 dirty_bitmap_addr[0x40]; 3967 u8 hw_available_index[0x10]; 3968 u8 hw_used_index[0x10]; 3969 u8 reserved_at_160[0xa0]; 3970 struct mlx5_ifc_virtio_q_bits virtio_q_context; 3971 }; 3972 3973 struct mlx5_ifc_create_virtq_in_bits { 3974 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3975 struct mlx5_ifc_virtio_net_q_bits virtq; 3976 }; 3977 3978 struct mlx5_ifc_query_virtq_out_bits { 3979 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3980 struct mlx5_ifc_virtio_net_q_bits virtq; 3981 }; 3982 3983 struct mlx5_ifc_flow_hit_aso_bits { 3984 u8 modify_field_select[0x40]; 3985 u8 reserved_at_40[0x48]; 3986 u8 access_pd[0x18]; 3987 u8 reserved_at_a0[0x160]; 3988 u8 flag[0x200]; 3989 }; 3990 3991 struct mlx5_ifc_create_flow_hit_aso_in_bits { 3992 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3993 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso; 3994 }; 3995 3996 struct mlx5_ifc_flow_meter_aso_bits { 3997 u8 modify_field_select[0x40]; 3998 u8 reserved_at_40[0x48]; 3999 u8 access_pd[0x18]; 4000 u8 reserved_at_a0[0x160]; 4001 u8 parameters[0x200]; 4002 }; 4003 4004 struct mlx5_ifc_create_flow_meter_aso_in_bits { 4005 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4006 struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso; 4007 }; 4008 4009 struct mlx5_ifc_tcp_window_params_bits { 4010 u8 max_ack[0x20]; 4011 u8 max_win[0x20]; 4012 u8 reply_end[0x20]; 4013 u8 sent_end[0x20]; 4014 }; 4015 4016 struct mlx5_ifc_conn_track_aso_bits { 4017 struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */ 4018 struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */ 4019 u8 last_end[0x20]; /* End of DW8. */ 4020 u8 last_ack[0x20]; /* End of DW9. */ 4021 u8 last_seq[0x20]; /* End of DW10. */ 4022 u8 last_win[0x10]; 4023 u8 reserved_at_170[0xa]; 4024 u8 last_dir[0x1]; 4025 u8 last_index[0x5]; /* End of DW11. */ 4026 u8 reserved_at_180[0x40]; /* End of DW13. */ 4027 u8 reply_direction_tcp_scale[0x4]; 4028 u8 reply_direction_tcp_close_initiated[0x1]; 4029 u8 reply_direction_tcp_liberal_enabled[0x1]; 4030 u8 reply_direction_tcp_data_unacked[0x1]; 4031 u8 reply_direction_tcp_max_ack[0x1]; 4032 u8 reserved_at_1c8[0x8]; 4033 u8 original_direction_tcp_scale[0x4]; 4034 u8 original_direction_tcp_close_initiated[0x1]; 4035 u8 original_direction_tcp_liberal_enabled[0x1]; 4036 u8 original_direction_tcp_data_unacked[0x1]; 4037 u8 original_direction_tcp_max_ack[0x1]; 4038 u8 reserved_at_1d8[0x8]; /* End of DW14. */ 4039 u8 valid[0x1]; 4040 u8 state[0x3]; 4041 u8 freeze_track[0x1]; 4042 u8 reserved_at_1e5[0xb]; 4043 u8 reserved_at_1f0[0x1]; 4044 u8 connection_assured[0x1]; 4045 u8 sack_permitted[0x1]; 4046 u8 challenged_acked[0x1]; 4047 u8 heartbeat[0x1]; 4048 u8 max_ack_window[0x3]; 4049 u8 reserved_at_1f8[0x1]; 4050 u8 retransmission_counter[0x3]; 4051 u8 retranmission_limit_exceeded[0x1]; 4052 u8 retranmission_limit[0x3]; /* End of DW15. */ 4053 }; 4054 4055 struct mlx5_ifc_conn_track_offload_bits { 4056 u8 modify_field_select[0x40]; 4057 u8 reserved_at_40[0x40]; 4058 u8 reserved_at_80[0x8]; 4059 u8 conn_track_aso_access_pd[0x18]; 4060 u8 reserved_at_a0[0x160]; 4061 struct mlx5_ifc_conn_track_aso_bits conn_track_aso; 4062 }; 4063 4064 struct mlx5_ifc_create_conn_track_aso_in_bits { 4065 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4066 struct mlx5_ifc_conn_track_offload_bits conn_track_offload; 4067 }; 4068 4069 enum mlx5_access_aso_opc_mod { 4070 ASO_OPC_MOD_IPSEC = 0x0, 4071 ASO_OPC_MOD_CONNECTION_TRACKING = 0x1, 4072 ASO_OPC_MOD_POLICER = 0x2, 4073 ASO_OPC_MOD_RACE_AVOIDANCE = 0x3, 4074 ASO_OPC_MOD_FLOW_HIT = 0x4, 4075 }; 4076 4077 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30 4078 4079 enum mlx5_aso_data_mask_mode { 4080 BITWISE_64BIT = 0x0, 4081 BYTEWISE_64BYTE = 0x1, 4082 CALCULATED_64BYTE = 0x2, 4083 }; 4084 4085 #define ASO_CSEG_COND_0_OPER_OFFSET 20 4086 #define ASO_CSEG_COND_1_OPER_OFFSET 16 4087 4088 enum mlx5_aso_pre_cond_op { 4089 ASO_OP_ALWAYS_FALSE = 0x0, 4090 ASO_OP_ALWAYS_TRUE = 0x1, 4091 ASO_OP_EQUAL = 0x2, 4092 ASO_OP_NOT_EQUAL = 0x3, 4093 ASO_OP_GREATER_OR_EQUAL = 0x4, 4094 ASO_OP_LESSER_OR_EQUAL = 0x5, 4095 ASO_OP_LESSER = 0x6, 4096 ASO_OP_GREATER = 0x7, 4097 ASO_OP_CYCLIC_GREATER = 0x8, 4098 ASO_OP_CYCLIC_LESSER = 0x9, 4099 }; 4100 4101 #define ASO_CSEG_COND_OPER_OFFSET 6 4102 4103 enum mlx5_aso_op { 4104 ASO_OPER_LOGICAL_AND = 0x0, 4105 ASO_OPER_LOGICAL_OR = 0x1, 4106 }; 4107 4108 #define MLX5_ASO_CSEG_READ_ENABLE 1 4109 4110 /* ASO WQE CTRL segment. */ 4111 struct mlx5_aso_cseg { 4112 uint32_t va_h; 4113 uint32_t va_l_r; 4114 uint32_t lkey; 4115 uint32_t operand_masks; 4116 uint32_t condition_0_data; 4117 uint32_t condition_0_mask; 4118 uint32_t condition_1_data; 4119 uint32_t condition_1_mask; 4120 uint64_t bitwise_data; 4121 uint64_t data_mask; 4122 } __rte_packed; 4123 4124 #define MLX5_MTR_MAX_TOKEN_VALUE INT32_MAX 4125 4126 /* A meter data segment - 2 per ASO WQE. */ 4127 struct mlx5_aso_mtr_dseg { 4128 uint32_t v_bo_sc_bbog_mm; 4129 /* 4130 * bit 31: valid, 30: bucket overflow, 28-29: start color, 4131 * 27: both buckets on green, 24-25: meter mode. 4132 */ 4133 uint32_t reserved; 4134 uint32_t cbs_cir; 4135 /* 4136 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 4137 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 4138 */ 4139 uint32_t c_tokens; 4140 uint32_t ebs_eir; 4141 /* 4142 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 4143 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 4144 */ 4145 uint32_t e_tokens; 4146 uint64_t timestamp; 4147 } __rte_packed; 4148 4149 #define ASO_DSEG_VALID_OFFSET 31 4150 #define ASO_DSEG_BO_OFFSET 30 4151 #define ASO_DSEG_SC_OFFSET 28 4152 #define ASO_DSEG_BBOG_OFFSET 27 4153 #define ASO_DSEG_MTR_MODE 24 4154 #define ASO_DSEG_CBS_EXP_OFFSET 24 4155 #define ASO_DSEG_CBS_MAN_OFFSET 16 4156 #define ASO_DSEG_XIR_EXP_MASK 0x1F 4157 #define ASO_DSEG_XIR_EXP_OFFSET 8 4158 #define ASO_DSEG_EBS_EXP_OFFSET 24 4159 #define ASO_DSEG_EBS_MAN_OFFSET 16 4160 #define ASO_DSEG_EXP_MASK 0x1F 4161 #define ASO_DSEG_MAN_MASK 0xFF 4162 4163 #define MLX5_ASO_WQE_DSEG_SIZE 0x40 4164 #define MLX5_ASO_METERS_PER_WQE 2 4165 #define MLX5_ASO_MTRS_PER_POOL 128 4166 4167 /* ASO WQE data segment. */ 4168 struct mlx5_aso_dseg { 4169 union { 4170 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE]; 4171 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE]; 4172 }; 4173 } __rte_packed; 4174 4175 /* ASO WQE. */ 4176 struct mlx5_aso_wqe { 4177 struct mlx5_wqe_cseg general_cseg; 4178 struct mlx5_aso_cseg aso_cseg; 4179 struct mlx5_aso_dseg aso_dseg; 4180 } __rte_packed; 4181 4182 enum { 4183 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, 4184 MLX5_EVENT_TYPE_SRQ_LIMIT_REACHED = 0x14, 4185 }; 4186 4187 enum { 4188 MLX5_QP_ST_RC = 0x0, 4189 }; 4190 4191 enum { 4192 MLX5_QP_PM_MIGRATED = 0x3, 4193 }; 4194 4195 enum { 4196 MLX5_NON_ZERO_RQ = 0x0, 4197 MLX5_SRQ_RQ = 0x1, 4198 MLX5_CRQ_RQ = 0x2, 4199 MLX5_ZERO_LEN_RQ = 0x3, 4200 }; 4201 4202 struct mlx5_ifc_ads_bits { 4203 u8 fl[0x1]; 4204 u8 free_ar[0x1]; 4205 u8 reserved_at_2[0xe]; 4206 u8 pkey_index[0x10]; 4207 u8 reserved_at_20[0x8]; 4208 u8 grh[0x1]; 4209 u8 mlid[0x7]; 4210 u8 rlid[0x10]; 4211 u8 ack_timeout[0x5]; 4212 u8 reserved_at_45[0x3]; 4213 u8 src_addr_index[0x8]; 4214 u8 reserved_at_50[0x4]; 4215 u8 stat_rate[0x4]; 4216 u8 hop_limit[0x8]; 4217 u8 reserved_at_60[0x4]; 4218 u8 tclass[0x8]; 4219 u8 flow_label[0x14]; 4220 u8 rgid_rip[16][0x8]; 4221 u8 reserved_at_100[0x4]; 4222 u8 f_dscp[0x1]; 4223 u8 f_ecn[0x1]; 4224 u8 reserved_at_106[0x1]; 4225 u8 f_eth_prio[0x1]; 4226 u8 ecn[0x2]; 4227 u8 dscp[0x6]; 4228 u8 udp_sport[0x10]; 4229 u8 dei_cfi[0x1]; 4230 u8 eth_prio[0x3]; 4231 u8 sl[0x4]; 4232 u8 vhca_port_num[0x8]; 4233 u8 rmac_47_32[0x10]; 4234 u8 rmac_31_0[0x20]; 4235 }; 4236 4237 struct mlx5_ifc_qpc_bits { 4238 u8 state[0x4]; 4239 u8 lag_tx_port_affinity[0x4]; 4240 u8 st[0x8]; 4241 u8 reserved_at_10[0x3]; 4242 u8 pm_state[0x2]; 4243 u8 reserved_at_15[0x1]; 4244 u8 req_e2e_credit_mode[0x2]; 4245 u8 offload_type[0x4]; 4246 u8 end_padding_mode[0x2]; 4247 u8 reserved_at_1e[0x2]; 4248 u8 wq_signature[0x1]; 4249 u8 block_lb_mc[0x1]; 4250 u8 atomic_like_write_en[0x1]; 4251 u8 latency_sensitive[0x1]; 4252 u8 reserved_at_24[0x1]; 4253 u8 drain_sigerr[0x1]; 4254 u8 reserved_at_26[0x2]; 4255 u8 pd[0x18]; 4256 u8 mtu[0x3]; 4257 u8 log_msg_max[0x5]; 4258 u8 reserved_at_48[0x1]; 4259 u8 log_rq_size[0x4]; 4260 u8 log_rq_stride[0x3]; 4261 u8 no_sq[0x1]; 4262 u8 log_sq_size[0x4]; 4263 u8 reserved_at_55[0x3]; 4264 u8 ts_format[0x2]; 4265 u8 reserved_at_5a[0x1]; 4266 u8 rlky[0x1]; 4267 u8 ulp_stateless_offload_mode[0x4]; 4268 u8 counter_set_id[0x8]; 4269 u8 uar_page[0x18]; 4270 u8 reserved_at_80[0x8]; 4271 u8 user_index[0x18]; 4272 u8 reserved_at_a0[0x3]; 4273 u8 log_page_size[0x5]; 4274 u8 remote_qpn[0x18]; 4275 struct mlx5_ifc_ads_bits primary_address_path; 4276 struct mlx5_ifc_ads_bits secondary_address_path; 4277 u8 log_ack_req_freq[0x4]; 4278 u8 reserved_at_384[0x4]; 4279 u8 log_sra_max[0x3]; 4280 u8 reserved_at_38b[0x2]; 4281 u8 retry_count[0x3]; 4282 u8 rnr_retry[0x3]; 4283 u8 reserved_at_393[0x1]; 4284 u8 fre[0x1]; 4285 u8 cur_rnr_retry[0x3]; 4286 u8 cur_retry_count[0x3]; 4287 u8 reserved_at_39b[0x5]; 4288 u8 reserved_at_3a0[0x20]; 4289 u8 reserved_at_3c0[0x8]; 4290 u8 next_send_psn[0x18]; 4291 u8 reserved_at_3e0[0x8]; 4292 u8 cqn_snd[0x18]; 4293 u8 reserved_at_400[0x8]; 4294 u8 deth_sqpn[0x18]; 4295 u8 reserved_at_420[0x20]; 4296 u8 reserved_at_440[0x8]; 4297 u8 last_acked_psn[0x18]; 4298 u8 reserved_at_460[0x8]; 4299 u8 ssn[0x18]; 4300 u8 reserved_at_480[0x8]; 4301 u8 log_rra_max[0x3]; 4302 u8 reserved_at_48b[0x1]; 4303 u8 atomic_mode[0x4]; 4304 u8 rre[0x1]; 4305 u8 rwe[0x1]; 4306 u8 rae[0x1]; 4307 u8 reserved_at_493[0x1]; 4308 u8 page_offset[0x6]; 4309 u8 reserved_at_49a[0x3]; 4310 u8 cd_slave_receive[0x1]; 4311 u8 cd_slave_send[0x1]; 4312 u8 cd_master[0x1]; 4313 u8 reserved_at_4a0[0x3]; 4314 u8 min_rnr_nak[0x5]; 4315 u8 next_rcv_psn[0x18]; 4316 u8 reserved_at_4c0[0x8]; 4317 u8 xrcd[0x18]; 4318 u8 reserved_at_4e0[0x8]; 4319 u8 cqn_rcv[0x18]; 4320 u8 dbr_addr[0x40]; 4321 u8 q_key[0x20]; 4322 u8 reserved_at_560[0x5]; 4323 u8 rq_type[0x3]; 4324 u8 srqn_rmpn_xrqn[0x18]; 4325 u8 reserved_at_580[0x8]; 4326 u8 rmsn[0x18]; 4327 u8 hw_sq_wqebb_counter[0x10]; 4328 u8 sw_sq_wqebb_counter[0x10]; 4329 u8 hw_rq_counter[0x20]; 4330 u8 sw_rq_counter[0x20]; 4331 u8 reserved_at_600[0x20]; 4332 u8 reserved_at_620[0xf]; 4333 u8 cgs[0x1]; 4334 u8 cs_req[0x8]; 4335 u8 cs_res[0x8]; 4336 u8 dc_access_key[0x40]; 4337 u8 reserved_at_680[0x3]; 4338 u8 dbr_umem_valid[0x1]; 4339 u8 reserved_at_684[0x9c]; 4340 u8 dbr_umem_id[0x20]; 4341 }; 4342 4343 struct mlx5_ifc_create_qp_out_bits { 4344 u8 status[0x8]; 4345 u8 reserved_at_8[0x18]; 4346 u8 syndrome[0x20]; 4347 u8 reserved_at_40[0x8]; 4348 u8 qpn[0x18]; 4349 u8 reserved_at_60[0x20]; 4350 }; 4351 4352 struct mlx5_ifc_qpc_extension_bits { 4353 u8 reserved_at_0[0x2]; 4354 u8 mmo[0x1]; 4355 u8 reserved_at_3[0x5fd]; 4356 }; 4357 4358 #ifdef PEDANTIC 4359 #pragma GCC diagnostic ignored "-Wpedantic" 4360 #endif 4361 struct mlx5_ifc_qpc_pas_list_bits { 4362 u8 pas[0][0x40]; 4363 }; 4364 4365 #ifdef PEDANTIC 4366 #pragma GCC diagnostic ignored "-Wpedantic" 4367 #endif 4368 struct mlx5_ifc_qpc_extension_and_pas_list_bits { 4369 struct mlx5_ifc_qpc_extension_bits qpc_data_extension; 4370 u8 pas[][0x40]; 4371 }; 4372 4373 4374 #ifdef PEDANTIC 4375 #pragma GCC diagnostic ignored "-Wpedantic" 4376 #endif 4377 struct mlx5_ifc_create_qp_in_bits { 4378 u8 opcode[0x10]; 4379 u8 uid[0x10]; 4380 u8 reserved_at_20[0x10]; 4381 u8 op_mod[0x10]; 4382 u8 qpc_ext[0x1]; 4383 u8 reserved_at_41[0x3f]; 4384 u8 opt_param_mask[0x20]; 4385 u8 reserved_at_a0[0x20]; 4386 struct mlx5_ifc_qpc_bits qpc; 4387 u8 wq_umem_offset[0x40]; 4388 u8 wq_umem_id[0x20]; 4389 u8 wq_umem_valid[0x1]; 4390 u8 reserved_at_861[0x1f]; 4391 union { 4392 struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list; 4393 struct mlx5_ifc_qpc_extension_and_pas_list_bits 4394 qpc_extension_and_pas_list; 4395 }; 4396 }; 4397 #ifdef PEDANTIC 4398 #pragma GCC diagnostic error "-Wpedantic" 4399 #endif 4400 4401 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4402 u8 status[0x8]; 4403 u8 reserved_at_8[0x18]; 4404 u8 syndrome[0x20]; 4405 u8 reserved_at_40[0x40]; 4406 }; 4407 4408 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4409 u8 opcode[0x10]; 4410 u8 uid[0x10]; 4411 u8 reserved_at_20[0x10]; 4412 u8 op_mod[0x10]; 4413 u8 reserved_at_40[0x8]; 4414 u8 qpn[0x18]; 4415 u8 reserved_at_60[0x20]; 4416 u8 opt_param_mask[0x20]; 4417 u8 reserved_at_a0[0x20]; 4418 struct mlx5_ifc_qpc_bits qpc; 4419 u8 reserved_at_800[0x80]; 4420 }; 4421 4422 struct mlx5_ifc_sqd2rts_qp_out_bits { 4423 u8 status[0x8]; 4424 u8 reserved_at_8[0x18]; 4425 u8 syndrome[0x20]; 4426 u8 reserved_at_40[0x40]; 4427 }; 4428 4429 struct mlx5_ifc_sqd2rts_qp_in_bits { 4430 u8 opcode[0x10]; 4431 u8 uid[0x10]; 4432 u8 reserved_at_20[0x10]; 4433 u8 op_mod[0x10]; 4434 u8 reserved_at_40[0x8]; 4435 u8 qpn[0x18]; 4436 u8 reserved_at_60[0x20]; 4437 u8 opt_param_mask[0x20]; 4438 u8 reserved_at_a0[0x20]; 4439 struct mlx5_ifc_qpc_bits qpc; 4440 u8 reserved_at_800[0x80]; 4441 }; 4442 4443 struct mlx5_ifc_rts2rts_qp_out_bits { 4444 u8 status[0x8]; 4445 u8 reserved_at_8[0x18]; 4446 u8 syndrome[0x20]; 4447 u8 reserved_at_40[0x40]; 4448 }; 4449 4450 struct mlx5_ifc_rts2rts_qp_in_bits { 4451 u8 opcode[0x10]; 4452 u8 uid[0x10]; 4453 u8 reserved_at_20[0x10]; 4454 u8 op_mod[0x10]; 4455 u8 reserved_at_40[0x8]; 4456 u8 qpn[0x18]; 4457 u8 reserved_at_60[0x20]; 4458 u8 opt_param_mask[0x20]; 4459 u8 reserved_at_a0[0x20]; 4460 struct mlx5_ifc_qpc_bits qpc; 4461 u8 reserved_at_800[0x80]; 4462 }; 4463 4464 struct mlx5_ifc_rtr2rts_qp_out_bits { 4465 u8 status[0x8]; 4466 u8 reserved_at_8[0x18]; 4467 u8 syndrome[0x20]; 4468 u8 reserved_at_40[0x40]; 4469 }; 4470 4471 struct mlx5_ifc_rtr2rts_qp_in_bits { 4472 u8 opcode[0x10]; 4473 u8 uid[0x10]; 4474 u8 reserved_at_20[0x10]; 4475 u8 op_mod[0x10]; 4476 u8 reserved_at_40[0x8]; 4477 u8 qpn[0x18]; 4478 u8 reserved_at_60[0x20]; 4479 u8 opt_param_mask[0x20]; 4480 u8 reserved_at_a0[0x20]; 4481 struct mlx5_ifc_qpc_bits qpc; 4482 u8 reserved_at_800[0x80]; 4483 }; 4484 4485 struct mlx5_ifc_rst2init_qp_out_bits { 4486 u8 status[0x8]; 4487 u8 reserved_at_8[0x18]; 4488 u8 syndrome[0x20]; 4489 u8 reserved_at_40[0x40]; 4490 }; 4491 4492 struct mlx5_ifc_rst2init_qp_in_bits { 4493 u8 opcode[0x10]; 4494 u8 uid[0x10]; 4495 u8 reserved_at_20[0x10]; 4496 u8 op_mod[0x10]; 4497 u8 reserved_at_40[0x8]; 4498 u8 qpn[0x18]; 4499 u8 reserved_at_60[0x20]; 4500 u8 opt_param_mask[0x20]; 4501 u8 reserved_at_a0[0x20]; 4502 struct mlx5_ifc_qpc_bits qpc; 4503 u8 reserved_at_800[0x80]; 4504 }; 4505 4506 struct mlx5_ifc_init2rtr_qp_out_bits { 4507 u8 status[0x8]; 4508 u8 reserved_at_8[0x18]; 4509 u8 syndrome[0x20]; 4510 u8 reserved_at_40[0x40]; 4511 }; 4512 4513 struct mlx5_ifc_init2rtr_qp_in_bits { 4514 u8 opcode[0x10]; 4515 u8 uid[0x10]; 4516 u8 reserved_at_20[0x10]; 4517 u8 op_mod[0x10]; 4518 u8 reserved_at_40[0x8]; 4519 u8 qpn[0x18]; 4520 u8 reserved_at_60[0x20]; 4521 u8 opt_param_mask[0x20]; 4522 u8 reserved_at_a0[0x20]; 4523 struct mlx5_ifc_qpc_bits qpc; 4524 u8 reserved_at_800[0x80]; 4525 }; 4526 4527 struct mlx5_ifc_init2init_qp_out_bits { 4528 u8 status[0x8]; 4529 u8 reserved_at_8[0x18]; 4530 u8 syndrome[0x20]; 4531 u8 reserved_at_40[0x40]; 4532 }; 4533 4534 struct mlx5_ifc_init2init_qp_in_bits { 4535 u8 opcode[0x10]; 4536 u8 uid[0x10]; 4537 u8 reserved_at_20[0x10]; 4538 u8 op_mod[0x10]; 4539 u8 reserved_at_40[0x8]; 4540 u8 qpn[0x18]; 4541 u8 reserved_at_60[0x20]; 4542 u8 opt_param_mask[0x20]; 4543 u8 reserved_at_a0[0x20]; 4544 struct mlx5_ifc_qpc_bits qpc; 4545 u8 reserved_at_800[0x80]; 4546 }; 4547 4548 struct mlx5_ifc_2rst_qp_out_bits { 4549 u8 status[0x8]; 4550 u8 reserved_at_8[0x18]; 4551 u8 syndrome[0x20]; 4552 u8 reserved_at_40[0x40]; 4553 }; 4554 4555 struct mlx5_ifc_2rst_qp_in_bits { 4556 u8 opcode[0x10]; 4557 u8 uid[0x10]; 4558 u8 vhca_tunnel_id[0x10]; 4559 u8 op_mod[0x10]; 4560 u8 reserved_at_80[0x8]; 4561 u8 qpn[0x18]; 4562 u8 reserved_at_a0[0x20]; 4563 }; 4564 4565 struct mlx5_ifc_dealloc_pd_out_bits { 4566 u8 status[0x8]; 4567 u8 reserved_0[0x18]; 4568 u8 syndrome[0x20]; 4569 u8 reserved_1[0x40]; 4570 }; 4571 4572 struct mlx5_ifc_dealloc_pd_in_bits { 4573 u8 opcode[0x10]; 4574 u8 reserved_0[0x10]; 4575 u8 reserved_1[0x10]; 4576 u8 op_mod[0x10]; 4577 u8 reserved_2[0x8]; 4578 u8 pd[0x18]; 4579 u8 reserved_3[0x20]; 4580 }; 4581 4582 struct mlx5_ifc_alloc_pd_out_bits { 4583 u8 status[0x8]; 4584 u8 reserved_0[0x18]; 4585 u8 syndrome[0x20]; 4586 u8 reserved_1[0x8]; 4587 u8 pd[0x18]; 4588 u8 reserved_2[0x20]; 4589 }; 4590 4591 struct mlx5_ifc_alloc_pd_in_bits { 4592 u8 opcode[0x10]; 4593 u8 reserved_0[0x10]; 4594 u8 reserved_1[0x10]; 4595 u8 op_mod[0x10]; 4596 u8 reserved_2[0x40]; 4597 }; 4598 4599 #ifdef PEDANTIC 4600 #pragma GCC diagnostic ignored "-Wpedantic" 4601 #endif 4602 struct mlx5_ifc_query_qp_out_bits { 4603 u8 status[0x8]; 4604 u8 reserved_at_8[0x18]; 4605 u8 syndrome[0x20]; 4606 u8 reserved_at_40[0x40]; 4607 u8 opt_param_mask[0x20]; 4608 u8 reserved_at_a0[0x20]; 4609 struct mlx5_ifc_qpc_bits qpc; 4610 u8 reserved_at_800[0x80]; 4611 u8 pas[][0x40]; 4612 }; 4613 #ifdef PEDANTIC 4614 #pragma GCC diagnostic error "-Wpedantic" 4615 #endif 4616 4617 struct mlx5_ifc_query_qp_in_bits { 4618 u8 opcode[0x10]; 4619 u8 reserved_at_10[0x10]; 4620 u8 reserved_at_20[0x10]; 4621 u8 op_mod[0x10]; 4622 u8 reserved_at_40[0x8]; 4623 u8 qpn[0x18]; 4624 u8 reserved_at_60[0x20]; 4625 }; 4626 4627 enum { 4628 MLX5_DATA_RATE = 0x0, 4629 MLX5_WQE_RATE = 0x1, 4630 }; 4631 4632 struct mlx5_ifc_set_pp_rate_limit_context_bits { 4633 u8 rate_limit[0x20]; 4634 u8 burst_upper_bound[0x20]; 4635 u8 reserved_at_40[0xC]; 4636 u8 rate_mode[0x4]; 4637 u8 typical_packet_size[0x10]; 4638 u8 reserved_at_60[0x120]; 4639 }; 4640 4641 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u 4642 4643 #ifdef PEDANTIC 4644 #pragma GCC diagnostic ignored "-Wpedantic" 4645 #endif 4646 struct mlx5_ifc_access_register_out_bits { 4647 u8 status[0x8]; 4648 u8 reserved_at_8[0x18]; 4649 u8 syndrome[0x20]; 4650 u8 reserved_at_40[0x40]; 4651 u8 register_data[][0x20]; 4652 }; 4653 4654 struct mlx5_ifc_access_register_in_bits { 4655 u8 opcode[0x10]; 4656 u8 reserved_at_10[0x10]; 4657 u8 reserved_at_20[0x10]; 4658 u8 op_mod[0x10]; 4659 u8 reserved_at_40[0x10]; 4660 u8 register_id[0x10]; 4661 u8 argument[0x20]; 4662 u8 register_data[][0x20]; 4663 }; 4664 #ifdef PEDANTIC 4665 #pragma GCC diagnostic error "-Wpedantic" 4666 #endif 4667 4668 enum { 4669 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 4670 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 4671 }; 4672 4673 enum { 4674 MLX5_REGISTER_ID_MTUTC = 0x9055, 4675 MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002, 4676 MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, 4677 MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, 4678 MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, 4679 MLX5_QSHR_REGISTER_ID = 0x4030, 4680 }; 4681 4682 struct mlx5_ifc_register_mtutc_bits { 4683 u8 time_stamp_mode[0x2]; 4684 u8 time_stamp_state[0x2]; 4685 u8 reserved_at_4[0x18]; 4686 u8 operation[0x4]; 4687 u8 freq_adjustment[0x20]; 4688 u8 reserved_at_40[0x40]; 4689 u8 utc_sec[0x20]; 4690 u8 utc_nsec[0x20]; 4691 u8 time_adjustment[0x20]; 4692 }; 4693 4694 struct mlx5_ifc_ets_global_config_register_bits { 4695 u8 reserved_at_0[0x2]; 4696 u8 rate_limit_update[0x1]; 4697 u8 reserved_at_3[0x29]; 4698 u8 max_bw_units[0x4]; 4699 u8 reserved_at_48[0x8]; 4700 u8 max_bw_value[0x8]; 4701 }; 4702 4703 #define ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED 0x0 4704 #define ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS 0x3 4705 #define ETS_GLOBAL_CONFIG_BW_UNIT_GBPS 0x4 4706 4707 struct mlx5_ifc_register_qshr_bits { 4708 u8 reserved_at_0[0x4]; 4709 u8 connected_host[0x1]; 4710 u8 vqos[0x1]; 4711 u8 fast_response[0x1]; 4712 u8 reserved_at_7[0x1]; 4713 u8 local_port[0x8]; 4714 u8 reserved_at_16[0x230]; 4715 struct mlx5_ifc_ets_global_config_register_bits global_config; 4716 }; 4717 4718 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 4719 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 4720 4721 struct mlx5_ifc_crypto_operational_register_bits { 4722 u8 wrapped_crypto_operational[0x1]; 4723 u8 reserved_at_1[0x1b]; 4724 u8 kek_size[0x4]; 4725 u8 reserved_at_20[0x20]; 4726 u8 credential[0x140]; 4727 u8 kek[0x100]; 4728 u8 reserved_at_280[0x180]; 4729 }; 4730 4731 struct mlx5_ifc_crypto_caps_bits { 4732 u8 wrapped_crypto_operational[0x1]; 4733 u8 wrapped_crypto_going_to_commissioning[0x1]; 4734 u8 sw_wrapped_dek[0x1]; 4735 u8 synchronize_dek[0x1]; 4736 u8 int_kek_manual[0x1]; 4737 u8 int_kek_auto[0x1]; 4738 u8 reserved_at_6[0xd]; 4739 u8 sw_wrapped_dek_key_purpose[0x1]; 4740 u8 reserved_at_14[0x4]; 4741 u8 wrapped_import_method[0x8]; 4742 u8 reserved_at_20[0x3]; 4743 u8 log_dek_max_alloc[0x5]; 4744 u8 reserved_at_28[0x3]; 4745 u8 log_max_num_deks[0x5]; 4746 u8 reserved_at_30[0x3]; 4747 u8 log_max_num_import_keks[0x5]; 4748 u8 reserved_at_38[0x3]; 4749 u8 log_max_num_creds[0x5]; 4750 u8 failed_selftests[0x10]; 4751 u8 num_nv_import_keks[0x8]; 4752 u8 num_nv_credentials[0x8]; 4753 u8 reserved_at_60[0x3]; 4754 u8 log_dek_granularity[0x5]; 4755 u8 reserved_at_68[0x3]; 4756 u8 log_max_num_int_kek[0x5]; 4757 u8 sw_wrapped_dek_new[0x10]; 4758 u8 reserved_at_80[0x80]; 4759 u8 crypto_mmo_qp[0x1]; 4760 u8 crypto_aes_gcm_256_encrypt[0x1]; 4761 u8 crypto_aes_gcm_128_encrypt[0x1]; 4762 u8 crypto_aes_gcm_256_decrypt[0x1]; 4763 u8 crypto_aes_gcm_128_decrypt[0x1]; 4764 u8 gcm_auth_tag_128[0x1]; 4765 u8 gcm_auth_tag_96[0x1]; 4766 u8 reserved_at_107[0x3]; 4767 u8 log_crypto_mmo_max_size[0x6]; 4768 u8 reserved_at_110[0x10]; 4769 u8 reserved_at_120[0x6e0]; 4770 }; 4771 4772 struct mlx5_ifc_crypto_commissioning_register_bits { 4773 u8 token[0x1]; /* TODO: add size after PRM update */ 4774 }; 4775 4776 struct mlx5_ifc_import_kek_handle_register_bits { 4777 struct mlx5_ifc_crypto_login_bits crypto_login_object; 4778 struct mlx5_ifc_import_kek_bits import_kek_object; 4779 u8 reserved_at_200[0x4]; 4780 u8 write_operation[0x4]; 4781 u8 import_kek_id[0x18]; 4782 u8 reserved_at_220[0xe0]; 4783 }; 4784 4785 struct mlx5_ifc_credential_handle_register_bits { 4786 struct mlx5_ifc_crypto_login_bits crypto_login_object; 4787 struct mlx5_ifc_credential_bits credential_object; 4788 u8 reserved_at_200[0x4]; 4789 u8 write_operation[0x4]; 4790 u8 credential_id[0x18]; 4791 u8 reserved_at_220[0xe0]; 4792 }; 4793 4794 enum { 4795 MLX5_REGISTER_ADD_OPERATION = 0x1, 4796 MLX5_REGISTER_DELETE_OPERATION = 0x2, 4797 }; 4798 4799 struct mlx5_ifc_parse_graph_arc_bits { 4800 u8 start_inner_tunnel[0x1]; 4801 u8 reserved_at_1[0x7]; 4802 u8 arc_parse_graph_node[0x8]; 4803 u8 compare_condition_value[0x10]; 4804 u8 parse_graph_node_handle[0x20]; 4805 u8 reserved_at_40[0x40]; 4806 }; 4807 4808 struct mlx5_ifc_parse_graph_flow_match_sample_bits { 4809 u8 flow_match_sample_en[0x1]; 4810 u8 reserved_at_1[0x3]; 4811 u8 flow_match_sample_offset_mode[0x4]; 4812 u8 reserved_at_5[0x8]; 4813 u8 flow_match_sample_field_offset[0x10]; 4814 u8 reserved_at_32[0x4]; 4815 u8 flow_match_sample_field_offset_shift[0x4]; 4816 u8 flow_match_sample_field_base_offset[0x8]; 4817 u8 reserved_at_48[0xd]; 4818 u8 flow_match_sample_tunnel_mode[0x3]; 4819 u8 flow_match_sample_field_offset_mask[0x20]; 4820 u8 flow_match_sample_field_id[0x20]; 4821 }; 4822 4823 struct mlx5_ifc_parse_graph_flex_bits { 4824 u8 modify_field_select[0x40]; 4825 u8 reserved_at_64[0x20]; 4826 u8 header_length_base_value[0x10]; 4827 u8 reserved_at_112[0x4]; 4828 u8 header_length_field_shift[0x4]; 4829 u8 reserved_at_120[0x4]; 4830 u8 header_length_mode[0x4]; 4831 u8 header_length_field_offset[0x10]; 4832 u8 next_header_field_offset[0x10]; 4833 u8 reserved_at_160[0x12]; 4834 u8 head_anchor_id[0x6]; 4835 u8 reserved_at_178[0x3]; 4836 u8 next_header_field_size[0x5]; 4837 u8 header_length_field_mask[0x20]; 4838 u8 reserved_at_224[0x20]; 4839 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8]; 4840 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8]; 4841 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8]; 4842 }; 4843 4844 struct mlx5_ifc_create_flex_parser_in_bits { 4845 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4846 struct mlx5_ifc_parse_graph_flex_bits flex; 4847 }; 4848 4849 struct mlx5_ifc_create_flex_parser_out_bits { 4850 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4851 struct mlx5_ifc_parse_graph_flex_bits flex; 4852 }; 4853 4854 struct mlx5_ifc_parse_graph_flex_out_bits { 4855 u8 status[0x8]; 4856 u8 reserved_at_8[0x18]; 4857 u8 syndrome[0x20]; 4858 u8 reserved_at_40[0x40]; 4859 struct mlx5_ifc_parse_graph_flex_bits capability; 4860 }; 4861 4862 struct regexp_params_field_select_bits { 4863 u8 reserved_at_0[0x1d]; 4864 u8 rof_mkey[0x1]; 4865 u8 stop_engine[0x1]; 4866 u8 reserved_at_1f[0x1]; 4867 }; 4868 4869 struct mlx5_ifc_regexp_params_bits { 4870 u8 reserved_at_0[0x1f]; 4871 u8 stop_engine[0x1]; 4872 u8 reserved_at_20[0x60]; 4873 u8 rof_mkey[0x20]; 4874 u8 rof_size[0x20]; 4875 u8 rof_mkey_va[0x40]; 4876 u8 reserved_at_100[0x80]; 4877 }; 4878 4879 struct mlx5_ifc_set_regexp_params_in_bits { 4880 u8 opcode[0x10]; 4881 u8 uid[0x10]; 4882 u8 reserved_at_20[0x10]; 4883 u8 op_mod[0x10]; 4884 u8 reserved_at_40[0x18]; 4885 u8 engine_id[0x8]; 4886 struct regexp_params_field_select_bits field_select; 4887 struct mlx5_ifc_regexp_params_bits regexp_params; 4888 }; 4889 4890 struct mlx5_ifc_set_regexp_params_out_bits { 4891 u8 status[0x8]; 4892 u8 reserved_at_8[0x18]; 4893 u8 syndrome[0x20]; 4894 u8 reserved_at_18[0x40]; 4895 }; 4896 4897 struct mlx5_ifc_query_regexp_params_in_bits { 4898 u8 opcode[0x10]; 4899 u8 uid[0x10]; 4900 u8 reserved_at_20[0x10]; 4901 u8 op_mod[0x10]; 4902 u8 reserved_at_40[0x18]; 4903 u8 engine_id[0x8]; 4904 u8 reserved[0x20]; 4905 }; 4906 4907 struct mlx5_ifc_query_regexp_params_out_bits { 4908 u8 status[0x8]; 4909 u8 reserved_at_8[0x18]; 4910 u8 syndrome[0x20]; 4911 u8 reserved[0x40]; 4912 struct mlx5_ifc_regexp_params_bits regexp_params; 4913 }; 4914 4915 struct mlx5_ifc_set_regexp_register_in_bits { 4916 u8 opcode[0x10]; 4917 u8 uid[0x10]; 4918 u8 reserved_at_20[0x10]; 4919 u8 op_mod[0x10]; 4920 u8 reserved_at_40[0x18]; 4921 u8 engine_id[0x8]; 4922 u8 register_address[0x20]; 4923 u8 register_data[0x20]; 4924 u8 reserved[0x60]; 4925 }; 4926 4927 struct mlx5_ifc_set_regexp_register_out_bits { 4928 u8 status[0x8]; 4929 u8 reserved_at_8[0x18]; 4930 u8 syndrome[0x20]; 4931 u8 reserved[0x40]; 4932 }; 4933 4934 struct mlx5_ifc_query_regexp_register_in_bits { 4935 u8 opcode[0x10]; 4936 u8 uid[0x10]; 4937 u8 reserved_at_20[0x10]; 4938 u8 op_mod[0x10]; 4939 u8 reserved_at_40[0x18]; 4940 u8 engine_id[0x8]; 4941 u8 register_address[0x20]; 4942 }; 4943 4944 struct mlx5_ifc_query_regexp_register_out_bits { 4945 u8 status[0x8]; 4946 u8 reserved_at_8[0x18]; 4947 u8 syndrome[0x20]; 4948 u8 reserved[0x20]; 4949 u8 register_data[0x20]; 4950 }; 4951 4952 /* Queue counters. */ 4953 struct mlx5_ifc_alloc_q_counter_out_bits { 4954 u8 status[0x8]; 4955 u8 reserved_at_8[0x18]; 4956 u8 syndrome[0x20]; 4957 u8 reserved_at_40[0x18]; 4958 u8 counter_set_id[0x8]; 4959 u8 reserved_at_60[0x20]; 4960 }; 4961 4962 struct mlx5_ifc_alloc_q_counter_in_bits { 4963 u8 opcode[0x10]; 4964 u8 uid[0x10]; 4965 u8 reserved_at_20[0x10]; 4966 u8 op_mod[0x10]; 4967 u8 reserved_at_40[0x40]; 4968 }; 4969 4970 struct mlx5_ifc_query_q_counter_out_bits { 4971 u8 status[0x8]; 4972 u8 reserved_at_8[0x18]; 4973 u8 syndrome[0x20]; 4974 u8 reserved_at_40[0x40]; 4975 u8 rx_write_requests[0x20]; 4976 u8 reserved_at_a0[0x20]; 4977 u8 rx_read_requests[0x20]; 4978 u8 reserved_at_e0[0x20]; 4979 u8 rx_atomic_requests[0x20]; 4980 u8 reserved_at_120[0x20]; 4981 u8 rx_dct_connect[0x20]; 4982 u8 reserved_at_160[0x20]; 4983 u8 out_of_buffer[0x20]; 4984 u8 reserved_at_1a0[0x20]; 4985 u8 out_of_sequence[0x20]; 4986 u8 reserved_at_1e0[0x20]; 4987 u8 duplicate_request[0x20]; 4988 u8 reserved_at_220[0x20]; 4989 u8 rnr_nak_retry_err[0x20]; 4990 u8 reserved_at_260[0x20]; 4991 u8 packet_seq_err[0x20]; 4992 u8 reserved_at_2a0[0x20]; 4993 u8 implied_nak_seq_err[0x20]; 4994 u8 reserved_at_2e0[0x20]; 4995 u8 local_ack_timeout_err[0x20]; 4996 u8 reserved_at_320[0xa0]; 4997 u8 resp_local_length_error[0x20]; 4998 u8 req_local_length_error[0x20]; 4999 u8 resp_local_qp_error[0x20]; 5000 u8 local_operation_error[0x20]; 5001 u8 resp_local_protection[0x20]; 5002 u8 req_local_protection[0x20]; 5003 u8 resp_cqe_error[0x20]; 5004 u8 req_cqe_error[0x20]; 5005 u8 req_mw_binding[0x20]; 5006 u8 req_bad_response[0x20]; 5007 u8 req_remote_invalid_request[0x20]; 5008 u8 resp_remote_invalid_request[0x20]; 5009 u8 req_remote_access_errors[0x20]; 5010 u8 resp_remote_access_errors[0x20]; 5011 u8 req_remote_operation_errors[0x20]; 5012 u8 req_transport_retries_exceeded[0x20]; 5013 u8 cq_overflow[0x20]; 5014 u8 resp_cqe_flush_error[0x20]; 5015 u8 req_cqe_flush_error[0x20]; 5016 u8 reserved_at_620[0x1e0]; 5017 }; 5018 5019 struct mlx5_ifc_query_q_counter_in_bits { 5020 u8 opcode[0x10]; 5021 u8 uid[0x10]; 5022 u8 reserved_at_20[0x10]; 5023 u8 op_mod[0x10]; 5024 u8 reserved_at_40[0x80]; 5025 u8 clear[0x1]; 5026 u8 reserved_at_c1[0x1f]; 5027 u8 reserved_at_e0[0x18]; 5028 u8 counter_set_id[0x8]; 5029 }; 5030 5031 enum { 5032 FS_FT_NIC_RX = 0x0, 5033 FS_FT_NIC_TX = 0x1, 5034 FS_FT_FDB = 0x4, 5035 FS_FT_FDB_RX = 0xa, 5036 FS_FT_FDB_TX = 0xb, 5037 }; 5038 5039 struct mlx5_ifc_flow_table_context_bits { 5040 u8 reformat_en[0x1]; 5041 u8 decap_en[0x1]; 5042 u8 sw_owner[0x1]; 5043 u8 termination_table[0x1]; 5044 u8 table_miss_action[0x4]; 5045 u8 level[0x8]; 5046 u8 rtc_valid[0x1]; 5047 u8 reserved_at_11[0x7]; 5048 u8 log_size[0x8]; 5049 5050 u8 reserved_at_20[0x8]; 5051 u8 table_miss_id[0x18]; 5052 5053 u8 reserved_at_40[0x8]; 5054 u8 lag_master_next_table_id[0x18]; 5055 5056 u8 reserved_at_60[0x60]; 5057 5058 union { 5059 struct { 5060 u8 rtc_id_0[0x20]; 5061 u8 rtc_id_1[0x20]; 5062 u8 reserved_at_100[0x40]; 5063 }; 5064 struct { 5065 u8 sw_owner_icm_root_1[0x40]; 5066 u8 sw_owner_icm_root_0[0x40]; 5067 }; 5068 }; 5069 }; 5070 5071 struct mlx5_ifc_create_flow_table_in_bits { 5072 u8 opcode[0x10]; 5073 u8 uid[0x10]; 5074 5075 u8 reserved_at_20[0x10]; 5076 u8 op_mod[0x10]; 5077 5078 u8 other_vport[0x1]; 5079 u8 reserved_at_41[0xf]; 5080 u8 vport_number[0x10]; 5081 5082 u8 reserved_at_60[0x20]; 5083 5084 u8 table_type[0x8]; 5085 u8 reserved_at_88[0x18]; 5086 5087 u8 reserved_at_a0[0x20]; 5088 5089 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5090 }; 5091 5092 struct mlx5_ifc_create_flow_table_out_bits { 5093 u8 status[0x8]; 5094 u8 icm_address_63_40[0x18]; 5095 u8 syndrome[0x20]; 5096 u8 icm_address_39_32[0x8]; 5097 u8 table_id[0x18]; 5098 u8 icm_address_31_0[0x20]; 5099 }; 5100 5101 struct mlx5_ifc_query_flow_table_in_bits { 5102 u8 opcode[0x10]; 5103 u8 uid[0x10]; 5104 5105 u8 vhca_tunnel_id[0x10]; 5106 u8 op_mod[0x10]; 5107 5108 u8 other_vport[0x1]; 5109 u8 reserved_at_41[0xf]; 5110 u8 vport_number[0x10]; 5111 5112 u8 reserved_at_60[0x20]; 5113 5114 u8 table_type[0x8]; 5115 u8 reserved_at_88[0x18]; 5116 5117 u8 reserved_at_a0[0x8]; 5118 u8 table_id[0x18]; 5119 5120 u8 reserved_at_c0[0x140]; 5121 }; 5122 5123 struct mlx5_ifc_query_flow_table_out_bits { 5124 u8 status[0x8]; 5125 u8 reserved_at_8[0x18]; 5126 5127 u8 syndrome[0x20]; 5128 5129 u8 reserved_at_40[0x80]; 5130 5131 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5132 }; 5133 5134 enum mlx5_flow_destination_type { 5135 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 5136 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 5137 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 5138 }; 5139 5140 enum mlx5_flow_context_action { 5141 MLX5_FLOW_CONTEXT_ACTION_DROP = 1 << 1, 5142 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 1 << 2, 5143 MLX5_FLOW_CONTEXT_ACTION_REFORMAT = 1 << 4, 5144 MLX5_FLOW_CONTEXT_ACTION_DECRYPT = 1 << 12, 5145 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT = 1 << 13, 5146 }; 5147 5148 enum mlx5_flow_context_flow_source { 5149 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 5150 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 5151 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 5152 }; 5153 5154 struct mlx5_ifc_set_fte_out_bits { 5155 u8 status[0x8]; 5156 u8 reserved_at_8[0x18]; 5157 u8 syndrome[0x20]; 5158 u8 reserved_at_40[0x40]; 5159 }; 5160 5161 struct mlx5_ifc_dest_format_bits { 5162 u8 destination_type[0x8]; 5163 u8 destination_id[0x18]; 5164 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5165 u8 packet_reformat[0x1]; 5166 u8 reserved_at_22[0xe]; 5167 u8 destination_eswitch_owner_vhca_id[0x10]; 5168 }; 5169 5170 struct mlx5_ifc_flow_counter_list_bits { 5171 u8 flow_counter_id[0x20]; 5172 u8 reserved_at_20[0x20]; 5173 }; 5174 5175 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 5176 struct mlx5_ifc_dest_format_bits dest_format; 5177 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 5178 u8 reserved_at_0[0x40]; 5179 }; 5180 5181 struct mlx5_ifc_extended_dest_format_bits { 5182 struct mlx5_ifc_dest_format_bits destination_entry; 5183 5184 u8 packet_reformat_id[0x20]; 5185 5186 u8 reserved_at_60[0x20]; 5187 }; 5188 5189 #define MLX5_IFC_MULTI_PATH_FT_MAX_LEVEL 64 5190 5191 #ifdef PEDANTIC 5192 #pragma GCC diagnostic ignored "-Wpedantic" 5193 #endif 5194 struct mlx5_ifc_flow_context_bits { 5195 u8 reserved_at_00[0x20]; 5196 u8 group_id[0x20]; 5197 u8 reserved_at_40[0x8]; 5198 u8 flow_tag[0x18]; 5199 u8 reserved_at_60[0x10]; 5200 u8 action[0x10]; 5201 u8 extended_destination[0x1]; 5202 u8 reserved_at_81[0x1]; 5203 u8 flow_source[0x2]; 5204 u8 encrypt_decrypt_type[0x4]; 5205 u8 destination_list_size[0x18]; 5206 u8 reserved_at_a0[0x8]; 5207 u8 flow_counter_list_size[0x18]; 5208 u8 packet_reformat_id[0x20]; 5209 u8 reserved_at_e0[0x40]; 5210 u8 encrypt_decrypt_obj_id[0x20]; 5211 u8 reserved_at_140[0x16c0]; 5212 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 5213 }; 5214 5215 struct mlx5_ifc_set_fte_in_bits { 5216 u8 opcode[0x10]; 5217 u8 reserved_at_10[0x10]; 5218 u8 reserved_at_20[0x10]; 5219 u8 op_mod[0x10]; 5220 u8 other_vport[0x1]; 5221 u8 reserved_at_41[0xf]; 5222 u8 vport_number[0x10]; 5223 u8 reserved_at_60[0x20]; 5224 u8 table_type[0x8]; 5225 u8 reserved_at_88[0x18]; 5226 u8 reserved_at_a0[0x8]; 5227 u8 table_id[0x18]; 5228 u8 ignore_flow_level[0x1]; 5229 u8 reserved_at_c1[0x17]; 5230 u8 modify_enable_mask[0x8]; 5231 u8 reserved_at_e0[0x20]; 5232 u8 flow_index[0x20]; 5233 u8 reserved_at_120[0xe0]; 5234 struct mlx5_ifc_flow_context_bits flow_context; 5235 }; 5236 5237 struct mlx5_ifc_create_flow_group_in_bits { 5238 u8 opcode[0x10]; 5239 u8 reserved_at_10[0x10]; 5240 u8 reserved_at_20[0x20]; 5241 u8 other_vport[0x1]; 5242 u8 reserved_at_41[0xf]; 5243 u8 vport_number[0x10]; 5244 u8 reserved_at_60[0x20]; 5245 u8 table_type[0x8]; 5246 u8 reserved_at_88[0x18]; 5247 u8 reserved_at_a0[0x8]; 5248 u8 table_id[0x18]; 5249 u8 reserved_at_c0[0x1f40]; 5250 }; 5251 5252 struct mlx5_ifc_create_flow_group_out_bits { 5253 u8 status[0x8]; 5254 u8 reserved_at_8[0x18]; 5255 u8 syndrome[0x20]; 5256 u8 reserved_at_40[0x8]; 5257 u8 group_id[0x18]; 5258 u8 reserved_at_60[0x20]; 5259 }; 5260 5261 enum { 5262 MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION = 1 << 0, 5263 MLX5_IFC_MODIFY_FLOW_TABLE_RTC_ID = 1 << 1, 5264 }; 5265 5266 enum { 5267 MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_DEFAULT = 0, 5268 MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_GOTO_TBL = 1, 5269 }; 5270 5271 struct mlx5_ifc_modify_flow_table_in_bits { 5272 u8 opcode[0x10]; 5273 u8 uid[0x10]; 5274 5275 u8 reserved_at_20[0x10]; 5276 u8 op_mod[0x10]; 5277 5278 u8 reserved_at_40[0x10]; 5279 u8 vport_number[0x10]; 5280 5281 u8 reserved_at_60[0x10]; 5282 u8 modify_field_select[0x10]; 5283 5284 u8 table_type[0x8]; 5285 u8 reserved_at_88[0x18]; 5286 5287 u8 reserved_at_a0[0x8]; 5288 u8 table_id[0x18]; 5289 5290 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5291 }; 5292 5293 struct mlx5_ifc_modify_flow_table_out_bits { 5294 u8 status[0x8]; 5295 u8 reserved_at_8[0x18]; 5296 5297 u8 syndrome[0x20]; 5298 5299 u8 reserved_at_40[0x60]; 5300 }; 5301 5302 struct mlx5_ifc_packet_reformat_context_in_bits { 5303 u8 reformat_type[0x8]; 5304 u8 reserved_at_8[0x4]; 5305 u8 reformat_param_0[0x4]; 5306 u8 reserved_at_16[0x6]; 5307 u8 reformat_data_size[0xa]; 5308 5309 u8 reformat_param_1[0x8]; 5310 u8 reserved_at_40[0x8]; 5311 u8 reformat_data[6][0x8]; 5312 5313 u8 more_reformat_data[][0x8]; 5314 }; 5315 5316 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5317 u8 opcode[0x10]; 5318 u8 uid[0x10]; 5319 5320 u8 reserved_at_20[0x10]; 5321 u8 op_mod[0x10]; 5322 5323 u8 reserved_at_40[0xa0]; 5324 5325 u8 packet_reformat_context[]; 5326 }; 5327 5328 struct mlx5_ifc_alloc_packet_reformat_out_bits { 5329 u8 status[0x8]; 5330 u8 reserved_at_8[0x18]; 5331 5332 u8 syndrome[0x20]; 5333 5334 u8 packet_reformat_id[0x20]; 5335 5336 u8 reserved_at_60[0x20]; 5337 }; 5338 5339 /* CQE format mask. */ 5340 #define MLX5E_CQE_FORMAT_MASK 0xc 5341 5342 /* MPW opcode. */ 5343 #define MLX5_OPC_MOD_MPW 0x01 5344 5345 /* Compressed Rx CQE structure. */ 5346 struct mlx5_mini_cqe8 { 5347 union { 5348 uint32_t rx_hash_result; 5349 struct { 5350 union { 5351 uint16_t checksum; 5352 uint16_t flow_tag_high; 5353 struct { 5354 uint8_t reserved; 5355 uint8_t hdr_type; 5356 }; 5357 }; 5358 uint16_t stride_idx; 5359 }; 5360 struct { 5361 uint16_t wqe_counter; 5362 uint8_t validity_iteration_count; 5363 uint8_t s_wqe_opcode; 5364 } s_wqe_info; 5365 }; 5366 union { 5367 uint32_t byte_cnt_flow; 5368 uint32_t byte_cnt; 5369 }; 5370 }; 5371 5372 /* Mini CQE responder format. */ 5373 enum { 5374 MLX5_CQE_RESP_FORMAT_HASH = 0x0, 5375 MLX5_CQE_RESP_FORMAT_CSUM = 0x1, 5376 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2, 5377 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3, 5378 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4, 5379 }; 5380 5381 /* srTCM PRM flow meter parameters. */ 5382 enum { 5383 MLX5_FLOW_COLOR_RED = 0, 5384 MLX5_FLOW_COLOR_YELLOW, 5385 MLX5_FLOW_COLOR_GREEN, 5386 MLX5_FLOW_COLOR_UNDEFINED, 5387 }; 5388 5389 /* Maximum value of srTCM & trTCM metering parameters. */ 5390 #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F)) 5391 #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF) 5392 5393 /* The bits meter color use. */ 5394 #define MLX5_MTR_COLOR_BITS 8 5395 5396 /* The bit size of one register. */ 5397 #define MLX5_REG_BITS 32 5398 5399 /* Idle bits for non-color usage in color register. */ 5400 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS) 5401 5402 /* Length mode of dynamic flex parser graph node. */ 5403 enum mlx5_parse_graph_node_len_mode { 5404 MLX5_GRAPH_NODE_LEN_FIXED = 0x0, 5405 MLX5_GRAPH_NODE_LEN_FIELD = 0x1, 5406 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2, 5407 }; 5408 5409 /* Offset mode of the samples of flex parser. */ 5410 enum mlx5_parse_graph_flow_match_sample_offset_mode { 5411 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0, 5412 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1, 5413 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, 5414 }; 5415 5416 enum mlx5_parse_graph_flow_match_sample_tunnel_mode { 5417 MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0, 5418 MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1, 5419 MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2 5420 }; 5421 5422 /* Node index for an input / output arc of the flex parser graph. */ 5423 enum mlx5_parse_graph_arc_node_index { 5424 MLX5_GRAPH_ARC_NODE_NULL = 0x0, 5425 MLX5_GRAPH_ARC_NODE_HEAD = 0x1, 5426 MLX5_GRAPH_ARC_NODE_MAC = 0x2, 5427 MLX5_GRAPH_ARC_NODE_IP = 0x3, 5428 MLX5_GRAPH_ARC_NODE_GRE = 0x4, 5429 MLX5_GRAPH_ARC_NODE_UDP = 0x5, 5430 MLX5_GRAPH_ARC_NODE_MPLS = 0x6, 5431 MLX5_GRAPH_ARC_NODE_TCP = 0x7, 5432 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, 5433 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, 5434 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, 5435 MLX5_GRAPH_ARC_NODE_IPV4 = 0xb, 5436 MLX5_GRAPH_ARC_NODE_IPV6 = 0xc, 5437 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, 5438 }; 5439 5440 enum mlx5_packet_reformat_context_reformat_type { 5441 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5442 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5443 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 5444 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 5445 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 5446 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 5447 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 5448 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xA, 5449 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xB, 5450 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xC, 5451 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_ADD_NISP_TNL = 0xD, 5452 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_REMOVE_NISP_TNL = 0xE, 5453 }; 5454 5455 #define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8 5456 #define MLX5_PARSE_GRAPH_IN_ARC_MAX 8 5457 #define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8 5458 5459 /** 5460 * Convert a user mark to flow mark. 5461 * 5462 * @param val 5463 * Mark value to convert. 5464 * 5465 * @return 5466 * Converted mark value. 5467 */ 5468 static inline uint32_t 5469 mlx5_flow_mark_set(uint32_t val) 5470 { 5471 uint32_t ret; 5472 5473 /* 5474 * Add one to the user value to differentiate un-marked flows from 5475 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it 5476 * remains untouched. 5477 */ 5478 if (val != MLX5_FLOW_MARK_DEFAULT) 5479 ++val; 5480 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 5481 /* 5482 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit 5483 * word, byte-swapped by the kernel on little-endian systems. In this 5484 * case, left-shifting the resulting big-endian value ensures the 5485 * least significant 24 bits are retained when converting it back. 5486 */ 5487 ret = rte_cpu_to_be_32(val) >> 8; 5488 #else 5489 ret = val; 5490 #endif 5491 return ret; 5492 } 5493 5494 /** 5495 * Convert a mark to user mark. 5496 * 5497 * @param val 5498 * Mark value to convert. 5499 * 5500 * @return 5501 * Converted mark value. 5502 */ 5503 static inline uint32_t 5504 mlx5_flow_mark_get(uint32_t val) 5505 { 5506 /* 5507 * Subtract one from the retrieved value. It was added by 5508 * mlx5_flow_mark_set() to distinguish unmarked flows. 5509 */ 5510 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 5511 return (val >> 8) - 1; 5512 #else 5513 return val - 1; 5514 #endif 5515 } 5516 5517 /** 5518 * Convert a timestamp format to configure settings in the queue context. 5519 * 5520 * @param val 5521 * timestamp format supported by the queue. 5522 * 5523 * @return 5524 * Converted timestamp format settings. 5525 */ 5526 static inline uint32_t 5527 mlx5_ts_format_conv(uint32_t ts_format) 5528 { 5529 return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ? 5530 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : 5531 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; 5532 } 5533 5534 #endif /* RTE_PMD_MLX5_PRM_H_ */ 5535