1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_PRM_H_ 7 #define RTE_PMD_MLX5_PRM_H_ 8 9 #include <unistd.h> 10 11 #include <rte_vect.h> 12 #include <rte_byteorder.h> 13 14 #include <mlx5_glue.h> 15 #include "mlx5_autoconf.h" 16 17 /* RSS hash key size. */ 18 #define MLX5_RSS_HASH_KEY_LEN 40 19 20 /* Get CQE owner bit. */ 21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK) 22 23 /* Get CQE format. */ 24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2) 25 26 /* Get CQE opcode. */ 27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4) 28 29 /* Get CQE number of mini CQEs. */ 30 #define MLX5_CQE_NUM_MINIS(op_own) (((op_own) & 0xf0) >> 4) 31 32 /* Get CQE solicited event. */ 33 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1) 34 35 /* Invalidate a CQE. */ 36 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4) 37 38 /* Initialize CQE validity iteration count. */ 39 #define MLX5_CQE_VIC_INIT 0xffu 40 41 /* Hardware index widths. */ 42 #define MLX5_CQ_INDEX_WIDTH 24 43 #define MLX5_WQ_INDEX_WIDTH 16 44 45 /* WQE Segment sizes in bytes. */ 46 #define MLX5_WSEG_SIZE 16u 47 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg) 48 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg) 49 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg) 50 51 /* WQE/WQEBB size in bytes. */ 52 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe) 53 54 /* 55 * Max size of a WQE session. 56 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments, 57 * the WQE size field in Control Segment is 6 bits wide. 58 */ 59 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE) 60 61 /* 62 * Default minimum number of Tx queues for inlining packets. 63 * If there are less queues as specified we assume we have 64 * no enough CPU resources (cycles) to perform inlining, 65 * the PCIe throughput is not supposed as bottleneck and 66 * inlining is disabled. 67 */ 68 #define MLX5_INLINE_MAX_TXQS 8u 69 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u 70 71 /* 72 * Default packet length threshold to be inlined with 73 * enhanced MPW. If packet length exceeds the threshold 74 * the data are not inlined. Should be aligned in WQEBB 75 * boundary with accounting the title Control and Ethernet 76 * segments. 77 */ 78 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \ 79 MLX5_DSEG_MIN_INLINE_SIZE) 80 /* 81 * Maximal inline data length sent with enhanced MPW. 82 * Is based on maximal WQE size. 83 */ 84 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 85 MLX5_WQE_CSEG_SIZE - \ 86 MLX5_WQE_ESEG_SIZE - \ 87 MLX5_WQE_DSEG_SIZE + \ 88 MLX5_DSEG_MIN_INLINE_SIZE) 89 /* 90 * Minimal amount of packets to be sent with EMPW. 91 * This limits the minimal required size of sent EMPW. 92 * If there are no enough resources to built minimal 93 * EMPW the sending loop exits. 94 */ 95 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u) 96 /* 97 * Maximal amount of packets to be sent with EMPW. 98 * This value is not recommended to exceed MLX5_TX_COMP_THRESH, 99 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs 100 * without CQE generation request, being multiplied by 101 * MLX5_TX_COMP_MAX_CQE it may cause significant latency 102 * in tx burst routine at the moment of freeing multiple mbufs. 103 */ 104 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH 105 #define MLX5_MPW_MAX_PACKETS 6 106 #define MLX5_MPW_INLINE_MAX_PACKETS 6 107 108 /* 109 * Default packet length threshold to be inlined with 110 * ordinary SEND. Inlining saves the MR key search 111 * and extra PCIe data fetch transaction, but eats the 112 * CPU cycles. 113 */ 114 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \ 115 MLX5_ESEG_MIN_INLINE_SIZE - \ 116 MLX5_WQE_CSEG_SIZE - \ 117 MLX5_WQE_ESEG_SIZE - \ 118 MLX5_WQE_DSEG_SIZE) 119 /* 120 * Maximal inline data length sent with ordinary SEND. 121 * Is based on maximal WQE size. 122 */ 123 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 124 MLX5_WQE_CSEG_SIZE - \ 125 MLX5_WQE_ESEG_SIZE - \ 126 MLX5_WQE_DSEG_SIZE + \ 127 MLX5_ESEG_MIN_INLINE_SIZE) 128 129 /* Missed in mlx5dv.h, should define here. */ 130 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW 131 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u 132 #endif 133 134 #ifndef HAVE_MLX5_OPCODE_SEND_EN 135 #define MLX5_OPCODE_SEND_EN 0x17u 136 #endif 137 138 #ifndef HAVE_MLX5_OPCODE_WAIT 139 #define MLX5_OPCODE_WAIT 0x0fu 140 #endif 141 142 #define MLX5_OPC_MOD_WAIT_CQ_PI 0u 143 #define MLX5_OPC_MOD_WAIT_DATA 1u 144 #define MLX5_OPC_MOD_WAIT_TIME 2u 145 146 147 #define MLX5_WAIT_COND_INVERT 0x10u 148 #define MLX5_WAIT_COND_ALWAYS_TRUE 0u 149 #define MLX5_WAIT_COND_EQUAL 1u 150 #define MLX5_WAIT_COND_BIGGER 2u 151 #define MLX5_WAIT_COND_SMALLER 3u 152 #define MLX5_WAIT_COND_CYCLIC_BIGGER 4u 153 #define MLX5_WAIT_COND_CYCLIC_SMALLER 5u 154 155 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO 156 #define MLX5_OPCODE_ACCESS_ASO 0x2du 157 #endif 158 159 /* CQE value to inform that VLAN is stripped. */ 160 #define MLX5_CQE_VLAN_STRIPPED (1u << 0) 161 162 /* IPv4 options. */ 163 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1) 164 165 /* IPv6 packet. */ 166 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2) 167 168 /* IPv4 packet. */ 169 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3) 170 171 /* TCP packet. */ 172 #define MLX5_CQE_RX_TCP_PACKET (1u << 4) 173 174 /* UDP packet. */ 175 #define MLX5_CQE_RX_UDP_PACKET (1u << 5) 176 177 /* IP is fragmented. */ 178 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7) 179 180 /* L2 header is valid. */ 181 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8) 182 183 /* L3 header is valid. */ 184 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9) 185 186 /* L4 header is valid. */ 187 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10) 188 189 /* Outer packet, 0 IPv4, 1 IPv6. */ 190 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1) 191 192 /* Tunnel packet bit in the CQE. */ 193 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0) 194 195 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */ 196 #define MLX5_CQE_LRO_PUSH_MASK 0x40 197 198 /* Mask for L4 type in the CQE hdr_type_etc field. */ 199 #define MLX5_CQE_L4_TYPE_MASK 0x70 200 201 /* The bit index of L4 type in CQE hdr_type_etc field. */ 202 #define MLX5_CQE_L4_TYPE_SHIFT 0x4 203 204 /* L4 type to indicate TCP packet without acknowledgment. */ 205 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3 206 207 /* L4 type to indicate TCP packet with acknowledgment. */ 208 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4 209 210 /* Inner L3 checksum offload (Tunneled packets only). */ 211 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4) 212 213 /* Inner L4 checksum offload (Tunneled packets only). */ 214 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5) 215 216 /* Outer L4 type is TCP. */ 217 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5) 218 219 /* Outer L4 type is UDP. */ 220 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5) 221 222 /* Outer L3 type is IPV4. */ 223 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4) 224 225 /* Outer L3 type is IPV6. */ 226 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4) 227 228 /* Inner L4 type is TCP. */ 229 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1) 230 231 /* Inner L4 type is UDP. */ 232 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1) 233 234 /* Inner L3 type is IPV4. */ 235 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0) 236 237 /* Inner L3 type is IPV6. */ 238 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0) 239 240 /* VLAN insertion flag. */ 241 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31) 242 243 /* Data inline segment flag. */ 244 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31) 245 246 /* Is flow mark valid. */ 247 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 248 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00) 249 #else 250 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff) 251 #endif 252 253 /* INVALID is used by packets matching no flow rules. */ 254 #define MLX5_FLOW_MARK_INVALID 0 255 256 /* Maximum allowed value to mark a packet. */ 257 #define MLX5_FLOW_MARK_MAX 0xfffff0 258 259 /* Default mark value used when none is provided. */ 260 #define MLX5_FLOW_MARK_DEFAULT 0xffffff 261 262 /* Default mark mask for metadata legacy mode. */ 263 #define MLX5_FLOW_MARK_MASK 0xffffff 264 265 /* Byte length mask when mark is enable in miniCQE */ 266 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00 267 268 /* Maximum number of DS in WQE. Limited by 6-bit field. */ 269 #define MLX5_DSEG_MAX 63 270 271 /* The 32 bit syndrome offset in struct mlx5_error_cqe. */ 272 #if (RTE_CACHE_LINE_SIZE == 128) 273 #define MLX5_ERROR_CQE_SYNDROME_OFFSET 116 274 #else 275 #define MLX5_ERROR_CQE_SYNDROME_OFFSET 52 276 #endif 277 278 /* The completion mode offset in the WQE control segment line 2. */ 279 #define MLX5_COMP_MODE_OFFSET 2 280 281 /* Amount of data bytes in minimal inline data segment. */ 282 #define MLX5_DSEG_MIN_INLINE_SIZE 12u 283 284 /* Amount of data bytes in minimal inline eth segment. */ 285 #define MLX5_ESEG_MIN_INLINE_SIZE 18u 286 287 /* Amount of data bytes after eth data segment. */ 288 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u 289 290 /* The maximum log value of segments per RQ WQE. */ 291 #define MLX5_MAX_LOG_RQ_SEGS 5u 292 293 /* Log 2 of the default size of a WQE for Multi-Packet RQ. */ 294 #define MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE 14U 295 296 /* The alignment needed for WQ buffer. */ 297 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size() 298 299 /* The alignment needed for CQ buffer. */ 300 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size() 301 302 #define MAX_ACTIONS_DATA_IN_HEADER_MODIFY 512 303 304 /* Alias FT id passed to the ALLOW_OTHER_VHCA_ACCESS & CREATE_GENERAL_OBJECT 305 * commands should have the following format: 306 * {table_type: 8bits, table_id: 24bits}. 307 */ 308 #define FT_ID_FT_TYPE_OFFSET 24 309 310 /* Completion mode. */ 311 enum mlx5_completion_mode { 312 MLX5_COMP_ONLY_ERR = 0x0, 313 MLX5_COMP_ONLY_FIRST_ERR = 0x1, 314 MLX5_COMP_ALWAYS = 0x2, 315 MLX5_COMP_CQE_AND_EQE = 0x3, 316 }; 317 318 /* MPW mode. */ 319 enum mlx5_mpw_mode { 320 MLX5_MPW_DISABLED, 321 MLX5_MPW, 322 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */ 323 }; 324 325 /* WQE Control segment. */ 326 struct __rte_aligned(MLX5_WSEG_SIZE) __rte_packed_begin mlx5_wqe_cseg { 327 uint32_t opcode; 328 uint32_t sq_ds; 329 uint32_t flags; 330 uint32_t misc; 331 } __rte_packed_end; 332 333 /* 334 * WQE CSEG opcode field size is 32 bits, divided: 335 * Bits 31:24 OPC_MOD 336 * Bits 23:8 wqe_index 337 * Bits 7:0 OPCODE 338 */ 339 #define WQE_CSEG_OPC_MOD_OFFSET 24 340 #define WQE_CSEG_WQE_INDEX_OFFSET 8 341 342 /* Header of data segment. Minimal size Data Segment */ 343 struct __rte_packed_begin mlx5_wqe_dseg { 344 uint32_t bcount; 345 union { 346 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE]; 347 struct __rte_packed_begin { 348 uint32_t lkey; 349 uint64_t pbuf; 350 } __rte_packed_end; 351 }; 352 } __rte_packed_end; 353 354 /* Subset of struct WQE Ethernet Segment. */ 355 struct __rte_packed_begin mlx5_wqe_eseg { 356 union { 357 struct __rte_packed_begin { 358 uint32_t swp_offs; 359 uint8_t cs_flags; 360 uint8_t swp_flags; 361 uint16_t mss; 362 uint32_t metadata; 363 uint16_t inline_hdr_sz; 364 union { 365 uint16_t inline_data; 366 uint16_t vlan_tag; 367 }; 368 } __rte_packed_end; 369 struct __rte_packed_begin { 370 uint32_t offsets; 371 uint32_t flags; 372 uint32_t flow_metadata; 373 uint32_t inline_hdr; 374 } __rte_packed_end; 375 }; 376 } __rte_packed_end; 377 378 struct __rte_packed_begin mlx5_wqe_qseg { 379 uint32_t reserved0; 380 uint32_t reserved1; 381 uint32_t max_index; 382 uint32_t qpn_cqn; 383 } __rte_packed_end; 384 385 struct __rte_packed_begin mlx5_wqe_wseg { 386 uint32_t operation; 387 uint32_t lkey; 388 uint32_t va_high; 389 uint32_t va_low; 390 uint64_t value; 391 uint64_t mask; 392 } __rte_packed_end; 393 394 /* The title WQEBB, header of WQE. */ 395 struct __rte_packed_begin mlx5_wqe { 396 union { 397 struct mlx5_wqe_cseg cseg; 398 uint32_t ctrl[4]; 399 }; 400 struct mlx5_wqe_eseg eseg; 401 union { 402 struct mlx5_wqe_dseg dseg[2]; 403 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE]; 404 }; 405 } __rte_packed_end; 406 407 /* WQE for Multi-Packet RQ. */ 408 struct mlx5_wqe_mprq { 409 struct mlx5_wqe_srq_next_seg next_seg; 410 struct mlx5_wqe_data_seg dseg; 411 }; 412 413 #define MLX5_MPRQ_LEN_MASK 0x000ffff 414 #define MLX5_MPRQ_LEN_SHIFT 0 415 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000 416 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16 417 #define MLX5_MPRQ_FILLER_MASK 0x80000000 418 #define MLX5_MPRQ_FILLER_SHIFT 31 419 420 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2 421 422 struct mlx5_error_cqe { 423 #if (RTE_CACHE_LINE_SIZE == 128) 424 uint8_t padding[64]; 425 #endif 426 uint8_t rsvd0[2]; 427 uint16_t eth_wqe_id; 428 uint8_t rsvd1[16]; 429 uint16_t ib_stride_index; 430 uint8_t rsvd2[10]; 431 uint32_t srqn; 432 uint8_t rsvd3[8]; 433 uint32_t byte_cnt; 434 uint8_t rsvd4[4]; 435 uint8_t hw_err_synd; 436 uint8_t hw_synd_type; 437 uint8_t vendor_err_synd; 438 uint8_t syndrome; 439 uint32_t s_wqe_opcode_qpn; 440 uint16_t wqe_counter; 441 uint8_t signature; 442 uint8_t op_own; 443 }; 444 445 /* CQ element structure - should be equal to the cache line size */ 446 struct mlx5_cqe { 447 #if (RTE_CACHE_LINE_SIZE == 128) 448 uint8_t padding[64]; 449 #endif 450 uint8_t pkt_info; 451 uint8_t rsvd0; 452 uint16_t wqe_id; 453 uint8_t lro_tcppsh_abort_dupack; 454 uint8_t lro_min_ttl; 455 uint16_t lro_tcp_win; 456 uint32_t lro_ack_seq_num; 457 uint32_t rx_hash_res; 458 uint8_t rx_hash_type; 459 uint8_t rsvd1[3]; 460 uint16_t csum; 461 uint8_t rsvd2[6]; 462 uint16_t hdr_type_etc; 463 uint16_t vlan_info; 464 uint8_t lro_num_seg; 465 union { 466 uint8_t user_index_bytes[3]; 467 struct __rte_packed_begin { 468 uint8_t user_index_hi; 469 uint16_t user_index_low; 470 } __rte_packed_end; 471 }; 472 uint32_t flow_table_metadata; 473 uint8_t rsvd4[4]; 474 uint32_t byte_cnt; 475 uint64_t timestamp; 476 uint32_t sop_drop_qpn; 477 uint16_t wqe_counter; 478 uint8_t validity_iteration_count; 479 uint8_t op_own; 480 }; 481 482 struct mlx5_cqe_ts { 483 uint64_t timestamp; 484 uint32_t sop_drop_qpn; 485 uint16_t wqe_counter; 486 uint8_t validity_iteration_count; 487 uint8_t op_own; 488 }; 489 490 struct __rte_packed_begin mlx5_wqe_rseg { 491 uint64_t raddr; 492 uint32_t rkey; 493 uint32_t reserved; 494 } __rte_packed_end; 495 496 #define MLX5_UMRC_IF_OFFSET 31u 497 #define MLX5_UMRC_KO_OFFSET 16u 498 #define MLX5_UMRC_TO_BS_OFFSET 0u 499 500 /* 501 * As PRM describes, the address of the UMR pointer must be 502 * aligned to 2KB. 503 */ 504 #define MLX5_UMR_KLM_PTR_ALIGN (1 << 11) 505 506 #define MLX5_UMR_KLM_NUM_ALIGN \ 507 (MLX5_UMR_KLM_PTR_ALIGN / sizeof(struct mlx5_klm)) 508 509 struct __rte_packed_begin mlx5_wqe_umr_cseg { 510 uint32_t if_cf_toe_cq_res; 511 uint32_t ko_to_bs; 512 uint64_t mkey_mask; 513 uint32_t rsvd1[8]; 514 } __rte_packed_end; 515 516 struct __rte_packed_begin mlx5_wqe_mkey_cseg { 517 uint32_t fr_res_af_sf; 518 uint32_t qpn_mkey; 519 uint32_t reserved2; 520 uint32_t flags_pd; 521 uint64_t start_addr; 522 uint64_t len; 523 uint32_t bsf_octword_size; 524 uint32_t reserved3[4]; 525 uint32_t translations_octword_size; 526 uint32_t res4_lps; 527 uint32_t reserved; 528 } __rte_packed_end; 529 530 enum { 531 MLX5_BSF_SIZE_16B = 0x0, 532 MLX5_BSF_SIZE_32B = 0x1, 533 MLX5_BSF_SIZE_64B = 0x2, 534 MLX5_BSF_SIZE_128B = 0x3, 535 }; 536 537 enum { 538 MLX5_BSF_P_TYPE_SIGNATURE = 0x0, 539 MLX5_BSF_P_TYPE_CRYPTO = 0x1, 540 }; 541 542 enum { 543 MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, 544 MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, 545 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, 546 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, 547 }; 548 549 enum { 550 MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, 551 }; 552 553 enum { 554 MLX5_BLOCK_SIZE_512B = 0x1, 555 MLX5_BLOCK_SIZE_520B = 0x2, 556 MLX5_BLOCK_SIZE_4096B = 0x3, 557 MLX5_BLOCK_SIZE_4160B = 0x4, 558 MLX5_BLOCK_SIZE_1MB = 0x5, 559 MLX5_BLOCK_SIZE_4048B = 0x6, 560 }; 561 562 enum { 563 MLX5_ENCRYPTION_TYPE_AES_GCM = 0x3, 564 }; 565 566 enum { 567 MLX5_CRYPTO_OP_TYPE_ENCRYPTION = 0x0, 568 MLX5_CRYPTO_OP_TYPE_DECRYPTION = 0x1, 569 }; 570 571 #define MLX5_BSF_SIZE_OFFSET 30 572 #define MLX5_BSF_P_TYPE_OFFSET 24 573 #define MLX5_ENCRYPTION_ORDER_OFFSET 16 574 #define MLX5_BLOCK_SIZE_OFFSET 24 575 576 #define MLX5_CRYPTO_MMO_TYPE_OFFSET 24 577 #define MLX5_CRYPTO_MMO_OP_OFFSET 20 578 579 struct __rte_packed_begin mlx5_wqe_umr_bsf_seg { 580 /* 581 * bs_bpt_eo_es contains: 582 * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET 583 * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET 584 * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET 585 * es encryption_standard 4 bits at offset 0 586 */ 587 uint32_t bs_bpt_eo_es; 588 uint32_t raw_data_size; 589 /* 590 * bsp_res contains: 591 * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET 592 * res reserved 24 bits 593 */ 594 uint32_t bsp_res; 595 uint32_t reserved0; 596 uint8_t xts_initial_tweak[16]; 597 /* 598 * res_dp contains: 599 * res reserved 8 bits 600 * dp dek_pointer 24 bits at offset 0 601 */ 602 uint32_t res_dp; 603 uint32_t reserved1; 604 uint64_t keytag; 605 uint32_t reserved2[4]; 606 } __rte_packed_end; 607 608 #ifdef PEDANTIC 609 #pragma GCC diagnostic ignored "-Wpedantic" 610 #endif 611 612 struct __rte_packed_begin mlx5_umr_wqe { 613 struct mlx5_wqe_cseg ctr; 614 struct mlx5_wqe_umr_cseg ucseg; 615 struct mlx5_wqe_mkey_cseg mkc; 616 union { 617 struct mlx5_wqe_dseg kseg[0]; 618 struct mlx5_wqe_umr_bsf_seg bsf[0]; 619 }; 620 } __rte_packed_end; 621 622 struct __rte_packed_begin mlx5_rdma_write_wqe { 623 struct mlx5_wqe_cseg ctr; 624 struct mlx5_wqe_rseg rseg; 625 struct mlx5_wqe_dseg dseg[]; 626 } __rte_packed_end; 627 628 struct __rte_packed_begin mlx5_wqe_send_en_seg { 629 uint32_t reserve[2]; 630 uint32_t sqnpc; 631 uint32_t qpn; 632 } __rte_packed_end; 633 634 struct __rte_packed_begin mlx5_wqe_send_en_wqe { 635 struct mlx5_wqe_cseg ctr; 636 struct mlx5_wqe_send_en_seg sseg; 637 } __rte_packed_end; 638 639 #ifdef PEDANTIC 640 #pragma GCC diagnostic error "-Wpedantic" 641 #endif 642 643 /* GGA */ 644 /* MMO metadata segment */ 645 646 #define MLX5_OPCODE_MMO 0x2fu 647 #define MLX5_OPC_MOD_MMO_CRYPTO 0x6u 648 #define MLX5_OPC_MOD_MMO_REGEX 0x4u 649 #define MLX5_OPC_MOD_MMO_COMP 0x2u 650 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u 651 #define MLX5_OPC_MOD_MMO_DMA 0x1u 652 653 #define WQE_GGA_DECOMP_DEFLATE 0x0u 654 #define WQE_GGA_DECOMP_LZ4 0x2u 655 656 #define MLX5_GGA_DECOMP_LZ4_BLOCK_WITHOUT_CHECKSUM 0x1u 657 #define MLX5_GGA_DECOMP_LZ4_BLOCK_WITH_CHECKSUM 0x2u 658 659 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u 660 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u 661 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u 662 #define WQE_GGA_DECOMP_PARAMS_OFFSET 20u 663 #define WQE_GGA_DECOMP_TYPE_OFFSET 8u 664 #define WQE_GGA_DECOMP_BLOCK_INDEPENDENT_OFFSET 22u 665 666 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u 667 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) 668 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u 669 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u 670 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u 671 #define MLX5_GGA_COMP_OUT_OF_SPACE_SYNDROME_BE 0x29D0084 672 #define MLX5_GGA_COMP_MISSING_BFINAL_SYNDROME_BE 0x29D0011 673 674 struct mlx5_wqe_metadata_seg { 675 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */ 676 uint32_t lkey; 677 uint64_t addr; 678 }; 679 680 struct __rte_packed_begin mlx5_gga_wqe { 681 uint32_t opcode; 682 uint32_t sq_ds; 683 uint32_t flags; 684 uint32_t gga_ctrl1; 685 uint32_t gga_ctrl2; 686 uint32_t opaque_lkey; 687 uint64_t opaque_vaddr; 688 struct mlx5_wqe_dseg gather; 689 struct mlx5_wqe_dseg scatter; 690 } __rte_packed_end; 691 692 union mlx5_gga_compress_opaque { 693 struct __rte_packed_begin { 694 uint32_t syndrome; 695 uint32_t reserved0; 696 uint32_t scattered_length; 697 union { 698 struct __rte_packed_begin { 699 uint32_t reserved1[5]; 700 uint32_t crc32; 701 uint32_t adler32; 702 } v1 __rte_packed_end; 703 struct __rte_packed_begin { 704 uint32_t crc32; 705 uint32_t adler32; 706 uint32_t crc32c; 707 uint32_t xxh32; 708 } v2 __rte_packed_end; 709 }; 710 } __rte_packed_end; 711 uint32_t data[64]; 712 }; 713 714 union mlx5_gga_crypto_opaque { 715 struct __rte_packed_begin { 716 uint32_t syndrome; 717 uint32_t reserved0[2]; 718 struct __rte_packed_begin { 719 uint32_t iv[3]; 720 uint32_t tag_size; 721 uint32_t aad_size; 722 } cp __rte_packed_end; 723 } __rte_packed_end; 724 uint8_t data[64]; 725 }; 726 727 struct mlx5_ifc_regexp_mmo_control_bits { 728 uint8_t reserved_at_31[0x2]; 729 uint8_t le[0x1]; 730 uint8_t reserved_at_28[0x1]; 731 uint8_t subset_id_0[0xc]; 732 uint8_t reserved_at_16[0x4]; 733 uint8_t subset_id_1[0xc]; 734 uint8_t ctrl[0x4]; 735 uint8_t subset_id_2[0xc]; 736 uint8_t reserved_at_16_1[0x4]; 737 uint8_t subset_id_3[0xc]; 738 }; 739 740 struct mlx5_ifc_regexp_metadata_bits { 741 uint8_t rof_version[0x10]; 742 uint8_t latency_count[0x10]; 743 uint8_t instruction_count[0x10]; 744 uint8_t primary_thread_count[0x10]; 745 uint8_t match_count[0x8]; 746 uint8_t detected_match_count[0x8]; 747 uint8_t status[0x10]; 748 uint8_t job_id[0x20]; 749 uint8_t reserved[0x80]; 750 }; 751 752 struct mlx5_ifc_regexp_match_tuple_bits { 753 uint8_t length[0x10]; 754 uint8_t start_ptr[0x10]; 755 uint8_t rule_id[0x20]; 756 }; 757 758 /* Adding direct verbs to data-path. */ 759 760 /* CQ sequence number mask. */ 761 #define MLX5_CQ_SQN_MASK 0x3 762 763 /* CQ sequence number index. */ 764 #define MLX5_CQ_SQN_OFFSET 28 765 766 /* CQ doorbell index mask. */ 767 #define MLX5_CI_MASK 0xffffff 768 769 /* CQ doorbell offset. */ 770 #define MLX5_CQ_ARM_DB 1 771 772 /* CQ doorbell offset*/ 773 #define MLX5_CQ_DOORBELL 0x20 774 775 /* CQE format value. */ 776 #define MLX5_COMPRESSED 0x3 777 778 /* CQ doorbell cmd types. */ 779 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24) 780 #define MLX5_CQ_DBR_CMD_ALL (0 << 24) 781 782 /* Action type of header modification. */ 783 enum { 784 MLX5_MODIFICATION_TYPE_SET = 0x1, 785 MLX5_MODIFICATION_TYPE_ADD = 0x2, 786 MLX5_MODIFICATION_TYPE_COPY = 0x3, 787 MLX5_MODIFICATION_TYPE_INSERT = 0x4, 788 MLX5_MODIFICATION_TYPE_REMOVE = 0x5, 789 MLX5_MODIFICATION_TYPE_NOP = 0x6, 790 MLX5_MODIFICATION_TYPE_REMOVE_WORDS = 0x7, 791 MLX5_MODIFICATION_TYPE_ADD_FIELD = 0x8, 792 MLX5_MODIFICATION_TYPE_MAX, 793 }; 794 795 /* The field of packet to be modified. */ 796 enum mlx5_modification_field { 797 MLX5_MODI_OUT_NONE = -1, 798 MLX5_MODI_OUT_SMAC_47_16 = 1, 799 MLX5_MODI_OUT_SMAC_15_0, 800 MLX5_MODI_OUT_ETHERTYPE, 801 MLX5_MODI_OUT_DMAC_47_16, 802 MLX5_MODI_OUT_DMAC_15_0, 803 MLX5_MODI_OUT_IP_DSCP, 804 MLX5_MODI_OUT_TCP_FLAGS, 805 MLX5_MODI_OUT_TCP_SPORT, 806 MLX5_MODI_OUT_TCP_DPORT, 807 MLX5_MODI_OUT_IPV4_TTL, 808 MLX5_MODI_OUT_UDP_SPORT, 809 MLX5_MODI_OUT_UDP_DPORT, 810 MLX5_MODI_OUT_SIPV6_127_96, 811 MLX5_MODI_OUT_SIPV6_95_64, 812 MLX5_MODI_OUT_SIPV6_63_32, 813 MLX5_MODI_OUT_SIPV6_31_0, 814 MLX5_MODI_OUT_DIPV6_127_96, 815 MLX5_MODI_OUT_DIPV6_95_64, 816 MLX5_MODI_OUT_DIPV6_63_32, 817 MLX5_MODI_OUT_DIPV6_31_0, 818 MLX5_MODI_OUT_SIPV4, 819 MLX5_MODI_OUT_DIPV4, 820 MLX5_MODI_OUT_FIRST_VID, 821 MLX5_MODI_IN_SMAC_47_16 = 0x31, 822 MLX5_MODI_IN_SMAC_15_0, 823 MLX5_MODI_IN_ETHERTYPE, 824 MLX5_MODI_IN_DMAC_47_16, 825 MLX5_MODI_IN_DMAC_15_0, 826 MLX5_MODI_IN_IP_DSCP, 827 MLX5_MODI_IN_TCP_FLAGS, 828 MLX5_MODI_IN_TCP_SPORT, 829 MLX5_MODI_IN_TCP_DPORT, 830 MLX5_MODI_IN_IPV4_TTL, 831 MLX5_MODI_IN_UDP_SPORT, 832 MLX5_MODI_IN_UDP_DPORT, 833 MLX5_MODI_IN_SIPV6_127_96, 834 MLX5_MODI_IN_SIPV6_95_64, 835 MLX5_MODI_IN_SIPV6_63_32, 836 MLX5_MODI_IN_SIPV6_31_0, 837 MLX5_MODI_IN_DIPV6_127_96, 838 MLX5_MODI_IN_DIPV6_95_64, 839 MLX5_MODI_IN_DIPV6_63_32, 840 MLX5_MODI_IN_DIPV6_31_0, 841 MLX5_MODI_IN_SIPV4, 842 MLX5_MODI_IN_DIPV4, 843 MLX5_MODI_OUT_IPV6_HOPLIMIT, 844 MLX5_MODI_IN_IPV6_HOPLIMIT, 845 MLX5_MODI_META_DATA_REG_A, 846 MLX5_MODI_OUT_IP_PROTOCOL, 847 MLX5_MODI_META_DATA_REG_B = 0x50, 848 MLX5_MODI_META_REG_C_0, 849 MLX5_MODI_META_REG_C_1, 850 MLX5_MODI_META_REG_C_2, 851 MLX5_MODI_META_REG_C_3, 852 MLX5_MODI_META_REG_C_4, 853 MLX5_MODI_META_REG_C_5, 854 MLX5_MODI_META_REG_C_6, 855 MLX5_MODI_META_REG_C_7, 856 MLX5_MODI_OUT_TCP_SEQ_NUM, 857 MLX5_MODI_IN_TCP_SEQ_NUM, 858 MLX5_MODI_OUT_TCP_ACK_NUM, 859 MLX5_MODI_IN_TCP_ACK_NUM, 860 MLX5_MODI_OUT_ESP_SPI = 0x5E, 861 MLX5_MODI_IN_ESP_SPI, 862 MLX5_MODI_GTP_TEID = 0x6E, 863 MLX5_MODI_OUT_IP_ECN = 0x73, 864 MLX5_MODI_IN_IP_ECN, 865 MLX5_MODI_TUNNEL_HDR_DW_1, 866 MLX5_MODI_GTPU_FIRST_EXT_DW_0, 867 MLX5_MODI_HASH_RESULT = 0x81, 868 MLX5_MODI_OUT_ESP_SEQ_NUM, 869 MLX5_MODI_IN_ESP_SEQ_NUM, 870 MLX5_MODI_IN_MPLS_LABEL_0 = 0x8a, 871 MLX5_MODI_IN_MPLS_LABEL_1, 872 MLX5_MODI_IN_MPLS_LABEL_2, 873 MLX5_MODI_IN_MPLS_LABEL_3, 874 MLX5_MODI_IN_MPLS_LABEL_4, 875 MLX5_MODI_META_REG_C_8, 876 MLX5_MODI_META_REG_C_9, 877 MLX5_MODI_META_REG_C_10, 878 MLX5_MODI_META_REG_C_11, 879 MLX5_MODI_META_REG_C_12, 880 MLX5_MODI_META_REG_C_13, 881 MLX5_MODI_META_REG_C_14, 882 MLX5_MODI_META_REG_C_15, 883 MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS = 0x11C, 884 MLX5_MODI_OUT_IPV4_TOTAL_LEN, 885 MLX5_MODI_OUT_IPV6_PAYLOAD_LEN, 886 MLX5_MODI_OUT_IPV4_IHL, 887 MLX5_MODI_OUT_TCP_DATA_OFFSET, 888 MLX5_MODI_IN_IPV6_TRAFFIC_CLASS, 889 MLX5_MODI_IN_IPV4_TOTAL_LEN, 890 MLX5_MODI_IN_IPV6_PAYLOAD_LEN, 891 MLX5_MODI_IN_IPV4_IHL, 892 MLX5_MODI_IN_TCP_DATA_OFFSET, 893 MLX5_MODI_OUT_IPSEC_NEXT_HDR, 894 MLX5_MODI_OUT_IPV6_FLOW_LABEL, 895 MLX5_MODI_IN_IPV6_FLOW_LABEL, 896 MLX5_MODI_INVALID = INT_MAX, 897 }; 898 899 /* Total number of metadata reg_c's. */ 900 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1) 901 902 enum modify_reg { 903 REG_NON = 0, 904 REG_A, 905 REG_B, 906 REG_C_0, 907 REG_C_1, 908 REG_C_2, 909 REG_C_3, 910 REG_C_4, 911 REG_C_5, 912 REG_C_6, 913 REG_C_7, 914 REG_C_8, 915 REG_C_9, 916 REG_C_10, 917 REG_C_11, 918 }; 919 920 static __rte_always_inline uint8_t 921 mlx5_regc_index(enum modify_reg regc_val) 922 { 923 return (uint8_t)(regc_val - REG_C_0); 924 } 925 926 static __rte_always_inline enum modify_reg 927 mlx5_regc_value(uint8_t regc_ix) 928 { 929 return REG_C_0 + regc_ix; 930 } 931 932 /* Modification sub command. */ 933 struct mlx5_modification_cmd { 934 union __rte_packed_begin { 935 uint32_t data0; 936 struct { 937 unsigned int length:5; 938 unsigned int rsvd0:3; 939 unsigned int offset:5; 940 unsigned int rsvd1:3; 941 unsigned int field:12; 942 unsigned int action_type:4; 943 }; 944 } __rte_packed_end; 945 union __rte_packed_begin { 946 uint32_t data1; 947 uint8_t data[4]; 948 struct { 949 unsigned int rsvd2:8; 950 unsigned int dst_offset:5; 951 unsigned int rsvd3:3; 952 unsigned int dst_field:12; 953 unsigned int rsvd4:4; 954 }; 955 } __rte_packed_end; 956 }; 957 958 typedef uint64_t u64; 959 typedef uint32_t u32; 960 typedef uint16_t u16; 961 typedef uint8_t u8; 962 963 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 964 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 965 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \ 966 (&(__mlx5_nullp(typ)->fld))) 967 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \ 968 (__mlx5_bit_off(typ, fld) & 0x1f)) 969 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 970 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 971 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \ 972 __mlx5_dw_bit_off(typ, fld)) 973 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 974 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 975 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \ 976 (__mlx5_bit_off(typ, fld) & 0xf)) 977 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 978 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \ 979 __mlx5_16_bit_off(typ, fld)) 980 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 981 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 982 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 983 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 984 985 /* insert a value to a struct */ 986 #define MLX5_SET(typ, p, fld, v) \ 987 do { \ 988 u32 _v = v; \ 989 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \ 990 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \ 991 __mlx5_dw_off(typ, fld))) & \ 992 (~__mlx5_dw_mask(typ, fld))) | \ 993 (((_v) & __mlx5_mask(typ, fld)) << \ 994 __mlx5_dw_bit_off(typ, fld))); \ 995 } while (0) 996 997 #define MLX5_SET64(typ, p, fld, v) \ 998 do { \ 999 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \ 1000 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \ 1001 rte_cpu_to_be_64(v); \ 1002 } while (0) 1003 1004 #define MLX5_SET16(typ, p, fld, v) \ 1005 do { \ 1006 u16 _v = v; \ 1007 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \ 1008 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 1009 __mlx5_16_off(typ, fld))) & \ 1010 (~__mlx5_16_mask(typ, fld))) | \ 1011 (((_v) & __mlx5_mask16(typ, fld)) << \ 1012 __mlx5_16_bit_off(typ, fld))); \ 1013 } while (0) 1014 1015 #define MLX5_GET_VOLATILE(typ, p, fld) \ 1016 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\ 1017 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 1018 __mlx5_mask(typ, fld)) 1019 #define MLX5_GET(typ, p, fld) \ 1020 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\ 1021 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 1022 __mlx5_mask(typ, fld)) 1023 #define MLX5_GET16(typ, p, fld) \ 1024 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 1025 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 1026 __mlx5_mask16(typ, fld)) 1027 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \ 1028 __mlx5_64_off(typ, fld))) 1029 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 1030 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 1031 1032 struct mlx5_ifc_fte_match_set_misc_bits { 1033 u8 gre_c_present[0x1]; 1034 u8 reserved_at_1[0x1]; 1035 u8 gre_k_present[0x1]; 1036 u8 gre_s_present[0x1]; 1037 u8 source_vhci_port[0x4]; 1038 u8 source_sqn[0x18]; 1039 u8 reserved_at_20[0x10]; 1040 u8 source_port[0x10]; 1041 u8 outer_second_prio[0x3]; 1042 u8 outer_second_cfi[0x1]; 1043 u8 outer_second_vid[0xc]; 1044 u8 inner_second_prio[0x3]; 1045 u8 inner_second_cfi[0x1]; 1046 u8 inner_second_vid[0xc]; 1047 u8 outer_second_cvlan_tag[0x1]; 1048 u8 inner_second_cvlan_tag[0x1]; 1049 u8 outer_second_svlan_tag[0x1]; 1050 u8 inner_second_svlan_tag[0x1]; 1051 u8 reserved_at_64[0xc]; 1052 u8 gre_protocol[0x10]; 1053 u8 gre_key_h[0x18]; 1054 u8 gre_key_l[0x8]; 1055 u8 vxlan_vni[0x18]; 1056 u8 bth_opcode[0x8]; 1057 u8 geneve_vni[0x18]; 1058 u8 lag_rx_port_affinity[0x4]; 1059 u8 reserved_at_e8[0x2]; 1060 u8 geneve_tlv_option_0_exist[0x1]; 1061 u8 geneve_oam[0x1]; 1062 u8 reserved_at_e0[0xc]; 1063 u8 outer_ipv6_flow_label[0x14]; 1064 u8 reserved_at_100[0xc]; 1065 u8 inner_ipv6_flow_label[0x14]; 1066 u8 reserved_at_120[0xa]; 1067 u8 geneve_opt_len[0x6]; 1068 u8 geneve_protocol_type[0x10]; 1069 u8 reserved_at_140[0x8]; 1070 u8 bth_dst_qp[0x18]; 1071 u8 inner_esp_spi[0x20]; 1072 u8 outer_esp_spi[0x20]; 1073 u8 reserved_at_1a0[0x60]; 1074 }; 1075 1076 struct mlx5_ifc_ipv4_layout_bits { 1077 u8 reserved_at_0[0x60]; 1078 u8 ipv4[0x20]; 1079 }; 1080 1081 struct mlx5_ifc_ipv6_layout_bits { 1082 u8 ipv6[16][0x8]; 1083 }; 1084 1085 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 1086 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 1087 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 1088 u8 reserved_at_0[0x80]; 1089 }; 1090 1091 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 1092 u8 smac_47_16[0x20]; 1093 u8 smac_15_0[0x10]; 1094 u8 ethertype[0x10]; 1095 u8 dmac_47_16[0x20]; 1096 u8 dmac_15_0[0x10]; 1097 u8 first_prio[0x3]; 1098 u8 first_cfi[0x1]; 1099 u8 first_vid[0xc]; 1100 u8 ip_protocol[0x8]; 1101 u8 ip_dscp[0x6]; 1102 u8 ip_ecn[0x2]; 1103 u8 cvlan_tag[0x1]; 1104 u8 svlan_tag[0x1]; 1105 u8 frag[0x1]; 1106 u8 ip_version[0x4]; 1107 u8 tcp_flags[0x9]; 1108 u8 tcp_sport[0x10]; 1109 u8 tcp_dport[0x10]; 1110 u8 reserved_at_c0[0x10]; 1111 u8 ipv4_ihl[0x4]; 1112 u8 l3_ok[0x1]; 1113 u8 l4_ok[0x1]; 1114 u8 ipv4_checksum_ok[0x1]; 1115 u8 l4_checksum_ok[0x1]; 1116 u8 ip_ttl_hoplimit[0x8]; 1117 u8 udp_sport[0x10]; 1118 u8 udp_dport[0x10]; 1119 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 1120 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 1121 }; 1122 1123 struct mlx5_ifc_fte_match_mpls_bits { 1124 u8 mpls_label[0x14]; 1125 u8 mpls_exp[0x3]; 1126 u8 mpls_s_bos[0x1]; 1127 u8 mpls_ttl[0x8]; 1128 }; 1129 1130 struct mlx5_ifc_fte_match_set_misc2_bits { 1131 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 1132 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 1133 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 1134 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 1135 u8 metadata_reg_c_7[0x20]; 1136 u8 metadata_reg_c_6[0x20]; 1137 u8 metadata_reg_c_5[0x20]; 1138 u8 metadata_reg_c_4[0x20]; 1139 u8 metadata_reg_c_3[0x20]; 1140 u8 metadata_reg_c_2[0x20]; 1141 u8 metadata_reg_c_1[0x20]; 1142 u8 metadata_reg_c_0[0x20]; 1143 u8 metadata_reg_a[0x20]; 1144 u8 metadata_reg_b[0x20]; 1145 u8 reserved_at_1c0[0x40]; 1146 }; 1147 1148 struct mlx5_ifc_fte_match_set_misc3_bits { 1149 u8 inner_tcp_seq_num[0x20]; 1150 u8 outer_tcp_seq_num[0x20]; 1151 u8 inner_tcp_ack_num[0x20]; 1152 u8 outer_tcp_ack_num[0x20]; 1153 u8 reserved_at_auto1[0x8]; 1154 u8 outer_vxlan_gpe_vni[0x18]; 1155 u8 outer_vxlan_gpe_next_protocol[0x8]; 1156 u8 outer_vxlan_gpe_flags[0x8]; 1157 u8 reserved_at_a8[0x10]; 1158 u8 icmp_header_data[0x20]; 1159 u8 icmpv6_header_data[0x20]; 1160 u8 icmp_type[0x8]; 1161 u8 icmp_code[0x8]; 1162 u8 icmpv6_type[0x8]; 1163 u8 icmpv6_code[0x8]; 1164 u8 geneve_tlv_option_0_data[0x20]; 1165 u8 gtpu_teid[0x20]; 1166 u8 gtpu_msg_type[0x08]; 1167 u8 gtpu_msg_flags[0x08]; 1168 u8 reserved_at_170[0x10]; 1169 u8 gtpu_dw_2[0x20]; 1170 u8 gtpu_first_ext_dw_0[0x20]; 1171 u8 gtpu_dw_0[0x20]; 1172 u8 reserved_at_240[0x20]; 1173 1174 }; 1175 1176 struct mlx5_ifc_fte_match_set_misc4_bits { 1177 u8 prog_sample_field_value_0[0x20]; 1178 u8 prog_sample_field_id_0[0x20]; 1179 u8 prog_sample_field_value_1[0x20]; 1180 u8 prog_sample_field_id_1[0x20]; 1181 u8 prog_sample_field_value_2[0x20]; 1182 u8 prog_sample_field_id_2[0x20]; 1183 u8 prog_sample_field_value_3[0x20]; 1184 u8 prog_sample_field_id_3[0x20]; 1185 u8 prog_sample_field_value_4[0x20]; 1186 u8 prog_sample_field_id_4[0x20]; 1187 u8 prog_sample_field_value_5[0x20]; 1188 u8 prog_sample_field_id_5[0x20]; 1189 u8 prog_sample_field_value_6[0x20]; 1190 u8 prog_sample_field_id_6[0x20]; 1191 u8 prog_sample_field_value_7[0x20]; 1192 u8 prog_sample_field_id_7[0x20]; 1193 }; 1194 1195 struct mlx5_ifc_fte_match_set_misc5_bits { 1196 u8 macsec_tag_0[0x20]; 1197 u8 macsec_tag_1[0x20]; 1198 u8 macsec_tag_2[0x20]; 1199 u8 macsec_tag_3[0x20]; 1200 u8 tunnel_header_0[0x20]; 1201 u8 tunnel_header_1[0x20]; 1202 u8 tunnel_header_2[0x20]; 1203 u8 tunnel_header_3[0x20]; 1204 u8 reserved[0x100]; 1205 }; 1206 1207 /* Flow matcher. */ 1208 struct mlx5_ifc_fte_match_param_bits { 1209 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1210 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1211 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1212 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1213 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1214 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1215 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1216 /* 1217 * Add reserved bit to match the struct size with the size defined in PRM. 1218 * This extension is not required in Linux. 1219 */ 1220 #ifndef HAVE_INFINIBAND_VERBS_H 1221 u8 reserved_0[0x200]; 1222 #endif 1223 }; 1224 1225 struct mlx5_ifc_dest_format_struct_bits { 1226 u8 destination_type[0x8]; 1227 u8 destination_id[0x18]; 1228 u8 reserved_0[0x20]; 1229 }; 1230 1231 enum { 1232 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 1233 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT, 1234 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT, 1235 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT, 1236 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT, 1237 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT, 1238 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT, 1239 }; 1240 1241 enum { 1242 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 1243 MLX5_CMD_OP_CREATE_MKEY = 0x200, 1244 MLX5_CMD_OP_CREATE_CQ = 0x400, 1245 MLX5_CMD_OP_QUERY_CQ = 0x402, 1246 MLX5_CMD_OP_CREATE_QP = 0x500, 1247 MLX5_CMD_OP_RST2INIT_QP = 0x502, 1248 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 1249 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 1250 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 1251 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 1252 MLX5_CMD_OP_QP_2ERR = 0x507, 1253 MLX5_CMD_OP_QP_2RST = 0x50A, 1254 MLX5_CMD_OP_QUERY_QP = 0x50B, 1255 MLX5_CMD_OP_SQD2RTS_QP = 0x50C, 1256 MLX5_CMD_OP_INIT2INIT_QP = 0x50E, 1257 MLX5_CMD_OP_SUSPEND_QP = 0x50F, 1258 MLX5_CMD_OP_RESUME_QP = 0x510, 1259 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 1260 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 1261 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 1262 MLX5_CMD_OP_ALLOC_PD = 0x800, 1263 MLX5_CMD_OP_DEALLOC_PD = 0x801, 1264 MLX5_CMD_OP_ACCESS_REGISTER = 0x805, 1265 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 1266 MLX5_CMD_OP_QUERY_LAG = 0x842, 1267 MLX5_CMD_OP_CREATE_TIR = 0x900, 1268 MLX5_CMD_OP_MODIFY_TIR = 0x901, 1269 MLX5_CMD_OP_CREATE_SQ = 0X904, 1270 MLX5_CMD_OP_MODIFY_SQ = 0X905, 1271 MLX5_CMD_OP_QUERY_SQ = 0x907, 1272 MLX5_CMD_OP_CREATE_RQ = 0x908, 1273 MLX5_CMD_OP_MODIFY_RQ = 0x909, 1274 MLX5_CMD_OP_QUERY_RQ = 0x90b, 1275 MLX5_CMD_OP_CREATE_RMP = 0x90c, 1276 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 1277 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 1278 MLX5_CMD_OP_QUERY_RMP = 0x90f, 1279 MLX5_CMD_OP_CREATE_TIS = 0x912, 1280 MLX5_CMD_OP_QUERY_TIS = 0x915, 1281 MLX5_CMD_OP_CREATE_RQT = 0x916, 1282 MLX5_CMD_OP_MODIFY_RQT = 0x917, 1283 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 1284 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 1285 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 1286 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 1287 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 1288 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 1289 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 1290 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 1291 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 1292 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 1293 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 1294 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 1295 MLX5_CMD_SET_REGEX_PARAMS = 0xb04, 1296 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05, 1297 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06, 1298 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07, 1299 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c, 1300 MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO = 0xb13, 1301 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 1302 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 1303 }; 1304 1305 enum { 1306 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 1307 MLX5_MKC_ACCESS_MODE_KLM = 0x2, 1308 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3, 1309 }; 1310 1311 #define MLX5_ADAPTER_PAGE_SHIFT 12 1312 #define MLX5_LOG_RQ_STRIDE_SHIFT 4 1313 /** 1314 * The batch counter dcs id starts from 0x800000 and none batch counter 1315 * starts from 0. As currently, the counter is changed to be indexed by 1316 * pool index and the offset of the counter in the pool counters_raw array. 1317 * It means now the counter index is same for batch and none batch counter. 1318 * Add the 0x800000 batch counter offset to the batch counter index helps 1319 * indicate the counter index is from batch or none batch container pool. 1320 */ 1321 #define MLX5_CNT_BATCH_OFFSET 0x800000 1322 1323 /* The counter batch query requires ID align with 4. */ 1324 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4 1325 1326 /* Flow counters. */ 1327 struct mlx5_ifc_alloc_flow_counter_out_bits { 1328 u8 status[0x8]; 1329 u8 reserved_at_8[0x18]; 1330 u8 syndrome[0x20]; 1331 u8 flow_counter_id[0x20]; 1332 u8 reserved_at_60[0x20]; 1333 }; 1334 1335 struct mlx5_ifc_alloc_flow_counter_in_bits { 1336 u8 opcode[0x10]; 1337 u8 reserved_at_10[0x10]; 1338 u8 reserved_at_20[0x10]; 1339 u8 op_mod[0x10]; 1340 u8 reserved_at_40[0x8]; 1341 u8 pd[0x18]; 1342 u8 reserved_at_60[0x13]; 1343 u8 flow_counter_bulk_log_size[0x5]; 1344 u8 flow_counter_bulk[0x8]; 1345 }; 1346 1347 struct mlx5_ifc_dealloc_flow_counter_out_bits { 1348 u8 status[0x8]; 1349 u8 reserved_at_8[0x18]; 1350 u8 syndrome[0x20]; 1351 u8 reserved_at_40[0x40]; 1352 }; 1353 1354 struct mlx5_ifc_dealloc_flow_counter_in_bits { 1355 u8 opcode[0x10]; 1356 u8 reserved_at_10[0x10]; 1357 u8 reserved_at_20[0x10]; 1358 u8 op_mod[0x10]; 1359 u8 flow_counter_id[0x20]; 1360 u8 reserved_at_60[0x20]; 1361 }; 1362 1363 struct mlx5_ifc_traffic_counter_bits { 1364 u8 packets[0x40]; 1365 u8 octets[0x40]; 1366 }; 1367 1368 struct mlx5_ifc_query_flow_counter_out_bits { 1369 u8 status[0x8]; 1370 u8 reserved_at_8[0x18]; 1371 u8 syndrome[0x20]; 1372 u8 reserved_at_40[0x40]; 1373 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 1374 }; 1375 1376 struct mlx5_ifc_query_flow_counter_in_bits { 1377 u8 opcode[0x10]; 1378 u8 reserved_at_10[0x10]; 1379 u8 reserved_at_20[0x10]; 1380 u8 op_mod[0x10]; 1381 u8 reserved_at_40[0x20]; 1382 u8 mkey[0x20]; 1383 u8 address[0x40]; 1384 u8 clear[0x1]; 1385 u8 dump_to_memory[0x1]; 1386 u8 num_of_counters[0x1e]; 1387 u8 flow_counter_id[0x20]; 1388 }; 1389 1390 struct mlx5_ifc_query_match_sample_info_out_bits { 1391 u8 status[0x8]; 1392 u8 reserved_at_8[0x18]; 1393 u8 syndrome[0x20]; 1394 u8 reserved_at_40[0x40]; 1395 u8 reserved_at_80[0x4]; 1396 u8 modify_field_id[0xc]; 1397 u8 ok_bit_format_select_dw[0x8]; 1398 u8 field_format_select_dw[0x8]; 1399 u8 reserved_at_a0[0x3]; 1400 u8 ok_bit_offset[0x5]; 1401 u8 reserved_at_a8[0x18]; 1402 u8 reserved_at_c0[0x40]; 1403 }; 1404 1405 struct mlx5_ifc_query_match_sample_info_in_bits { 1406 u8 opcode[0x10]; 1407 u8 uid[0x10]; 1408 u8 reserved_at_20[0x10]; 1409 u8 op_mod[0x10]; 1410 u8 reserved_at_40[0x60]; 1411 u8 sample_field_id[0x20]; 1412 u8 reserved_at_c0[0x140]; 1413 }; 1414 1415 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u 1416 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u 1417 1418 struct mlx5_ifc_klm_bits { 1419 u8 byte_count[0x20]; 1420 u8 mkey[0x20]; 1421 u8 address[0x40]; 1422 }; 1423 1424 struct mlx5_ifc_mkc_bits { 1425 u8 reserved_at_0[0x1]; 1426 u8 free[0x1]; 1427 u8 reserved_at_2[0x1]; 1428 u8 access_mode_4_2[0x3]; 1429 u8 reserved_at_6[0x7]; 1430 u8 relaxed_ordering_write[0x1]; 1431 u8 reserved_at_e[0x1]; 1432 u8 small_fence_on_rdma_read_response[0x1]; 1433 u8 umr_en[0x1]; 1434 u8 a[0x1]; 1435 u8 rw[0x1]; 1436 u8 rr[0x1]; 1437 u8 lw[0x1]; 1438 u8 lr[0x1]; 1439 u8 access_mode_1_0[0x2]; 1440 u8 reserved_at_18[0x8]; 1441 u8 qpn[0x18]; 1442 u8 mkey_7_0[0x8]; 1443 u8 reserved_at_40[0x20]; 1444 u8 length64[0x1]; 1445 u8 bsf_en[0x1]; 1446 u8 sync_umr[0x1]; 1447 u8 reserved_at_63[0x2]; 1448 u8 expected_sigerr_count[0x1]; 1449 u8 reserved_at_66[0x1]; 1450 u8 en_rinval[0x1]; 1451 u8 pd[0x18]; 1452 u8 start_addr[0x40]; 1453 u8 len[0x40]; 1454 u8 bsf_octword_size[0x20]; 1455 u8 reserved_at_120[0x80]; 1456 u8 translations_octword_size[0x20]; 1457 u8 reserved_at_1c0[0x19]; 1458 u8 relaxed_ordering_read[0x1]; 1459 u8 reserved_at_1da[0x1]; 1460 u8 log_page_size[0x5]; 1461 u8 reserved_at_1e0[0x3]; 1462 u8 crypto_en[0x2]; 1463 u8 reserved_at_1e5[0x1b]; 1464 }; 1465 1466 /* Range of values for MKEY context crypto_en field. */ 1467 enum { 1468 MLX5_MKEY_CRYPTO_DISABLED = 0x0, 1469 MLX5_MKEY_CRYPTO_ENABLED = 0x1, 1470 }; 1471 1472 struct mlx5_ifc_create_mkey_out_bits { 1473 u8 status[0x8]; 1474 u8 reserved_at_8[0x18]; 1475 u8 syndrome[0x20]; 1476 u8 reserved_at_40[0x8]; 1477 u8 mkey_index[0x18]; 1478 u8 reserved_at_60[0x20]; 1479 }; 1480 1481 struct mlx5_ifc_create_mkey_in_bits { 1482 u8 opcode[0x10]; 1483 u8 reserved_at_10[0x10]; 1484 u8 reserved_at_20[0x10]; 1485 u8 op_mod[0x10]; 1486 u8 reserved_at_40[0x20]; 1487 u8 pg_access[0x1]; 1488 u8 reserved_at_61[0x1f]; 1489 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 1490 u8 reserved_at_280[0x80]; 1491 u8 translations_octword_actual_size[0x20]; 1492 u8 mkey_umem_id[0x20]; 1493 u8 mkey_umem_offset[0x40]; 1494 u8 reserved_at_380[0x500]; 1495 u8 klm_pas_mtt[][0x20]; 1496 }; 1497 1498 enum { 1499 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, 1500 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, 1501 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1, 1502 MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, 1503 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, 1504 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE = 0x8 << 1, 1505 MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1, 1506 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, 1507 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO = 0x1A << 1, 1508 MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE = 0x1B << 1, 1509 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1, 1510 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, 1511 }; 1512 1513 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \ 1514 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ) 1515 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \ 1516 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS) 1517 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \ 1518 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH) 1519 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \ 1520 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO) 1521 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \ 1522 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO) 1523 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ 1524 (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT) 1525 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \ 1526 (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD) 1527 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEFINER \ 1528 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEFINER) 1529 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \ 1530 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK) 1531 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \ 1532 (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK) 1533 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \ 1534 (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL) 1535 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \ 1536 (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN) 1537 1538 enum { 1539 MLX5_HCA_CAP_OPMOD_GET_MAX = 0, 1540 MLX5_HCA_CAP_OPMOD_GET_CUR = 1, 1541 }; 1542 1543 enum { 1544 MLX5_CAP_INLINE_MODE_L2, 1545 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT, 1546 MLX5_CAP_INLINE_MODE_NOT_REQUIRED, 1547 }; 1548 1549 enum { 1550 MLX5_INLINE_MODE_NONE, 1551 MLX5_INLINE_MODE_L2, 1552 MLX5_INLINE_MODE_IP, 1553 MLX5_INLINE_MODE_TCP_UDP, 1554 MLX5_INLINE_MODE_RESERVED4, 1555 MLX5_INLINE_MODE_INNER_L2, 1556 MLX5_INLINE_MODE_INNER_IP, 1557 MLX5_INLINE_MODE_INNER_TCP_UDP, 1558 }; 1559 1560 /* The supported timestamp formats reported in HCA attributes. */ 1561 enum { 1562 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0, 1563 MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1, 1564 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2, 1565 }; 1566 1567 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */ 1568 enum { 1569 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 1570 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 1571 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 1572 }; 1573 1574 /* HCA bit masks indicating which Flex parser protocols are already enabled. */ 1575 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0) 1576 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1) 1577 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2) 1578 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3) 1579 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4) 1580 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5) 1581 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6) 1582 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7) 1583 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8) 1584 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9) 1585 #define MLX5_HCA_FLEX_GTPU_ENABLED (1UL << 11) 1586 #define MLX5_HCA_FLEX_GTPU_DW_2_ENABLED (1UL << 16) 1587 #define MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED (1UL << 17) 1588 #define MLX5_HCA_FLEX_GTPU_DW_0_ENABLED (1UL << 18) 1589 #define MLX5_HCA_FLEX_GTPU_TEID_ENABLED (1UL << 19) 1590 1591 /* The device steering logic format. */ 1592 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0 1593 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1 1594 1595 struct mlx5_ifc_cmd_hca_cap_bits { 1596 u8 access_other_hca_roce[0x1]; 1597 u8 alloc_flow_counter_pd[0x1]; 1598 u8 flow_counter_access_aso[0x1]; 1599 u8 query_match_sample_info[0x1]; 1600 u8 reserved_at_4[0x4]; 1601 u8 flow_access_aso_opc_mod[0x8]; 1602 u8 reserved_at_10[0xf]; 1603 u8 vhca_resource_manager[0x1]; 1604 u8 hca_cap_2[0x1]; 1605 u8 reserved_at_21[0xf]; 1606 u8 vhca_id[0x10]; 1607 u8 reserved_at_40[0x20]; 1608 u8 reserved_at_60[0x3]; 1609 u8 log_regexp_scatter_gather_size[0x5]; 1610 u8 reserved_at_68[0x3]; 1611 u8 log_dma_mmo_size[0x5]; 1612 u8 reserved_at_70[0x3]; 1613 u8 log_compress_mmo_size[0x5]; 1614 u8 decompress_lz4_data_only_v2[0x1]; 1615 u8 decompress_lz4_no_checksum_v2[0x1]; 1616 u8 decompress_lz4_checksum_v2[0x1]; 1617 u8 log_decompress_mmo_size[0x5]; 1618 u8 log_max_srq_sz[0x8]; 1619 u8 log_max_qp_sz[0x8]; 1620 u8 reserved_at_90[0x9]; 1621 u8 wqe_index_ignore_cap[0x1]; 1622 u8 dynamic_qp_allocation[0x1]; 1623 u8 log_max_qp[0x5]; 1624 u8 reserved_at_a0[0x4]; 1625 u8 regexp_num_of_engines[0x4]; 1626 u8 reserved_at_a8[0x1]; 1627 u8 reg_c_preserve[0x1]; 1628 u8 reserved_at_aa[0x1]; 1629 u8 log_max_srq[0x5]; 1630 u8 reserved_at_b0[0xb]; 1631 u8 scatter_fcs_w_decap_disable[0x1]; 1632 u8 reserved_at_bc[0x4]; 1633 u8 reserved_at_c0[0x8]; 1634 u8 log_max_cq_sz[0x8]; 1635 u8 reserved_at_d0[0x2]; 1636 u8 access_register_user[0x1]; 1637 u8 reserved_at_d3[0x8]; 1638 u8 log_max_cq[0x5]; 1639 u8 log_max_eq_sz[0x8]; 1640 u8 relaxed_ordering_write[0x1]; 1641 u8 relaxed_ordering_read[0x1]; 1642 u8 log_max_mkey[0x6]; 1643 u8 reserved_at_f0[0x8]; 1644 u8 dump_fill_mkey[0x1]; 1645 u8 reserved_at_f9[0x3]; 1646 u8 log_max_eq[0x4]; 1647 u8 max_indirection[0x8]; 1648 u8 fixed_buffer_size[0x1]; 1649 u8 log_max_mrw_sz[0x7]; 1650 u8 force_teardown[0x1]; 1651 u8 reserved_at_111[0x1]; 1652 u8 log_max_bsf_list_size[0x6]; 1653 u8 umr_extended_translation_offset[0x1]; 1654 u8 null_mkey[0x1]; 1655 u8 log_maxklm_list_size[0x6]; 1656 u8 non_wire_sq[0x1]; 1657 u8 reserved_at_121[0x9]; 1658 u8 log_max_ra_req_dc[0x6]; 1659 u8 reserved_at_130[0x3]; 1660 u8 log_max_static_sq_wq[0x5]; 1661 u8 reserved_at_138[0x2]; 1662 u8 log_max_ra_res_dc[0x6]; 1663 u8 reserved_at_140[0xa]; 1664 u8 log_max_ra_req_qp[0x6]; 1665 u8 rtr2rts_qp_counters_set_id[0x1]; 1666 u8 rts2rts_udp_sport[0x1]; 1667 u8 rts2rts_lag_tx_port_affinity[0x1]; 1668 u8 dma_mmo_sq[0x1]; 1669 u8 compress_min_block_size[0x4]; 1670 u8 compress_mmo_sq[0x1]; 1671 u8 decompress_mmo_sq[0x1]; 1672 u8 log_max_ra_res_qp[0x6]; 1673 u8 end_pad[0x1]; 1674 u8 cc_query_allowed[0x1]; 1675 u8 cc_modify_allowed[0x1]; 1676 u8 start_pad[0x1]; 1677 u8 cache_line_128byte[0x1]; 1678 u8 reserved_at_165[0xa]; 1679 u8 qcam_reg[0x1]; 1680 u8 gid_table_size[0x10]; 1681 u8 out_of_seq_cnt[0x1]; 1682 u8 vport_counters[0x1]; 1683 u8 retransmission_q_counters[0x1]; 1684 u8 debug[0x1]; 1685 u8 modify_rq_counter_set_id[0x1]; 1686 u8 rq_delay_drop[0x1]; 1687 u8 max_qp_cnt[0xa]; 1688 u8 pkey_table_size[0x10]; 1689 u8 vport_group_manager[0x1]; 1690 u8 vhca_group_manager[0x1]; 1691 u8 ib_virt[0x1]; 1692 u8 eth_virt[0x1]; 1693 u8 vnic_env_queue_counters[0x1]; 1694 u8 ets[0x1]; 1695 u8 nic_flow_table[0x1]; 1696 u8 eswitch_manager[0x1]; 1697 u8 device_memory[0x1]; 1698 u8 mcam_reg[0x1]; 1699 u8 pcam_reg[0x1]; 1700 u8 local_ca_ack_delay[0x5]; 1701 u8 port_module_event[0x1]; 1702 u8 enhanced_error_q_counters[0x1]; 1703 u8 ports_check[0x1]; 1704 u8 reserved_at_1b3[0x1]; 1705 u8 disable_link_up[0x1]; 1706 u8 beacon_led[0x1]; 1707 u8 port_type[0x2]; 1708 u8 num_ports[0x8]; 1709 u8 reserved_at_1c0[0x1]; 1710 u8 pps[0x1]; 1711 u8 pps_modify[0x1]; 1712 u8 log_max_msg[0x5]; 1713 u8 reserved_at_1c8[0x4]; 1714 u8 max_tc[0x4]; 1715 u8 temp_warn_event[0x1]; 1716 u8 dcbx[0x1]; 1717 u8 general_notification_event[0x1]; 1718 u8 reserved_at_1d3[0x2]; 1719 u8 fpga[0x1]; 1720 u8 rol_s[0x1]; 1721 u8 rol_g[0x1]; 1722 u8 reserved_at_1d8[0x1]; 1723 u8 wol_s[0x1]; 1724 u8 wol_g[0x1]; 1725 u8 wol_a[0x1]; 1726 u8 wol_b[0x1]; 1727 u8 wol_m[0x1]; 1728 u8 wol_u[0x1]; 1729 u8 wol_p[0x1]; 1730 u8 stat_rate_support[0x10]; 1731 u8 reserved_at_1ef[0xb]; 1732 u8 wqe_based_flow_table_update_cap[0x1]; 1733 u8 cqe_version[0x4]; 1734 u8 compact_address_vector[0x1]; 1735 u8 striding_rq[0x1]; 1736 u8 reserved_at_202[0x1]; 1737 u8 ipoib_enhanced_offloads[0x1]; 1738 u8 ipoib_basic_offloads[0x1]; 1739 u8 reserved_at_205[0x1]; 1740 u8 repeated_block_disabled[0x1]; 1741 u8 umr_modify_entity_size_disabled[0x1]; 1742 u8 umr_modify_atomic_disabled[0x1]; 1743 u8 umr_indirect_mkey_disabled[0x1]; 1744 u8 umr_fence[0x2]; 1745 u8 reserved_at_20c[0x3]; 1746 u8 drain_sigerr[0x1]; 1747 u8 cmdif_checksum[0x2]; 1748 u8 sigerr_cqe[0x1]; 1749 u8 reserved_at_213[0x1]; 1750 u8 wq_signature[0x1]; 1751 u8 sctr_data_cqe[0x1]; 1752 u8 reserved_at_216[0x1]; 1753 u8 sho[0x1]; 1754 u8 tph[0x1]; 1755 u8 rf[0x1]; 1756 u8 dct[0x1]; 1757 u8 qos[0x1]; 1758 u8 eth_net_offloads[0x1]; 1759 u8 roce[0x1]; 1760 u8 atomic[0x1]; 1761 u8 reserved_at_21f[0x1]; 1762 u8 cq_oi[0x1]; 1763 u8 cq_resize[0x1]; 1764 u8 cq_moderation[0x1]; 1765 u8 reserved_at_223[0x3]; 1766 u8 cq_eq_remap[0x1]; 1767 u8 pg[0x1]; 1768 u8 block_lb_mc[0x1]; 1769 u8 reserved_at_229[0x1]; 1770 u8 scqe_break_moderation[0x1]; 1771 u8 cq_period_start_from_cqe[0x1]; 1772 u8 cd[0x1]; 1773 u8 reserved_at_22d[0x1]; 1774 u8 apm[0x1]; 1775 u8 vector_calc[0x1]; 1776 u8 umr_ptr_rlky[0x1]; 1777 u8 imaicl[0x1]; 1778 u8 reserved_at_232[0x4]; 1779 u8 qkv[0x1]; 1780 u8 pkv[0x1]; 1781 u8 set_deth_sqpn[0x1]; 1782 u8 reserved_at_239[0x3]; 1783 u8 xrc[0x1]; 1784 u8 ud[0x1]; 1785 u8 uc[0x1]; 1786 u8 rc[0x1]; 1787 u8 uar_4k[0x1]; 1788 u8 reserved_at_241[0x8]; 1789 u8 regexp_params[0x1]; 1790 u8 uar_sz[0x6]; 1791 u8 port_selection_cap[0x1]; 1792 u8 reserved_at_251[0x7]; 1793 u8 log_pg_sz[0x8]; 1794 u8 bf[0x1]; 1795 u8 driver_version[0x1]; 1796 u8 pad_tx_eth_packet[0x1]; 1797 u8 reserved_at_263[0x8]; 1798 u8 log_bf_reg_size[0x5]; 1799 u8 reserved_at_270[0xb]; 1800 u8 lag_master[0x1]; 1801 u8 num_lag_ports[0x4]; 1802 u8 reserved_at_280[0x10]; 1803 u8 max_wqe_sz_sq[0x10]; 1804 u8 reserved_at_2a0[0xc]; 1805 u8 regexp_mmo_sq[0x1]; 1806 u8 regexp_version[0x3]; 1807 u8 max_wqe_sz_rq[0x10]; 1808 u8 max_flow_counter_31_16[0x10]; 1809 u8 max_wqe_sz_sq_dc[0x10]; 1810 u8 reserved_at_2e0[0x7]; 1811 u8 max_qp_mcg[0x19]; 1812 u8 reserved_at_300[0x10]; 1813 u8 flow_counter_bulk_alloc[0x08]; 1814 u8 log_max_mcg[0x8]; 1815 u8 reserved_at_320[0x3]; 1816 u8 log_max_transport_domain[0x5]; 1817 u8 reserved_at_328[0x3]; 1818 u8 log_max_pd[0x5]; 1819 u8 reserved_at_330[0xb]; 1820 u8 log_max_xrcd[0x5]; 1821 u8 nic_receive_steering_discard[0x1]; 1822 u8 receive_discard_vport_down[0x1]; 1823 u8 transmit_discard_vport_down[0x1]; 1824 u8 reserved_at_343[0x5]; 1825 u8 log_max_flow_counter_bulk[0x8]; 1826 u8 max_flow_counter_15_0[0x10]; 1827 u8 modify_tis[0x1]; 1828 u8 flow_counters_dump[0x1]; 1829 u8 reserved_at_360[0x1]; 1830 u8 log_max_rq[0x5]; 1831 u8 reserved_at_368[0x3]; 1832 u8 log_max_sq[0x5]; 1833 u8 reserved_at_370[0x3]; 1834 u8 log_max_tir[0x5]; 1835 u8 reserved_at_378[0x3]; 1836 u8 log_max_tis[0x5]; 1837 u8 basic_cyclic_rcv_wqe[0x1]; 1838 u8 reserved_at_381[0x1]; 1839 u8 mem_rq_rmp[0x1]; 1840 u8 log_max_rmp[0x5]; 1841 u8 reserved_at_388[0x3]; 1842 u8 log_max_rqt[0x5]; 1843 u8 reserved_at_390[0x3]; 1844 u8 log_max_rqt_size[0x5]; 1845 u8 reserved_at_398[0x3]; 1846 u8 log_max_tis_per_sq[0x5]; 1847 u8 ext_stride_num_range[0x1]; 1848 u8 reserved_at_3a1[0x2]; 1849 u8 log_max_stride_sz_rq[0x5]; 1850 u8 reserved_at_3a8[0x3]; 1851 u8 log_min_stride_sz_rq[0x5]; 1852 u8 reserved_at_3b0[0x3]; 1853 u8 log_max_stride_sz_sq[0x5]; 1854 u8 reserved_at_3b8[0x3]; 1855 u8 log_min_stride_sz_sq[0x5]; 1856 u8 hairpin[0x1]; 1857 u8 reserved_at_3c1[0x2]; 1858 u8 log_max_hairpin_queues[0x5]; 1859 u8 reserved_at_3c8[0x3]; 1860 u8 log_max_hairpin_wq_data_sz[0x5]; 1861 u8 reserved_at_3d0[0x3]; 1862 u8 log_max_hairpin_num_packets[0x5]; 1863 u8 reserved_at_3d8[0x3]; 1864 u8 log_max_wq_sz[0x5]; 1865 u8 nic_vport_change_event[0x1]; 1866 u8 disable_local_lb_uc[0x1]; 1867 u8 disable_local_lb_mc[0x1]; 1868 u8 log_min_hairpin_wq_data_sz[0x5]; 1869 u8 reserved_at_3e8[0x3]; 1870 u8 log_max_vlan_list[0x5]; 1871 u8 reserved_at_3f0[0x1]; 1872 u8 aes_xts_single_block_le_tweak[1]; 1873 u8 aes_xts_multi_block_be_tweak[1]; 1874 u8 log_max_current_mc_list[0x5]; 1875 u8 reserved_at_3f8[0x3]; 1876 u8 log_max_current_uc_list[0x5]; 1877 u8 general_obj_types[0x40]; 1878 u8 sq_ts_format[0x2]; 1879 u8 rq_ts_format[0x2]; 1880 u8 steering_format_version[0x4]; 1881 u8 reserved_at_448[0x18]; 1882 u8 reserved_at_460[0x8]; 1883 u8 aes_xts[0x1]; 1884 u8 crypto[0x1]; 1885 u8 ipsec_offload[0x1]; 1886 u8 reserved_at_46b[0x5]; 1887 u8 max_num_eqs[0x10]; 1888 u8 reserved_at_480[0x3]; 1889 u8 log_max_l2_table[0x5]; 1890 u8 reserved_at_488[0x8]; 1891 u8 log_uar_page_sz[0x10]; 1892 u8 reserved_at_4a0[0x20]; 1893 u8 device_frequency_mhz[0x20]; 1894 u8 device_frequency_khz[0x20]; 1895 u8 reserved_at_500[0x20]; 1896 u8 num_of_uars_per_page[0x20]; 1897 u8 flex_parser_protocols[0x20]; 1898 u8 max_geneve_tlv_options[0x8]; 1899 u8 geneve_tlv_sample[0x1]; 1900 u8 geneve_tlv_option_offset[0x1]; 1901 u8 reserved_at_56a[0x1]; 1902 u8 max_geneve_tlv_option_data_len[0x5]; 1903 u8 flex_parser_header_modify[0x1]; 1904 u8 reserved_at_571[0x2]; 1905 u8 log_max_guaranteed_connections[0x5]; 1906 u8 driver_version_before_init_hca[0x1]; 1907 u8 adv_virtualization[0x1]; 1908 u8 reserved_at_57a[0x1]; 1909 u8 log_max_dct_connections[0x5]; 1910 u8 log_max_atomic_size_qp[0x8]; 1911 u8 reserved_at_587[0x3]; 1912 u8 log_max_dci_stream_channels[0x5]; 1913 u8 reserved_at_58f[0x3]; 1914 u8 log_max_dci_errored_streams[0x5]; 1915 u8 log_max_atomic_dize_dc[0x8]; 1916 u8 max_multi_user_ggroup_size[0x10]; 1917 u8 enhanced_cqe_compression[0x1]; 1918 u8 reserved_at_5b0[0x1]; 1919 u8 crossing_vhca_mkey[0x1]; 1920 u8 log_max_dek[0x5]; 1921 u8 reserved_at_5b7[0x1]; 1922 u8 mini_cqe_resp_l3_l4_tag[0x1]; 1923 u8 mini_cqe_resp_flow_tag[0x1]; 1924 u8 reserved_at_5ba[0x1]; 1925 u8 mini_cqe_resp_stride_index[0x1]; 1926 u8 cqe_128_always[0x1]; 1927 u8 cqe_compression_128[0x1]; 1928 u8 cqe_compression[0x1]; 1929 u8 cqe_compression_timeout[0x10]; 1930 u8 cqe_compression_max_num[0x10]; 1931 u8 reserved_at_5e0[0x8]; 1932 u8 flex_parser_id_gtpu_dw_0[0x4]; 1933 u8 reserved_at_5ec[0x4]; 1934 u8 tag_matching[0x1]; 1935 u8 rndv_offload_rc[0x1]; 1936 u8 rndv_offload_dc[0x1]; 1937 u8 log_tag_matching_list_sz[0x5]; 1938 u8 reserved_at_5f8[0x3]; 1939 u8 log_max_xrq[0x5]; 1940 u8 affiliate_nic_vport_criteria[0x8]; 1941 u8 native_port_num[0x8]; 1942 u8 num_vhca_ports[0x8]; 1943 u8 flex_parser_id_gtpu_teid[0x4]; 1944 u8 reserved_at_61c[0x2]; 1945 u8 sw_owner_id[0x1]; 1946 u8 reserved_at_61f[0x6C]; 1947 u8 wait_on_data[0x1]; 1948 u8 wait_on_time[0x1]; 1949 u8 reserved_at_68d[0x37]; 1950 u8 flex_parser_id_geneve_opt_0[0x4]; 1951 u8 flex_parser_id_icmp_dw1[0x4]; 1952 u8 flex_parser_id_icmp_dw0[0x4]; 1953 u8 flex_parser_id_icmpv6_dw1[0x4]; 1954 u8 flex_parser_id_icmpv6_dw0[0x4]; 1955 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1956 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1957 u8 reserved_at_6e0[0x20]; 1958 u8 flex_parser_id_gtpu_dw_2[0x4]; 1959 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1960 u8 reserved_at_708[0x40]; 1961 u8 dma_mmo_qp[0x1]; 1962 u8 regexp_mmo_qp[0x1]; 1963 u8 compress_mmo_qp[0x1]; 1964 u8 decompress_deflate_v1[0x1]; 1965 u8 reserved_at_74c[0x4]; 1966 u8 decompress_deflate_v2[0x1]; 1967 u8 reserved_at_751[0xf]; 1968 u8 reserved_at_760[0x3]; 1969 u8 log_max_num_header_modify_argument[0x5]; 1970 u8 log_header_modify_argument_granularity_offset[0x4]; 1971 u8 log_header_modify_argument_granularity[0x4]; 1972 u8 reserved_at_770[0x3]; 1973 u8 log_header_modify_argument_max_alloc[0x5]; 1974 u8 reserved_at_778[0x8]; 1975 u8 reserved_at_780[0x40]; 1976 u8 match_definer_format_supported[0x40]; 1977 }; 1978 1979 struct mlx5_ifc_qos_cap_bits { 1980 u8 packet_pacing[0x1]; 1981 u8 esw_scheduling[0x1]; 1982 u8 esw_bw_share[0x1]; 1983 u8 esw_rate_limit[0x1]; 1984 u8 reserved_at_4[0x1]; 1985 u8 packet_pacing_burst_bound[0x1]; 1986 u8 packet_pacing_typical_size[0x1]; 1987 u8 flow_meter_old[0x1]; 1988 u8 reserved_at_8[0x8]; 1989 u8 log_max_flow_meter[0x8]; 1990 u8 flow_meter_reg_id[0x8]; 1991 u8 wqe_rate_pp[0x1]; 1992 u8 reserved_at_25[0x7]; 1993 u8 flow_meter[0x1]; 1994 u8 reserved_at_2e[0x17]; 1995 u8 packet_pacing_max_rate[0x20]; 1996 u8 packet_pacing_min_rate[0x20]; 1997 u8 reserved_at_80[0x10]; 1998 u8 packet_pacing_rate_table_size[0x10]; 1999 u8 esw_element_type[0x10]; 2000 u8 esw_tsar_type[0x10]; 2001 u8 reserved_at_c0[0x10]; 2002 u8 max_qos_para_vport[0x10]; 2003 u8 max_tsar_bw_share[0x20]; 2004 u8 nic_element_type[0x10]; 2005 u8 nic_tsar_type[0x10]; 2006 u8 reserved_at_120[0x3]; 2007 u8 log_meter_aso_granularity[0x5]; 2008 u8 reserved_at_128[0x3]; 2009 u8 log_meter_aso_max_alloc[0x5]; 2010 u8 reserved_at_130[0x3]; 2011 u8 log_max_num_meter_aso[0x5]; 2012 u8 reserved_at_138[0x6b0]; 2013 }; 2014 2015 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 2016 u8 csum_cap[0x1]; 2017 u8 vlan_cap[0x1]; 2018 u8 lro_cap[0x1]; 2019 u8 lro_psh_flag[0x1]; 2020 u8 lro_time_stamp[0x1]; 2021 u8 lro_max_msg_sz_mode[0x2]; 2022 u8 wqe_vlan_insert[0x1]; 2023 u8 self_lb_en_modifiable[0x1]; 2024 u8 self_lb_mc[0x1]; 2025 u8 self_lb_uc[0x1]; 2026 u8 max_lso_cap[0x5]; 2027 u8 multi_pkt_send_wqe[0x2]; 2028 u8 wqe_inline_mode[0x2]; 2029 u8 rss_ind_tbl_cap[0x4]; 2030 u8 reg_umr_sq[0x1]; 2031 u8 scatter_fcs[0x1]; 2032 u8 enhanced_multi_pkt_send_wqe[0x1]; 2033 u8 tunnel_lso_const_out_ip_id[0x1]; 2034 u8 tunnel_lro_gre[0x1]; 2035 u8 tunnel_lro_vxlan[0x1]; 2036 u8 tunnel_stateless_gre[0x1]; 2037 u8 tunnel_stateless_vxlan[0x1]; 2038 u8 swp[0x1]; 2039 u8 swp_csum[0x1]; 2040 u8 swp_lso[0x1]; 2041 u8 reserved_at_23[0x8]; 2042 u8 tunnel_stateless_gtp[0x1]; 2043 u8 reserved_at_25[0x2]; 2044 u8 tunnel_stateless_vxlan_gpe_nsh[0x1]; 2045 u8 reserved_at_28[0x1]; 2046 u8 max_vxlan_udp_ports[0x8]; 2047 u8 reserved_at_38[0x6]; 2048 u8 max_geneve_opt_len[0x1]; 2049 u8 tunnel_stateless_geneve_rx[0x1]; 2050 u8 reserved_at_40[0x10]; 2051 u8 lro_min_mss_size[0x10]; 2052 u8 reserved_at_60[0x120]; 2053 u8 lro_timer_supported_periods[4][0x20]; 2054 u8 reserved_at_200[0x600]; 2055 }; 2056 2057 enum { 2058 MLX5_VIRTQ_TYPE_SPLIT = 0, 2059 MLX5_VIRTQ_TYPE_PACKED = 1, 2060 }; 2061 2062 enum { 2063 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0, 2064 MLX5_VIRTQ_EVENT_MODE_QP = 1, 2065 MLX5_VIRTQ_EVENT_MODE_MSIX = 2, 2066 }; 2067 2068 struct mlx5_ifc_virtio_emulation_cap_bits { 2069 u8 desc_tunnel_offload_type[0x1]; 2070 u8 eth_frame_offload_type[0x1]; 2071 u8 virtio_version_1_0[0x1]; 2072 u8 tso_ipv4[0x1]; 2073 u8 tso_ipv6[0x1]; 2074 u8 tx_csum[0x1]; 2075 u8 rx_csum[0x1]; 2076 u8 reserved_at_7[0x1][0x9]; 2077 u8 event_mode[0x8]; 2078 u8 virtio_queue_type[0x8]; 2079 u8 reserved_at_20[0x13]; 2080 u8 log_doorbell_stride[0x5]; 2081 u8 vnet_modify_ext[0x1]; 2082 u8 virtio_net_q_addr_modify[0x1]; 2083 u8 virtio_q_index_modify[0x1]; 2084 u8 log_doorbell_bar_size[0x5]; 2085 u8 doorbell_bar_offset[0x40]; 2086 u8 reserved_at_80[0x8]; 2087 u8 max_num_virtio_queues[0x18]; 2088 u8 reserved_at_a0[0x60]; 2089 u8 umem_1_buffer_param_a[0x20]; 2090 u8 umem_1_buffer_param_b[0x20]; 2091 u8 umem_2_buffer_param_a[0x20]; 2092 u8 umem_2_buffer_param_b[0x20]; 2093 u8 umem_3_buffer_param_a[0x20]; 2094 u8 umem_3_buffer_param_b[0x20]; 2095 u8 reserved_at_1c0[0x620]; 2096 }; 2097 2098 /** 2099 * PARSE_GRAPH_NODE Capabilities Field Descriptions 2100 */ 2101 struct mlx5_ifc_parse_graph_node_cap_bits { 2102 u8 node_in[0x20]; 2103 u8 node_out[0x20]; 2104 u8 header_length_mode[0x10]; 2105 u8 sample_offset_mode[0x10]; 2106 u8 max_num_arc_in[0x08]; 2107 u8 max_num_arc_out[0x08]; 2108 u8 max_num_sample[0x08]; 2109 u8 reserved_at_78[0x03]; 2110 u8 parse_graph_anchor[0x1]; 2111 u8 reserved_at_7c[0x01]; 2112 u8 sample_tunnel_inner2[0x1]; 2113 u8 zero_size_supported[0x1]; 2114 u8 sample_id_in_out[0x1]; 2115 u8 max_base_header_length[0x10]; 2116 u8 reserved_at_90[0x08]; 2117 u8 max_sample_base_offset[0x08]; 2118 u8 max_next_header_offset[0x10]; 2119 u8 reserved_at_b0[0x08]; 2120 u8 header_length_mask_width[0x08]; 2121 }; 2122 2123 struct mlx5_ifc_flow_table_prop_layout_bits { 2124 u8 ft_support[0x1]; 2125 u8 flow_tag[0x1]; 2126 u8 flow_counter[0x1]; 2127 u8 flow_modify_en[0x1]; 2128 u8 modify_root[0x1]; 2129 u8 identified_miss_table[0x1]; 2130 u8 flow_table_modify[0x1]; 2131 u8 reformat[0x1]; 2132 u8 decap[0x1]; 2133 u8 reset_root_to_default[0x1]; 2134 u8 pop_vlan[0x1]; 2135 u8 push_vlan[0x1]; 2136 u8 fpga_vendor_acceleration[0x1]; 2137 u8 pop_vlan_2[0x1]; 2138 u8 push_vlan_2[0x1]; 2139 u8 reformat_and_vlan_action[0x1]; 2140 u8 modify_and_vlan_action[0x1]; 2141 u8 sw_owner[0x1]; 2142 u8 reformat_l3_tunnel_to_l2[0x1]; 2143 u8 reformat_l2_to_l3_tunnel[0x1]; 2144 u8 reformat_and_modify_action[0x1]; 2145 u8 reserved_at_15[0x9]; 2146 u8 sw_owner_v2[0x1]; 2147 u8 reserved_at_1f[0x1]; 2148 u8 reserved_at_20[0x2]; 2149 u8 log_max_ft_size[0x6]; 2150 u8 log_max_modify_header_context[0x8]; 2151 u8 max_modify_header_actions[0x8]; 2152 u8 max_ft_level[0x8]; 2153 u8 reserved_at_40[0x8]; 2154 u8 log_max_ft_sampler_num[8]; 2155 u8 metadata_reg_b_width[0x8]; 2156 u8 metadata_reg_a_width[0x8]; 2157 u8 reserved_at_60[0xa]; 2158 u8 reparse[0x1]; 2159 u8 reserved_at_6b[0x1]; 2160 u8 cross_vhca_object[0x1]; 2161 u8 reformat_l2_to_l3_audp_tunnel[0x1]; 2162 u8 reformat_l3_audp_tunnel_to_l2[0x1]; 2163 u8 ignore_flow_level_rtc_valid[0x1]; 2164 u8 reserved_at_70[0x8]; 2165 u8 log_max_ft_num[0x8]; 2166 u8 reserved_at_80[0x10]; 2167 u8 log_max_flow_counter[0x8]; 2168 u8 log_max_destination[0x8]; 2169 u8 reserved_at_a0[0x18]; 2170 u8 log_max_flow[0x8]; 2171 u8 reserved_at_c0[0x140]; 2172 }; 2173 2174 struct mlx5_ifc_roce_caps_bits { 2175 u8 reserved_0[0x1e]; 2176 u8 qp_ts_format[0x2]; 2177 u8 reserved_at_20[0xa0]; 2178 u8 r_roce_max_src_udp_port[0x10]; 2179 u8 r_roce_min_src_udp_port[0x10]; 2180 u8 reserved_at_e0[0x720]; 2181 }; 2182 2183 struct mlx5_ifc_ft_fields_support_bits { 2184 /* set_action_field_support */ 2185 u8 outer_dmac[0x1]; 2186 u8 outer_smac[0x1]; 2187 u8 outer_ether_type[0x1]; 2188 u8 reserved_at_3[0x1]; 2189 u8 outer_first_prio[0x1]; 2190 u8 outer_first_cfi[0x1]; 2191 u8 outer_first_vid[0x1]; 2192 u8 reserved_at_7[0x1]; 2193 u8 outer_second_prio[0x1]; 2194 u8 outer_second_cfi[0x1]; 2195 u8 outer_second_vid[0x1]; 2196 u8 reserved_at_b[0x1]; 2197 u8 outer_sip[0x1]; 2198 u8 outer_dip[0x1]; 2199 u8 outer_frag[0x1]; 2200 u8 outer_ip_protocol[0x1]; 2201 u8 outer_ip_ecn[0x1]; 2202 u8 outer_ip_dscp[0x1]; 2203 u8 outer_udp_sport[0x1]; 2204 u8 outer_udp_dport[0x1]; 2205 u8 outer_tcp_sport[0x1]; 2206 u8 outer_tcp_dport[0x1]; 2207 u8 outer_tcp_flags[0x1]; 2208 u8 outer_gre_protocol[0x1]; 2209 u8 outer_gre_key[0x1]; 2210 u8 outer_vxlan_vni[0x1]; 2211 u8 reserved_at_1a[0x5]; 2212 u8 source_eswitch_port[0x1]; /* end of DW0 */ 2213 u8 inner_dmac[0x1]; 2214 u8 inner_smac[0x1]; 2215 u8 inner_ether_type[0x1]; 2216 u8 reserved_at_23[0x1]; 2217 u8 inner_first_prio[0x1]; 2218 u8 inner_first_cfi[0x1]; 2219 u8 inner_first_vid[0x1]; 2220 u8 reserved_at_27[0x1]; 2221 u8 inner_second_prio[0x1]; 2222 u8 inner_second_cfi[0x1]; 2223 u8 inner_second_vid[0x1]; 2224 u8 reserved_at_2b[0x1]; 2225 u8 inner_sip[0x1]; 2226 u8 inner_dip[0x1]; 2227 u8 inner_frag[0x1]; 2228 u8 inner_ip_protocol[0x1]; 2229 u8 inner_ip_ecn[0x1]; 2230 u8 inner_ip_dscp[0x1]; 2231 u8 inner_udp_sport[0x1]; 2232 u8 inner_udp_dport[0x1]; 2233 u8 inner_tcp_sport[0x1]; 2234 u8 inner_tcp_dport[0x1]; 2235 u8 inner_tcp_flags[0x1]; 2236 u8 reserved_at_37[0x9]; /* end of DW1 */ 2237 u8 reserved_at_40[0x20]; /* end of DW2 */ 2238 u8 reserved_at_60[0x18]; 2239 union { 2240 struct { 2241 u8 metadata_reg_c_7[0x1]; 2242 u8 metadata_reg_c_6[0x1]; 2243 u8 metadata_reg_c_5[0x1]; 2244 u8 metadata_reg_c_4[0x1]; 2245 u8 metadata_reg_c_3[0x1]; 2246 u8 metadata_reg_c_2[0x1]; 2247 u8 metadata_reg_c_1[0x1]; 2248 u8 metadata_reg_c_0[0x1]; 2249 }; 2250 u8 metadata_reg_c_x[0x8]; 2251 }; /* end of DW3 */ 2252 /* set_action_field_support_2 */ 2253 u8 reserved_at_80[0x37]; 2254 u8 outer_ipv6_traffic_class[0x1]; 2255 u8 reserved_at_B8[0x48]; 2256 /* add_action_field_support */ 2257 u8 reserved_at_100[0x80]; 2258 /* add_action_field_support_2 */ 2259 u8 reserved_at_180[0x80]; 2260 /* copy_action_field_support */ 2261 u8 reserved_at_200[0x80]; 2262 /* copy_action_field_support_2 */ 2263 u8 reserved_at_280[0x80]; 2264 u8 reserved_at_300[0x100]; 2265 }; 2266 2267 /* 2268 * Table 1872 - Flow Table Fields Supported 2 Format 2269 */ 2270 struct mlx5_ifc_ft_fields_support_2_bits { 2271 u8 reserved_at_0[0xa]; 2272 u8 lag_rx_port_affinity[0x1]; 2273 u8 reserved_at_c[0x2]; 2274 u8 hash_result[0x1]; 2275 u8 reserved_at_e[0x1]; 2276 u8 tunnel_header_2_3[0x1]; 2277 u8 tunnel_header_0_1[0x1]; 2278 u8 macsec_syndrome[0x1]; 2279 u8 macsec_tag[0x1]; 2280 u8 outer_lrh_sl[0x1]; 2281 u8 inner_ipv4_ihl[0x1]; 2282 u8 outer_ipv4_ihl[0x1]; 2283 u8 psp_syndrome[0x1]; 2284 u8 inner_l3_ok[0x1]; 2285 u8 inner_l4_ok[0x1]; 2286 u8 outer_l3_ok[0x1]; 2287 u8 outer_l4_ok[0x1]; 2288 u8 psp_header[0x1]; 2289 u8 inner_ipv4_checksum_ok[0x1]; 2290 u8 inner_l4_checksum_ok[0x1]; 2291 u8 outer_ipv4_checksum_ok[0x1]; 2292 u8 outer_l4_checksum_ok[0x1]; /* end of DW0 */ 2293 u8 reserved_at_20[0x17]; 2294 u8 outer_ipv6_traffic_class[0x1]; 2295 union { 2296 struct { 2297 u8 metadata_reg_c_15[0x1]; 2298 u8 metadata_reg_c_14[0x1]; 2299 u8 metadata_reg_c_13[0x1]; 2300 u8 metadata_reg_c_12[0x1]; 2301 u8 metadata_reg_c_11[0x1]; 2302 u8 metadata_reg_c_10[0x1]; 2303 u8 metadata_reg_c_9[0x1]; 2304 u8 metadata_reg_c_8[0x1]; 2305 }; 2306 u8 metadata_reg_c_8_15[0x8]; 2307 }; /* end of DW1 */ 2308 u8 reserved_at_40[0x40]; 2309 }; 2310 2311 struct mlx5_ifc_flow_table_nic_cap_bits { 2312 u8 reserved_at_0[0x200]; 2313 struct mlx5_ifc_flow_table_prop_layout_bits 2314 flow_table_properties_nic_receive; 2315 struct mlx5_ifc_flow_table_prop_layout_bits 2316 flow_table_properties_nic_receive_rdma; 2317 struct mlx5_ifc_flow_table_prop_layout_bits 2318 flow_table_properties_nic_receive_sniffer; 2319 struct mlx5_ifc_flow_table_prop_layout_bits 2320 flow_table_properties_nic_transmit; 2321 struct mlx5_ifc_flow_table_prop_layout_bits 2322 flow_table_properties_nic_transmit_rdma; 2323 struct mlx5_ifc_flow_table_prop_layout_bits 2324 flow_table_properties_nic_transmit_sniffer; 2325 u8 reserved_at_e00[0x200]; 2326 struct mlx5_ifc_ft_fields_support_bits 2327 ft_header_modify_nic_receive; 2328 struct mlx5_ifc_ft_fields_support_2_bits 2329 ft_field_support_2_nic_receive; 2330 u8 reserved_at_1480[0x280]; 2331 struct mlx5_ifc_ft_fields_support_2_bits 2332 ft_field_support_2_nic_transmit; 2333 u8 reserved_at_1780[0x480]; 2334 struct mlx5_ifc_ft_fields_support_bits 2335 ft_header_modify_nic_transmit; 2336 u8 reserved_at_2000[0x6000]; 2337 }; 2338 2339 struct mlx5_ifc_flow_table_esw_cap_bits { 2340 u8 reserved_at_0[0x800]; 2341 struct mlx5_ifc_ft_fields_support_bits ft_header_modify_esw_fdb; 2342 u8 reserved_at_C00[0x800]; 2343 struct mlx5_ifc_ft_fields_support_2_bits 2344 ft_field_support_2_esw_fdb; 2345 u8 reserved_at_1480[0x6b80]; 2346 }; 2347 2348 enum mlx5_ifc_cross_vhca_object_to_object_supported_types { 2349 MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR = 1 << 10, 2350 MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT = 1 << 11, 2351 MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT = 1 << 12, 2352 MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC = 1 << 13, 2353 }; 2354 2355 enum mlx5_ifc_cross_vhca_allowed_objects_types { 2356 MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR = 1 << 0x8, 2357 MLX5_CROSS_VHCA_ALLOWED_OBJS_FT = 1 << 0x9, 2358 MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC = 1 << 0xa, 2359 }; 2360 2361 enum { 2362 MLX5_GENERATE_WQE_TYPE_FLOW_UPDATE = 1 << 1, 2363 }; 2364 2365 enum { 2366 MLX5_FLOW_TABLE_HASH_TYPE_CRC32, 2367 }; 2368 /* 2369 * HCA Capabilities 2 2370 */ 2371 struct mlx5_ifc_cmd_hca_cap_2_bits { 2372 u8 reserved_at_0[0x80]; /* End of DW4. */ 2373 u8 reserved_at_80[0x3]; 2374 u8 max_num_prog_sample_field[0x5]; 2375 u8 reserved_at_88[0x3]; 2376 u8 log_max_num_reserved_qpn[0x5]; 2377 u8 reserved_at_90[0x3]; 2378 u8 log_reserved_qpn_granularity[0x5]; 2379 u8 reserved_at_98[0x3]; 2380 u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */ 2381 u8 max_reformat_insert_size[0x8]; 2382 u8 max_reformat_insert_offset[0x8]; 2383 u8 max_reformat_remove_size[0x8]; 2384 u8 max_reformat_remove_offset[0x8]; /* End of DW6. */ 2385 u8 reserved_at_c0[0x3]; 2386 u8 log_min_stride_wqe_sz[0x5]; 2387 u8 reserved_at_c8[0x3]; 2388 u8 log_conn_track_granularity[0x5]; 2389 u8 reserved_at_d0[0x3]; 2390 u8 log_conn_track_max_alloc[0x5]; 2391 u8 reserved_at_d8[0x3]; 2392 u8 log_max_conn_track_offload[0x5]; /* End of DW7. */ 2393 u8 cross_vhca_object_to_object_supported[0x20]; 2394 u8 allowed_object_for_other_vhca_access_high[0x20]; 2395 u8 allowed_object_for_other_vhca_access[0x20]; 2396 u8 reserved_at_140[0x20]; 2397 u8 reserved_at_160[0x3]; 2398 u8 hairpin_sq_wqe_bb_size[0x5]; 2399 u8 hairpin_sq_wq_in_host_mem[0x1]; 2400 u8 hairpin_data_buffer_locked[0x1]; 2401 u8 reserved_at_16a[0x16]; 2402 u8 reserved_at_180[0x20]; 2403 u8 reserved_at_1a0[0xa]; 2404 u8 format_select_dw_8_6_ext[0x1]; 2405 u8 reserved_at_1ac[0x15]; 2406 u8 general_obj_types_127_64[0x40]; 2407 u8 reserved_at_200[0x53]; 2408 u8 flow_counter_bulk_log_max_alloc[0x5]; 2409 u8 reserved_at_258[0x3]; 2410 u8 flow_counter_bulk_log_granularity[0x5]; 2411 u8 reserved_at_260[0x20]; 2412 u8 format_select_dw_gtpu_dw_0[0x8]; 2413 u8 format_select_dw_gtpu_dw_1[0x8]; 2414 u8 format_select_dw_gtpu_dw_2[0x8]; 2415 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2416 u8 generate_wqe_type[0x20]; 2417 u8 reserved_at_2c0[0x160]; 2418 u8 reserved_at_420[0x18]; 2419 u8 encap_entropy_hash_type[0x4]; 2420 u8 flow_table_hash_type[0x4]; 2421 u8 reserved_at_440[0x3c0]; 2422 }; 2423 2424 struct mlx5_ifc_esw_cap_bits { 2425 u8 reserved_at_0[0x1d]; 2426 u8 merged_eswitch[0x1]; 2427 u8 reserved_at_1e[0x2]; 2428 2429 u8 reserved_at_20[0x40]; 2430 2431 u8 esw_manager_vport_number_valid[0x1]; 2432 u8 reserved_at_61[0xf]; 2433 u8 esw_manager_vport_number[0x10]; 2434 2435 u8 reserved_at_80[0x780]; 2436 }; 2437 2438 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 2439 u8 reserved_at_0[0x3]; 2440 u8 log_max_num_ste[0x5]; 2441 u8 reserved_at_8[0x3]; 2442 u8 log_max_num_stc[0x5]; 2443 u8 reserved_at_10[0x3]; 2444 u8 log_max_num_rtc[0x5]; 2445 u8 reserved_at_18[0x3]; 2446 u8 log_max_num_header_modify_pattern[0x5]; 2447 u8 rtc_hash_split_table[0x1]; 2448 u8 rtc_linear_lookup_table[0x1]; 2449 u8 reserved_at_22[0x1]; 2450 u8 stc_alloc_log_granularity[0x5]; 2451 u8 reserved_at_28[0x3]; 2452 u8 stc_alloc_log_max[0x5]; 2453 u8 reserved_at_30[0x3]; 2454 u8 ste_alloc_log_granularity[0x5]; 2455 u8 reserved_at_38[0x3]; 2456 u8 ste_alloc_log_max[0x5]; 2457 u8 reserved_at_40[0xb]; 2458 u8 rtc_reparse_mode[0x5]; 2459 u8 reserved_at_50[0x3]; 2460 u8 rtc_index_mode[0x5]; 2461 u8 reserved_at_58[0x3]; 2462 u8 rtc_log_depth_max[0x5]; 2463 u8 reserved_at_60[0x8]; 2464 u8 max_header_modify_pattern_length[0x8]; 2465 u8 ste_format[0x10]; 2466 u8 stc_action_type[0x80]; 2467 u8 header_insert_type[0x10]; 2468 u8 header_remove_type[0x10]; 2469 u8 trivial_match_definer[0x20]; 2470 u8 reserved_at_140[0x1b]; 2471 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 2472 u8 reserved_at_160[0x18]; 2473 u8 access_index_mode[0x8]; 2474 u8 reserved_at_180[0x10]; 2475 u8 ste_format_gen_wqe[0x10]; 2476 u8 linear_match_definer_reg_c3[0x20]; 2477 u8 fdb_jump_to_tir_stc[0x1]; 2478 u8 reserved_at_1c1[0x1f]; 2479 }; 2480 2481 union mlx5_ifc_hca_cap_union_bits { 2482 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2483 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 2484 struct mlx5_ifc_per_protocol_networking_offload_caps_bits 2485 per_protocol_networking_offload_caps; 2486 struct mlx5_ifc_qos_cap_bits qos_cap; 2487 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps; 2488 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2489 struct mlx5_ifc_flow_table_esw_cap_bits flow_table_esw_cap; 2490 struct mlx5_ifc_esw_cap_bits esw_cap; 2491 struct mlx5_ifc_roce_caps_bits roce_caps; 2492 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 2493 u8 reserved_at_0[0x8000]; 2494 }; 2495 2496 struct mlx5_ifc_set_action_in_bits { 2497 u8 action_type[0x4]; 2498 u8 field[0xc]; 2499 u8 reserved_at_10[0x3]; 2500 u8 offset[0x5]; 2501 u8 reserved_at_18[0x3]; 2502 u8 length[0x5]; 2503 u8 data[0x20]; 2504 }; 2505 2506 struct mlx5_ifc_copy_action_in_bits { 2507 u8 action_type[0x4]; 2508 u8 src_field[0xc]; 2509 u8 reserved_at_10[0x3]; 2510 u8 src_offset[0x5]; 2511 u8 reserved_at_18[0x3]; 2512 u8 length[0x5]; 2513 u8 reserved_at_20[0x4]; 2514 u8 dst_field[0xc]; 2515 u8 reserved_at_30[0x3]; 2516 u8 dst_offset[0x5]; 2517 u8 reserved_at_38[0x8]; 2518 }; 2519 2520 struct mlx5_ifc_query_hca_cap_out_bits { 2521 u8 status[0x8]; 2522 u8 reserved_at_8[0x18]; 2523 u8 syndrome[0x20]; 2524 u8 reserved_at_40[0x40]; 2525 union mlx5_ifc_hca_cap_union_bits capability; 2526 }; 2527 2528 struct mlx5_ifc_query_hca_cap_in_bits { 2529 u8 opcode[0x10]; 2530 u8 reserved_at_10[0x10]; 2531 u8 reserved_at_20[0x10]; 2532 u8 op_mod[0x10]; 2533 u8 reserved_at_40[0x40]; 2534 }; 2535 2536 struct mlx5_ifc_mac_address_layout_bits { 2537 u8 reserved_at_0[0x10]; 2538 u8 mac_addr_47_32[0x10]; 2539 u8 mac_addr_31_0[0x20]; 2540 }; 2541 2542 struct mlx5_ifc_nic_vport_context_bits { 2543 u8 reserved_at_0[0x5]; 2544 u8 min_wqe_inline_mode[0x3]; 2545 u8 reserved_at_8[0x15]; 2546 u8 disable_mc_local_lb[0x1]; 2547 u8 disable_uc_local_lb[0x1]; 2548 u8 roce_en[0x1]; 2549 u8 arm_change_event[0x1]; 2550 u8 reserved_at_21[0x1a]; 2551 u8 event_on_mtu[0x1]; 2552 u8 event_on_promisc_change[0x1]; 2553 u8 event_on_vlan_change[0x1]; 2554 u8 event_on_mc_address_change[0x1]; 2555 u8 event_on_uc_address_change[0x1]; 2556 u8 reserved_at_40[0xc]; 2557 u8 affiliation_criteria[0x4]; 2558 u8 affiliated_vhca_id[0x10]; 2559 u8 reserved_at_60[0xd0]; 2560 u8 mtu[0x10]; 2561 u8 system_image_guid[0x40]; 2562 u8 port_guid[0x40]; 2563 u8 node_guid[0x40]; 2564 u8 reserved_at_200[0x140]; 2565 u8 qkey_violation_counter[0x10]; 2566 u8 reserved_at_350[0x430]; 2567 u8 promisc_uc[0x1]; 2568 u8 promisc_mc[0x1]; 2569 u8 promisc_all[0x1]; 2570 u8 reserved_at_783[0x2]; 2571 u8 allowed_list_type[0x3]; 2572 u8 reserved_at_788[0xc]; 2573 u8 allowed_list_size[0xc]; 2574 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2575 u8 reserved_at_7e0[0x20]; 2576 }; 2577 2578 struct mlx5_ifc_query_nic_vport_context_out_bits { 2579 u8 status[0x8]; 2580 u8 reserved_at_8[0x18]; 2581 u8 syndrome[0x20]; 2582 u8 reserved_at_40[0x40]; 2583 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 2584 }; 2585 2586 struct mlx5_ifc_query_nic_vport_context_in_bits { 2587 u8 opcode[0x10]; 2588 u8 reserved_at_10[0x10]; 2589 u8 reserved_at_20[0x10]; 2590 u8 op_mod[0x10]; 2591 u8 other_vport[0x1]; 2592 u8 reserved_at_41[0xf]; 2593 u8 vport_number[0x10]; 2594 u8 reserved_at_60[0x5]; 2595 u8 allowed_list_type[0x3]; 2596 u8 reserved_at_68[0x18]; 2597 }; 2598 2599 struct mlx5_ifc_tisc_bits { 2600 u8 strict_lag_tx_port_affinity[0x1]; 2601 u8 reserved_at_1[0x3]; 2602 u8 lag_tx_port_affinity[0x04]; 2603 u8 reserved_at_8[0x4]; 2604 u8 prio[0x4]; 2605 u8 reserved_at_10[0x10]; 2606 u8 reserved_at_20[0x100]; 2607 u8 reserved_at_120[0x8]; 2608 u8 transport_domain[0x18]; 2609 u8 reserved_at_140[0x8]; 2610 u8 underlay_qpn[0x18]; 2611 u8 reserved_at_160[0x3a0]; 2612 }; 2613 2614 struct mlx5_ifc_query_tis_out_bits { 2615 u8 status[0x8]; 2616 u8 reserved_at_8[0x18]; 2617 u8 syndrome[0x20]; 2618 u8 reserved_at_40[0x40]; 2619 struct mlx5_ifc_tisc_bits tis_context; 2620 }; 2621 2622 struct mlx5_ifc_query_tis_in_bits { 2623 u8 opcode[0x10]; 2624 u8 reserved_at_10[0x10]; 2625 u8 reserved_at_20[0x10]; 2626 u8 op_mod[0x10]; 2627 u8 reserved_at_40[0x8]; 2628 u8 tisn[0x18]; 2629 u8 reserved_at_60[0x20]; 2630 }; 2631 2632 /* port_select_mode definition. */ 2633 enum mlx5_lag_mode_type { 2634 MLX5_LAG_MODE_TIS = 0, 2635 MLX5_LAG_MODE_HASH = 1, 2636 }; 2637 2638 struct mlx5_ifc_lag_context_bits { 2639 u8 fdb_selection_mode[0x1]; 2640 u8 reserved_at_1[0x14]; 2641 u8 port_select_mode[0x3]; 2642 u8 reserved_at_18[0x5]; 2643 u8 lag_state[0x3]; 2644 u8 reserved_at_20[0x14]; 2645 u8 tx_remap_affinity_2[0x4]; 2646 u8 reserved_at_38[0x4]; 2647 u8 tx_remap_affinity_1[0x4]; 2648 }; 2649 2650 struct mlx5_ifc_query_lag_in_bits { 2651 u8 opcode[0x10]; 2652 u8 uid[0x10]; 2653 u8 reserved_at_20[0x10]; 2654 u8 op_mod[0x10]; 2655 u8 reserved_at_40[0x40]; 2656 }; 2657 2658 struct mlx5_ifc_query_lag_out_bits { 2659 u8 status[0x8]; 2660 u8 reserved_at_8[0x18]; 2661 u8 syndrome[0x20]; 2662 struct mlx5_ifc_lag_context_bits context; 2663 }; 2664 2665 struct mlx5_ifc_alloc_transport_domain_out_bits { 2666 u8 status[0x8]; 2667 u8 reserved_at_8[0x18]; 2668 u8 syndrome[0x20]; 2669 u8 reserved_at_40[0x8]; 2670 u8 transport_domain[0x18]; 2671 u8 reserved_at_60[0x20]; 2672 }; 2673 2674 struct mlx5_ifc_alloc_transport_domain_in_bits { 2675 u8 opcode[0x10]; 2676 u8 reserved_at_10[0x10]; 2677 u8 reserved_at_20[0x10]; 2678 u8 op_mod[0x10]; 2679 u8 reserved_at_40[0x40]; 2680 }; 2681 2682 enum { 2683 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 2684 MLX5_WQ_TYPE_CYCLIC = 0x1, 2685 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 2686 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 2687 }; 2688 2689 enum { 2690 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 2691 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 2692 }; 2693 2694 struct mlx5_ifc_wq_bits { 2695 u8 wq_type[0x4]; 2696 u8 wq_signature[0x1]; 2697 u8 end_padding_mode[0x2]; 2698 u8 cd_slave[0x1]; 2699 u8 reserved_at_8[0x18]; 2700 u8 hds_skip_first_sge[0x1]; 2701 u8 log2_hds_buf_size[0x3]; 2702 u8 reserved_at_24[0x7]; 2703 u8 page_offset[0x5]; 2704 u8 lwm[0x10]; 2705 u8 reserved_at_40[0x8]; 2706 u8 pd[0x18]; 2707 u8 reserved_at_60[0x8]; 2708 u8 uar_page[0x18]; 2709 u8 dbr_addr[0x40]; 2710 u8 hw_counter[0x20]; 2711 u8 sw_counter[0x20]; 2712 u8 reserved_at_100[0xc]; 2713 u8 log_wq_stride[0x4]; 2714 u8 reserved_at_110[0x3]; 2715 u8 log_wq_pg_sz[0x5]; 2716 u8 reserved_at_118[0x3]; 2717 u8 log_wq_sz[0x5]; 2718 u8 dbr_umem_valid[0x1]; 2719 u8 wq_umem_valid[0x1]; 2720 u8 reserved_at_122[0x1]; 2721 u8 log_hairpin_num_packets[0x5]; 2722 u8 reserved_at_128[0x3]; 2723 u8 log_hairpin_data_sz[0x5]; 2724 u8 reserved_at_130[0x4]; 2725 u8 single_wqe_log_num_of_strides[0x4]; 2726 u8 two_byte_shift_en[0x1]; 2727 u8 reserved_at_139[0x4]; 2728 u8 single_stride_log_num_of_bytes[0x3]; 2729 u8 dbr_umem_id[0x20]; 2730 u8 wq_umem_id[0x20]; 2731 u8 wq_umem_offset[0x40]; 2732 u8 reserved_at_1c0[0x440]; 2733 }; 2734 2735 enum { 2736 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2737 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2738 }; 2739 2740 enum { 2741 MLX5_RQC_STATE_RST = 0x0, 2742 MLX5_RQC_STATE_RDY = 0x1, 2743 MLX5_RQC_STATE_ERR = 0x3, 2744 }; 2745 2746 struct mlx5_ifc_rqc_bits { 2747 u8 rlky[0x1]; 2748 u8 delay_drop_en[0x1]; 2749 u8 scatter_fcs[0x1]; 2750 u8 vsd[0x1]; 2751 u8 mem_rq_type[0x4]; 2752 u8 state[0x4]; 2753 u8 reserved_at_c[0x1]; 2754 u8 flush_in_error_en[0x1]; 2755 u8 hairpin[0x1]; 2756 u8 reserved_at_f[0x6]; 2757 u8 hairpin_data_buffer_type[0x3]; 2758 u8 reserved_at_a8[0x2]; 2759 u8 ts_format[0x02]; 2760 u8 reserved_at_1c[0x4]; 2761 u8 reserved_at_20[0x8]; 2762 u8 user_index[0x18]; 2763 u8 reserved_at_40[0x8]; 2764 u8 cqn[0x18]; 2765 u8 counter_set_id[0x8]; 2766 u8 reserved_at_68[0x18]; 2767 u8 reserved_at_80[0x8]; 2768 u8 rmpn[0x18]; 2769 u8 reserved_at_a0[0x8]; 2770 u8 hairpin_peer_sq[0x18]; 2771 u8 reserved_at_c0[0x10]; 2772 u8 hairpin_peer_vhca[0x10]; 2773 u8 reserved_at_e0[0xa0]; 2774 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */ 2775 }; 2776 2777 struct mlx5_ifc_create_rq_out_bits { 2778 u8 status[0x8]; 2779 u8 reserved_at_8[0x18]; 2780 u8 syndrome[0x20]; 2781 u8 reserved_at_40[0x8]; 2782 u8 rqn[0x18]; 2783 u8 reserved_at_60[0x20]; 2784 }; 2785 2786 struct mlx5_ifc_create_rq_in_bits { 2787 u8 opcode[0x10]; 2788 u8 uid[0x10]; 2789 u8 reserved_at_20[0x10]; 2790 u8 op_mod[0x10]; 2791 u8 reserved_at_40[0xc0]; 2792 struct mlx5_ifc_rqc_bits ctx; 2793 }; 2794 2795 struct mlx5_ifc_modify_rq_out_bits { 2796 u8 status[0x8]; 2797 u8 reserved_at_8[0x18]; 2798 u8 syndrome[0x20]; 2799 u8 reserved_at_40[0x40]; 2800 }; 2801 2802 struct mlx5_ifc_query_rq_out_bits { 2803 u8 status[0x8]; 2804 u8 reserved_at_8[0x18]; 2805 u8 syndrome[0x20]; 2806 u8 reserved_at_40[0xc0]; 2807 struct mlx5_ifc_rqc_bits rq_context; 2808 }; 2809 2810 struct mlx5_ifc_query_rq_in_bits { 2811 u8 opcode[0x10]; 2812 u8 reserved_at_10[0x10]; 2813 u8 reserved_at_20[0x10]; 2814 u8 op_mod[0x10]; 2815 u8 reserved_at_40[0x8]; 2816 u8 rqn[0x18]; 2817 u8 reserved_at_60[0x20]; 2818 }; 2819 2820 enum { 2821 MLX5_RMPC_STATE_RDY = 0x1, 2822 MLX5_RMPC_STATE_ERR = 0x3, 2823 }; 2824 2825 struct mlx5_ifc_rmpc_bits { 2826 u8 reserved_at_0[0x8]; 2827 u8 state[0x4]; 2828 u8 reserved_at_c[0x14]; 2829 u8 basic_cyclic_rcv_wqe[0x1]; 2830 u8 reserved_at_21[0x1f]; 2831 u8 reserved_at_40[0x140]; 2832 struct mlx5_ifc_wq_bits wq; 2833 }; 2834 2835 struct mlx5_ifc_query_rmp_out_bits { 2836 u8 status[0x8]; 2837 u8 reserved_at_8[0x18]; 2838 u8 syndrome[0x20]; 2839 u8 reserved_at_40[0xc0]; 2840 struct mlx5_ifc_rmpc_bits rmp_context; 2841 }; 2842 2843 struct mlx5_ifc_query_rmp_in_bits { 2844 u8 opcode[0x10]; 2845 u8 reserved_at_10[0x10]; 2846 u8 reserved_at_20[0x10]; 2847 u8 op_mod[0x10]; 2848 u8 reserved_at_40[0x8]; 2849 u8 rmpn[0x18]; 2850 u8 reserved_at_60[0x20]; 2851 }; 2852 2853 struct mlx5_ifc_modify_rmp_out_bits { 2854 u8 status[0x8]; 2855 u8 reserved_at_8[0x18]; 2856 u8 syndrome[0x20]; 2857 u8 reserved_at_40[0x40]; 2858 }; 2859 2860 struct mlx5_ifc_rmp_bitmask_bits { 2861 u8 reserved_at_0[0x20]; 2862 u8 reserved_at_20[0x1f]; 2863 u8 lwm[0x1]; 2864 }; 2865 2866 struct mlx5_ifc_modify_rmp_in_bits { 2867 u8 opcode[0x10]; 2868 u8 uid[0x10]; 2869 u8 reserved_at_20[0x10]; 2870 u8 op_mod[0x10]; 2871 u8 rmp_state[0x4]; 2872 u8 reserved_at_44[0x4]; 2873 u8 rmpn[0x18]; 2874 u8 reserved_at_60[0x20]; 2875 struct mlx5_ifc_rmp_bitmask_bits bitmask; 2876 u8 reserved_at_c0[0x40]; 2877 struct mlx5_ifc_rmpc_bits ctx; 2878 }; 2879 2880 struct mlx5_ifc_create_rmp_out_bits { 2881 u8 status[0x8]; 2882 u8 reserved_at_8[0x18]; 2883 u8 syndrome[0x20]; 2884 u8 reserved_at_40[0x8]; 2885 u8 rmpn[0x18]; 2886 u8 reserved_at_60[0x20]; 2887 }; 2888 2889 struct mlx5_ifc_create_rmp_in_bits { 2890 u8 opcode[0x10]; 2891 u8 uid[0x10]; 2892 u8 reserved_at_20[0x10]; 2893 u8 op_mod[0x10]; 2894 u8 reserved_at_40[0xc0]; 2895 struct mlx5_ifc_rmpc_bits ctx; 2896 }; 2897 2898 struct mlx5_ifc_create_tis_out_bits { 2899 u8 status[0x8]; 2900 u8 reserved_at_8[0x18]; 2901 u8 syndrome[0x20]; 2902 u8 reserved_at_40[0x8]; 2903 u8 tisn[0x18]; 2904 u8 reserved_at_60[0x20]; 2905 }; 2906 2907 struct mlx5_ifc_create_tis_in_bits { 2908 u8 opcode[0x10]; 2909 u8 uid[0x10]; 2910 u8 reserved_at_20[0x10]; 2911 u8 op_mod[0x10]; 2912 u8 reserved_at_40[0xc0]; 2913 struct mlx5_ifc_tisc_bits ctx; 2914 }; 2915 2916 enum { 2917 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0, 2918 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 2919 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 2920 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 2921 }; 2922 2923 struct mlx5_ifc_modify_rq_in_bits { 2924 u8 opcode[0x10]; 2925 u8 uid[0x10]; 2926 u8 reserved_at_20[0x10]; 2927 u8 op_mod[0x10]; 2928 u8 rq_state[0x4]; 2929 u8 reserved_at_44[0x4]; 2930 u8 rqn[0x18]; 2931 u8 reserved_at_60[0x20]; 2932 u8 modify_bitmask[0x40]; 2933 u8 reserved_at_c0[0x40]; 2934 struct mlx5_ifc_rqc_bits ctx; 2935 }; 2936 2937 enum { 2938 MLX5_L3_PROT_TYPE_IPV4 = 0, 2939 MLX5_L3_PROT_TYPE_IPV6 = 1, 2940 }; 2941 2942 enum { 2943 MLX5_L4_PROT_TYPE_TCP = 0, 2944 MLX5_L4_PROT_TYPE_UDP = 1, 2945 }; 2946 2947 enum { 2948 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2949 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2950 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2951 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2952 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2953 }; 2954 2955 struct mlx5_ifc_rx_hash_field_select_bits { 2956 u8 l3_prot_type[0x1]; 2957 u8 l4_prot_type[0x1]; 2958 u8 selected_fields[0x1e]; 2959 }; 2960 2961 enum { 2962 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2963 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2964 }; 2965 2966 enum { 2967 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2968 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2969 }; 2970 2971 enum { 2972 MLX5_RX_HASH_FN_NONE = 0x0, 2973 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2974 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2975 }; 2976 2977 enum { 2978 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2979 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2980 }; 2981 2982 enum { 2983 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0, 2984 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1, 2985 }; 2986 2987 struct mlx5_ifc_tirc_bits { 2988 u8 reserved_at_0[0x20]; 2989 u8 disp_type[0x4]; 2990 u8 reserved_at_24[0x1c]; 2991 u8 reserved_at_40[0x40]; 2992 u8 reserved_at_80[0x4]; 2993 u8 lro_timeout_period_usecs[0x10]; 2994 u8 lro_enable_mask[0x4]; 2995 u8 lro_max_msg_sz[0x8]; 2996 u8 reserved_at_a0[0x40]; 2997 u8 reserved_at_e0[0x8]; 2998 u8 inline_rqn[0x18]; 2999 u8 rx_hash_symmetric[0x1]; 3000 u8 reserved_at_101[0x1]; 3001 u8 tunneled_offload_en[0x1]; 3002 u8 reserved_at_103[0x5]; 3003 u8 indirect_table[0x18]; 3004 u8 rx_hash_fn[0x4]; 3005 u8 reserved_at_124[0x2]; 3006 u8 self_lb_block[0x2]; 3007 u8 transport_domain[0x18]; 3008 u8 rx_hash_toeplitz_key[10][0x20]; 3009 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3010 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3011 u8 reserved_at_2c0[0x4c0]; 3012 }; 3013 3014 struct mlx5_ifc_create_tir_out_bits { 3015 u8 status[0x8]; 3016 u8 reserved_at_8[0x18]; 3017 u8 syndrome[0x20]; 3018 u8 reserved_at_40[0x8]; 3019 u8 tirn[0x18]; 3020 u8 reserved_at_60[0x20]; 3021 }; 3022 3023 struct mlx5_ifc_create_tir_in_bits { 3024 u8 opcode[0x10]; 3025 u8 uid[0x10]; 3026 u8 reserved_at_20[0x10]; 3027 u8 op_mod[0x10]; 3028 u8 reserved_at_40[0xc0]; 3029 struct mlx5_ifc_tirc_bits ctx; 3030 }; 3031 3032 enum { 3033 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0, 3034 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1, 3035 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2, 3036 /* bit 3 - tunneled_offload_en modify not supported. */ 3037 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4, 3038 }; 3039 3040 struct mlx5_ifc_modify_tir_out_bits { 3041 u8 status[0x8]; 3042 u8 reserved_at_8[0x18]; 3043 u8 syndrome[0x20]; 3044 u8 reserved_at_40[0x40]; 3045 }; 3046 3047 struct mlx5_ifc_modify_tir_in_bits { 3048 u8 opcode[0x10]; 3049 u8 uid[0x10]; 3050 u8 reserved_at_20[0x10]; 3051 u8 op_mod[0x10]; 3052 u8 reserved_at_40[0x8]; 3053 u8 tirn[0x18]; 3054 u8 reserved_at_60[0x20]; 3055 u8 modify_bitmask[0x40]; 3056 u8 reserved_at_c0[0x40]; 3057 struct mlx5_ifc_tirc_bits ctx; 3058 }; 3059 3060 enum { 3061 MLX5_INLINE_Q_TYPE_RQ = 0x0, 3062 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1, 3063 }; 3064 3065 struct mlx5_ifc_rq_num_bits { 3066 u8 reserved_at_0[0x8]; 3067 u8 rq_num[0x18]; 3068 }; 3069 3070 struct mlx5_ifc_rqtc_bits { 3071 u8 reserved_at_0[0xa5]; 3072 u8 list_q_type[0x3]; 3073 u8 reserved_at_a8[0x8]; 3074 u8 rqt_max_size[0x10]; 3075 u8 reserved_at_c0[0x10]; 3076 u8 rqt_actual_size[0x10]; 3077 u8 reserved_at_e0[0x6a0]; 3078 struct mlx5_ifc_rq_num_bits rq_num[]; 3079 }; 3080 3081 struct mlx5_ifc_create_rqt_out_bits { 3082 u8 status[0x8]; 3083 u8 reserved_at_8[0x18]; 3084 u8 syndrome[0x20]; 3085 u8 reserved_at_40[0x8]; 3086 u8 rqtn[0x18]; 3087 u8 reserved_at_60[0x20]; 3088 }; 3089 3090 #ifdef PEDANTIC 3091 #pragma GCC diagnostic ignored "-Wpedantic" 3092 #endif 3093 struct mlx5_ifc_create_rqt_in_bits { 3094 u8 opcode[0x10]; 3095 u8 uid[0x10]; 3096 u8 reserved_at_20[0x10]; 3097 u8 op_mod[0x10]; 3098 u8 reserved_at_40[0xc0]; 3099 struct mlx5_ifc_rqtc_bits rqt_context; 3100 }; 3101 3102 struct mlx5_ifc_modify_rqt_in_bits { 3103 u8 opcode[0x10]; 3104 u8 uid[0x10]; 3105 u8 reserved_at_20[0x10]; 3106 u8 op_mod[0x10]; 3107 u8 reserved_at_40[0x8]; 3108 u8 rqtn[0x18]; 3109 u8 reserved_at_60[0x20]; 3110 u8 modify_bitmask[0x40]; 3111 u8 reserved_at_c0[0x40]; 3112 struct mlx5_ifc_rqtc_bits rqt_context; 3113 }; 3114 #ifdef PEDANTIC 3115 #pragma GCC diagnostic error "-Wpedantic" 3116 #endif 3117 3118 struct mlx5_ifc_modify_rqt_out_bits { 3119 u8 status[0x8]; 3120 u8 reserved_at_8[0x18]; 3121 u8 syndrome[0x20]; 3122 u8 reserved_at_40[0x40]; 3123 }; 3124 3125 enum { 3126 MLX5_SQC_STATE_RST = 0x0, 3127 MLX5_SQC_STATE_RDY = 0x1, 3128 MLX5_SQC_STATE_ERR = 0x3, 3129 }; 3130 3131 enum { 3132 MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER = 0x0, 3133 MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY = 0x1, 3134 }; 3135 3136 struct mlx5_ifc_sqc_bits { 3137 u8 rlky[0x1]; 3138 u8 cd_master[0x1]; 3139 u8 fre[0x1]; 3140 u8 flush_in_error_en[0x1]; 3141 u8 allow_multi_pkt_send_wqe[0x1]; 3142 u8 min_wqe_inline_mode[0x3]; 3143 u8 state[0x4]; 3144 u8 reg_umr[0x1]; 3145 u8 allow_swp[0x1]; 3146 u8 hairpin[0x1]; 3147 u8 non_wire[0x1]; 3148 u8 static_sq_wq[0x1]; 3149 u8 reserved_at_11[0x4]; 3150 u8 hairpin_wq_buffer_type[0x3]; 3151 u8 reserved_at_18[0x2]; 3152 u8 ts_format[0x02]; 3153 u8 reserved_at_1c[0x4]; 3154 u8 reserved_at_20[0x8]; 3155 u8 user_index[0x18]; 3156 u8 reserved_at_40[0x8]; 3157 u8 cqn[0x18]; 3158 u8 reserved_at_60[0x8]; 3159 u8 hairpin_peer_rq[0x18]; 3160 u8 reserved_at_80[0x10]; 3161 u8 hairpin_peer_vhca[0x10]; 3162 u8 reserved_at_a0[0x50]; 3163 u8 packet_pacing_rate_limit_index[0x10]; 3164 u8 tis_lst_sz[0x10]; 3165 u8 reserved_at_110[0x10]; 3166 u8 reserved_at_120[0x40]; 3167 u8 reserved_at_160[0x8]; 3168 u8 tis_num_0[0x18]; 3169 struct mlx5_ifc_wq_bits wq; 3170 }; 3171 3172 struct mlx5_ifc_query_sq_out_bits { 3173 u8 status[0x8]; 3174 u8 reserved_at_8[0x18]; 3175 u8 syndrome[0x20]; 3176 u8 reserved_at_40[0xc0]; 3177 struct mlx5_ifc_sqc_bits sq_context; 3178 }; 3179 3180 struct mlx5_ifc_query_sq_in_bits { 3181 u8 opcode[0x10]; 3182 u8 reserved_at_10[0x10]; 3183 u8 reserved_at_20[0x10]; 3184 u8 op_mod[0x10]; 3185 u8 reserved_at_40[0x8]; 3186 u8 sqn[0x18]; 3187 u8 reserved_at_60[0x20]; 3188 }; 3189 3190 struct mlx5_ifc_modify_sq_out_bits { 3191 u8 status[0x8]; 3192 u8 reserved_at_8[0x18]; 3193 u8 syndrome[0x20]; 3194 u8 reserved_at_40[0x40]; 3195 }; 3196 3197 struct mlx5_ifc_modify_sq_in_bits { 3198 u8 opcode[0x10]; 3199 u8 uid[0x10]; 3200 u8 reserved_at_20[0x10]; 3201 u8 op_mod[0x10]; 3202 u8 sq_state[0x4]; 3203 u8 reserved_at_44[0x4]; 3204 u8 sqn[0x18]; 3205 u8 reserved_at_60[0x20]; 3206 u8 modify_bitmask[0x40]; 3207 u8 reserved_at_c0[0x40]; 3208 struct mlx5_ifc_sqc_bits ctx; 3209 }; 3210 3211 struct mlx5_ifc_create_sq_out_bits { 3212 u8 status[0x8]; 3213 u8 reserved_at_8[0x18]; 3214 u8 syndrome[0x20]; 3215 u8 reserved_at_40[0x8]; 3216 u8 sqn[0x18]; 3217 u8 reserved_at_60[0x20]; 3218 }; 3219 3220 struct mlx5_ifc_create_sq_in_bits { 3221 u8 opcode[0x10]; 3222 u8 uid[0x10]; 3223 u8 reserved_at_20[0x10]; 3224 u8 op_mod[0x10]; 3225 u8 reserved_at_40[0xc0]; 3226 struct mlx5_ifc_sqc_bits ctx; 3227 }; 3228 3229 enum { 3230 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0), 3231 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1), 3232 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2), 3233 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3), 3234 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4), 3235 }; 3236 3237 struct mlx5_ifc_flow_meter_parameters_bits { 3238 u8 valid[0x1]; 3239 u8 bucket_overflow[0x1]; 3240 u8 start_color[0x2]; 3241 u8 both_buckets_on_green[0x1]; 3242 u8 meter_mode[0x2]; 3243 u8 reserved_at_1[0x19]; 3244 u8 reserved_at_2[0x20]; 3245 u8 reserved_at_3[0x3]; 3246 u8 cbs_exponent[0x5]; 3247 u8 cbs_mantissa[0x8]; 3248 u8 reserved_at_4[0x3]; 3249 u8 cir_exponent[0x5]; 3250 u8 cir_mantissa[0x8]; 3251 u8 reserved_at_5[0x20]; 3252 u8 reserved_at_6[0x3]; 3253 u8 ebs_exponent[0x5]; 3254 u8 ebs_mantissa[0x8]; 3255 u8 reserved_at_7[0x3]; 3256 u8 eir_exponent[0x5]; 3257 u8 eir_mantissa[0x8]; 3258 u8 reserved_at_8[0x60]; 3259 }; 3260 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF) 3261 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8 3262 3263 enum { 3264 MLX5_METER_MODE_IP_LEN = 0x0, 3265 MLX5_METER_MODE_L2_LEN = 0x1, 3266 MLX5_METER_MODE_L2_IPG_LEN = 0x2, 3267 MLX5_METER_MODE_PKT = 0x3, 3268 }; 3269 3270 enum { 3271 MLX5_CQE_SIZE_64B = 0x0, 3272 MLX5_CQE_SIZE_128B = 0x1, 3273 }; 3274 3275 enum { 3276 MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER = 0x0, 3277 MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER = 0x1, 3278 }; 3279 3280 struct mlx5_ifc_cqc_bits { 3281 u8 status[0x4]; 3282 u8 as_notify[0x1]; 3283 u8 initiator_src_dct[0x1]; 3284 u8 dbr_umem_valid[0x1]; 3285 u8 ext_element[0x1]; 3286 u8 cqe_sz[0x3]; 3287 u8 cc[0x1]; 3288 u8 reserved_at_c[0x1]; 3289 u8 scqe_break_moderation_en[0x1]; 3290 u8 oi[0x1]; 3291 u8 cq_period_mode[0x2]; 3292 u8 cqe_comp_en[0x1]; 3293 u8 mini_cqe_res_format[0x2]; 3294 u8 st[0x4]; 3295 u8 always_armed_cq[0x1]; 3296 u8 ext_element_type[0x3]; 3297 u8 reserved_at_1c[0x2]; 3298 u8 cqe_comp_layout[0x2]; 3299 u8 dbr_umem_id[0x20]; 3300 u8 reserved_at_40[0x14]; 3301 u8 page_offset[0x6]; 3302 u8 reserved_at_5a[0x2]; 3303 u8 mini_cqe_res_format_ext[0x2]; 3304 u8 cq_timestamp_format[0x2]; 3305 u8 reserved_at_60[0x3]; 3306 u8 log_cq_size[0x5]; 3307 u8 uar_page[0x18]; 3308 u8 reserved_at_80[0x4]; 3309 u8 cq_period[0xc]; 3310 u8 cq_max_count[0x10]; 3311 u8 reserved_at_a0[0x18]; 3312 u8 c_eqn[0x8]; 3313 u8 reserved_at_c0[0x3]; 3314 u8 log_page_size[0x5]; 3315 u8 reserved_at_c8[0x18]; 3316 u8 reserved_at_e0[0x20]; 3317 u8 reserved_at_100[0x8]; 3318 u8 last_notified_index[0x18]; 3319 u8 reserved_at_120[0x8]; 3320 u8 last_solicit_index[0x18]; 3321 u8 reserved_at_140[0x8]; 3322 u8 consumer_counter[0x18]; 3323 u8 reserved_at_160[0x8]; 3324 u8 producer_counter[0x18]; 3325 u8 local_partition_id[0xc]; 3326 u8 process_id[0x14]; 3327 u8 reserved_at_1A0[0x20]; 3328 u8 dbr_addr[0x40]; 3329 }; 3330 3331 struct mlx5_ifc_health_buffer_bits { 3332 u8 reserved_0[0x100]; 3333 u8 assert_existptr[0x20]; 3334 u8 assert_callra[0x20]; 3335 u8 reserved_1[0x40]; 3336 u8 fw_version[0x20]; 3337 u8 hw_id[0x20]; 3338 u8 reserved_2[0x20]; 3339 u8 irisc_index[0x8]; 3340 u8 synd[0x8]; 3341 u8 ext_synd[0x10]; 3342 }; 3343 3344 /* HCA PCI BAR resource structure. */ 3345 struct mlx5_ifc_initial_seg_bits { 3346 u8 fw_rev_minor[0x10]; 3347 u8 fw_rev_major[0x10]; 3348 u8 cmd_interface_rev[0x10]; 3349 u8 fw_rev_subminor[0x10]; 3350 u8 reserved_0[0x40]; 3351 u8 cmdq_phy_addr_63_32[0x20]; 3352 u8 cmdq_phy_addr_31_12[0x14]; 3353 u8 reserved_1[0x2]; 3354 u8 nic_interface[0x2]; 3355 u8 log_cmdq_size[0x4]; 3356 u8 log_cmdq_stride[0x4]; 3357 u8 command_doorbell_vector[0x20]; 3358 u8 reserved_2[0xf00]; 3359 u8 initializing[0x1]; 3360 u8 nic_interface_supported[0x7]; 3361 u8 reserved_4[0x18]; 3362 struct mlx5_ifc_health_buffer_bits health_buffer; 3363 u8 no_dram_nic_offset[0x20]; 3364 u8 reserved_5[0x6de0]; 3365 u8 internal_timer_h[0x20]; 3366 u8 internal_timer_l[0x20]; 3367 u8 reserved_6[0x20]; 3368 u8 reserved_7[0x1f]; 3369 u8 clear_int[0x1]; 3370 u8 health_syndrome[0x8]; 3371 u8 health_counter[0x18]; 3372 u8 reserved_8[0x160]; 3373 u8 real_time[0x40]; 3374 u8 reserved_9[0x17e20]; 3375 }; 3376 3377 struct mlx5_ifc_create_cq_out_bits { 3378 u8 status[0x8]; 3379 u8 reserved_at_8[0x18]; 3380 u8 syndrome[0x20]; 3381 u8 reserved_at_40[0x8]; 3382 u8 cqn[0x18]; 3383 u8 reserved_at_60[0x20]; 3384 }; 3385 3386 struct mlx5_ifc_create_cq_in_bits { 3387 u8 opcode[0x10]; 3388 u8 uid[0x10]; 3389 u8 reserved_at_20[0x10]; 3390 u8 op_mod[0x10]; 3391 u8 reserved_at_40[0x40]; 3392 struct mlx5_ifc_cqc_bits cq_context; 3393 u8 cq_umem_offset[0x40]; 3394 u8 cq_umem_id[0x20]; 3395 u8 cq_umem_valid[0x1]; 3396 u8 reserved_at_2e1[0x1f]; 3397 u8 reserved_at_300[0x580]; 3398 u8 pas[]; 3399 }; 3400 3401 struct mlx5_ifc_query_cq_out_bits { 3402 u8 status[0x8]; 3403 u8 reserved_at_8[0x18]; 3404 u8 syndrome[0x20]; 3405 u8 reserved_at_40[0x40]; 3406 struct mlx5_ifc_cqc_bits cq_context; 3407 u8 reserved_at_280[0x600]; 3408 u8 pas[][0x40]; 3409 }; 3410 3411 struct mlx5_ifc_query_cq_in_bits { 3412 u8 opcode[0x10]; 3413 u8 reserved_at_10[0x10]; 3414 u8 reserved_at_20[0x10]; 3415 u8 op_mod[0x10]; 3416 u8 reserved_at_40[0x8]; 3417 u8 cqn[0x18]; 3418 u8 reserved_at_60[0x20]; 3419 }; 3420 3421 enum { 3422 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 3423 MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c, 3424 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, 3425 MLX5_GENERAL_OBJ_TYPE_DEFINER = 0x0018, 3426 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 3427 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d, 3428 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e, 3429 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f, 3430 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, 3431 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, 3432 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, 3433 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031, 3434 MLX5_GENERAL_OBJ_TYPE_ARG = 0x0023, 3435 MLX5_GENERAL_OBJ_TYPE_STC = 0x0040, 3436 MLX5_GENERAL_OBJ_TYPE_RTC = 0x0041, 3437 MLX5_GENERAL_OBJ_TYPE_STE = 0x0042, 3438 MLX5_GENERAL_OBJ_TYPE_MODIFY_HEADER_PATTERN = 0x0043, 3439 MLX5_GENERAL_OBJ_TYPE_FT_ALIAS = 0xff15, 3440 MLX5_GENERAL_OBJ_TYPE_TIR_ALIAS = 0xff16, 3441 }; 3442 3443 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 3444 u8 opcode[0x10]; 3445 u8 reserved_at_10[0x20]; 3446 u8 obj_type[0x10]; 3447 u8 obj_id[0x20]; 3448 union { 3449 struct { 3450 u8 alias_object[0x1]; 3451 u8 reserved_at_61[0x2]; 3452 u8 log_obj_range[0x5]; 3453 u8 reserved_at_68[0x18]; 3454 }; 3455 u8 obj_offset[0x20]; 3456 }; 3457 }; 3458 3459 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 3460 u8 status[0x8]; 3461 u8 reserved_at_8[0x18]; 3462 u8 syndrome[0x20]; 3463 u8 obj_id[0x20]; 3464 u8 reserved_at_60[0x20]; 3465 }; 3466 3467 struct mlx5_ifc_allow_other_vhca_access_in_bits { 3468 u8 opcode[0x10]; 3469 u8 uid[0x10]; 3470 u8 reserved_at_20[0x10]; 3471 u8 op_mod[0x10]; 3472 u8 reserved_at_40[0x50]; 3473 u8 object_type_to_be_accessed[0x10]; 3474 u8 object_id_to_be_accessed[0x20]; 3475 u8 reserved_at_c0[0x40]; 3476 union { 3477 u8 access_key_raw[0x100]; 3478 u8 access_key[8][0x20]; 3479 }; 3480 }; 3481 3482 struct mlx5_ifc_allow_other_vhca_access_out_bits { 3483 u8 status[0x8]; 3484 u8 reserved_at_8[0x18]; 3485 u8 syndrome[0x20]; 3486 u8 reserved_at_40[0x40]; 3487 }; 3488 3489 struct mlx5_ifc_virtio_q_counters_bits { 3490 u8 modify_field_select[0x40]; 3491 u8 reserved_at_40[0x40]; 3492 u8 received_desc[0x40]; 3493 u8 completed_desc[0x40]; 3494 u8 error_cqes[0x20]; 3495 u8 bad_desc_errors[0x20]; 3496 u8 exceed_max_chain[0x20]; 3497 u8 invalid_buffer[0x20]; 3498 u8 reserved_at_180[0x50]; 3499 }; 3500 3501 struct mlx5_ifc_geneve_tlv_option_bits { 3502 u8 modify_field_select[0x40]; 3503 u8 reserved_at_40[0x8]; 3504 u8 sample_offset[0x8]; 3505 u8 sample_id_valid[0x1]; 3506 u8 sample_offset_valid[0x1]; 3507 u8 option_class_ignore[0x1]; 3508 u8 reserved_at_53[0x5]; 3509 u8 geneve_option_fte_index[0x8]; 3510 u8 option_class[0x10]; 3511 u8 option_type[0x8]; 3512 u8 reserved_at_78[0x3]; 3513 u8 option_data_length[0x5]; 3514 u8 geneve_sample_field_id[0x20]; 3515 u8 reserved_at_a0[0x160]; 3516 }; 3517 3518 enum mlx5_ifc_rtc_update_mode { 3519 MLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH = 0x0, 3520 MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET = 0x1, 3521 }; 3522 3523 enum mlx5_ifc_rtc_access_mode { 3524 MLX5_IFC_RTC_STE_ACCESS_MODE_BY_HASH = 0x0, 3525 MLX5_IFC_RTC_STE_ACCESS_MODE_LINEAR = 0x1, 3526 }; 3527 3528 enum mlx5_ifc_rtc_ste_format { 3529 MLX5_IFC_RTC_STE_FORMAT_8DW = 0x4, 3530 MLX5_IFC_RTC_STE_FORMAT_11DW = 0x5, 3531 MLX5_IFC_RTC_STE_FORMAT_RANGE = 0x7, 3532 MLX5_IFC_RTC_STE_FORMAT_4DW_RANGE = 0x8, 3533 }; 3534 3535 enum mlx5_ifc_rtc_reparse_mode { 3536 MLX5_IFC_RTC_REPARSE_NEVER = 0x0, 3537 MLX5_IFC_RTC_REPARSE_ALWAYS = 0x1, 3538 MLX5_IFC_RTC_REPARSE_BY_STC = 0x2, 3539 }; 3540 3541 #define MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX 16 3542 3543 struct mlx5_ifc_rtc_bits { 3544 u8 modify_field_select[0x40]; 3545 u8 reserved_at_40[0x40]; 3546 u8 update_index_mode[0x2]; 3547 u8 reparse_mode[0x2]; 3548 u8 num_match_ste[0x4]; 3549 u8 pd[0x18]; 3550 u8 reserved_at_a0[0x9]; 3551 u8 access_index_mode[0x3]; 3552 u8 num_hash_definer[0x4]; 3553 u8 update_method[0x1]; 3554 u8 reserved_at_b1[0x2]; 3555 u8 log_depth[0x5]; 3556 u8 log_hash_size[0x8]; 3557 u8 ste_format_0[0x8]; 3558 u8 table_type[0x8]; 3559 u8 ste_format_1[0x8]; 3560 u8 reserved_at_d8[0x8]; 3561 u8 match_definer_0[0x20]; 3562 u8 stc_id[0x20]; 3563 u8 ste_table_base_id[0x20]; 3564 u8 ste_table_offset[0x20]; 3565 u8 reserved_at_160[0x8]; 3566 u8 miss_flow_table_id[0x18]; 3567 u8 match_definer_1[0x20]; 3568 u8 reserved_at_1a0[0x260]; 3569 }; 3570 3571 struct mlx5_ifc_ste_match_4dw_range_ctrl_dw_bits { 3572 u8 match[0x1]; 3573 u8 reserved_at_1[0x2]; 3574 u8 base1[0x1]; 3575 u8 inverse1[0x1]; 3576 u8 reserved_at_5[0x1]; 3577 u8 operator1[0x2]; 3578 u8 reserved_at_8[0x3]; 3579 u8 base0[0x1]; 3580 u8 inverse0[0x1]; 3581 u8 reserved_at_a[0x1]; 3582 u8 operator0[0x2]; 3583 u8 compare_delta[0x10]; 3584 }; 3585 3586 struct mlx5_ifc_alias_context_bits { 3587 u8 vhca_id_to_be_accessed[0x10]; 3588 u8 reserved_at_10[0xd]; 3589 u8 status[0x3]; 3590 u8 object_id_to_be_accessed[0x20]; 3591 u8 reserved_at_40[0x40]; 3592 union { 3593 u8 access_key_raw[0x100]; 3594 u8 access_key[8][0x20]; 3595 }; 3596 u8 metadata[0x80]; 3597 }; 3598 3599 enum mlx5_ifc_stc_action_type { 3600 MLX5_IFC_STC_ACTION_TYPE_NOP = 0x00, 3601 MLX5_IFC_STC_ACTION_TYPE_COPY = 0x05, 3602 MLX5_IFC_STC_ACTION_TYPE_SET = 0x06, 3603 MLX5_IFC_STC_ACTION_TYPE_ADD = 0x07, 3604 MLX5_IFC_STC_ACTION_TYPE_REMOVE_WORDS = 0x08, 3605 MLX5_IFC_STC_ACTION_TYPE_HEADER_REMOVE = 0x09, 3606 MLX5_IFC_STC_ACTION_TYPE_HEADER_INSERT = 0x0b, 3607 MLX5_IFC_STC_ACTION_TYPE_TAG = 0x0c, 3608 MLX5_IFC_STC_ACTION_TYPE_ACC_MODIFY_LIST = 0x0e, 3609 MLX5_IFC_STC_ACTION_TYPE_ASO = 0x12, 3610 MLX5_IFC_STC_ACTION_TYPE_COUNTER = 0x14, 3611 MLX5_IFC_STC_ACTION_TYPE_ADD_FIELD = 0x1b, 3612 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_STE_TABLE = 0x80, 3613 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_TIR = 0x81, 3614 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_FT = 0x82, 3615 MLX5_IFC_STC_ACTION_TYPE_DROP = 0x83, 3616 MLX5_IFC_STC_ACTION_TYPE_ALLOW = 0x84, 3617 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT = 0x85, 3618 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_UPLINK = 0x86, 3619 }; 3620 3621 enum mlx5_ifc_stc_reparse_mode { 3622 MLX5_IFC_STC_REPARSE_IGNORE = 0x0, 3623 MLX5_IFC_STC_REPARSE_NEVER = 0x1, 3624 MLX5_IFC_STC_REPARSE_ALWAYS = 0x2, 3625 }; 3626 3627 struct mlx5_ifc_stc_ste_param_ste_table_bits { 3628 u8 ste_obj_id[0x20]; 3629 u8 match_definer_id[0x20]; 3630 u8 reserved_at_40[0x3]; 3631 u8 log_hash_size[0x5]; 3632 u8 reserved_at_48[0x38]; 3633 }; 3634 3635 struct mlx5_ifc_stc_ste_param_tir_bits { 3636 u8 reserved_at_0[0x8]; 3637 u8 tirn[0x18]; 3638 u8 reserved_at_20[0x60]; 3639 }; 3640 3641 struct mlx5_ifc_stc_ste_param_table_bits { 3642 u8 reserved_at_0[0x8]; 3643 u8 table_id[0x18]; 3644 u8 reserved_at_20[0x60]; 3645 }; 3646 3647 struct mlx5_ifc_stc_ste_param_flow_counter_bits { 3648 u8 flow_counter_id[0x20]; 3649 }; 3650 3651 enum { 3652 MLX5_ASO_CT_NUM_PER_OBJ = 1, 3653 MLX5_ASO_METER_NUM_PER_OBJ = 2, 3654 }; 3655 3656 struct mlx5_ifc_stc_ste_param_execute_aso_bits { 3657 u8 aso_object_id[0x20]; 3658 u8 return_reg_id[0x4]; 3659 u8 aso_type[0x4]; 3660 u8 reserved_at_28[0x18]; 3661 }; 3662 3663 struct mlx5_ifc_stc_ste_param_header_modify_list_bits { 3664 u8 header_modify_pattern_id[0x20]; 3665 u8 header_modify_argument_id[0x20]; 3666 }; 3667 3668 enum mlx5_ifc_header_anchors { 3669 MLX5_HEADER_ANCHOR_PACKET_START = 0x0, 3670 MLX5_HEADER_ANCHOR_FIRST_VLAN_START = 0x2, 3671 MLX5_HEADER_ANCHOR_IPV6_IPV4 = 0x07, 3672 MLX5_HEADER_ANCHOR_TCP_UDP = 0x09, 3673 MLX5_HEADER_ANCHOR_INNER_MAC = 0x13, 3674 MLX5_HEADER_ANCHOR_INNER_IPV6_IPV4 = 0x19, 3675 }; 3676 3677 struct mlx5_ifc_stc_ste_param_remove_bits { 3678 u8 action_type[0x4]; 3679 u8 decap[0x1]; 3680 u8 reserved_at_5[0x5]; 3681 u8 remove_start_anchor[0x6]; 3682 u8 reserved_at_10[0x2]; 3683 u8 remove_end_anchor[0x6]; 3684 u8 reserved_at_18[0x8]; 3685 }; 3686 3687 struct mlx5_ifc_stc_ste_param_remove_words_bits { 3688 u8 action_type[0x4]; 3689 u8 reserved_at_4[0x6]; 3690 u8 remove_start_anchor[0x6]; 3691 u8 reserved_at_10[0x1]; 3692 u8 remove_offset[0x7]; 3693 u8 reserved_at_18[0x2]; 3694 u8 remove_size[0x6]; 3695 }; 3696 3697 struct mlx5_ifc_stc_ste_param_insert_bits { 3698 u8 action_type[0x4]; 3699 u8 encap[0x1]; 3700 u8 inline_data[0x1]; 3701 u8 push_esp[0x1]; 3702 u8 reserved_at_7[0x3]; 3703 u8 insert_anchor[0x6]; 3704 u8 reserved_at_10[0x1]; 3705 u8 insert_offset[0x7]; 3706 u8 reserved_at_18[0x1]; 3707 u8 insert_size[0x7]; 3708 u8 insert_argument[0x20]; 3709 }; 3710 3711 struct mlx5_ifc_stc_ste_param_vport_bits { 3712 u8 eswitch_owner_vhca_id[0x10]; 3713 u8 vport_number[0x10]; 3714 u8 eswitch_owner_vhca_id_valid[0x1]; 3715 u8 reserved_at_21[0x5f]; 3716 }; 3717 3718 union mlx5_ifc_stc_param_bits { 3719 struct mlx5_ifc_stc_ste_param_ste_table_bits ste_table; 3720 struct mlx5_ifc_stc_ste_param_tir_bits tir; 3721 struct mlx5_ifc_stc_ste_param_table_bits table; 3722 struct mlx5_ifc_stc_ste_param_flow_counter_bits counter; 3723 struct mlx5_ifc_stc_ste_param_header_modify_list_bits modify_header; 3724 struct mlx5_ifc_stc_ste_param_execute_aso_bits aso; 3725 struct mlx5_ifc_stc_ste_param_remove_bits remove_header; 3726 struct mlx5_ifc_stc_ste_param_insert_bits insert_header; 3727 struct mlx5_ifc_set_action_in_bits add; 3728 struct mlx5_ifc_set_action_in_bits set; 3729 struct mlx5_ifc_copy_action_in_bits copy; 3730 struct mlx5_ifc_stc_ste_param_vport_bits vport; 3731 u8 reserved_at_0[0x80]; 3732 }; 3733 3734 enum { 3735 MLX5_IFC_MODIFY_STC_FIELD_SELECT_NEW_STC = 1 << 0, 3736 }; 3737 3738 struct mlx5_ifc_stc_bits { 3739 u8 modify_field_select[0x40]; 3740 u8 reserved_at_40[0x46]; 3741 u8 reparse_mode[0x2]; 3742 u8 table_type[0x8]; 3743 u8 ste_action_offset[0x8]; 3744 u8 action_type[0x8]; 3745 u8 reserved_at_a0[0x60]; 3746 union mlx5_ifc_stc_param_bits stc_param; 3747 u8 reserved_at_180[0x280]; 3748 }; 3749 3750 struct mlx5_ifc_ste_bits { 3751 u8 modify_field_select[0x40]; 3752 u8 reserved_at_40[0x48]; 3753 u8 table_type[0x8]; 3754 u8 reserved_at_90[0x370]; 3755 }; 3756 3757 enum { 3758 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 3759 }; 3760 3761 struct mlx5_ifc_definer_bits { 3762 u8 modify_field_select[0x40]; 3763 u8 reserved_at_40[0x50]; 3764 u8 format_id[0x10]; 3765 u8 reserved_at_60[0x60]; 3766 u8 format_select_dw3[0x8]; 3767 u8 format_select_dw2[0x8]; 3768 u8 format_select_dw1[0x8]; 3769 u8 format_select_dw0[0x8]; 3770 u8 format_select_dw7[0x8]; 3771 u8 format_select_dw6[0x8]; 3772 u8 format_select_dw5[0x8]; 3773 u8 format_select_dw4[0x8]; 3774 u8 reserved_at_100[0x18]; 3775 u8 format_select_dw8[0x8]; 3776 u8 reserved_at_120[0x20]; 3777 u8 format_select_byte3[0x8]; 3778 u8 format_select_byte2[0x8]; 3779 u8 format_select_byte1[0x8]; 3780 u8 format_select_byte0[0x8]; 3781 u8 format_select_byte7[0x8]; 3782 u8 format_select_byte6[0x8]; 3783 u8 format_select_byte5[0x8]; 3784 u8 format_select_byte4[0x8]; 3785 u8 reserved_at_180[0x40]; 3786 u8 ctrl[0xa0]; 3787 u8 match_mask[0x160]; 3788 }; 3789 3790 struct mlx5_ifc_arg_bits { 3791 u8 rsvd0[0x88]; 3792 u8 access_pd[0x18]; 3793 }; 3794 3795 struct mlx5_ifc_header_modify_pattern_in_bits { 3796 u8 modify_field_select[0x40]; 3797 3798 u8 reserved_at_40[0x40]; 3799 3800 u8 pattern_length[0x8]; 3801 u8 reserved_at_88[0x18]; 3802 3803 u8 reserved_at_a0[0x60]; 3804 3805 u8 pattern_data[MAX_ACTIONS_DATA_IN_HEADER_MODIFY * 8]; 3806 }; 3807 3808 struct mlx5_ifc_create_virtio_q_counters_in_bits { 3809 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3810 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 3811 }; 3812 3813 struct mlx5_ifc_query_virtio_q_counters_out_bits { 3814 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3815 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 3816 }; 3817 3818 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 3819 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3820 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 3821 }; 3822 3823 struct mlx5_ifc_query_geneve_tlv_option_out_bits { 3824 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3825 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 3826 }; 3827 3828 struct mlx5_ifc_create_rtc_in_bits { 3829 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3830 struct mlx5_ifc_rtc_bits rtc; 3831 }; 3832 3833 struct mlx5_ifc_create_stc_in_bits { 3834 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3835 struct mlx5_ifc_stc_bits stc; 3836 }; 3837 3838 struct mlx5_ifc_create_ste_in_bits { 3839 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3840 struct mlx5_ifc_ste_bits ste; 3841 }; 3842 3843 struct mlx5_ifc_create_definer_in_bits { 3844 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3845 struct mlx5_ifc_definer_bits definer; 3846 }; 3847 3848 struct mlx5_ifc_create_arg_in_bits { 3849 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3850 struct mlx5_ifc_arg_bits arg; 3851 }; 3852 3853 struct mlx5_ifc_create_header_modify_pattern_in_bits { 3854 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3855 struct mlx5_ifc_header_modify_pattern_in_bits pattern; 3856 }; 3857 3858 struct mlx5_ifc_create_alias_obj_in_bits { 3859 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3860 struct mlx5_ifc_alias_context_bits alias_ctx; 3861 }; 3862 3863 struct mlx5_ifc_generate_wqe_in_bits { 3864 u8 opcode[0x10]; 3865 u8 uid[0x10]; 3866 u8 reserved_at_20[0x10]; 3867 u8 op_mode[0x10]; 3868 u8 reserved_at_40[0x40]; 3869 u8 reserved_at_80[0x8]; 3870 u8 pdn[0x18]; 3871 u8 reserved_at_a0[0x160]; 3872 u8 wqe_ctrl[0x80]; 3873 u8 wqe_gta_ctrl[0x180]; 3874 u8 wqe_gta_data_0[0x200]; 3875 u8 wqe_gta_data_1[0x200]; 3876 }; 3877 3878 struct mlx5_ifc_generate_wqe_out_bits { 3879 u8 status[0x8]; 3880 u8 reserved_at_8[0x18]; 3881 u8 syndrome[0x20]; 3882 u8 reserved_at_40[0x1c0]; 3883 u8 cqe_data[0x200]; 3884 }; 3885 3886 enum { 3887 MLX5_CRYPTO_KEY_SIZE_128b = 0x0, 3888 MLX5_CRYPTO_KEY_SIZE_256b = 0x1, 3889 }; 3890 3891 enum { 3892 MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1, 3893 MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2, 3894 MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3, 3895 MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4, 3896 MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5, 3897 MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6, 3898 }; 3899 3900 struct mlx5_ifc_dek_bits { 3901 u8 modify_field_select[0x40]; 3902 u8 state[0x8]; 3903 u8 reserved_at_48[0xc]; 3904 u8 key_size[0x4]; 3905 u8 has_keytag[0x1]; 3906 u8 reserved_at_59[0x3]; 3907 u8 key_purpose[0x4]; 3908 u8 reserved_at_60[0x8]; 3909 u8 pd[0x18]; 3910 u8 reserved_at_80[0x100]; 3911 u8 opaque[0x40]; 3912 u8 reserved_at_1c0[0x40]; 3913 u8 key[0x400]; 3914 u8 reserved_at_600[0x200]; 3915 }; 3916 3917 struct mlx5_ifc_create_dek_in_bits { 3918 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3919 struct mlx5_ifc_dek_bits dek; 3920 }; 3921 3922 struct mlx5_ifc_import_kek_bits { 3923 u8 modify_field_select[0x40]; 3924 u8 state[0x8]; 3925 u8 reserved_at_48[0xc]; 3926 u8 key_size[0x4]; 3927 u8 reserved_at_58[0x1a8]; 3928 u8 key[0x400]; 3929 u8 reserved_at_600[0x200]; 3930 }; 3931 3932 struct mlx5_ifc_create_import_kek_in_bits { 3933 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3934 struct mlx5_ifc_import_kek_bits import_kek; 3935 }; 3936 3937 enum { 3938 MLX5_CREDENTIAL_ROLE_OFFICER = 0x0, 3939 MLX5_CREDENTIAL_ROLE_USER = 0x1, 3940 }; 3941 3942 struct mlx5_ifc_credential_bits { 3943 u8 modify_field_select[0x40]; 3944 u8 state[0x8]; 3945 u8 reserved_at_48[0x10]; 3946 u8 credential_role[0x8]; 3947 u8 reserved_at_60[0x1a0]; 3948 u8 credential[0x180]; 3949 u8 reserved_at_380[0x480]; 3950 }; 3951 3952 struct mlx5_ifc_create_credential_in_bits { 3953 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3954 struct mlx5_ifc_credential_bits credential; 3955 }; 3956 3957 struct mlx5_ifc_crypto_login_bits { 3958 u8 modify_field_select[0x40]; 3959 u8 reserved_at_40[0x48]; 3960 u8 credential_pointer[0x18]; 3961 u8 reserved_at_a0[0x8]; 3962 u8 session_import_kek_ptr[0x18]; 3963 u8 reserved_at_c0[0x140]; 3964 u8 credential[0x180]; 3965 u8 reserved_at_380[0x480]; 3966 }; 3967 3968 struct mlx5_ifc_create_crypto_login_in_bits { 3969 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3970 struct mlx5_ifc_crypto_login_bits crypto_login; 3971 }; 3972 3973 enum { 3974 MLX5_VIRTQ_STATE_INIT = 0, 3975 MLX5_VIRTQ_STATE_RDY = 1, 3976 MLX5_VIRTQ_STATE_SUSPEND = 2, 3977 MLX5_VIRTQ_STATE_ERROR = 3, 3978 }; 3979 3980 enum { 3981 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0), 3982 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3), 3983 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4), 3984 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD = (1UL << 5), 3985 MLX5_VIRTQ_MODIFY_TYPE_ADDR = (1UL << 6), 3986 MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX = (1UL << 7), 3987 MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX = (1UL << 8), 3988 MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE = (1UL << 9), 3989 MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0 = (1UL << 10), 3990 MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY = (1UL << 11), 3991 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK = (1UL << 12), 3992 MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE = (1UL << 13), 3993 }; 3994 3995 struct mlx5_ifc_virtio_q_bits { 3996 u8 virtio_q_type[0x8]; 3997 u8 reserved_at_8[0x5]; 3998 u8 event_mode[0x3]; 3999 u8 queue_index[0x10]; 4000 u8 full_emulation[0x1]; 4001 u8 virtio_version_1_0[0x1]; 4002 u8 reserved_at_22[0x2]; 4003 u8 offload_type[0x4]; 4004 u8 event_qpn_or_msix[0x18]; 4005 u8 doorbell_stride_idx[0x10]; 4006 u8 queue_size[0x10]; 4007 u8 device_emulation_id[0x20]; 4008 u8 desc_addr[0x40]; 4009 u8 used_addr[0x40]; 4010 u8 available_addr[0x40]; 4011 u8 virtio_q_mkey[0x20]; 4012 u8 reserved_at_160[0x18]; 4013 u8 error_type[0x8]; 4014 u8 umem_1_id[0x20]; 4015 u8 umem_1_size[0x20]; 4016 u8 umem_1_offset[0x40]; 4017 u8 umem_2_id[0x20]; 4018 u8 umem_2_size[0x20]; 4019 u8 umem_2_offset[0x40]; 4020 u8 umem_3_id[0x20]; 4021 u8 umem_3_size[0x20]; 4022 u8 umem_3_offset[0x40]; 4023 u8 counter_set_id[0x20]; 4024 u8 reserved_at_320[0x8]; 4025 u8 pd[0x18]; 4026 u8 reserved_at_340[0x2]; 4027 u8 queue_period_mode[0x2]; 4028 u8 queue_period_us[0xc]; 4029 u8 queue_max_count[0x10]; 4030 u8 reserved_at_360[0xa0]; 4031 }; 4032 4033 struct mlx5_ifc_virtio_net_q_bits { 4034 u8 modify_field_select[0x40]; 4035 u8 reserved_at_40[0x40]; 4036 u8 tso_ipv4[0x1]; 4037 u8 tso_ipv6[0x1]; 4038 u8 tx_csum[0x1]; 4039 u8 rx_csum[0x1]; 4040 u8 reserved_at_84[0x6]; 4041 u8 dirty_bitmap_dump_enable[0x1]; 4042 u8 vhost_log_page[0x5]; 4043 u8 reserved_at_90[0xc]; 4044 u8 state[0x4]; 4045 u8 reserved_at_a0[0x8]; 4046 u8 tisn_or_qpn[0x18]; 4047 u8 dirty_bitmap_mkey[0x20]; 4048 u8 dirty_bitmap_size[0x20]; 4049 u8 dirty_bitmap_addr[0x40]; 4050 u8 hw_available_index[0x10]; 4051 u8 hw_used_index[0x10]; 4052 u8 reserved_at_160[0xa0]; 4053 struct mlx5_ifc_virtio_q_bits virtio_q_context; 4054 }; 4055 4056 struct mlx5_ifc_create_virtq_in_bits { 4057 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4058 struct mlx5_ifc_virtio_net_q_bits virtq; 4059 }; 4060 4061 struct mlx5_ifc_query_virtq_out_bits { 4062 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4063 struct mlx5_ifc_virtio_net_q_bits virtq; 4064 }; 4065 4066 struct mlx5_ifc_flow_hit_aso_bits { 4067 u8 modify_field_select[0x40]; 4068 u8 reserved_at_40[0x48]; 4069 u8 access_pd[0x18]; 4070 u8 reserved_at_a0[0x160]; 4071 u8 flag[0x200]; 4072 }; 4073 4074 struct mlx5_ifc_create_flow_hit_aso_in_bits { 4075 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4076 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso; 4077 }; 4078 4079 struct mlx5_ifc_flow_meter_aso_bits { 4080 u8 modify_field_select[0x40]; 4081 u8 reserved_at_40[0x48]; 4082 u8 access_pd[0x18]; 4083 u8 reserved_at_a0[0x160]; 4084 u8 parameters[0x200]; 4085 }; 4086 4087 struct mlx5_ifc_create_flow_meter_aso_in_bits { 4088 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4089 struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso; 4090 }; 4091 4092 struct mlx5_ifc_tcp_window_params_bits { 4093 u8 max_ack[0x20]; 4094 u8 max_win[0x20]; 4095 u8 reply_end[0x20]; 4096 u8 sent_end[0x20]; 4097 }; 4098 4099 struct mlx5_ifc_conn_track_aso_bits { 4100 struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */ 4101 struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */ 4102 u8 last_end[0x20]; /* End of DW8. */ 4103 u8 last_ack[0x20]; /* End of DW9. */ 4104 u8 last_seq[0x20]; /* End of DW10. */ 4105 u8 last_win[0x10]; 4106 u8 reserved_at_170[0xa]; 4107 u8 last_dir[0x1]; 4108 u8 last_index[0x5]; /* End of DW11. */ 4109 u8 reserved_at_180[0x40]; /* End of DW13. */ 4110 u8 reply_direction_tcp_scale[0x4]; 4111 u8 reply_direction_tcp_close_initiated[0x1]; 4112 u8 reply_direction_tcp_liberal_enabled[0x1]; 4113 u8 reply_direction_tcp_data_unacked[0x1]; 4114 u8 reply_direction_tcp_max_ack[0x1]; 4115 u8 reserved_at_1c8[0x8]; 4116 u8 original_direction_tcp_scale[0x4]; 4117 u8 original_direction_tcp_close_initiated[0x1]; 4118 u8 original_direction_tcp_liberal_enabled[0x1]; 4119 u8 original_direction_tcp_data_unacked[0x1]; 4120 u8 original_direction_tcp_max_ack[0x1]; 4121 u8 reserved_at_1d8[0x8]; /* End of DW14. */ 4122 u8 valid[0x1]; 4123 u8 state[0x3]; 4124 u8 freeze_track[0x1]; 4125 u8 reserved_at_1e5[0xb]; 4126 u8 reserved_at_1f0[0x1]; 4127 u8 connection_assured[0x1]; 4128 u8 sack_permitted[0x1]; 4129 u8 challenged_acked[0x1]; 4130 u8 heartbeat[0x1]; 4131 u8 max_ack_window[0x3]; 4132 u8 reserved_at_1f8[0x1]; 4133 u8 retransmission_counter[0x3]; 4134 u8 retranmission_limit_exceeded[0x1]; 4135 u8 retranmission_limit[0x3]; /* End of DW15. */ 4136 }; 4137 4138 struct mlx5_ifc_conn_track_offload_bits { 4139 u8 modify_field_select[0x40]; 4140 u8 reserved_at_40[0x40]; 4141 u8 reserved_at_80[0x8]; 4142 u8 conn_track_aso_access_pd[0x18]; 4143 u8 reserved_at_a0[0x160]; 4144 struct mlx5_ifc_conn_track_aso_bits conn_track_aso; 4145 }; 4146 4147 struct mlx5_ifc_create_conn_track_aso_in_bits { 4148 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4149 struct mlx5_ifc_conn_track_offload_bits conn_track_offload; 4150 }; 4151 4152 enum mlx5_access_aso_opc_mod { 4153 ASO_OPC_MOD_IPSEC = 0x0, 4154 ASO_OPC_MOD_CONNECTION_TRACKING = 0x1, 4155 ASO_OPC_MOD_POLICER = 0x2, 4156 ASO_OPC_MOD_RACE_AVOIDANCE = 0x3, 4157 ASO_OPC_MOD_FLOW_HIT = 0x4, 4158 }; 4159 4160 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30 4161 4162 enum mlx5_aso_data_mask_mode { 4163 BITWISE_64BIT = 0x0, 4164 BYTEWISE_64BYTE = 0x1, 4165 CALCULATED_64BYTE = 0x2, 4166 }; 4167 4168 #define ASO_CSEG_COND_0_OPER_OFFSET 20 4169 #define ASO_CSEG_COND_1_OPER_OFFSET 16 4170 4171 enum mlx5_aso_pre_cond_op { 4172 ASO_OP_ALWAYS_FALSE = 0x0, 4173 ASO_OP_ALWAYS_TRUE = 0x1, 4174 ASO_OP_EQUAL = 0x2, 4175 ASO_OP_NOT_EQUAL = 0x3, 4176 ASO_OP_GREATER_OR_EQUAL = 0x4, 4177 ASO_OP_LESSER_OR_EQUAL = 0x5, 4178 ASO_OP_LESSER = 0x6, 4179 ASO_OP_GREATER = 0x7, 4180 ASO_OP_CYCLIC_GREATER = 0x8, 4181 ASO_OP_CYCLIC_LESSER = 0x9, 4182 }; 4183 4184 #define ASO_CSEG_COND_OPER_OFFSET 6 4185 4186 enum mlx5_aso_op { 4187 ASO_OPER_LOGICAL_AND = 0x0, 4188 ASO_OPER_LOGICAL_OR = 0x1, 4189 }; 4190 4191 #define MLX5_ASO_CSEG_READ_ENABLE 1 4192 4193 /* ASO WQE CTRL segment. */ 4194 struct __rte_packed_begin mlx5_aso_cseg { 4195 uint32_t va_h; 4196 uint32_t va_l_r; 4197 uint32_t lkey; 4198 uint32_t operand_masks; 4199 uint32_t condition_0_data; 4200 uint32_t condition_0_mask; 4201 uint32_t condition_1_data; 4202 uint32_t condition_1_mask; 4203 uint64_t bitwise_data; 4204 uint64_t data_mask; 4205 } __rte_packed_end; 4206 4207 #define MLX5_MTR_MAX_TOKEN_VALUE INT32_MAX 4208 4209 /* A meter data segment - 2 per ASO WQE. */ 4210 struct __rte_packed_begin mlx5_aso_mtr_dseg { 4211 uint32_t v_bo_sc_bbog_mm; 4212 /* 4213 * bit 31: valid, 30: bucket overflow, 28-29: start color, 4214 * 27: both buckets on green, 24-25: meter mode. 4215 */ 4216 uint32_t reserved; 4217 uint32_t cbs_cir; 4218 /* 4219 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 4220 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 4221 */ 4222 uint32_t c_tokens; 4223 uint32_t ebs_eir; 4224 /* 4225 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 4226 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 4227 */ 4228 uint32_t e_tokens; 4229 uint64_t timestamp; 4230 } __rte_packed_end; 4231 4232 #define ASO_DSEG_VALID_OFFSET 31 4233 #define ASO_DSEG_BO_OFFSET 30 4234 #define ASO_DSEG_SC_OFFSET 28 4235 #define ASO_DSEG_BBOG_OFFSET 27 4236 #define ASO_DSEG_MTR_MODE 24 4237 #define ASO_DSEG_CBS_EXP_OFFSET 24 4238 #define ASO_DSEG_CBS_MAN_OFFSET 16 4239 #define ASO_DSEG_XIR_EXP_MASK 0x1F 4240 #define ASO_DSEG_XIR_EXP_OFFSET 8 4241 #define ASO_DSEG_EBS_EXP_OFFSET 24 4242 #define ASO_DSEG_EBS_MAN_OFFSET 16 4243 #define ASO_DSEG_EXP_MASK 0x1F 4244 #define ASO_DSEG_MAN_MASK 0xFF 4245 4246 #define MLX5_ASO_WQE_DSEG_SIZE 0x40 4247 #define MLX5_ASO_METERS_PER_WQE 2 4248 #define MLX5_ASO_MTRS_PER_POOL 128 4249 4250 /* ASO WQE data segment. */ 4251 struct __rte_packed_begin mlx5_aso_dseg { 4252 union { 4253 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE]; 4254 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE]; 4255 }; 4256 } __rte_packed_end; 4257 4258 /* ASO WQE. */ 4259 struct __rte_packed_begin mlx5_aso_wqe { 4260 struct mlx5_wqe_cseg general_cseg; 4261 struct mlx5_aso_cseg aso_cseg; 4262 struct mlx5_aso_dseg aso_dseg; 4263 } __rte_packed_end; 4264 4265 enum { 4266 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, 4267 MLX5_EVENT_TYPE_SRQ_LIMIT_REACHED = 0x14, 4268 }; 4269 4270 enum { 4271 MLX5_QP_ST_RC = 0x0, 4272 }; 4273 4274 enum { 4275 MLX5_QP_PM_MIGRATED = 0x3, 4276 }; 4277 4278 enum { 4279 MLX5_NON_ZERO_RQ = 0x0, 4280 MLX5_SRQ_RQ = 0x1, 4281 MLX5_CRQ_RQ = 0x2, 4282 MLX5_ZERO_LEN_RQ = 0x3, 4283 }; 4284 4285 struct mlx5_ifc_ads_bits { 4286 u8 fl[0x1]; 4287 u8 free_ar[0x1]; 4288 u8 reserved_at_2[0xe]; 4289 u8 pkey_index[0x10]; 4290 u8 reserved_at_20[0x8]; 4291 u8 grh[0x1]; 4292 u8 mlid[0x7]; 4293 u8 rlid[0x10]; 4294 u8 ack_timeout[0x5]; 4295 u8 reserved_at_45[0x3]; 4296 u8 src_addr_index[0x8]; 4297 u8 reserved_at_50[0x4]; 4298 u8 stat_rate[0x4]; 4299 u8 hop_limit[0x8]; 4300 u8 reserved_at_60[0x4]; 4301 u8 tclass[0x8]; 4302 u8 flow_label[0x14]; 4303 u8 rgid_rip[16][0x8]; 4304 u8 reserved_at_100[0x4]; 4305 u8 f_dscp[0x1]; 4306 u8 f_ecn[0x1]; 4307 u8 reserved_at_106[0x1]; 4308 u8 f_eth_prio[0x1]; 4309 u8 ecn[0x2]; 4310 u8 dscp[0x6]; 4311 u8 udp_sport[0x10]; 4312 u8 dei_cfi[0x1]; 4313 u8 eth_prio[0x3]; 4314 u8 sl[0x4]; 4315 u8 vhca_port_num[0x8]; 4316 u8 rmac_47_32[0x10]; 4317 u8 rmac_31_0[0x20]; 4318 }; 4319 4320 struct mlx5_ifc_qpc_bits { 4321 u8 state[0x4]; 4322 u8 lag_tx_port_affinity[0x4]; 4323 u8 st[0x8]; 4324 u8 reserved_at_10[0x3]; 4325 u8 pm_state[0x2]; 4326 u8 reserved_at_15[0x1]; 4327 u8 req_e2e_credit_mode[0x2]; 4328 u8 offload_type[0x4]; 4329 u8 end_padding_mode[0x2]; 4330 u8 reserved_at_1e[0x2]; 4331 u8 wq_signature[0x1]; 4332 u8 block_lb_mc[0x1]; 4333 u8 atomic_like_write_en[0x1]; 4334 u8 latency_sensitive[0x1]; 4335 u8 reserved_at_24[0x1]; 4336 u8 drain_sigerr[0x1]; 4337 u8 reserved_at_26[0x2]; 4338 u8 pd[0x18]; 4339 u8 mtu[0x3]; 4340 u8 log_msg_max[0x5]; 4341 u8 reserved_at_48[0x1]; 4342 u8 log_rq_size[0x4]; 4343 u8 log_rq_stride[0x3]; 4344 u8 no_sq[0x1]; 4345 u8 log_sq_size[0x4]; 4346 u8 reserved_at_55[0x3]; 4347 u8 ts_format[0x2]; 4348 u8 reserved_at_5a[0x1]; 4349 u8 rlky[0x1]; 4350 u8 ulp_stateless_offload_mode[0x4]; 4351 u8 counter_set_id[0x8]; 4352 u8 uar_page[0x18]; 4353 u8 reserved_at_80[0x8]; 4354 u8 user_index[0x18]; 4355 u8 reserved_at_a0[0x3]; 4356 u8 log_page_size[0x5]; 4357 u8 remote_qpn[0x18]; 4358 struct mlx5_ifc_ads_bits primary_address_path; 4359 struct mlx5_ifc_ads_bits secondary_address_path; 4360 u8 log_ack_req_freq[0x4]; 4361 u8 reserved_at_384[0x4]; 4362 u8 log_sra_max[0x3]; 4363 u8 reserved_at_38b[0x2]; 4364 u8 retry_count[0x3]; 4365 u8 rnr_retry[0x3]; 4366 u8 reserved_at_393[0x1]; 4367 u8 fre[0x1]; 4368 u8 cur_rnr_retry[0x3]; 4369 u8 cur_retry_count[0x3]; 4370 u8 reserved_at_39b[0x5]; 4371 u8 reserved_at_3a0[0x20]; 4372 u8 reserved_at_3c0[0x8]; 4373 u8 next_send_psn[0x18]; 4374 u8 reserved_at_3e0[0x8]; 4375 u8 cqn_snd[0x18]; 4376 u8 reserved_at_400[0x8]; 4377 u8 deth_sqpn[0x18]; 4378 u8 reserved_at_420[0x20]; 4379 u8 reserved_at_440[0x8]; 4380 u8 last_acked_psn[0x18]; 4381 u8 reserved_at_460[0x8]; 4382 u8 ssn[0x18]; 4383 u8 reserved_at_480[0x8]; 4384 u8 log_rra_max[0x3]; 4385 u8 reserved_at_48b[0x1]; 4386 u8 atomic_mode[0x4]; 4387 u8 rre[0x1]; 4388 u8 rwe[0x1]; 4389 u8 rae[0x1]; 4390 u8 reserved_at_493[0x1]; 4391 u8 page_offset[0x6]; 4392 u8 reserved_at_49a[0x3]; 4393 u8 cd_slave_receive[0x1]; 4394 u8 cd_slave_send[0x1]; 4395 u8 cd_master[0x1]; 4396 u8 reserved_at_4a0[0x3]; 4397 u8 min_rnr_nak[0x5]; 4398 u8 next_rcv_psn[0x18]; 4399 u8 reserved_at_4c0[0x8]; 4400 u8 xrcd[0x18]; 4401 u8 reserved_at_4e0[0x8]; 4402 u8 cqn_rcv[0x18]; 4403 u8 dbr_addr[0x40]; 4404 u8 q_key[0x20]; 4405 u8 reserved_at_560[0x5]; 4406 u8 rq_type[0x3]; 4407 u8 srqn_rmpn_xrqn[0x18]; 4408 u8 reserved_at_580[0x8]; 4409 u8 rmsn[0x18]; 4410 u8 hw_sq_wqebb_counter[0x10]; 4411 u8 sw_sq_wqebb_counter[0x10]; 4412 u8 hw_rq_counter[0x20]; 4413 u8 sw_rq_counter[0x20]; 4414 u8 reserved_at_600[0x20]; 4415 u8 reserved_at_620[0xf]; 4416 u8 cgs[0x1]; 4417 u8 cs_req[0x8]; 4418 u8 cs_res[0x8]; 4419 u8 dc_access_key[0x40]; 4420 u8 reserved_at_680[0x3]; 4421 u8 dbr_umem_valid[0x1]; 4422 u8 reserved_at_684[0x9c]; 4423 u8 dbr_umem_id[0x20]; 4424 }; 4425 4426 struct mlx5_ifc_create_qp_out_bits { 4427 u8 status[0x8]; 4428 u8 reserved_at_8[0x18]; 4429 u8 syndrome[0x20]; 4430 u8 reserved_at_40[0x8]; 4431 u8 qpn[0x18]; 4432 u8 reserved_at_60[0x20]; 4433 }; 4434 4435 struct mlx5_ifc_qpc_extension_bits { 4436 u8 reserved_at_0[0x2]; 4437 u8 mmo[0x1]; 4438 u8 reserved_at_3[0x5fd]; 4439 }; 4440 4441 #ifdef PEDANTIC 4442 #pragma GCC diagnostic ignored "-Wpedantic" 4443 #endif 4444 struct mlx5_ifc_qpc_pas_list_bits { 4445 u8 pas[0][0x40]; 4446 }; 4447 4448 #ifdef PEDANTIC 4449 #pragma GCC diagnostic ignored "-Wpedantic" 4450 #endif 4451 struct mlx5_ifc_qpc_extension_and_pas_list_bits { 4452 struct mlx5_ifc_qpc_extension_bits qpc_data_extension; 4453 u8 pas[][0x40]; 4454 }; 4455 4456 4457 #ifdef PEDANTIC 4458 #pragma GCC diagnostic ignored "-Wpedantic" 4459 #endif 4460 struct mlx5_ifc_create_qp_in_bits { 4461 u8 opcode[0x10]; 4462 u8 uid[0x10]; 4463 u8 reserved_at_20[0x10]; 4464 u8 op_mod[0x10]; 4465 u8 qpc_ext[0x1]; 4466 u8 reserved_at_41[0x3f]; 4467 u8 opt_param_mask[0x20]; 4468 u8 reserved_at_a0[0x20]; 4469 struct mlx5_ifc_qpc_bits qpc; 4470 u8 wq_umem_offset[0x40]; 4471 u8 wq_umem_id[0x20]; 4472 u8 wq_umem_valid[0x1]; 4473 u8 reserved_at_861[0x1f]; 4474 union { 4475 struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list; 4476 struct mlx5_ifc_qpc_extension_and_pas_list_bits 4477 qpc_extension_and_pas_list; 4478 }; 4479 }; 4480 #ifdef PEDANTIC 4481 #pragma GCC diagnostic error "-Wpedantic" 4482 #endif 4483 4484 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4485 u8 status[0x8]; 4486 u8 reserved_at_8[0x18]; 4487 u8 syndrome[0x20]; 4488 u8 reserved_at_40[0x40]; 4489 }; 4490 4491 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4492 u8 opcode[0x10]; 4493 u8 uid[0x10]; 4494 u8 reserved_at_20[0x10]; 4495 u8 op_mod[0x10]; 4496 u8 reserved_at_40[0x8]; 4497 u8 qpn[0x18]; 4498 u8 reserved_at_60[0x20]; 4499 u8 opt_param_mask[0x20]; 4500 u8 reserved_at_a0[0x20]; 4501 struct mlx5_ifc_qpc_bits qpc; 4502 u8 reserved_at_800[0x80]; 4503 }; 4504 4505 struct mlx5_ifc_sqd2rts_qp_out_bits { 4506 u8 status[0x8]; 4507 u8 reserved_at_8[0x18]; 4508 u8 syndrome[0x20]; 4509 u8 reserved_at_40[0x40]; 4510 }; 4511 4512 struct mlx5_ifc_sqd2rts_qp_in_bits { 4513 u8 opcode[0x10]; 4514 u8 uid[0x10]; 4515 u8 reserved_at_20[0x10]; 4516 u8 op_mod[0x10]; 4517 u8 reserved_at_40[0x8]; 4518 u8 qpn[0x18]; 4519 u8 reserved_at_60[0x20]; 4520 u8 opt_param_mask[0x20]; 4521 u8 reserved_at_a0[0x20]; 4522 struct mlx5_ifc_qpc_bits qpc; 4523 u8 reserved_at_800[0x80]; 4524 }; 4525 4526 struct mlx5_ifc_rts2rts_qp_out_bits { 4527 u8 status[0x8]; 4528 u8 reserved_at_8[0x18]; 4529 u8 syndrome[0x20]; 4530 u8 reserved_at_40[0x40]; 4531 }; 4532 4533 struct mlx5_ifc_rts2rts_qp_in_bits { 4534 u8 opcode[0x10]; 4535 u8 uid[0x10]; 4536 u8 reserved_at_20[0x10]; 4537 u8 op_mod[0x10]; 4538 u8 reserved_at_40[0x8]; 4539 u8 qpn[0x18]; 4540 u8 reserved_at_60[0x20]; 4541 u8 opt_param_mask[0x20]; 4542 u8 reserved_at_a0[0x20]; 4543 struct mlx5_ifc_qpc_bits qpc; 4544 u8 reserved_at_800[0x80]; 4545 }; 4546 4547 struct mlx5_ifc_rtr2rts_qp_out_bits { 4548 u8 status[0x8]; 4549 u8 reserved_at_8[0x18]; 4550 u8 syndrome[0x20]; 4551 u8 reserved_at_40[0x40]; 4552 }; 4553 4554 struct mlx5_ifc_rtr2rts_qp_in_bits { 4555 u8 opcode[0x10]; 4556 u8 uid[0x10]; 4557 u8 reserved_at_20[0x10]; 4558 u8 op_mod[0x10]; 4559 u8 reserved_at_40[0x8]; 4560 u8 qpn[0x18]; 4561 u8 reserved_at_60[0x20]; 4562 u8 opt_param_mask[0x20]; 4563 u8 reserved_at_a0[0x20]; 4564 struct mlx5_ifc_qpc_bits qpc; 4565 u8 reserved_at_800[0x80]; 4566 }; 4567 4568 struct mlx5_ifc_rst2init_qp_out_bits { 4569 u8 status[0x8]; 4570 u8 reserved_at_8[0x18]; 4571 u8 syndrome[0x20]; 4572 u8 reserved_at_40[0x40]; 4573 }; 4574 4575 struct mlx5_ifc_rst2init_qp_in_bits { 4576 u8 opcode[0x10]; 4577 u8 uid[0x10]; 4578 u8 reserved_at_20[0x10]; 4579 u8 op_mod[0x10]; 4580 u8 reserved_at_40[0x8]; 4581 u8 qpn[0x18]; 4582 u8 reserved_at_60[0x20]; 4583 u8 opt_param_mask[0x20]; 4584 u8 reserved_at_a0[0x20]; 4585 struct mlx5_ifc_qpc_bits qpc; 4586 u8 reserved_at_800[0x80]; 4587 }; 4588 4589 struct mlx5_ifc_init2rtr_qp_out_bits { 4590 u8 status[0x8]; 4591 u8 reserved_at_8[0x18]; 4592 u8 syndrome[0x20]; 4593 u8 reserved_at_40[0x40]; 4594 }; 4595 4596 struct mlx5_ifc_init2rtr_qp_in_bits { 4597 u8 opcode[0x10]; 4598 u8 uid[0x10]; 4599 u8 reserved_at_20[0x10]; 4600 u8 op_mod[0x10]; 4601 u8 reserved_at_40[0x8]; 4602 u8 qpn[0x18]; 4603 u8 reserved_at_60[0x20]; 4604 u8 opt_param_mask[0x20]; 4605 u8 reserved_at_a0[0x20]; 4606 struct mlx5_ifc_qpc_bits qpc; 4607 u8 reserved_at_800[0x80]; 4608 }; 4609 4610 struct mlx5_ifc_init2init_qp_out_bits { 4611 u8 status[0x8]; 4612 u8 reserved_at_8[0x18]; 4613 u8 syndrome[0x20]; 4614 u8 reserved_at_40[0x40]; 4615 }; 4616 4617 struct mlx5_ifc_init2init_qp_in_bits { 4618 u8 opcode[0x10]; 4619 u8 uid[0x10]; 4620 u8 reserved_at_20[0x10]; 4621 u8 op_mod[0x10]; 4622 u8 reserved_at_40[0x8]; 4623 u8 qpn[0x18]; 4624 u8 reserved_at_60[0x20]; 4625 u8 opt_param_mask[0x20]; 4626 u8 reserved_at_a0[0x20]; 4627 struct mlx5_ifc_qpc_bits qpc; 4628 u8 reserved_at_800[0x80]; 4629 }; 4630 4631 struct mlx5_ifc_2rst_qp_out_bits { 4632 u8 status[0x8]; 4633 u8 reserved_at_8[0x18]; 4634 u8 syndrome[0x20]; 4635 u8 reserved_at_40[0x40]; 4636 }; 4637 4638 struct mlx5_ifc_2rst_qp_in_bits { 4639 u8 opcode[0x10]; 4640 u8 uid[0x10]; 4641 u8 vhca_tunnel_id[0x10]; 4642 u8 op_mod[0x10]; 4643 u8 reserved_at_80[0x8]; 4644 u8 qpn[0x18]; 4645 u8 reserved_at_a0[0x20]; 4646 }; 4647 4648 struct mlx5_ifc_dealloc_pd_out_bits { 4649 u8 status[0x8]; 4650 u8 reserved_0[0x18]; 4651 u8 syndrome[0x20]; 4652 u8 reserved_1[0x40]; 4653 }; 4654 4655 struct mlx5_ifc_dealloc_pd_in_bits { 4656 u8 opcode[0x10]; 4657 u8 reserved_0[0x10]; 4658 u8 reserved_1[0x10]; 4659 u8 op_mod[0x10]; 4660 u8 reserved_2[0x8]; 4661 u8 pd[0x18]; 4662 u8 reserved_3[0x20]; 4663 }; 4664 4665 struct mlx5_ifc_alloc_pd_out_bits { 4666 u8 status[0x8]; 4667 u8 reserved_0[0x18]; 4668 u8 syndrome[0x20]; 4669 u8 reserved_1[0x8]; 4670 u8 pd[0x18]; 4671 u8 reserved_2[0x20]; 4672 }; 4673 4674 struct mlx5_ifc_alloc_pd_in_bits { 4675 u8 opcode[0x10]; 4676 u8 reserved_0[0x10]; 4677 u8 reserved_1[0x10]; 4678 u8 op_mod[0x10]; 4679 u8 reserved_2[0x40]; 4680 }; 4681 4682 #ifdef PEDANTIC 4683 #pragma GCC diagnostic ignored "-Wpedantic" 4684 #endif 4685 struct mlx5_ifc_query_qp_out_bits { 4686 u8 status[0x8]; 4687 u8 reserved_at_8[0x18]; 4688 u8 syndrome[0x20]; 4689 u8 reserved_at_40[0x40]; 4690 u8 opt_param_mask[0x20]; 4691 u8 reserved_at_a0[0x20]; 4692 struct mlx5_ifc_qpc_bits qpc; 4693 u8 reserved_at_800[0x80]; 4694 u8 pas[][0x40]; 4695 }; 4696 #ifdef PEDANTIC 4697 #pragma GCC diagnostic error "-Wpedantic" 4698 #endif 4699 4700 struct mlx5_ifc_query_qp_in_bits { 4701 u8 opcode[0x10]; 4702 u8 reserved_at_10[0x10]; 4703 u8 reserved_at_20[0x10]; 4704 u8 op_mod[0x10]; 4705 u8 reserved_at_40[0x8]; 4706 u8 qpn[0x18]; 4707 u8 reserved_at_60[0x20]; 4708 }; 4709 4710 enum { 4711 MLX5_DATA_RATE = 0x0, 4712 MLX5_WQE_RATE = 0x1, 4713 }; 4714 4715 struct mlx5_ifc_set_pp_rate_limit_context_bits { 4716 u8 rate_limit[0x20]; 4717 u8 burst_upper_bound[0x20]; 4718 u8 reserved_at_40[0xC]; 4719 u8 rate_mode[0x4]; 4720 u8 typical_packet_size[0x10]; 4721 u8 reserved_at_60[0x120]; 4722 }; 4723 4724 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u 4725 4726 #ifdef PEDANTIC 4727 #pragma GCC diagnostic ignored "-Wpedantic" 4728 #endif 4729 struct mlx5_ifc_access_register_out_bits { 4730 u8 status[0x8]; 4731 u8 reserved_at_8[0x18]; 4732 u8 syndrome[0x20]; 4733 u8 reserved_at_40[0x40]; 4734 u8 register_data[][0x20]; 4735 }; 4736 4737 struct mlx5_ifc_access_register_in_bits { 4738 u8 opcode[0x10]; 4739 u8 reserved_at_10[0x10]; 4740 u8 reserved_at_20[0x10]; 4741 u8 op_mod[0x10]; 4742 u8 reserved_at_40[0x10]; 4743 u8 register_id[0x10]; 4744 u8 argument[0x20]; 4745 u8 register_data[][0x20]; 4746 }; 4747 #ifdef PEDANTIC 4748 #pragma GCC diagnostic error "-Wpedantic" 4749 #endif 4750 4751 enum { 4752 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 4753 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 4754 }; 4755 4756 enum { 4757 MLX5_REGISTER_ID_MTUTC = 0x9055, 4758 MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002, 4759 MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, 4760 MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, 4761 MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, 4762 MLX5_QSHR_REGISTER_ID = 0x4030, 4763 }; 4764 4765 struct mlx5_ifc_register_mtutc_bits { 4766 u8 time_stamp_mode[0x2]; 4767 u8 time_stamp_state[0x2]; 4768 u8 reserved_at_4[0x18]; 4769 u8 operation[0x4]; 4770 u8 freq_adjustment[0x20]; 4771 u8 reserved_at_40[0x40]; 4772 u8 utc_sec[0x20]; 4773 u8 utc_nsec[0x20]; 4774 u8 time_adjustment[0x20]; 4775 }; 4776 4777 struct mlx5_ifc_ets_global_config_register_bits { 4778 u8 reserved_at_0[0x2]; 4779 u8 rate_limit_update[0x1]; 4780 u8 reserved_at_3[0x29]; 4781 u8 max_bw_units[0x4]; 4782 u8 reserved_at_48[0x8]; 4783 u8 max_bw_value[0x8]; 4784 }; 4785 4786 #define ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED 0x0 4787 #define ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS 0x3 4788 #define ETS_GLOBAL_CONFIG_BW_UNIT_GBPS 0x4 4789 4790 struct mlx5_ifc_register_qshr_bits { 4791 u8 reserved_at_0[0x4]; 4792 u8 connected_host[0x1]; 4793 u8 vqos[0x1]; 4794 u8 fast_response[0x1]; 4795 u8 reserved_at_7[0x1]; 4796 u8 local_port[0x8]; 4797 u8 reserved_at_16[0x230]; 4798 struct mlx5_ifc_ets_global_config_register_bits global_config; 4799 }; 4800 4801 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 4802 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 4803 4804 struct mlx5_ifc_crypto_operational_register_bits { 4805 u8 wrapped_crypto_operational[0x1]; 4806 u8 reserved_at_1[0x1b]; 4807 u8 kek_size[0x4]; 4808 u8 reserved_at_20[0x20]; 4809 u8 credential[0x140]; 4810 u8 kek[0x100]; 4811 u8 reserved_at_280[0x180]; 4812 }; 4813 4814 struct mlx5_ifc_crypto_caps_bits { 4815 u8 wrapped_crypto_operational[0x1]; 4816 u8 wrapped_crypto_going_to_commissioning[0x1]; 4817 u8 sw_wrapped_dek[0x1]; 4818 u8 synchronize_dek[0x1]; 4819 u8 int_kek_manual[0x1]; 4820 u8 int_kek_auto[0x1]; 4821 u8 reserved_at_6[0xd]; 4822 u8 sw_wrapped_dek_key_purpose[0x1]; 4823 u8 reserved_at_14[0x4]; 4824 u8 wrapped_import_method[0x8]; 4825 u8 reserved_at_20[0x3]; 4826 u8 log_dek_max_alloc[0x5]; 4827 u8 reserved_at_28[0x3]; 4828 u8 log_max_num_deks[0x5]; 4829 u8 reserved_at_30[0x3]; 4830 u8 log_max_num_import_keks[0x5]; 4831 u8 reserved_at_38[0x3]; 4832 u8 log_max_num_creds[0x5]; 4833 u8 failed_selftests[0x10]; 4834 u8 num_nv_import_keks[0x8]; 4835 u8 num_nv_credentials[0x8]; 4836 u8 reserved_at_60[0x3]; 4837 u8 log_dek_granularity[0x5]; 4838 u8 reserved_at_68[0x3]; 4839 u8 log_max_num_int_kek[0x5]; 4840 u8 sw_wrapped_dek_new[0x10]; 4841 u8 reserved_at_80[0x80]; 4842 u8 crypto_mmo_qp[0x1]; 4843 u8 crypto_aes_gcm_256_encrypt[0x1]; 4844 u8 crypto_aes_gcm_128_encrypt[0x1]; 4845 u8 crypto_aes_gcm_256_decrypt[0x1]; 4846 u8 crypto_aes_gcm_128_decrypt[0x1]; 4847 u8 gcm_auth_tag_128[0x1]; 4848 u8 gcm_auth_tag_96[0x1]; 4849 u8 reserved_at_107[0x3]; 4850 u8 log_crypto_mmo_max_size[0x6]; 4851 u8 reserved_at_110[0x10]; 4852 u8 reserved_at_120[0x6e0]; 4853 }; 4854 4855 struct mlx5_ifc_crypto_commissioning_register_bits { 4856 u8 token[0x1]; /* TODO: add size after PRM update */ 4857 }; 4858 4859 struct mlx5_ifc_import_kek_handle_register_bits { 4860 struct mlx5_ifc_crypto_login_bits crypto_login_object; 4861 struct mlx5_ifc_import_kek_bits import_kek_object; 4862 u8 reserved_at_200[0x4]; 4863 u8 write_operation[0x4]; 4864 u8 import_kek_id[0x18]; 4865 u8 reserved_at_220[0xe0]; 4866 }; 4867 4868 struct mlx5_ifc_credential_handle_register_bits { 4869 struct mlx5_ifc_crypto_login_bits crypto_login_object; 4870 struct mlx5_ifc_credential_bits credential_object; 4871 u8 reserved_at_200[0x4]; 4872 u8 write_operation[0x4]; 4873 u8 credential_id[0x18]; 4874 u8 reserved_at_220[0xe0]; 4875 }; 4876 4877 enum { 4878 MLX5_REGISTER_ADD_OPERATION = 0x1, 4879 MLX5_REGISTER_DELETE_OPERATION = 0x2, 4880 }; 4881 4882 struct mlx5_ifc_parse_graph_arc_bits { 4883 u8 start_inner_tunnel[0x1]; 4884 u8 reserved_at_1[0x7]; 4885 u8 arc_parse_graph_node[0x8]; 4886 u8 compare_condition_value[0x10]; 4887 u8 parse_graph_node_handle[0x20]; 4888 u8 reserved_at_40[0x40]; 4889 }; 4890 4891 struct mlx5_ifc_parse_graph_flow_match_sample_bits { 4892 u8 flow_match_sample_en[0x1]; 4893 u8 reserved_at_1[0x3]; 4894 u8 flow_match_sample_offset_mode[0x4]; 4895 u8 reserved_at_5[0x8]; 4896 u8 flow_match_sample_field_offset[0x10]; 4897 u8 reserved_at_32[0x4]; 4898 u8 flow_match_sample_field_offset_shift[0x4]; 4899 u8 flow_match_sample_field_base_offset[0x8]; 4900 u8 reserved_at_48[0xd]; 4901 u8 flow_match_sample_tunnel_mode[0x3]; 4902 u8 flow_match_sample_field_offset_mask[0x20]; 4903 u8 flow_match_sample_field_id[0x20]; 4904 }; 4905 4906 struct mlx5_ifc_parse_graph_flex_bits { 4907 u8 modify_field_select[0x40]; 4908 u8 reserved_at_64[0x20]; 4909 u8 header_length_base_value[0x10]; 4910 u8 reserved_at_112[0x4]; 4911 u8 header_length_field_shift[0x4]; 4912 u8 reserved_at_120[0x4]; 4913 u8 header_length_mode[0x4]; 4914 u8 header_length_field_offset[0x10]; 4915 u8 next_header_field_offset[0x10]; 4916 u8 reserved_at_160[0x12]; 4917 u8 head_anchor_id[0x6]; 4918 u8 reserved_at_178[0x3]; 4919 u8 next_header_field_size[0x5]; 4920 u8 header_length_field_mask[0x20]; 4921 u8 reserved_at_224[0x20]; 4922 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8]; 4923 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8]; 4924 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8]; 4925 }; 4926 4927 struct mlx5_ifc_create_flex_parser_in_bits { 4928 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4929 struct mlx5_ifc_parse_graph_flex_bits flex; 4930 }; 4931 4932 struct mlx5_ifc_create_flex_parser_out_bits { 4933 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4934 struct mlx5_ifc_parse_graph_flex_bits flex; 4935 }; 4936 4937 struct mlx5_ifc_parse_graph_flex_out_bits { 4938 u8 status[0x8]; 4939 u8 reserved_at_8[0x18]; 4940 u8 syndrome[0x20]; 4941 u8 reserved_at_40[0x40]; 4942 struct mlx5_ifc_parse_graph_flex_bits capability; 4943 }; 4944 4945 struct regexp_params_field_select_bits { 4946 u8 reserved_at_0[0x1d]; 4947 u8 rof_mkey[0x1]; 4948 u8 stop_engine[0x1]; 4949 u8 reserved_at_1f[0x1]; 4950 }; 4951 4952 struct mlx5_ifc_regexp_params_bits { 4953 u8 reserved_at_0[0x1f]; 4954 u8 stop_engine[0x1]; 4955 u8 reserved_at_20[0x60]; 4956 u8 rof_mkey[0x20]; 4957 u8 rof_size[0x20]; 4958 u8 rof_mkey_va[0x40]; 4959 u8 reserved_at_100[0x80]; 4960 }; 4961 4962 struct mlx5_ifc_set_regexp_params_in_bits { 4963 u8 opcode[0x10]; 4964 u8 uid[0x10]; 4965 u8 reserved_at_20[0x10]; 4966 u8 op_mod[0x10]; 4967 u8 reserved_at_40[0x18]; 4968 u8 engine_id[0x8]; 4969 struct regexp_params_field_select_bits field_select; 4970 struct mlx5_ifc_regexp_params_bits regexp_params; 4971 }; 4972 4973 struct mlx5_ifc_set_regexp_params_out_bits { 4974 u8 status[0x8]; 4975 u8 reserved_at_8[0x18]; 4976 u8 syndrome[0x20]; 4977 u8 reserved_at_18[0x40]; 4978 }; 4979 4980 struct mlx5_ifc_query_regexp_params_in_bits { 4981 u8 opcode[0x10]; 4982 u8 uid[0x10]; 4983 u8 reserved_at_20[0x10]; 4984 u8 op_mod[0x10]; 4985 u8 reserved_at_40[0x18]; 4986 u8 engine_id[0x8]; 4987 u8 reserved[0x20]; 4988 }; 4989 4990 struct mlx5_ifc_query_regexp_params_out_bits { 4991 u8 status[0x8]; 4992 u8 reserved_at_8[0x18]; 4993 u8 syndrome[0x20]; 4994 u8 reserved[0x40]; 4995 struct mlx5_ifc_regexp_params_bits regexp_params; 4996 }; 4997 4998 struct mlx5_ifc_set_regexp_register_in_bits { 4999 u8 opcode[0x10]; 5000 u8 uid[0x10]; 5001 u8 reserved_at_20[0x10]; 5002 u8 op_mod[0x10]; 5003 u8 reserved_at_40[0x18]; 5004 u8 engine_id[0x8]; 5005 u8 register_address[0x20]; 5006 u8 register_data[0x20]; 5007 u8 reserved[0x60]; 5008 }; 5009 5010 struct mlx5_ifc_set_regexp_register_out_bits { 5011 u8 status[0x8]; 5012 u8 reserved_at_8[0x18]; 5013 u8 syndrome[0x20]; 5014 u8 reserved[0x40]; 5015 }; 5016 5017 struct mlx5_ifc_query_regexp_register_in_bits { 5018 u8 opcode[0x10]; 5019 u8 uid[0x10]; 5020 u8 reserved_at_20[0x10]; 5021 u8 op_mod[0x10]; 5022 u8 reserved_at_40[0x18]; 5023 u8 engine_id[0x8]; 5024 u8 register_address[0x20]; 5025 }; 5026 5027 struct mlx5_ifc_query_regexp_register_out_bits { 5028 u8 status[0x8]; 5029 u8 reserved_at_8[0x18]; 5030 u8 syndrome[0x20]; 5031 u8 reserved[0x20]; 5032 u8 register_data[0x20]; 5033 }; 5034 5035 /* Queue counters. */ 5036 struct mlx5_ifc_alloc_q_counter_out_bits { 5037 u8 status[0x8]; 5038 u8 reserved_at_8[0x18]; 5039 u8 syndrome[0x20]; 5040 u8 reserved_at_40[0x18]; 5041 u8 counter_set_id[0x8]; 5042 u8 reserved_at_60[0x20]; 5043 }; 5044 5045 struct mlx5_ifc_alloc_q_counter_in_bits { 5046 u8 opcode[0x10]; 5047 u8 uid[0x10]; 5048 u8 reserved_at_20[0x10]; 5049 u8 op_mod[0x10]; 5050 u8 reserved_at_40[0x40]; 5051 }; 5052 5053 struct mlx5_ifc_query_q_counter_out_bits { 5054 u8 status[0x8]; 5055 u8 reserved_at_8[0x18]; 5056 u8 syndrome[0x20]; 5057 u8 reserved_at_40[0x40]; 5058 u8 rx_write_requests[0x20]; 5059 u8 reserved_at_a0[0x20]; 5060 u8 rx_read_requests[0x20]; 5061 u8 reserved_at_e0[0x20]; 5062 u8 rx_atomic_requests[0x20]; 5063 u8 reserved_at_120[0x20]; 5064 u8 rx_dct_connect[0x20]; 5065 u8 reserved_at_160[0x20]; 5066 u8 out_of_buffer[0x20]; 5067 u8 reserved_at_1a0[0x20]; 5068 u8 out_of_sequence[0x20]; 5069 u8 reserved_at_1e0[0x20]; 5070 u8 duplicate_request[0x20]; 5071 u8 reserved_at_220[0x20]; 5072 u8 rnr_nak_retry_err[0x20]; 5073 u8 reserved_at_260[0x20]; 5074 u8 packet_seq_err[0x20]; 5075 u8 reserved_at_2a0[0x20]; 5076 u8 implied_nak_seq_err[0x20]; 5077 u8 reserved_at_2e0[0x20]; 5078 u8 local_ack_timeout_err[0x20]; 5079 u8 reserved_at_320[0xa0]; 5080 u8 resp_local_length_error[0x20]; 5081 u8 req_local_length_error[0x20]; 5082 u8 resp_local_qp_error[0x20]; 5083 u8 local_operation_error[0x20]; 5084 u8 resp_local_protection[0x20]; 5085 u8 req_local_protection[0x20]; 5086 u8 resp_cqe_error[0x20]; 5087 u8 req_cqe_error[0x20]; 5088 u8 req_mw_binding[0x20]; 5089 u8 req_bad_response[0x20]; 5090 u8 req_remote_invalid_request[0x20]; 5091 u8 resp_remote_invalid_request[0x20]; 5092 u8 req_remote_access_errors[0x20]; 5093 u8 resp_remote_access_errors[0x20]; 5094 u8 req_remote_operation_errors[0x20]; 5095 u8 req_transport_retries_exceeded[0x20]; 5096 u8 cq_overflow[0x20]; 5097 u8 resp_cqe_flush_error[0x20]; 5098 u8 req_cqe_flush_error[0x20]; 5099 u8 reserved_at_620[0x1e0]; 5100 }; 5101 5102 struct mlx5_ifc_query_q_counter_in_bits { 5103 u8 opcode[0x10]; 5104 u8 uid[0x10]; 5105 u8 reserved_at_20[0x10]; 5106 u8 op_mod[0x10]; 5107 u8 reserved_at_40[0x80]; 5108 u8 clear[0x1]; 5109 u8 reserved_at_c1[0x1f]; 5110 u8 reserved_at_e0[0x18]; 5111 u8 counter_set_id[0x8]; 5112 }; 5113 5114 enum { 5115 FS_FT_NIC_RX = 0x0, 5116 FS_FT_NIC_TX = 0x1, 5117 FS_FT_FDB = 0x4, 5118 FS_FT_FDB_RX = 0xa, 5119 FS_FT_FDB_TX = 0xb, 5120 }; 5121 5122 struct mlx5_ifc_flow_table_context_bits { 5123 u8 reformat_en[0x1]; 5124 u8 decap_en[0x1]; 5125 u8 sw_owner[0x1]; 5126 u8 termination_table[0x1]; 5127 u8 table_miss_action[0x4]; 5128 u8 level[0x8]; 5129 u8 rtc_valid[0x1]; 5130 u8 reserved_at_11[0x7]; 5131 u8 log_size[0x8]; 5132 5133 u8 reserved_at_20[0x8]; 5134 u8 table_miss_id[0x18]; 5135 5136 u8 reserved_at_40[0x8]; 5137 u8 lag_master_next_table_id[0x18]; 5138 5139 u8 reserved_at_60[0x60]; 5140 5141 union { 5142 struct { 5143 u8 rtc_id_0[0x20]; 5144 u8 rtc_id_1[0x20]; 5145 u8 reserved_at_100[0x40]; 5146 }; 5147 struct { 5148 u8 sw_owner_icm_root_1[0x40]; 5149 u8 sw_owner_icm_root_0[0x40]; 5150 }; 5151 }; 5152 }; 5153 5154 struct mlx5_ifc_create_flow_table_in_bits { 5155 u8 opcode[0x10]; 5156 u8 uid[0x10]; 5157 5158 u8 reserved_at_20[0x10]; 5159 u8 op_mod[0x10]; 5160 5161 u8 other_vport[0x1]; 5162 u8 reserved_at_41[0xf]; 5163 u8 vport_number[0x10]; 5164 5165 u8 reserved_at_60[0x20]; 5166 5167 u8 table_type[0x8]; 5168 u8 reserved_at_88[0x18]; 5169 5170 u8 reserved_at_a0[0x20]; 5171 5172 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5173 }; 5174 5175 struct mlx5_ifc_create_flow_table_out_bits { 5176 u8 status[0x8]; 5177 u8 icm_address_63_40[0x18]; 5178 u8 syndrome[0x20]; 5179 u8 icm_address_39_32[0x8]; 5180 u8 table_id[0x18]; 5181 u8 icm_address_31_0[0x20]; 5182 }; 5183 5184 struct mlx5_ifc_query_flow_table_in_bits { 5185 u8 opcode[0x10]; 5186 u8 uid[0x10]; 5187 5188 u8 vhca_tunnel_id[0x10]; 5189 u8 op_mod[0x10]; 5190 5191 u8 other_vport[0x1]; 5192 u8 reserved_at_41[0xf]; 5193 u8 vport_number[0x10]; 5194 5195 u8 reserved_at_60[0x20]; 5196 5197 u8 table_type[0x8]; 5198 u8 reserved_at_88[0x18]; 5199 5200 u8 reserved_at_a0[0x8]; 5201 u8 table_id[0x18]; 5202 5203 u8 reserved_at_c0[0x140]; 5204 }; 5205 5206 struct mlx5_ifc_query_flow_table_out_bits { 5207 u8 status[0x8]; 5208 u8 reserved_at_8[0x18]; 5209 5210 u8 syndrome[0x20]; 5211 5212 u8 reserved_at_40[0x80]; 5213 5214 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5215 }; 5216 5217 enum mlx5_flow_destination_type { 5218 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 5219 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 5220 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 5221 }; 5222 5223 enum mlx5_flow_context_action { 5224 MLX5_FLOW_CONTEXT_ACTION_DROP = 1 << 1, 5225 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 1 << 2, 5226 MLX5_FLOW_CONTEXT_ACTION_REFORMAT = 1 << 4, 5227 MLX5_FLOW_CONTEXT_ACTION_DECRYPT = 1 << 12, 5228 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT = 1 << 13, 5229 }; 5230 5231 enum mlx5_flow_context_flow_source { 5232 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 5233 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 5234 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 5235 }; 5236 5237 struct mlx5_ifc_set_fte_out_bits { 5238 u8 status[0x8]; 5239 u8 reserved_at_8[0x18]; 5240 u8 syndrome[0x20]; 5241 u8 reserved_at_40[0x40]; 5242 }; 5243 5244 struct mlx5_ifc_dest_format_bits { 5245 u8 destination_type[0x8]; 5246 u8 destination_id[0x18]; 5247 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 5248 u8 packet_reformat[0x1]; 5249 u8 reserved_at_22[0xe]; 5250 u8 destination_eswitch_owner_vhca_id[0x10]; 5251 }; 5252 5253 struct mlx5_ifc_flow_counter_list_bits { 5254 u8 flow_counter_id[0x20]; 5255 u8 reserved_at_20[0x20]; 5256 }; 5257 5258 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 5259 struct mlx5_ifc_dest_format_bits dest_format; 5260 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 5261 u8 reserved_at_0[0x40]; 5262 }; 5263 5264 struct mlx5_ifc_extended_dest_format_bits { 5265 struct mlx5_ifc_dest_format_bits destination_entry; 5266 5267 u8 packet_reformat_id[0x20]; 5268 5269 u8 reserved_at_60[0x20]; 5270 }; 5271 5272 #define MLX5_IFC_MULTI_PATH_FT_MAX_LEVEL 64 5273 5274 #ifdef PEDANTIC 5275 #pragma GCC diagnostic ignored "-Wpedantic" 5276 #endif 5277 struct mlx5_ifc_flow_context_bits { 5278 u8 reserved_at_00[0x20]; 5279 u8 group_id[0x20]; 5280 u8 reserved_at_40[0x8]; 5281 u8 flow_tag[0x18]; 5282 u8 reserved_at_60[0x10]; 5283 u8 action[0x10]; 5284 u8 extended_destination[0x1]; 5285 u8 reserved_at_81[0x1]; 5286 u8 flow_source[0x2]; 5287 u8 encrypt_decrypt_type[0x4]; 5288 u8 destination_list_size[0x18]; 5289 u8 reserved_at_a0[0x8]; 5290 u8 flow_counter_list_size[0x18]; 5291 u8 packet_reformat_id[0x20]; 5292 u8 reserved_at_e0[0x40]; 5293 u8 encrypt_decrypt_obj_id[0x20]; 5294 u8 reserved_at_140[0x16c0]; 5295 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[]; 5296 }; 5297 5298 struct mlx5_ifc_set_fte_in_bits { 5299 u8 opcode[0x10]; 5300 u8 reserved_at_10[0x10]; 5301 u8 reserved_at_20[0x10]; 5302 u8 op_mod[0x10]; 5303 u8 other_vport[0x1]; 5304 u8 reserved_at_41[0xf]; 5305 u8 vport_number[0x10]; 5306 u8 reserved_at_60[0x20]; 5307 u8 table_type[0x8]; 5308 u8 reserved_at_88[0x18]; 5309 u8 reserved_at_a0[0x8]; 5310 u8 table_id[0x18]; 5311 u8 ignore_flow_level[0x1]; 5312 u8 reserved_at_c1[0x17]; 5313 u8 modify_enable_mask[0x8]; 5314 u8 reserved_at_e0[0x20]; 5315 u8 flow_index[0x20]; 5316 u8 reserved_at_120[0xe0]; 5317 struct mlx5_ifc_flow_context_bits flow_context; 5318 }; 5319 5320 struct mlx5_ifc_create_flow_group_in_bits { 5321 u8 opcode[0x10]; 5322 u8 reserved_at_10[0x10]; 5323 u8 reserved_at_20[0x20]; 5324 u8 other_vport[0x1]; 5325 u8 reserved_at_41[0xf]; 5326 u8 vport_number[0x10]; 5327 u8 reserved_at_60[0x20]; 5328 u8 table_type[0x8]; 5329 u8 reserved_at_88[0x18]; 5330 u8 reserved_at_a0[0x8]; 5331 u8 table_id[0x18]; 5332 u8 reserved_at_c0[0x1f40]; 5333 }; 5334 5335 struct mlx5_ifc_create_flow_group_out_bits { 5336 u8 status[0x8]; 5337 u8 reserved_at_8[0x18]; 5338 u8 syndrome[0x20]; 5339 u8 reserved_at_40[0x8]; 5340 u8 group_id[0x18]; 5341 u8 reserved_at_60[0x20]; 5342 }; 5343 5344 enum { 5345 MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION = 1 << 0, 5346 MLX5_IFC_MODIFY_FLOW_TABLE_RTC_ID = 1 << 1, 5347 }; 5348 5349 enum { 5350 MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_DEFAULT = 0, 5351 MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_GOTO_TBL = 1, 5352 }; 5353 5354 struct mlx5_ifc_modify_flow_table_in_bits { 5355 u8 opcode[0x10]; 5356 u8 uid[0x10]; 5357 5358 u8 reserved_at_20[0x10]; 5359 u8 op_mod[0x10]; 5360 5361 u8 reserved_at_40[0x10]; 5362 u8 vport_number[0x10]; 5363 5364 u8 reserved_at_60[0x10]; 5365 u8 modify_field_select[0x10]; 5366 5367 u8 table_type[0x8]; 5368 u8 reserved_at_88[0x18]; 5369 5370 u8 reserved_at_a0[0x8]; 5371 u8 table_id[0x18]; 5372 5373 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5374 }; 5375 5376 struct mlx5_ifc_modify_flow_table_out_bits { 5377 u8 status[0x8]; 5378 u8 reserved_at_8[0x18]; 5379 5380 u8 syndrome[0x20]; 5381 5382 u8 reserved_at_40[0x60]; 5383 }; 5384 5385 struct mlx5_ifc_packet_reformat_context_in_bits { 5386 u8 reformat_type[0x8]; 5387 u8 reserved_at_8[0x4]; 5388 u8 reformat_param_0[0x4]; 5389 u8 reserved_at_16[0x6]; 5390 u8 reformat_data_size[0xa]; 5391 5392 u8 reformat_param_1[0x8]; 5393 u8 reserved_at_40[0x8]; 5394 u8 reformat_data[6][0x8]; 5395 5396 u8 more_reformat_data[][0x8]; 5397 }; 5398 5399 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5400 u8 opcode[0x10]; 5401 u8 uid[0x10]; 5402 5403 u8 reserved_at_20[0x10]; 5404 u8 op_mod[0x10]; 5405 5406 u8 reserved_at_40[0xa0]; 5407 5408 u8 packet_reformat_context[]; 5409 }; 5410 5411 struct mlx5_ifc_alloc_packet_reformat_out_bits { 5412 u8 status[0x8]; 5413 u8 reserved_at_8[0x18]; 5414 5415 u8 syndrome[0x20]; 5416 5417 u8 packet_reformat_id[0x20]; 5418 5419 u8 reserved_at_60[0x20]; 5420 }; 5421 5422 /* CQE format mask. */ 5423 #define MLX5E_CQE_FORMAT_MASK 0xc 5424 5425 /* MPW opcode. */ 5426 #define MLX5_OPC_MOD_MPW 0x01 5427 5428 /* Compressed Rx CQE structure. */ 5429 struct mlx5_mini_cqe8 { 5430 union { 5431 uint32_t rx_hash_result; 5432 struct { 5433 union { 5434 uint16_t checksum; 5435 uint16_t flow_tag_high; 5436 struct { 5437 uint8_t reserved; 5438 uint8_t hdr_type; 5439 }; 5440 }; 5441 uint16_t stride_idx; 5442 }; 5443 struct { 5444 uint16_t wqe_counter; 5445 uint8_t validity_iteration_count; 5446 uint8_t s_wqe_opcode; 5447 } s_wqe_info; 5448 }; 5449 union { 5450 uint32_t byte_cnt_flow; 5451 uint32_t byte_cnt; 5452 }; 5453 }; 5454 5455 /* Mini CQE responder format. */ 5456 enum { 5457 MLX5_CQE_RESP_FORMAT_HASH = 0x0, 5458 MLX5_CQE_RESP_FORMAT_CSUM = 0x1, 5459 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2, 5460 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3, 5461 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4, 5462 }; 5463 5464 /* srTCM PRM flow meter parameters. */ 5465 enum { 5466 MLX5_FLOW_COLOR_RED = 0, 5467 MLX5_FLOW_COLOR_YELLOW, 5468 MLX5_FLOW_COLOR_GREEN, 5469 MLX5_FLOW_COLOR_UNDEFINED, 5470 }; 5471 5472 /* Maximum value of srTCM & trTCM metering parameters. */ 5473 #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F)) 5474 #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF) 5475 5476 /* The bits meter color use. */ 5477 #define MLX5_MTR_COLOR_BITS 8 5478 5479 /* The bit size of one register. */ 5480 #define MLX5_REG_BITS 32 5481 5482 /* Idle bits for non-color usage in color register. */ 5483 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS) 5484 5485 /* Length mode of dynamic flex parser graph node. */ 5486 enum mlx5_parse_graph_node_len_mode { 5487 MLX5_GRAPH_NODE_LEN_FIXED = 0x0, 5488 MLX5_GRAPH_NODE_LEN_FIELD = 0x1, 5489 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2, 5490 }; 5491 5492 /* Offset mode of the samples of flex parser. */ 5493 enum mlx5_parse_graph_flow_match_sample_offset_mode { 5494 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0, 5495 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1, 5496 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, 5497 }; 5498 5499 enum mlx5_parse_graph_flow_match_sample_tunnel_mode { 5500 MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0, 5501 MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1, 5502 MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2 5503 }; 5504 5505 /* Node index for an input / output arc of the flex parser graph. */ 5506 enum mlx5_parse_graph_arc_node_index { 5507 MLX5_GRAPH_ARC_NODE_NULL = 0x0, 5508 MLX5_GRAPH_ARC_NODE_HEAD = 0x1, 5509 MLX5_GRAPH_ARC_NODE_MAC = 0x2, 5510 MLX5_GRAPH_ARC_NODE_IP = 0x3, 5511 MLX5_GRAPH_ARC_NODE_GRE = 0x4, 5512 MLX5_GRAPH_ARC_NODE_UDP = 0x5, 5513 MLX5_GRAPH_ARC_NODE_MPLS = 0x6, 5514 MLX5_GRAPH_ARC_NODE_TCP = 0x7, 5515 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, 5516 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, 5517 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, 5518 MLX5_GRAPH_ARC_NODE_IPV4 = 0xb, 5519 MLX5_GRAPH_ARC_NODE_IPV6 = 0xc, 5520 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, 5521 }; 5522 5523 enum mlx5_packet_reformat_context_reformat_type { 5524 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5525 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5526 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 5527 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6, 5528 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 5529 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 5530 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9, 5531 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xA, 5532 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xB, 5533 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xC, 5534 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_ADD_NISP_TNL = 0xD, 5535 MLX5_PACKET_REFORMAT_CONTEXT_REFORMAT_TYPE_REMOVE_NISP_TNL = 0xE, 5536 }; 5537 5538 #define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8 5539 #define MLX5_PARSE_GRAPH_IN_ARC_MAX 8 5540 #define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8 5541 5542 /** 5543 * Convert a user mark to flow mark. 5544 * 5545 * @param val 5546 * Mark value to convert. 5547 * 5548 * @return 5549 * Converted mark value. 5550 */ 5551 static inline uint32_t 5552 mlx5_flow_mark_set(uint32_t val) 5553 { 5554 uint32_t ret; 5555 5556 /* 5557 * Add one to the user value to differentiate un-marked flows from 5558 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it 5559 * remains untouched. 5560 */ 5561 if (val != MLX5_FLOW_MARK_DEFAULT) 5562 ++val; 5563 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 5564 /* 5565 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit 5566 * word, byte-swapped by the kernel on little-endian systems. In this 5567 * case, left-shifting the resulting big-endian value ensures the 5568 * least significant 24 bits are retained when converting it back. 5569 */ 5570 ret = rte_cpu_to_be_32(val) >> 8; 5571 #else 5572 ret = val; 5573 #endif 5574 return ret; 5575 } 5576 5577 /** 5578 * Convert a mark to user mark. 5579 * 5580 * @param val 5581 * Mark value to convert. 5582 * 5583 * @return 5584 * Converted mark value. 5585 */ 5586 static inline uint32_t 5587 mlx5_flow_mark_get(uint32_t val) 5588 { 5589 /* 5590 * Subtract one from the retrieved value. It was added by 5591 * mlx5_flow_mark_set() to distinguish unmarked flows. 5592 */ 5593 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 5594 return (val >> 8) - 1; 5595 #else 5596 return val - 1; 5597 #endif 5598 } 5599 5600 /** 5601 * Convert a timestamp format to configure settings in the queue context. 5602 * 5603 * @param val 5604 * timestamp format supported by the queue. 5605 * 5606 * @return 5607 * Converted timestamp format settings. 5608 */ 5609 static inline uint32_t 5610 mlx5_ts_format_conv(uint32_t ts_format) 5611 { 5612 return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ? 5613 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : 5614 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; 5615 } 5616 5617 #endif /* RTE_PMD_MLX5_PRM_H_ */ 5618