1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_PRM_H_ 7 #define RTE_PMD_MLX5_PRM_H_ 8 9 #include <unistd.h> 10 11 #include <rte_vect.h> 12 #include <rte_byteorder.h> 13 14 #include <mlx5_glue.h> 15 #include "mlx5_autoconf.h" 16 17 /* RSS hash key size. */ 18 #define MLX5_RSS_HASH_KEY_LEN 40 19 20 /* Get CQE owner bit. */ 21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK) 22 23 /* Get CQE format. */ 24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2) 25 26 /* Get CQE opcode. */ 27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4) 28 29 /* Get CQE solicited event. */ 30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1) 31 32 /* Invalidate a CQE. */ 33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4) 34 35 /* Hardware index widths. */ 36 #define MLX5_CQ_INDEX_WIDTH 24 37 #define MLX5_WQ_INDEX_WIDTH 16 38 39 /* WQE Segment sizes in bytes. */ 40 #define MLX5_WSEG_SIZE 16u 41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg) 42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg) 43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg) 44 45 /* WQE/WQEBB size in bytes. */ 46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe) 47 48 /* 49 * Max size of a WQE session. 50 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments, 51 * the WQE size field in Control Segment is 6 bits wide. 52 */ 53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE) 54 55 /* 56 * Default minimum number of Tx queues for inlining packets. 57 * If there are less queues as specified we assume we have 58 * no enough CPU resources (cycles) to perform inlining, 59 * the PCIe throughput is not supposed as bottleneck and 60 * inlining is disabled. 61 */ 62 #define MLX5_INLINE_MAX_TXQS 8u 63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u 64 65 /* 66 * Default packet length threshold to be inlined with 67 * enhanced MPW. If packet length exceeds the threshold 68 * the data are not inlined. Should be aligned in WQEBB 69 * boundary with accounting the title Control and Ethernet 70 * segments. 71 */ 72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \ 73 MLX5_DSEG_MIN_INLINE_SIZE) 74 /* 75 * Maximal inline data length sent with enhanced MPW. 76 * Is based on maximal WQE size. 77 */ 78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 79 MLX5_WQE_CSEG_SIZE - \ 80 MLX5_WQE_ESEG_SIZE - \ 81 MLX5_WQE_DSEG_SIZE + \ 82 MLX5_DSEG_MIN_INLINE_SIZE) 83 /* 84 * Minimal amount of packets to be sent with EMPW. 85 * This limits the minimal required size of sent EMPW. 86 * If there are no enough resources to built minimal 87 * EMPW the sending loop exits. 88 */ 89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u) 90 /* 91 * Maximal amount of packets to be sent with EMPW. 92 * This value is not recommended to exceed MLX5_TX_COMP_THRESH, 93 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs 94 * without CQE generation request, being multiplied by 95 * MLX5_TX_COMP_MAX_CQE it may cause significant latency 96 * in tx burst routine at the moment of freeing multiple mbufs. 97 */ 98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH 99 #define MLX5_MPW_MAX_PACKETS 6 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6 101 102 /* 103 * Default packet length threshold to be inlined with 104 * ordinary SEND. Inlining saves the MR key search 105 * and extra PCIe data fetch transaction, but eats the 106 * CPU cycles. 107 */ 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \ 109 MLX5_ESEG_MIN_INLINE_SIZE - \ 110 MLX5_WQE_CSEG_SIZE - \ 111 MLX5_WQE_ESEG_SIZE - \ 112 MLX5_WQE_DSEG_SIZE) 113 /* 114 * Maximal inline data length sent with ordinary SEND. 115 * Is based on maximal WQE size. 116 */ 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 118 MLX5_WQE_CSEG_SIZE - \ 119 MLX5_WQE_ESEG_SIZE - \ 120 MLX5_WQE_DSEG_SIZE + \ 121 MLX5_ESEG_MIN_INLINE_SIZE) 122 123 /* Missed in mlx5dv.h, should define here. */ 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u 126 #endif 127 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN 129 #define MLX5_OPCODE_SEND_EN 0x17u 130 #endif 131 132 #ifndef HAVE_MLX5_OPCODE_WAIT 133 #define MLX5_OPCODE_WAIT 0x0fu 134 #endif 135 136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO 137 #define MLX5_OPCODE_ACCESS_ASO 0x2du 138 #endif 139 140 /* CQE value to inform that VLAN is stripped. */ 141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0) 142 143 /* IPv4 options. */ 144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1) 145 146 /* IPv6 packet. */ 147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2) 148 149 /* IPv4 packet. */ 150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3) 151 152 /* TCP packet. */ 153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4) 154 155 /* UDP packet. */ 156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5) 157 158 /* IP is fragmented. */ 159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7) 160 161 /* L2 header is valid. */ 162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8) 163 164 /* L3 header is valid. */ 165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9) 166 167 /* L4 header is valid. */ 168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10) 169 170 /* Outer packet, 0 IPv4, 1 IPv6. */ 171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1) 172 173 /* Tunnel packet bit in the CQE. */ 174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0) 175 176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */ 177 #define MLX5_CQE_LRO_PUSH_MASK 0x40 178 179 /* Mask for L4 type in the CQE hdr_type_etc field. */ 180 #define MLX5_CQE_L4_TYPE_MASK 0x70 181 182 /* The bit index of L4 type in CQE hdr_type_etc field. */ 183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4 184 185 /* L4 type to indicate TCP packet without acknowledgment. */ 186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3 187 188 /* L4 type to indicate TCP packet with acknowledgment. */ 189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4 190 191 /* Inner L3 checksum offload (Tunneled packets only). */ 192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4) 193 194 /* Inner L4 checksum offload (Tunneled packets only). */ 195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5) 196 197 /* Outer L4 type is TCP. */ 198 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5) 199 200 /* Outer L4 type is UDP. */ 201 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5) 202 203 /* Outer L3 type is IPV4. */ 204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4) 205 206 /* Outer L3 type is IPV6. */ 207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4) 208 209 /* Inner L4 type is TCP. */ 210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1) 211 212 /* Inner L4 type is UDP. */ 213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1) 214 215 /* Inner L3 type is IPV4. */ 216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0) 217 218 /* Inner L3 type is IPV6. */ 219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0) 220 221 /* VLAN insertion flag. */ 222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31) 223 224 /* Data inline segment flag. */ 225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31) 226 227 /* Is flow mark valid. */ 228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00) 230 #else 231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff) 232 #endif 233 234 /* INVALID is used by packets matching no flow rules. */ 235 #define MLX5_FLOW_MARK_INVALID 0 236 237 /* Maximum allowed value to mark a packet. */ 238 #define MLX5_FLOW_MARK_MAX 0xfffff0 239 240 /* Default mark value used when none is provided. */ 241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff 242 243 /* Default mark mask for metadata legacy mode. */ 244 #define MLX5_FLOW_MARK_MASK 0xffffff 245 246 /* Byte length mask when mark is enable in miniCQE */ 247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00 248 249 /* Maximum number of DS in WQE. Limited by 6-bit field. */ 250 #define MLX5_DSEG_MAX 63 251 252 /* The completion mode offset in the WQE control segment line 2. */ 253 #define MLX5_COMP_MODE_OFFSET 2 254 255 /* Amount of data bytes in minimal inline data segment. */ 256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u 257 258 /* Amount of data bytes in minimal inline eth segment. */ 259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u 260 261 /* Amount of data bytes after eth data segment. */ 262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u 263 264 /* The maximum log value of segments per RQ WQE. */ 265 #define MLX5_MAX_LOG_RQ_SEGS 5u 266 267 /* The alignment needed for WQ buffer. */ 268 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size() 269 270 /* The alignment needed for CQ buffer. */ 271 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size() 272 273 /* Completion mode. */ 274 enum mlx5_completion_mode { 275 MLX5_COMP_ONLY_ERR = 0x0, 276 MLX5_COMP_ONLY_FIRST_ERR = 0x1, 277 MLX5_COMP_ALWAYS = 0x2, 278 MLX5_COMP_CQE_AND_EQE = 0x3, 279 }; 280 281 /* MPW mode. */ 282 enum mlx5_mpw_mode { 283 MLX5_MPW_DISABLED, 284 MLX5_MPW, 285 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */ 286 }; 287 288 /* WQE Control segment. */ 289 struct mlx5_wqe_cseg { 290 uint32_t opcode; 291 uint32_t sq_ds; 292 uint32_t flags; 293 uint32_t misc; 294 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE); 295 296 /* 297 * WQE CSEG opcode field size is 32 bits, divided: 298 * Bits 31:24 OPC_MOD 299 * Bits 23:8 wqe_index 300 * Bits 7:0 OPCODE 301 */ 302 #define WQE_CSEG_OPC_MOD_OFFSET 24 303 #define WQE_CSEG_WQE_INDEX_OFFSET 8 304 305 /* Header of data segment. Minimal size Data Segment */ 306 struct mlx5_wqe_dseg { 307 uint32_t bcount; 308 union { 309 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE]; 310 struct { 311 uint32_t lkey; 312 uint64_t pbuf; 313 } __rte_packed; 314 }; 315 } __rte_packed; 316 317 /* Subset of struct WQE Ethernet Segment. */ 318 struct mlx5_wqe_eseg { 319 union { 320 struct { 321 uint32_t swp_offs; 322 uint8_t cs_flags; 323 uint8_t swp_flags; 324 uint16_t mss; 325 uint32_t metadata; 326 uint16_t inline_hdr_sz; 327 union { 328 uint16_t inline_data; 329 uint16_t vlan_tag; 330 }; 331 } __rte_packed; 332 struct { 333 uint32_t offsets; 334 uint32_t flags; 335 uint32_t flow_metadata; 336 uint32_t inline_hdr; 337 } __rte_packed; 338 }; 339 } __rte_packed; 340 341 struct mlx5_wqe_qseg { 342 uint32_t reserved0; 343 uint32_t reserved1; 344 uint32_t max_index; 345 uint32_t qpn_cqn; 346 } __rte_packed; 347 348 /* The title WQEBB, header of WQE. */ 349 struct mlx5_wqe { 350 union { 351 struct mlx5_wqe_cseg cseg; 352 uint32_t ctrl[4]; 353 }; 354 struct mlx5_wqe_eseg eseg; 355 union { 356 struct mlx5_wqe_dseg dseg[2]; 357 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE]; 358 }; 359 } __rte_packed; 360 361 /* WQE for Multi-Packet RQ. */ 362 struct mlx5_wqe_mprq { 363 struct mlx5_wqe_srq_next_seg next_seg; 364 struct mlx5_wqe_data_seg dseg; 365 }; 366 367 #define MLX5_MPRQ_LEN_MASK 0x000ffff 368 #define MLX5_MPRQ_LEN_SHIFT 0 369 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000 370 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16 371 #define MLX5_MPRQ_FILLER_MASK 0x80000000 372 #define MLX5_MPRQ_FILLER_SHIFT 31 373 374 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2 375 376 /* CQ element structure - should be equal to the cache line size */ 377 struct mlx5_cqe { 378 #if (RTE_CACHE_LINE_SIZE == 128) 379 uint8_t padding[64]; 380 #endif 381 uint8_t pkt_info; 382 uint8_t rsvd0; 383 uint16_t wqe_id; 384 uint8_t lro_tcppsh_abort_dupack; 385 uint8_t lro_min_ttl; 386 uint16_t lro_tcp_win; 387 uint32_t lro_ack_seq_num; 388 uint32_t rx_hash_res; 389 uint8_t rx_hash_type; 390 uint8_t rsvd1[3]; 391 uint16_t csum; 392 uint8_t rsvd2[6]; 393 uint16_t hdr_type_etc; 394 uint16_t vlan_info; 395 uint8_t lro_num_seg; 396 uint8_t rsvd3[3]; 397 uint32_t flow_table_metadata; 398 uint8_t rsvd4[4]; 399 uint32_t byte_cnt; 400 uint64_t timestamp; 401 uint32_t sop_drop_qpn; 402 uint16_t wqe_counter; 403 uint8_t rsvd5; 404 uint8_t op_own; 405 }; 406 407 struct mlx5_cqe_ts { 408 uint64_t timestamp; 409 uint32_t sop_drop_qpn; 410 uint16_t wqe_counter; 411 uint8_t rsvd5; 412 uint8_t op_own; 413 }; 414 415 struct mlx5_wqe_rseg { 416 uint64_t raddr; 417 uint32_t rkey; 418 uint32_t reserved; 419 } __rte_packed; 420 421 #define MLX5_UMRC_IF_OFFSET 31u 422 #define MLX5_UMRC_KO_OFFSET 16u 423 #define MLX5_UMRC_TO_BS_OFFSET 0u 424 425 struct mlx5_wqe_umr_cseg { 426 uint32_t if_cf_toe_cq_res; 427 uint32_t ko_to_bs; 428 uint64_t mkey_mask; 429 uint32_t rsvd1[8]; 430 } __rte_packed; 431 432 struct mlx5_wqe_mkey_cseg { 433 uint32_t fr_res_af_sf; 434 uint32_t qpn_mkey; 435 uint32_t reserved2; 436 uint32_t flags_pd; 437 uint64_t start_addr; 438 uint64_t len; 439 uint32_t bsf_octword_size; 440 uint32_t reserved3[4]; 441 uint32_t translations_octword_size; 442 uint32_t res4_lps; 443 uint32_t reserved; 444 } __rte_packed; 445 446 enum { 447 MLX5_BSF_SIZE_16B = 0x0, 448 MLX5_BSF_SIZE_32B = 0x1, 449 MLX5_BSF_SIZE_64B = 0x2, 450 MLX5_BSF_SIZE_128B = 0x3, 451 }; 452 453 enum { 454 MLX5_BSF_P_TYPE_SIGNATURE = 0x0, 455 MLX5_BSF_P_TYPE_CRYPTO = 0x1, 456 }; 457 458 enum { 459 MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, 460 MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, 461 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, 462 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, 463 }; 464 465 enum { 466 MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, 467 }; 468 469 enum { 470 MLX5_BLOCK_SIZE_512B = 0x1, 471 MLX5_BLOCK_SIZE_520B = 0x2, 472 MLX5_BLOCK_SIZE_4096B = 0x3, 473 MLX5_BLOCK_SIZE_4160B = 0x4, 474 MLX5_BLOCK_SIZE_1MB = 0x5, 475 MLX5_BLOCK_SIZE_4048B = 0x6, 476 }; 477 478 #define MLX5_BSF_SIZE_OFFSET 30 479 #define MLX5_BSF_P_TYPE_OFFSET 24 480 #define MLX5_ENCRYPTION_ORDER_OFFSET 16 481 #define MLX5_BLOCK_SIZE_OFFSET 24 482 483 struct mlx5_wqe_umr_bsf_seg { 484 /* 485 * bs_bpt_eo_es contains: 486 * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET 487 * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET 488 * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET 489 * es encryption_standard 4 bits at offset 0 490 */ 491 uint32_t bs_bpt_eo_es; 492 uint32_t raw_data_size; 493 /* 494 * bsp_res contains: 495 * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET 496 * res reserved 24 bits 497 */ 498 uint32_t bsp_res; 499 uint32_t reserved0; 500 uint8_t xts_initial_tweak[16]; 501 /* 502 * res_dp contains: 503 * res reserved 8 bits 504 * dp dek_pointer 24 bits at offset 0 505 */ 506 uint32_t res_dp; 507 uint32_t reserved1; 508 uint64_t keytag; 509 uint32_t reserved2[4]; 510 } __rte_packed; 511 512 #ifdef PEDANTIC 513 #pragma GCC diagnostic ignored "-Wpedantic" 514 #endif 515 516 struct mlx5_umr_wqe { 517 struct mlx5_wqe_cseg ctr; 518 struct mlx5_wqe_umr_cseg ucseg; 519 struct mlx5_wqe_mkey_cseg mkc; 520 union { 521 struct mlx5_wqe_dseg kseg[0]; 522 struct mlx5_wqe_umr_bsf_seg bsf[0]; 523 }; 524 } __rte_packed; 525 526 struct mlx5_rdma_write_wqe { 527 struct mlx5_wqe_cseg ctr; 528 struct mlx5_wqe_rseg rseg; 529 struct mlx5_wqe_dseg dseg[0]; 530 } __rte_packed; 531 532 #ifdef PEDANTIC 533 #pragma GCC diagnostic error "-Wpedantic" 534 #endif 535 536 /* GGA */ 537 /* MMO metadata segment */ 538 539 #define MLX5_OPCODE_MMO 0x2fu 540 #define MLX5_OPC_MOD_MMO_REGEX 0x4u 541 #define MLX5_OPC_MOD_MMO_COMP 0x2u 542 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u 543 #define MLX5_OPC_MOD_MMO_DMA 0x1u 544 545 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u 546 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u 547 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u 548 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u 549 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) 550 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u 551 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u 552 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u 553 554 struct mlx5_wqe_metadata_seg { 555 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */ 556 uint32_t lkey; 557 uint64_t addr; 558 }; 559 560 struct mlx5_gga_wqe { 561 uint32_t opcode; 562 uint32_t sq_ds; 563 uint32_t flags; 564 uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */ 565 uint32_t gga_ctrl2; 566 uint32_t opaque_lkey; 567 uint64_t opaque_vaddr; 568 struct mlx5_wqe_dseg gather; 569 struct mlx5_wqe_dseg scatter; 570 } __rte_packed; 571 572 struct mlx5_gga_compress_opaque { 573 uint32_t syndrom; 574 uint32_t reserved0; 575 uint32_t scattered_length; 576 uint32_t gathered_length; 577 uint64_t scatter_crc; 578 uint64_t gather_crc; 579 uint32_t crc32; 580 uint32_t adler32; 581 uint8_t reserved1[216]; 582 } __rte_packed; 583 584 struct mlx5_ifc_regexp_mmo_control_bits { 585 uint8_t reserved_at_31[0x2]; 586 uint8_t le[0x1]; 587 uint8_t reserved_at_28[0x1]; 588 uint8_t subset_id_0[0xc]; 589 uint8_t reserved_at_16[0x4]; 590 uint8_t subset_id_1[0xc]; 591 uint8_t ctrl[0x4]; 592 uint8_t subset_id_2[0xc]; 593 uint8_t reserved_at_16_1[0x4]; 594 uint8_t subset_id_3[0xc]; 595 }; 596 597 struct mlx5_ifc_regexp_metadata_bits { 598 uint8_t rof_version[0x10]; 599 uint8_t latency_count[0x10]; 600 uint8_t instruction_count[0x10]; 601 uint8_t primary_thread_count[0x10]; 602 uint8_t match_count[0x8]; 603 uint8_t detected_match_count[0x8]; 604 uint8_t status[0x10]; 605 uint8_t job_id[0x20]; 606 uint8_t reserved[0x80]; 607 }; 608 609 struct mlx5_ifc_regexp_match_tuple_bits { 610 uint8_t length[0x10]; 611 uint8_t start_ptr[0x10]; 612 uint8_t rule_id[0x20]; 613 }; 614 615 /* Adding direct verbs to data-path. */ 616 617 /* CQ sequence number mask. */ 618 #define MLX5_CQ_SQN_MASK 0x3 619 620 /* CQ sequence number index. */ 621 #define MLX5_CQ_SQN_OFFSET 28 622 623 /* CQ doorbell index mask. */ 624 #define MLX5_CI_MASK 0xffffff 625 626 /* CQ doorbell offset. */ 627 #define MLX5_CQ_ARM_DB 1 628 629 /* CQ doorbell offset*/ 630 #define MLX5_CQ_DOORBELL 0x20 631 632 /* CQE format value. */ 633 #define MLX5_COMPRESSED 0x3 634 635 /* CQ doorbell cmd types. */ 636 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24) 637 #define MLX5_CQ_DBR_CMD_ALL (0 << 24) 638 639 /* Action type of header modification. */ 640 enum { 641 MLX5_MODIFICATION_TYPE_SET = 0x1, 642 MLX5_MODIFICATION_TYPE_ADD = 0x2, 643 MLX5_MODIFICATION_TYPE_COPY = 0x3, 644 }; 645 646 /* The field of packet to be modified. */ 647 enum mlx5_modification_field { 648 MLX5_MODI_OUT_NONE = -1, 649 MLX5_MODI_OUT_SMAC_47_16 = 1, 650 MLX5_MODI_OUT_SMAC_15_0, 651 MLX5_MODI_OUT_ETHERTYPE, 652 MLX5_MODI_OUT_DMAC_47_16, 653 MLX5_MODI_OUT_DMAC_15_0, 654 MLX5_MODI_OUT_IP_DSCP, 655 MLX5_MODI_OUT_TCP_FLAGS, 656 MLX5_MODI_OUT_TCP_SPORT, 657 MLX5_MODI_OUT_TCP_DPORT, 658 MLX5_MODI_OUT_IPV4_TTL, 659 MLX5_MODI_OUT_UDP_SPORT, 660 MLX5_MODI_OUT_UDP_DPORT, 661 MLX5_MODI_OUT_SIPV6_127_96, 662 MLX5_MODI_OUT_SIPV6_95_64, 663 MLX5_MODI_OUT_SIPV6_63_32, 664 MLX5_MODI_OUT_SIPV6_31_0, 665 MLX5_MODI_OUT_DIPV6_127_96, 666 MLX5_MODI_OUT_DIPV6_95_64, 667 MLX5_MODI_OUT_DIPV6_63_32, 668 MLX5_MODI_OUT_DIPV6_31_0, 669 MLX5_MODI_OUT_SIPV4, 670 MLX5_MODI_OUT_DIPV4, 671 MLX5_MODI_OUT_FIRST_VID, 672 MLX5_MODI_IN_SMAC_47_16 = 0x31, 673 MLX5_MODI_IN_SMAC_15_0, 674 MLX5_MODI_IN_ETHERTYPE, 675 MLX5_MODI_IN_DMAC_47_16, 676 MLX5_MODI_IN_DMAC_15_0, 677 MLX5_MODI_IN_IP_DSCP, 678 MLX5_MODI_IN_TCP_FLAGS, 679 MLX5_MODI_IN_TCP_SPORT, 680 MLX5_MODI_IN_TCP_DPORT, 681 MLX5_MODI_IN_IPV4_TTL, 682 MLX5_MODI_IN_UDP_SPORT, 683 MLX5_MODI_IN_UDP_DPORT, 684 MLX5_MODI_IN_SIPV6_127_96, 685 MLX5_MODI_IN_SIPV6_95_64, 686 MLX5_MODI_IN_SIPV6_63_32, 687 MLX5_MODI_IN_SIPV6_31_0, 688 MLX5_MODI_IN_DIPV6_127_96, 689 MLX5_MODI_IN_DIPV6_95_64, 690 MLX5_MODI_IN_DIPV6_63_32, 691 MLX5_MODI_IN_DIPV6_31_0, 692 MLX5_MODI_IN_SIPV4, 693 MLX5_MODI_IN_DIPV4, 694 MLX5_MODI_OUT_IPV6_HOPLIMIT, 695 MLX5_MODI_IN_IPV6_HOPLIMIT, 696 MLX5_MODI_META_DATA_REG_A, 697 MLX5_MODI_META_DATA_REG_B = 0x50, 698 MLX5_MODI_META_REG_C_0, 699 MLX5_MODI_META_REG_C_1, 700 MLX5_MODI_META_REG_C_2, 701 MLX5_MODI_META_REG_C_3, 702 MLX5_MODI_META_REG_C_4, 703 MLX5_MODI_META_REG_C_5, 704 MLX5_MODI_META_REG_C_6, 705 MLX5_MODI_META_REG_C_7, 706 MLX5_MODI_OUT_TCP_SEQ_NUM, 707 MLX5_MODI_IN_TCP_SEQ_NUM, 708 MLX5_MODI_OUT_TCP_ACK_NUM, 709 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C, 710 MLX5_MODI_GTP_TEID = 0x6E, 711 }; 712 713 /* Total number of metadata reg_c's. */ 714 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1) 715 716 enum modify_reg { 717 REG_NON = 0, 718 REG_A, 719 REG_B, 720 REG_C_0, 721 REG_C_1, 722 REG_C_2, 723 REG_C_3, 724 REG_C_4, 725 REG_C_5, 726 REG_C_6, 727 REG_C_7, 728 }; 729 730 /* Modification sub command. */ 731 struct mlx5_modification_cmd { 732 union { 733 uint32_t data0; 734 struct { 735 unsigned int length:5; 736 unsigned int rsvd0:3; 737 unsigned int offset:5; 738 unsigned int rsvd1:3; 739 unsigned int field:12; 740 unsigned int action_type:4; 741 }; 742 }; 743 union { 744 uint32_t data1; 745 uint8_t data[4]; 746 struct { 747 unsigned int rsvd2:8; 748 unsigned int dst_offset:5; 749 unsigned int rsvd3:3; 750 unsigned int dst_field:12; 751 unsigned int rsvd4:4; 752 }; 753 }; 754 }; 755 756 typedef uint64_t u64; 757 typedef uint32_t u32; 758 typedef uint16_t u16; 759 typedef uint8_t u8; 760 761 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 762 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 763 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \ 764 (&(__mlx5_nullp(typ)->fld))) 765 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \ 766 (__mlx5_bit_off(typ, fld) & 0x1f)) 767 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 768 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 769 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \ 770 __mlx5_dw_bit_off(typ, fld)) 771 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 772 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 773 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \ 774 (__mlx5_bit_off(typ, fld) & 0xf)) 775 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 776 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \ 777 __mlx5_16_bit_off(typ, fld)) 778 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 779 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 780 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 781 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 782 783 /* insert a value to a struct */ 784 #define MLX5_SET(typ, p, fld, v) \ 785 do { \ 786 u32 _v = v; \ 787 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \ 788 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \ 789 __mlx5_dw_off(typ, fld))) & \ 790 (~__mlx5_dw_mask(typ, fld))) | \ 791 (((_v) & __mlx5_mask(typ, fld)) << \ 792 __mlx5_dw_bit_off(typ, fld))); \ 793 } while (0) 794 795 #define MLX5_SET64(typ, p, fld, v) \ 796 do { \ 797 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \ 798 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \ 799 rte_cpu_to_be_64(v); \ 800 } while (0) 801 802 #define MLX5_SET16(typ, p, fld, v) \ 803 do { \ 804 u16 _v = v; \ 805 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \ 806 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 807 __mlx5_16_off(typ, fld))) & \ 808 (~__mlx5_16_mask(typ, fld))) | \ 809 (((_v) & __mlx5_mask16(typ, fld)) << \ 810 __mlx5_16_bit_off(typ, fld))); \ 811 } while (0) 812 813 #define MLX5_GET_VOLATILE(typ, p, fld) \ 814 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\ 815 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 816 __mlx5_mask(typ, fld)) 817 #define MLX5_GET(typ, p, fld) \ 818 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\ 819 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 820 __mlx5_mask(typ, fld)) 821 #define MLX5_GET16(typ, p, fld) \ 822 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 823 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 824 __mlx5_mask16(typ, fld)) 825 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \ 826 __mlx5_64_off(typ, fld))) 827 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 828 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 829 830 struct mlx5_ifc_fte_match_set_misc_bits { 831 u8 gre_c_present[0x1]; 832 u8 reserved_at_1[0x1]; 833 u8 gre_k_present[0x1]; 834 u8 gre_s_present[0x1]; 835 u8 source_vhci_port[0x4]; 836 u8 source_sqn[0x18]; 837 u8 reserved_at_20[0x10]; 838 u8 source_port[0x10]; 839 u8 outer_second_prio[0x3]; 840 u8 outer_second_cfi[0x1]; 841 u8 outer_second_vid[0xc]; 842 u8 inner_second_prio[0x3]; 843 u8 inner_second_cfi[0x1]; 844 u8 inner_second_vid[0xc]; 845 u8 outer_second_cvlan_tag[0x1]; 846 u8 inner_second_cvlan_tag[0x1]; 847 u8 outer_second_svlan_tag[0x1]; 848 u8 inner_second_svlan_tag[0x1]; 849 u8 reserved_at_64[0xc]; 850 u8 gre_protocol[0x10]; 851 u8 gre_key_h[0x18]; 852 u8 gre_key_l[0x8]; 853 u8 vxlan_vni[0x18]; 854 u8 reserved_at_b8[0x8]; 855 u8 geneve_vni[0x18]; 856 u8 reserved_at_e4[0x6]; 857 u8 geneve_tlv_option_0_exist[0x1]; 858 u8 geneve_oam[0x1]; 859 u8 reserved_at_e0[0xc]; 860 u8 outer_ipv6_flow_label[0x14]; 861 u8 reserved_at_100[0xc]; 862 u8 inner_ipv6_flow_label[0x14]; 863 u8 reserved_at_120[0xa]; 864 u8 geneve_opt_len[0x6]; 865 u8 geneve_protocol_type[0x10]; 866 u8 reserved_at_140[0xc0]; 867 }; 868 869 struct mlx5_ifc_ipv4_layout_bits { 870 u8 reserved_at_0[0x60]; 871 u8 ipv4[0x20]; 872 }; 873 874 struct mlx5_ifc_ipv6_layout_bits { 875 u8 ipv6[16][0x8]; 876 }; 877 878 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 879 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 880 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 881 u8 reserved_at_0[0x80]; 882 }; 883 884 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 885 u8 smac_47_16[0x20]; 886 u8 smac_15_0[0x10]; 887 u8 ethertype[0x10]; 888 u8 dmac_47_16[0x20]; 889 u8 dmac_15_0[0x10]; 890 u8 first_prio[0x3]; 891 u8 first_cfi[0x1]; 892 u8 first_vid[0xc]; 893 u8 ip_protocol[0x8]; 894 u8 ip_dscp[0x6]; 895 u8 ip_ecn[0x2]; 896 u8 cvlan_tag[0x1]; 897 u8 svlan_tag[0x1]; 898 u8 frag[0x1]; 899 u8 ip_version[0x4]; 900 u8 tcp_flags[0x9]; 901 u8 tcp_sport[0x10]; 902 u8 tcp_dport[0x10]; 903 u8 reserved_at_c0[0x10]; 904 u8 ipv4_ihl[0x4]; 905 u8 l3_ok[0x1]; 906 u8 l4_ok[0x1]; 907 u8 ipv4_checksum_ok[0x1]; 908 u8 l4_checksum_ok[0x1]; 909 u8 ip_ttl_hoplimit[0x8]; 910 u8 udp_sport[0x10]; 911 u8 udp_dport[0x10]; 912 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 913 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 914 }; 915 916 struct mlx5_ifc_fte_match_mpls_bits { 917 u8 mpls_label[0x14]; 918 u8 mpls_exp[0x3]; 919 u8 mpls_s_bos[0x1]; 920 u8 mpls_ttl[0x8]; 921 }; 922 923 struct mlx5_ifc_fte_match_set_misc2_bits { 924 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 925 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 926 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 927 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 928 u8 metadata_reg_c_7[0x20]; 929 u8 metadata_reg_c_6[0x20]; 930 u8 metadata_reg_c_5[0x20]; 931 u8 metadata_reg_c_4[0x20]; 932 u8 metadata_reg_c_3[0x20]; 933 u8 metadata_reg_c_2[0x20]; 934 u8 metadata_reg_c_1[0x20]; 935 u8 metadata_reg_c_0[0x20]; 936 u8 metadata_reg_a[0x20]; 937 u8 metadata_reg_b[0x20]; 938 u8 reserved_at_1c0[0x40]; 939 }; 940 941 struct mlx5_ifc_fte_match_set_misc3_bits { 942 u8 inner_tcp_seq_num[0x20]; 943 u8 outer_tcp_seq_num[0x20]; 944 u8 inner_tcp_ack_num[0x20]; 945 u8 outer_tcp_ack_num[0x20]; 946 u8 reserved_at_auto1[0x8]; 947 u8 outer_vxlan_gpe_vni[0x18]; 948 u8 outer_vxlan_gpe_next_protocol[0x8]; 949 u8 outer_vxlan_gpe_flags[0x8]; 950 u8 reserved_at_a8[0x10]; 951 u8 icmp_header_data[0x20]; 952 u8 icmpv6_header_data[0x20]; 953 u8 icmp_type[0x8]; 954 u8 icmp_code[0x8]; 955 u8 icmpv6_type[0x8]; 956 u8 icmpv6_code[0x8]; 957 u8 geneve_tlv_option_0_data[0x20]; 958 u8 gtpu_teid[0x20]; 959 u8 gtpu_msg_type[0x08]; 960 u8 gtpu_msg_flags[0x08]; 961 u8 reserved_at_170[0x10]; 962 u8 gtpu_dw_2[0x20]; 963 u8 gtpu_first_ext_dw_0[0x20]; 964 u8 gtpu_dw_0[0x20]; 965 u8 reserved_at_240[0x20]; 966 967 }; 968 969 struct mlx5_ifc_fte_match_set_misc4_bits { 970 u8 prog_sample_field_value_0[0x20]; 971 u8 prog_sample_field_id_0[0x20]; 972 u8 prog_sample_field_value_1[0x20]; 973 u8 prog_sample_field_id_1[0x20]; 974 u8 prog_sample_field_value_2[0x20]; 975 u8 prog_sample_field_id_2[0x20]; 976 u8 prog_sample_field_value_3[0x20]; 977 u8 prog_sample_field_id_3[0x20]; 978 u8 reserved_at_100[0x100]; 979 }; 980 981 struct mlx5_ifc_fte_match_set_misc5_bits { 982 u8 macsec_tag_0[0x20]; 983 u8 macsec_tag_1[0x20]; 984 u8 macsec_tag_2[0x20]; 985 u8 macsec_tag_3[0x20]; 986 u8 tunnel_header_0[0x20]; 987 u8 tunnel_header_1[0x20]; 988 u8 tunnel_header_2[0x20]; 989 u8 tunnel_header_3[0x20]; 990 u8 reserved[0x100]; 991 }; 992 993 /* Flow matcher. */ 994 struct mlx5_ifc_fte_match_param_bits { 995 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 996 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 997 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 998 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 999 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1000 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1001 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1002 /* 1003 * Add reserved bit to match the struct size with the size defined in PRM. 1004 * This extension is not required in Linux. 1005 */ 1006 #ifndef HAVE_INFINIBAND_VERBS_H 1007 u8 reserved_0[0x200]; 1008 #endif 1009 }; 1010 1011 struct mlx5_ifc_dest_format_struct_bits { 1012 u8 destination_type[0x8]; 1013 u8 destination_id[0x18]; 1014 u8 reserved_0[0x20]; 1015 }; 1016 1017 enum { 1018 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 1019 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT, 1020 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT, 1021 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT, 1022 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT, 1023 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT, 1024 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT, 1025 }; 1026 1027 enum { 1028 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 1029 MLX5_CMD_OP_CREATE_MKEY = 0x200, 1030 MLX5_CMD_OP_CREATE_CQ = 0x400, 1031 MLX5_CMD_OP_CREATE_QP = 0x500, 1032 MLX5_CMD_OP_RST2INIT_QP = 0x502, 1033 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 1034 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 1035 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 1036 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 1037 MLX5_CMD_OP_QP_2ERR = 0x507, 1038 MLX5_CMD_OP_QP_2RST = 0x50A, 1039 MLX5_CMD_OP_QUERY_QP = 0x50B, 1040 MLX5_CMD_OP_SQD2RTS_QP = 0x50C, 1041 MLX5_CMD_OP_INIT2INIT_QP = 0x50E, 1042 MLX5_CMD_OP_SUSPEND_QP = 0x50F, 1043 MLX5_CMD_OP_RESUME_QP = 0x510, 1044 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 1045 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 1046 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 1047 MLX5_CMD_OP_ALLOC_PD = 0x800, 1048 MLX5_CMD_OP_DEALLOC_PD = 0x801, 1049 MLX5_CMD_OP_ACCESS_REGISTER = 0x805, 1050 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 1051 MLX5_CMD_OP_QUERY_LAG = 0x842, 1052 MLX5_CMD_OP_CREATE_TIR = 0x900, 1053 MLX5_CMD_OP_MODIFY_TIR = 0x901, 1054 MLX5_CMD_OP_CREATE_SQ = 0X904, 1055 MLX5_CMD_OP_MODIFY_SQ = 0X905, 1056 MLX5_CMD_OP_CREATE_RQ = 0x908, 1057 MLX5_CMD_OP_MODIFY_RQ = 0x909, 1058 MLX5_CMD_OP_QUERY_RQ = 0x90b, 1059 MLX5_CMD_OP_CREATE_TIS = 0x912, 1060 MLX5_CMD_OP_QUERY_TIS = 0x915, 1061 MLX5_CMD_OP_CREATE_RQT = 0x916, 1062 MLX5_CMD_OP_MODIFY_RQT = 0x917, 1063 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 1064 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 1065 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 1066 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 1067 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 1068 MLX5_CMD_SET_REGEX_PARAMS = 0xb04, 1069 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05, 1070 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06, 1071 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07, 1072 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c, 1073 }; 1074 1075 enum { 1076 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 1077 MLX5_MKC_ACCESS_MODE_KLM = 0x2, 1078 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3, 1079 }; 1080 1081 #define MLX5_ADAPTER_PAGE_SHIFT 12 1082 #define MLX5_LOG_RQ_STRIDE_SHIFT 4 1083 /** 1084 * The batch counter dcs id starts from 0x800000 and none batch counter 1085 * starts from 0. As currently, the counter is changed to be indexed by 1086 * pool index and the offset of the counter in the pool counters_raw array. 1087 * It means now the counter index is same for batch and none batch counter. 1088 * Add the 0x800000 batch counter offset to the batch counter index helps 1089 * indicate the counter index is from batch or none batch container pool. 1090 */ 1091 #define MLX5_CNT_BATCH_OFFSET 0x800000 1092 1093 /* The counter batch query requires ID align with 4. */ 1094 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4 1095 1096 /* Flow counters. */ 1097 struct mlx5_ifc_alloc_flow_counter_out_bits { 1098 u8 status[0x8]; 1099 u8 reserved_at_8[0x18]; 1100 u8 syndrome[0x20]; 1101 u8 flow_counter_id[0x20]; 1102 u8 reserved_at_60[0x20]; 1103 }; 1104 1105 struct mlx5_ifc_alloc_flow_counter_in_bits { 1106 u8 opcode[0x10]; 1107 u8 reserved_at_10[0x10]; 1108 u8 reserved_at_20[0x10]; 1109 u8 op_mod[0x10]; 1110 u8 flow_counter_id[0x20]; 1111 u8 reserved_at_40[0x18]; 1112 u8 flow_counter_bulk[0x8]; 1113 }; 1114 1115 struct mlx5_ifc_dealloc_flow_counter_out_bits { 1116 u8 status[0x8]; 1117 u8 reserved_at_8[0x18]; 1118 u8 syndrome[0x20]; 1119 u8 reserved_at_40[0x40]; 1120 }; 1121 1122 struct mlx5_ifc_dealloc_flow_counter_in_bits { 1123 u8 opcode[0x10]; 1124 u8 reserved_at_10[0x10]; 1125 u8 reserved_at_20[0x10]; 1126 u8 op_mod[0x10]; 1127 u8 flow_counter_id[0x20]; 1128 u8 reserved_at_60[0x20]; 1129 }; 1130 1131 struct mlx5_ifc_traffic_counter_bits { 1132 u8 packets[0x40]; 1133 u8 octets[0x40]; 1134 }; 1135 1136 struct mlx5_ifc_query_flow_counter_out_bits { 1137 u8 status[0x8]; 1138 u8 reserved_at_8[0x18]; 1139 u8 syndrome[0x20]; 1140 u8 reserved_at_40[0x40]; 1141 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 1142 }; 1143 1144 struct mlx5_ifc_query_flow_counter_in_bits { 1145 u8 opcode[0x10]; 1146 u8 reserved_at_10[0x10]; 1147 u8 reserved_at_20[0x10]; 1148 u8 op_mod[0x10]; 1149 u8 reserved_at_40[0x20]; 1150 u8 mkey[0x20]; 1151 u8 address[0x40]; 1152 u8 clear[0x1]; 1153 u8 dump_to_memory[0x1]; 1154 u8 num_of_counters[0x1e]; 1155 u8 flow_counter_id[0x20]; 1156 }; 1157 1158 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u 1159 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u 1160 1161 struct mlx5_ifc_klm_bits { 1162 u8 byte_count[0x20]; 1163 u8 mkey[0x20]; 1164 u8 address[0x40]; 1165 }; 1166 1167 struct mlx5_ifc_mkc_bits { 1168 u8 reserved_at_0[0x1]; 1169 u8 free[0x1]; 1170 u8 reserved_at_2[0x1]; 1171 u8 access_mode_4_2[0x3]; 1172 u8 reserved_at_6[0x7]; 1173 u8 relaxed_ordering_write[0x1]; 1174 u8 reserved_at_e[0x1]; 1175 u8 small_fence_on_rdma_read_response[0x1]; 1176 u8 umr_en[0x1]; 1177 u8 a[0x1]; 1178 u8 rw[0x1]; 1179 u8 rr[0x1]; 1180 u8 lw[0x1]; 1181 u8 lr[0x1]; 1182 u8 access_mode_1_0[0x2]; 1183 u8 reserved_at_18[0x8]; 1184 u8 qpn[0x18]; 1185 u8 mkey_7_0[0x8]; 1186 u8 reserved_at_40[0x20]; 1187 u8 length64[0x1]; 1188 u8 bsf_en[0x1]; 1189 u8 sync_umr[0x1]; 1190 u8 reserved_at_63[0x2]; 1191 u8 expected_sigerr_count[0x1]; 1192 u8 reserved_at_66[0x1]; 1193 u8 en_rinval[0x1]; 1194 u8 pd[0x18]; 1195 u8 start_addr[0x40]; 1196 u8 len[0x40]; 1197 u8 bsf_octword_size[0x20]; 1198 u8 reserved_at_120[0x80]; 1199 u8 translations_octword_size[0x20]; 1200 u8 reserved_at_1c0[0x19]; 1201 u8 relaxed_ordering_read[0x1]; 1202 u8 reserved_at_1da[0x1]; 1203 u8 log_page_size[0x5]; 1204 u8 reserved_at_1e0[0x3]; 1205 u8 crypto_en[0x2]; 1206 u8 reserved_at_1e5[0x1b]; 1207 }; 1208 1209 /* Range of values for MKEY context crypto_en field. */ 1210 enum { 1211 MLX5_MKEY_CRYPTO_DISABLED = 0x0, 1212 MLX5_MKEY_CRYPTO_ENABLED = 0x1, 1213 }; 1214 1215 struct mlx5_ifc_create_mkey_out_bits { 1216 u8 status[0x8]; 1217 u8 reserved_at_8[0x18]; 1218 u8 syndrome[0x20]; 1219 u8 reserved_at_40[0x8]; 1220 u8 mkey_index[0x18]; 1221 u8 reserved_at_60[0x20]; 1222 }; 1223 1224 struct mlx5_ifc_create_mkey_in_bits { 1225 u8 opcode[0x10]; 1226 u8 reserved_at_10[0x10]; 1227 u8 reserved_at_20[0x10]; 1228 u8 op_mod[0x10]; 1229 u8 reserved_at_40[0x20]; 1230 u8 pg_access[0x1]; 1231 u8 reserved_at_61[0x1f]; 1232 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 1233 u8 reserved_at_280[0x80]; 1234 u8 translations_octword_actual_size[0x20]; 1235 u8 mkey_umem_id[0x20]; 1236 u8 mkey_umem_offset[0x40]; 1237 u8 reserved_at_380[0x500]; 1238 u8 klm_pas_mtt[][0x20]; 1239 }; 1240 1241 enum { 1242 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, 1243 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, 1244 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1, 1245 MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, 1246 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, 1247 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, 1248 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, 1249 }; 1250 1251 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \ 1252 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ) 1253 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \ 1254 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS) 1255 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \ 1256 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH) 1257 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \ 1258 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO) 1259 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \ 1260 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO) 1261 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ 1262 (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT) 1263 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \ 1264 (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD) 1265 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \ 1266 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK) 1267 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \ 1268 (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK) 1269 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \ 1270 (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL) 1271 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \ 1272 (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN) 1273 1274 enum { 1275 MLX5_HCA_CAP_OPMOD_GET_MAX = 0, 1276 MLX5_HCA_CAP_OPMOD_GET_CUR = 1, 1277 }; 1278 1279 enum { 1280 MLX5_CAP_INLINE_MODE_L2, 1281 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT, 1282 MLX5_CAP_INLINE_MODE_NOT_REQUIRED, 1283 }; 1284 1285 enum { 1286 MLX5_INLINE_MODE_NONE, 1287 MLX5_INLINE_MODE_L2, 1288 MLX5_INLINE_MODE_IP, 1289 MLX5_INLINE_MODE_TCP_UDP, 1290 MLX5_INLINE_MODE_RESERVED4, 1291 MLX5_INLINE_MODE_INNER_L2, 1292 MLX5_INLINE_MODE_INNER_IP, 1293 MLX5_INLINE_MODE_INNER_TCP_UDP, 1294 }; 1295 1296 /* The supported timestamp formats reported in HCA attributes. */ 1297 enum { 1298 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0, 1299 MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1, 1300 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2, 1301 }; 1302 1303 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */ 1304 enum { 1305 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 1306 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 1307 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 1308 }; 1309 1310 /* HCA bit masks indicating which Flex parser protocols are already enabled. */ 1311 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0) 1312 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1) 1313 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2) 1314 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3) 1315 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4) 1316 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5) 1317 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6) 1318 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7) 1319 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8) 1320 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9) 1321 1322 /* The device steering logic format. */ 1323 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0 1324 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1 1325 1326 struct mlx5_ifc_cmd_hca_cap_bits { 1327 u8 reserved_at_0[0x30]; 1328 u8 vhca_id[0x10]; 1329 u8 reserved_at_40[0x20]; 1330 u8 reserved_at_60[0x3]; 1331 u8 log_regexp_scatter_gather_size[0x5]; 1332 u8 reserved_at_68[0x3]; 1333 u8 log_dma_mmo_size[0x5]; 1334 u8 reserved_at_70[0x3]; 1335 u8 log_compress_mmo_size[0x5]; 1336 u8 reserved_at_78[0x3]; 1337 u8 log_decompress_mmo_size[0x5]; 1338 u8 log_max_srq_sz[0x8]; 1339 u8 log_max_qp_sz[0x8]; 1340 u8 reserved_at_90[0x9]; 1341 u8 wqe_index_ignore_cap[0x1]; 1342 u8 dynamic_qp_allocation[0x1]; 1343 u8 log_max_qp[0x5]; 1344 u8 regexp[0x1]; 1345 u8 reserved_at_a1[0x3]; 1346 u8 regexp_num_of_engines[0x4]; 1347 u8 reserved_at_a8[0x1]; 1348 u8 reg_c_preserve[0x1]; 1349 u8 reserved_at_aa[0x1]; 1350 u8 log_max_srq[0x5]; 1351 u8 reserved_at_b0[0x3]; 1352 u8 regexp_log_crspace_size[0x5]; 1353 u8 reserved_at_b8[0x3]; 1354 u8 scatter_fcs_w_decap_disable[0x1]; 1355 u8 reserved_at_bc[0x4]; 1356 u8 reserved_at_c0[0x8]; 1357 u8 log_max_cq_sz[0x8]; 1358 u8 reserved_at_d0[0xb]; 1359 u8 log_max_cq[0x5]; 1360 u8 log_max_eq_sz[0x8]; 1361 u8 relaxed_ordering_write[0x1]; 1362 u8 relaxed_ordering_read[0x1]; 1363 u8 access_register_user[0x1]; 1364 u8 log_max_mkey[0x5]; 1365 u8 reserved_at_f0[0x8]; 1366 u8 dump_fill_mkey[0x1]; 1367 u8 reserved_at_f9[0x3]; 1368 u8 log_max_eq[0x4]; 1369 u8 max_indirection[0x8]; 1370 u8 fixed_buffer_size[0x1]; 1371 u8 log_max_mrw_sz[0x7]; 1372 u8 force_teardown[0x1]; 1373 u8 reserved_at_111[0x1]; 1374 u8 log_max_bsf_list_size[0x6]; 1375 u8 umr_extended_translation_offset[0x1]; 1376 u8 null_mkey[0x1]; 1377 u8 log_max_klm_list_size[0x6]; 1378 u8 non_wire_sq[0x1]; 1379 u8 reserved_at_121[0x9]; 1380 u8 log_max_ra_req_dc[0x6]; 1381 u8 reserved_at_130[0x3]; 1382 u8 log_max_static_sq_wq[0x5]; 1383 u8 reserved_at_138[0x2]; 1384 u8 log_max_ra_res_dc[0x6]; 1385 u8 reserved_at_140[0xa]; 1386 u8 log_max_ra_req_qp[0x6]; 1387 u8 rtr2rts_qp_counters_set_id[0x1]; 1388 u8 rts2rts_udp_sport[0x1]; 1389 u8 rts2rts_lag_tx_port_affinity[0x1]; 1390 u8 dma_mmo_sq[0x1]; 1391 u8 compress_min_block_size[0x4]; 1392 u8 compress_mmo_sq[0x1]; 1393 u8 decompress_mmo_sq[0x1]; 1394 u8 log_max_ra_res_qp[0x6]; 1395 u8 end_pad[0x1]; 1396 u8 cc_query_allowed[0x1]; 1397 u8 cc_modify_allowed[0x1]; 1398 u8 start_pad[0x1]; 1399 u8 cache_line_128byte[0x1]; 1400 u8 reserved_at_165[0xa]; 1401 u8 qcam_reg[0x1]; 1402 u8 gid_table_size[0x10]; 1403 u8 out_of_seq_cnt[0x1]; 1404 u8 vport_counters[0x1]; 1405 u8 retransmission_q_counters[0x1]; 1406 u8 debug[0x1]; 1407 u8 modify_rq_counter_set_id[0x1]; 1408 u8 rq_delay_drop[0x1]; 1409 u8 max_qp_cnt[0xa]; 1410 u8 pkey_table_size[0x10]; 1411 u8 vport_group_manager[0x1]; 1412 u8 vhca_group_manager[0x1]; 1413 u8 ib_virt[0x1]; 1414 u8 eth_virt[0x1]; 1415 u8 vnic_env_queue_counters[0x1]; 1416 u8 ets[0x1]; 1417 u8 nic_flow_table[0x1]; 1418 u8 eswitch_manager[0x1]; 1419 u8 device_memory[0x1]; 1420 u8 mcam_reg[0x1]; 1421 u8 pcam_reg[0x1]; 1422 u8 local_ca_ack_delay[0x5]; 1423 u8 port_module_event[0x1]; 1424 u8 enhanced_error_q_counters[0x1]; 1425 u8 ports_check[0x1]; 1426 u8 reserved_at_1b3[0x1]; 1427 u8 disable_link_up[0x1]; 1428 u8 beacon_led[0x1]; 1429 u8 port_type[0x2]; 1430 u8 num_ports[0x8]; 1431 u8 reserved_at_1c0[0x1]; 1432 u8 pps[0x1]; 1433 u8 pps_modify[0x1]; 1434 u8 log_max_msg[0x5]; 1435 u8 reserved_at_1c8[0x4]; 1436 u8 max_tc[0x4]; 1437 u8 temp_warn_event[0x1]; 1438 u8 dcbx[0x1]; 1439 u8 general_notification_event[0x1]; 1440 u8 reserved_at_1d3[0x2]; 1441 u8 fpga[0x1]; 1442 u8 rol_s[0x1]; 1443 u8 rol_g[0x1]; 1444 u8 reserved_at_1d8[0x1]; 1445 u8 wol_s[0x1]; 1446 u8 wol_g[0x1]; 1447 u8 wol_a[0x1]; 1448 u8 wol_b[0x1]; 1449 u8 wol_m[0x1]; 1450 u8 wol_u[0x1]; 1451 u8 wol_p[0x1]; 1452 u8 stat_rate_support[0x10]; 1453 u8 reserved_at_1f0[0xc]; 1454 u8 cqe_version[0x4]; 1455 u8 compact_address_vector[0x1]; 1456 u8 striding_rq[0x1]; 1457 u8 reserved_at_202[0x1]; 1458 u8 ipoib_enhanced_offloads[0x1]; 1459 u8 ipoib_basic_offloads[0x1]; 1460 u8 reserved_at_205[0x1]; 1461 u8 repeated_block_disabled[0x1]; 1462 u8 umr_modify_entity_size_disabled[0x1]; 1463 u8 umr_modify_atomic_disabled[0x1]; 1464 u8 umr_indirect_mkey_disabled[0x1]; 1465 u8 umr_fence[0x2]; 1466 u8 reserved_at_20c[0x3]; 1467 u8 drain_sigerr[0x1]; 1468 u8 cmdif_checksum[0x2]; 1469 u8 sigerr_cqe[0x1]; 1470 u8 reserved_at_213[0x1]; 1471 u8 wq_signature[0x1]; 1472 u8 sctr_data_cqe[0x1]; 1473 u8 reserved_at_216[0x1]; 1474 u8 sho[0x1]; 1475 u8 tph[0x1]; 1476 u8 rf[0x1]; 1477 u8 dct[0x1]; 1478 u8 qos[0x1]; 1479 u8 eth_net_offloads[0x1]; 1480 u8 roce[0x1]; 1481 u8 atomic[0x1]; 1482 u8 reserved_at_21f[0x1]; 1483 u8 cq_oi[0x1]; 1484 u8 cq_resize[0x1]; 1485 u8 cq_moderation[0x1]; 1486 u8 reserved_at_223[0x3]; 1487 u8 cq_eq_remap[0x1]; 1488 u8 pg[0x1]; 1489 u8 block_lb_mc[0x1]; 1490 u8 reserved_at_229[0x1]; 1491 u8 scqe_break_moderation[0x1]; 1492 u8 cq_period_start_from_cqe[0x1]; 1493 u8 cd[0x1]; 1494 u8 reserved_at_22d[0x1]; 1495 u8 apm[0x1]; 1496 u8 vector_calc[0x1]; 1497 u8 umr_ptr_rlky[0x1]; 1498 u8 imaicl[0x1]; 1499 u8 reserved_at_232[0x4]; 1500 u8 qkv[0x1]; 1501 u8 pkv[0x1]; 1502 u8 set_deth_sqpn[0x1]; 1503 u8 reserved_at_239[0x3]; 1504 u8 xrc[0x1]; 1505 u8 ud[0x1]; 1506 u8 uc[0x1]; 1507 u8 rc[0x1]; 1508 u8 uar_4k[0x1]; 1509 u8 reserved_at_241[0x9]; 1510 u8 uar_sz[0x6]; 1511 u8 port_selection_cap[0x1]; 1512 u8 reserved_at_251[0x7]; 1513 u8 log_pg_sz[0x8]; 1514 u8 bf[0x1]; 1515 u8 driver_version[0x1]; 1516 u8 pad_tx_eth_packet[0x1]; 1517 u8 reserved_at_263[0x8]; 1518 u8 log_bf_reg_size[0x5]; 1519 u8 reserved_at_270[0xb]; 1520 u8 lag_master[0x1]; 1521 u8 num_lag_ports[0x4]; 1522 u8 reserved_at_280[0x10]; 1523 u8 max_wqe_sz_sq[0x10]; 1524 u8 reserved_at_2a0[0xc]; 1525 u8 regexp_mmo_sq[0x1]; 1526 u8 reserved_at_2b0[0x3]; 1527 u8 max_wqe_sz_rq[0x10]; 1528 u8 max_flow_counter_31_16[0x10]; 1529 u8 max_wqe_sz_sq_dc[0x10]; 1530 u8 reserved_at_2e0[0x7]; 1531 u8 max_qp_mcg[0x19]; 1532 u8 reserved_at_300[0x10]; 1533 u8 flow_counter_bulk_alloc[0x08]; 1534 u8 log_max_mcg[0x8]; 1535 u8 reserved_at_320[0x3]; 1536 u8 log_max_transport_domain[0x5]; 1537 u8 reserved_at_328[0x3]; 1538 u8 log_max_pd[0x5]; 1539 u8 reserved_at_330[0xb]; 1540 u8 log_max_xrcd[0x5]; 1541 u8 nic_receive_steering_discard[0x1]; 1542 u8 receive_discard_vport_down[0x1]; 1543 u8 transmit_discard_vport_down[0x1]; 1544 u8 reserved_at_343[0x5]; 1545 u8 log_max_flow_counter_bulk[0x8]; 1546 u8 max_flow_counter_15_0[0x10]; 1547 u8 modify_tis[0x1]; 1548 u8 flow_counters_dump[0x1]; 1549 u8 reserved_at_360[0x1]; 1550 u8 log_max_rq[0x5]; 1551 u8 reserved_at_368[0x3]; 1552 u8 log_max_sq[0x5]; 1553 u8 reserved_at_370[0x3]; 1554 u8 log_max_tir[0x5]; 1555 u8 reserved_at_378[0x3]; 1556 u8 log_max_tis[0x5]; 1557 u8 basic_cyclic_rcv_wqe[0x1]; 1558 u8 reserved_at_381[0x2]; 1559 u8 log_max_rmp[0x5]; 1560 u8 reserved_at_388[0x3]; 1561 u8 log_max_rqt[0x5]; 1562 u8 reserved_at_390[0x3]; 1563 u8 log_max_rqt_size[0x5]; 1564 u8 reserved_at_398[0x3]; 1565 u8 log_max_tis_per_sq[0x5]; 1566 u8 ext_stride_num_range[0x1]; 1567 u8 reserved_at_3a1[0x2]; 1568 u8 log_max_stride_sz_rq[0x5]; 1569 u8 reserved_at_3a8[0x3]; 1570 u8 log_min_stride_sz_rq[0x5]; 1571 u8 reserved_at_3b0[0x3]; 1572 u8 log_max_stride_sz_sq[0x5]; 1573 u8 reserved_at_3b8[0x3]; 1574 u8 log_min_stride_sz_sq[0x5]; 1575 u8 hairpin[0x1]; 1576 u8 reserved_at_3c1[0x2]; 1577 u8 log_max_hairpin_queues[0x5]; 1578 u8 reserved_at_3c8[0x3]; 1579 u8 log_max_hairpin_wq_data_sz[0x5]; 1580 u8 reserved_at_3d0[0x3]; 1581 u8 log_max_hairpin_num_packets[0x5]; 1582 u8 reserved_at_3d8[0x3]; 1583 u8 log_max_wq_sz[0x5]; 1584 u8 nic_vport_change_event[0x1]; 1585 u8 disable_local_lb_uc[0x1]; 1586 u8 disable_local_lb_mc[0x1]; 1587 u8 log_min_hairpin_wq_data_sz[0x5]; 1588 u8 reserved_at_3e8[0x3]; 1589 u8 log_max_vlan_list[0x5]; 1590 u8 reserved_at_3f0[0x3]; 1591 u8 log_max_current_mc_list[0x5]; 1592 u8 reserved_at_3f8[0x3]; 1593 u8 log_max_current_uc_list[0x5]; 1594 u8 general_obj_types[0x40]; 1595 u8 sq_ts_format[0x2]; 1596 u8 rq_ts_format[0x2]; 1597 u8 steering_format_version[0x4]; 1598 u8 reserved_at_448[0x18]; 1599 u8 reserved_at_460[0x8]; 1600 u8 aes_xts[0x1]; 1601 u8 crypto[0x1]; 1602 u8 reserved_at_46a[0x6]; 1603 u8 max_num_eqs[0x10]; 1604 u8 reserved_at_480[0x3]; 1605 u8 log_max_l2_table[0x5]; 1606 u8 reserved_at_488[0x8]; 1607 u8 log_uar_page_sz[0x10]; 1608 u8 reserved_at_4a0[0x20]; 1609 u8 device_frequency_mhz[0x20]; 1610 u8 device_frequency_khz[0x20]; 1611 u8 reserved_at_500[0x20]; 1612 u8 num_of_uars_per_page[0x20]; 1613 u8 flex_parser_protocols[0x20]; 1614 u8 max_geneve_tlv_options[0x8]; 1615 u8 reserved_at_568[0x3]; 1616 u8 max_geneve_tlv_option_data_len[0x5]; 1617 u8 reserved_at_570[0x49]; 1618 u8 mini_cqe_resp_l3_l4_tag[0x1]; 1619 u8 mini_cqe_resp_flow_tag[0x1]; 1620 u8 enhanced_cqe_compression[0x1]; 1621 u8 mini_cqe_resp_stride_index[0x1]; 1622 u8 cqe_128_always[0x1]; 1623 u8 cqe_compression_128[0x1]; 1624 u8 cqe_compression[0x1]; 1625 u8 cqe_compression_timeout[0x10]; 1626 u8 cqe_compression_max_num[0x10]; 1627 u8 reserved_at_5e0[0x10]; 1628 u8 tag_matching[0x1]; 1629 u8 rndv_offload_rc[0x1]; 1630 u8 rndv_offload_dc[0x1]; 1631 u8 log_tag_matching_list_sz[0x5]; 1632 u8 reserved_at_5f8[0x3]; 1633 u8 log_max_xrq[0x5]; 1634 u8 affiliate_nic_vport_criteria[0x8]; 1635 u8 native_port_num[0x8]; 1636 u8 num_vhca_ports[0x8]; 1637 u8 reserved_at_618[0x6]; 1638 u8 sw_owner_id[0x1]; 1639 u8 reserved_at_61f[0x109]; 1640 u8 dma_mmo_qp[0x1]; 1641 u8 regexp_mmo_qp[0x1]; 1642 u8 compress_mmo_qp[0x1]; 1643 u8 decompress_mmo_qp[0x1]; 1644 u8 reserved_at_624[0xd4]; 1645 }; 1646 1647 struct mlx5_ifc_qos_cap_bits { 1648 u8 packet_pacing[0x1]; 1649 u8 esw_scheduling[0x1]; 1650 u8 esw_bw_share[0x1]; 1651 u8 esw_rate_limit[0x1]; 1652 u8 reserved_at_4[0x1]; 1653 u8 packet_pacing_burst_bound[0x1]; 1654 u8 packet_pacing_typical_size[0x1]; 1655 u8 flow_meter_old[0x1]; 1656 u8 reserved_at_8[0x8]; 1657 u8 log_max_flow_meter[0x8]; 1658 u8 flow_meter_reg_id[0x8]; 1659 u8 wqe_rate_pp[0x1]; 1660 u8 reserved_at_25[0x7]; 1661 u8 flow_meter[0x1]; 1662 u8 reserved_at_2e[0x17]; 1663 u8 packet_pacing_max_rate[0x20]; 1664 u8 packet_pacing_min_rate[0x20]; 1665 u8 reserved_at_80[0x10]; 1666 u8 packet_pacing_rate_table_size[0x10]; 1667 u8 esw_element_type[0x10]; 1668 u8 esw_tsar_type[0x10]; 1669 u8 reserved_at_c0[0x10]; 1670 u8 max_qos_para_vport[0x10]; 1671 u8 max_tsar_bw_share[0x20]; 1672 u8 nic_element_type[0x10]; 1673 u8 nic_tsar_type[0x10]; 1674 u8 reserved_at_120[0x3]; 1675 u8 log_meter_aso_granularity[0x5]; 1676 u8 reserved_at_128[0x3]; 1677 u8 log_meter_aso_max_alloc[0x5]; 1678 u8 reserved_at_130[0x3]; 1679 u8 log_max_num_meter_aso[0x5]; 1680 u8 reserved_at_138[0x6b0]; 1681 }; 1682 1683 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1684 u8 csum_cap[0x1]; 1685 u8 vlan_cap[0x1]; 1686 u8 lro_cap[0x1]; 1687 u8 lro_psh_flag[0x1]; 1688 u8 lro_time_stamp[0x1]; 1689 u8 lro_max_msg_sz_mode[0x2]; 1690 u8 wqe_vlan_insert[0x1]; 1691 u8 self_lb_en_modifiable[0x1]; 1692 u8 self_lb_mc[0x1]; 1693 u8 self_lb_uc[0x1]; 1694 u8 max_lso_cap[0x5]; 1695 u8 multi_pkt_send_wqe[0x2]; 1696 u8 wqe_inline_mode[0x2]; 1697 u8 rss_ind_tbl_cap[0x4]; 1698 u8 reg_umr_sq[0x1]; 1699 u8 scatter_fcs[0x1]; 1700 u8 enhanced_multi_pkt_send_wqe[0x1]; 1701 u8 tunnel_lso_const_out_ip_id[0x1]; 1702 u8 tunnel_lro_gre[0x1]; 1703 u8 tunnel_lro_vxlan[0x1]; 1704 u8 tunnel_stateless_gre[0x1]; 1705 u8 tunnel_stateless_vxlan[0x1]; 1706 u8 swp[0x1]; 1707 u8 swp_csum[0x1]; 1708 u8 swp_lso[0x1]; 1709 u8 reserved_at_23[0x8]; 1710 u8 tunnel_stateless_gtp[0x1]; 1711 u8 reserved_at_25[0x4]; 1712 u8 max_vxlan_udp_ports[0x8]; 1713 u8 reserved_at_38[0x6]; 1714 u8 max_geneve_opt_len[0x1]; 1715 u8 tunnel_stateless_geneve_rx[0x1]; 1716 u8 reserved_at_40[0x10]; 1717 u8 lro_min_mss_size[0x10]; 1718 u8 reserved_at_60[0x120]; 1719 u8 lro_timer_supported_periods[4][0x20]; 1720 u8 reserved_at_200[0x600]; 1721 }; 1722 1723 enum { 1724 MLX5_VIRTQ_TYPE_SPLIT = 0, 1725 MLX5_VIRTQ_TYPE_PACKED = 1, 1726 }; 1727 1728 enum { 1729 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0, 1730 MLX5_VIRTQ_EVENT_MODE_QP = 1, 1731 MLX5_VIRTQ_EVENT_MODE_MSIX = 2, 1732 }; 1733 1734 struct mlx5_ifc_virtio_emulation_cap_bits { 1735 u8 desc_tunnel_offload_type[0x1]; 1736 u8 eth_frame_offload_type[0x1]; 1737 u8 virtio_version_1_0[0x1]; 1738 u8 tso_ipv4[0x1]; 1739 u8 tso_ipv6[0x1]; 1740 u8 tx_csum[0x1]; 1741 u8 rx_csum[0x1]; 1742 u8 reserved_at_7[0x1][0x9]; 1743 u8 event_mode[0x8]; 1744 u8 virtio_queue_type[0x8]; 1745 u8 reserved_at_20[0x13]; 1746 u8 log_doorbell_stride[0x5]; 1747 u8 reserved_at_3b[0x3]; 1748 u8 log_doorbell_bar_size[0x5]; 1749 u8 doorbell_bar_offset[0x40]; 1750 u8 reserved_at_80[0x8]; 1751 u8 max_num_virtio_queues[0x18]; 1752 u8 reserved_at_a0[0x60]; 1753 u8 umem_1_buffer_param_a[0x20]; 1754 u8 umem_1_buffer_param_b[0x20]; 1755 u8 umem_2_buffer_param_a[0x20]; 1756 u8 umem_2_buffer_param_b[0x20]; 1757 u8 umem_3_buffer_param_a[0x20]; 1758 u8 umem_3_buffer_param_b[0x20]; 1759 u8 reserved_at_1c0[0x620]; 1760 }; 1761 1762 struct mlx5_ifc_flow_table_prop_layout_bits { 1763 u8 ft_support[0x1]; 1764 u8 flow_tag[0x1]; 1765 u8 flow_counter[0x1]; 1766 u8 flow_modify_en[0x1]; 1767 u8 modify_root[0x1]; 1768 u8 identified_miss_table[0x1]; 1769 u8 flow_table_modify[0x1]; 1770 u8 reformat[0x1]; 1771 u8 decap[0x1]; 1772 u8 reset_root_to_default[0x1]; 1773 u8 pop_vlan[0x1]; 1774 u8 push_vlan[0x1]; 1775 u8 fpga_vendor_acceleration[0x1]; 1776 u8 pop_vlan_2[0x1]; 1777 u8 push_vlan_2[0x1]; 1778 u8 reformat_and_vlan_action[0x1]; 1779 u8 modify_and_vlan_action[0x1]; 1780 u8 sw_owner[0x1]; 1781 u8 reformat_l3_tunnel_to_l2[0x1]; 1782 u8 reformat_l2_to_l3_tunnel[0x1]; 1783 u8 reformat_and_modify_action[0x1]; 1784 u8 reserved_at_15[0x9]; 1785 u8 sw_owner_v2[0x1]; 1786 u8 reserved_at_1f[0x1]; 1787 u8 reserved_at_20[0x2]; 1788 u8 log_max_ft_size[0x6]; 1789 u8 log_max_modify_header_context[0x8]; 1790 u8 max_modify_header_actions[0x8]; 1791 u8 max_ft_level[0x8]; 1792 u8 reserved_at_40[0x8]; 1793 u8 log_max_ft_sampler_num[8]; 1794 u8 metadata_reg_b_width[0x8]; 1795 u8 metadata_reg_a_width[0x8]; 1796 u8 reserved_at_60[0x18]; 1797 u8 log_max_ft_num[0x8]; 1798 u8 reserved_at_80[0x10]; 1799 u8 log_max_flow_counter[0x8]; 1800 u8 log_max_destination[0x8]; 1801 u8 reserved_at_a0[0x18]; 1802 u8 log_max_flow[0x8]; 1803 u8 reserved_at_c0[0x140]; 1804 }; 1805 1806 struct mlx5_ifc_roce_caps_bits { 1807 u8 reserved_0[0x1e]; 1808 u8 qp_ts_format[0x2]; 1809 u8 reserved_at_20[0x7e0]; 1810 }; 1811 1812 /* 1813 * Table 1872 - Flow Table Fields Supported 2 Format 1814 */ 1815 struct mlx5_ifc_ft_fields_support_2_bits { 1816 u8 reserved_at_0[0xf]; 1817 u8 tunnel_header_2_3[0x1]; 1818 u8 tunnel_header_0_1[0x1]; 1819 u8 macsec_syndrome[0x1]; 1820 u8 macsec_tag[0x1]; 1821 u8 outer_lrh_sl[0x1]; 1822 u8 inner_ipv4_ihl[0x1]; 1823 u8 outer_ipv4_ihl[0x1]; 1824 u8 psp_syndrome[0x1]; 1825 u8 inner_l3_ok[0x1]; 1826 u8 inner_l4_ok[0x1]; 1827 u8 outer_l3_ok[0x1]; 1828 u8 outer_l4_ok[0x1]; 1829 u8 psp_header[0x1]; 1830 u8 inner_ipv4_checksum_ok[0x1]; 1831 u8 inner_l4_checksum_ok[0x1]; 1832 u8 outer_ipv4_checksum_ok[0x1]; 1833 u8 outer_l4_checksum_ok[0x1]; 1834 u8 reserved_at_20[0x60]; 1835 }; 1836 1837 struct mlx5_ifc_flow_table_nic_cap_bits { 1838 u8 reserved_at_0[0x200]; 1839 struct mlx5_ifc_flow_table_prop_layout_bits 1840 flow_table_properties_nic_receive; 1841 struct mlx5_ifc_flow_table_prop_layout_bits 1842 flow_table_properties_nic_receive_rdma; 1843 struct mlx5_ifc_flow_table_prop_layout_bits 1844 flow_table_properties_nic_receive_sniffer; 1845 struct mlx5_ifc_flow_table_prop_layout_bits 1846 flow_table_properties_nic_transmit; 1847 struct mlx5_ifc_flow_table_prop_layout_bits 1848 flow_table_properties_nic_transmit_rdma; 1849 struct mlx5_ifc_flow_table_prop_layout_bits 1850 flow_table_properties_nic_transmit_sniffer; 1851 u8 reserved_at_e00[0x600]; 1852 struct mlx5_ifc_ft_fields_support_2_bits 1853 ft_field_support_2_nic_receive; 1854 }; 1855 1856 struct mlx5_ifc_cmd_hca_cap_2_bits { 1857 u8 reserved_at_0[0x80]; /* End of DW4. */ 1858 u8 reserved_at_80[0xb]; 1859 u8 log_max_num_reserved_qpn[0x5]; 1860 u8 reserved_at_90[0x3]; 1861 u8 log_reserved_qpn_granularity[0x5]; 1862 u8 reserved_at_98[0x3]; 1863 u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */ 1864 u8 max_reformat_insert_size[0x8]; 1865 u8 max_reformat_insert_offset[0x8]; 1866 u8 max_reformat_remove_size[0x8]; 1867 u8 max_reformat_remove_offset[0x8]; /* End of DW6. */ 1868 u8 aso_conntrack_reg_id[0x8]; 1869 u8 reserved_at_c8[0x3]; 1870 u8 log_conn_track_granularity[0x5]; 1871 u8 reserved_at_d0[0x3]; 1872 u8 log_conn_track_max_alloc[0x5]; 1873 u8 reserved_at_d8[0x3]; 1874 u8 log_max_conn_track_offload[0x5]; 1875 u8 reserved_at_e0[0x20]; /* End of DW7. */ 1876 u8 reserved_at_100[0x700]; 1877 }; 1878 1879 union mlx5_ifc_hca_cap_union_bits { 1880 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 1881 struct mlx5_ifc_per_protocol_networking_offload_caps_bits 1882 per_protocol_networking_offload_caps; 1883 struct mlx5_ifc_qos_cap_bits qos_cap; 1884 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps; 1885 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 1886 struct mlx5_ifc_roce_caps_bits roce_caps; 1887 u8 reserved_at_0[0x8000]; 1888 }; 1889 1890 struct mlx5_ifc_set_action_in_bits { 1891 u8 action_type[0x4]; 1892 u8 field[0xc]; 1893 u8 reserved_at_10[0x3]; 1894 u8 offset[0x5]; 1895 u8 reserved_at_18[0x3]; 1896 u8 length[0x5]; 1897 u8 data[0x20]; 1898 }; 1899 1900 struct mlx5_ifc_query_hca_cap_out_bits { 1901 u8 status[0x8]; 1902 u8 reserved_at_8[0x18]; 1903 u8 syndrome[0x20]; 1904 u8 reserved_at_40[0x40]; 1905 union mlx5_ifc_hca_cap_union_bits capability; 1906 }; 1907 1908 struct mlx5_ifc_query_hca_cap_in_bits { 1909 u8 opcode[0x10]; 1910 u8 reserved_at_10[0x10]; 1911 u8 reserved_at_20[0x10]; 1912 u8 op_mod[0x10]; 1913 u8 reserved_at_40[0x40]; 1914 }; 1915 1916 struct mlx5_ifc_mac_address_layout_bits { 1917 u8 reserved_at_0[0x10]; 1918 u8 mac_addr_47_32[0x10]; 1919 u8 mac_addr_31_0[0x20]; 1920 }; 1921 1922 struct mlx5_ifc_nic_vport_context_bits { 1923 u8 reserved_at_0[0x5]; 1924 u8 min_wqe_inline_mode[0x3]; 1925 u8 reserved_at_8[0x15]; 1926 u8 disable_mc_local_lb[0x1]; 1927 u8 disable_uc_local_lb[0x1]; 1928 u8 roce_en[0x1]; 1929 u8 arm_change_event[0x1]; 1930 u8 reserved_at_21[0x1a]; 1931 u8 event_on_mtu[0x1]; 1932 u8 event_on_promisc_change[0x1]; 1933 u8 event_on_vlan_change[0x1]; 1934 u8 event_on_mc_address_change[0x1]; 1935 u8 event_on_uc_address_change[0x1]; 1936 u8 reserved_at_40[0xc]; 1937 u8 affiliation_criteria[0x4]; 1938 u8 affiliated_vhca_id[0x10]; 1939 u8 reserved_at_60[0xd0]; 1940 u8 mtu[0x10]; 1941 u8 system_image_guid[0x40]; 1942 u8 port_guid[0x40]; 1943 u8 node_guid[0x40]; 1944 u8 reserved_at_200[0x140]; 1945 u8 qkey_violation_counter[0x10]; 1946 u8 reserved_at_350[0x430]; 1947 u8 promisc_uc[0x1]; 1948 u8 promisc_mc[0x1]; 1949 u8 promisc_all[0x1]; 1950 u8 reserved_at_783[0x2]; 1951 u8 allowed_list_type[0x3]; 1952 u8 reserved_at_788[0xc]; 1953 u8 allowed_list_size[0xc]; 1954 struct mlx5_ifc_mac_address_layout_bits permanent_address; 1955 u8 reserved_at_7e0[0x20]; 1956 }; 1957 1958 struct mlx5_ifc_query_nic_vport_context_out_bits { 1959 u8 status[0x8]; 1960 u8 reserved_at_8[0x18]; 1961 u8 syndrome[0x20]; 1962 u8 reserved_at_40[0x40]; 1963 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 1964 }; 1965 1966 struct mlx5_ifc_query_nic_vport_context_in_bits { 1967 u8 opcode[0x10]; 1968 u8 reserved_at_10[0x10]; 1969 u8 reserved_at_20[0x10]; 1970 u8 op_mod[0x10]; 1971 u8 other_vport[0x1]; 1972 u8 reserved_at_41[0xf]; 1973 u8 vport_number[0x10]; 1974 u8 reserved_at_60[0x5]; 1975 u8 allowed_list_type[0x3]; 1976 u8 reserved_at_68[0x18]; 1977 }; 1978 1979 /* 1980 * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa. 1981 * Each TIS binds to one PF by setting lag_tx_port_affinity (>0). 1982 * Once LAG enabled, we create multiple TISs and bind each one to 1983 * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1. 1984 */ 1985 #define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \ 1986 (index) % (num) + 1 : 0) 1987 struct mlx5_ifc_tisc_bits { 1988 u8 strict_lag_tx_port_affinity[0x1]; 1989 u8 reserved_at_1[0x3]; 1990 u8 lag_tx_port_affinity[0x04]; 1991 u8 reserved_at_8[0x4]; 1992 u8 prio[0x4]; 1993 u8 reserved_at_10[0x10]; 1994 u8 reserved_at_20[0x100]; 1995 u8 reserved_at_120[0x8]; 1996 u8 transport_domain[0x18]; 1997 u8 reserved_at_140[0x8]; 1998 u8 underlay_qpn[0x18]; 1999 u8 reserved_at_160[0x3a0]; 2000 }; 2001 2002 struct mlx5_ifc_query_tis_out_bits { 2003 u8 status[0x8]; 2004 u8 reserved_at_8[0x18]; 2005 u8 syndrome[0x20]; 2006 u8 reserved_at_40[0x40]; 2007 struct mlx5_ifc_tisc_bits tis_context; 2008 }; 2009 2010 struct mlx5_ifc_query_tis_in_bits { 2011 u8 opcode[0x10]; 2012 u8 reserved_at_10[0x10]; 2013 u8 reserved_at_20[0x10]; 2014 u8 op_mod[0x10]; 2015 u8 reserved_at_40[0x8]; 2016 u8 tisn[0x18]; 2017 u8 reserved_at_60[0x20]; 2018 }; 2019 2020 /* port_select_mode definition. */ 2021 enum mlx5_lag_mode_type { 2022 MLX5_LAG_MODE_TIS = 0, 2023 MLX5_LAG_MODE_HASH = 1, 2024 }; 2025 2026 struct mlx5_ifc_lag_context_bits { 2027 u8 fdb_selection_mode[0x1]; 2028 u8 reserved_at_1[0x14]; 2029 u8 port_select_mode[0x3]; 2030 u8 reserved_at_18[0x5]; 2031 u8 lag_state[0x3]; 2032 u8 reserved_at_20[0x14]; 2033 u8 tx_remap_affinity_2[0x4]; 2034 u8 reserved_at_38[0x4]; 2035 u8 tx_remap_affinity_1[0x4]; 2036 }; 2037 2038 struct mlx5_ifc_query_lag_in_bits { 2039 u8 opcode[0x10]; 2040 u8 uid[0x10]; 2041 u8 reserved_at_20[0x10]; 2042 u8 op_mod[0x10]; 2043 u8 reserved_at_40[0x40]; 2044 }; 2045 2046 struct mlx5_ifc_query_lag_out_bits { 2047 u8 status[0x8]; 2048 u8 reserved_at_8[0x18]; 2049 u8 syndrome[0x20]; 2050 struct mlx5_ifc_lag_context_bits context; 2051 }; 2052 2053 struct mlx5_ifc_alloc_transport_domain_out_bits { 2054 u8 status[0x8]; 2055 u8 reserved_at_8[0x18]; 2056 u8 syndrome[0x20]; 2057 u8 reserved_at_40[0x8]; 2058 u8 transport_domain[0x18]; 2059 u8 reserved_at_60[0x20]; 2060 }; 2061 2062 struct mlx5_ifc_alloc_transport_domain_in_bits { 2063 u8 opcode[0x10]; 2064 u8 reserved_at_10[0x10]; 2065 u8 reserved_at_20[0x10]; 2066 u8 op_mod[0x10]; 2067 u8 reserved_at_40[0x40]; 2068 }; 2069 2070 enum { 2071 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 2072 MLX5_WQ_TYPE_CYCLIC = 0x1, 2073 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 2074 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 2075 }; 2076 2077 enum { 2078 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 2079 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 2080 }; 2081 2082 struct mlx5_ifc_wq_bits { 2083 u8 wq_type[0x4]; 2084 u8 wq_signature[0x1]; 2085 u8 end_padding_mode[0x2]; 2086 u8 cd_slave[0x1]; 2087 u8 reserved_at_8[0x18]; 2088 u8 hds_skip_first_sge[0x1]; 2089 u8 log2_hds_buf_size[0x3]; 2090 u8 reserved_at_24[0x7]; 2091 u8 page_offset[0x5]; 2092 u8 lwm[0x10]; 2093 u8 reserved_at_40[0x8]; 2094 u8 pd[0x18]; 2095 u8 reserved_at_60[0x8]; 2096 u8 uar_page[0x18]; 2097 u8 dbr_addr[0x40]; 2098 u8 hw_counter[0x20]; 2099 u8 sw_counter[0x20]; 2100 u8 reserved_at_100[0xc]; 2101 u8 log_wq_stride[0x4]; 2102 u8 reserved_at_110[0x3]; 2103 u8 log_wq_pg_sz[0x5]; 2104 u8 reserved_at_118[0x3]; 2105 u8 log_wq_sz[0x5]; 2106 u8 dbr_umem_valid[0x1]; 2107 u8 wq_umem_valid[0x1]; 2108 u8 reserved_at_122[0x1]; 2109 u8 log_hairpin_num_packets[0x5]; 2110 u8 reserved_at_128[0x3]; 2111 u8 log_hairpin_data_sz[0x5]; 2112 u8 reserved_at_130[0x4]; 2113 u8 single_wqe_log_num_of_strides[0x4]; 2114 u8 two_byte_shift_en[0x1]; 2115 u8 reserved_at_139[0x4]; 2116 u8 single_stride_log_num_of_bytes[0x3]; 2117 u8 dbr_umem_id[0x20]; 2118 u8 wq_umem_id[0x20]; 2119 u8 wq_umem_offset[0x40]; 2120 u8 reserved_at_1c0[0x440]; 2121 }; 2122 2123 enum { 2124 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2125 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2126 }; 2127 2128 enum { 2129 MLX5_RQC_STATE_RST = 0x0, 2130 MLX5_RQC_STATE_RDY = 0x1, 2131 MLX5_RQC_STATE_ERR = 0x3, 2132 }; 2133 2134 struct mlx5_ifc_rqc_bits { 2135 u8 rlky[0x1]; 2136 u8 delay_drop_en[0x1]; 2137 u8 scatter_fcs[0x1]; 2138 u8 vsd[0x1]; 2139 u8 mem_rq_type[0x4]; 2140 u8 state[0x4]; 2141 u8 reserved_at_c[0x1]; 2142 u8 flush_in_error_en[0x1]; 2143 u8 hairpin[0x1]; 2144 u8 reserved_at_f[0xB]; 2145 u8 ts_format[0x02]; 2146 u8 reserved_at_1c[0x4]; 2147 u8 reserved_at_20[0x8]; 2148 u8 user_index[0x18]; 2149 u8 reserved_at_40[0x8]; 2150 u8 cqn[0x18]; 2151 u8 counter_set_id[0x8]; 2152 u8 reserved_at_68[0x18]; 2153 u8 reserved_at_80[0x8]; 2154 u8 rmpn[0x18]; 2155 u8 reserved_at_a0[0x8]; 2156 u8 hairpin_peer_sq[0x18]; 2157 u8 reserved_at_c0[0x10]; 2158 u8 hairpin_peer_vhca[0x10]; 2159 u8 reserved_at_e0[0xa0]; 2160 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */ 2161 }; 2162 2163 struct mlx5_ifc_create_rq_out_bits { 2164 u8 status[0x8]; 2165 u8 reserved_at_8[0x18]; 2166 u8 syndrome[0x20]; 2167 u8 reserved_at_40[0x8]; 2168 u8 rqn[0x18]; 2169 u8 reserved_at_60[0x20]; 2170 }; 2171 2172 struct mlx5_ifc_create_rq_in_bits { 2173 u8 opcode[0x10]; 2174 u8 uid[0x10]; 2175 u8 reserved_at_20[0x10]; 2176 u8 op_mod[0x10]; 2177 u8 reserved_at_40[0xc0]; 2178 struct mlx5_ifc_rqc_bits ctx; 2179 }; 2180 2181 struct mlx5_ifc_modify_rq_out_bits { 2182 u8 status[0x8]; 2183 u8 reserved_at_8[0x18]; 2184 u8 syndrome[0x20]; 2185 u8 reserved_at_40[0x40]; 2186 }; 2187 2188 struct mlx5_ifc_query_rq_out_bits { 2189 u8 status[0x8]; 2190 u8 reserved_at_8[0x18]; 2191 u8 syndrome[0x20]; 2192 u8 reserved_at_40[0xc0]; 2193 struct mlx5_ifc_rqc_bits rq_context; 2194 }; 2195 2196 struct mlx5_ifc_query_rq_in_bits { 2197 u8 opcode[0x10]; 2198 u8 reserved_at_10[0x10]; 2199 u8 reserved_at_20[0x10]; 2200 u8 op_mod[0x10]; 2201 u8 reserved_at_40[0x8]; 2202 u8 rqn[0x18]; 2203 u8 reserved_at_60[0x20]; 2204 }; 2205 2206 struct mlx5_ifc_create_tis_out_bits { 2207 u8 status[0x8]; 2208 u8 reserved_at_8[0x18]; 2209 u8 syndrome[0x20]; 2210 u8 reserved_at_40[0x8]; 2211 u8 tisn[0x18]; 2212 u8 reserved_at_60[0x20]; 2213 }; 2214 2215 struct mlx5_ifc_create_tis_in_bits { 2216 u8 opcode[0x10]; 2217 u8 uid[0x10]; 2218 u8 reserved_at_20[0x10]; 2219 u8 op_mod[0x10]; 2220 u8 reserved_at_40[0xc0]; 2221 struct mlx5_ifc_tisc_bits ctx; 2222 }; 2223 2224 enum { 2225 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0, 2226 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 2227 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 2228 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 2229 }; 2230 2231 struct mlx5_ifc_modify_rq_in_bits { 2232 u8 opcode[0x10]; 2233 u8 uid[0x10]; 2234 u8 reserved_at_20[0x10]; 2235 u8 op_mod[0x10]; 2236 u8 rq_state[0x4]; 2237 u8 reserved_at_44[0x4]; 2238 u8 rqn[0x18]; 2239 u8 reserved_at_60[0x20]; 2240 u8 modify_bitmask[0x40]; 2241 u8 reserved_at_c0[0x40]; 2242 struct mlx5_ifc_rqc_bits ctx; 2243 }; 2244 2245 enum { 2246 MLX5_L3_PROT_TYPE_IPV4 = 0, 2247 MLX5_L3_PROT_TYPE_IPV6 = 1, 2248 }; 2249 2250 enum { 2251 MLX5_L4_PROT_TYPE_TCP = 0, 2252 MLX5_L4_PROT_TYPE_UDP = 1, 2253 }; 2254 2255 enum { 2256 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2257 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2258 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2259 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2260 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2261 }; 2262 2263 struct mlx5_ifc_rx_hash_field_select_bits { 2264 u8 l3_prot_type[0x1]; 2265 u8 l4_prot_type[0x1]; 2266 u8 selected_fields[0x1e]; 2267 }; 2268 2269 enum { 2270 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2271 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2272 }; 2273 2274 enum { 2275 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2276 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2277 }; 2278 2279 enum { 2280 MLX5_RX_HASH_FN_NONE = 0x0, 2281 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2282 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2283 }; 2284 2285 enum { 2286 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2287 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2288 }; 2289 2290 enum { 2291 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0, 2292 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1, 2293 }; 2294 2295 struct mlx5_ifc_tirc_bits { 2296 u8 reserved_at_0[0x20]; 2297 u8 disp_type[0x4]; 2298 u8 reserved_at_24[0x1c]; 2299 u8 reserved_at_40[0x40]; 2300 u8 reserved_at_80[0x4]; 2301 u8 lro_timeout_period_usecs[0x10]; 2302 u8 lro_enable_mask[0x4]; 2303 u8 lro_max_msg_sz[0x8]; 2304 u8 reserved_at_a0[0x40]; 2305 u8 reserved_at_e0[0x8]; 2306 u8 inline_rqn[0x18]; 2307 u8 rx_hash_symmetric[0x1]; 2308 u8 reserved_at_101[0x1]; 2309 u8 tunneled_offload_en[0x1]; 2310 u8 reserved_at_103[0x5]; 2311 u8 indirect_table[0x18]; 2312 u8 rx_hash_fn[0x4]; 2313 u8 reserved_at_124[0x2]; 2314 u8 self_lb_block[0x2]; 2315 u8 transport_domain[0x18]; 2316 u8 rx_hash_toeplitz_key[10][0x20]; 2317 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2318 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2319 u8 reserved_at_2c0[0x4c0]; 2320 }; 2321 2322 struct mlx5_ifc_create_tir_out_bits { 2323 u8 status[0x8]; 2324 u8 reserved_at_8[0x18]; 2325 u8 syndrome[0x20]; 2326 u8 reserved_at_40[0x8]; 2327 u8 tirn[0x18]; 2328 u8 reserved_at_60[0x20]; 2329 }; 2330 2331 struct mlx5_ifc_create_tir_in_bits { 2332 u8 opcode[0x10]; 2333 u8 uid[0x10]; 2334 u8 reserved_at_20[0x10]; 2335 u8 op_mod[0x10]; 2336 u8 reserved_at_40[0xc0]; 2337 struct mlx5_ifc_tirc_bits ctx; 2338 }; 2339 2340 enum { 2341 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0, 2342 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1, 2343 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2, 2344 /* bit 3 - tunneled_offload_en modify not supported. */ 2345 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4, 2346 }; 2347 2348 struct mlx5_ifc_modify_tir_out_bits { 2349 u8 status[0x8]; 2350 u8 reserved_at_8[0x18]; 2351 u8 syndrome[0x20]; 2352 u8 reserved_at_40[0x40]; 2353 }; 2354 2355 struct mlx5_ifc_modify_tir_in_bits { 2356 u8 opcode[0x10]; 2357 u8 uid[0x10]; 2358 u8 reserved_at_20[0x10]; 2359 u8 op_mod[0x10]; 2360 u8 reserved_at_40[0x8]; 2361 u8 tirn[0x18]; 2362 u8 reserved_at_60[0x20]; 2363 u8 modify_bitmask[0x40]; 2364 u8 reserved_at_c0[0x40]; 2365 struct mlx5_ifc_tirc_bits ctx; 2366 }; 2367 2368 enum { 2369 MLX5_INLINE_Q_TYPE_RQ = 0x0, 2370 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1, 2371 }; 2372 2373 struct mlx5_ifc_rq_num_bits { 2374 u8 reserved_at_0[0x8]; 2375 u8 rq_num[0x18]; 2376 }; 2377 2378 struct mlx5_ifc_rqtc_bits { 2379 u8 reserved_at_0[0xa5]; 2380 u8 list_q_type[0x3]; 2381 u8 reserved_at_a8[0x8]; 2382 u8 rqt_max_size[0x10]; 2383 u8 reserved_at_c0[0x10]; 2384 u8 rqt_actual_size[0x10]; 2385 u8 reserved_at_e0[0x6a0]; 2386 struct mlx5_ifc_rq_num_bits rq_num[]; 2387 }; 2388 2389 struct mlx5_ifc_create_rqt_out_bits { 2390 u8 status[0x8]; 2391 u8 reserved_at_8[0x18]; 2392 u8 syndrome[0x20]; 2393 u8 reserved_at_40[0x8]; 2394 u8 rqtn[0x18]; 2395 u8 reserved_at_60[0x20]; 2396 }; 2397 2398 #ifdef PEDANTIC 2399 #pragma GCC diagnostic ignored "-Wpedantic" 2400 #endif 2401 struct mlx5_ifc_create_rqt_in_bits { 2402 u8 opcode[0x10]; 2403 u8 uid[0x10]; 2404 u8 reserved_at_20[0x10]; 2405 u8 op_mod[0x10]; 2406 u8 reserved_at_40[0xc0]; 2407 struct mlx5_ifc_rqtc_bits rqt_context; 2408 }; 2409 2410 struct mlx5_ifc_modify_rqt_in_bits { 2411 u8 opcode[0x10]; 2412 u8 uid[0x10]; 2413 u8 reserved_at_20[0x10]; 2414 u8 op_mod[0x10]; 2415 u8 reserved_at_40[0x8]; 2416 u8 rqtn[0x18]; 2417 u8 reserved_at_60[0x20]; 2418 u8 modify_bitmask[0x40]; 2419 u8 reserved_at_c0[0x40]; 2420 struct mlx5_ifc_rqtc_bits rqt_context; 2421 }; 2422 #ifdef PEDANTIC 2423 #pragma GCC diagnostic error "-Wpedantic" 2424 #endif 2425 2426 struct mlx5_ifc_modify_rqt_out_bits { 2427 u8 status[0x8]; 2428 u8 reserved_at_8[0x18]; 2429 u8 syndrome[0x20]; 2430 u8 reserved_at_40[0x40]; 2431 }; 2432 2433 enum { 2434 MLX5_SQC_STATE_RST = 0x0, 2435 MLX5_SQC_STATE_RDY = 0x1, 2436 MLX5_SQC_STATE_ERR = 0x3, 2437 }; 2438 2439 struct mlx5_ifc_sqc_bits { 2440 u8 rlky[0x1]; 2441 u8 cd_master[0x1]; 2442 u8 fre[0x1]; 2443 u8 flush_in_error_en[0x1]; 2444 u8 allow_multi_pkt_send_wqe[0x1]; 2445 u8 min_wqe_inline_mode[0x3]; 2446 u8 state[0x4]; 2447 u8 reg_umr[0x1]; 2448 u8 allow_swp[0x1]; 2449 u8 hairpin[0x1]; 2450 u8 non_wire[0x1]; 2451 u8 static_sq_wq[0x1]; 2452 u8 reserved_at_11[0x9]; 2453 u8 ts_format[0x02]; 2454 u8 reserved_at_1c[0x4]; 2455 u8 reserved_at_20[0x8]; 2456 u8 user_index[0x18]; 2457 u8 reserved_at_40[0x8]; 2458 u8 cqn[0x18]; 2459 u8 reserved_at_60[0x8]; 2460 u8 hairpin_peer_rq[0x18]; 2461 u8 reserved_at_80[0x10]; 2462 u8 hairpin_peer_vhca[0x10]; 2463 u8 reserved_at_a0[0x50]; 2464 u8 packet_pacing_rate_limit_index[0x10]; 2465 u8 tis_lst_sz[0x10]; 2466 u8 reserved_at_110[0x10]; 2467 u8 reserved_at_120[0x40]; 2468 u8 reserved_at_160[0x8]; 2469 u8 tis_num_0[0x18]; 2470 struct mlx5_ifc_wq_bits wq; 2471 }; 2472 2473 struct mlx5_ifc_query_sq_in_bits { 2474 u8 opcode[0x10]; 2475 u8 reserved_at_10[0x10]; 2476 u8 reserved_at_20[0x10]; 2477 u8 op_mod[0x10]; 2478 u8 reserved_at_40[0x8]; 2479 u8 sqn[0x18]; 2480 u8 reserved_at_60[0x20]; 2481 }; 2482 2483 struct mlx5_ifc_modify_sq_out_bits { 2484 u8 status[0x8]; 2485 u8 reserved_at_8[0x18]; 2486 u8 syndrome[0x20]; 2487 u8 reserved_at_40[0x40]; 2488 }; 2489 2490 struct mlx5_ifc_modify_sq_in_bits { 2491 u8 opcode[0x10]; 2492 u8 uid[0x10]; 2493 u8 reserved_at_20[0x10]; 2494 u8 op_mod[0x10]; 2495 u8 sq_state[0x4]; 2496 u8 reserved_at_44[0x4]; 2497 u8 sqn[0x18]; 2498 u8 reserved_at_60[0x20]; 2499 u8 modify_bitmask[0x40]; 2500 u8 reserved_at_c0[0x40]; 2501 struct mlx5_ifc_sqc_bits ctx; 2502 }; 2503 2504 struct mlx5_ifc_create_sq_out_bits { 2505 u8 status[0x8]; 2506 u8 reserved_at_8[0x18]; 2507 u8 syndrome[0x20]; 2508 u8 reserved_at_40[0x8]; 2509 u8 sqn[0x18]; 2510 u8 reserved_at_60[0x20]; 2511 }; 2512 2513 struct mlx5_ifc_create_sq_in_bits { 2514 u8 opcode[0x10]; 2515 u8 uid[0x10]; 2516 u8 reserved_at_20[0x10]; 2517 u8 op_mod[0x10]; 2518 u8 reserved_at_40[0xc0]; 2519 struct mlx5_ifc_sqc_bits ctx; 2520 }; 2521 2522 enum { 2523 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0), 2524 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1), 2525 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2), 2526 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3), 2527 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4), 2528 }; 2529 2530 struct mlx5_ifc_flow_meter_parameters_bits { 2531 u8 valid[0x1]; 2532 u8 bucket_overflow[0x1]; 2533 u8 start_color[0x2]; 2534 u8 both_buckets_on_green[0x1]; 2535 u8 meter_mode[0x2]; 2536 u8 reserved_at_1[0x19]; 2537 u8 reserved_at_2[0x20]; 2538 u8 reserved_at_3[0x3]; 2539 u8 cbs_exponent[0x5]; 2540 u8 cbs_mantissa[0x8]; 2541 u8 reserved_at_4[0x3]; 2542 u8 cir_exponent[0x5]; 2543 u8 cir_mantissa[0x8]; 2544 u8 reserved_at_5[0x20]; 2545 u8 reserved_at_6[0x3]; 2546 u8 ebs_exponent[0x5]; 2547 u8 ebs_mantissa[0x8]; 2548 u8 reserved_at_7[0x3]; 2549 u8 eir_exponent[0x5]; 2550 u8 eir_mantissa[0x8]; 2551 u8 reserved_at_8[0x60]; 2552 }; 2553 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF) 2554 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8 2555 2556 enum { 2557 MLX5_METER_MODE_IP_LEN = 0x0, 2558 MLX5_METER_MODE_L2_LEN = 0x1, 2559 MLX5_METER_MODE_L2_IPG_LEN = 0x2, 2560 MLX5_METER_MODE_PKT = 0x3, 2561 }; 2562 2563 enum { 2564 MLX5_CQE_SIZE_64B = 0x0, 2565 MLX5_CQE_SIZE_128B = 0x1, 2566 }; 2567 2568 struct mlx5_ifc_cqc_bits { 2569 u8 status[0x4]; 2570 u8 as_notify[0x1]; 2571 u8 initiator_src_dct[0x1]; 2572 u8 dbr_umem_valid[0x1]; 2573 u8 reserved_at_7[0x1]; 2574 u8 cqe_sz[0x3]; 2575 u8 cc[0x1]; 2576 u8 reserved_at_c[0x1]; 2577 u8 scqe_break_moderation_en[0x1]; 2578 u8 oi[0x1]; 2579 u8 cq_period_mode[0x2]; 2580 u8 cqe_comp_en[0x1]; 2581 u8 mini_cqe_res_format[0x2]; 2582 u8 st[0x4]; 2583 u8 reserved_at_18[0x1]; 2584 u8 cqe_comp_layout[0x7]; 2585 u8 dbr_umem_id[0x20]; 2586 u8 reserved_at_40[0x14]; 2587 u8 page_offset[0x6]; 2588 u8 reserved_at_5a[0x2]; 2589 u8 mini_cqe_res_format_ext[0x2]; 2590 u8 cq_timestamp_format[0x2]; 2591 u8 reserved_at_60[0x3]; 2592 u8 log_cq_size[0x5]; 2593 u8 uar_page[0x18]; 2594 u8 reserved_at_80[0x4]; 2595 u8 cq_period[0xc]; 2596 u8 cq_max_count[0x10]; 2597 u8 reserved_at_a0[0x18]; 2598 u8 c_eqn[0x8]; 2599 u8 reserved_at_c0[0x3]; 2600 u8 log_page_size[0x5]; 2601 u8 reserved_at_c8[0x18]; 2602 u8 reserved_at_e0[0x20]; 2603 u8 reserved_at_100[0x8]; 2604 u8 last_notified_index[0x18]; 2605 u8 reserved_at_120[0x8]; 2606 u8 last_solicit_index[0x18]; 2607 u8 reserved_at_140[0x8]; 2608 u8 consumer_counter[0x18]; 2609 u8 reserved_at_160[0x8]; 2610 u8 producer_counter[0x18]; 2611 u8 local_partition_id[0xc]; 2612 u8 process_id[0x14]; 2613 u8 reserved_at_1A0[0x20]; 2614 u8 dbr_addr[0x40]; 2615 }; 2616 2617 struct mlx5_ifc_health_buffer_bits { 2618 u8 reserved_0[0x100]; 2619 u8 assert_existptr[0x20]; 2620 u8 assert_callra[0x20]; 2621 u8 reserved_1[0x40]; 2622 u8 fw_version[0x20]; 2623 u8 hw_id[0x20]; 2624 u8 reserved_2[0x20]; 2625 u8 irisc_index[0x8]; 2626 u8 synd[0x8]; 2627 u8 ext_synd[0x10]; 2628 }; 2629 2630 struct mlx5_ifc_initial_seg_bits { 2631 u8 fw_rev_minor[0x10]; 2632 u8 fw_rev_major[0x10]; 2633 u8 cmd_interface_rev[0x10]; 2634 u8 fw_rev_subminor[0x10]; 2635 u8 reserved_0[0x40]; 2636 u8 cmdq_phy_addr_63_32[0x20]; 2637 u8 cmdq_phy_addr_31_12[0x14]; 2638 u8 reserved_1[0x2]; 2639 u8 nic_interface[0x2]; 2640 u8 log_cmdq_size[0x4]; 2641 u8 log_cmdq_stride[0x4]; 2642 u8 command_doorbell_vector[0x20]; 2643 u8 reserved_2[0xf00]; 2644 u8 initializing[0x1]; 2645 u8 nic_interface_supported[0x7]; 2646 u8 reserved_4[0x18]; 2647 struct mlx5_ifc_health_buffer_bits health_buffer; 2648 u8 no_dram_nic_offset[0x20]; 2649 u8 reserved_5[0x6de0]; 2650 u8 internal_timer_h[0x20]; 2651 u8 internal_timer_l[0x20]; 2652 u8 reserved_6[0x20]; 2653 u8 reserved_7[0x1f]; 2654 u8 clear_int[0x1]; 2655 u8 health_syndrome[0x8]; 2656 u8 health_counter[0x18]; 2657 u8 reserved_8[0x17fc0]; 2658 }; 2659 2660 struct mlx5_ifc_create_cq_out_bits { 2661 u8 status[0x8]; 2662 u8 reserved_at_8[0x18]; 2663 u8 syndrome[0x20]; 2664 u8 reserved_at_40[0x8]; 2665 u8 cqn[0x18]; 2666 u8 reserved_at_60[0x20]; 2667 }; 2668 2669 struct mlx5_ifc_create_cq_in_bits { 2670 u8 opcode[0x10]; 2671 u8 uid[0x10]; 2672 u8 reserved_at_20[0x10]; 2673 u8 op_mod[0x10]; 2674 u8 reserved_at_40[0x40]; 2675 struct mlx5_ifc_cqc_bits cq_context; 2676 u8 cq_umem_offset[0x40]; 2677 u8 cq_umem_id[0x20]; 2678 u8 cq_umem_valid[0x1]; 2679 u8 reserved_at_2e1[0x1f]; 2680 u8 reserved_at_300[0x580]; 2681 u8 pas[]; 2682 }; 2683 2684 enum { 2685 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 2686 MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c, 2687 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, 2688 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 2689 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d, 2690 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e, 2691 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f, 2692 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, 2693 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, 2694 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, 2695 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031, 2696 }; 2697 2698 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 2699 u8 opcode[0x10]; 2700 u8 reserved_at_10[0x20]; 2701 u8 obj_type[0x10]; 2702 u8 obj_id[0x20]; 2703 u8 reserved_at_60[0x3]; 2704 u8 log_obj_range[0x5]; 2705 u8 reserved_at_58[0x18]; 2706 }; 2707 2708 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 2709 u8 status[0x8]; 2710 u8 reserved_at_8[0x18]; 2711 u8 syndrome[0x20]; 2712 u8 obj_id[0x20]; 2713 u8 reserved_at_60[0x20]; 2714 }; 2715 2716 struct mlx5_ifc_virtio_q_counters_bits { 2717 u8 modify_field_select[0x40]; 2718 u8 reserved_at_40[0x40]; 2719 u8 received_desc[0x40]; 2720 u8 completed_desc[0x40]; 2721 u8 error_cqes[0x20]; 2722 u8 bad_desc_errors[0x20]; 2723 u8 exceed_max_chain[0x20]; 2724 u8 invalid_buffer[0x20]; 2725 u8 reserved_at_180[0x50]; 2726 }; 2727 2728 struct mlx5_ifc_geneve_tlv_option_bits { 2729 u8 modify_field_select[0x40]; 2730 u8 reserved_at_40[0x18]; 2731 u8 geneve_option_fte_index[0x8]; 2732 u8 option_class[0x10]; 2733 u8 option_type[0x8]; 2734 u8 reserved_at_78[0x3]; 2735 u8 option_data_length[0x5]; 2736 u8 reserved_at_80[0x180]; 2737 }; 2738 2739 struct mlx5_ifc_create_virtio_q_counters_in_bits { 2740 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2741 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 2742 }; 2743 2744 struct mlx5_ifc_query_virtio_q_counters_out_bits { 2745 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2746 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 2747 }; 2748 2749 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 2750 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2751 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 2752 }; 2753 2754 enum { 2755 MLX5_CRYPTO_KEY_SIZE_128b = 0x0, 2756 MLX5_CRYPTO_KEY_SIZE_256b = 0x1, 2757 }; 2758 2759 enum { 2760 MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1, 2761 MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2, 2762 MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3, 2763 MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4, 2764 MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5, 2765 MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6, 2766 }; 2767 2768 struct mlx5_ifc_dek_bits { 2769 u8 modify_field_select[0x40]; 2770 u8 state[0x8]; 2771 u8 reserved_at_48[0xc]; 2772 u8 key_size[0x4]; 2773 u8 has_keytag[0x1]; 2774 u8 reserved_at_59[0x3]; 2775 u8 key_purpose[0x4]; 2776 u8 reserved_at_60[0x8]; 2777 u8 pd[0x18]; 2778 u8 reserved_at_80[0x100]; 2779 u8 opaque[0x40]; 2780 u8 reserved_at_1c0[0x40]; 2781 u8 key[0x400]; 2782 u8 reserved_at_600[0x200]; 2783 }; 2784 2785 struct mlx5_ifc_create_dek_in_bits { 2786 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2787 struct mlx5_ifc_dek_bits dek; 2788 }; 2789 2790 struct mlx5_ifc_import_kek_bits { 2791 u8 modify_field_select[0x40]; 2792 u8 state[0x8]; 2793 u8 reserved_at_48[0xc]; 2794 u8 key_size[0x4]; 2795 u8 reserved_at_58[0x1a8]; 2796 u8 key[0x400]; 2797 u8 reserved_at_600[0x200]; 2798 }; 2799 2800 struct mlx5_ifc_create_import_kek_in_bits { 2801 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2802 struct mlx5_ifc_import_kek_bits import_kek; 2803 }; 2804 2805 enum { 2806 MLX5_CREDENTIAL_ROLE_OFFICER = 0x0, 2807 MLX5_CREDENTIAL_ROLE_USER = 0x1, 2808 }; 2809 2810 struct mlx5_ifc_credential_bits { 2811 u8 modify_field_select[0x40]; 2812 u8 state[0x8]; 2813 u8 reserved_at_48[0x10]; 2814 u8 credential_role[0x8]; 2815 u8 reserved_at_60[0x1a0]; 2816 u8 credential[0x180]; 2817 u8 reserved_at_380[0x480]; 2818 }; 2819 2820 struct mlx5_ifc_create_credential_in_bits { 2821 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2822 struct mlx5_ifc_credential_bits credential; 2823 }; 2824 2825 struct mlx5_ifc_crypto_login_bits { 2826 u8 modify_field_select[0x40]; 2827 u8 reserved_at_40[0x48]; 2828 u8 credential_pointer[0x18]; 2829 u8 reserved_at_a0[0x8]; 2830 u8 session_import_kek_ptr[0x18]; 2831 u8 reserved_at_c0[0x140]; 2832 u8 credential[0x180]; 2833 u8 reserved_at_380[0x480]; 2834 }; 2835 2836 struct mlx5_ifc_create_crypto_login_in_bits { 2837 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2838 struct mlx5_ifc_crypto_login_bits crypto_login; 2839 }; 2840 2841 enum { 2842 MLX5_VIRTQ_STATE_INIT = 0, 2843 MLX5_VIRTQ_STATE_RDY = 1, 2844 MLX5_VIRTQ_STATE_SUSPEND = 2, 2845 MLX5_VIRTQ_STATE_ERROR = 3, 2846 }; 2847 2848 enum { 2849 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0), 2850 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3), 2851 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4), 2852 }; 2853 2854 struct mlx5_ifc_virtio_q_bits { 2855 u8 virtio_q_type[0x8]; 2856 u8 reserved_at_8[0x5]; 2857 u8 event_mode[0x3]; 2858 u8 queue_index[0x10]; 2859 u8 full_emulation[0x1]; 2860 u8 virtio_version_1_0[0x1]; 2861 u8 reserved_at_22[0x2]; 2862 u8 offload_type[0x4]; 2863 u8 event_qpn_or_msix[0x18]; 2864 u8 doorbell_stride_idx[0x10]; 2865 u8 queue_size[0x10]; 2866 u8 device_emulation_id[0x20]; 2867 u8 desc_addr[0x40]; 2868 u8 used_addr[0x40]; 2869 u8 available_addr[0x40]; 2870 u8 virtio_q_mkey[0x20]; 2871 u8 reserved_at_160[0x18]; 2872 u8 error_type[0x8]; 2873 u8 umem_1_id[0x20]; 2874 u8 umem_1_size[0x20]; 2875 u8 umem_1_offset[0x40]; 2876 u8 umem_2_id[0x20]; 2877 u8 umem_2_size[0x20]; 2878 u8 umem_2_offset[0x40]; 2879 u8 umem_3_id[0x20]; 2880 u8 umem_3_size[0x20]; 2881 u8 umem_3_offset[0x40]; 2882 u8 counter_set_id[0x20]; 2883 u8 reserved_at_320[0x8]; 2884 u8 pd[0x18]; 2885 u8 reserved_at_340[0x2]; 2886 u8 queue_period_mode[0x2]; 2887 u8 queue_period_us[0xc]; 2888 u8 queue_max_count[0x10]; 2889 u8 reserved_at_360[0xa0]; 2890 }; 2891 2892 struct mlx5_ifc_virtio_net_q_bits { 2893 u8 modify_field_select[0x40]; 2894 u8 reserved_at_40[0x40]; 2895 u8 tso_ipv4[0x1]; 2896 u8 tso_ipv6[0x1]; 2897 u8 tx_csum[0x1]; 2898 u8 rx_csum[0x1]; 2899 u8 reserved_at_84[0x6]; 2900 u8 dirty_bitmap_dump_enable[0x1]; 2901 u8 vhost_log_page[0x5]; 2902 u8 reserved_at_90[0xc]; 2903 u8 state[0x4]; 2904 u8 reserved_at_a0[0x8]; 2905 u8 tisn_or_qpn[0x18]; 2906 u8 dirty_bitmap_mkey[0x20]; 2907 u8 dirty_bitmap_size[0x20]; 2908 u8 dirty_bitmap_addr[0x40]; 2909 u8 hw_available_index[0x10]; 2910 u8 hw_used_index[0x10]; 2911 u8 reserved_at_160[0xa0]; 2912 struct mlx5_ifc_virtio_q_bits virtio_q_context; 2913 }; 2914 2915 struct mlx5_ifc_create_virtq_in_bits { 2916 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2917 struct mlx5_ifc_virtio_net_q_bits virtq; 2918 }; 2919 2920 struct mlx5_ifc_query_virtq_out_bits { 2921 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2922 struct mlx5_ifc_virtio_net_q_bits virtq; 2923 }; 2924 2925 struct mlx5_ifc_flow_hit_aso_bits { 2926 u8 modify_field_select[0x40]; 2927 u8 reserved_at_40[0x48]; 2928 u8 access_pd[0x18]; 2929 u8 reserved_at_a0[0x160]; 2930 u8 flag[0x200]; 2931 }; 2932 2933 struct mlx5_ifc_create_flow_hit_aso_in_bits { 2934 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2935 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso; 2936 }; 2937 2938 struct mlx5_ifc_flow_meter_aso_bits { 2939 u8 modify_field_select[0x40]; 2940 u8 reserved_at_40[0x48]; 2941 u8 access_pd[0x18]; 2942 u8 reserved_at_a0[0x160]; 2943 u8 parameters[0x200]; 2944 }; 2945 2946 struct mlx5_ifc_create_flow_meter_aso_in_bits { 2947 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2948 struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso; 2949 }; 2950 2951 struct mlx5_ifc_tcp_window_params_bits { 2952 u8 max_ack[0x20]; 2953 u8 max_win[0x20]; 2954 u8 reply_end[0x20]; 2955 u8 sent_end[0x20]; 2956 }; 2957 2958 struct mlx5_ifc_conn_track_aso_bits { 2959 struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */ 2960 struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */ 2961 u8 last_end[0x20]; /* End of DW8. */ 2962 u8 last_ack[0x20]; /* End of DW9. */ 2963 u8 last_seq[0x20]; /* End of DW10. */ 2964 u8 last_win[0x10]; 2965 u8 reserved_at_170[0xa]; 2966 u8 last_dir[0x1]; 2967 u8 last_index[0x5]; /* End of DW11. */ 2968 u8 reserved_at_180[0x40]; /* End of DW13. */ 2969 u8 reply_direction_tcp_scale[0x4]; 2970 u8 reply_direction_tcp_close_initiated[0x1]; 2971 u8 reply_direction_tcp_liberal_enabled[0x1]; 2972 u8 reply_direction_tcp_data_unacked[0x1]; 2973 u8 reply_direction_tcp_max_ack[0x1]; 2974 u8 reserved_at_1c8[0x8]; 2975 u8 original_direction_tcp_scale[0x4]; 2976 u8 original_direction_tcp_close_initiated[0x1]; 2977 u8 original_direction_tcp_liberal_enabled[0x1]; 2978 u8 original_direction_tcp_data_unacked[0x1]; 2979 u8 original_direction_tcp_max_ack[0x1]; 2980 u8 reserved_at_1d8[0x8]; /* End of DW14. */ 2981 u8 valid[0x1]; 2982 u8 state[0x3]; 2983 u8 freeze_track[0x1]; 2984 u8 reserved_at_1e5[0xb]; 2985 u8 reserved_at_1f0[0x1]; 2986 u8 connection_assured[0x1]; 2987 u8 sack_permitted[0x1]; 2988 u8 challenged_acked[0x1]; 2989 u8 heartbeat[0x1]; 2990 u8 max_ack_window[0x3]; 2991 u8 reserved_at_1f8[0x1]; 2992 u8 retransmission_counter[0x3]; 2993 u8 retranmission_limit_exceeded[0x1]; 2994 u8 retranmission_limit[0x3]; /* End of DW15. */ 2995 }; 2996 2997 struct mlx5_ifc_conn_track_offload_bits { 2998 u8 modify_field_select[0x40]; 2999 u8 reserved_at_40[0x40]; 3000 u8 reserved_at_80[0x8]; 3001 u8 conn_track_aso_access_pd[0x18]; 3002 u8 reserved_at_a0[0x160]; 3003 struct mlx5_ifc_conn_track_aso_bits conn_track_aso; 3004 }; 3005 3006 struct mlx5_ifc_create_conn_track_aso_in_bits { 3007 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3008 struct mlx5_ifc_conn_track_offload_bits conn_track_offload; 3009 }; 3010 3011 enum mlx5_access_aso_opc_mod { 3012 ASO_OPC_MOD_IPSEC = 0x0, 3013 ASO_OPC_MOD_CONNECTION_TRACKING = 0x1, 3014 ASO_OPC_MOD_POLICER = 0x2, 3015 ASO_OPC_MOD_RACE_AVOIDANCE = 0x3, 3016 ASO_OPC_MOD_FLOW_HIT = 0x4, 3017 }; 3018 3019 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30 3020 3021 enum mlx5_aso_data_mask_mode { 3022 BITWISE_64BIT = 0x0, 3023 BYTEWISE_64BYTE = 0x1, 3024 CALCULATED_64BYTE = 0x2, 3025 }; 3026 3027 #define ASO_CSEG_COND_0_OPER_OFFSET 20 3028 #define ASO_CSEG_COND_1_OPER_OFFSET 16 3029 3030 enum mlx5_aso_pre_cond_op { 3031 ASO_OP_ALWAYS_FALSE = 0x0, 3032 ASO_OP_ALWAYS_TRUE = 0x1, 3033 ASO_OP_EQUAL = 0x2, 3034 ASO_OP_NOT_EQUAL = 0x3, 3035 ASO_OP_GREATER_OR_EQUAL = 0x4, 3036 ASO_OP_LESSER_OR_EQUAL = 0x5, 3037 ASO_OP_LESSER = 0x6, 3038 ASO_OP_GREATER = 0x7, 3039 ASO_OP_CYCLIC_GREATER = 0x8, 3040 ASO_OP_CYCLIC_LESSER = 0x9, 3041 }; 3042 3043 #define ASO_CSEG_COND_OPER_OFFSET 6 3044 3045 enum mlx5_aso_op { 3046 ASO_OPER_LOGICAL_AND = 0x0, 3047 ASO_OPER_LOGICAL_OR = 0x1, 3048 }; 3049 3050 /* ASO WQE CTRL segment. */ 3051 struct mlx5_aso_cseg { 3052 uint32_t va_h; 3053 uint32_t va_l_r; 3054 uint32_t lkey; 3055 uint32_t operand_masks; 3056 uint32_t condition_0_data; 3057 uint32_t condition_0_mask; 3058 uint32_t condition_1_data; 3059 uint32_t condition_1_mask; 3060 uint64_t bitwise_data; 3061 uint64_t data_mask; 3062 } __rte_packed; 3063 3064 /* A meter data segment - 2 per ASO WQE. */ 3065 struct mlx5_aso_mtr_dseg { 3066 uint32_t v_bo_sc_bbog_mm; 3067 /* 3068 * bit 31: valid, 30: bucket overflow, 28-29: start color, 3069 * 27: both buckets on green, 24-25: meter mode. 3070 */ 3071 uint32_t reserved; 3072 uint32_t cbs_cir; 3073 /* 3074 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 3075 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 3076 */ 3077 uint32_t c_tokens; 3078 uint32_t ebs_eir; 3079 /* 3080 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 3081 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 3082 */ 3083 uint32_t e_tokens; 3084 uint64_t timestamp; 3085 } __rte_packed; 3086 3087 #define ASO_DSEG_VALID_OFFSET 31 3088 #define ASO_DSEG_BO_OFFSET 30 3089 #define ASO_DSEG_SC_OFFSET 28 3090 #define ASO_DSEG_BBOG_OFFSET 27 3091 #define ASO_DSEG_MTR_MODE 24 3092 #define ASO_DSEG_CBS_EXP_OFFSET 24 3093 #define ASO_DSEG_CBS_MAN_OFFSET 16 3094 #define ASO_DSEG_XIR_EXP_MASK 0x1F 3095 #define ASO_DSEG_XIR_EXP_OFFSET 8 3096 #define ASO_DSEG_EBS_EXP_OFFSET 24 3097 #define ASO_DSEG_EBS_MAN_OFFSET 16 3098 #define ASO_DSEG_EXP_MASK 0x1F 3099 #define ASO_DSEG_MAN_MASK 0xFF 3100 3101 #define MLX5_ASO_WQE_DSEG_SIZE 0x40 3102 #define MLX5_ASO_METERS_PER_WQE 2 3103 #define MLX5_ASO_MTRS_PER_POOL 128 3104 3105 /* ASO WQE data segment. */ 3106 struct mlx5_aso_dseg { 3107 union { 3108 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE]; 3109 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE]; 3110 }; 3111 } __rte_packed; 3112 3113 /* ASO WQE. */ 3114 struct mlx5_aso_wqe { 3115 struct mlx5_wqe_cseg general_cseg; 3116 struct mlx5_aso_cseg aso_cseg; 3117 struct mlx5_aso_dseg aso_dseg; 3118 } __rte_packed; 3119 3120 enum { 3121 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, 3122 }; 3123 3124 enum { 3125 MLX5_QP_ST_RC = 0x0, 3126 }; 3127 3128 enum { 3129 MLX5_QP_PM_MIGRATED = 0x3, 3130 }; 3131 3132 enum { 3133 MLX5_NON_ZERO_RQ = 0x0, 3134 MLX5_SRQ_RQ = 0x1, 3135 MLX5_CRQ_RQ = 0x2, 3136 MLX5_ZERO_LEN_RQ = 0x3, 3137 }; 3138 3139 struct mlx5_ifc_ads_bits { 3140 u8 fl[0x1]; 3141 u8 free_ar[0x1]; 3142 u8 reserved_at_2[0xe]; 3143 u8 pkey_index[0x10]; 3144 u8 reserved_at_20[0x8]; 3145 u8 grh[0x1]; 3146 u8 mlid[0x7]; 3147 u8 rlid[0x10]; 3148 u8 ack_timeout[0x5]; 3149 u8 reserved_at_45[0x3]; 3150 u8 src_addr_index[0x8]; 3151 u8 reserved_at_50[0x4]; 3152 u8 stat_rate[0x4]; 3153 u8 hop_limit[0x8]; 3154 u8 reserved_at_60[0x4]; 3155 u8 tclass[0x8]; 3156 u8 flow_label[0x14]; 3157 u8 rgid_rip[16][0x8]; 3158 u8 reserved_at_100[0x4]; 3159 u8 f_dscp[0x1]; 3160 u8 f_ecn[0x1]; 3161 u8 reserved_at_106[0x1]; 3162 u8 f_eth_prio[0x1]; 3163 u8 ecn[0x2]; 3164 u8 dscp[0x6]; 3165 u8 udp_sport[0x10]; 3166 u8 dei_cfi[0x1]; 3167 u8 eth_prio[0x3]; 3168 u8 sl[0x4]; 3169 u8 vhca_port_num[0x8]; 3170 u8 rmac_47_32[0x10]; 3171 u8 rmac_31_0[0x20]; 3172 }; 3173 3174 struct mlx5_ifc_qpc_bits { 3175 u8 state[0x4]; 3176 u8 lag_tx_port_affinity[0x4]; 3177 u8 st[0x8]; 3178 u8 reserved_at_10[0x3]; 3179 u8 pm_state[0x2]; 3180 u8 reserved_at_15[0x1]; 3181 u8 req_e2e_credit_mode[0x2]; 3182 u8 offload_type[0x4]; 3183 u8 end_padding_mode[0x2]; 3184 u8 reserved_at_1e[0x2]; 3185 u8 wq_signature[0x1]; 3186 u8 block_lb_mc[0x1]; 3187 u8 atomic_like_write_en[0x1]; 3188 u8 latency_sensitive[0x1]; 3189 u8 reserved_at_24[0x1]; 3190 u8 drain_sigerr[0x1]; 3191 u8 reserved_at_26[0x2]; 3192 u8 pd[0x18]; 3193 u8 mtu[0x3]; 3194 u8 log_msg_max[0x5]; 3195 u8 reserved_at_48[0x1]; 3196 u8 log_rq_size[0x4]; 3197 u8 log_rq_stride[0x3]; 3198 u8 no_sq[0x1]; 3199 u8 log_sq_size[0x4]; 3200 u8 reserved_at_55[0x3]; 3201 u8 ts_format[0x2]; 3202 u8 reserved_at_5a[0x1]; 3203 u8 rlky[0x1]; 3204 u8 ulp_stateless_offload_mode[0x4]; 3205 u8 counter_set_id[0x8]; 3206 u8 uar_page[0x18]; 3207 u8 reserved_at_80[0x8]; 3208 u8 user_index[0x18]; 3209 u8 reserved_at_a0[0x3]; 3210 u8 log_page_size[0x5]; 3211 u8 remote_qpn[0x18]; 3212 struct mlx5_ifc_ads_bits primary_address_path; 3213 struct mlx5_ifc_ads_bits secondary_address_path; 3214 u8 log_ack_req_freq[0x4]; 3215 u8 reserved_at_384[0x4]; 3216 u8 log_sra_max[0x3]; 3217 u8 reserved_at_38b[0x2]; 3218 u8 retry_count[0x3]; 3219 u8 rnr_retry[0x3]; 3220 u8 reserved_at_393[0x1]; 3221 u8 fre[0x1]; 3222 u8 cur_rnr_retry[0x3]; 3223 u8 cur_retry_count[0x3]; 3224 u8 reserved_at_39b[0x5]; 3225 u8 reserved_at_3a0[0x20]; 3226 u8 reserved_at_3c0[0x8]; 3227 u8 next_send_psn[0x18]; 3228 u8 reserved_at_3e0[0x8]; 3229 u8 cqn_snd[0x18]; 3230 u8 reserved_at_400[0x8]; 3231 u8 deth_sqpn[0x18]; 3232 u8 reserved_at_420[0x20]; 3233 u8 reserved_at_440[0x8]; 3234 u8 last_acked_psn[0x18]; 3235 u8 reserved_at_460[0x8]; 3236 u8 ssn[0x18]; 3237 u8 reserved_at_480[0x8]; 3238 u8 log_rra_max[0x3]; 3239 u8 reserved_at_48b[0x1]; 3240 u8 atomic_mode[0x4]; 3241 u8 rre[0x1]; 3242 u8 rwe[0x1]; 3243 u8 rae[0x1]; 3244 u8 reserved_at_493[0x1]; 3245 u8 page_offset[0x6]; 3246 u8 reserved_at_49a[0x3]; 3247 u8 cd_slave_receive[0x1]; 3248 u8 cd_slave_send[0x1]; 3249 u8 cd_master[0x1]; 3250 u8 reserved_at_4a0[0x3]; 3251 u8 min_rnr_nak[0x5]; 3252 u8 next_rcv_psn[0x18]; 3253 u8 reserved_at_4c0[0x8]; 3254 u8 xrcd[0x18]; 3255 u8 reserved_at_4e0[0x8]; 3256 u8 cqn_rcv[0x18]; 3257 u8 dbr_addr[0x40]; 3258 u8 q_key[0x20]; 3259 u8 reserved_at_560[0x5]; 3260 u8 rq_type[0x3]; 3261 u8 srqn_rmpn_xrqn[0x18]; 3262 u8 reserved_at_580[0x8]; 3263 u8 rmsn[0x18]; 3264 u8 hw_sq_wqebb_counter[0x10]; 3265 u8 sw_sq_wqebb_counter[0x10]; 3266 u8 hw_rq_counter[0x20]; 3267 u8 sw_rq_counter[0x20]; 3268 u8 reserved_at_600[0x20]; 3269 u8 reserved_at_620[0xf]; 3270 u8 cgs[0x1]; 3271 u8 cs_req[0x8]; 3272 u8 cs_res[0x8]; 3273 u8 dc_access_key[0x40]; 3274 u8 reserved_at_680[0x3]; 3275 u8 dbr_umem_valid[0x1]; 3276 u8 reserved_at_684[0x9c]; 3277 u8 dbr_umem_id[0x20]; 3278 }; 3279 3280 struct mlx5_ifc_create_qp_out_bits { 3281 u8 status[0x8]; 3282 u8 reserved_at_8[0x18]; 3283 u8 syndrome[0x20]; 3284 u8 reserved_at_40[0x8]; 3285 u8 qpn[0x18]; 3286 u8 reserved_at_60[0x20]; 3287 }; 3288 3289 struct mlx5_ifc_qpc_extension_bits { 3290 u8 reserved_at_0[0x2]; 3291 u8 mmo[0x1]; 3292 u8 reserved_at_3[0x5fd]; 3293 }; 3294 3295 #ifdef PEDANTIC 3296 #pragma GCC diagnostic ignored "-Wpedantic" 3297 #endif 3298 struct mlx5_ifc_qpc_pas_list_bits { 3299 u8 pas[0][0x40]; 3300 }; 3301 3302 #ifdef PEDANTIC 3303 #pragma GCC diagnostic ignored "-Wpedantic" 3304 #endif 3305 struct mlx5_ifc_qpc_extension_and_pas_list_bits { 3306 struct mlx5_ifc_qpc_extension_bits qpc_data_extension; 3307 u8 pas[0][0x40]; 3308 }; 3309 3310 3311 #ifdef PEDANTIC 3312 #pragma GCC diagnostic ignored "-Wpedantic" 3313 #endif 3314 struct mlx5_ifc_create_qp_in_bits { 3315 u8 opcode[0x10]; 3316 u8 uid[0x10]; 3317 u8 reserved_at_20[0x10]; 3318 u8 op_mod[0x10]; 3319 u8 qpc_ext[0x1]; 3320 u8 reserved_at_41[0x3f]; 3321 u8 opt_param_mask[0x20]; 3322 u8 reserved_at_a0[0x20]; 3323 struct mlx5_ifc_qpc_bits qpc; 3324 u8 wq_umem_offset[0x40]; 3325 u8 wq_umem_id[0x20]; 3326 u8 wq_umem_valid[0x1]; 3327 u8 reserved_at_861[0x1f]; 3328 union { 3329 struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list; 3330 struct mlx5_ifc_qpc_extension_and_pas_list_bits 3331 qpc_extension_and_pas_list; 3332 }; 3333 }; 3334 #ifdef PEDANTIC 3335 #pragma GCC diagnostic error "-Wpedantic" 3336 #endif 3337 3338 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3339 u8 status[0x8]; 3340 u8 reserved_at_8[0x18]; 3341 u8 syndrome[0x20]; 3342 u8 reserved_at_40[0x40]; 3343 }; 3344 3345 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3346 u8 opcode[0x10]; 3347 u8 uid[0x10]; 3348 u8 reserved_at_20[0x10]; 3349 u8 op_mod[0x10]; 3350 u8 reserved_at_40[0x8]; 3351 u8 qpn[0x18]; 3352 u8 reserved_at_60[0x20]; 3353 u8 opt_param_mask[0x20]; 3354 u8 reserved_at_a0[0x20]; 3355 struct mlx5_ifc_qpc_bits qpc; 3356 u8 reserved_at_800[0x80]; 3357 }; 3358 3359 struct mlx5_ifc_sqd2rts_qp_out_bits { 3360 u8 status[0x8]; 3361 u8 reserved_at_8[0x18]; 3362 u8 syndrome[0x20]; 3363 u8 reserved_at_40[0x40]; 3364 }; 3365 3366 struct mlx5_ifc_sqd2rts_qp_in_bits { 3367 u8 opcode[0x10]; 3368 u8 uid[0x10]; 3369 u8 reserved_at_20[0x10]; 3370 u8 op_mod[0x10]; 3371 u8 reserved_at_40[0x8]; 3372 u8 qpn[0x18]; 3373 u8 reserved_at_60[0x20]; 3374 u8 opt_param_mask[0x20]; 3375 u8 reserved_at_a0[0x20]; 3376 struct mlx5_ifc_qpc_bits qpc; 3377 u8 reserved_at_800[0x80]; 3378 }; 3379 3380 struct mlx5_ifc_rts2rts_qp_out_bits { 3381 u8 status[0x8]; 3382 u8 reserved_at_8[0x18]; 3383 u8 syndrome[0x20]; 3384 u8 reserved_at_40[0x40]; 3385 }; 3386 3387 struct mlx5_ifc_rts2rts_qp_in_bits { 3388 u8 opcode[0x10]; 3389 u8 uid[0x10]; 3390 u8 reserved_at_20[0x10]; 3391 u8 op_mod[0x10]; 3392 u8 reserved_at_40[0x8]; 3393 u8 qpn[0x18]; 3394 u8 reserved_at_60[0x20]; 3395 u8 opt_param_mask[0x20]; 3396 u8 reserved_at_a0[0x20]; 3397 struct mlx5_ifc_qpc_bits qpc; 3398 u8 reserved_at_800[0x80]; 3399 }; 3400 3401 struct mlx5_ifc_rtr2rts_qp_out_bits { 3402 u8 status[0x8]; 3403 u8 reserved_at_8[0x18]; 3404 u8 syndrome[0x20]; 3405 u8 reserved_at_40[0x40]; 3406 }; 3407 3408 struct mlx5_ifc_rtr2rts_qp_in_bits { 3409 u8 opcode[0x10]; 3410 u8 uid[0x10]; 3411 u8 reserved_at_20[0x10]; 3412 u8 op_mod[0x10]; 3413 u8 reserved_at_40[0x8]; 3414 u8 qpn[0x18]; 3415 u8 reserved_at_60[0x20]; 3416 u8 opt_param_mask[0x20]; 3417 u8 reserved_at_a0[0x20]; 3418 struct mlx5_ifc_qpc_bits qpc; 3419 u8 reserved_at_800[0x80]; 3420 }; 3421 3422 struct mlx5_ifc_rst2init_qp_out_bits { 3423 u8 status[0x8]; 3424 u8 reserved_at_8[0x18]; 3425 u8 syndrome[0x20]; 3426 u8 reserved_at_40[0x40]; 3427 }; 3428 3429 struct mlx5_ifc_rst2init_qp_in_bits { 3430 u8 opcode[0x10]; 3431 u8 uid[0x10]; 3432 u8 reserved_at_20[0x10]; 3433 u8 op_mod[0x10]; 3434 u8 reserved_at_40[0x8]; 3435 u8 qpn[0x18]; 3436 u8 reserved_at_60[0x20]; 3437 u8 opt_param_mask[0x20]; 3438 u8 reserved_at_a0[0x20]; 3439 struct mlx5_ifc_qpc_bits qpc; 3440 u8 reserved_at_800[0x80]; 3441 }; 3442 3443 struct mlx5_ifc_init2rtr_qp_out_bits { 3444 u8 status[0x8]; 3445 u8 reserved_at_8[0x18]; 3446 u8 syndrome[0x20]; 3447 u8 reserved_at_40[0x40]; 3448 }; 3449 3450 struct mlx5_ifc_init2rtr_qp_in_bits { 3451 u8 opcode[0x10]; 3452 u8 uid[0x10]; 3453 u8 reserved_at_20[0x10]; 3454 u8 op_mod[0x10]; 3455 u8 reserved_at_40[0x8]; 3456 u8 qpn[0x18]; 3457 u8 reserved_at_60[0x20]; 3458 u8 opt_param_mask[0x20]; 3459 u8 reserved_at_a0[0x20]; 3460 struct mlx5_ifc_qpc_bits qpc; 3461 u8 reserved_at_800[0x80]; 3462 }; 3463 3464 struct mlx5_ifc_init2init_qp_out_bits { 3465 u8 status[0x8]; 3466 u8 reserved_at_8[0x18]; 3467 u8 syndrome[0x20]; 3468 u8 reserved_at_40[0x40]; 3469 }; 3470 3471 struct mlx5_ifc_init2init_qp_in_bits { 3472 u8 opcode[0x10]; 3473 u8 uid[0x10]; 3474 u8 reserved_at_20[0x10]; 3475 u8 op_mod[0x10]; 3476 u8 reserved_at_40[0x8]; 3477 u8 qpn[0x18]; 3478 u8 reserved_at_60[0x20]; 3479 u8 opt_param_mask[0x20]; 3480 u8 reserved_at_a0[0x20]; 3481 struct mlx5_ifc_qpc_bits qpc; 3482 u8 reserved_at_800[0x80]; 3483 }; 3484 3485 struct mlx5_ifc_dealloc_pd_out_bits { 3486 u8 status[0x8]; 3487 u8 reserved_0[0x18]; 3488 u8 syndrome[0x20]; 3489 u8 reserved_1[0x40]; 3490 }; 3491 3492 struct mlx5_ifc_dealloc_pd_in_bits { 3493 u8 opcode[0x10]; 3494 u8 reserved_0[0x10]; 3495 u8 reserved_1[0x10]; 3496 u8 op_mod[0x10]; 3497 u8 reserved_2[0x8]; 3498 u8 pd[0x18]; 3499 u8 reserved_3[0x20]; 3500 }; 3501 3502 struct mlx5_ifc_alloc_pd_out_bits { 3503 u8 status[0x8]; 3504 u8 reserved_0[0x18]; 3505 u8 syndrome[0x20]; 3506 u8 reserved_1[0x8]; 3507 u8 pd[0x18]; 3508 u8 reserved_2[0x20]; 3509 }; 3510 3511 struct mlx5_ifc_alloc_pd_in_bits { 3512 u8 opcode[0x10]; 3513 u8 reserved_0[0x10]; 3514 u8 reserved_1[0x10]; 3515 u8 op_mod[0x10]; 3516 u8 reserved_2[0x40]; 3517 }; 3518 3519 #ifdef PEDANTIC 3520 #pragma GCC diagnostic ignored "-Wpedantic" 3521 #endif 3522 struct mlx5_ifc_query_qp_out_bits { 3523 u8 status[0x8]; 3524 u8 reserved_at_8[0x18]; 3525 u8 syndrome[0x20]; 3526 u8 reserved_at_40[0x40]; 3527 u8 opt_param_mask[0x20]; 3528 u8 reserved_at_a0[0x20]; 3529 struct mlx5_ifc_qpc_bits qpc; 3530 u8 reserved_at_800[0x80]; 3531 u8 pas[0][0x40]; 3532 }; 3533 #ifdef PEDANTIC 3534 #pragma GCC diagnostic error "-Wpedantic" 3535 #endif 3536 3537 struct mlx5_ifc_query_qp_in_bits { 3538 u8 opcode[0x10]; 3539 u8 reserved_at_10[0x10]; 3540 u8 reserved_at_20[0x10]; 3541 u8 op_mod[0x10]; 3542 u8 reserved_at_40[0x8]; 3543 u8 qpn[0x18]; 3544 u8 reserved_at_60[0x20]; 3545 }; 3546 3547 enum { 3548 MLX5_DATA_RATE = 0x0, 3549 MLX5_WQE_RATE = 0x1, 3550 }; 3551 3552 struct mlx5_ifc_set_pp_rate_limit_context_bits { 3553 u8 rate_limit[0x20]; 3554 u8 burst_upper_bound[0x20]; 3555 u8 reserved_at_40[0xC]; 3556 u8 rate_mode[0x4]; 3557 u8 typical_packet_size[0x10]; 3558 u8 reserved_at_60[0x120]; 3559 }; 3560 3561 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u 3562 3563 #ifdef PEDANTIC 3564 #pragma GCC diagnostic ignored "-Wpedantic" 3565 #endif 3566 struct mlx5_ifc_access_register_out_bits { 3567 u8 status[0x8]; 3568 u8 reserved_at_8[0x18]; 3569 u8 syndrome[0x20]; 3570 u8 reserved_at_40[0x40]; 3571 u8 register_data[0][0x20]; 3572 }; 3573 3574 struct mlx5_ifc_access_register_in_bits { 3575 u8 opcode[0x10]; 3576 u8 reserved_at_10[0x10]; 3577 u8 reserved_at_20[0x10]; 3578 u8 op_mod[0x10]; 3579 u8 reserved_at_40[0x10]; 3580 u8 register_id[0x10]; 3581 u8 argument[0x20]; 3582 u8 register_data[0][0x20]; 3583 }; 3584 #ifdef PEDANTIC 3585 #pragma GCC diagnostic error "-Wpedantic" 3586 #endif 3587 3588 enum { 3589 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 3590 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 3591 }; 3592 3593 enum { 3594 MLX5_REGISTER_ID_MTUTC = 0x9055, 3595 MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002, 3596 MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, 3597 MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, 3598 MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, 3599 }; 3600 3601 struct mlx5_ifc_register_mtutc_bits { 3602 u8 time_stamp_mode[0x2]; 3603 u8 time_stamp_state[0x2]; 3604 u8 reserved_at_4[0x18]; 3605 u8 operation[0x4]; 3606 u8 freq_adjustment[0x20]; 3607 u8 reserved_at_40[0x40]; 3608 u8 utc_sec[0x20]; 3609 u8 utc_nsec[0x20]; 3610 u8 time_adjustment[0x20]; 3611 }; 3612 3613 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 3614 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 3615 3616 struct mlx5_ifc_crypto_operational_register_bits { 3617 u8 wrapped_crypto_operational[0x1]; 3618 u8 reserved_at_1[0x1b]; 3619 u8 kek_size[0x4]; 3620 u8 reserved_at_20[0x20]; 3621 u8 credential[0x140]; 3622 u8 kek[0x100]; 3623 u8 reserved_at_280[0x180]; 3624 }; 3625 3626 struct mlx5_ifc_crypto_commissioning_register_bits { 3627 u8 token[0x1]; /* TODO: add size after PRM update */ 3628 }; 3629 3630 struct mlx5_ifc_import_kek_handle_register_bits { 3631 struct mlx5_ifc_crypto_login_bits crypto_login_object; 3632 struct mlx5_ifc_import_kek_bits import_kek_object; 3633 u8 reserved_at_200[0x4]; 3634 u8 write_operation[0x4]; 3635 u8 import_kek_id[0x18]; 3636 u8 reserved_at_220[0xe0]; 3637 }; 3638 3639 struct mlx5_ifc_credential_handle_register_bits { 3640 struct mlx5_ifc_crypto_login_bits crypto_login_object; 3641 struct mlx5_ifc_credential_bits credential_object; 3642 u8 reserved_at_200[0x4]; 3643 u8 write_operation[0x4]; 3644 u8 credential_id[0x18]; 3645 u8 reserved_at_220[0xe0]; 3646 }; 3647 3648 enum { 3649 MLX5_REGISTER_ADD_OPERATION = 0x1, 3650 MLX5_REGISTER_DELETE_OPERATION = 0x2, 3651 }; 3652 3653 struct mlx5_ifc_parse_graph_arc_bits { 3654 u8 start_inner_tunnel[0x1]; 3655 u8 reserved_at_1[0x7]; 3656 u8 arc_parse_graph_node[0x8]; 3657 u8 compare_condition_value[0x10]; 3658 u8 parse_graph_node_handle[0x20]; 3659 u8 reserved_at_40[0x40]; 3660 }; 3661 3662 struct mlx5_ifc_parse_graph_flow_match_sample_bits { 3663 u8 flow_match_sample_en[0x1]; 3664 u8 reserved_at_1[0x3]; 3665 u8 flow_match_sample_offset_mode[0x4]; 3666 u8 reserved_at_5[0x8]; 3667 u8 flow_match_sample_field_offset[0x10]; 3668 u8 reserved_at_32[0x4]; 3669 u8 flow_match_sample_field_offset_shift[0x4]; 3670 u8 flow_match_sample_field_base_offset[0x8]; 3671 u8 reserved_at_48[0xd]; 3672 u8 flow_match_sample_tunnel_mode[0x3]; 3673 u8 flow_match_sample_field_offset_mask[0x20]; 3674 u8 flow_match_sample_field_id[0x20]; 3675 }; 3676 3677 struct mlx5_ifc_parse_graph_flex_bits { 3678 u8 modify_field_select[0x40]; 3679 u8 reserved_at_64[0x20]; 3680 u8 header_length_base_value[0x10]; 3681 u8 reserved_at_112[0x4]; 3682 u8 header_length_field_shift[0x4]; 3683 u8 reserved_at_120[0x4]; 3684 u8 header_length_mode[0x4]; 3685 u8 header_length_field_offset[0x10]; 3686 u8 next_header_field_offset[0x10]; 3687 u8 reserved_at_160[0x1b]; 3688 u8 next_header_field_size[0x5]; 3689 u8 header_length_field_mask[0x20]; 3690 u8 reserved_at_224[0x20]; 3691 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8]; 3692 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8]; 3693 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8]; 3694 }; 3695 3696 struct mlx5_ifc_create_flex_parser_in_bits { 3697 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3698 struct mlx5_ifc_parse_graph_flex_bits flex; 3699 }; 3700 3701 struct mlx5_ifc_create_flex_parser_out_bits { 3702 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3703 struct mlx5_ifc_parse_graph_flex_bits flex; 3704 }; 3705 3706 struct mlx5_ifc_parse_graph_flex_out_bits { 3707 u8 status[0x8]; 3708 u8 reserved_at_8[0x18]; 3709 u8 syndrome[0x20]; 3710 u8 reserved_at_40[0x40]; 3711 struct mlx5_ifc_parse_graph_flex_bits capability; 3712 }; 3713 3714 struct regexp_params_field_select_bits { 3715 u8 reserved_at_0[0x1e]; 3716 u8 stop_engine[0x1]; 3717 u8 db_umem_id[0x1]; 3718 }; 3719 3720 struct mlx5_ifc_regexp_params_bits { 3721 u8 reserved_at_0[0x1f]; 3722 u8 stop_engine[0x1]; 3723 u8 db_umem_id[0x20]; 3724 u8 db_umem_offset[0x40]; 3725 u8 reserved_at_80[0x100]; 3726 }; 3727 3728 struct mlx5_ifc_set_regexp_params_in_bits { 3729 u8 opcode[0x10]; 3730 u8 uid[0x10]; 3731 u8 reserved_at_20[0x10]; 3732 u8 op_mod[0x10]; 3733 u8 reserved_at_40[0x18]; 3734 u8 engine_id[0x8]; 3735 struct regexp_params_field_select_bits field_select; 3736 struct mlx5_ifc_regexp_params_bits regexp_params; 3737 }; 3738 3739 struct mlx5_ifc_set_regexp_params_out_bits { 3740 u8 status[0x8]; 3741 u8 reserved_at_8[0x18]; 3742 u8 syndrome[0x20]; 3743 u8 reserved_at_18[0x40]; 3744 }; 3745 3746 struct mlx5_ifc_query_regexp_params_in_bits { 3747 u8 opcode[0x10]; 3748 u8 uid[0x10]; 3749 u8 reserved_at_20[0x10]; 3750 u8 op_mod[0x10]; 3751 u8 reserved_at_40[0x18]; 3752 u8 engine_id[0x8]; 3753 u8 reserved[0x20]; 3754 }; 3755 3756 struct mlx5_ifc_query_regexp_params_out_bits { 3757 u8 status[0x8]; 3758 u8 reserved_at_8[0x18]; 3759 u8 syndrome[0x20]; 3760 u8 reserved[0x40]; 3761 struct mlx5_ifc_regexp_params_bits regexp_params; 3762 }; 3763 3764 struct mlx5_ifc_set_regexp_register_in_bits { 3765 u8 opcode[0x10]; 3766 u8 uid[0x10]; 3767 u8 reserved_at_20[0x10]; 3768 u8 op_mod[0x10]; 3769 u8 reserved_at_40[0x18]; 3770 u8 engine_id[0x8]; 3771 u8 register_address[0x20]; 3772 u8 register_data[0x20]; 3773 u8 reserved[0x60]; 3774 }; 3775 3776 struct mlx5_ifc_set_regexp_register_out_bits { 3777 u8 status[0x8]; 3778 u8 reserved_at_8[0x18]; 3779 u8 syndrome[0x20]; 3780 u8 reserved[0x40]; 3781 }; 3782 3783 struct mlx5_ifc_query_regexp_register_in_bits { 3784 u8 opcode[0x10]; 3785 u8 uid[0x10]; 3786 u8 reserved_at_20[0x10]; 3787 u8 op_mod[0x10]; 3788 u8 reserved_at_40[0x18]; 3789 u8 engine_id[0x8]; 3790 u8 register_address[0x20]; 3791 }; 3792 3793 struct mlx5_ifc_query_regexp_register_out_bits { 3794 u8 status[0x8]; 3795 u8 reserved_at_8[0x18]; 3796 u8 syndrome[0x20]; 3797 u8 reserved[0x20]; 3798 u8 register_data[0x20]; 3799 }; 3800 3801 /* Queue counters. */ 3802 struct mlx5_ifc_alloc_q_counter_out_bits { 3803 u8 status[0x8]; 3804 u8 reserved_at_8[0x18]; 3805 u8 syndrome[0x20]; 3806 u8 reserved_at_40[0x18]; 3807 u8 counter_set_id[0x8]; 3808 u8 reserved_at_60[0x20]; 3809 }; 3810 3811 struct mlx5_ifc_alloc_q_counter_in_bits { 3812 u8 opcode[0x10]; 3813 u8 uid[0x10]; 3814 u8 reserved_at_20[0x10]; 3815 u8 op_mod[0x10]; 3816 u8 reserved_at_40[0x40]; 3817 }; 3818 3819 struct mlx5_ifc_query_q_counter_out_bits { 3820 u8 status[0x8]; 3821 u8 reserved_at_8[0x18]; 3822 u8 syndrome[0x20]; 3823 u8 reserved_at_40[0x40]; 3824 u8 rx_write_requests[0x20]; 3825 u8 reserved_at_a0[0x20]; 3826 u8 rx_read_requests[0x20]; 3827 u8 reserved_at_e0[0x20]; 3828 u8 rx_atomic_requests[0x20]; 3829 u8 reserved_at_120[0x20]; 3830 u8 rx_dct_connect[0x20]; 3831 u8 reserved_at_160[0x20]; 3832 u8 out_of_buffer[0x20]; 3833 u8 reserved_at_1a0[0x20]; 3834 u8 out_of_sequence[0x20]; 3835 u8 reserved_at_1e0[0x20]; 3836 u8 duplicate_request[0x20]; 3837 u8 reserved_at_220[0x20]; 3838 u8 rnr_nak_retry_err[0x20]; 3839 u8 reserved_at_260[0x20]; 3840 u8 packet_seq_err[0x20]; 3841 u8 reserved_at_2a0[0x20]; 3842 u8 implied_nak_seq_err[0x20]; 3843 u8 reserved_at_2e0[0x20]; 3844 u8 local_ack_timeout_err[0x20]; 3845 u8 reserved_at_320[0xa0]; 3846 u8 resp_local_length_error[0x20]; 3847 u8 req_local_length_error[0x20]; 3848 u8 resp_local_qp_error[0x20]; 3849 u8 local_operation_error[0x20]; 3850 u8 resp_local_protection[0x20]; 3851 u8 req_local_protection[0x20]; 3852 u8 resp_cqe_error[0x20]; 3853 u8 req_cqe_error[0x20]; 3854 u8 req_mw_binding[0x20]; 3855 u8 req_bad_response[0x20]; 3856 u8 req_remote_invalid_request[0x20]; 3857 u8 resp_remote_invalid_request[0x20]; 3858 u8 req_remote_access_errors[0x20]; 3859 u8 resp_remote_access_errors[0x20]; 3860 u8 req_remote_operation_errors[0x20]; 3861 u8 req_transport_retries_exceeded[0x20]; 3862 u8 cq_overflow[0x20]; 3863 u8 resp_cqe_flush_error[0x20]; 3864 u8 req_cqe_flush_error[0x20]; 3865 u8 reserved_at_620[0x1e0]; 3866 }; 3867 3868 struct mlx5_ifc_query_q_counter_in_bits { 3869 u8 opcode[0x10]; 3870 u8 uid[0x10]; 3871 u8 reserved_at_20[0x10]; 3872 u8 op_mod[0x10]; 3873 u8 reserved_at_40[0x80]; 3874 u8 clear[0x1]; 3875 u8 reserved_at_c1[0x1f]; 3876 u8 reserved_at_e0[0x18]; 3877 u8 counter_set_id[0x8]; 3878 }; 3879 3880 /* CQE format mask. */ 3881 #define MLX5E_CQE_FORMAT_MASK 0xc 3882 3883 /* MPW opcode. */ 3884 #define MLX5_OPC_MOD_MPW 0x01 3885 3886 /* Compressed Rx CQE structure. */ 3887 struct mlx5_mini_cqe8 { 3888 union { 3889 uint32_t rx_hash_result; 3890 struct { 3891 union { 3892 uint16_t checksum; 3893 uint16_t flow_tag_high; 3894 struct { 3895 uint8_t reserved; 3896 uint8_t hdr_type; 3897 }; 3898 }; 3899 uint16_t stride_idx; 3900 }; 3901 struct { 3902 uint16_t wqe_counter; 3903 uint8_t s_wqe_opcode; 3904 uint8_t reserved; 3905 } s_wqe_info; 3906 }; 3907 union { 3908 uint32_t byte_cnt_flow; 3909 uint32_t byte_cnt; 3910 }; 3911 }; 3912 3913 /* Mini CQE responder format. */ 3914 enum { 3915 MLX5_CQE_RESP_FORMAT_HASH = 0x0, 3916 MLX5_CQE_RESP_FORMAT_CSUM = 0x1, 3917 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2, 3918 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3, 3919 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4, 3920 }; 3921 3922 /* srTCM PRM flow meter parameters. */ 3923 enum { 3924 MLX5_FLOW_COLOR_RED = 0, 3925 MLX5_FLOW_COLOR_YELLOW, 3926 MLX5_FLOW_COLOR_GREEN, 3927 MLX5_FLOW_COLOR_UNDEFINED, 3928 }; 3929 3930 /* Maximum value of srTCM & trTCM metering parameters. */ 3931 #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F)) 3932 #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF) 3933 3934 /* The bits meter color use. */ 3935 #define MLX5_MTR_COLOR_BITS 8 3936 3937 /* The bit size of one register. */ 3938 #define MLX5_REG_BITS 32 3939 3940 /* Idle bits for non-color usage in color register. */ 3941 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS) 3942 3943 /* Length mode of dynamic flex parser graph node. */ 3944 enum mlx5_parse_graph_node_len_mode { 3945 MLX5_GRAPH_NODE_LEN_FIXED = 0x0, 3946 MLX5_GRAPH_NODE_LEN_FIELD = 0x1, 3947 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2, 3948 }; 3949 3950 /* Offset mode of the samples of flex parser. */ 3951 enum mlx5_parse_graph_flow_match_sample_offset_mode { 3952 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0, 3953 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1, 3954 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, 3955 }; 3956 3957 /* Node index for an input / output arc of the flex parser graph. */ 3958 enum mlx5_parse_graph_arc_node_index { 3959 MLX5_GRAPH_ARC_NODE_NULL = 0x0, 3960 MLX5_GRAPH_ARC_NODE_HEAD = 0x1, 3961 MLX5_GRAPH_ARC_NODE_MAC = 0x2, 3962 MLX5_GRAPH_ARC_NODE_IP = 0x3, 3963 MLX5_GRAPH_ARC_NODE_GRE = 0x4, 3964 MLX5_GRAPH_ARC_NODE_UDP = 0x5, 3965 MLX5_GRAPH_ARC_NODE_MPLS = 0x6, 3966 MLX5_GRAPH_ARC_NODE_TCP = 0x7, 3967 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, 3968 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, 3969 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, 3970 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, 3971 }; 3972 3973 /** 3974 * Convert a user mark to flow mark. 3975 * 3976 * @param val 3977 * Mark value to convert. 3978 * 3979 * @return 3980 * Converted mark value. 3981 */ 3982 static inline uint32_t 3983 mlx5_flow_mark_set(uint32_t val) 3984 { 3985 uint32_t ret; 3986 3987 /* 3988 * Add one to the user value to differentiate un-marked flows from 3989 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it 3990 * remains untouched. 3991 */ 3992 if (val != MLX5_FLOW_MARK_DEFAULT) 3993 ++val; 3994 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 3995 /* 3996 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit 3997 * word, byte-swapped by the kernel on little-endian systems. In this 3998 * case, left-shifting the resulting big-endian value ensures the 3999 * least significant 24 bits are retained when converting it back. 4000 */ 4001 ret = rte_cpu_to_be_32(val) >> 8; 4002 #else 4003 ret = val; 4004 #endif 4005 return ret; 4006 } 4007 4008 /** 4009 * Convert a mark to user mark. 4010 * 4011 * @param val 4012 * Mark value to convert. 4013 * 4014 * @return 4015 * Converted mark value. 4016 */ 4017 static inline uint32_t 4018 mlx5_flow_mark_get(uint32_t val) 4019 { 4020 /* 4021 * Subtract one from the retrieved value. It was added by 4022 * mlx5_flow_mark_set() to distinguish unmarked flows. 4023 */ 4024 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 4025 return (val >> 8) - 1; 4026 #else 4027 return val - 1; 4028 #endif 4029 } 4030 4031 /** 4032 * Convert a timestamp format to configure settings in the queue context. 4033 * 4034 * @param val 4035 * timestamp format supported by the queue. 4036 * 4037 * @return 4038 * Converted timstamp format settings. 4039 */ 4040 static inline uint32_t 4041 mlx5_ts_format_conv(uint32_t ts_format) 4042 { 4043 return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ? 4044 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : 4045 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; 4046 } 4047 4048 #endif /* RTE_PMD_MLX5_PRM_H_ */ 4049