1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_PRM_H_ 7 #define RTE_PMD_MLX5_PRM_H_ 8 9 #include <unistd.h> 10 11 #include <rte_vect.h> 12 #include <rte_byteorder.h> 13 14 #include <mlx5_glue.h> 15 #include "mlx5_autoconf.h" 16 17 /* RSS hash key size. */ 18 #define MLX5_RSS_HASH_KEY_LEN 40 19 20 /* Get CQE owner bit. */ 21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK) 22 23 /* Get CQE format. */ 24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2) 25 26 /* Get CQE opcode. */ 27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4) 28 29 /* Get CQE solicited event. */ 30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1) 31 32 /* Invalidate a CQE. */ 33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4) 34 35 /* Hardware index widths. */ 36 #define MLX5_CQ_INDEX_WIDTH 24 37 #define MLX5_WQ_INDEX_WIDTH 16 38 39 /* WQE Segment sizes in bytes. */ 40 #define MLX5_WSEG_SIZE 16u 41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg) 42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg) 43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg) 44 45 /* WQE/WQEBB size in bytes. */ 46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe) 47 48 /* 49 * Max size of a WQE session. 50 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments, 51 * the WQE size field in Control Segment is 6 bits wide. 52 */ 53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE) 54 55 /* 56 * Default minimum number of Tx queues for inlining packets. 57 * If there are less queues as specified we assume we have 58 * no enough CPU resources (cycles) to perform inlining, 59 * the PCIe throughput is not supposed as bottleneck and 60 * inlining is disabled. 61 */ 62 #define MLX5_INLINE_MAX_TXQS 8u 63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u 64 65 /* 66 * Default packet length threshold to be inlined with 67 * enhanced MPW. If packet length exceeds the threshold 68 * the data are not inlined. Should be aligned in WQEBB 69 * boundary with accounting the title Control and Ethernet 70 * segments. 71 */ 72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \ 73 MLX5_DSEG_MIN_INLINE_SIZE) 74 /* 75 * Maximal inline data length sent with enhanced MPW. 76 * Is based on maximal WQE size. 77 */ 78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 79 MLX5_WQE_CSEG_SIZE - \ 80 MLX5_WQE_ESEG_SIZE - \ 81 MLX5_WQE_DSEG_SIZE + \ 82 MLX5_DSEG_MIN_INLINE_SIZE) 83 /* 84 * Minimal amount of packets to be sent with EMPW. 85 * This limits the minimal required size of sent EMPW. 86 * If there are no enough resources to built minimal 87 * EMPW the sending loop exits. 88 */ 89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u) 90 /* 91 * Maximal amount of packets to be sent with EMPW. 92 * This value is not recommended to exceed MLX5_TX_COMP_THRESH, 93 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs 94 * without CQE generation request, being multiplied by 95 * MLX5_TX_COMP_MAX_CQE it may cause significant latency 96 * in tx burst routine at the moment of freeing multiple mbufs. 97 */ 98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH 99 #define MLX5_MPW_MAX_PACKETS 6 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6 101 102 /* 103 * Default packet length threshold to be inlined with 104 * ordinary SEND. Inlining saves the MR key search 105 * and extra PCIe data fetch transaction, but eats the 106 * CPU cycles. 107 */ 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \ 109 MLX5_ESEG_MIN_INLINE_SIZE - \ 110 MLX5_WQE_CSEG_SIZE - \ 111 MLX5_WQE_ESEG_SIZE - \ 112 MLX5_WQE_DSEG_SIZE) 113 /* 114 * Maximal inline data length sent with ordinary SEND. 115 * Is based on maximal WQE size. 116 */ 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 118 MLX5_WQE_CSEG_SIZE - \ 119 MLX5_WQE_ESEG_SIZE - \ 120 MLX5_WQE_DSEG_SIZE + \ 121 MLX5_ESEG_MIN_INLINE_SIZE) 122 123 /* Missed in mlx5dv.h, should define here. */ 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u 126 #endif 127 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN 129 #define MLX5_OPCODE_SEND_EN 0x17u 130 #endif 131 132 #ifndef HAVE_MLX5_OPCODE_WAIT 133 #define MLX5_OPCODE_WAIT 0x0fu 134 #endif 135 136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO 137 #define MLX5_OPCODE_ACCESS_ASO 0x2du 138 #endif 139 140 /* CQE value to inform that VLAN is stripped. */ 141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0) 142 143 /* IPv4 options. */ 144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1) 145 146 /* IPv6 packet. */ 147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2) 148 149 /* IPv4 packet. */ 150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3) 151 152 /* TCP packet. */ 153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4) 154 155 /* UDP packet. */ 156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5) 157 158 /* IP is fragmented. */ 159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7) 160 161 /* L2 header is valid. */ 162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8) 163 164 /* L3 header is valid. */ 165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9) 166 167 /* L4 header is valid. */ 168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10) 169 170 /* Outer packet, 0 IPv4, 1 IPv6. */ 171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1) 172 173 /* Tunnel packet bit in the CQE. */ 174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0) 175 176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */ 177 #define MLX5_CQE_LRO_PUSH_MASK 0x40 178 179 /* Mask for L4 type in the CQE hdr_type_etc field. */ 180 #define MLX5_CQE_L4_TYPE_MASK 0x70 181 182 /* The bit index of L4 type in CQE hdr_type_etc field. */ 183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4 184 185 /* L4 type to indicate TCP packet without acknowledgment. */ 186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3 187 188 /* L4 type to indicate TCP packet with acknowledgment. */ 189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4 190 191 /* Inner L3 checksum offload (Tunneled packets only). */ 192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4) 193 194 /* Inner L4 checksum offload (Tunneled packets only). */ 195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5) 196 197 /* Outer L4 type is TCP. */ 198 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5) 199 200 /* Outer L4 type is UDP. */ 201 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5) 202 203 /* Outer L3 type is IPV4. */ 204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4) 205 206 /* Outer L3 type is IPV6. */ 207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4) 208 209 /* Inner L4 type is TCP. */ 210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1) 211 212 /* Inner L4 type is UDP. */ 213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1) 214 215 /* Inner L3 type is IPV4. */ 216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0) 217 218 /* Inner L3 type is IPV6. */ 219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0) 220 221 /* VLAN insertion flag. */ 222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31) 223 224 /* Data inline segment flag. */ 225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31) 226 227 /* Is flow mark valid. */ 228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00) 230 #else 231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff) 232 #endif 233 234 /* INVALID is used by packets matching no flow rules. */ 235 #define MLX5_FLOW_MARK_INVALID 0 236 237 /* Maximum allowed value to mark a packet. */ 238 #define MLX5_FLOW_MARK_MAX 0xfffff0 239 240 /* Default mark value used when none is provided. */ 241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff 242 243 /* Default mark mask for metadata legacy mode. */ 244 #define MLX5_FLOW_MARK_MASK 0xffffff 245 246 /* Byte length mask when mark is enable in miniCQE */ 247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00 248 249 /* Maximum number of DS in WQE. Limited by 6-bit field. */ 250 #define MLX5_DSEG_MAX 63 251 252 /* The completion mode offset in the WQE control segment line 2. */ 253 #define MLX5_COMP_MODE_OFFSET 2 254 255 /* Amount of data bytes in minimal inline data segment. */ 256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u 257 258 /* Amount of data bytes in minimal inline eth segment. */ 259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u 260 261 /* Amount of data bytes after eth data segment. */ 262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u 263 264 /* The maximum log value of segments per RQ WQE. */ 265 #define MLX5_MAX_LOG_RQ_SEGS 5u 266 267 /* The alignment needed for WQ buffer. */ 268 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size() 269 270 /* The alignment needed for CQ buffer. */ 271 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size() 272 273 /* Completion mode. */ 274 enum mlx5_completion_mode { 275 MLX5_COMP_ONLY_ERR = 0x0, 276 MLX5_COMP_ONLY_FIRST_ERR = 0x1, 277 MLX5_COMP_ALWAYS = 0x2, 278 MLX5_COMP_CQE_AND_EQE = 0x3, 279 }; 280 281 /* MPW mode. */ 282 enum mlx5_mpw_mode { 283 MLX5_MPW_DISABLED, 284 MLX5_MPW, 285 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */ 286 }; 287 288 /* WQE Control segment. */ 289 struct mlx5_wqe_cseg { 290 uint32_t opcode; 291 uint32_t sq_ds; 292 uint32_t flags; 293 uint32_t misc; 294 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE); 295 296 /* 297 * WQE CSEG opcode field size is 32 bits, divided: 298 * Bits 31:24 OPC_MOD 299 * Bits 23:8 wqe_index 300 * Bits 7:0 OPCODE 301 */ 302 #define WQE_CSEG_OPC_MOD_OFFSET 24 303 #define WQE_CSEG_WQE_INDEX_OFFSET 8 304 305 /* Header of data segment. Minimal size Data Segment */ 306 struct mlx5_wqe_dseg { 307 uint32_t bcount; 308 union { 309 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE]; 310 struct { 311 uint32_t lkey; 312 uint64_t pbuf; 313 } __rte_packed; 314 }; 315 } __rte_packed; 316 317 /* Subset of struct WQE Ethernet Segment. */ 318 struct mlx5_wqe_eseg { 319 union { 320 struct { 321 uint32_t swp_offs; 322 uint8_t cs_flags; 323 uint8_t swp_flags; 324 uint16_t mss; 325 uint32_t metadata; 326 uint16_t inline_hdr_sz; 327 union { 328 uint16_t inline_data; 329 uint16_t vlan_tag; 330 }; 331 } __rte_packed; 332 struct { 333 uint32_t offsets; 334 uint32_t flags; 335 uint32_t flow_metadata; 336 uint32_t inline_hdr; 337 } __rte_packed; 338 }; 339 } __rte_packed; 340 341 struct mlx5_wqe_qseg { 342 uint32_t reserved0; 343 uint32_t reserved1; 344 uint32_t max_index; 345 uint32_t qpn_cqn; 346 } __rte_packed; 347 348 /* The title WQEBB, header of WQE. */ 349 struct mlx5_wqe { 350 union { 351 struct mlx5_wqe_cseg cseg; 352 uint32_t ctrl[4]; 353 }; 354 struct mlx5_wqe_eseg eseg; 355 union { 356 struct mlx5_wqe_dseg dseg[2]; 357 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE]; 358 }; 359 } __rte_packed; 360 361 /* WQE for Multi-Packet RQ. */ 362 struct mlx5_wqe_mprq { 363 struct mlx5_wqe_srq_next_seg next_seg; 364 struct mlx5_wqe_data_seg dseg; 365 }; 366 367 #define MLX5_MPRQ_LEN_MASK 0x000ffff 368 #define MLX5_MPRQ_LEN_SHIFT 0 369 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000 370 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16 371 #define MLX5_MPRQ_FILLER_MASK 0x80000000 372 #define MLX5_MPRQ_FILLER_SHIFT 31 373 374 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2 375 376 /* CQ element structure - should be equal to the cache line size */ 377 struct mlx5_cqe { 378 #if (RTE_CACHE_LINE_SIZE == 128) 379 uint8_t padding[64]; 380 #endif 381 uint8_t pkt_info; 382 uint8_t rsvd0; 383 uint16_t wqe_id; 384 uint8_t lro_tcppsh_abort_dupack; 385 uint8_t lro_min_ttl; 386 uint16_t lro_tcp_win; 387 uint32_t lro_ack_seq_num; 388 uint32_t rx_hash_res; 389 uint8_t rx_hash_type; 390 uint8_t rsvd1[3]; 391 uint16_t csum; 392 uint8_t rsvd2[6]; 393 uint16_t hdr_type_etc; 394 uint16_t vlan_info; 395 uint8_t lro_num_seg; 396 uint8_t rsvd3[3]; 397 uint32_t flow_table_metadata; 398 uint8_t rsvd4[4]; 399 uint32_t byte_cnt; 400 uint64_t timestamp; 401 uint32_t sop_drop_qpn; 402 uint16_t wqe_counter; 403 uint8_t rsvd5; 404 uint8_t op_own; 405 }; 406 407 struct mlx5_cqe_ts { 408 uint64_t timestamp; 409 uint32_t sop_drop_qpn; 410 uint16_t wqe_counter; 411 uint8_t rsvd5; 412 uint8_t op_own; 413 }; 414 415 /* GGA */ 416 /* MMO metadata segment */ 417 418 #define MLX5_OPCODE_MMO 0x2fu 419 #define MLX5_OPC_MOD_MMO_REGEX 0x4u 420 #define MLX5_OPC_MOD_MMO_COMP 0x2u 421 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u 422 #define MLX5_OPC_MOD_MMO_DMA 0x1u 423 424 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u 425 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u 426 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u 427 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u 428 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) 429 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u 430 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u 431 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u 432 433 struct mlx5_wqe_metadata_seg { 434 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */ 435 uint32_t lkey; 436 uint64_t addr; 437 }; 438 439 struct mlx5_gga_wqe { 440 uint32_t opcode; 441 uint32_t sq_ds; 442 uint32_t flags; 443 uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */ 444 uint32_t gga_ctrl2; 445 uint32_t opaque_lkey; 446 uint64_t opaque_vaddr; 447 struct mlx5_wqe_dseg gather; 448 struct mlx5_wqe_dseg scatter; 449 } __rte_packed; 450 451 struct mlx5_gga_compress_opaque { 452 uint32_t syndrom; 453 uint32_t reserved0; 454 uint32_t scattered_length; 455 uint32_t gathered_length; 456 uint64_t scatter_crc; 457 uint64_t gather_crc; 458 uint32_t crc32; 459 uint32_t adler32; 460 uint8_t reserved1[216]; 461 } __rte_packed; 462 463 struct mlx5_ifc_regexp_mmo_control_bits { 464 uint8_t reserved_at_31[0x2]; 465 uint8_t le[0x1]; 466 uint8_t reserved_at_28[0x1]; 467 uint8_t subset_id_0[0xc]; 468 uint8_t reserved_at_16[0x4]; 469 uint8_t subset_id_1[0xc]; 470 uint8_t ctrl[0x4]; 471 uint8_t subset_id_2[0xc]; 472 uint8_t reserved_at_16_1[0x4]; 473 uint8_t subset_id_3[0xc]; 474 }; 475 476 struct mlx5_ifc_regexp_metadata_bits { 477 uint8_t rof_version[0x10]; 478 uint8_t latency_count[0x10]; 479 uint8_t instruction_count[0x10]; 480 uint8_t primary_thread_count[0x10]; 481 uint8_t match_count[0x8]; 482 uint8_t detected_match_count[0x8]; 483 uint8_t status[0x10]; 484 uint8_t job_id[0x20]; 485 uint8_t reserved[0x80]; 486 }; 487 488 struct mlx5_ifc_regexp_match_tuple_bits { 489 uint8_t length[0x10]; 490 uint8_t start_ptr[0x10]; 491 uint8_t rule_id[0x20]; 492 }; 493 494 /* Adding direct verbs to data-path. */ 495 496 /* CQ sequence number mask. */ 497 #define MLX5_CQ_SQN_MASK 0x3 498 499 /* CQ sequence number index. */ 500 #define MLX5_CQ_SQN_OFFSET 28 501 502 /* CQ doorbell index mask. */ 503 #define MLX5_CI_MASK 0xffffff 504 505 /* CQ doorbell offset. */ 506 #define MLX5_CQ_ARM_DB 1 507 508 /* CQ doorbell offset*/ 509 #define MLX5_CQ_DOORBELL 0x20 510 511 /* CQE format value. */ 512 #define MLX5_COMPRESSED 0x3 513 514 /* CQ doorbell cmd types. */ 515 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24) 516 #define MLX5_CQ_DBR_CMD_ALL (0 << 24) 517 518 /* Action type of header modification. */ 519 enum { 520 MLX5_MODIFICATION_TYPE_SET = 0x1, 521 MLX5_MODIFICATION_TYPE_ADD = 0x2, 522 MLX5_MODIFICATION_TYPE_COPY = 0x3, 523 }; 524 525 /* The field of packet to be modified. */ 526 enum mlx5_modification_field { 527 MLX5_MODI_OUT_NONE = -1, 528 MLX5_MODI_OUT_SMAC_47_16 = 1, 529 MLX5_MODI_OUT_SMAC_15_0, 530 MLX5_MODI_OUT_ETHERTYPE, 531 MLX5_MODI_OUT_DMAC_47_16, 532 MLX5_MODI_OUT_DMAC_15_0, 533 MLX5_MODI_OUT_IP_DSCP, 534 MLX5_MODI_OUT_TCP_FLAGS, 535 MLX5_MODI_OUT_TCP_SPORT, 536 MLX5_MODI_OUT_TCP_DPORT, 537 MLX5_MODI_OUT_IPV4_TTL, 538 MLX5_MODI_OUT_UDP_SPORT, 539 MLX5_MODI_OUT_UDP_DPORT, 540 MLX5_MODI_OUT_SIPV6_127_96, 541 MLX5_MODI_OUT_SIPV6_95_64, 542 MLX5_MODI_OUT_SIPV6_63_32, 543 MLX5_MODI_OUT_SIPV6_31_0, 544 MLX5_MODI_OUT_DIPV6_127_96, 545 MLX5_MODI_OUT_DIPV6_95_64, 546 MLX5_MODI_OUT_DIPV6_63_32, 547 MLX5_MODI_OUT_DIPV6_31_0, 548 MLX5_MODI_OUT_SIPV4, 549 MLX5_MODI_OUT_DIPV4, 550 MLX5_MODI_OUT_FIRST_VID, 551 MLX5_MODI_IN_SMAC_47_16 = 0x31, 552 MLX5_MODI_IN_SMAC_15_0, 553 MLX5_MODI_IN_ETHERTYPE, 554 MLX5_MODI_IN_DMAC_47_16, 555 MLX5_MODI_IN_DMAC_15_0, 556 MLX5_MODI_IN_IP_DSCP, 557 MLX5_MODI_IN_TCP_FLAGS, 558 MLX5_MODI_IN_TCP_SPORT, 559 MLX5_MODI_IN_TCP_DPORT, 560 MLX5_MODI_IN_IPV4_TTL, 561 MLX5_MODI_IN_UDP_SPORT, 562 MLX5_MODI_IN_UDP_DPORT, 563 MLX5_MODI_IN_SIPV6_127_96, 564 MLX5_MODI_IN_SIPV6_95_64, 565 MLX5_MODI_IN_SIPV6_63_32, 566 MLX5_MODI_IN_SIPV6_31_0, 567 MLX5_MODI_IN_DIPV6_127_96, 568 MLX5_MODI_IN_DIPV6_95_64, 569 MLX5_MODI_IN_DIPV6_63_32, 570 MLX5_MODI_IN_DIPV6_31_0, 571 MLX5_MODI_IN_SIPV4, 572 MLX5_MODI_IN_DIPV4, 573 MLX5_MODI_OUT_IPV6_HOPLIMIT, 574 MLX5_MODI_IN_IPV6_HOPLIMIT, 575 MLX5_MODI_META_DATA_REG_A, 576 MLX5_MODI_META_DATA_REG_B = 0x50, 577 MLX5_MODI_META_REG_C_0, 578 MLX5_MODI_META_REG_C_1, 579 MLX5_MODI_META_REG_C_2, 580 MLX5_MODI_META_REG_C_3, 581 MLX5_MODI_META_REG_C_4, 582 MLX5_MODI_META_REG_C_5, 583 MLX5_MODI_META_REG_C_6, 584 MLX5_MODI_META_REG_C_7, 585 MLX5_MODI_OUT_TCP_SEQ_NUM, 586 MLX5_MODI_IN_TCP_SEQ_NUM, 587 MLX5_MODI_OUT_TCP_ACK_NUM, 588 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C, 589 MLX5_MODI_GTP_TEID = 0x6E, 590 }; 591 592 /* Total number of metadata reg_c's. */ 593 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1) 594 595 enum modify_reg { 596 REG_NON = 0, 597 REG_A, 598 REG_B, 599 REG_C_0, 600 REG_C_1, 601 REG_C_2, 602 REG_C_3, 603 REG_C_4, 604 REG_C_5, 605 REG_C_6, 606 REG_C_7, 607 }; 608 609 /* Modification sub command. */ 610 struct mlx5_modification_cmd { 611 union { 612 uint32_t data0; 613 struct { 614 unsigned int length:5; 615 unsigned int rsvd0:3; 616 unsigned int offset:5; 617 unsigned int rsvd1:3; 618 unsigned int field:12; 619 unsigned int action_type:4; 620 }; 621 }; 622 union { 623 uint32_t data1; 624 uint8_t data[4]; 625 struct { 626 unsigned int rsvd2:8; 627 unsigned int dst_offset:5; 628 unsigned int rsvd3:3; 629 unsigned int dst_field:12; 630 unsigned int rsvd4:4; 631 }; 632 }; 633 }; 634 635 typedef uint64_t u64; 636 typedef uint32_t u32; 637 typedef uint16_t u16; 638 typedef uint8_t u8; 639 640 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 641 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 642 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \ 643 (&(__mlx5_nullp(typ)->fld))) 644 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \ 645 (__mlx5_bit_off(typ, fld) & 0x1f)) 646 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 647 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 648 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \ 649 __mlx5_dw_bit_off(typ, fld)) 650 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 651 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 652 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \ 653 (__mlx5_bit_off(typ, fld) & 0xf)) 654 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 655 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \ 656 __mlx5_16_bit_off(typ, fld)) 657 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 658 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 659 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 660 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 661 662 /* insert a value to a struct */ 663 #define MLX5_SET(typ, p, fld, v) \ 664 do { \ 665 u32 _v = v; \ 666 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \ 667 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \ 668 __mlx5_dw_off(typ, fld))) & \ 669 (~__mlx5_dw_mask(typ, fld))) | \ 670 (((_v) & __mlx5_mask(typ, fld)) << \ 671 __mlx5_dw_bit_off(typ, fld))); \ 672 } while (0) 673 674 #define MLX5_SET64(typ, p, fld, v) \ 675 do { \ 676 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \ 677 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \ 678 rte_cpu_to_be_64(v); \ 679 } while (0) 680 681 #define MLX5_SET16(typ, p, fld, v) \ 682 do { \ 683 u16 _v = v; \ 684 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \ 685 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 686 __mlx5_16_off(typ, fld))) & \ 687 (~__mlx5_16_mask(typ, fld))) | \ 688 (((_v) & __mlx5_mask16(typ, fld)) << \ 689 __mlx5_16_bit_off(typ, fld))); \ 690 } while (0) 691 692 #define MLX5_GET_VOLATILE(typ, p, fld) \ 693 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\ 694 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 695 __mlx5_mask(typ, fld)) 696 #define MLX5_GET(typ, p, fld) \ 697 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\ 698 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 699 __mlx5_mask(typ, fld)) 700 #define MLX5_GET16(typ, p, fld) \ 701 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 702 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 703 __mlx5_mask16(typ, fld)) 704 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \ 705 __mlx5_64_off(typ, fld))) 706 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 707 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 708 709 struct mlx5_ifc_fte_match_set_misc_bits { 710 u8 gre_c_present[0x1]; 711 u8 reserved_at_1[0x1]; 712 u8 gre_k_present[0x1]; 713 u8 gre_s_present[0x1]; 714 u8 source_vhci_port[0x4]; 715 u8 source_sqn[0x18]; 716 u8 reserved_at_20[0x10]; 717 u8 source_port[0x10]; 718 u8 outer_second_prio[0x3]; 719 u8 outer_second_cfi[0x1]; 720 u8 outer_second_vid[0xc]; 721 u8 inner_second_prio[0x3]; 722 u8 inner_second_cfi[0x1]; 723 u8 inner_second_vid[0xc]; 724 u8 outer_second_cvlan_tag[0x1]; 725 u8 inner_second_cvlan_tag[0x1]; 726 u8 outer_second_svlan_tag[0x1]; 727 u8 inner_second_svlan_tag[0x1]; 728 u8 reserved_at_64[0xc]; 729 u8 gre_protocol[0x10]; 730 u8 gre_key_h[0x18]; 731 u8 gre_key_l[0x8]; 732 u8 vxlan_vni[0x18]; 733 u8 reserved_at_b8[0x8]; 734 u8 geneve_vni[0x18]; 735 u8 reserved_at_e4[0x7]; 736 u8 geneve_oam[0x1]; 737 u8 reserved_at_e0[0xc]; 738 u8 outer_ipv6_flow_label[0x14]; 739 u8 reserved_at_100[0xc]; 740 u8 inner_ipv6_flow_label[0x14]; 741 u8 reserved_at_120[0xa]; 742 u8 geneve_opt_len[0x6]; 743 u8 geneve_protocol_type[0x10]; 744 u8 reserved_at_140[0xc0]; 745 }; 746 747 struct mlx5_ifc_ipv4_layout_bits { 748 u8 reserved_at_0[0x60]; 749 u8 ipv4[0x20]; 750 }; 751 752 struct mlx5_ifc_ipv6_layout_bits { 753 u8 ipv6[16][0x8]; 754 }; 755 756 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 757 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 758 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 759 u8 reserved_at_0[0x80]; 760 }; 761 762 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 763 u8 smac_47_16[0x20]; 764 u8 smac_15_0[0x10]; 765 u8 ethertype[0x10]; 766 u8 dmac_47_16[0x20]; 767 u8 dmac_15_0[0x10]; 768 u8 first_prio[0x3]; 769 u8 first_cfi[0x1]; 770 u8 first_vid[0xc]; 771 u8 ip_protocol[0x8]; 772 u8 ip_dscp[0x6]; 773 u8 ip_ecn[0x2]; 774 u8 cvlan_tag[0x1]; 775 u8 svlan_tag[0x1]; 776 u8 frag[0x1]; 777 u8 ip_version[0x4]; 778 u8 tcp_flags[0x9]; 779 u8 tcp_sport[0x10]; 780 u8 tcp_dport[0x10]; 781 u8 reserved_at_c0[0x18]; 782 u8 ip_ttl_hoplimit[0x8]; 783 u8 udp_sport[0x10]; 784 u8 udp_dport[0x10]; 785 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 786 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 787 }; 788 789 struct mlx5_ifc_fte_match_mpls_bits { 790 u8 mpls_label[0x14]; 791 u8 mpls_exp[0x3]; 792 u8 mpls_s_bos[0x1]; 793 u8 mpls_ttl[0x8]; 794 }; 795 796 struct mlx5_ifc_fte_match_set_misc2_bits { 797 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 798 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 799 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 800 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 801 u8 metadata_reg_c_7[0x20]; 802 u8 metadata_reg_c_6[0x20]; 803 u8 metadata_reg_c_5[0x20]; 804 u8 metadata_reg_c_4[0x20]; 805 u8 metadata_reg_c_3[0x20]; 806 u8 metadata_reg_c_2[0x20]; 807 u8 metadata_reg_c_1[0x20]; 808 u8 metadata_reg_c_0[0x20]; 809 u8 metadata_reg_a[0x20]; 810 u8 metadata_reg_b[0x20]; 811 u8 reserved_at_1c0[0x40]; 812 }; 813 814 struct mlx5_ifc_fte_match_set_misc3_bits { 815 u8 inner_tcp_seq_num[0x20]; 816 u8 outer_tcp_seq_num[0x20]; 817 u8 inner_tcp_ack_num[0x20]; 818 u8 outer_tcp_ack_num[0x20]; 819 u8 reserved_at_auto1[0x8]; 820 u8 outer_vxlan_gpe_vni[0x18]; 821 u8 outer_vxlan_gpe_next_protocol[0x8]; 822 u8 outer_vxlan_gpe_flags[0x8]; 823 u8 reserved_at_a8[0x10]; 824 u8 icmp_header_data[0x20]; 825 u8 icmpv6_header_data[0x20]; 826 u8 icmp_type[0x8]; 827 u8 icmp_code[0x8]; 828 u8 icmpv6_type[0x8]; 829 u8 icmpv6_code[0x8]; 830 u8 geneve_tlv_option_0_data[0x20]; 831 u8 gtpu_teid[0x20]; 832 u8 gtpu_msg_type[0x08]; 833 u8 gtpu_msg_flags[0x08]; 834 u8 reserved_at_170[0x10]; 835 u8 gtpu_dw_2[0x20]; 836 u8 gtpu_first_ext_dw_0[0x20]; 837 u8 gtpu_dw_0[0x20]; 838 u8 reserved_at_240[0x20]; 839 840 }; 841 842 struct mlx5_ifc_fte_match_set_misc4_bits { 843 u8 prog_sample_field_value_0[0x20]; 844 u8 prog_sample_field_id_0[0x20]; 845 u8 prog_sample_field_value_1[0x20]; 846 u8 prog_sample_field_id_1[0x20]; 847 u8 prog_sample_field_value_2[0x20]; 848 u8 prog_sample_field_id_2[0x20]; 849 u8 prog_sample_field_value_3[0x20]; 850 u8 prog_sample_field_id_3[0x20]; 851 u8 reserved_at_100[0x100]; 852 }; 853 854 /* Flow matcher. */ 855 struct mlx5_ifc_fte_match_param_bits { 856 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 857 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 858 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 859 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 860 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 861 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 862 /* 863 * Add reserved bit to match the struct size with the size defined in PRM. 864 * This extension is not required in Linux. 865 */ 866 #ifndef HAVE_INFINIBAND_VERBS_H 867 u8 reserved_0[0x400]; 868 #endif 869 }; 870 871 struct mlx5_ifc_dest_format_struct_bits { 872 u8 destination_type[0x8]; 873 u8 destination_id[0x18]; 874 u8 reserved_0[0x20]; 875 }; 876 877 enum { 878 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 879 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT, 880 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT, 881 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT, 882 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT, 883 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT, 884 }; 885 886 enum { 887 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 888 MLX5_CMD_OP_CREATE_MKEY = 0x200, 889 MLX5_CMD_OP_CREATE_CQ = 0x400, 890 MLX5_CMD_OP_CREATE_QP = 0x500, 891 MLX5_CMD_OP_RST2INIT_QP = 0x502, 892 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 893 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 894 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 895 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 896 MLX5_CMD_OP_QP_2ERR = 0x507, 897 MLX5_CMD_OP_QP_2RST = 0x50A, 898 MLX5_CMD_OP_QUERY_QP = 0x50B, 899 MLX5_CMD_OP_SQD2RTS_QP = 0x50C, 900 MLX5_CMD_OP_INIT2INIT_QP = 0x50E, 901 MLX5_CMD_OP_SUSPEND_QP = 0x50F, 902 MLX5_CMD_OP_RESUME_QP = 0x510, 903 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 904 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 905 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 906 MLX5_CMD_OP_ALLOC_PD = 0x800, 907 MLX5_CMD_OP_DEALLOC_PD = 0x801, 908 MLX5_CMD_OP_ACCESS_REGISTER = 0x805, 909 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 910 MLX5_CMD_OP_CREATE_TIR = 0x900, 911 MLX5_CMD_OP_MODIFY_TIR = 0x901, 912 MLX5_CMD_OP_CREATE_SQ = 0X904, 913 MLX5_CMD_OP_MODIFY_SQ = 0X905, 914 MLX5_CMD_OP_CREATE_RQ = 0x908, 915 MLX5_CMD_OP_MODIFY_RQ = 0x909, 916 MLX5_CMD_OP_QUERY_RQ = 0x90b, 917 MLX5_CMD_OP_CREATE_TIS = 0x912, 918 MLX5_CMD_OP_QUERY_TIS = 0x915, 919 MLX5_CMD_OP_CREATE_RQT = 0x916, 920 MLX5_CMD_OP_MODIFY_RQT = 0x917, 921 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 922 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 923 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 924 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 925 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 926 MLX5_CMD_SET_REGEX_PARAMS = 0xb04, 927 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05, 928 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06, 929 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07, 930 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c, 931 }; 932 933 enum { 934 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 935 MLX5_MKC_ACCESS_MODE_KLM = 0x2, 936 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3, 937 }; 938 939 #define MLX5_ADAPTER_PAGE_SHIFT 12 940 #define MLX5_LOG_RQ_STRIDE_SHIFT 4 941 /** 942 * The batch counter dcs id starts from 0x800000 and none batch counter 943 * starts from 0. As currently, the counter is changed to be indexed by 944 * pool index and the offset of the counter in the pool counters_raw array. 945 * It means now the counter index is same for batch and none batch counter. 946 * Add the 0x800000 batch counter offset to the batch counter index helps 947 * indicate the counter index is from batch or none batch container pool. 948 */ 949 #define MLX5_CNT_BATCH_OFFSET 0x800000 950 951 /* The counter batch query requires ID align with 4. */ 952 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4 953 954 /* Flow counters. */ 955 struct mlx5_ifc_alloc_flow_counter_out_bits { 956 u8 status[0x8]; 957 u8 reserved_at_8[0x18]; 958 u8 syndrome[0x20]; 959 u8 flow_counter_id[0x20]; 960 u8 reserved_at_60[0x20]; 961 }; 962 963 struct mlx5_ifc_alloc_flow_counter_in_bits { 964 u8 opcode[0x10]; 965 u8 reserved_at_10[0x10]; 966 u8 reserved_at_20[0x10]; 967 u8 op_mod[0x10]; 968 u8 flow_counter_id[0x20]; 969 u8 reserved_at_40[0x18]; 970 u8 flow_counter_bulk[0x8]; 971 }; 972 973 struct mlx5_ifc_dealloc_flow_counter_out_bits { 974 u8 status[0x8]; 975 u8 reserved_at_8[0x18]; 976 u8 syndrome[0x20]; 977 u8 reserved_at_40[0x40]; 978 }; 979 980 struct mlx5_ifc_dealloc_flow_counter_in_bits { 981 u8 opcode[0x10]; 982 u8 reserved_at_10[0x10]; 983 u8 reserved_at_20[0x10]; 984 u8 op_mod[0x10]; 985 u8 flow_counter_id[0x20]; 986 u8 reserved_at_60[0x20]; 987 }; 988 989 struct mlx5_ifc_traffic_counter_bits { 990 u8 packets[0x40]; 991 u8 octets[0x40]; 992 }; 993 994 struct mlx5_ifc_query_flow_counter_out_bits { 995 u8 status[0x8]; 996 u8 reserved_at_8[0x18]; 997 u8 syndrome[0x20]; 998 u8 reserved_at_40[0x40]; 999 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 1000 }; 1001 1002 struct mlx5_ifc_query_flow_counter_in_bits { 1003 u8 opcode[0x10]; 1004 u8 reserved_at_10[0x10]; 1005 u8 reserved_at_20[0x10]; 1006 u8 op_mod[0x10]; 1007 u8 reserved_at_40[0x20]; 1008 u8 mkey[0x20]; 1009 u8 address[0x40]; 1010 u8 clear[0x1]; 1011 u8 dump_to_memory[0x1]; 1012 u8 num_of_counters[0x1e]; 1013 u8 flow_counter_id[0x20]; 1014 }; 1015 1016 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u 1017 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u 1018 1019 1020 struct mlx5_ifc_klm_bits { 1021 u8 byte_count[0x20]; 1022 u8 mkey[0x20]; 1023 u8 address[0x40]; 1024 }; 1025 1026 struct mlx5_ifc_mkc_bits { 1027 u8 reserved_at_0[0x1]; 1028 u8 free[0x1]; 1029 u8 reserved_at_2[0x1]; 1030 u8 access_mode_4_2[0x3]; 1031 u8 reserved_at_6[0x7]; 1032 u8 relaxed_ordering_write[0x1]; 1033 u8 reserved_at_e[0x1]; 1034 u8 small_fence_on_rdma_read_response[0x1]; 1035 u8 umr_en[0x1]; 1036 u8 a[0x1]; 1037 u8 rw[0x1]; 1038 u8 rr[0x1]; 1039 u8 lw[0x1]; 1040 u8 lr[0x1]; 1041 u8 access_mode_1_0[0x2]; 1042 u8 reserved_at_18[0x8]; 1043 1044 u8 qpn[0x18]; 1045 u8 mkey_7_0[0x8]; 1046 1047 u8 reserved_at_40[0x20]; 1048 1049 u8 length64[0x1]; 1050 u8 bsf_en[0x1]; 1051 u8 sync_umr[0x1]; 1052 u8 reserved_at_63[0x2]; 1053 u8 expected_sigerr_count[0x1]; 1054 u8 reserved_at_66[0x1]; 1055 u8 en_rinval[0x1]; 1056 u8 pd[0x18]; 1057 1058 u8 start_addr[0x40]; 1059 1060 u8 len[0x40]; 1061 1062 u8 bsf_octword_size[0x20]; 1063 1064 u8 reserved_at_120[0x80]; 1065 1066 u8 translations_octword_size[0x20]; 1067 1068 u8 reserved_at_1c0[0x19]; 1069 u8 relaxed_ordering_read[0x1]; 1070 u8 reserved_at_1da[0x1]; 1071 u8 log_page_size[0x5]; 1072 1073 u8 reserved_at_1e0[0x20]; 1074 }; 1075 1076 struct mlx5_ifc_create_mkey_out_bits { 1077 u8 status[0x8]; 1078 u8 reserved_at_8[0x18]; 1079 1080 u8 syndrome[0x20]; 1081 1082 u8 reserved_at_40[0x8]; 1083 u8 mkey_index[0x18]; 1084 1085 u8 reserved_at_60[0x20]; 1086 }; 1087 1088 struct mlx5_ifc_create_mkey_in_bits { 1089 u8 opcode[0x10]; 1090 u8 reserved_at_10[0x10]; 1091 1092 u8 reserved_at_20[0x10]; 1093 u8 op_mod[0x10]; 1094 1095 u8 reserved_at_40[0x20]; 1096 1097 u8 pg_access[0x1]; 1098 u8 reserved_at_61[0x1f]; 1099 1100 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 1101 1102 u8 reserved_at_280[0x80]; 1103 1104 u8 translations_octword_actual_size[0x20]; 1105 1106 u8 mkey_umem_id[0x20]; 1107 1108 u8 mkey_umem_offset[0x40]; 1109 1110 u8 reserved_at_380[0x500]; 1111 1112 u8 klm_pas_mtt[][0x20]; 1113 }; 1114 1115 enum { 1116 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, 1117 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, 1118 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1, 1119 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, 1120 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, 1121 }; 1122 1123 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \ 1124 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ) 1125 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \ 1126 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS) 1127 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \ 1128 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH) 1129 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \ 1130 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO) 1131 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ 1132 (1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT) 1133 1134 enum { 1135 MLX5_HCA_CAP_OPMOD_GET_MAX = 0, 1136 MLX5_HCA_CAP_OPMOD_GET_CUR = 1, 1137 }; 1138 1139 enum { 1140 MLX5_CAP_INLINE_MODE_L2, 1141 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT, 1142 MLX5_CAP_INLINE_MODE_NOT_REQUIRED, 1143 }; 1144 1145 enum { 1146 MLX5_INLINE_MODE_NONE, 1147 MLX5_INLINE_MODE_L2, 1148 MLX5_INLINE_MODE_IP, 1149 MLX5_INLINE_MODE_TCP_UDP, 1150 MLX5_INLINE_MODE_RESERVED4, 1151 MLX5_INLINE_MODE_INNER_L2, 1152 MLX5_INLINE_MODE_INNER_IP, 1153 MLX5_INLINE_MODE_INNER_TCP_UDP, 1154 }; 1155 1156 /* HCA bit masks indicating which Flex parser protocols are already enabled. */ 1157 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0) 1158 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1) 1159 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2) 1160 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3) 1161 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4) 1162 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5) 1163 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6) 1164 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7) 1165 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8) 1166 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9) 1167 1168 struct mlx5_ifc_cmd_hca_cap_bits { 1169 u8 reserved_at_0[0x30]; 1170 u8 vhca_id[0x10]; 1171 u8 reserved_at_40[0x20]; 1172 u8 reserved_at_60[0x3]; 1173 u8 log_regexp_scatter_gather_size[0x5]; 1174 u8 reserved_at_68[0x3]; 1175 u8 log_dma_mmo_size[0x5]; 1176 u8 reserved_at_70[0x3]; 1177 u8 log_compress_mmo_size[0x5]; 1178 u8 reserved_at_78[0x3]; 1179 u8 log_decompress_mmo_size[0x5]; 1180 u8 log_max_srq_sz[0x8]; 1181 u8 log_max_qp_sz[0x8]; 1182 u8 reserved_at_90[0x9]; 1183 u8 wqe_index_ignore_cap[0x1]; 1184 u8 dynamic_qp_allocation[0x1]; 1185 u8 log_max_qp[0x5]; 1186 u8 regexp[0x1]; 1187 u8 reserved_at_a1[0x3]; 1188 u8 regexp_num_of_engines[0x4]; 1189 u8 reserved_at_a8[0x1]; 1190 u8 reg_c_preserve[0x1]; 1191 u8 reserved_at_aa[0x1]; 1192 u8 log_max_srq[0x5]; 1193 u8 reserved_at_b0[0x3]; 1194 u8 regexp_log_crspace_size[0x5]; 1195 u8 reserved_at_b8[0x3]; 1196 u8 scatter_fcs_w_decap_disable[0x1]; 1197 u8 reserved_at_bc[0x4]; 1198 u8 reserved_at_c0[0x8]; 1199 u8 log_max_cq_sz[0x8]; 1200 u8 reserved_at_d0[0xb]; 1201 u8 log_max_cq[0x5]; 1202 u8 log_max_eq_sz[0x8]; 1203 u8 relaxed_ordering_write[0x1]; 1204 u8 relaxed_ordering_read[0x1]; 1205 u8 access_register_user[0x1]; 1206 u8 log_max_mkey[0x5]; 1207 u8 reserved_at_f0[0x8]; 1208 u8 dump_fill_mkey[0x1]; 1209 u8 reserved_at_f9[0x3]; 1210 u8 log_max_eq[0x4]; 1211 u8 max_indirection[0x8]; 1212 u8 fixed_buffer_size[0x1]; 1213 u8 log_max_mrw_sz[0x7]; 1214 u8 force_teardown[0x1]; 1215 u8 reserved_at_111[0x1]; 1216 u8 log_max_bsf_list_size[0x6]; 1217 u8 umr_extended_translation_offset[0x1]; 1218 u8 null_mkey[0x1]; 1219 u8 log_max_klm_list_size[0x6]; 1220 u8 non_wire_sq[0x1]; 1221 u8 reserved_at_121[0x9]; 1222 u8 log_max_ra_req_dc[0x6]; 1223 u8 reserved_at_130[0x3]; 1224 u8 log_max_static_sq_wq[0x5]; 1225 u8 reserved_at_138[0x2]; 1226 u8 log_max_ra_res_dc[0x6]; 1227 u8 reserved_at_140[0xa]; 1228 u8 log_max_ra_req_qp[0x6]; 1229 u8 rtr2rts_qp_counters_set_id[0x1]; 1230 u8 rts2rts_udp_sport[0x1]; 1231 u8 rts2rts_lag_tx_port_affinity[0x1]; 1232 u8 dma_mmo[0x1]; 1233 u8 compress_min_block_size[0x4]; 1234 u8 compress[0x1]; 1235 u8 decompress[0x1]; 1236 u8 log_max_ra_res_qp[0x6]; 1237 u8 end_pad[0x1]; 1238 u8 cc_query_allowed[0x1]; 1239 u8 cc_modify_allowed[0x1]; 1240 u8 start_pad[0x1]; 1241 u8 cache_line_128byte[0x1]; 1242 u8 reserved_at_165[0xa]; 1243 u8 qcam_reg[0x1]; 1244 u8 gid_table_size[0x10]; 1245 u8 out_of_seq_cnt[0x1]; 1246 u8 vport_counters[0x1]; 1247 u8 retransmission_q_counters[0x1]; 1248 u8 debug[0x1]; 1249 u8 modify_rq_counter_set_id[0x1]; 1250 u8 rq_delay_drop[0x1]; 1251 u8 max_qp_cnt[0xa]; 1252 u8 pkey_table_size[0x10]; 1253 u8 vport_group_manager[0x1]; 1254 u8 vhca_group_manager[0x1]; 1255 u8 ib_virt[0x1]; 1256 u8 eth_virt[0x1]; 1257 u8 vnic_env_queue_counters[0x1]; 1258 u8 ets[0x1]; 1259 u8 nic_flow_table[0x1]; 1260 u8 eswitch_manager[0x1]; 1261 u8 device_memory[0x1]; 1262 u8 mcam_reg[0x1]; 1263 u8 pcam_reg[0x1]; 1264 u8 local_ca_ack_delay[0x5]; 1265 u8 port_module_event[0x1]; 1266 u8 enhanced_error_q_counters[0x1]; 1267 u8 ports_check[0x1]; 1268 u8 reserved_at_1b3[0x1]; 1269 u8 disable_link_up[0x1]; 1270 u8 beacon_led[0x1]; 1271 u8 port_type[0x2]; 1272 u8 num_ports[0x8]; 1273 u8 reserved_at_1c0[0x1]; 1274 u8 pps[0x1]; 1275 u8 pps_modify[0x1]; 1276 u8 log_max_msg[0x5]; 1277 u8 reserved_at_1c8[0x4]; 1278 u8 max_tc[0x4]; 1279 u8 temp_warn_event[0x1]; 1280 u8 dcbx[0x1]; 1281 u8 general_notification_event[0x1]; 1282 u8 reserved_at_1d3[0x2]; 1283 u8 fpga[0x1]; 1284 u8 rol_s[0x1]; 1285 u8 rol_g[0x1]; 1286 u8 reserved_at_1d8[0x1]; 1287 u8 wol_s[0x1]; 1288 u8 wol_g[0x1]; 1289 u8 wol_a[0x1]; 1290 u8 wol_b[0x1]; 1291 u8 wol_m[0x1]; 1292 u8 wol_u[0x1]; 1293 u8 wol_p[0x1]; 1294 u8 stat_rate_support[0x10]; 1295 u8 reserved_at_1f0[0xc]; 1296 u8 cqe_version[0x4]; 1297 u8 compact_address_vector[0x1]; 1298 u8 striding_rq[0x1]; 1299 u8 reserved_at_202[0x1]; 1300 u8 ipoib_enhanced_offloads[0x1]; 1301 u8 ipoib_basic_offloads[0x1]; 1302 u8 reserved_at_205[0x1]; 1303 u8 repeated_block_disabled[0x1]; 1304 u8 umr_modify_entity_size_disabled[0x1]; 1305 u8 umr_modify_atomic_disabled[0x1]; 1306 u8 umr_indirect_mkey_disabled[0x1]; 1307 u8 umr_fence[0x2]; 1308 u8 reserved_at_20c[0x3]; 1309 u8 drain_sigerr[0x1]; 1310 u8 cmdif_checksum[0x2]; 1311 u8 sigerr_cqe[0x1]; 1312 u8 reserved_at_213[0x1]; 1313 u8 wq_signature[0x1]; 1314 u8 sctr_data_cqe[0x1]; 1315 u8 reserved_at_216[0x1]; 1316 u8 sho[0x1]; 1317 u8 tph[0x1]; 1318 u8 rf[0x1]; 1319 u8 dct[0x1]; 1320 u8 qos[0x1]; 1321 u8 eth_net_offloads[0x1]; 1322 u8 roce[0x1]; 1323 u8 atomic[0x1]; 1324 u8 reserved_at_21f[0x1]; 1325 u8 cq_oi[0x1]; 1326 u8 cq_resize[0x1]; 1327 u8 cq_moderation[0x1]; 1328 u8 reserved_at_223[0x3]; 1329 u8 cq_eq_remap[0x1]; 1330 u8 pg[0x1]; 1331 u8 block_lb_mc[0x1]; 1332 u8 reserved_at_229[0x1]; 1333 u8 scqe_break_moderation[0x1]; 1334 u8 cq_period_start_from_cqe[0x1]; 1335 u8 cd[0x1]; 1336 u8 reserved_at_22d[0x1]; 1337 u8 apm[0x1]; 1338 u8 vector_calc[0x1]; 1339 u8 umr_ptr_rlky[0x1]; 1340 u8 imaicl[0x1]; 1341 u8 reserved_at_232[0x4]; 1342 u8 qkv[0x1]; 1343 u8 pkv[0x1]; 1344 u8 set_deth_sqpn[0x1]; 1345 u8 reserved_at_239[0x3]; 1346 u8 xrc[0x1]; 1347 u8 ud[0x1]; 1348 u8 uc[0x1]; 1349 u8 rc[0x1]; 1350 u8 uar_4k[0x1]; 1351 u8 reserved_at_241[0x9]; 1352 u8 uar_sz[0x6]; 1353 u8 reserved_at_250[0x8]; 1354 u8 log_pg_sz[0x8]; 1355 u8 bf[0x1]; 1356 u8 driver_version[0x1]; 1357 u8 pad_tx_eth_packet[0x1]; 1358 u8 reserved_at_263[0x8]; 1359 u8 log_bf_reg_size[0x5]; 1360 u8 reserved_at_270[0xb]; 1361 u8 lag_master[0x1]; 1362 u8 num_lag_ports[0x4]; 1363 u8 reserved_at_280[0x10]; 1364 u8 max_wqe_sz_sq[0x10]; 1365 u8 reserved_at_2a0[0x10]; 1366 u8 max_wqe_sz_rq[0x10]; 1367 u8 max_flow_counter_31_16[0x10]; 1368 u8 max_wqe_sz_sq_dc[0x10]; 1369 u8 reserved_at_2e0[0x7]; 1370 u8 max_qp_mcg[0x19]; 1371 u8 reserved_at_300[0x10]; 1372 u8 flow_counter_bulk_alloc[0x08]; 1373 u8 log_max_mcg[0x8]; 1374 u8 reserved_at_320[0x3]; 1375 u8 log_max_transport_domain[0x5]; 1376 u8 reserved_at_328[0x3]; 1377 u8 log_max_pd[0x5]; 1378 u8 reserved_at_330[0xb]; 1379 u8 log_max_xrcd[0x5]; 1380 u8 nic_receive_steering_discard[0x1]; 1381 u8 receive_discard_vport_down[0x1]; 1382 u8 transmit_discard_vport_down[0x1]; 1383 u8 reserved_at_343[0x5]; 1384 u8 log_max_flow_counter_bulk[0x8]; 1385 u8 max_flow_counter_15_0[0x10]; 1386 u8 modify_tis[0x1]; 1387 u8 flow_counters_dump[0x1]; 1388 u8 reserved_at_360[0x1]; 1389 u8 log_max_rq[0x5]; 1390 u8 reserved_at_368[0x3]; 1391 u8 log_max_sq[0x5]; 1392 u8 reserved_at_370[0x3]; 1393 u8 log_max_tir[0x5]; 1394 u8 reserved_at_378[0x3]; 1395 u8 log_max_tis[0x5]; 1396 u8 basic_cyclic_rcv_wqe[0x1]; 1397 u8 reserved_at_381[0x2]; 1398 u8 log_max_rmp[0x5]; 1399 u8 reserved_at_388[0x3]; 1400 u8 log_max_rqt[0x5]; 1401 u8 reserved_at_390[0x3]; 1402 u8 log_max_rqt_size[0x5]; 1403 u8 reserved_at_398[0x3]; 1404 u8 log_max_tis_per_sq[0x5]; 1405 u8 ext_stride_num_range[0x1]; 1406 u8 reserved_at_3a1[0x2]; 1407 u8 log_max_stride_sz_rq[0x5]; 1408 u8 reserved_at_3a8[0x3]; 1409 u8 log_min_stride_sz_rq[0x5]; 1410 u8 reserved_at_3b0[0x3]; 1411 u8 log_max_stride_sz_sq[0x5]; 1412 u8 reserved_at_3b8[0x3]; 1413 u8 log_min_stride_sz_sq[0x5]; 1414 u8 hairpin[0x1]; 1415 u8 reserved_at_3c1[0x2]; 1416 u8 log_max_hairpin_queues[0x5]; 1417 u8 reserved_at_3c8[0x3]; 1418 u8 log_max_hairpin_wq_data_sz[0x5]; 1419 u8 reserved_at_3d0[0x3]; 1420 u8 log_max_hairpin_num_packets[0x5]; 1421 u8 reserved_at_3d8[0x3]; 1422 u8 log_max_wq_sz[0x5]; 1423 u8 nic_vport_change_event[0x1]; 1424 u8 disable_local_lb_uc[0x1]; 1425 u8 disable_local_lb_mc[0x1]; 1426 u8 log_min_hairpin_wq_data_sz[0x5]; 1427 u8 reserved_at_3e8[0x3]; 1428 u8 log_max_vlan_list[0x5]; 1429 u8 reserved_at_3f0[0x3]; 1430 u8 log_max_current_mc_list[0x5]; 1431 u8 reserved_at_3f8[0x3]; 1432 u8 log_max_current_uc_list[0x5]; 1433 u8 general_obj_types[0x40]; 1434 u8 reserved_at_440[0x20]; 1435 u8 reserved_at_460[0x10]; 1436 u8 max_num_eqs[0x10]; 1437 u8 reserved_at_480[0x3]; 1438 u8 log_max_l2_table[0x5]; 1439 u8 reserved_at_488[0x8]; 1440 u8 log_uar_page_sz[0x10]; 1441 u8 reserved_at_4a0[0x20]; 1442 u8 device_frequency_mhz[0x20]; 1443 u8 device_frequency_khz[0x20]; 1444 u8 reserved_at_500[0x20]; 1445 u8 num_of_uars_per_page[0x20]; 1446 u8 flex_parser_protocols[0x20]; 1447 u8 max_geneve_tlv_options[0x8]; 1448 u8 reserved_at_568[0x3]; 1449 u8 max_geneve_tlv_option_data_len[0x5]; 1450 u8 reserved_at_570[0x49]; 1451 u8 mini_cqe_resp_l3_l4_tag[0x1]; 1452 u8 mini_cqe_resp_flow_tag[0x1]; 1453 u8 enhanced_cqe_compression[0x1]; 1454 u8 mini_cqe_resp_stride_index[0x1]; 1455 u8 cqe_128_always[0x1]; 1456 u8 cqe_compression_128[0x1]; 1457 u8 cqe_compression[0x1]; 1458 u8 cqe_compression_timeout[0x10]; 1459 u8 cqe_compression_max_num[0x10]; 1460 u8 reserved_at_5e0[0x10]; 1461 u8 tag_matching[0x1]; 1462 u8 rndv_offload_rc[0x1]; 1463 u8 rndv_offload_dc[0x1]; 1464 u8 log_tag_matching_list_sz[0x5]; 1465 u8 reserved_at_5f8[0x3]; 1466 u8 log_max_xrq[0x5]; 1467 u8 affiliate_nic_vport_criteria[0x8]; 1468 u8 native_port_num[0x8]; 1469 u8 num_vhca_ports[0x8]; 1470 u8 reserved_at_618[0x6]; 1471 u8 sw_owner_id[0x1]; 1472 u8 reserved_at_61f[0x1e1]; 1473 }; 1474 1475 struct mlx5_ifc_qos_cap_bits { 1476 u8 packet_pacing[0x1]; 1477 u8 esw_scheduling[0x1]; 1478 u8 esw_bw_share[0x1]; 1479 u8 esw_rate_limit[0x1]; 1480 u8 reserved_at_4[0x1]; 1481 u8 packet_pacing_burst_bound[0x1]; 1482 u8 packet_pacing_typical_size[0x1]; 1483 u8 flow_meter_old[0x1]; 1484 u8 reserved_at_8[0x8]; 1485 u8 log_max_flow_meter[0x8]; 1486 u8 flow_meter_reg_id[0x8]; 1487 u8 wqe_rate_pp[0x1]; 1488 u8 reserved_at_25[0x7]; 1489 u8 flow_meter[0x1]; 1490 u8 reserved_at_2e[0x17]; 1491 u8 packet_pacing_max_rate[0x20]; 1492 u8 packet_pacing_min_rate[0x20]; 1493 u8 reserved_at_80[0x10]; 1494 u8 packet_pacing_rate_table_size[0x10]; 1495 u8 esw_element_type[0x10]; 1496 u8 esw_tsar_type[0x10]; 1497 u8 reserved_at_c0[0x10]; 1498 u8 max_qos_para_vport[0x10]; 1499 u8 max_tsar_bw_share[0x20]; 1500 u8 reserved_at_100[0x6e8]; 1501 }; 1502 1503 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1504 u8 csum_cap[0x1]; 1505 u8 vlan_cap[0x1]; 1506 u8 lro_cap[0x1]; 1507 u8 lro_psh_flag[0x1]; 1508 u8 lro_time_stamp[0x1]; 1509 u8 lro_max_msg_sz_mode[0x2]; 1510 u8 wqe_vlan_insert[0x1]; 1511 u8 self_lb_en_modifiable[0x1]; 1512 u8 self_lb_mc[0x1]; 1513 u8 self_lb_uc[0x1]; 1514 u8 max_lso_cap[0x5]; 1515 u8 multi_pkt_send_wqe[0x2]; 1516 u8 wqe_inline_mode[0x2]; 1517 u8 rss_ind_tbl_cap[0x4]; 1518 u8 reg_umr_sq[0x1]; 1519 u8 scatter_fcs[0x1]; 1520 u8 enhanced_multi_pkt_send_wqe[0x1]; 1521 u8 tunnel_lso_const_out_ip_id[0x1]; 1522 u8 tunnel_lro_gre[0x1]; 1523 u8 tunnel_lro_vxlan[0x1]; 1524 u8 tunnel_stateless_gre[0x1]; 1525 u8 tunnel_stateless_vxlan[0x1]; 1526 u8 swp[0x1]; 1527 u8 swp_csum[0x1]; 1528 u8 swp_lso[0x1]; 1529 u8 reserved_at_23[0x8]; 1530 u8 tunnel_stateless_gtp[0x1]; 1531 u8 reserved_at_25[0x4]; 1532 u8 max_vxlan_udp_ports[0x8]; 1533 u8 reserved_at_38[0x6]; 1534 u8 max_geneve_opt_len[0x1]; 1535 u8 tunnel_stateless_geneve_rx[0x1]; 1536 u8 reserved_at_40[0x10]; 1537 u8 lro_min_mss_size[0x10]; 1538 u8 reserved_at_60[0x120]; 1539 u8 lro_timer_supported_periods[4][0x20]; 1540 u8 reserved_at_200[0x600]; 1541 }; 1542 1543 enum { 1544 MLX5_VIRTQ_TYPE_SPLIT = 0, 1545 MLX5_VIRTQ_TYPE_PACKED = 1, 1546 }; 1547 1548 enum { 1549 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0, 1550 MLX5_VIRTQ_EVENT_MODE_QP = 1, 1551 MLX5_VIRTQ_EVENT_MODE_MSIX = 2, 1552 }; 1553 1554 struct mlx5_ifc_virtio_emulation_cap_bits { 1555 u8 desc_tunnel_offload_type[0x1]; 1556 u8 eth_frame_offload_type[0x1]; 1557 u8 virtio_version_1_0[0x1]; 1558 u8 tso_ipv4[0x1]; 1559 u8 tso_ipv6[0x1]; 1560 u8 tx_csum[0x1]; 1561 u8 rx_csum[0x1]; 1562 u8 reserved_at_7[0x1][0x9]; 1563 u8 event_mode[0x8]; 1564 u8 virtio_queue_type[0x8]; 1565 u8 reserved_at_20[0x13]; 1566 u8 log_doorbell_stride[0x5]; 1567 u8 reserved_at_3b[0x3]; 1568 u8 log_doorbell_bar_size[0x5]; 1569 u8 doorbell_bar_offset[0x40]; 1570 u8 reserved_at_80[0x8]; 1571 u8 max_num_virtio_queues[0x18]; 1572 u8 reserved_at_a0[0x60]; 1573 u8 umem_1_buffer_param_a[0x20]; 1574 u8 umem_1_buffer_param_b[0x20]; 1575 u8 umem_2_buffer_param_a[0x20]; 1576 u8 umem_2_buffer_param_b[0x20]; 1577 u8 umem_3_buffer_param_a[0x20]; 1578 u8 umem_3_buffer_param_b[0x20]; 1579 u8 reserved_at_1c0[0x620]; 1580 }; 1581 1582 struct mlx5_ifc_flow_table_prop_layout_bits { 1583 u8 ft_support[0x1]; 1584 u8 flow_tag[0x1]; 1585 u8 flow_counter[0x1]; 1586 u8 flow_modify_en[0x1]; 1587 u8 modify_root[0x1]; 1588 u8 identified_miss_table[0x1]; 1589 u8 flow_table_modify[0x1]; 1590 u8 reformat[0x1]; 1591 u8 decap[0x1]; 1592 u8 reset_root_to_default[0x1]; 1593 u8 pop_vlan[0x1]; 1594 u8 push_vlan[0x1]; 1595 u8 fpga_vendor_acceleration[0x1]; 1596 u8 pop_vlan_2[0x1]; 1597 u8 push_vlan_2[0x1]; 1598 u8 reformat_and_vlan_action[0x1]; 1599 u8 modify_and_vlan_action[0x1]; 1600 u8 sw_owner[0x1]; 1601 u8 reformat_l3_tunnel_to_l2[0x1]; 1602 u8 reformat_l2_to_l3_tunnel[0x1]; 1603 u8 reformat_and_modify_action[0x1]; 1604 u8 reserved_at_15[0x9]; 1605 u8 sw_owner_v2[0x1]; 1606 u8 reserved_at_1f[0x1]; 1607 u8 reserved_at_20[0x2]; 1608 u8 log_max_ft_size[0x6]; 1609 u8 log_max_modify_header_context[0x8]; 1610 u8 max_modify_header_actions[0x8]; 1611 u8 max_ft_level[0x8]; 1612 u8 reserved_at_40[0x8]; 1613 u8 log_max_ft_sampler_num[8]; 1614 u8 metadata_reg_b_width[0x8]; 1615 u8 metadata_reg_a_width[0x8]; 1616 u8 reserved_at_60[0x18]; 1617 u8 log_max_ft_num[0x8]; 1618 u8 reserved_at_80[0x10]; 1619 u8 log_max_flow_counter[0x8]; 1620 u8 log_max_destination[0x8]; 1621 u8 reserved_at_a0[0x18]; 1622 u8 log_max_flow[0x8]; 1623 u8 reserved_at_c0[0x140]; 1624 }; 1625 1626 struct mlx5_ifc_flow_table_nic_cap_bits { 1627 u8 reserved_at_0[0x200]; 1628 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties; 1629 }; 1630 1631 union mlx5_ifc_hca_cap_union_bits { 1632 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 1633 struct mlx5_ifc_per_protocol_networking_offload_caps_bits 1634 per_protocol_networking_offload_caps; 1635 struct mlx5_ifc_qos_cap_bits qos_cap; 1636 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps; 1637 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 1638 u8 reserved_at_0[0x8000]; 1639 }; 1640 1641 struct mlx5_ifc_set_action_in_bits { 1642 u8 action_type[0x4]; 1643 u8 field[0xc]; 1644 u8 reserved_at_10[0x3]; 1645 u8 offset[0x5]; 1646 u8 reserved_at_18[0x3]; 1647 u8 length[0x5]; 1648 u8 data[0x20]; 1649 }; 1650 1651 struct mlx5_ifc_query_hca_cap_out_bits { 1652 u8 status[0x8]; 1653 u8 reserved_at_8[0x18]; 1654 u8 syndrome[0x20]; 1655 u8 reserved_at_40[0x40]; 1656 union mlx5_ifc_hca_cap_union_bits capability; 1657 }; 1658 1659 struct mlx5_ifc_query_hca_cap_in_bits { 1660 u8 opcode[0x10]; 1661 u8 reserved_at_10[0x10]; 1662 u8 reserved_at_20[0x10]; 1663 u8 op_mod[0x10]; 1664 u8 reserved_at_40[0x40]; 1665 }; 1666 1667 struct mlx5_ifc_mac_address_layout_bits { 1668 u8 reserved_at_0[0x10]; 1669 u8 mac_addr_47_32[0x10]; 1670 u8 mac_addr_31_0[0x20]; 1671 }; 1672 1673 struct mlx5_ifc_nic_vport_context_bits { 1674 u8 reserved_at_0[0x5]; 1675 u8 min_wqe_inline_mode[0x3]; 1676 u8 reserved_at_8[0x15]; 1677 u8 disable_mc_local_lb[0x1]; 1678 u8 disable_uc_local_lb[0x1]; 1679 u8 roce_en[0x1]; 1680 u8 arm_change_event[0x1]; 1681 u8 reserved_at_21[0x1a]; 1682 u8 event_on_mtu[0x1]; 1683 u8 event_on_promisc_change[0x1]; 1684 u8 event_on_vlan_change[0x1]; 1685 u8 event_on_mc_address_change[0x1]; 1686 u8 event_on_uc_address_change[0x1]; 1687 u8 reserved_at_40[0xc]; 1688 u8 affiliation_criteria[0x4]; 1689 u8 affiliated_vhca_id[0x10]; 1690 u8 reserved_at_60[0xd0]; 1691 u8 mtu[0x10]; 1692 u8 system_image_guid[0x40]; 1693 u8 port_guid[0x40]; 1694 u8 node_guid[0x40]; 1695 u8 reserved_at_200[0x140]; 1696 u8 qkey_violation_counter[0x10]; 1697 u8 reserved_at_350[0x430]; 1698 u8 promisc_uc[0x1]; 1699 u8 promisc_mc[0x1]; 1700 u8 promisc_all[0x1]; 1701 u8 reserved_at_783[0x2]; 1702 u8 allowed_list_type[0x3]; 1703 u8 reserved_at_788[0xc]; 1704 u8 allowed_list_size[0xc]; 1705 struct mlx5_ifc_mac_address_layout_bits permanent_address; 1706 u8 reserved_at_7e0[0x20]; 1707 }; 1708 1709 struct mlx5_ifc_query_nic_vport_context_out_bits { 1710 u8 status[0x8]; 1711 u8 reserved_at_8[0x18]; 1712 u8 syndrome[0x20]; 1713 u8 reserved_at_40[0x40]; 1714 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 1715 }; 1716 1717 struct mlx5_ifc_query_nic_vport_context_in_bits { 1718 u8 opcode[0x10]; 1719 u8 reserved_at_10[0x10]; 1720 u8 reserved_at_20[0x10]; 1721 u8 op_mod[0x10]; 1722 u8 other_vport[0x1]; 1723 u8 reserved_at_41[0xf]; 1724 u8 vport_number[0x10]; 1725 u8 reserved_at_60[0x5]; 1726 u8 allowed_list_type[0x3]; 1727 u8 reserved_at_68[0x18]; 1728 }; 1729 1730 struct mlx5_ifc_tisc_bits { 1731 u8 strict_lag_tx_port_affinity[0x1]; 1732 u8 reserved_at_1[0x3]; 1733 u8 lag_tx_port_affinity[0x04]; 1734 u8 reserved_at_8[0x4]; 1735 u8 prio[0x4]; 1736 u8 reserved_at_10[0x10]; 1737 u8 reserved_at_20[0x100]; 1738 u8 reserved_at_120[0x8]; 1739 u8 transport_domain[0x18]; 1740 u8 reserved_at_140[0x8]; 1741 u8 underlay_qpn[0x18]; 1742 u8 reserved_at_160[0x3a0]; 1743 }; 1744 1745 struct mlx5_ifc_query_tis_out_bits { 1746 u8 status[0x8]; 1747 u8 reserved_at_8[0x18]; 1748 u8 syndrome[0x20]; 1749 u8 reserved_at_40[0x40]; 1750 struct mlx5_ifc_tisc_bits tis_context; 1751 }; 1752 1753 struct mlx5_ifc_query_tis_in_bits { 1754 u8 opcode[0x10]; 1755 u8 reserved_at_10[0x10]; 1756 u8 reserved_at_20[0x10]; 1757 u8 op_mod[0x10]; 1758 u8 reserved_at_40[0x8]; 1759 u8 tisn[0x18]; 1760 u8 reserved_at_60[0x20]; 1761 }; 1762 1763 struct mlx5_ifc_alloc_transport_domain_out_bits { 1764 u8 status[0x8]; 1765 u8 reserved_at_8[0x18]; 1766 u8 syndrome[0x20]; 1767 u8 reserved_at_40[0x8]; 1768 u8 transport_domain[0x18]; 1769 u8 reserved_at_60[0x20]; 1770 }; 1771 1772 struct mlx5_ifc_alloc_transport_domain_in_bits { 1773 u8 opcode[0x10]; 1774 u8 reserved_at_10[0x10]; 1775 u8 reserved_at_20[0x10]; 1776 u8 op_mod[0x10]; 1777 u8 reserved_at_40[0x40]; 1778 }; 1779 1780 enum { 1781 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1782 MLX5_WQ_TYPE_CYCLIC = 0x1, 1783 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1784 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1785 }; 1786 1787 enum { 1788 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1789 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1790 }; 1791 1792 struct mlx5_ifc_wq_bits { 1793 u8 wq_type[0x4]; 1794 u8 wq_signature[0x1]; 1795 u8 end_padding_mode[0x2]; 1796 u8 cd_slave[0x1]; 1797 u8 reserved_at_8[0x18]; 1798 u8 hds_skip_first_sge[0x1]; 1799 u8 log2_hds_buf_size[0x3]; 1800 u8 reserved_at_24[0x7]; 1801 u8 page_offset[0x5]; 1802 u8 lwm[0x10]; 1803 u8 reserved_at_40[0x8]; 1804 u8 pd[0x18]; 1805 u8 reserved_at_60[0x8]; 1806 u8 uar_page[0x18]; 1807 u8 dbr_addr[0x40]; 1808 u8 hw_counter[0x20]; 1809 u8 sw_counter[0x20]; 1810 u8 reserved_at_100[0xc]; 1811 u8 log_wq_stride[0x4]; 1812 u8 reserved_at_110[0x3]; 1813 u8 log_wq_pg_sz[0x5]; 1814 u8 reserved_at_118[0x3]; 1815 u8 log_wq_sz[0x5]; 1816 u8 dbr_umem_valid[0x1]; 1817 u8 wq_umem_valid[0x1]; 1818 u8 reserved_at_122[0x1]; 1819 u8 log_hairpin_num_packets[0x5]; 1820 u8 reserved_at_128[0x3]; 1821 u8 log_hairpin_data_sz[0x5]; 1822 u8 reserved_at_130[0x4]; 1823 u8 single_wqe_log_num_of_strides[0x4]; 1824 u8 two_byte_shift_en[0x1]; 1825 u8 reserved_at_139[0x4]; 1826 u8 single_stride_log_num_of_bytes[0x3]; 1827 u8 dbr_umem_id[0x20]; 1828 u8 wq_umem_id[0x20]; 1829 u8 wq_umem_offset[0x40]; 1830 u8 reserved_at_1c0[0x440]; 1831 }; 1832 1833 enum { 1834 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 1835 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 1836 }; 1837 1838 enum { 1839 MLX5_RQC_STATE_RST = 0x0, 1840 MLX5_RQC_STATE_RDY = 0x1, 1841 MLX5_RQC_STATE_ERR = 0x3, 1842 }; 1843 1844 struct mlx5_ifc_rqc_bits { 1845 u8 rlky[0x1]; 1846 u8 delay_drop_en[0x1]; 1847 u8 scatter_fcs[0x1]; 1848 u8 vsd[0x1]; 1849 u8 mem_rq_type[0x4]; 1850 u8 state[0x4]; 1851 u8 reserved_at_c[0x1]; 1852 u8 flush_in_error_en[0x1]; 1853 u8 hairpin[0x1]; 1854 u8 reserved_at_f[0x11]; 1855 u8 reserved_at_20[0x8]; 1856 u8 user_index[0x18]; 1857 u8 reserved_at_40[0x8]; 1858 u8 cqn[0x18]; 1859 u8 counter_set_id[0x8]; 1860 u8 reserved_at_68[0x18]; 1861 u8 reserved_at_80[0x8]; 1862 u8 rmpn[0x18]; 1863 u8 reserved_at_a0[0x8]; 1864 u8 hairpin_peer_sq[0x18]; 1865 u8 reserved_at_c0[0x10]; 1866 u8 hairpin_peer_vhca[0x10]; 1867 u8 reserved_at_e0[0xa0]; 1868 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */ 1869 }; 1870 1871 struct mlx5_ifc_create_rq_out_bits { 1872 u8 status[0x8]; 1873 u8 reserved_at_8[0x18]; 1874 u8 syndrome[0x20]; 1875 u8 reserved_at_40[0x8]; 1876 u8 rqn[0x18]; 1877 u8 reserved_at_60[0x20]; 1878 }; 1879 1880 struct mlx5_ifc_create_rq_in_bits { 1881 u8 opcode[0x10]; 1882 u8 uid[0x10]; 1883 u8 reserved_at_20[0x10]; 1884 u8 op_mod[0x10]; 1885 u8 reserved_at_40[0xc0]; 1886 struct mlx5_ifc_rqc_bits ctx; 1887 }; 1888 1889 struct mlx5_ifc_modify_rq_out_bits { 1890 u8 status[0x8]; 1891 u8 reserved_at_8[0x18]; 1892 u8 syndrome[0x20]; 1893 u8 reserved_at_40[0x40]; 1894 }; 1895 1896 struct mlx5_ifc_query_rq_out_bits { 1897 u8 status[0x8]; 1898 u8 reserved_at_8[0x18]; 1899 u8 syndrome[0x20]; 1900 u8 reserved_at_40[0xc0]; 1901 struct mlx5_ifc_rqc_bits rq_context; 1902 }; 1903 1904 struct mlx5_ifc_query_rq_in_bits { 1905 u8 opcode[0x10]; 1906 u8 reserved_at_10[0x10]; 1907 u8 reserved_at_20[0x10]; 1908 u8 op_mod[0x10]; 1909 u8 reserved_at_40[0x8]; 1910 u8 rqn[0x18]; 1911 u8 reserved_at_60[0x20]; 1912 }; 1913 1914 struct mlx5_ifc_create_tis_out_bits { 1915 u8 status[0x8]; 1916 u8 reserved_at_8[0x18]; 1917 u8 syndrome[0x20]; 1918 u8 reserved_at_40[0x8]; 1919 u8 tisn[0x18]; 1920 u8 reserved_at_60[0x20]; 1921 }; 1922 1923 struct mlx5_ifc_create_tis_in_bits { 1924 u8 opcode[0x10]; 1925 u8 uid[0x10]; 1926 u8 reserved_at_20[0x10]; 1927 u8 op_mod[0x10]; 1928 u8 reserved_at_40[0xc0]; 1929 struct mlx5_ifc_tisc_bits ctx; 1930 }; 1931 1932 enum { 1933 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0, 1934 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 1935 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 1936 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 1937 }; 1938 1939 struct mlx5_ifc_modify_rq_in_bits { 1940 u8 opcode[0x10]; 1941 u8 uid[0x10]; 1942 u8 reserved_at_20[0x10]; 1943 u8 op_mod[0x10]; 1944 u8 rq_state[0x4]; 1945 u8 reserved_at_44[0x4]; 1946 u8 rqn[0x18]; 1947 u8 reserved_at_60[0x20]; 1948 u8 modify_bitmask[0x40]; 1949 u8 reserved_at_c0[0x40]; 1950 struct mlx5_ifc_rqc_bits ctx; 1951 }; 1952 1953 enum { 1954 MLX5_L3_PROT_TYPE_IPV4 = 0, 1955 MLX5_L3_PROT_TYPE_IPV6 = 1, 1956 }; 1957 1958 enum { 1959 MLX5_L4_PROT_TYPE_TCP = 0, 1960 MLX5_L4_PROT_TYPE_UDP = 1, 1961 }; 1962 1963 enum { 1964 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1965 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1966 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1967 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1968 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1969 }; 1970 1971 struct mlx5_ifc_rx_hash_field_select_bits { 1972 u8 l3_prot_type[0x1]; 1973 u8 l4_prot_type[0x1]; 1974 u8 selected_fields[0x1e]; 1975 }; 1976 1977 enum { 1978 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 1979 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 1980 }; 1981 1982 enum { 1983 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 1984 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 1985 }; 1986 1987 enum { 1988 MLX5_RX_HASH_FN_NONE = 0x0, 1989 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 1990 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 1991 }; 1992 1993 enum { 1994 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 1995 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 1996 }; 1997 1998 enum { 1999 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0, 2000 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1, 2001 }; 2002 2003 struct mlx5_ifc_tirc_bits { 2004 u8 reserved_at_0[0x20]; 2005 u8 disp_type[0x4]; 2006 u8 reserved_at_24[0x1c]; 2007 u8 reserved_at_40[0x40]; 2008 u8 reserved_at_80[0x4]; 2009 u8 lro_timeout_period_usecs[0x10]; 2010 u8 lro_enable_mask[0x4]; 2011 u8 lro_max_msg_sz[0x8]; 2012 u8 reserved_at_a0[0x40]; 2013 u8 reserved_at_e0[0x8]; 2014 u8 inline_rqn[0x18]; 2015 u8 rx_hash_symmetric[0x1]; 2016 u8 reserved_at_101[0x1]; 2017 u8 tunneled_offload_en[0x1]; 2018 u8 reserved_at_103[0x5]; 2019 u8 indirect_table[0x18]; 2020 u8 rx_hash_fn[0x4]; 2021 u8 reserved_at_124[0x2]; 2022 u8 self_lb_block[0x2]; 2023 u8 transport_domain[0x18]; 2024 u8 rx_hash_toeplitz_key[10][0x20]; 2025 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2026 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2027 u8 reserved_at_2c0[0x4c0]; 2028 }; 2029 2030 struct mlx5_ifc_create_tir_out_bits { 2031 u8 status[0x8]; 2032 u8 reserved_at_8[0x18]; 2033 u8 syndrome[0x20]; 2034 u8 reserved_at_40[0x8]; 2035 u8 tirn[0x18]; 2036 u8 reserved_at_60[0x20]; 2037 }; 2038 2039 struct mlx5_ifc_create_tir_in_bits { 2040 u8 opcode[0x10]; 2041 u8 uid[0x10]; 2042 u8 reserved_at_20[0x10]; 2043 u8 op_mod[0x10]; 2044 u8 reserved_at_40[0xc0]; 2045 struct mlx5_ifc_tirc_bits ctx; 2046 }; 2047 2048 enum { 2049 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0, 2050 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1, 2051 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2, 2052 /* bit 3 - tunneled_offload_en modify not supported. */ 2053 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4, 2054 }; 2055 2056 struct mlx5_ifc_modify_tir_out_bits { 2057 u8 status[0x8]; 2058 u8 reserved_at_8[0x18]; 2059 u8 syndrome[0x20]; 2060 u8 reserved_at_40[0x40]; 2061 }; 2062 2063 struct mlx5_ifc_modify_tir_in_bits { 2064 u8 opcode[0x10]; 2065 u8 uid[0x10]; 2066 u8 reserved_at_20[0x10]; 2067 u8 op_mod[0x10]; 2068 u8 reserved_at_40[0x8]; 2069 u8 tirn[0x18]; 2070 u8 reserved_at_60[0x20]; 2071 u8 modify_bitmask[0x40]; 2072 u8 reserved_at_c0[0x40]; 2073 struct mlx5_ifc_tirc_bits ctx; 2074 }; 2075 2076 enum { 2077 MLX5_INLINE_Q_TYPE_RQ = 0x0, 2078 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1, 2079 }; 2080 2081 struct mlx5_ifc_rq_num_bits { 2082 u8 reserved_at_0[0x8]; 2083 u8 rq_num[0x18]; 2084 }; 2085 2086 struct mlx5_ifc_rqtc_bits { 2087 u8 reserved_at_0[0xa5]; 2088 u8 list_q_type[0x3]; 2089 u8 reserved_at_a8[0x8]; 2090 u8 rqt_max_size[0x10]; 2091 u8 reserved_at_c0[0x10]; 2092 u8 rqt_actual_size[0x10]; 2093 u8 reserved_at_e0[0x6a0]; 2094 struct mlx5_ifc_rq_num_bits rq_num[]; 2095 }; 2096 2097 struct mlx5_ifc_create_rqt_out_bits { 2098 u8 status[0x8]; 2099 u8 reserved_at_8[0x18]; 2100 u8 syndrome[0x20]; 2101 u8 reserved_at_40[0x8]; 2102 u8 rqtn[0x18]; 2103 u8 reserved_at_60[0x20]; 2104 }; 2105 2106 #ifdef PEDANTIC 2107 #pragma GCC diagnostic ignored "-Wpedantic" 2108 #endif 2109 struct mlx5_ifc_create_rqt_in_bits { 2110 u8 opcode[0x10]; 2111 u8 uid[0x10]; 2112 u8 reserved_at_20[0x10]; 2113 u8 op_mod[0x10]; 2114 u8 reserved_at_40[0xc0]; 2115 struct mlx5_ifc_rqtc_bits rqt_context; 2116 }; 2117 2118 struct mlx5_ifc_modify_rqt_in_bits { 2119 u8 opcode[0x10]; 2120 u8 uid[0x10]; 2121 u8 reserved_at_20[0x10]; 2122 u8 op_mod[0x10]; 2123 u8 reserved_at_40[0x8]; 2124 u8 rqtn[0x18]; 2125 u8 reserved_at_60[0x20]; 2126 u8 modify_bitmask[0x40]; 2127 u8 reserved_at_c0[0x40]; 2128 struct mlx5_ifc_rqtc_bits rqt_context; 2129 }; 2130 #ifdef PEDANTIC 2131 #pragma GCC diagnostic error "-Wpedantic" 2132 #endif 2133 2134 struct mlx5_ifc_modify_rqt_out_bits { 2135 u8 status[0x8]; 2136 u8 reserved_at_8[0x18]; 2137 u8 syndrome[0x20]; 2138 u8 reserved_at_40[0x40]; 2139 }; 2140 2141 enum { 2142 MLX5_SQC_STATE_RST = 0x0, 2143 MLX5_SQC_STATE_RDY = 0x1, 2144 MLX5_SQC_STATE_ERR = 0x3, 2145 }; 2146 2147 struct mlx5_ifc_sqc_bits { 2148 u8 rlky[0x1]; 2149 u8 cd_master[0x1]; 2150 u8 fre[0x1]; 2151 u8 flush_in_error_en[0x1]; 2152 u8 allow_multi_pkt_send_wqe[0x1]; 2153 u8 min_wqe_inline_mode[0x3]; 2154 u8 state[0x4]; 2155 u8 reg_umr[0x1]; 2156 u8 allow_swp[0x1]; 2157 u8 hairpin[0x1]; 2158 u8 non_wire[0x1]; 2159 u8 static_sq_wq[0x1]; 2160 u8 reserved_at_11[0xf]; 2161 u8 reserved_at_20[0x8]; 2162 u8 user_index[0x18]; 2163 u8 reserved_at_40[0x8]; 2164 u8 cqn[0x18]; 2165 u8 reserved_at_60[0x8]; 2166 u8 hairpin_peer_rq[0x18]; 2167 u8 reserved_at_80[0x10]; 2168 u8 hairpin_peer_vhca[0x10]; 2169 u8 reserved_at_a0[0x50]; 2170 u8 packet_pacing_rate_limit_index[0x10]; 2171 u8 tis_lst_sz[0x10]; 2172 u8 reserved_at_110[0x10]; 2173 u8 reserved_at_120[0x40]; 2174 u8 reserved_at_160[0x8]; 2175 u8 tis_num_0[0x18]; 2176 struct mlx5_ifc_wq_bits wq; 2177 }; 2178 2179 struct mlx5_ifc_query_sq_in_bits { 2180 u8 opcode[0x10]; 2181 u8 reserved_at_10[0x10]; 2182 u8 reserved_at_20[0x10]; 2183 u8 op_mod[0x10]; 2184 u8 reserved_at_40[0x8]; 2185 u8 sqn[0x18]; 2186 u8 reserved_at_60[0x20]; 2187 }; 2188 2189 struct mlx5_ifc_modify_sq_out_bits { 2190 u8 status[0x8]; 2191 u8 reserved_at_8[0x18]; 2192 u8 syndrome[0x20]; 2193 u8 reserved_at_40[0x40]; 2194 }; 2195 2196 struct mlx5_ifc_modify_sq_in_bits { 2197 u8 opcode[0x10]; 2198 u8 uid[0x10]; 2199 u8 reserved_at_20[0x10]; 2200 u8 op_mod[0x10]; 2201 u8 sq_state[0x4]; 2202 u8 reserved_at_44[0x4]; 2203 u8 sqn[0x18]; 2204 u8 reserved_at_60[0x20]; 2205 u8 modify_bitmask[0x40]; 2206 u8 reserved_at_c0[0x40]; 2207 struct mlx5_ifc_sqc_bits ctx; 2208 }; 2209 2210 struct mlx5_ifc_create_sq_out_bits { 2211 u8 status[0x8]; 2212 u8 reserved_at_8[0x18]; 2213 u8 syndrome[0x20]; 2214 u8 reserved_at_40[0x8]; 2215 u8 sqn[0x18]; 2216 u8 reserved_at_60[0x20]; 2217 }; 2218 2219 struct mlx5_ifc_create_sq_in_bits { 2220 u8 opcode[0x10]; 2221 u8 uid[0x10]; 2222 u8 reserved_at_20[0x10]; 2223 u8 op_mod[0x10]; 2224 u8 reserved_at_40[0xc0]; 2225 struct mlx5_ifc_sqc_bits ctx; 2226 }; 2227 2228 enum { 2229 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0), 2230 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1), 2231 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2), 2232 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3), 2233 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4), 2234 }; 2235 2236 struct mlx5_ifc_flow_meter_parameters_bits { 2237 u8 valid[0x1]; // 00h 2238 u8 bucket_overflow[0x1]; 2239 u8 start_color[0x2]; 2240 u8 both_buckets_on_green[0x1]; 2241 u8 meter_mode[0x2]; 2242 u8 reserved_at_1[0x19]; 2243 u8 reserved_at_2[0x20]; //04h 2244 u8 reserved_at_3[0x3]; 2245 u8 cbs_exponent[0x5]; // 08h 2246 u8 cbs_mantissa[0x8]; 2247 u8 reserved_at_4[0x3]; 2248 u8 cir_exponent[0x5]; 2249 u8 cir_mantissa[0x8]; 2250 u8 reserved_at_5[0x20]; // 0Ch 2251 u8 reserved_at_6[0x3]; 2252 u8 ebs_exponent[0x5]; // 10h 2253 u8 ebs_mantissa[0x8]; 2254 u8 reserved_at_7[0x3]; 2255 u8 eir_exponent[0x5]; 2256 u8 eir_mantissa[0x8]; 2257 u8 reserved_at_8[0x60]; // 14h-1Ch 2258 }; 2259 2260 enum { 2261 MLX5_CQE_SIZE_64B = 0x0, 2262 MLX5_CQE_SIZE_128B = 0x1, 2263 }; 2264 2265 struct mlx5_ifc_cqc_bits { 2266 u8 status[0x4]; 2267 u8 as_notify[0x1]; 2268 u8 initiator_src_dct[0x1]; 2269 u8 dbr_umem_valid[0x1]; 2270 u8 reserved_at_7[0x1]; 2271 u8 cqe_sz[0x3]; 2272 u8 cc[0x1]; 2273 u8 reserved_at_c[0x1]; 2274 u8 scqe_break_moderation_en[0x1]; 2275 u8 oi[0x1]; 2276 u8 cq_period_mode[0x2]; 2277 u8 cqe_comp_en[0x1]; 2278 u8 mini_cqe_res_format[0x2]; 2279 u8 st[0x4]; 2280 u8 reserved_at_18[0x1]; 2281 u8 cqe_comp_layout[0x7]; 2282 u8 dbr_umem_id[0x20]; 2283 u8 reserved_at_40[0x14]; 2284 u8 page_offset[0x6]; 2285 u8 reserved_at_5a[0x2]; 2286 u8 mini_cqe_res_format_ext[0x2]; 2287 u8 cq_timestamp_format[0x2]; 2288 u8 reserved_at_60[0x3]; 2289 u8 log_cq_size[0x5]; 2290 u8 uar_page[0x18]; 2291 u8 reserved_at_80[0x4]; 2292 u8 cq_period[0xc]; 2293 u8 cq_max_count[0x10]; 2294 u8 reserved_at_a0[0x18]; 2295 u8 c_eqn[0x8]; 2296 u8 reserved_at_c0[0x3]; 2297 u8 log_page_size[0x5]; 2298 u8 reserved_at_c8[0x18]; 2299 u8 reserved_at_e0[0x20]; 2300 u8 reserved_at_100[0x8]; 2301 u8 last_notified_index[0x18]; 2302 u8 reserved_at_120[0x8]; 2303 u8 last_solicit_index[0x18]; 2304 u8 reserved_at_140[0x8]; 2305 u8 consumer_counter[0x18]; 2306 u8 reserved_at_160[0x8]; 2307 u8 producer_counter[0x18]; 2308 u8 local_partition_id[0xc]; 2309 u8 process_id[0x14]; 2310 u8 reserved_at_1A0[0x20]; 2311 u8 dbr_addr[0x40]; 2312 }; 2313 2314 struct mlx5_ifc_health_buffer_bits { 2315 u8 reserved_0[0x100]; 2316 u8 assert_existptr[0x20]; 2317 u8 assert_callra[0x20]; 2318 u8 reserved_1[0x40]; 2319 u8 fw_version[0x20]; 2320 u8 hw_id[0x20]; 2321 u8 reserved_2[0x20]; 2322 u8 irisc_index[0x8]; 2323 u8 synd[0x8]; 2324 u8 ext_synd[0x10]; 2325 }; 2326 2327 struct mlx5_ifc_initial_seg_bits { 2328 u8 fw_rev_minor[0x10]; 2329 u8 fw_rev_major[0x10]; 2330 u8 cmd_interface_rev[0x10]; 2331 u8 fw_rev_subminor[0x10]; 2332 u8 reserved_0[0x40]; 2333 u8 cmdq_phy_addr_63_32[0x20]; 2334 u8 cmdq_phy_addr_31_12[0x14]; 2335 u8 reserved_1[0x2]; 2336 u8 nic_interface[0x2]; 2337 u8 log_cmdq_size[0x4]; 2338 u8 log_cmdq_stride[0x4]; 2339 u8 command_doorbell_vector[0x20]; 2340 u8 reserved_2[0xf00]; 2341 u8 initializing[0x1]; 2342 u8 nic_interface_supported[0x7]; 2343 u8 reserved_4[0x18]; 2344 struct mlx5_ifc_health_buffer_bits health_buffer; 2345 u8 no_dram_nic_offset[0x20]; 2346 u8 reserved_5[0x6de0]; 2347 u8 internal_timer_h[0x20]; 2348 u8 internal_timer_l[0x20]; 2349 u8 reserved_6[0x20]; 2350 u8 reserved_7[0x1f]; 2351 u8 clear_int[0x1]; 2352 u8 health_syndrome[0x8]; 2353 u8 health_counter[0x18]; 2354 u8 reserved_8[0x17fc0]; 2355 }; 2356 2357 struct mlx5_ifc_create_cq_out_bits { 2358 u8 status[0x8]; 2359 u8 reserved_at_8[0x18]; 2360 u8 syndrome[0x20]; 2361 u8 reserved_at_40[0x8]; 2362 u8 cqn[0x18]; 2363 u8 reserved_at_60[0x20]; 2364 }; 2365 2366 struct mlx5_ifc_create_cq_in_bits { 2367 u8 opcode[0x10]; 2368 u8 uid[0x10]; 2369 u8 reserved_at_20[0x10]; 2370 u8 op_mod[0x10]; 2371 u8 reserved_at_40[0x40]; 2372 struct mlx5_ifc_cqc_bits cq_context; 2373 u8 cq_umem_offset[0x40]; 2374 u8 cq_umem_id[0x20]; 2375 u8 cq_umem_valid[0x1]; 2376 u8 reserved_at_2e1[0x1f]; 2377 u8 reserved_at_300[0x580]; 2378 u8 pas[]; 2379 }; 2380 2381 enum { 2382 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 2383 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, 2384 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 2385 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, 2386 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, 2387 }; 2388 2389 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 2390 u8 opcode[0x10]; 2391 u8 reserved_at_10[0x20]; 2392 u8 obj_type[0x10]; 2393 u8 obj_id[0x20]; 2394 u8 reserved_at_60[0x20]; 2395 }; 2396 2397 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 2398 u8 status[0x8]; 2399 u8 reserved_at_8[0x18]; 2400 u8 syndrome[0x20]; 2401 u8 obj_id[0x20]; 2402 u8 reserved_at_60[0x20]; 2403 }; 2404 2405 struct mlx5_ifc_virtio_q_counters_bits { 2406 u8 modify_field_select[0x40]; 2407 u8 reserved_at_40[0x40]; 2408 u8 received_desc[0x40]; 2409 u8 completed_desc[0x40]; 2410 u8 error_cqes[0x20]; 2411 u8 bad_desc_errors[0x20]; 2412 u8 exceed_max_chain[0x20]; 2413 u8 invalid_buffer[0x20]; 2414 u8 reserved_at_180[0x50]; 2415 }; 2416 2417 struct mlx5_ifc_geneve_tlv_option_bits { 2418 u8 modify_field_select[0x40]; 2419 u8 reserved_at_40[0x18]; 2420 u8 geneve_option_fte_index[0x8]; 2421 u8 option_class[0x10]; 2422 u8 option_type[0x8]; 2423 u8 reserved_at_78[0x3]; 2424 u8 option_data_length[0x5]; 2425 u8 reserved_at_80[0x180]; 2426 }; 2427 2428 struct mlx5_ifc_create_virtio_q_counters_in_bits { 2429 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2430 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 2431 }; 2432 2433 struct mlx5_ifc_query_virtio_q_counters_out_bits { 2434 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2435 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 2436 }; 2437 2438 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 2439 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2440 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 2441 }; 2442 2443 enum { 2444 MLX5_VIRTQ_STATE_INIT = 0, 2445 MLX5_VIRTQ_STATE_RDY = 1, 2446 MLX5_VIRTQ_STATE_SUSPEND = 2, 2447 MLX5_VIRTQ_STATE_ERROR = 3, 2448 }; 2449 2450 enum { 2451 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0), 2452 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3), 2453 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4), 2454 }; 2455 2456 struct mlx5_ifc_virtio_q_bits { 2457 u8 virtio_q_type[0x8]; 2458 u8 reserved_at_8[0x5]; 2459 u8 event_mode[0x3]; 2460 u8 queue_index[0x10]; 2461 u8 full_emulation[0x1]; 2462 u8 virtio_version_1_0[0x1]; 2463 u8 reserved_at_22[0x2]; 2464 u8 offload_type[0x4]; 2465 u8 event_qpn_or_msix[0x18]; 2466 u8 doorbell_stride_idx[0x10]; 2467 u8 queue_size[0x10]; 2468 u8 device_emulation_id[0x20]; 2469 u8 desc_addr[0x40]; 2470 u8 used_addr[0x40]; 2471 u8 available_addr[0x40]; 2472 u8 virtio_q_mkey[0x20]; 2473 u8 reserved_at_160[0x18]; 2474 u8 error_type[0x8]; 2475 u8 umem_1_id[0x20]; 2476 u8 umem_1_size[0x20]; 2477 u8 umem_1_offset[0x40]; 2478 u8 umem_2_id[0x20]; 2479 u8 umem_2_size[0x20]; 2480 u8 umem_2_offset[0x40]; 2481 u8 umem_3_id[0x20]; 2482 u8 umem_3_size[0x20]; 2483 u8 umem_3_offset[0x40]; 2484 u8 counter_set_id[0x20]; 2485 u8 reserved_at_320[0x8]; 2486 u8 pd[0x18]; 2487 u8 reserved_at_340[0x2]; 2488 u8 queue_period_mode[0x2]; 2489 u8 queue_period_us[0xc]; 2490 u8 queue_max_count[0x10]; 2491 u8 reserved_at_360[0xa0]; 2492 }; 2493 2494 struct mlx5_ifc_virtio_net_q_bits { 2495 u8 modify_field_select[0x40]; 2496 u8 reserved_at_40[0x40]; 2497 u8 tso_ipv4[0x1]; 2498 u8 tso_ipv6[0x1]; 2499 u8 tx_csum[0x1]; 2500 u8 rx_csum[0x1]; 2501 u8 reserved_at_84[0x6]; 2502 u8 dirty_bitmap_dump_enable[0x1]; 2503 u8 vhost_log_page[0x5]; 2504 u8 reserved_at_90[0xc]; 2505 u8 state[0x4]; 2506 u8 reserved_at_a0[0x8]; 2507 u8 tisn_or_qpn[0x18]; 2508 u8 dirty_bitmap_mkey[0x20]; 2509 u8 dirty_bitmap_size[0x20]; 2510 u8 dirty_bitmap_addr[0x40]; 2511 u8 hw_available_index[0x10]; 2512 u8 hw_used_index[0x10]; 2513 u8 reserved_at_160[0xa0]; 2514 struct mlx5_ifc_virtio_q_bits virtio_q_context; 2515 }; 2516 2517 struct mlx5_ifc_create_virtq_in_bits { 2518 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2519 struct mlx5_ifc_virtio_net_q_bits virtq; 2520 }; 2521 2522 struct mlx5_ifc_query_virtq_out_bits { 2523 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2524 struct mlx5_ifc_virtio_net_q_bits virtq; 2525 }; 2526 2527 struct mlx5_ifc_flow_hit_aso_bits { 2528 u8 modify_field_select[0x40]; 2529 u8 reserved_at_40[0x48]; 2530 u8 access_pd[0x18]; 2531 u8 reserved_at_a0[0x160]; 2532 u8 flag[0x200]; 2533 }; 2534 2535 struct mlx5_ifc_create_flow_hit_aso_in_bits { 2536 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2537 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso; 2538 }; 2539 2540 enum mlx5_access_aso_opc_mod { 2541 ASO_OPC_MOD_IPSEC = 0x0, 2542 ASO_OPC_MOD_CONNECTION_TRACKING = 0x1, 2543 ASO_OPC_MOD_POLICER = 0x2, 2544 ASO_OPC_MOD_RACE_AVOIDANCE = 0x3, 2545 ASO_OPC_MOD_FLOW_HIT = 0x4, 2546 }; 2547 2548 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30 2549 2550 enum mlx5_aso_data_mask_mode { 2551 BITWISE_64BIT = 0x0, 2552 BYTEWISE_64BYTE = 0x1, 2553 CALCULATED_64BYTE = 0x2, 2554 }; 2555 2556 #define ASO_CSEG_COND_0_OPER_OFFSET 20 2557 #define ASO_CSEG_COND_1_OPER_OFFSET 16 2558 2559 enum mlx5_aso_pre_cond_op { 2560 ASO_OP_ALWAYS_FALSE = 0x0, 2561 ASO_OP_ALWAYS_TRUE = 0x1, 2562 ASO_OP_EQUAL = 0x2, 2563 ASO_OP_NOT_EQUAL = 0x3, 2564 ASO_OP_GREATER_OR_EQUAL = 0x4, 2565 ASO_OP_LESSER_OR_EQUAL = 0x5, 2566 ASO_OP_LESSER = 0x6, 2567 ASO_OP_GREATER = 0x7, 2568 ASO_OP_CYCLIC_GREATER = 0x8, 2569 ASO_OP_CYCLIC_LESSER = 0x9, 2570 }; 2571 2572 #define ASO_CSEG_COND_OPER_OFFSET 6 2573 2574 enum mlx5_aso_op { 2575 ASO_OPER_LOGICAL_AND = 0x0, 2576 ASO_OPER_LOGICAL_OR = 0x1, 2577 }; 2578 2579 /* ASO WQE CTRL segment. */ 2580 struct mlx5_aso_cseg { 2581 uint32_t va_h; 2582 uint32_t va_l_r; 2583 uint32_t lkey; 2584 uint32_t operand_masks; 2585 uint32_t condition_0_data; 2586 uint32_t condition_0_mask; 2587 uint32_t condition_1_data; 2588 uint32_t condition_1_mask; 2589 uint64_t bitwise_data; 2590 uint64_t data_mask; 2591 } __rte_packed; 2592 2593 #define MLX5_ASO_WQE_DSEG_SIZE 0x40 2594 2595 /* ASO WQE Data segment. */ 2596 struct mlx5_aso_dseg { 2597 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE]; 2598 } __rte_packed; 2599 2600 /* ASO WQE. */ 2601 struct mlx5_aso_wqe { 2602 struct mlx5_wqe_cseg general_cseg; 2603 struct mlx5_aso_cseg aso_cseg; 2604 struct mlx5_aso_dseg aso_dseg; 2605 } __rte_packed; 2606 2607 enum { 2608 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, 2609 }; 2610 2611 enum { 2612 MLX5_QP_ST_RC = 0x0, 2613 }; 2614 2615 enum { 2616 MLX5_QP_PM_MIGRATED = 0x3, 2617 }; 2618 2619 enum { 2620 MLX5_NON_ZERO_RQ = 0x0, 2621 MLX5_SRQ_RQ = 0x1, 2622 MLX5_CRQ_RQ = 0x2, 2623 MLX5_ZERO_LEN_RQ = 0x3, 2624 }; 2625 2626 struct mlx5_ifc_ads_bits { 2627 u8 fl[0x1]; 2628 u8 free_ar[0x1]; 2629 u8 reserved_at_2[0xe]; 2630 u8 pkey_index[0x10]; 2631 u8 reserved_at_20[0x8]; 2632 u8 grh[0x1]; 2633 u8 mlid[0x7]; 2634 u8 rlid[0x10]; 2635 u8 ack_timeout[0x5]; 2636 u8 reserved_at_45[0x3]; 2637 u8 src_addr_index[0x8]; 2638 u8 reserved_at_50[0x4]; 2639 u8 stat_rate[0x4]; 2640 u8 hop_limit[0x8]; 2641 u8 reserved_at_60[0x4]; 2642 u8 tclass[0x8]; 2643 u8 flow_label[0x14]; 2644 u8 rgid_rip[16][0x8]; 2645 u8 reserved_at_100[0x4]; 2646 u8 f_dscp[0x1]; 2647 u8 f_ecn[0x1]; 2648 u8 reserved_at_106[0x1]; 2649 u8 f_eth_prio[0x1]; 2650 u8 ecn[0x2]; 2651 u8 dscp[0x6]; 2652 u8 udp_sport[0x10]; 2653 u8 dei_cfi[0x1]; 2654 u8 eth_prio[0x3]; 2655 u8 sl[0x4]; 2656 u8 vhca_port_num[0x8]; 2657 u8 rmac_47_32[0x10]; 2658 u8 rmac_31_0[0x20]; 2659 }; 2660 2661 struct mlx5_ifc_qpc_bits { 2662 u8 state[0x4]; 2663 u8 lag_tx_port_affinity[0x4]; 2664 u8 st[0x8]; 2665 u8 reserved_at_10[0x3]; 2666 u8 pm_state[0x2]; 2667 u8 reserved_at_15[0x1]; 2668 u8 req_e2e_credit_mode[0x2]; 2669 u8 offload_type[0x4]; 2670 u8 end_padding_mode[0x2]; 2671 u8 reserved_at_1e[0x2]; 2672 u8 wq_signature[0x1]; 2673 u8 block_lb_mc[0x1]; 2674 u8 atomic_like_write_en[0x1]; 2675 u8 latency_sensitive[0x1]; 2676 u8 reserved_at_24[0x1]; 2677 u8 drain_sigerr[0x1]; 2678 u8 reserved_at_26[0x2]; 2679 u8 pd[0x18]; 2680 u8 mtu[0x3]; 2681 u8 log_msg_max[0x5]; 2682 u8 reserved_at_48[0x1]; 2683 u8 log_rq_size[0x4]; 2684 u8 log_rq_stride[0x3]; 2685 u8 no_sq[0x1]; 2686 u8 log_sq_size[0x4]; 2687 u8 reserved_at_55[0x6]; 2688 u8 rlky[0x1]; 2689 u8 ulp_stateless_offload_mode[0x4]; 2690 u8 counter_set_id[0x8]; 2691 u8 uar_page[0x18]; 2692 u8 reserved_at_80[0x8]; 2693 u8 user_index[0x18]; 2694 u8 reserved_at_a0[0x3]; 2695 u8 log_page_size[0x5]; 2696 u8 remote_qpn[0x18]; 2697 struct mlx5_ifc_ads_bits primary_address_path; 2698 struct mlx5_ifc_ads_bits secondary_address_path; 2699 u8 log_ack_req_freq[0x4]; 2700 u8 reserved_at_384[0x4]; 2701 u8 log_sra_max[0x3]; 2702 u8 reserved_at_38b[0x2]; 2703 u8 retry_count[0x3]; 2704 u8 rnr_retry[0x3]; 2705 u8 reserved_at_393[0x1]; 2706 u8 fre[0x1]; 2707 u8 cur_rnr_retry[0x3]; 2708 u8 cur_retry_count[0x3]; 2709 u8 reserved_at_39b[0x5]; 2710 u8 reserved_at_3a0[0x20]; 2711 u8 reserved_at_3c0[0x8]; 2712 u8 next_send_psn[0x18]; 2713 u8 reserved_at_3e0[0x8]; 2714 u8 cqn_snd[0x18]; 2715 u8 reserved_at_400[0x8]; 2716 u8 deth_sqpn[0x18]; 2717 u8 reserved_at_420[0x20]; 2718 u8 reserved_at_440[0x8]; 2719 u8 last_acked_psn[0x18]; 2720 u8 reserved_at_460[0x8]; 2721 u8 ssn[0x18]; 2722 u8 reserved_at_480[0x8]; 2723 u8 log_rra_max[0x3]; 2724 u8 reserved_at_48b[0x1]; 2725 u8 atomic_mode[0x4]; 2726 u8 rre[0x1]; 2727 u8 rwe[0x1]; 2728 u8 rae[0x1]; 2729 u8 reserved_at_493[0x1]; 2730 u8 page_offset[0x6]; 2731 u8 reserved_at_49a[0x3]; 2732 u8 cd_slave_receive[0x1]; 2733 u8 cd_slave_send[0x1]; 2734 u8 cd_master[0x1]; 2735 u8 reserved_at_4a0[0x3]; 2736 u8 min_rnr_nak[0x5]; 2737 u8 next_rcv_psn[0x18]; 2738 u8 reserved_at_4c0[0x8]; 2739 u8 xrcd[0x18]; 2740 u8 reserved_at_4e0[0x8]; 2741 u8 cqn_rcv[0x18]; 2742 u8 dbr_addr[0x40]; 2743 u8 q_key[0x20]; 2744 u8 reserved_at_560[0x5]; 2745 u8 rq_type[0x3]; 2746 u8 srqn_rmpn_xrqn[0x18]; 2747 u8 reserved_at_580[0x8]; 2748 u8 rmsn[0x18]; 2749 u8 hw_sq_wqebb_counter[0x10]; 2750 u8 sw_sq_wqebb_counter[0x10]; 2751 u8 hw_rq_counter[0x20]; 2752 u8 sw_rq_counter[0x20]; 2753 u8 reserved_at_600[0x20]; 2754 u8 reserved_at_620[0xf]; 2755 u8 cgs[0x1]; 2756 u8 cs_req[0x8]; 2757 u8 cs_res[0x8]; 2758 u8 dc_access_key[0x40]; 2759 u8 reserved_at_680[0x3]; 2760 u8 dbr_umem_valid[0x1]; 2761 u8 reserved_at_684[0x9c]; 2762 u8 dbr_umem_id[0x20]; 2763 }; 2764 2765 struct mlx5_ifc_create_qp_out_bits { 2766 u8 status[0x8]; 2767 u8 reserved_at_8[0x18]; 2768 u8 syndrome[0x20]; 2769 u8 reserved_at_40[0x8]; 2770 u8 qpn[0x18]; 2771 u8 reserved_at_60[0x20]; 2772 }; 2773 2774 #ifdef PEDANTIC 2775 #pragma GCC diagnostic ignored "-Wpedantic" 2776 #endif 2777 struct mlx5_ifc_create_qp_in_bits { 2778 u8 opcode[0x10]; 2779 u8 uid[0x10]; 2780 u8 reserved_at_20[0x10]; 2781 u8 op_mod[0x10]; 2782 u8 reserved_at_40[0x40]; 2783 u8 opt_param_mask[0x20]; 2784 u8 reserved_at_a0[0x20]; 2785 struct mlx5_ifc_qpc_bits qpc; 2786 u8 wq_umem_offset[0x40]; 2787 u8 wq_umem_id[0x20]; 2788 u8 wq_umem_valid[0x1]; 2789 u8 reserved_at_861[0x1f]; 2790 u8 pas[0][0x40]; 2791 }; 2792 #ifdef PEDANTIC 2793 #pragma GCC diagnostic error "-Wpedantic" 2794 #endif 2795 2796 struct mlx5_ifc_sqerr2rts_qp_out_bits { 2797 u8 status[0x8]; 2798 u8 reserved_at_8[0x18]; 2799 u8 syndrome[0x20]; 2800 u8 reserved_at_40[0x40]; 2801 }; 2802 2803 struct mlx5_ifc_sqerr2rts_qp_in_bits { 2804 u8 opcode[0x10]; 2805 u8 uid[0x10]; 2806 u8 reserved_at_20[0x10]; 2807 u8 op_mod[0x10]; 2808 u8 reserved_at_40[0x8]; 2809 u8 qpn[0x18]; 2810 u8 reserved_at_60[0x20]; 2811 u8 opt_param_mask[0x20]; 2812 u8 reserved_at_a0[0x20]; 2813 struct mlx5_ifc_qpc_bits qpc; 2814 u8 reserved_at_800[0x80]; 2815 }; 2816 2817 struct mlx5_ifc_sqd2rts_qp_out_bits { 2818 u8 status[0x8]; 2819 u8 reserved_at_8[0x18]; 2820 u8 syndrome[0x20]; 2821 u8 reserved_at_40[0x40]; 2822 }; 2823 2824 struct mlx5_ifc_sqd2rts_qp_in_bits { 2825 u8 opcode[0x10]; 2826 u8 uid[0x10]; 2827 u8 reserved_at_20[0x10]; 2828 u8 op_mod[0x10]; 2829 u8 reserved_at_40[0x8]; 2830 u8 qpn[0x18]; 2831 u8 reserved_at_60[0x20]; 2832 u8 opt_param_mask[0x20]; 2833 u8 reserved_at_a0[0x20]; 2834 struct mlx5_ifc_qpc_bits qpc; 2835 u8 reserved_at_800[0x80]; 2836 }; 2837 2838 struct mlx5_ifc_rts2rts_qp_out_bits { 2839 u8 status[0x8]; 2840 u8 reserved_at_8[0x18]; 2841 u8 syndrome[0x20]; 2842 u8 reserved_at_40[0x40]; 2843 }; 2844 2845 struct mlx5_ifc_rts2rts_qp_in_bits { 2846 u8 opcode[0x10]; 2847 u8 uid[0x10]; 2848 u8 reserved_at_20[0x10]; 2849 u8 op_mod[0x10]; 2850 u8 reserved_at_40[0x8]; 2851 u8 qpn[0x18]; 2852 u8 reserved_at_60[0x20]; 2853 u8 opt_param_mask[0x20]; 2854 u8 reserved_at_a0[0x20]; 2855 struct mlx5_ifc_qpc_bits qpc; 2856 u8 reserved_at_800[0x80]; 2857 }; 2858 2859 struct mlx5_ifc_rtr2rts_qp_out_bits { 2860 u8 status[0x8]; 2861 u8 reserved_at_8[0x18]; 2862 u8 syndrome[0x20]; 2863 u8 reserved_at_40[0x40]; 2864 }; 2865 2866 struct mlx5_ifc_rtr2rts_qp_in_bits { 2867 u8 opcode[0x10]; 2868 u8 uid[0x10]; 2869 u8 reserved_at_20[0x10]; 2870 u8 op_mod[0x10]; 2871 u8 reserved_at_40[0x8]; 2872 u8 qpn[0x18]; 2873 u8 reserved_at_60[0x20]; 2874 u8 opt_param_mask[0x20]; 2875 u8 reserved_at_a0[0x20]; 2876 struct mlx5_ifc_qpc_bits qpc; 2877 u8 reserved_at_800[0x80]; 2878 }; 2879 2880 struct mlx5_ifc_rst2init_qp_out_bits { 2881 u8 status[0x8]; 2882 u8 reserved_at_8[0x18]; 2883 u8 syndrome[0x20]; 2884 u8 reserved_at_40[0x40]; 2885 }; 2886 2887 struct mlx5_ifc_rst2init_qp_in_bits { 2888 u8 opcode[0x10]; 2889 u8 uid[0x10]; 2890 u8 reserved_at_20[0x10]; 2891 u8 op_mod[0x10]; 2892 u8 reserved_at_40[0x8]; 2893 u8 qpn[0x18]; 2894 u8 reserved_at_60[0x20]; 2895 u8 opt_param_mask[0x20]; 2896 u8 reserved_at_a0[0x20]; 2897 struct mlx5_ifc_qpc_bits qpc; 2898 u8 reserved_at_800[0x80]; 2899 }; 2900 2901 struct mlx5_ifc_init2rtr_qp_out_bits { 2902 u8 status[0x8]; 2903 u8 reserved_at_8[0x18]; 2904 u8 syndrome[0x20]; 2905 u8 reserved_at_40[0x40]; 2906 }; 2907 2908 struct mlx5_ifc_init2rtr_qp_in_bits { 2909 u8 opcode[0x10]; 2910 u8 uid[0x10]; 2911 u8 reserved_at_20[0x10]; 2912 u8 op_mod[0x10]; 2913 u8 reserved_at_40[0x8]; 2914 u8 qpn[0x18]; 2915 u8 reserved_at_60[0x20]; 2916 u8 opt_param_mask[0x20]; 2917 u8 reserved_at_a0[0x20]; 2918 struct mlx5_ifc_qpc_bits qpc; 2919 u8 reserved_at_800[0x80]; 2920 }; 2921 2922 struct mlx5_ifc_init2init_qp_out_bits { 2923 u8 status[0x8]; 2924 u8 reserved_at_8[0x18]; 2925 u8 syndrome[0x20]; 2926 u8 reserved_at_40[0x40]; 2927 }; 2928 2929 struct mlx5_ifc_init2init_qp_in_bits { 2930 u8 opcode[0x10]; 2931 u8 uid[0x10]; 2932 u8 reserved_at_20[0x10]; 2933 u8 op_mod[0x10]; 2934 u8 reserved_at_40[0x8]; 2935 u8 qpn[0x18]; 2936 u8 reserved_at_60[0x20]; 2937 u8 opt_param_mask[0x20]; 2938 u8 reserved_at_a0[0x20]; 2939 struct mlx5_ifc_qpc_bits qpc; 2940 u8 reserved_at_800[0x80]; 2941 }; 2942 2943 struct mlx5_ifc_dealloc_pd_out_bits { 2944 u8 status[0x8]; 2945 u8 reserved_0[0x18]; 2946 u8 syndrome[0x20]; 2947 u8 reserved_1[0x40]; 2948 }; 2949 2950 struct mlx5_ifc_dealloc_pd_in_bits { 2951 u8 opcode[0x10]; 2952 u8 reserved_0[0x10]; 2953 u8 reserved_1[0x10]; 2954 u8 op_mod[0x10]; 2955 u8 reserved_2[0x8]; 2956 u8 pd[0x18]; 2957 u8 reserved_3[0x20]; 2958 }; 2959 2960 struct mlx5_ifc_alloc_pd_out_bits { 2961 u8 status[0x8]; 2962 u8 reserved_0[0x18]; 2963 u8 syndrome[0x20]; 2964 u8 reserved_1[0x8]; 2965 u8 pd[0x18]; 2966 u8 reserved_2[0x20]; 2967 }; 2968 2969 struct mlx5_ifc_alloc_pd_in_bits { 2970 u8 opcode[0x10]; 2971 u8 reserved_0[0x10]; 2972 u8 reserved_1[0x10]; 2973 u8 op_mod[0x10]; 2974 u8 reserved_2[0x40]; 2975 }; 2976 2977 #ifdef PEDANTIC 2978 #pragma GCC diagnostic ignored "-Wpedantic" 2979 #endif 2980 struct mlx5_ifc_query_qp_out_bits { 2981 u8 status[0x8]; 2982 u8 reserved_at_8[0x18]; 2983 u8 syndrome[0x20]; 2984 u8 reserved_at_40[0x40]; 2985 u8 opt_param_mask[0x20]; 2986 u8 reserved_at_a0[0x20]; 2987 struct mlx5_ifc_qpc_bits qpc; 2988 u8 reserved_at_800[0x80]; 2989 u8 pas[0][0x40]; 2990 }; 2991 #ifdef PEDANTIC 2992 #pragma GCC diagnostic error "-Wpedantic" 2993 #endif 2994 2995 struct mlx5_ifc_query_qp_in_bits { 2996 u8 opcode[0x10]; 2997 u8 reserved_at_10[0x10]; 2998 u8 reserved_at_20[0x10]; 2999 u8 op_mod[0x10]; 3000 u8 reserved_at_40[0x8]; 3001 u8 qpn[0x18]; 3002 u8 reserved_at_60[0x20]; 3003 }; 3004 3005 enum { 3006 MLX5_DATA_RATE = 0x0, 3007 MLX5_WQE_RATE = 0x1, 3008 }; 3009 3010 struct mlx5_ifc_set_pp_rate_limit_context_bits { 3011 u8 rate_limit[0x20]; 3012 u8 burst_upper_bound[0x20]; 3013 u8 reserved_at_40[0xC]; 3014 u8 rate_mode[0x4]; 3015 u8 typical_packet_size[0x10]; 3016 u8 reserved_at_60[0x120]; 3017 }; 3018 3019 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u 3020 3021 #ifdef PEDANTIC 3022 #pragma GCC diagnostic ignored "-Wpedantic" 3023 #endif 3024 struct mlx5_ifc_access_register_out_bits { 3025 u8 status[0x8]; 3026 u8 reserved_at_8[0x18]; 3027 u8 syndrome[0x20]; 3028 u8 reserved_at_40[0x40]; 3029 u8 register_data[0][0x20]; 3030 }; 3031 3032 struct mlx5_ifc_access_register_in_bits { 3033 u8 opcode[0x10]; 3034 u8 reserved_at_10[0x10]; 3035 u8 reserved_at_20[0x10]; 3036 u8 op_mod[0x10]; 3037 u8 reserved_at_40[0x10]; 3038 u8 register_id[0x10]; 3039 u8 argument[0x20]; 3040 u8 register_data[0][0x20]; 3041 }; 3042 #ifdef PEDANTIC 3043 #pragma GCC diagnostic error "-Wpedantic" 3044 #endif 3045 3046 enum { 3047 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 3048 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 3049 }; 3050 3051 enum { 3052 MLX5_REGISTER_ID_MTUTC = 0x9055, 3053 }; 3054 3055 struct mlx5_ifc_register_mtutc_bits { 3056 u8 time_stamp_mode[0x2]; 3057 u8 time_stamp_state[0x2]; 3058 u8 reserved_at_4[0x18]; 3059 u8 operation[0x4]; 3060 u8 freq_adjustment[0x20]; 3061 u8 reserved_at_40[0x40]; 3062 u8 utc_sec[0x20]; 3063 u8 utc_nsec[0x20]; 3064 u8 time_adjustment[0x20]; 3065 }; 3066 3067 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 3068 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 3069 3070 struct mlx5_ifc_parse_graph_arc_bits { 3071 u8 start_inner_tunnel[0x1]; 3072 u8 reserved_at_1[0x7]; 3073 u8 arc_parse_graph_node[0x8]; 3074 u8 compare_condition_value[0x10]; 3075 u8 parse_graph_node_handle[0x20]; 3076 u8 reserved_at_40[0x40]; 3077 }; 3078 3079 struct mlx5_ifc_parse_graph_flow_match_sample_bits { 3080 u8 flow_match_sample_en[0x1]; 3081 u8 reserved_at_1[0x3]; 3082 u8 flow_match_sample_offset_mode[0x4]; 3083 u8 reserved_at_5[0x8]; 3084 u8 flow_match_sample_field_offset[0x10]; 3085 u8 reserved_at_32[0x4]; 3086 u8 flow_match_sample_field_offset_shift[0x4]; 3087 u8 flow_match_sample_field_base_offset[0x8]; 3088 u8 reserved_at_48[0xd]; 3089 u8 flow_match_sample_tunnel_mode[0x3]; 3090 u8 flow_match_sample_field_offset_mask[0x20]; 3091 u8 flow_match_sample_field_id[0x20]; 3092 }; 3093 3094 struct mlx5_ifc_parse_graph_flex_bits { 3095 u8 modify_field_select[0x40]; 3096 u8 reserved_at_64[0x20]; 3097 u8 header_length_base_value[0x10]; 3098 u8 reserved_at_112[0x4]; 3099 u8 header_length_field_shift[0x4]; 3100 u8 reserved_at_120[0x4]; 3101 u8 header_length_mode[0x4]; 3102 u8 header_length_field_offset[0x10]; 3103 u8 next_header_field_offset[0x10]; 3104 u8 reserved_at_160[0x1b]; 3105 u8 next_header_field_size[0x5]; 3106 u8 header_length_field_mask[0x20]; 3107 u8 reserved_at_224[0x20]; 3108 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8]; 3109 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8]; 3110 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8]; 3111 }; 3112 3113 struct mlx5_ifc_create_flex_parser_in_bits { 3114 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3115 struct mlx5_ifc_parse_graph_flex_bits flex; 3116 }; 3117 3118 struct mlx5_ifc_create_flex_parser_out_bits { 3119 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3120 struct mlx5_ifc_parse_graph_flex_bits flex; 3121 }; 3122 3123 struct mlx5_ifc_parse_graph_flex_out_bits { 3124 u8 status[0x8]; 3125 u8 reserved_at_8[0x18]; 3126 u8 syndrome[0x20]; 3127 u8 reserved_at_40[0x40]; 3128 struct mlx5_ifc_parse_graph_flex_bits capability; 3129 }; 3130 3131 struct regexp_params_field_select_bits { 3132 u8 reserved_at_0[0x1e]; 3133 u8 stop_engine[0x1]; 3134 u8 db_umem_id[0x1]; 3135 }; 3136 3137 struct mlx5_ifc_regexp_params_bits { 3138 u8 reserved_at_0[0x1f]; 3139 u8 stop_engine[0x1]; 3140 u8 db_umem_id[0x20]; 3141 u8 db_umem_offset[0x40]; 3142 u8 reserved_at_80[0x100]; 3143 }; 3144 3145 struct mlx5_ifc_set_regexp_params_in_bits { 3146 u8 opcode[0x10]; 3147 u8 uid[0x10]; 3148 u8 reserved_at_20[0x10]; 3149 u8 op_mod[0x10]; 3150 u8 reserved_at_40[0x18]; 3151 u8 engine_id[0x8]; 3152 struct regexp_params_field_select_bits field_select; 3153 struct mlx5_ifc_regexp_params_bits regexp_params; 3154 }; 3155 3156 struct mlx5_ifc_set_regexp_params_out_bits { 3157 u8 status[0x8]; 3158 u8 reserved_at_8[0x18]; 3159 u8 syndrome[0x20]; 3160 u8 reserved_at_18[0x40]; 3161 }; 3162 3163 struct mlx5_ifc_query_regexp_params_in_bits { 3164 u8 opcode[0x10]; 3165 u8 uid[0x10]; 3166 u8 reserved_at_20[0x10]; 3167 u8 op_mod[0x10]; 3168 u8 reserved_at_40[0x18]; 3169 u8 engine_id[0x8]; 3170 u8 reserved[0x20]; 3171 }; 3172 3173 struct mlx5_ifc_query_regexp_params_out_bits { 3174 u8 status[0x8]; 3175 u8 reserved_at_8[0x18]; 3176 u8 syndrome[0x20]; 3177 u8 reserved[0x40]; 3178 struct mlx5_ifc_regexp_params_bits regexp_params; 3179 }; 3180 3181 struct mlx5_ifc_set_regexp_register_in_bits { 3182 u8 opcode[0x10]; 3183 u8 uid[0x10]; 3184 u8 reserved_at_20[0x10]; 3185 u8 op_mod[0x10]; 3186 u8 reserved_at_40[0x18]; 3187 u8 engine_id[0x8]; 3188 u8 register_address[0x20]; 3189 u8 register_data[0x20]; 3190 u8 reserved[0x60]; 3191 }; 3192 3193 struct mlx5_ifc_set_regexp_register_out_bits { 3194 u8 status[0x8]; 3195 u8 reserved_at_8[0x18]; 3196 u8 syndrome[0x20]; 3197 u8 reserved[0x40]; 3198 }; 3199 3200 struct mlx5_ifc_query_regexp_register_in_bits { 3201 u8 opcode[0x10]; 3202 u8 uid[0x10]; 3203 u8 reserved_at_20[0x10]; 3204 u8 op_mod[0x10]; 3205 u8 reserved_at_40[0x18]; 3206 u8 engine_id[0x8]; 3207 u8 register_address[0x20]; 3208 }; 3209 3210 struct mlx5_ifc_query_regexp_register_out_bits { 3211 u8 status[0x8]; 3212 u8 reserved_at_8[0x18]; 3213 u8 syndrome[0x20]; 3214 u8 reserved[0x20]; 3215 u8 register_data[0x20]; 3216 }; 3217 3218 /* Queue counters. */ 3219 struct mlx5_ifc_alloc_q_counter_out_bits { 3220 u8 status[0x8]; 3221 u8 reserved_at_8[0x18]; 3222 u8 syndrome[0x20]; 3223 u8 reserved_at_40[0x18]; 3224 u8 counter_set_id[0x8]; 3225 u8 reserved_at_60[0x20]; 3226 }; 3227 3228 struct mlx5_ifc_alloc_q_counter_in_bits { 3229 u8 opcode[0x10]; 3230 u8 uid[0x10]; 3231 u8 reserved_at_20[0x10]; 3232 u8 op_mod[0x10]; 3233 u8 reserved_at_40[0x40]; 3234 }; 3235 3236 struct mlx5_ifc_query_q_counter_out_bits { 3237 u8 status[0x8]; 3238 u8 reserved_at_8[0x18]; 3239 u8 syndrome[0x20]; 3240 u8 reserved_at_40[0x40]; 3241 u8 rx_write_requests[0x20]; 3242 u8 reserved_at_a0[0x20]; 3243 u8 rx_read_requests[0x20]; 3244 u8 reserved_at_e0[0x20]; 3245 u8 rx_atomic_requests[0x20]; 3246 u8 reserved_at_120[0x20]; 3247 u8 rx_dct_connect[0x20]; 3248 u8 reserved_at_160[0x20]; 3249 u8 out_of_buffer[0x20]; 3250 u8 reserved_at_1a0[0x20]; 3251 u8 out_of_sequence[0x20]; 3252 u8 reserved_at_1e0[0x20]; 3253 u8 duplicate_request[0x20]; 3254 u8 reserved_at_220[0x20]; 3255 u8 rnr_nak_retry_err[0x20]; 3256 u8 reserved_at_260[0x20]; 3257 u8 packet_seq_err[0x20]; 3258 u8 reserved_at_2a0[0x20]; 3259 u8 implied_nak_seq_err[0x20]; 3260 u8 reserved_at_2e0[0x20]; 3261 u8 local_ack_timeout_err[0x20]; 3262 u8 reserved_at_320[0xa0]; 3263 u8 resp_local_length_error[0x20]; 3264 u8 req_local_length_error[0x20]; 3265 u8 resp_local_qp_error[0x20]; 3266 u8 local_operation_error[0x20]; 3267 u8 resp_local_protection[0x20]; 3268 u8 req_local_protection[0x20]; 3269 u8 resp_cqe_error[0x20]; 3270 u8 req_cqe_error[0x20]; 3271 u8 req_mw_binding[0x20]; 3272 u8 req_bad_response[0x20]; 3273 u8 req_remote_invalid_request[0x20]; 3274 u8 resp_remote_invalid_request[0x20]; 3275 u8 req_remote_access_errors[0x20]; 3276 u8 resp_remote_access_errors[0x20]; 3277 u8 req_remote_operation_errors[0x20]; 3278 u8 req_transport_retries_exceeded[0x20]; 3279 u8 cq_overflow[0x20]; 3280 u8 resp_cqe_flush_error[0x20]; 3281 u8 req_cqe_flush_error[0x20]; 3282 u8 reserved_at_620[0x1e0]; 3283 }; 3284 3285 struct mlx5_ifc_query_q_counter_in_bits { 3286 u8 opcode[0x10]; 3287 u8 uid[0x10]; 3288 u8 reserved_at_20[0x10]; 3289 u8 op_mod[0x10]; 3290 u8 reserved_at_40[0x80]; 3291 u8 clear[0x1]; 3292 u8 reserved_at_c1[0x1f]; 3293 u8 reserved_at_e0[0x18]; 3294 u8 counter_set_id[0x8]; 3295 }; 3296 3297 /* CQE format mask. */ 3298 #define MLX5E_CQE_FORMAT_MASK 0xc 3299 3300 /* MPW opcode. */ 3301 #define MLX5_OPC_MOD_MPW 0x01 3302 3303 /* Compressed Rx CQE structure. */ 3304 struct mlx5_mini_cqe8 { 3305 union { 3306 uint32_t rx_hash_result; 3307 struct { 3308 union { 3309 uint16_t checksum; 3310 uint16_t flow_tag_high; 3311 struct { 3312 uint8_t reserved; 3313 uint8_t hdr_type; 3314 }; 3315 }; 3316 uint16_t stride_idx; 3317 }; 3318 struct { 3319 uint16_t wqe_counter; 3320 uint8_t s_wqe_opcode; 3321 uint8_t reserved; 3322 } s_wqe_info; 3323 }; 3324 union { 3325 uint32_t byte_cnt_flow; 3326 uint32_t byte_cnt; 3327 }; 3328 }; 3329 3330 /* Mini CQE responder format. */ 3331 enum { 3332 MLX5_CQE_RESP_FORMAT_HASH = 0x0, 3333 MLX5_CQE_RESP_FORMAT_CSUM = 0x1, 3334 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2, 3335 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3, 3336 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4, 3337 }; 3338 3339 /* srTCM PRM flow meter parameters. */ 3340 enum { 3341 MLX5_FLOW_COLOR_RED = 0, 3342 MLX5_FLOW_COLOR_YELLOW, 3343 MLX5_FLOW_COLOR_GREEN, 3344 MLX5_FLOW_COLOR_UNDEFINED, 3345 }; 3346 3347 /* Maximum value of srTCM metering parameters. */ 3348 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F)) 3349 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF) 3350 #define MLX5_SRTCM_EBS_MAX 0 3351 3352 /* The bits meter color use. */ 3353 #define MLX5_MTR_COLOR_BITS 8 3354 3355 /* Length mode of dynamic flex parser graph node. */ 3356 enum mlx5_parse_graph_node_len_mode { 3357 MLX5_GRAPH_NODE_LEN_FIXED = 0x0, 3358 MLX5_GRAPH_NODE_LEN_FIELD = 0x1, 3359 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2, 3360 }; 3361 3362 /* Offset mode of the samples of flex parser. */ 3363 enum mlx5_parse_graph_flow_match_sample_offset_mode { 3364 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0, 3365 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1, 3366 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, 3367 }; 3368 3369 /* Node index for an input / output arc of the flex parser graph. */ 3370 enum mlx5_parse_graph_arc_node_index { 3371 MLX5_GRAPH_ARC_NODE_NULL = 0x0, 3372 MLX5_GRAPH_ARC_NODE_HEAD = 0x1, 3373 MLX5_GRAPH_ARC_NODE_MAC = 0x2, 3374 MLX5_GRAPH_ARC_NODE_IP = 0x3, 3375 MLX5_GRAPH_ARC_NODE_GRE = 0x4, 3376 MLX5_GRAPH_ARC_NODE_UDP = 0x5, 3377 MLX5_GRAPH_ARC_NODE_MPLS = 0x6, 3378 MLX5_GRAPH_ARC_NODE_TCP = 0x7, 3379 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, 3380 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, 3381 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, 3382 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, 3383 }; 3384 3385 /** 3386 * Convert a user mark to flow mark. 3387 * 3388 * @param val 3389 * Mark value to convert. 3390 * 3391 * @return 3392 * Converted mark value. 3393 */ 3394 static inline uint32_t 3395 mlx5_flow_mark_set(uint32_t val) 3396 { 3397 uint32_t ret; 3398 3399 /* 3400 * Add one to the user value to differentiate un-marked flows from 3401 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it 3402 * remains untouched. 3403 */ 3404 if (val != MLX5_FLOW_MARK_DEFAULT) 3405 ++val; 3406 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 3407 /* 3408 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit 3409 * word, byte-swapped by the kernel on little-endian systems. In this 3410 * case, left-shifting the resulting big-endian value ensures the 3411 * least significant 24 bits are retained when converting it back. 3412 */ 3413 ret = rte_cpu_to_be_32(val) >> 8; 3414 #else 3415 ret = val; 3416 #endif 3417 return ret; 3418 } 3419 3420 /** 3421 * Convert a mark to user mark. 3422 * 3423 * @param val 3424 * Mark value to convert. 3425 * 3426 * @return 3427 * Converted mark value. 3428 */ 3429 static inline uint32_t 3430 mlx5_flow_mark_get(uint32_t val) 3431 { 3432 /* 3433 * Subtract one from the retrieved value. It was added by 3434 * mlx5_flow_mark_set() to distinguish unmarked flows. 3435 */ 3436 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 3437 return (val >> 8) - 1; 3438 #else 3439 return val - 1; 3440 #endif 3441 } 3442 3443 #endif /* RTE_PMD_MLX5_PRM_H_ */ 3444