1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_PRM_H_ 7 #define RTE_PMD_MLX5_PRM_H_ 8 9 #include <unistd.h> 10 11 #include <rte_vect.h> 12 #include <rte_byteorder.h> 13 14 #include <mlx5_glue.h> 15 #include "mlx5_autoconf.h" 16 17 /* RSS hash key size. */ 18 #define MLX5_RSS_HASH_KEY_LEN 40 19 20 /* Get CQE owner bit. */ 21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK) 22 23 /* Get CQE format. */ 24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2) 25 26 /* Get CQE opcode. */ 27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4) 28 29 /* Get CQE solicited event. */ 30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1) 31 32 /* Invalidate a CQE. */ 33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4) 34 35 /* Hardware index widths. */ 36 #define MLX5_CQ_INDEX_WIDTH 24 37 #define MLX5_WQ_INDEX_WIDTH 16 38 39 /* WQE Segment sizes in bytes. */ 40 #define MLX5_WSEG_SIZE 16u 41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg) 42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg) 43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg) 44 45 /* WQE/WQEBB size in bytes. */ 46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe) 47 48 /* 49 * Max size of a WQE session. 50 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments, 51 * the WQE size field in Control Segment is 6 bits wide. 52 */ 53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE) 54 55 /* 56 * Default minimum number of Tx queues for inlining packets. 57 * If there are less queues as specified we assume we have 58 * no enough CPU resources (cycles) to perform inlining, 59 * the PCIe throughput is not supposed as bottleneck and 60 * inlining is disabled. 61 */ 62 #define MLX5_INLINE_MAX_TXQS 8u 63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u 64 65 /* 66 * Default packet length threshold to be inlined with 67 * enhanced MPW. If packet length exceeds the threshold 68 * the data are not inlined. Should be aligned in WQEBB 69 * boundary with accounting the title Control and Ethernet 70 * segments. 71 */ 72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \ 73 MLX5_DSEG_MIN_INLINE_SIZE) 74 /* 75 * Maximal inline data length sent with enhanced MPW. 76 * Is based on maximal WQE size. 77 */ 78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 79 MLX5_WQE_CSEG_SIZE - \ 80 MLX5_WQE_ESEG_SIZE - \ 81 MLX5_WQE_DSEG_SIZE + \ 82 MLX5_DSEG_MIN_INLINE_SIZE) 83 /* 84 * Minimal amount of packets to be sent with EMPW. 85 * This limits the minimal required size of sent EMPW. 86 * If there are no enough resources to built minimal 87 * EMPW the sending loop exits. 88 */ 89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u) 90 /* 91 * Maximal amount of packets to be sent with EMPW. 92 * This value is not recommended to exceed MLX5_TX_COMP_THRESH, 93 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs 94 * without CQE generation request, being multiplied by 95 * MLX5_TX_COMP_MAX_CQE it may cause significant latency 96 * in tx burst routine at the moment of freeing multiple mbufs. 97 */ 98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH 99 #define MLX5_MPW_MAX_PACKETS 6 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6 101 102 /* 103 * Default packet length threshold to be inlined with 104 * ordinary SEND. Inlining saves the MR key search 105 * and extra PCIe data fetch transaction, but eats the 106 * CPU cycles. 107 */ 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \ 109 MLX5_ESEG_MIN_INLINE_SIZE - \ 110 MLX5_WQE_CSEG_SIZE - \ 111 MLX5_WQE_ESEG_SIZE - \ 112 MLX5_WQE_DSEG_SIZE) 113 /* 114 * Maximal inline data length sent with ordinary SEND. 115 * Is based on maximal WQE size. 116 */ 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 118 MLX5_WQE_CSEG_SIZE - \ 119 MLX5_WQE_ESEG_SIZE - \ 120 MLX5_WQE_DSEG_SIZE + \ 121 MLX5_ESEG_MIN_INLINE_SIZE) 122 123 /* Missed in mlx5dv.h, should define here. */ 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u 126 #endif 127 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN 129 #define MLX5_OPCODE_SEND_EN 0x17u 130 #endif 131 132 #ifndef HAVE_MLX5_OPCODE_WAIT 133 #define MLX5_OPCODE_WAIT 0x0fu 134 #endif 135 136 #define MLX5_OPC_MOD_WAIT_CQ_PI 0u 137 #define MLX5_OPC_MOD_WAIT_DATA 1u 138 #define MLX5_OPC_MOD_WAIT_TIME 2u 139 140 141 #define MLX5_WAIT_COND_INVERT 0x10u 142 #define MLX5_WAIT_COND_ALWAYS_TRUE 0u 143 #define MLX5_WAIT_COND_EQUAL 1u 144 #define MLX5_WAIT_COND_BIGGER 2u 145 #define MLX5_WAIT_COND_SMALLER 3u 146 #define MLX5_WAIT_COND_CYCLIC_BIGGER 4u 147 #define MLX5_WAIT_COND_CYCLIC_SMALLER 5u 148 149 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO 150 #define MLX5_OPCODE_ACCESS_ASO 0x2du 151 #endif 152 153 /* CQE value to inform that VLAN is stripped. */ 154 #define MLX5_CQE_VLAN_STRIPPED (1u << 0) 155 156 /* IPv4 options. */ 157 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1) 158 159 /* IPv6 packet. */ 160 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2) 161 162 /* IPv4 packet. */ 163 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3) 164 165 /* TCP packet. */ 166 #define MLX5_CQE_RX_TCP_PACKET (1u << 4) 167 168 /* UDP packet. */ 169 #define MLX5_CQE_RX_UDP_PACKET (1u << 5) 170 171 /* IP is fragmented. */ 172 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7) 173 174 /* L2 header is valid. */ 175 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8) 176 177 /* L3 header is valid. */ 178 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9) 179 180 /* L4 header is valid. */ 181 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10) 182 183 /* Outer packet, 0 IPv4, 1 IPv6. */ 184 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1) 185 186 /* Tunnel packet bit in the CQE. */ 187 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0) 188 189 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */ 190 #define MLX5_CQE_LRO_PUSH_MASK 0x40 191 192 /* Mask for L4 type in the CQE hdr_type_etc field. */ 193 #define MLX5_CQE_L4_TYPE_MASK 0x70 194 195 /* The bit index of L4 type in CQE hdr_type_etc field. */ 196 #define MLX5_CQE_L4_TYPE_SHIFT 0x4 197 198 /* L4 type to indicate TCP packet without acknowledgment. */ 199 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3 200 201 /* L4 type to indicate TCP packet with acknowledgment. */ 202 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4 203 204 /* Inner L3 checksum offload (Tunneled packets only). */ 205 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4) 206 207 /* Inner L4 checksum offload (Tunneled packets only). */ 208 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5) 209 210 /* Outer L4 type is TCP. */ 211 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5) 212 213 /* Outer L4 type is UDP. */ 214 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5) 215 216 /* Outer L3 type is IPV4. */ 217 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4) 218 219 /* Outer L3 type is IPV6. */ 220 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4) 221 222 /* Inner L4 type is TCP. */ 223 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1) 224 225 /* Inner L4 type is UDP. */ 226 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1) 227 228 /* Inner L3 type is IPV4. */ 229 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0) 230 231 /* Inner L3 type is IPV6. */ 232 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0) 233 234 /* VLAN insertion flag. */ 235 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31) 236 237 /* Data inline segment flag. */ 238 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31) 239 240 /* Is flow mark valid. */ 241 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 242 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00) 243 #else 244 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff) 245 #endif 246 247 /* INVALID is used by packets matching no flow rules. */ 248 #define MLX5_FLOW_MARK_INVALID 0 249 250 /* Maximum allowed value to mark a packet. */ 251 #define MLX5_FLOW_MARK_MAX 0xfffff0 252 253 /* Default mark value used when none is provided. */ 254 #define MLX5_FLOW_MARK_DEFAULT 0xffffff 255 256 /* Default mark mask for metadata legacy mode. */ 257 #define MLX5_FLOW_MARK_MASK 0xffffff 258 259 /* Byte length mask when mark is enable in miniCQE */ 260 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00 261 262 /* Maximum number of DS in WQE. Limited by 6-bit field. */ 263 #define MLX5_DSEG_MAX 63 264 265 /* The 32 bit syndrome offset in struct mlx5_err_cqe. */ 266 #define MLX5_ERROR_CQE_SYNDROME_OFFSET 52 267 268 /* The completion mode offset in the WQE control segment line 2. */ 269 #define MLX5_COMP_MODE_OFFSET 2 270 271 /* Amount of data bytes in minimal inline data segment. */ 272 #define MLX5_DSEG_MIN_INLINE_SIZE 12u 273 274 /* Amount of data bytes in minimal inline eth segment. */ 275 #define MLX5_ESEG_MIN_INLINE_SIZE 18u 276 277 /* Amount of data bytes after eth data segment. */ 278 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u 279 280 /* The maximum log value of segments per RQ WQE. */ 281 #define MLX5_MAX_LOG_RQ_SEGS 5u 282 283 /* Log 2 of the default size of a WQE for Multi-Packet RQ. */ 284 #define MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE 14U 285 286 /* The alignment needed for WQ buffer. */ 287 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size() 288 289 /* The alignment needed for CQ buffer. */ 290 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size() 291 292 #define MAX_ACTIONS_DATA_IN_HEADER_MODIFY 512 293 294 /* Alias FT id passed to the ALLOW_OTHER_VHCA_ACCESS & CREATE_GENERAL_OBJECT 295 * commands should have the following format: 296 * {table_type: 8bits, table_id: 24bits}. 297 */ 298 #define FT_ID_FT_TYPE_OFFSET 24 299 300 /* Completion mode. */ 301 enum mlx5_completion_mode { 302 MLX5_COMP_ONLY_ERR = 0x0, 303 MLX5_COMP_ONLY_FIRST_ERR = 0x1, 304 MLX5_COMP_ALWAYS = 0x2, 305 MLX5_COMP_CQE_AND_EQE = 0x3, 306 }; 307 308 /* MPW mode. */ 309 enum mlx5_mpw_mode { 310 MLX5_MPW_DISABLED, 311 MLX5_MPW, 312 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */ 313 }; 314 315 /* WQE Control segment. */ 316 struct mlx5_wqe_cseg { 317 uint32_t opcode; 318 uint32_t sq_ds; 319 uint32_t flags; 320 uint32_t misc; 321 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE); 322 323 /* 324 * WQE CSEG opcode field size is 32 bits, divided: 325 * Bits 31:24 OPC_MOD 326 * Bits 23:8 wqe_index 327 * Bits 7:0 OPCODE 328 */ 329 #define WQE_CSEG_OPC_MOD_OFFSET 24 330 #define WQE_CSEG_WQE_INDEX_OFFSET 8 331 332 /* Header of data segment. Minimal size Data Segment */ 333 struct mlx5_wqe_dseg { 334 uint32_t bcount; 335 union { 336 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE]; 337 struct { 338 uint32_t lkey; 339 uint64_t pbuf; 340 } __rte_packed; 341 }; 342 } __rte_packed; 343 344 /* Subset of struct WQE Ethernet Segment. */ 345 struct mlx5_wqe_eseg { 346 union { 347 struct { 348 uint32_t swp_offs; 349 uint8_t cs_flags; 350 uint8_t swp_flags; 351 uint16_t mss; 352 uint32_t metadata; 353 uint16_t inline_hdr_sz; 354 union { 355 uint16_t inline_data; 356 uint16_t vlan_tag; 357 }; 358 } __rte_packed; 359 struct { 360 uint32_t offsets; 361 uint32_t flags; 362 uint32_t flow_metadata; 363 uint32_t inline_hdr; 364 } __rte_packed; 365 }; 366 } __rte_packed; 367 368 struct mlx5_wqe_qseg { 369 uint32_t reserved0; 370 uint32_t reserved1; 371 uint32_t max_index; 372 uint32_t qpn_cqn; 373 } __rte_packed; 374 375 struct mlx5_wqe_wseg { 376 uint32_t operation; 377 uint32_t lkey; 378 uint32_t va_high; 379 uint32_t va_low; 380 uint64_t value; 381 uint64_t mask; 382 } __rte_packed; 383 384 /* The title WQEBB, header of WQE. */ 385 struct mlx5_wqe { 386 union { 387 struct mlx5_wqe_cseg cseg; 388 uint32_t ctrl[4]; 389 }; 390 struct mlx5_wqe_eseg eseg; 391 union { 392 struct mlx5_wqe_dseg dseg[2]; 393 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE]; 394 }; 395 } __rte_packed; 396 397 /* WQE for Multi-Packet RQ. */ 398 struct mlx5_wqe_mprq { 399 struct mlx5_wqe_srq_next_seg next_seg; 400 struct mlx5_wqe_data_seg dseg; 401 }; 402 403 #define MLX5_MPRQ_LEN_MASK 0x000ffff 404 #define MLX5_MPRQ_LEN_SHIFT 0 405 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000 406 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16 407 #define MLX5_MPRQ_FILLER_MASK 0x80000000 408 #define MLX5_MPRQ_FILLER_SHIFT 31 409 410 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2 411 412 /* CQ element structure - should be equal to the cache line size */ 413 struct mlx5_cqe { 414 #if (RTE_CACHE_LINE_SIZE == 128) 415 uint8_t padding[64]; 416 #endif 417 uint8_t pkt_info; 418 uint8_t rsvd0; 419 uint16_t wqe_id; 420 uint8_t lro_tcppsh_abort_dupack; 421 uint8_t lro_min_ttl; 422 uint16_t lro_tcp_win; 423 uint32_t lro_ack_seq_num; 424 uint32_t rx_hash_res; 425 uint8_t rx_hash_type; 426 uint8_t rsvd1[3]; 427 uint16_t csum; 428 uint8_t rsvd2[6]; 429 uint16_t hdr_type_etc; 430 uint16_t vlan_info; 431 uint8_t lro_num_seg; 432 union { 433 uint8_t user_index_bytes[3]; 434 struct { 435 uint8_t user_index_hi; 436 uint16_t user_index_low; 437 } __rte_packed; 438 }; 439 uint32_t flow_table_metadata; 440 uint8_t rsvd4[4]; 441 uint32_t byte_cnt; 442 uint64_t timestamp; 443 uint32_t sop_drop_qpn; 444 uint16_t wqe_counter; 445 uint8_t rsvd5; 446 uint8_t op_own; 447 }; 448 449 struct mlx5_cqe_ts { 450 uint64_t timestamp; 451 uint32_t sop_drop_qpn; 452 uint16_t wqe_counter; 453 uint8_t rsvd5; 454 uint8_t op_own; 455 }; 456 457 struct mlx5_wqe_rseg { 458 uint64_t raddr; 459 uint32_t rkey; 460 uint32_t reserved; 461 } __rte_packed; 462 463 #define MLX5_UMRC_IF_OFFSET 31u 464 #define MLX5_UMRC_KO_OFFSET 16u 465 #define MLX5_UMRC_TO_BS_OFFSET 0u 466 467 struct mlx5_wqe_umr_cseg { 468 uint32_t if_cf_toe_cq_res; 469 uint32_t ko_to_bs; 470 uint64_t mkey_mask; 471 uint32_t rsvd1[8]; 472 } __rte_packed; 473 474 struct mlx5_wqe_mkey_cseg { 475 uint32_t fr_res_af_sf; 476 uint32_t qpn_mkey; 477 uint32_t reserved2; 478 uint32_t flags_pd; 479 uint64_t start_addr; 480 uint64_t len; 481 uint32_t bsf_octword_size; 482 uint32_t reserved3[4]; 483 uint32_t translations_octword_size; 484 uint32_t res4_lps; 485 uint32_t reserved; 486 } __rte_packed; 487 488 enum { 489 MLX5_BSF_SIZE_16B = 0x0, 490 MLX5_BSF_SIZE_32B = 0x1, 491 MLX5_BSF_SIZE_64B = 0x2, 492 MLX5_BSF_SIZE_128B = 0x3, 493 }; 494 495 enum { 496 MLX5_BSF_P_TYPE_SIGNATURE = 0x0, 497 MLX5_BSF_P_TYPE_CRYPTO = 0x1, 498 }; 499 500 enum { 501 MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, 502 MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, 503 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, 504 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, 505 }; 506 507 enum { 508 MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, 509 }; 510 511 enum { 512 MLX5_BLOCK_SIZE_512B = 0x1, 513 MLX5_BLOCK_SIZE_520B = 0x2, 514 MLX5_BLOCK_SIZE_4096B = 0x3, 515 MLX5_BLOCK_SIZE_4160B = 0x4, 516 MLX5_BLOCK_SIZE_1MB = 0x5, 517 MLX5_BLOCK_SIZE_4048B = 0x6, 518 }; 519 520 #define MLX5_BSF_SIZE_OFFSET 30 521 #define MLX5_BSF_P_TYPE_OFFSET 24 522 #define MLX5_ENCRYPTION_ORDER_OFFSET 16 523 #define MLX5_BLOCK_SIZE_OFFSET 24 524 525 struct mlx5_wqe_umr_bsf_seg { 526 /* 527 * bs_bpt_eo_es contains: 528 * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET 529 * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET 530 * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET 531 * es encryption_standard 4 bits at offset 0 532 */ 533 uint32_t bs_bpt_eo_es; 534 uint32_t raw_data_size; 535 /* 536 * bsp_res contains: 537 * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET 538 * res reserved 24 bits 539 */ 540 uint32_t bsp_res; 541 uint32_t reserved0; 542 uint8_t xts_initial_tweak[16]; 543 /* 544 * res_dp contains: 545 * res reserved 8 bits 546 * dp dek_pointer 24 bits at offset 0 547 */ 548 uint32_t res_dp; 549 uint32_t reserved1; 550 uint64_t keytag; 551 uint32_t reserved2[4]; 552 } __rte_packed; 553 554 #ifdef PEDANTIC 555 #pragma GCC diagnostic ignored "-Wpedantic" 556 #endif 557 558 struct mlx5_umr_wqe { 559 struct mlx5_wqe_cseg ctr; 560 struct mlx5_wqe_umr_cseg ucseg; 561 struct mlx5_wqe_mkey_cseg mkc; 562 union { 563 struct mlx5_wqe_dseg kseg[0]; 564 struct mlx5_wqe_umr_bsf_seg bsf[0]; 565 }; 566 } __rte_packed; 567 568 struct mlx5_rdma_write_wqe { 569 struct mlx5_wqe_cseg ctr; 570 struct mlx5_wqe_rseg rseg; 571 struct mlx5_wqe_dseg dseg[]; 572 } __rte_packed; 573 574 #ifdef PEDANTIC 575 #pragma GCC diagnostic error "-Wpedantic" 576 #endif 577 578 /* GGA */ 579 /* MMO metadata segment */ 580 581 #define MLX5_OPCODE_MMO 0x2fu 582 #define MLX5_OPC_MOD_MMO_REGEX 0x4u 583 #define MLX5_OPC_MOD_MMO_COMP 0x2u 584 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u 585 #define MLX5_OPC_MOD_MMO_DMA 0x1u 586 587 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u 588 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u 589 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u 590 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u 591 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) 592 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u 593 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u 594 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u 595 #define MLX5_GGA_COMP_OUT_OF_SPACE_SYNDROME_BE 0x29D0084 596 #define MLX5_GGA_COMP_MISSING_BFINAL_SYNDROME_BE 0x29D0011 597 598 struct mlx5_wqe_metadata_seg { 599 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */ 600 uint32_t lkey; 601 uint64_t addr; 602 }; 603 604 struct mlx5_gga_wqe { 605 uint32_t opcode; 606 uint32_t sq_ds; 607 uint32_t flags; 608 uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */ 609 uint32_t gga_ctrl2; 610 uint32_t opaque_lkey; 611 uint64_t opaque_vaddr; 612 struct mlx5_wqe_dseg gather; 613 struct mlx5_wqe_dseg scatter; 614 } __rte_packed; 615 616 struct mlx5_gga_compress_opaque { 617 uint32_t syndrom; 618 uint32_t reserved0; 619 uint32_t scattered_length; 620 uint32_t gathered_length; 621 uint64_t scatter_crc; 622 uint64_t gather_crc; 623 uint32_t crc32; 624 uint32_t adler32; 625 uint8_t reserved1[216]; 626 } __rte_packed; 627 628 struct mlx5_ifc_regexp_mmo_control_bits { 629 uint8_t reserved_at_31[0x2]; 630 uint8_t le[0x1]; 631 uint8_t reserved_at_28[0x1]; 632 uint8_t subset_id_0[0xc]; 633 uint8_t reserved_at_16[0x4]; 634 uint8_t subset_id_1[0xc]; 635 uint8_t ctrl[0x4]; 636 uint8_t subset_id_2[0xc]; 637 uint8_t reserved_at_16_1[0x4]; 638 uint8_t subset_id_3[0xc]; 639 }; 640 641 struct mlx5_ifc_regexp_metadata_bits { 642 uint8_t rof_version[0x10]; 643 uint8_t latency_count[0x10]; 644 uint8_t instruction_count[0x10]; 645 uint8_t primary_thread_count[0x10]; 646 uint8_t match_count[0x8]; 647 uint8_t detected_match_count[0x8]; 648 uint8_t status[0x10]; 649 uint8_t job_id[0x20]; 650 uint8_t reserved[0x80]; 651 }; 652 653 struct mlx5_ifc_regexp_match_tuple_bits { 654 uint8_t length[0x10]; 655 uint8_t start_ptr[0x10]; 656 uint8_t rule_id[0x20]; 657 }; 658 659 /* Adding direct verbs to data-path. */ 660 661 /* CQ sequence number mask. */ 662 #define MLX5_CQ_SQN_MASK 0x3 663 664 /* CQ sequence number index. */ 665 #define MLX5_CQ_SQN_OFFSET 28 666 667 /* CQ doorbell index mask. */ 668 #define MLX5_CI_MASK 0xffffff 669 670 /* CQ doorbell offset. */ 671 #define MLX5_CQ_ARM_DB 1 672 673 /* CQ doorbell offset*/ 674 #define MLX5_CQ_DOORBELL 0x20 675 676 /* CQE format value. */ 677 #define MLX5_COMPRESSED 0x3 678 679 /* CQ doorbell cmd types. */ 680 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24) 681 #define MLX5_CQ_DBR_CMD_ALL (0 << 24) 682 683 /* Action type of header modification. */ 684 enum { 685 MLX5_MODIFICATION_TYPE_SET = 0x1, 686 MLX5_MODIFICATION_TYPE_ADD = 0x2, 687 MLX5_MODIFICATION_TYPE_COPY = 0x3, 688 MLX5_MODIFICATION_TYPE_INSERT = 0x4, 689 MLX5_MODIFICATION_TYPE_REMOVE = 0x5, 690 MLX5_MODIFICATION_TYPE_NOP = 0x6, 691 MLX5_MODIFICATION_TYPE_REMOVE_WORDS = 0x7, 692 }; 693 694 /* The field of packet to be modified. */ 695 enum mlx5_modification_field { 696 MLX5_MODI_OUT_NONE = -1, 697 MLX5_MODI_OUT_SMAC_47_16 = 1, 698 MLX5_MODI_OUT_SMAC_15_0, 699 MLX5_MODI_OUT_ETHERTYPE, 700 MLX5_MODI_OUT_DMAC_47_16, 701 MLX5_MODI_OUT_DMAC_15_0, 702 MLX5_MODI_OUT_IP_DSCP, 703 MLX5_MODI_OUT_TCP_FLAGS, 704 MLX5_MODI_OUT_TCP_SPORT, 705 MLX5_MODI_OUT_TCP_DPORT, 706 MLX5_MODI_OUT_IPV4_TTL, 707 MLX5_MODI_OUT_UDP_SPORT, 708 MLX5_MODI_OUT_UDP_DPORT, 709 MLX5_MODI_OUT_SIPV6_127_96, 710 MLX5_MODI_OUT_SIPV6_95_64, 711 MLX5_MODI_OUT_SIPV6_63_32, 712 MLX5_MODI_OUT_SIPV6_31_0, 713 MLX5_MODI_OUT_DIPV6_127_96, 714 MLX5_MODI_OUT_DIPV6_95_64, 715 MLX5_MODI_OUT_DIPV6_63_32, 716 MLX5_MODI_OUT_DIPV6_31_0, 717 MLX5_MODI_OUT_SIPV4, 718 MLX5_MODI_OUT_DIPV4, 719 MLX5_MODI_OUT_FIRST_VID, 720 MLX5_MODI_IN_SMAC_47_16 = 0x31, 721 MLX5_MODI_IN_SMAC_15_0, 722 MLX5_MODI_IN_ETHERTYPE, 723 MLX5_MODI_IN_DMAC_47_16, 724 MLX5_MODI_IN_DMAC_15_0, 725 MLX5_MODI_IN_IP_DSCP, 726 MLX5_MODI_IN_TCP_FLAGS, 727 MLX5_MODI_IN_TCP_SPORT, 728 MLX5_MODI_IN_TCP_DPORT, 729 MLX5_MODI_IN_IPV4_TTL, 730 MLX5_MODI_IN_UDP_SPORT, 731 MLX5_MODI_IN_UDP_DPORT, 732 MLX5_MODI_IN_SIPV6_127_96, 733 MLX5_MODI_IN_SIPV6_95_64, 734 MLX5_MODI_IN_SIPV6_63_32, 735 MLX5_MODI_IN_SIPV6_31_0, 736 MLX5_MODI_IN_DIPV6_127_96, 737 MLX5_MODI_IN_DIPV6_95_64, 738 MLX5_MODI_IN_DIPV6_63_32, 739 MLX5_MODI_IN_DIPV6_31_0, 740 MLX5_MODI_IN_SIPV4, 741 MLX5_MODI_IN_DIPV4, 742 MLX5_MODI_OUT_IPV6_HOPLIMIT, 743 MLX5_MODI_IN_IPV6_HOPLIMIT, 744 MLX5_MODI_META_DATA_REG_A, 745 MLX5_MODI_META_DATA_REG_B = 0x50, 746 MLX5_MODI_META_REG_C_0, 747 MLX5_MODI_META_REG_C_1, 748 MLX5_MODI_META_REG_C_2, 749 MLX5_MODI_META_REG_C_3, 750 MLX5_MODI_META_REG_C_4, 751 MLX5_MODI_META_REG_C_5, 752 MLX5_MODI_META_REG_C_6, 753 MLX5_MODI_META_REG_C_7, 754 MLX5_MODI_OUT_TCP_SEQ_NUM, 755 MLX5_MODI_IN_TCP_SEQ_NUM, 756 MLX5_MODI_OUT_TCP_ACK_NUM, 757 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C, 758 MLX5_MODI_GTP_TEID = 0x6E, 759 MLX5_MODI_OUT_IP_ECN = 0x73, 760 MLX5_MODI_TUNNEL_HDR_DW_1 = 0x75, 761 MLX5_MODI_GTPU_FIRST_EXT_DW_0 = 0x76, 762 MLX5_MODI_HASH_RESULT = 0x81, 763 MLX5_MODI_OUT_IPV6_NEXT_HDR = 0x4A, 764 }; 765 766 /* Total number of metadata reg_c's. */ 767 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1) 768 769 enum modify_reg { 770 REG_NON = 0, 771 REG_A, 772 REG_B, 773 REG_C_0, 774 REG_C_1, 775 REG_C_2, 776 REG_C_3, 777 REG_C_4, 778 REG_C_5, 779 REG_C_6, 780 REG_C_7, 781 }; 782 783 /* Modification sub command. */ 784 struct mlx5_modification_cmd { 785 union { 786 uint32_t data0; 787 struct { 788 unsigned int length:5; 789 unsigned int rsvd0:3; 790 unsigned int offset:5; 791 unsigned int rsvd1:3; 792 unsigned int field:12; 793 unsigned int action_type:4; 794 }; 795 }; 796 union { 797 uint32_t data1; 798 uint8_t data[4]; 799 struct { 800 unsigned int rsvd2:8; 801 unsigned int dst_offset:5; 802 unsigned int rsvd3:3; 803 unsigned int dst_field:12; 804 unsigned int rsvd4:4; 805 }; 806 }; 807 }; 808 809 typedef uint64_t u64; 810 typedef uint32_t u32; 811 typedef uint16_t u16; 812 typedef uint8_t u8; 813 814 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 815 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 816 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \ 817 (&(__mlx5_nullp(typ)->fld))) 818 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \ 819 (__mlx5_bit_off(typ, fld) & 0x1f)) 820 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 821 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 822 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \ 823 __mlx5_dw_bit_off(typ, fld)) 824 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 825 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 826 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \ 827 (__mlx5_bit_off(typ, fld) & 0xf)) 828 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 829 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \ 830 __mlx5_16_bit_off(typ, fld)) 831 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 832 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 833 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 834 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 835 836 /* insert a value to a struct */ 837 #define MLX5_SET(typ, p, fld, v) \ 838 do { \ 839 u32 _v = v; \ 840 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \ 841 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \ 842 __mlx5_dw_off(typ, fld))) & \ 843 (~__mlx5_dw_mask(typ, fld))) | \ 844 (((_v) & __mlx5_mask(typ, fld)) << \ 845 __mlx5_dw_bit_off(typ, fld))); \ 846 } while (0) 847 848 #define MLX5_SET64(typ, p, fld, v) \ 849 do { \ 850 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \ 851 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \ 852 rte_cpu_to_be_64(v); \ 853 } while (0) 854 855 #define MLX5_SET16(typ, p, fld, v) \ 856 do { \ 857 u16 _v = v; \ 858 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \ 859 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 860 __mlx5_16_off(typ, fld))) & \ 861 (~__mlx5_16_mask(typ, fld))) | \ 862 (((_v) & __mlx5_mask16(typ, fld)) << \ 863 __mlx5_16_bit_off(typ, fld))); \ 864 } while (0) 865 866 #define MLX5_GET_VOLATILE(typ, p, fld) \ 867 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\ 868 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 869 __mlx5_mask(typ, fld)) 870 #define MLX5_GET(typ, p, fld) \ 871 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\ 872 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 873 __mlx5_mask(typ, fld)) 874 #define MLX5_GET16(typ, p, fld) \ 875 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 876 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 877 __mlx5_mask16(typ, fld)) 878 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \ 879 __mlx5_64_off(typ, fld))) 880 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 881 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 882 883 struct mlx5_ifc_fte_match_set_misc_bits { 884 u8 gre_c_present[0x1]; 885 u8 reserved_at_1[0x1]; 886 u8 gre_k_present[0x1]; 887 u8 gre_s_present[0x1]; 888 u8 source_vhci_port[0x4]; 889 u8 source_sqn[0x18]; 890 u8 reserved_at_20[0x10]; 891 u8 source_port[0x10]; 892 u8 outer_second_prio[0x3]; 893 u8 outer_second_cfi[0x1]; 894 u8 outer_second_vid[0xc]; 895 u8 inner_second_prio[0x3]; 896 u8 inner_second_cfi[0x1]; 897 u8 inner_second_vid[0xc]; 898 u8 outer_second_cvlan_tag[0x1]; 899 u8 inner_second_cvlan_tag[0x1]; 900 u8 outer_second_svlan_tag[0x1]; 901 u8 inner_second_svlan_tag[0x1]; 902 u8 reserved_at_64[0xc]; 903 u8 gre_protocol[0x10]; 904 u8 gre_key_h[0x18]; 905 u8 gre_key_l[0x8]; 906 u8 vxlan_vni[0x18]; 907 u8 reserved_at_b8[0x8]; 908 u8 geneve_vni[0x18]; 909 u8 reserved_at_e4[0x6]; 910 u8 geneve_tlv_option_0_exist[0x1]; 911 u8 geneve_oam[0x1]; 912 u8 reserved_at_e0[0xc]; 913 u8 outer_ipv6_flow_label[0x14]; 914 u8 reserved_at_100[0xc]; 915 u8 inner_ipv6_flow_label[0x14]; 916 u8 reserved_at_120[0xa]; 917 u8 geneve_opt_len[0x6]; 918 u8 geneve_protocol_type[0x10]; 919 u8 reserved_at_140[0x20]; 920 u8 inner_esp_spi[0x20]; 921 u8 outer_esp_spi[0x20]; 922 u8 reserved_at_1a0[0x60]; 923 }; 924 925 struct mlx5_ifc_ipv4_layout_bits { 926 u8 reserved_at_0[0x60]; 927 u8 ipv4[0x20]; 928 }; 929 930 struct mlx5_ifc_ipv6_layout_bits { 931 u8 ipv6[16][0x8]; 932 }; 933 934 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 935 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 936 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 937 u8 reserved_at_0[0x80]; 938 }; 939 940 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 941 u8 smac_47_16[0x20]; 942 u8 smac_15_0[0x10]; 943 u8 ethertype[0x10]; 944 u8 dmac_47_16[0x20]; 945 u8 dmac_15_0[0x10]; 946 u8 first_prio[0x3]; 947 u8 first_cfi[0x1]; 948 u8 first_vid[0xc]; 949 u8 ip_protocol[0x8]; 950 u8 ip_dscp[0x6]; 951 u8 ip_ecn[0x2]; 952 u8 cvlan_tag[0x1]; 953 u8 svlan_tag[0x1]; 954 u8 frag[0x1]; 955 u8 ip_version[0x4]; 956 u8 tcp_flags[0x9]; 957 u8 tcp_sport[0x10]; 958 u8 tcp_dport[0x10]; 959 u8 reserved_at_c0[0x10]; 960 u8 ipv4_ihl[0x4]; 961 u8 l3_ok[0x1]; 962 u8 l4_ok[0x1]; 963 u8 ipv4_checksum_ok[0x1]; 964 u8 l4_checksum_ok[0x1]; 965 u8 ip_ttl_hoplimit[0x8]; 966 u8 udp_sport[0x10]; 967 u8 udp_dport[0x10]; 968 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 969 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 970 }; 971 972 struct mlx5_ifc_fte_match_mpls_bits { 973 u8 mpls_label[0x14]; 974 u8 mpls_exp[0x3]; 975 u8 mpls_s_bos[0x1]; 976 u8 mpls_ttl[0x8]; 977 }; 978 979 struct mlx5_ifc_fte_match_set_misc2_bits { 980 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 981 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 982 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 983 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 984 u8 metadata_reg_c_7[0x20]; 985 u8 metadata_reg_c_6[0x20]; 986 u8 metadata_reg_c_5[0x20]; 987 u8 metadata_reg_c_4[0x20]; 988 u8 metadata_reg_c_3[0x20]; 989 u8 metadata_reg_c_2[0x20]; 990 u8 metadata_reg_c_1[0x20]; 991 u8 metadata_reg_c_0[0x20]; 992 u8 metadata_reg_a[0x20]; 993 u8 metadata_reg_b[0x20]; 994 u8 reserved_at_1c0[0x40]; 995 }; 996 997 struct mlx5_ifc_fte_match_set_misc3_bits { 998 u8 inner_tcp_seq_num[0x20]; 999 u8 outer_tcp_seq_num[0x20]; 1000 u8 inner_tcp_ack_num[0x20]; 1001 u8 outer_tcp_ack_num[0x20]; 1002 u8 reserved_at_auto1[0x8]; 1003 u8 outer_vxlan_gpe_vni[0x18]; 1004 u8 outer_vxlan_gpe_next_protocol[0x8]; 1005 u8 outer_vxlan_gpe_flags[0x8]; 1006 u8 reserved_at_a8[0x10]; 1007 u8 icmp_header_data[0x20]; 1008 u8 icmpv6_header_data[0x20]; 1009 u8 icmp_type[0x8]; 1010 u8 icmp_code[0x8]; 1011 u8 icmpv6_type[0x8]; 1012 u8 icmpv6_code[0x8]; 1013 u8 geneve_tlv_option_0_data[0x20]; 1014 u8 gtpu_teid[0x20]; 1015 u8 gtpu_msg_type[0x08]; 1016 u8 gtpu_msg_flags[0x08]; 1017 u8 reserved_at_170[0x10]; 1018 u8 gtpu_dw_2[0x20]; 1019 u8 gtpu_first_ext_dw_0[0x20]; 1020 u8 gtpu_dw_0[0x20]; 1021 u8 reserved_at_240[0x20]; 1022 1023 }; 1024 1025 struct mlx5_ifc_fte_match_set_misc4_bits { 1026 u8 prog_sample_field_value_0[0x20]; 1027 u8 prog_sample_field_id_0[0x20]; 1028 u8 prog_sample_field_value_1[0x20]; 1029 u8 prog_sample_field_id_1[0x20]; 1030 u8 prog_sample_field_value_2[0x20]; 1031 u8 prog_sample_field_id_2[0x20]; 1032 u8 prog_sample_field_value_3[0x20]; 1033 u8 prog_sample_field_id_3[0x20]; 1034 u8 prog_sample_field_value_4[0x20]; 1035 u8 prog_sample_field_id_4[0x20]; 1036 u8 prog_sample_field_value_5[0x20]; 1037 u8 prog_sample_field_id_5[0x20]; 1038 u8 prog_sample_field_value_6[0x20]; 1039 u8 prog_sample_field_id_6[0x20]; 1040 u8 prog_sample_field_value_7[0x20]; 1041 u8 prog_sample_field_id_7[0x20]; 1042 }; 1043 1044 struct mlx5_ifc_fte_match_set_misc5_bits { 1045 u8 macsec_tag_0[0x20]; 1046 u8 macsec_tag_1[0x20]; 1047 u8 macsec_tag_2[0x20]; 1048 u8 macsec_tag_3[0x20]; 1049 u8 tunnel_header_0[0x20]; 1050 u8 tunnel_header_1[0x20]; 1051 u8 tunnel_header_2[0x20]; 1052 u8 tunnel_header_3[0x20]; 1053 u8 reserved[0x100]; 1054 }; 1055 1056 /* Flow matcher. */ 1057 struct mlx5_ifc_fte_match_param_bits { 1058 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1059 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1060 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1061 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1062 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1063 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1064 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1065 /* 1066 * Add reserved bit to match the struct size with the size defined in PRM. 1067 * This extension is not required in Linux. 1068 */ 1069 #ifndef HAVE_INFINIBAND_VERBS_H 1070 u8 reserved_0[0x200]; 1071 #endif 1072 }; 1073 1074 struct mlx5_ifc_dest_format_struct_bits { 1075 u8 destination_type[0x8]; 1076 u8 destination_id[0x18]; 1077 u8 reserved_0[0x20]; 1078 }; 1079 1080 enum { 1081 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 1082 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT, 1083 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT, 1084 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT, 1085 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT, 1086 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT, 1087 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT, 1088 }; 1089 1090 enum { 1091 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 1092 MLX5_CMD_OP_CREATE_MKEY = 0x200, 1093 MLX5_CMD_OP_CREATE_CQ = 0x400, 1094 MLX5_CMD_OP_CREATE_QP = 0x500, 1095 MLX5_CMD_OP_RST2INIT_QP = 0x502, 1096 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 1097 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 1098 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 1099 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 1100 MLX5_CMD_OP_QP_2ERR = 0x507, 1101 MLX5_CMD_OP_QP_2RST = 0x50A, 1102 MLX5_CMD_OP_QUERY_QP = 0x50B, 1103 MLX5_CMD_OP_SQD2RTS_QP = 0x50C, 1104 MLX5_CMD_OP_INIT2INIT_QP = 0x50E, 1105 MLX5_CMD_OP_SUSPEND_QP = 0x50F, 1106 MLX5_CMD_OP_RESUME_QP = 0x510, 1107 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 1108 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 1109 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 1110 MLX5_CMD_OP_ALLOC_PD = 0x800, 1111 MLX5_CMD_OP_DEALLOC_PD = 0x801, 1112 MLX5_CMD_OP_ACCESS_REGISTER = 0x805, 1113 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 1114 MLX5_CMD_OP_QUERY_LAG = 0x842, 1115 MLX5_CMD_OP_CREATE_TIR = 0x900, 1116 MLX5_CMD_OP_MODIFY_TIR = 0x901, 1117 MLX5_CMD_OP_CREATE_SQ = 0X904, 1118 MLX5_CMD_OP_MODIFY_SQ = 0X905, 1119 MLX5_CMD_OP_CREATE_RQ = 0x908, 1120 MLX5_CMD_OP_MODIFY_RQ = 0x909, 1121 MLX5_CMD_OP_QUERY_RQ = 0x90b, 1122 MLX5_CMD_OP_CREATE_RMP = 0x90c, 1123 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 1124 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 1125 MLX5_CMD_OP_QUERY_RMP = 0x90f, 1126 MLX5_CMD_OP_CREATE_TIS = 0x912, 1127 MLX5_CMD_OP_QUERY_TIS = 0x915, 1128 MLX5_CMD_OP_CREATE_RQT = 0x916, 1129 MLX5_CMD_OP_MODIFY_RQT = 0x917, 1130 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 1131 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 1132 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 1133 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 1134 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 1135 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 1136 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 1137 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 1138 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 1139 MLX5_CMD_SET_REGEX_PARAMS = 0xb04, 1140 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05, 1141 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06, 1142 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07, 1143 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c, 1144 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16, 1145 MLX5_CMD_OP_GENERATE_WQE = 0xb17, 1146 }; 1147 1148 enum { 1149 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 1150 MLX5_MKC_ACCESS_MODE_KLM = 0x2, 1151 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3, 1152 }; 1153 1154 #define MLX5_ADAPTER_PAGE_SHIFT 12 1155 #define MLX5_LOG_RQ_STRIDE_SHIFT 4 1156 /** 1157 * The batch counter dcs id starts from 0x800000 and none batch counter 1158 * starts from 0. As currently, the counter is changed to be indexed by 1159 * pool index and the offset of the counter in the pool counters_raw array. 1160 * It means now the counter index is same for batch and none batch counter. 1161 * Add the 0x800000 batch counter offset to the batch counter index helps 1162 * indicate the counter index is from batch or none batch container pool. 1163 */ 1164 #define MLX5_CNT_BATCH_OFFSET 0x800000 1165 1166 /* The counter batch query requires ID align with 4. */ 1167 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4 1168 1169 /* Flow counters. */ 1170 struct mlx5_ifc_alloc_flow_counter_out_bits { 1171 u8 status[0x8]; 1172 u8 reserved_at_8[0x18]; 1173 u8 syndrome[0x20]; 1174 u8 flow_counter_id[0x20]; 1175 u8 reserved_at_60[0x20]; 1176 }; 1177 1178 struct mlx5_ifc_alloc_flow_counter_in_bits { 1179 u8 opcode[0x10]; 1180 u8 reserved_at_10[0x10]; 1181 u8 reserved_at_20[0x10]; 1182 u8 op_mod[0x10]; 1183 u8 reserved_at_40[0x8]; 1184 u8 pd[0x18]; 1185 u8 reserved_at_60[0x13]; 1186 u8 flow_counter_bulk_log_size[0x5]; 1187 u8 flow_counter_bulk[0x8]; 1188 }; 1189 1190 struct mlx5_ifc_dealloc_flow_counter_out_bits { 1191 u8 status[0x8]; 1192 u8 reserved_at_8[0x18]; 1193 u8 syndrome[0x20]; 1194 u8 reserved_at_40[0x40]; 1195 }; 1196 1197 struct mlx5_ifc_dealloc_flow_counter_in_bits { 1198 u8 opcode[0x10]; 1199 u8 reserved_at_10[0x10]; 1200 u8 reserved_at_20[0x10]; 1201 u8 op_mod[0x10]; 1202 u8 flow_counter_id[0x20]; 1203 u8 reserved_at_60[0x20]; 1204 }; 1205 1206 struct mlx5_ifc_traffic_counter_bits { 1207 u8 packets[0x40]; 1208 u8 octets[0x40]; 1209 }; 1210 1211 struct mlx5_ifc_query_flow_counter_out_bits { 1212 u8 status[0x8]; 1213 u8 reserved_at_8[0x18]; 1214 u8 syndrome[0x20]; 1215 u8 reserved_at_40[0x40]; 1216 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 1217 }; 1218 1219 struct mlx5_ifc_query_flow_counter_in_bits { 1220 u8 opcode[0x10]; 1221 u8 reserved_at_10[0x10]; 1222 u8 reserved_at_20[0x10]; 1223 u8 op_mod[0x10]; 1224 u8 reserved_at_40[0x20]; 1225 u8 mkey[0x20]; 1226 u8 address[0x40]; 1227 u8 clear[0x1]; 1228 u8 dump_to_memory[0x1]; 1229 u8 num_of_counters[0x1e]; 1230 u8 flow_counter_id[0x20]; 1231 }; 1232 1233 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u 1234 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u 1235 1236 struct mlx5_ifc_klm_bits { 1237 u8 byte_count[0x20]; 1238 u8 mkey[0x20]; 1239 u8 address[0x40]; 1240 }; 1241 1242 struct mlx5_ifc_mkc_bits { 1243 u8 reserved_at_0[0x1]; 1244 u8 free[0x1]; 1245 u8 reserved_at_2[0x1]; 1246 u8 access_mode_4_2[0x3]; 1247 u8 reserved_at_6[0x7]; 1248 u8 relaxed_ordering_write[0x1]; 1249 u8 reserved_at_e[0x1]; 1250 u8 small_fence_on_rdma_read_response[0x1]; 1251 u8 umr_en[0x1]; 1252 u8 a[0x1]; 1253 u8 rw[0x1]; 1254 u8 rr[0x1]; 1255 u8 lw[0x1]; 1256 u8 lr[0x1]; 1257 u8 access_mode_1_0[0x2]; 1258 u8 reserved_at_18[0x8]; 1259 u8 qpn[0x18]; 1260 u8 mkey_7_0[0x8]; 1261 u8 reserved_at_40[0x20]; 1262 u8 length64[0x1]; 1263 u8 bsf_en[0x1]; 1264 u8 sync_umr[0x1]; 1265 u8 reserved_at_63[0x2]; 1266 u8 expected_sigerr_count[0x1]; 1267 u8 reserved_at_66[0x1]; 1268 u8 en_rinval[0x1]; 1269 u8 pd[0x18]; 1270 u8 start_addr[0x40]; 1271 u8 len[0x40]; 1272 u8 bsf_octword_size[0x20]; 1273 u8 reserved_at_120[0x80]; 1274 u8 translations_octword_size[0x20]; 1275 u8 reserved_at_1c0[0x19]; 1276 u8 relaxed_ordering_read[0x1]; 1277 u8 reserved_at_1da[0x1]; 1278 u8 log_page_size[0x5]; 1279 u8 reserved_at_1e0[0x3]; 1280 u8 crypto_en[0x2]; 1281 u8 reserved_at_1e5[0x1b]; 1282 }; 1283 1284 /* Range of values for MKEY context crypto_en field. */ 1285 enum { 1286 MLX5_MKEY_CRYPTO_DISABLED = 0x0, 1287 MLX5_MKEY_CRYPTO_ENABLED = 0x1, 1288 }; 1289 1290 struct mlx5_ifc_create_mkey_out_bits { 1291 u8 status[0x8]; 1292 u8 reserved_at_8[0x18]; 1293 u8 syndrome[0x20]; 1294 u8 reserved_at_40[0x8]; 1295 u8 mkey_index[0x18]; 1296 u8 reserved_at_60[0x20]; 1297 }; 1298 1299 struct mlx5_ifc_create_mkey_in_bits { 1300 u8 opcode[0x10]; 1301 u8 reserved_at_10[0x10]; 1302 u8 reserved_at_20[0x10]; 1303 u8 op_mod[0x10]; 1304 u8 reserved_at_40[0x20]; 1305 u8 pg_access[0x1]; 1306 u8 reserved_at_61[0x1f]; 1307 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 1308 u8 reserved_at_280[0x80]; 1309 u8 translations_octword_actual_size[0x20]; 1310 u8 mkey_umem_id[0x20]; 1311 u8 mkey_umem_offset[0x40]; 1312 u8 reserved_at_380[0x500]; 1313 u8 klm_pas_mtt[][0x20]; 1314 }; 1315 1316 enum { 1317 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, 1318 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, 1319 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1, 1320 MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, 1321 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, 1322 MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE = 0x8 << 1, 1323 MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1, 1324 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, 1325 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO = 0x1A << 1, 1326 MLX5_GET_HCA_CAP_OP_MOD_WQE_BASED_FLOW_TABLE = 0x1B << 1, 1327 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1, 1328 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, 1329 }; 1330 1331 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \ 1332 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ) 1333 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \ 1334 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS) 1335 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \ 1336 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH) 1337 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \ 1338 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO) 1339 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \ 1340 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO) 1341 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ 1342 (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT) 1343 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \ 1344 (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD) 1345 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEFINER \ 1346 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEFINER) 1347 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \ 1348 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK) 1349 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \ 1350 (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK) 1351 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \ 1352 (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL) 1353 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \ 1354 (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN) 1355 1356 enum { 1357 MLX5_HCA_CAP_OPMOD_GET_MAX = 0, 1358 MLX5_HCA_CAP_OPMOD_GET_CUR = 1, 1359 }; 1360 1361 enum { 1362 MLX5_CAP_INLINE_MODE_L2, 1363 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT, 1364 MLX5_CAP_INLINE_MODE_NOT_REQUIRED, 1365 }; 1366 1367 enum { 1368 MLX5_INLINE_MODE_NONE, 1369 MLX5_INLINE_MODE_L2, 1370 MLX5_INLINE_MODE_IP, 1371 MLX5_INLINE_MODE_TCP_UDP, 1372 MLX5_INLINE_MODE_RESERVED4, 1373 MLX5_INLINE_MODE_INNER_L2, 1374 MLX5_INLINE_MODE_INNER_IP, 1375 MLX5_INLINE_MODE_INNER_TCP_UDP, 1376 }; 1377 1378 /* The supported timestamp formats reported in HCA attributes. */ 1379 enum { 1380 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0, 1381 MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1, 1382 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2, 1383 }; 1384 1385 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */ 1386 enum { 1387 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 1388 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 1389 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 1390 }; 1391 1392 /* HCA bit masks indicating which Flex parser protocols are already enabled. */ 1393 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0) 1394 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1) 1395 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2) 1396 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3) 1397 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4) 1398 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5) 1399 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6) 1400 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7) 1401 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8) 1402 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9) 1403 #define MLX5_HCA_FLEX_GTPU_ENABLED (1UL << 11) 1404 #define MLX5_HCA_FLEX_GTPU_DW_2_ENABLED (1UL << 16) 1405 #define MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED (1UL << 17) 1406 #define MLX5_HCA_FLEX_GTPU_DW_0_ENABLED (1UL << 18) 1407 #define MLX5_HCA_FLEX_GTPU_TEID_ENABLED (1UL << 19) 1408 1409 /* The device steering logic format. */ 1410 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0 1411 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1 1412 1413 struct mlx5_ifc_cmd_hca_cap_bits { 1414 u8 access_other_hca_roce[0x1]; 1415 u8 alloc_flow_counter_pd[0x1]; 1416 u8 flow_counter_access_aso[0x1]; 1417 u8 reserved_at_3[0x5]; 1418 u8 flow_access_aso_opc_mod[0x8]; 1419 u8 reserved_at_10[0xf]; 1420 u8 vhca_resource_manager[0x1]; 1421 u8 hca_cap_2[0x1]; 1422 u8 reserved_at_21[0xf]; 1423 u8 vhca_id[0x10]; 1424 u8 reserved_at_40[0x20]; 1425 u8 reserved_at_60[0x3]; 1426 u8 log_regexp_scatter_gather_size[0x5]; 1427 u8 reserved_at_68[0x3]; 1428 u8 log_dma_mmo_size[0x5]; 1429 u8 reserved_at_70[0x3]; 1430 u8 log_compress_mmo_size[0x5]; 1431 u8 reserved_at_78[0x3]; 1432 u8 log_decompress_mmo_size[0x5]; 1433 u8 log_max_srq_sz[0x8]; 1434 u8 log_max_qp_sz[0x8]; 1435 u8 reserved_at_90[0x9]; 1436 u8 wqe_index_ignore_cap[0x1]; 1437 u8 dynamic_qp_allocation[0x1]; 1438 u8 log_max_qp[0x5]; 1439 u8 reserved_at_a0[0x4]; 1440 u8 regexp_num_of_engines[0x4]; 1441 u8 reserved_at_a8[0x1]; 1442 u8 reg_c_preserve[0x1]; 1443 u8 reserved_at_aa[0x1]; 1444 u8 log_max_srq[0x5]; 1445 u8 reserved_at_b0[0xb]; 1446 u8 scatter_fcs_w_decap_disable[0x1]; 1447 u8 reserved_at_bc[0x4]; 1448 u8 reserved_at_c0[0x8]; 1449 u8 log_max_cq_sz[0x8]; 1450 u8 reserved_at_d0[0x2]; 1451 u8 access_register_user[0x1]; 1452 u8 reserved_at_d3[0x8]; 1453 u8 log_max_cq[0x5]; 1454 u8 log_max_eq_sz[0x8]; 1455 u8 relaxed_ordering_write[0x1]; 1456 u8 relaxed_ordering_read[0x1]; 1457 u8 log_max_mkey[0x6]; 1458 u8 reserved_at_f0[0x8]; 1459 u8 dump_fill_mkey[0x1]; 1460 u8 reserved_at_f9[0x3]; 1461 u8 log_max_eq[0x4]; 1462 u8 max_indirection[0x8]; 1463 u8 fixed_buffer_size[0x1]; 1464 u8 log_max_mrw_sz[0x7]; 1465 u8 force_teardown[0x1]; 1466 u8 reserved_at_111[0x1]; 1467 u8 log_max_bsf_list_size[0x6]; 1468 u8 umr_extended_translation_offset[0x1]; 1469 u8 null_mkey[0x1]; 1470 u8 log_max_klm_list_size[0x6]; 1471 u8 non_wire_sq[0x1]; 1472 u8 reserved_at_121[0x9]; 1473 u8 log_max_ra_req_dc[0x6]; 1474 u8 reserved_at_130[0x3]; 1475 u8 log_max_static_sq_wq[0x5]; 1476 u8 reserved_at_138[0x2]; 1477 u8 log_max_ra_res_dc[0x6]; 1478 u8 reserved_at_140[0xa]; 1479 u8 log_max_ra_req_qp[0x6]; 1480 u8 rtr2rts_qp_counters_set_id[0x1]; 1481 u8 rts2rts_udp_sport[0x1]; 1482 u8 rts2rts_lag_tx_port_affinity[0x1]; 1483 u8 dma_mmo_sq[0x1]; 1484 u8 compress_min_block_size[0x4]; 1485 u8 compress_mmo_sq[0x1]; 1486 u8 decompress_mmo_sq[0x1]; 1487 u8 log_max_ra_res_qp[0x6]; 1488 u8 end_pad[0x1]; 1489 u8 cc_query_allowed[0x1]; 1490 u8 cc_modify_allowed[0x1]; 1491 u8 start_pad[0x1]; 1492 u8 cache_line_128byte[0x1]; 1493 u8 reserved_at_165[0xa]; 1494 u8 qcam_reg[0x1]; 1495 u8 gid_table_size[0x10]; 1496 u8 out_of_seq_cnt[0x1]; 1497 u8 vport_counters[0x1]; 1498 u8 retransmission_q_counters[0x1]; 1499 u8 debug[0x1]; 1500 u8 modify_rq_counter_set_id[0x1]; 1501 u8 rq_delay_drop[0x1]; 1502 u8 max_qp_cnt[0xa]; 1503 u8 pkey_table_size[0x10]; 1504 u8 vport_group_manager[0x1]; 1505 u8 vhca_group_manager[0x1]; 1506 u8 ib_virt[0x1]; 1507 u8 eth_virt[0x1]; 1508 u8 vnic_env_queue_counters[0x1]; 1509 u8 ets[0x1]; 1510 u8 nic_flow_table[0x1]; 1511 u8 eswitch_manager[0x1]; 1512 u8 device_memory[0x1]; 1513 u8 mcam_reg[0x1]; 1514 u8 pcam_reg[0x1]; 1515 u8 local_ca_ack_delay[0x5]; 1516 u8 port_module_event[0x1]; 1517 u8 enhanced_error_q_counters[0x1]; 1518 u8 ports_check[0x1]; 1519 u8 reserved_at_1b3[0x1]; 1520 u8 disable_link_up[0x1]; 1521 u8 beacon_led[0x1]; 1522 u8 port_type[0x2]; 1523 u8 num_ports[0x8]; 1524 u8 reserved_at_1c0[0x1]; 1525 u8 pps[0x1]; 1526 u8 pps_modify[0x1]; 1527 u8 log_max_msg[0x5]; 1528 u8 reserved_at_1c8[0x4]; 1529 u8 max_tc[0x4]; 1530 u8 temp_warn_event[0x1]; 1531 u8 dcbx[0x1]; 1532 u8 general_notification_event[0x1]; 1533 u8 reserved_at_1d3[0x2]; 1534 u8 fpga[0x1]; 1535 u8 rol_s[0x1]; 1536 u8 rol_g[0x1]; 1537 u8 reserved_at_1d8[0x1]; 1538 u8 wol_s[0x1]; 1539 u8 wol_g[0x1]; 1540 u8 wol_a[0x1]; 1541 u8 wol_b[0x1]; 1542 u8 wol_m[0x1]; 1543 u8 wol_u[0x1]; 1544 u8 wol_p[0x1]; 1545 u8 stat_rate_support[0x10]; 1546 u8 reserved_at_1ef[0xb]; 1547 u8 wqe_based_flow_table_update_cap[0x1]; 1548 u8 cqe_version[0x4]; 1549 u8 compact_address_vector[0x1]; 1550 u8 striding_rq[0x1]; 1551 u8 reserved_at_202[0x1]; 1552 u8 ipoib_enhanced_offloads[0x1]; 1553 u8 ipoib_basic_offloads[0x1]; 1554 u8 reserved_at_205[0x1]; 1555 u8 repeated_block_disabled[0x1]; 1556 u8 umr_modify_entity_size_disabled[0x1]; 1557 u8 umr_modify_atomic_disabled[0x1]; 1558 u8 umr_indirect_mkey_disabled[0x1]; 1559 u8 umr_fence[0x2]; 1560 u8 reserved_at_20c[0x3]; 1561 u8 drain_sigerr[0x1]; 1562 u8 cmdif_checksum[0x2]; 1563 u8 sigerr_cqe[0x1]; 1564 u8 reserved_at_213[0x1]; 1565 u8 wq_signature[0x1]; 1566 u8 sctr_data_cqe[0x1]; 1567 u8 reserved_at_216[0x1]; 1568 u8 sho[0x1]; 1569 u8 tph[0x1]; 1570 u8 rf[0x1]; 1571 u8 dct[0x1]; 1572 u8 qos[0x1]; 1573 u8 eth_net_offloads[0x1]; 1574 u8 roce[0x1]; 1575 u8 atomic[0x1]; 1576 u8 reserved_at_21f[0x1]; 1577 u8 cq_oi[0x1]; 1578 u8 cq_resize[0x1]; 1579 u8 cq_moderation[0x1]; 1580 u8 reserved_at_223[0x3]; 1581 u8 cq_eq_remap[0x1]; 1582 u8 pg[0x1]; 1583 u8 block_lb_mc[0x1]; 1584 u8 reserved_at_229[0x1]; 1585 u8 scqe_break_moderation[0x1]; 1586 u8 cq_period_start_from_cqe[0x1]; 1587 u8 cd[0x1]; 1588 u8 reserved_at_22d[0x1]; 1589 u8 apm[0x1]; 1590 u8 vector_calc[0x1]; 1591 u8 umr_ptr_rlky[0x1]; 1592 u8 imaicl[0x1]; 1593 u8 reserved_at_232[0x4]; 1594 u8 qkv[0x1]; 1595 u8 pkv[0x1]; 1596 u8 set_deth_sqpn[0x1]; 1597 u8 reserved_at_239[0x3]; 1598 u8 xrc[0x1]; 1599 u8 ud[0x1]; 1600 u8 uc[0x1]; 1601 u8 rc[0x1]; 1602 u8 uar_4k[0x1]; 1603 u8 reserved_at_241[0x8]; 1604 u8 regexp_params[0x1]; 1605 u8 uar_sz[0x6]; 1606 u8 port_selection_cap[0x1]; 1607 u8 reserved_at_251[0x7]; 1608 u8 log_pg_sz[0x8]; 1609 u8 bf[0x1]; 1610 u8 driver_version[0x1]; 1611 u8 pad_tx_eth_packet[0x1]; 1612 u8 reserved_at_263[0x8]; 1613 u8 log_bf_reg_size[0x5]; 1614 u8 reserved_at_270[0xb]; 1615 u8 lag_master[0x1]; 1616 u8 num_lag_ports[0x4]; 1617 u8 reserved_at_280[0x10]; 1618 u8 max_wqe_sz_sq[0x10]; 1619 u8 reserved_at_2a0[0xc]; 1620 u8 regexp_mmo_sq[0x1]; 1621 u8 regexp_version[0x3]; 1622 u8 max_wqe_sz_rq[0x10]; 1623 u8 max_flow_counter_31_16[0x10]; 1624 u8 max_wqe_sz_sq_dc[0x10]; 1625 u8 reserved_at_2e0[0x7]; 1626 u8 max_qp_mcg[0x19]; 1627 u8 reserved_at_300[0x10]; 1628 u8 flow_counter_bulk_alloc[0x08]; 1629 u8 log_max_mcg[0x8]; 1630 u8 reserved_at_320[0x3]; 1631 u8 log_max_transport_domain[0x5]; 1632 u8 reserved_at_328[0x3]; 1633 u8 log_max_pd[0x5]; 1634 u8 reserved_at_330[0xb]; 1635 u8 log_max_xrcd[0x5]; 1636 u8 nic_receive_steering_discard[0x1]; 1637 u8 receive_discard_vport_down[0x1]; 1638 u8 transmit_discard_vport_down[0x1]; 1639 u8 reserved_at_343[0x5]; 1640 u8 log_max_flow_counter_bulk[0x8]; 1641 u8 max_flow_counter_15_0[0x10]; 1642 u8 modify_tis[0x1]; 1643 u8 flow_counters_dump[0x1]; 1644 u8 reserved_at_360[0x1]; 1645 u8 log_max_rq[0x5]; 1646 u8 reserved_at_368[0x3]; 1647 u8 log_max_sq[0x5]; 1648 u8 reserved_at_370[0x3]; 1649 u8 log_max_tir[0x5]; 1650 u8 reserved_at_378[0x3]; 1651 u8 log_max_tis[0x5]; 1652 u8 basic_cyclic_rcv_wqe[0x1]; 1653 u8 reserved_at_381[0x1]; 1654 u8 mem_rq_rmp[0x1]; 1655 u8 log_max_rmp[0x5]; 1656 u8 reserved_at_388[0x3]; 1657 u8 log_max_rqt[0x5]; 1658 u8 reserved_at_390[0x3]; 1659 u8 log_max_rqt_size[0x5]; 1660 u8 reserved_at_398[0x3]; 1661 u8 log_max_tis_per_sq[0x5]; 1662 u8 ext_stride_num_range[0x1]; 1663 u8 reserved_at_3a1[0x2]; 1664 u8 log_max_stride_sz_rq[0x5]; 1665 u8 reserved_at_3a8[0x3]; 1666 u8 log_min_stride_sz_rq[0x5]; 1667 u8 reserved_at_3b0[0x3]; 1668 u8 log_max_stride_sz_sq[0x5]; 1669 u8 reserved_at_3b8[0x3]; 1670 u8 log_min_stride_sz_sq[0x5]; 1671 u8 hairpin[0x1]; 1672 u8 reserved_at_3c1[0x2]; 1673 u8 log_max_hairpin_queues[0x5]; 1674 u8 reserved_at_3c8[0x3]; 1675 u8 log_max_hairpin_wq_data_sz[0x5]; 1676 u8 reserved_at_3d0[0x3]; 1677 u8 log_max_hairpin_num_packets[0x5]; 1678 u8 reserved_at_3d8[0x3]; 1679 u8 log_max_wq_sz[0x5]; 1680 u8 nic_vport_change_event[0x1]; 1681 u8 disable_local_lb_uc[0x1]; 1682 u8 disable_local_lb_mc[0x1]; 1683 u8 log_min_hairpin_wq_data_sz[0x5]; 1684 u8 reserved_at_3e8[0x3]; 1685 u8 log_max_vlan_list[0x5]; 1686 u8 reserved_at_3f0[0x1]; 1687 u8 aes_xts_single_block_le_tweak[1]; 1688 u8 aes_xts_multi_block_be_tweak[1]; 1689 u8 log_max_current_mc_list[0x5]; 1690 u8 reserved_at_3f8[0x3]; 1691 u8 log_max_current_uc_list[0x5]; 1692 u8 general_obj_types[0x40]; 1693 u8 sq_ts_format[0x2]; 1694 u8 rq_ts_format[0x2]; 1695 u8 steering_format_version[0x4]; 1696 u8 reserved_at_448[0x18]; 1697 u8 reserved_at_460[0x8]; 1698 u8 aes_xts[0x1]; 1699 u8 crypto[0x1]; 1700 u8 ipsec_offload[0x1]; 1701 u8 reserved_at_46b[0x5]; 1702 u8 max_num_eqs[0x10]; 1703 u8 reserved_at_480[0x3]; 1704 u8 log_max_l2_table[0x5]; 1705 u8 reserved_at_488[0x8]; 1706 u8 log_uar_page_sz[0x10]; 1707 u8 reserved_at_4a0[0x20]; 1708 u8 device_frequency_mhz[0x20]; 1709 u8 device_frequency_khz[0x20]; 1710 u8 reserved_at_500[0x20]; 1711 u8 num_of_uars_per_page[0x20]; 1712 u8 flex_parser_protocols[0x20]; 1713 u8 max_geneve_tlv_options[0x8]; 1714 u8 reserved_at_568[0x3]; 1715 u8 max_geneve_tlv_option_data_len[0x5]; 1716 u8 reserved_at_570[0x49]; 1717 u8 mini_cqe_resp_l3_l4_tag[0x1]; 1718 u8 mini_cqe_resp_flow_tag[0x1]; 1719 u8 enhanced_cqe_compression[0x1]; 1720 u8 mini_cqe_resp_stride_index[0x1]; 1721 u8 cqe_128_always[0x1]; 1722 u8 cqe_compression_128[0x1]; 1723 u8 cqe_compression[0x1]; 1724 u8 cqe_compression_timeout[0x10]; 1725 u8 cqe_compression_max_num[0x10]; 1726 u8 reserved_at_5e0[0x8]; 1727 u8 flex_parser_id_gtpu_dw_0[0x4]; 1728 u8 reserved_at_5ec[0x4]; 1729 u8 tag_matching[0x1]; 1730 u8 rndv_offload_rc[0x1]; 1731 u8 rndv_offload_dc[0x1]; 1732 u8 log_tag_matching_list_sz[0x5]; 1733 u8 reserved_at_5f8[0x3]; 1734 u8 log_max_xrq[0x5]; 1735 u8 affiliate_nic_vport_criteria[0x8]; 1736 u8 native_port_num[0x8]; 1737 u8 num_vhca_ports[0x8]; 1738 u8 flex_parser_id_gtpu_teid[0x4]; 1739 u8 reserved_at_61c[0x2]; 1740 u8 sw_owner_id[0x1]; 1741 u8 reserved_at_61f[0x6C]; 1742 u8 wait_on_data[0x1]; 1743 u8 wait_on_time[0x1]; 1744 u8 reserved_at_68d[0x37]; 1745 u8 flex_parser_id_geneve_opt_0[0x4]; 1746 u8 flex_parser_id_icmp_dw1[0x4]; 1747 u8 flex_parser_id_icmp_dw0[0x4]; 1748 u8 flex_parser_id_icmpv6_dw1[0x4]; 1749 u8 flex_parser_id_icmpv6_dw0[0x4]; 1750 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1751 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1752 u8 reserved_at_6e0[0x20]; 1753 u8 flex_parser_id_gtpu_dw_2[0x4]; 1754 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1755 u8 reserved_at_708[0x40]; 1756 u8 dma_mmo_qp[0x1]; 1757 u8 regexp_mmo_qp[0x1]; 1758 u8 compress_mmo_qp[0x1]; 1759 u8 decompress_mmo_qp[0x1]; 1760 u8 reserved_at_74c[0x14]; 1761 u8 reserved_at_760[0x3]; 1762 u8 log_max_num_header_modify_argument[0x5]; 1763 u8 log_header_modify_argument_granularity_offset[0x4]; 1764 u8 log_header_modify_argument_granularity[0x4]; 1765 u8 reserved_at_770[0x3]; 1766 u8 log_header_modify_argument_max_alloc[0x5]; 1767 u8 reserved_at_778[0x8]; 1768 u8 reserved_at_780[0x40]; 1769 u8 match_definer_format_supported[0x40]; 1770 }; 1771 1772 struct mlx5_ifc_qos_cap_bits { 1773 u8 packet_pacing[0x1]; 1774 u8 esw_scheduling[0x1]; 1775 u8 esw_bw_share[0x1]; 1776 u8 esw_rate_limit[0x1]; 1777 u8 reserved_at_4[0x1]; 1778 u8 packet_pacing_burst_bound[0x1]; 1779 u8 packet_pacing_typical_size[0x1]; 1780 u8 flow_meter_old[0x1]; 1781 u8 reserved_at_8[0x8]; 1782 u8 log_max_flow_meter[0x8]; 1783 u8 flow_meter_reg_id[0x8]; 1784 u8 wqe_rate_pp[0x1]; 1785 u8 reserved_at_25[0x7]; 1786 u8 flow_meter[0x1]; 1787 u8 reserved_at_2e[0x17]; 1788 u8 packet_pacing_max_rate[0x20]; 1789 u8 packet_pacing_min_rate[0x20]; 1790 u8 reserved_at_80[0x10]; 1791 u8 packet_pacing_rate_table_size[0x10]; 1792 u8 esw_element_type[0x10]; 1793 u8 esw_tsar_type[0x10]; 1794 u8 reserved_at_c0[0x10]; 1795 u8 max_qos_para_vport[0x10]; 1796 u8 max_tsar_bw_share[0x20]; 1797 u8 nic_element_type[0x10]; 1798 u8 nic_tsar_type[0x10]; 1799 u8 reserved_at_120[0x3]; 1800 u8 log_meter_aso_granularity[0x5]; 1801 u8 reserved_at_128[0x3]; 1802 u8 log_meter_aso_max_alloc[0x5]; 1803 u8 reserved_at_130[0x3]; 1804 u8 log_max_num_meter_aso[0x5]; 1805 u8 reserved_at_138[0x6b0]; 1806 }; 1807 1808 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1809 u8 csum_cap[0x1]; 1810 u8 vlan_cap[0x1]; 1811 u8 lro_cap[0x1]; 1812 u8 lro_psh_flag[0x1]; 1813 u8 lro_time_stamp[0x1]; 1814 u8 lro_max_msg_sz_mode[0x2]; 1815 u8 wqe_vlan_insert[0x1]; 1816 u8 self_lb_en_modifiable[0x1]; 1817 u8 self_lb_mc[0x1]; 1818 u8 self_lb_uc[0x1]; 1819 u8 max_lso_cap[0x5]; 1820 u8 multi_pkt_send_wqe[0x2]; 1821 u8 wqe_inline_mode[0x2]; 1822 u8 rss_ind_tbl_cap[0x4]; 1823 u8 reg_umr_sq[0x1]; 1824 u8 scatter_fcs[0x1]; 1825 u8 enhanced_multi_pkt_send_wqe[0x1]; 1826 u8 tunnel_lso_const_out_ip_id[0x1]; 1827 u8 tunnel_lro_gre[0x1]; 1828 u8 tunnel_lro_vxlan[0x1]; 1829 u8 tunnel_stateless_gre[0x1]; 1830 u8 tunnel_stateless_vxlan[0x1]; 1831 u8 swp[0x1]; 1832 u8 swp_csum[0x1]; 1833 u8 swp_lso[0x1]; 1834 u8 reserved_at_23[0x8]; 1835 u8 tunnel_stateless_gtp[0x1]; 1836 u8 reserved_at_25[0x4]; 1837 u8 max_vxlan_udp_ports[0x8]; 1838 u8 reserved_at_38[0x6]; 1839 u8 max_geneve_opt_len[0x1]; 1840 u8 tunnel_stateless_geneve_rx[0x1]; 1841 u8 reserved_at_40[0x10]; 1842 u8 lro_min_mss_size[0x10]; 1843 u8 reserved_at_60[0x120]; 1844 u8 lro_timer_supported_periods[4][0x20]; 1845 u8 reserved_at_200[0x600]; 1846 }; 1847 1848 enum { 1849 MLX5_VIRTQ_TYPE_SPLIT = 0, 1850 MLX5_VIRTQ_TYPE_PACKED = 1, 1851 }; 1852 1853 enum { 1854 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0, 1855 MLX5_VIRTQ_EVENT_MODE_QP = 1, 1856 MLX5_VIRTQ_EVENT_MODE_MSIX = 2, 1857 }; 1858 1859 struct mlx5_ifc_virtio_emulation_cap_bits { 1860 u8 desc_tunnel_offload_type[0x1]; 1861 u8 eth_frame_offload_type[0x1]; 1862 u8 virtio_version_1_0[0x1]; 1863 u8 tso_ipv4[0x1]; 1864 u8 tso_ipv6[0x1]; 1865 u8 tx_csum[0x1]; 1866 u8 rx_csum[0x1]; 1867 u8 reserved_at_7[0x1][0x9]; 1868 u8 event_mode[0x8]; 1869 u8 virtio_queue_type[0x8]; 1870 u8 reserved_at_20[0x13]; 1871 u8 log_doorbell_stride[0x5]; 1872 u8 vnet_modify_ext[0x1]; 1873 u8 virtio_net_q_addr_modify[0x1]; 1874 u8 virtio_q_index_modify[0x1]; 1875 u8 log_doorbell_bar_size[0x5]; 1876 u8 doorbell_bar_offset[0x40]; 1877 u8 reserved_at_80[0x8]; 1878 u8 max_num_virtio_queues[0x18]; 1879 u8 reserved_at_a0[0x60]; 1880 u8 umem_1_buffer_param_a[0x20]; 1881 u8 umem_1_buffer_param_b[0x20]; 1882 u8 umem_2_buffer_param_a[0x20]; 1883 u8 umem_2_buffer_param_b[0x20]; 1884 u8 umem_3_buffer_param_a[0x20]; 1885 u8 umem_3_buffer_param_b[0x20]; 1886 u8 reserved_at_1c0[0x620]; 1887 }; 1888 1889 /** 1890 * PARSE_GRAPH_NODE Capabilities Field Descriptions 1891 */ 1892 struct mlx5_ifc_parse_graph_node_cap_bits { 1893 u8 node_in[0x20]; 1894 u8 node_out[0x20]; 1895 u8 header_length_mode[0x10]; 1896 u8 sample_offset_mode[0x10]; 1897 u8 max_num_arc_in[0x08]; 1898 u8 max_num_arc_out[0x08]; 1899 u8 max_num_sample[0x08]; 1900 u8 reserved_at_78[0x03]; 1901 u8 anchor_en[0x1]; 1902 u8 ext_sample_id[0x1]; 1903 u8 sample_tunnel_inner2[0x1]; 1904 u8 zero_size_supported[0x1]; 1905 u8 sample_id_in_out[0x1]; 1906 u8 max_base_header_length[0x10]; 1907 u8 reserved_at_90[0x08]; 1908 u8 max_sample_base_offset[0x08]; 1909 u8 max_next_header_offset[0x10]; 1910 u8 reserved_at_b0[0x08]; 1911 u8 header_length_mask_width[0x08]; 1912 }; 1913 1914 /* ext_sample_id structure, see PRM Table: Flow Match Sample ID Format. */ 1915 struct mlx5_ext_sample_id { 1916 union { 1917 struct { 1918 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 1919 uint32_t format_select_dw:8; 1920 uint32_t modify_field_id:12; 1921 uint32_t sample_id:12; 1922 #else 1923 uint32_t sample_id:12; 1924 uint32_t modify_field_id:12; 1925 uint32_t format_select_dw:8; 1926 #endif 1927 }; 1928 uint32_t id; 1929 }; 1930 }; 1931 1932 struct mlx5_ifc_flow_table_prop_layout_bits { 1933 u8 ft_support[0x1]; 1934 u8 flow_tag[0x1]; 1935 u8 flow_counter[0x1]; 1936 u8 flow_modify_en[0x1]; 1937 u8 modify_root[0x1]; 1938 u8 identified_miss_table[0x1]; 1939 u8 flow_table_modify[0x1]; 1940 u8 reformat[0x1]; 1941 u8 decap[0x1]; 1942 u8 reset_root_to_default[0x1]; 1943 u8 pop_vlan[0x1]; 1944 u8 push_vlan[0x1]; 1945 u8 fpga_vendor_acceleration[0x1]; 1946 u8 pop_vlan_2[0x1]; 1947 u8 push_vlan_2[0x1]; 1948 u8 reformat_and_vlan_action[0x1]; 1949 u8 modify_and_vlan_action[0x1]; 1950 u8 sw_owner[0x1]; 1951 u8 reformat_l3_tunnel_to_l2[0x1]; 1952 u8 reformat_l2_to_l3_tunnel[0x1]; 1953 u8 reformat_and_modify_action[0x1]; 1954 u8 reserved_at_15[0x9]; 1955 u8 sw_owner_v2[0x1]; 1956 u8 reserved_at_1f[0x1]; 1957 u8 reserved_at_20[0x2]; 1958 u8 log_max_ft_size[0x6]; 1959 u8 log_max_modify_header_context[0x8]; 1960 u8 max_modify_header_actions[0x8]; 1961 u8 max_ft_level[0x8]; 1962 u8 reserved_at_40[0x8]; 1963 u8 log_max_ft_sampler_num[8]; 1964 u8 metadata_reg_b_width[0x8]; 1965 u8 metadata_reg_a_width[0x8]; 1966 u8 reserved_at_60[0xa]; 1967 u8 reparse[0x1]; 1968 u8 reserved_at_6b[0x1]; 1969 u8 cross_vhca_object[0x1]; 1970 u8 reserved_at_6d[0xb]; 1971 u8 log_max_ft_num[0x8]; 1972 u8 reserved_at_80[0x10]; 1973 u8 log_max_flow_counter[0x8]; 1974 u8 log_max_destination[0x8]; 1975 u8 reserved_at_a0[0x18]; 1976 u8 log_max_flow[0x8]; 1977 u8 reserved_at_c0[0x140]; 1978 }; 1979 1980 struct mlx5_ifc_roce_caps_bits { 1981 u8 reserved_0[0x1e]; 1982 u8 qp_ts_format[0x2]; 1983 u8 reserved_at_20[0x7e0]; 1984 }; 1985 1986 struct mlx5_ifc_ft_fields_support_bits { 1987 /* set_action_field_support */ 1988 u8 outer_dmac[0x1]; 1989 u8 outer_smac[0x1]; 1990 u8 outer_ether_type[0x1]; 1991 u8 reserved_at_3[0x1]; 1992 u8 outer_first_prio[0x1]; 1993 u8 outer_first_cfi[0x1]; 1994 u8 outer_first_vid[0x1]; 1995 u8 reserved_at_7[0x1]; 1996 u8 outer_second_prio[0x1]; 1997 u8 outer_second_cfi[0x1]; 1998 u8 outer_second_vid[0x1]; 1999 u8 reserved_at_b[0x1]; 2000 u8 outer_sip[0x1]; 2001 u8 outer_dip[0x1]; 2002 u8 outer_frag[0x1]; 2003 u8 outer_ip_protocol[0x1]; 2004 u8 outer_ip_ecn[0x1]; 2005 u8 outer_ip_dscp[0x1]; 2006 u8 outer_udp_sport[0x1]; 2007 u8 outer_udp_dport[0x1]; 2008 u8 outer_tcp_sport[0x1]; 2009 u8 outer_tcp_dport[0x1]; 2010 u8 outer_tcp_flags[0x1]; 2011 u8 outer_gre_protocol[0x1]; 2012 u8 outer_gre_key[0x1]; 2013 u8 outer_vxlan_vni[0x1]; 2014 u8 reserved_at_1a[0x5]; 2015 u8 source_eswitch_port[0x1]; /* end of DW0 */ 2016 u8 inner_dmac[0x1]; 2017 u8 inner_smac[0x1]; 2018 u8 inner_ether_type[0x1]; 2019 u8 reserved_at_23[0x1]; 2020 u8 inner_first_prio[0x1]; 2021 u8 inner_first_cfi[0x1]; 2022 u8 inner_first_vid[0x1]; 2023 u8 reserved_at_27[0x1]; 2024 u8 inner_second_prio[0x1]; 2025 u8 inner_second_cfi[0x1]; 2026 u8 inner_second_vid[0x1]; 2027 u8 reserved_at_2b[0x1]; 2028 u8 inner_sip[0x1]; 2029 u8 inner_dip[0x1]; 2030 u8 inner_frag[0x1]; 2031 u8 inner_ip_protocol[0x1]; 2032 u8 inner_ip_ecn[0x1]; 2033 u8 inner_ip_dscp[0x1]; 2034 u8 inner_udp_sport[0x1]; 2035 u8 inner_udp_dport[0x1]; 2036 u8 inner_tcp_sport[0x1]; 2037 u8 inner_tcp_dport[0x1]; 2038 u8 inner_tcp_flags[0x1]; 2039 u8 reserved_at_37[0x9]; /* end of DW1 */ 2040 u8 reserved_at_40[0x20]; /* end of DW2 */ 2041 u8 reserved_at_60[0x18]; 2042 union { 2043 struct { 2044 u8 metadata_reg_c_7[0x1]; 2045 u8 metadata_reg_c_6[0x1]; 2046 u8 metadata_reg_c_5[0x1]; 2047 u8 metadata_reg_c_4[0x1]; 2048 u8 metadata_reg_c_3[0x1]; 2049 u8 metadata_reg_c_2[0x1]; 2050 u8 metadata_reg_c_1[0x1]; 2051 u8 metadata_reg_c_0[0x1]; 2052 }; 2053 u8 metadata_reg_c_x[0x8]; 2054 }; /* end of DW3 */ 2055 /* set_action_field_support_2 */ 2056 u8 reserved_at_80[0x80]; 2057 /* add_action_field_support */ 2058 u8 reserved_at_100[0x80]; 2059 /* add_action_field_support_2 */ 2060 u8 reserved_at_180[0x80]; 2061 /* copy_action_field_support */ 2062 u8 reserved_at_200[0x80]; 2063 /* copy_action_field_support_2 */ 2064 u8 reserved_at_280[0x80]; 2065 u8 reserved_at_300[0x100]; 2066 }; 2067 2068 /* 2069 * Table 1872 - Flow Table Fields Supported 2 Format 2070 */ 2071 struct mlx5_ifc_ft_fields_support_2_bits { 2072 u8 reserved_at_0[0xd]; 2073 u8 hash_result[0x1]; 2074 u8 reserved_at_e[0x1]; 2075 u8 tunnel_header_2_3[0x1]; 2076 u8 tunnel_header_0_1[0x1]; 2077 u8 macsec_syndrome[0x1]; 2078 u8 macsec_tag[0x1]; 2079 u8 outer_lrh_sl[0x1]; 2080 u8 inner_ipv4_ihl[0x1]; 2081 u8 outer_ipv4_ihl[0x1]; 2082 u8 psp_syndrome[0x1]; 2083 u8 inner_l3_ok[0x1]; 2084 u8 inner_l4_ok[0x1]; 2085 u8 outer_l3_ok[0x1]; 2086 u8 outer_l4_ok[0x1]; 2087 u8 psp_header[0x1]; 2088 u8 inner_ipv4_checksum_ok[0x1]; 2089 u8 inner_l4_checksum_ok[0x1]; 2090 u8 outer_ipv4_checksum_ok[0x1]; 2091 u8 outer_l4_checksum_ok[0x1]; 2092 u8 reserved_at_20[0x60]; 2093 }; 2094 2095 struct mlx5_ifc_flow_table_nic_cap_bits { 2096 u8 reserved_at_0[0x200]; 2097 struct mlx5_ifc_flow_table_prop_layout_bits 2098 flow_table_properties_nic_receive; 2099 struct mlx5_ifc_flow_table_prop_layout_bits 2100 flow_table_properties_nic_receive_rdma; 2101 struct mlx5_ifc_flow_table_prop_layout_bits 2102 flow_table_properties_nic_receive_sniffer; 2103 struct mlx5_ifc_flow_table_prop_layout_bits 2104 flow_table_properties_nic_transmit; 2105 struct mlx5_ifc_flow_table_prop_layout_bits 2106 flow_table_properties_nic_transmit_rdma; 2107 struct mlx5_ifc_flow_table_prop_layout_bits 2108 flow_table_properties_nic_transmit_sniffer; 2109 u8 reserved_at_e00[0x200]; 2110 struct mlx5_ifc_ft_fields_support_bits 2111 ft_header_modify_nic_receive; 2112 struct mlx5_ifc_ft_fields_support_2_bits 2113 ft_field_support_2_nic_receive; 2114 u8 reserved_at_1480[0x780]; 2115 struct mlx5_ifc_ft_fields_support_bits 2116 ft_header_modify_nic_transmit; 2117 u8 reserved_at_2000[0x6000]; 2118 }; 2119 2120 struct mlx5_ifc_flow_table_esw_cap_bits { 2121 u8 reserved_at_0[0x800]; 2122 struct mlx5_ifc_ft_fields_support_bits ft_header_modify_esw_fdb; 2123 u8 reserved_at_C00[0x7400]; 2124 }; 2125 2126 enum mlx5_ifc_cross_vhca_object_to_object_supported_types { 2127 MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_TIR = 1 << 10, 2128 MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_STC_TO_FT = 1 << 11, 2129 MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_FT = 1 << 12, 2130 MLX5_CROSS_VHCA_OBJ_TO_OBJ_TYPE_FT_TO_RTC = 1 << 13, 2131 }; 2132 2133 enum mlx5_ifc_cross_vhca_allowed_objects_types { 2134 MLX5_CROSS_VHCA_ALLOWED_OBJS_TIR = 1 << 0x8, 2135 MLX5_CROSS_VHCA_ALLOWED_OBJS_FT = 1 << 0x9, 2136 MLX5_CROSS_VHCA_ALLOWED_OBJS_RTC = 1 << 0xa, 2137 }; 2138 2139 enum { 2140 MLX5_GENERATE_WQE_TYPE_FLOW_UPDATE = 1 << 1, 2141 }; 2142 2143 /* 2144 * HCA Capabilities 2 2145 */ 2146 struct mlx5_ifc_cmd_hca_cap_2_bits { 2147 u8 reserved_at_0[0x80]; /* End of DW4. */ 2148 u8 reserved_at_80[0x3]; 2149 u8 max_num_prog_sample_field[0x5]; 2150 u8 reserved_at_88[0x3]; 2151 u8 log_max_num_reserved_qpn[0x5]; 2152 u8 reserved_at_90[0x3]; 2153 u8 log_reserved_qpn_granularity[0x5]; 2154 u8 reserved_at_98[0x3]; 2155 u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */ 2156 u8 max_reformat_insert_size[0x8]; 2157 u8 max_reformat_insert_offset[0x8]; 2158 u8 max_reformat_remove_size[0x8]; 2159 u8 max_reformat_remove_offset[0x8]; /* End of DW6. */ 2160 u8 reserved_at_c0[0x3]; 2161 u8 log_min_stride_wqe_sz[0x5]; 2162 u8 reserved_at_c8[0x3]; 2163 u8 log_conn_track_granularity[0x5]; 2164 u8 reserved_at_d0[0x3]; 2165 u8 log_conn_track_max_alloc[0x5]; 2166 u8 reserved_at_d8[0x3]; 2167 u8 log_max_conn_track_offload[0x5]; 2168 u8 cross_vhca_object_to_object_supported[0x20]; /* End of DW7. */ 2169 u8 allowed_object_for_other_vhca_access_high[0x20]; 2170 u8 allowed_object_for_other_vhca_access[0x20]; 2171 u8 reserved_at_140[0x20]; 2172 u8 reserved_at_160[0x3]; 2173 u8 hairpin_sq_wqe_bb_size[0x5]; 2174 u8 hairpin_sq_wq_in_host_mem[0x1]; 2175 u8 hairpin_data_buffer_locked[0x1]; 2176 u8 reserved_at_16a[0x16]; 2177 u8 reserved_at_180[0x20]; 2178 u8 reserved_at_1a0[0xa]; 2179 u8 format_select_dw_8_6_ext[0x1]; 2180 u8 reserved_at_1ac[0x15]; 2181 u8 general_obj_types_127_64[0x40]; 2182 u8 reserved_at_200[0x53]; 2183 u8 flow_counter_bulk_log_max_alloc[0x5]; 2184 u8 reserved_at_258[0x3]; 2185 u8 flow_counter_bulk_log_granularity[0x5]; 2186 u8 reserved_at_260[0x20]; 2187 u8 format_select_dw_gtpu_dw_0[0x8]; 2188 u8 format_select_dw_gtpu_dw_1[0x8]; 2189 u8 format_select_dw_gtpu_dw_2[0x8]; 2190 u8 format_select_dw_gtpu_first_ext_dw_0[0x8]; 2191 u8 generate_wqe_type[0x20]; 2192 u8 reserved_at_2c0[0x540]; 2193 }; 2194 2195 struct mlx5_ifc_esw_cap_bits { 2196 u8 reserved_at_0[0x60]; 2197 2198 u8 esw_manager_vport_number_valid[0x1]; 2199 u8 reserved_at_61[0xf]; 2200 u8 esw_manager_vport_number[0x10]; 2201 2202 u8 reserved_at_80[0x780]; 2203 }; 2204 2205 struct mlx5_ifc_wqe_based_flow_table_cap_bits { 2206 u8 reserved_at_0[0x3]; 2207 u8 log_max_num_ste[0x5]; 2208 u8 reserved_at_8[0x3]; 2209 u8 log_max_num_stc[0x5]; 2210 u8 reserved_at_10[0x3]; 2211 u8 log_max_num_rtc[0x5]; 2212 u8 reserved_at_18[0x3]; 2213 u8 log_max_num_header_modify_pattern[0x5]; 2214 u8 rtc_hash_split_table[0x1]; 2215 u8 rtc_linear_lookup_table[0x1]; 2216 u8 reserved_at_22[0x1]; 2217 u8 stc_alloc_log_granularity[0x5]; 2218 u8 reserved_at_28[0x3]; 2219 u8 stc_alloc_log_max[0x5]; 2220 u8 reserved_at_30[0x3]; 2221 u8 ste_alloc_log_granularity[0x5]; 2222 u8 reserved_at_38[0x3]; 2223 u8 ste_alloc_log_max[0x5]; 2224 u8 reserved_at_40[0xb]; 2225 u8 rtc_reparse_mode[0x5]; 2226 u8 reserved_at_50[0x3]; 2227 u8 rtc_index_mode[0x5]; 2228 u8 reserved_at_58[0x3]; 2229 u8 rtc_log_depth_max[0x5]; 2230 u8 reserved_at_60[0x10]; 2231 u8 ste_format[0x10]; 2232 u8 stc_action_type[0x80]; 2233 u8 header_insert_type[0x10]; 2234 u8 header_remove_type[0x10]; 2235 u8 trivial_match_definer[0x20]; 2236 u8 reserved_at_140[0x1b]; 2237 u8 rtc_max_num_hash_definer_gen_wqe[0x5]; 2238 u8 reserved_at_160[0x18]; 2239 u8 access_index_mode[0x8]; 2240 u8 reserved_at_180[0x10]; 2241 u8 ste_format_gen_wqe[0x10]; 2242 u8 linear_match_definer_reg_c3[0x20]; 2243 }; 2244 2245 union mlx5_ifc_hca_cap_union_bits { 2246 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2247 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 2248 struct mlx5_ifc_per_protocol_networking_offload_caps_bits 2249 per_protocol_networking_offload_caps; 2250 struct mlx5_ifc_qos_cap_bits qos_cap; 2251 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps; 2252 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2253 struct mlx5_ifc_flow_table_esw_cap_bits flow_table_esw_cap; 2254 struct mlx5_ifc_esw_cap_bits esw_cap; 2255 struct mlx5_ifc_roce_caps_bits roce_caps; 2256 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap; 2257 u8 reserved_at_0[0x8000]; 2258 }; 2259 2260 struct mlx5_ifc_set_action_in_bits { 2261 u8 action_type[0x4]; 2262 u8 field[0xc]; 2263 u8 reserved_at_10[0x3]; 2264 u8 offset[0x5]; 2265 u8 reserved_at_18[0x3]; 2266 u8 length[0x5]; 2267 u8 data[0x20]; 2268 }; 2269 2270 struct mlx5_ifc_copy_action_in_bits { 2271 u8 action_type[0x4]; 2272 u8 src_field[0xc]; 2273 u8 reserved_at_10[0x3]; 2274 u8 src_offset[0x5]; 2275 u8 reserved_at_18[0x3]; 2276 u8 length[0x5]; 2277 u8 reserved_at_20[0x4]; 2278 u8 dst_field[0xc]; 2279 u8 reserved_at_30[0x3]; 2280 u8 dst_offset[0x5]; 2281 u8 reserved_at_38[0x8]; 2282 }; 2283 2284 struct mlx5_ifc_query_hca_cap_out_bits { 2285 u8 status[0x8]; 2286 u8 reserved_at_8[0x18]; 2287 u8 syndrome[0x20]; 2288 u8 reserved_at_40[0x40]; 2289 union mlx5_ifc_hca_cap_union_bits capability; 2290 }; 2291 2292 struct mlx5_ifc_query_hca_cap_in_bits { 2293 u8 opcode[0x10]; 2294 u8 reserved_at_10[0x10]; 2295 u8 reserved_at_20[0x10]; 2296 u8 op_mod[0x10]; 2297 u8 reserved_at_40[0x40]; 2298 }; 2299 2300 struct mlx5_ifc_mac_address_layout_bits { 2301 u8 reserved_at_0[0x10]; 2302 u8 mac_addr_47_32[0x10]; 2303 u8 mac_addr_31_0[0x20]; 2304 }; 2305 2306 struct mlx5_ifc_nic_vport_context_bits { 2307 u8 reserved_at_0[0x5]; 2308 u8 min_wqe_inline_mode[0x3]; 2309 u8 reserved_at_8[0x15]; 2310 u8 disable_mc_local_lb[0x1]; 2311 u8 disable_uc_local_lb[0x1]; 2312 u8 roce_en[0x1]; 2313 u8 arm_change_event[0x1]; 2314 u8 reserved_at_21[0x1a]; 2315 u8 event_on_mtu[0x1]; 2316 u8 event_on_promisc_change[0x1]; 2317 u8 event_on_vlan_change[0x1]; 2318 u8 event_on_mc_address_change[0x1]; 2319 u8 event_on_uc_address_change[0x1]; 2320 u8 reserved_at_40[0xc]; 2321 u8 affiliation_criteria[0x4]; 2322 u8 affiliated_vhca_id[0x10]; 2323 u8 reserved_at_60[0xd0]; 2324 u8 mtu[0x10]; 2325 u8 system_image_guid[0x40]; 2326 u8 port_guid[0x40]; 2327 u8 node_guid[0x40]; 2328 u8 reserved_at_200[0x140]; 2329 u8 qkey_violation_counter[0x10]; 2330 u8 reserved_at_350[0x430]; 2331 u8 promisc_uc[0x1]; 2332 u8 promisc_mc[0x1]; 2333 u8 promisc_all[0x1]; 2334 u8 reserved_at_783[0x2]; 2335 u8 allowed_list_type[0x3]; 2336 u8 reserved_at_788[0xc]; 2337 u8 allowed_list_size[0xc]; 2338 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2339 u8 reserved_at_7e0[0x20]; 2340 }; 2341 2342 struct mlx5_ifc_query_nic_vport_context_out_bits { 2343 u8 status[0x8]; 2344 u8 reserved_at_8[0x18]; 2345 u8 syndrome[0x20]; 2346 u8 reserved_at_40[0x40]; 2347 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 2348 }; 2349 2350 struct mlx5_ifc_query_nic_vport_context_in_bits { 2351 u8 opcode[0x10]; 2352 u8 reserved_at_10[0x10]; 2353 u8 reserved_at_20[0x10]; 2354 u8 op_mod[0x10]; 2355 u8 other_vport[0x1]; 2356 u8 reserved_at_41[0xf]; 2357 u8 vport_number[0x10]; 2358 u8 reserved_at_60[0x5]; 2359 u8 allowed_list_type[0x3]; 2360 u8 reserved_at_68[0x18]; 2361 }; 2362 2363 /* 2364 * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa. 2365 * Each TIS binds to one PF by setting lag_tx_port_affinity (>0). 2366 * Once LAG enabled, we create multiple TISs and bind each one to 2367 * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1. 2368 */ 2369 #define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \ 2370 (index) % (num) + 1 : 0) 2371 struct mlx5_ifc_tisc_bits { 2372 u8 strict_lag_tx_port_affinity[0x1]; 2373 u8 reserved_at_1[0x3]; 2374 u8 lag_tx_port_affinity[0x04]; 2375 u8 reserved_at_8[0x4]; 2376 u8 prio[0x4]; 2377 u8 reserved_at_10[0x10]; 2378 u8 reserved_at_20[0x100]; 2379 u8 reserved_at_120[0x8]; 2380 u8 transport_domain[0x18]; 2381 u8 reserved_at_140[0x8]; 2382 u8 underlay_qpn[0x18]; 2383 u8 reserved_at_160[0x3a0]; 2384 }; 2385 2386 struct mlx5_ifc_query_tis_out_bits { 2387 u8 status[0x8]; 2388 u8 reserved_at_8[0x18]; 2389 u8 syndrome[0x20]; 2390 u8 reserved_at_40[0x40]; 2391 struct mlx5_ifc_tisc_bits tis_context; 2392 }; 2393 2394 struct mlx5_ifc_query_tis_in_bits { 2395 u8 opcode[0x10]; 2396 u8 reserved_at_10[0x10]; 2397 u8 reserved_at_20[0x10]; 2398 u8 op_mod[0x10]; 2399 u8 reserved_at_40[0x8]; 2400 u8 tisn[0x18]; 2401 u8 reserved_at_60[0x20]; 2402 }; 2403 2404 /* port_select_mode definition. */ 2405 enum mlx5_lag_mode_type { 2406 MLX5_LAG_MODE_TIS = 0, 2407 MLX5_LAG_MODE_HASH = 1, 2408 }; 2409 2410 struct mlx5_ifc_lag_context_bits { 2411 u8 fdb_selection_mode[0x1]; 2412 u8 reserved_at_1[0x14]; 2413 u8 port_select_mode[0x3]; 2414 u8 reserved_at_18[0x5]; 2415 u8 lag_state[0x3]; 2416 u8 reserved_at_20[0x14]; 2417 u8 tx_remap_affinity_2[0x4]; 2418 u8 reserved_at_38[0x4]; 2419 u8 tx_remap_affinity_1[0x4]; 2420 }; 2421 2422 struct mlx5_ifc_query_lag_in_bits { 2423 u8 opcode[0x10]; 2424 u8 uid[0x10]; 2425 u8 reserved_at_20[0x10]; 2426 u8 op_mod[0x10]; 2427 u8 reserved_at_40[0x40]; 2428 }; 2429 2430 struct mlx5_ifc_query_lag_out_bits { 2431 u8 status[0x8]; 2432 u8 reserved_at_8[0x18]; 2433 u8 syndrome[0x20]; 2434 struct mlx5_ifc_lag_context_bits context; 2435 }; 2436 2437 struct mlx5_ifc_alloc_transport_domain_out_bits { 2438 u8 status[0x8]; 2439 u8 reserved_at_8[0x18]; 2440 u8 syndrome[0x20]; 2441 u8 reserved_at_40[0x8]; 2442 u8 transport_domain[0x18]; 2443 u8 reserved_at_60[0x20]; 2444 }; 2445 2446 struct mlx5_ifc_alloc_transport_domain_in_bits { 2447 u8 opcode[0x10]; 2448 u8 reserved_at_10[0x10]; 2449 u8 reserved_at_20[0x10]; 2450 u8 op_mod[0x10]; 2451 u8 reserved_at_40[0x40]; 2452 }; 2453 2454 enum { 2455 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 2456 MLX5_WQ_TYPE_CYCLIC = 0x1, 2457 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 2458 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 2459 }; 2460 2461 enum { 2462 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 2463 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 2464 }; 2465 2466 struct mlx5_ifc_wq_bits { 2467 u8 wq_type[0x4]; 2468 u8 wq_signature[0x1]; 2469 u8 end_padding_mode[0x2]; 2470 u8 cd_slave[0x1]; 2471 u8 reserved_at_8[0x18]; 2472 u8 hds_skip_first_sge[0x1]; 2473 u8 log2_hds_buf_size[0x3]; 2474 u8 reserved_at_24[0x7]; 2475 u8 page_offset[0x5]; 2476 u8 lwm[0x10]; 2477 u8 reserved_at_40[0x8]; 2478 u8 pd[0x18]; 2479 u8 reserved_at_60[0x8]; 2480 u8 uar_page[0x18]; 2481 u8 dbr_addr[0x40]; 2482 u8 hw_counter[0x20]; 2483 u8 sw_counter[0x20]; 2484 u8 reserved_at_100[0xc]; 2485 u8 log_wq_stride[0x4]; 2486 u8 reserved_at_110[0x3]; 2487 u8 log_wq_pg_sz[0x5]; 2488 u8 reserved_at_118[0x3]; 2489 u8 log_wq_sz[0x5]; 2490 u8 dbr_umem_valid[0x1]; 2491 u8 wq_umem_valid[0x1]; 2492 u8 reserved_at_122[0x1]; 2493 u8 log_hairpin_num_packets[0x5]; 2494 u8 reserved_at_128[0x3]; 2495 u8 log_hairpin_data_sz[0x5]; 2496 u8 reserved_at_130[0x4]; 2497 u8 single_wqe_log_num_of_strides[0x4]; 2498 u8 two_byte_shift_en[0x1]; 2499 u8 reserved_at_139[0x4]; 2500 u8 single_stride_log_num_of_bytes[0x3]; 2501 u8 dbr_umem_id[0x20]; 2502 u8 wq_umem_id[0x20]; 2503 u8 wq_umem_offset[0x40]; 2504 u8 reserved_at_1c0[0x440]; 2505 }; 2506 2507 enum { 2508 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2509 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2510 }; 2511 2512 enum { 2513 MLX5_RQC_STATE_RST = 0x0, 2514 MLX5_RQC_STATE_RDY = 0x1, 2515 MLX5_RQC_STATE_ERR = 0x3, 2516 }; 2517 2518 struct mlx5_ifc_rqc_bits { 2519 u8 rlky[0x1]; 2520 u8 delay_drop_en[0x1]; 2521 u8 scatter_fcs[0x1]; 2522 u8 vsd[0x1]; 2523 u8 mem_rq_type[0x4]; 2524 u8 state[0x4]; 2525 u8 reserved_at_c[0x1]; 2526 u8 flush_in_error_en[0x1]; 2527 u8 hairpin[0x1]; 2528 u8 reserved_at_f[0x6]; 2529 u8 hairpin_data_buffer_type[0x3]; 2530 u8 reserved_at_a8[0x2]; 2531 u8 ts_format[0x02]; 2532 u8 reserved_at_1c[0x4]; 2533 u8 reserved_at_20[0x8]; 2534 u8 user_index[0x18]; 2535 u8 reserved_at_40[0x8]; 2536 u8 cqn[0x18]; 2537 u8 counter_set_id[0x8]; 2538 u8 reserved_at_68[0x18]; 2539 u8 reserved_at_80[0x8]; 2540 u8 rmpn[0x18]; 2541 u8 reserved_at_a0[0x8]; 2542 u8 hairpin_peer_sq[0x18]; 2543 u8 reserved_at_c0[0x10]; 2544 u8 hairpin_peer_vhca[0x10]; 2545 u8 reserved_at_e0[0xa0]; 2546 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */ 2547 }; 2548 2549 struct mlx5_ifc_create_rq_out_bits { 2550 u8 status[0x8]; 2551 u8 reserved_at_8[0x18]; 2552 u8 syndrome[0x20]; 2553 u8 reserved_at_40[0x8]; 2554 u8 rqn[0x18]; 2555 u8 reserved_at_60[0x20]; 2556 }; 2557 2558 struct mlx5_ifc_create_rq_in_bits { 2559 u8 opcode[0x10]; 2560 u8 uid[0x10]; 2561 u8 reserved_at_20[0x10]; 2562 u8 op_mod[0x10]; 2563 u8 reserved_at_40[0xc0]; 2564 struct mlx5_ifc_rqc_bits ctx; 2565 }; 2566 2567 struct mlx5_ifc_modify_rq_out_bits { 2568 u8 status[0x8]; 2569 u8 reserved_at_8[0x18]; 2570 u8 syndrome[0x20]; 2571 u8 reserved_at_40[0x40]; 2572 }; 2573 2574 struct mlx5_ifc_query_rq_out_bits { 2575 u8 status[0x8]; 2576 u8 reserved_at_8[0x18]; 2577 u8 syndrome[0x20]; 2578 u8 reserved_at_40[0xc0]; 2579 struct mlx5_ifc_rqc_bits rq_context; 2580 }; 2581 2582 struct mlx5_ifc_query_rq_in_bits { 2583 u8 opcode[0x10]; 2584 u8 reserved_at_10[0x10]; 2585 u8 reserved_at_20[0x10]; 2586 u8 op_mod[0x10]; 2587 u8 reserved_at_40[0x8]; 2588 u8 rqn[0x18]; 2589 u8 reserved_at_60[0x20]; 2590 }; 2591 2592 enum { 2593 MLX5_RMPC_STATE_RDY = 0x1, 2594 MLX5_RMPC_STATE_ERR = 0x3, 2595 }; 2596 2597 struct mlx5_ifc_rmpc_bits { 2598 u8 reserved_at_0[0x8]; 2599 u8 state[0x4]; 2600 u8 reserved_at_c[0x14]; 2601 u8 basic_cyclic_rcv_wqe[0x1]; 2602 u8 reserved_at_21[0x1f]; 2603 u8 reserved_at_40[0x140]; 2604 struct mlx5_ifc_wq_bits wq; 2605 }; 2606 2607 struct mlx5_ifc_query_rmp_out_bits { 2608 u8 status[0x8]; 2609 u8 reserved_at_8[0x18]; 2610 u8 syndrome[0x20]; 2611 u8 reserved_at_40[0xc0]; 2612 struct mlx5_ifc_rmpc_bits rmp_context; 2613 }; 2614 2615 struct mlx5_ifc_query_rmp_in_bits { 2616 u8 opcode[0x10]; 2617 u8 reserved_at_10[0x10]; 2618 u8 reserved_at_20[0x10]; 2619 u8 op_mod[0x10]; 2620 u8 reserved_at_40[0x8]; 2621 u8 rmpn[0x18]; 2622 u8 reserved_at_60[0x20]; 2623 }; 2624 2625 struct mlx5_ifc_modify_rmp_out_bits { 2626 u8 status[0x8]; 2627 u8 reserved_at_8[0x18]; 2628 u8 syndrome[0x20]; 2629 u8 reserved_at_40[0x40]; 2630 }; 2631 2632 struct mlx5_ifc_rmp_bitmask_bits { 2633 u8 reserved_at_0[0x20]; 2634 u8 reserved_at_20[0x1f]; 2635 u8 lwm[0x1]; 2636 }; 2637 2638 struct mlx5_ifc_modify_rmp_in_bits { 2639 u8 opcode[0x10]; 2640 u8 uid[0x10]; 2641 u8 reserved_at_20[0x10]; 2642 u8 op_mod[0x10]; 2643 u8 rmp_state[0x4]; 2644 u8 reserved_at_44[0x4]; 2645 u8 rmpn[0x18]; 2646 u8 reserved_at_60[0x20]; 2647 struct mlx5_ifc_rmp_bitmask_bits bitmask; 2648 u8 reserved_at_c0[0x40]; 2649 struct mlx5_ifc_rmpc_bits ctx; 2650 }; 2651 2652 struct mlx5_ifc_create_rmp_out_bits { 2653 u8 status[0x8]; 2654 u8 reserved_at_8[0x18]; 2655 u8 syndrome[0x20]; 2656 u8 reserved_at_40[0x8]; 2657 u8 rmpn[0x18]; 2658 u8 reserved_at_60[0x20]; 2659 }; 2660 2661 struct mlx5_ifc_create_rmp_in_bits { 2662 u8 opcode[0x10]; 2663 u8 uid[0x10]; 2664 u8 reserved_at_20[0x10]; 2665 u8 op_mod[0x10]; 2666 u8 reserved_at_40[0xc0]; 2667 struct mlx5_ifc_rmpc_bits ctx; 2668 }; 2669 2670 struct mlx5_ifc_create_tis_out_bits { 2671 u8 status[0x8]; 2672 u8 reserved_at_8[0x18]; 2673 u8 syndrome[0x20]; 2674 u8 reserved_at_40[0x8]; 2675 u8 tisn[0x18]; 2676 u8 reserved_at_60[0x20]; 2677 }; 2678 2679 struct mlx5_ifc_create_tis_in_bits { 2680 u8 opcode[0x10]; 2681 u8 uid[0x10]; 2682 u8 reserved_at_20[0x10]; 2683 u8 op_mod[0x10]; 2684 u8 reserved_at_40[0xc0]; 2685 struct mlx5_ifc_tisc_bits ctx; 2686 }; 2687 2688 enum { 2689 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0, 2690 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 2691 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 2692 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 2693 }; 2694 2695 struct mlx5_ifc_modify_rq_in_bits { 2696 u8 opcode[0x10]; 2697 u8 uid[0x10]; 2698 u8 reserved_at_20[0x10]; 2699 u8 op_mod[0x10]; 2700 u8 rq_state[0x4]; 2701 u8 reserved_at_44[0x4]; 2702 u8 rqn[0x18]; 2703 u8 reserved_at_60[0x20]; 2704 u8 modify_bitmask[0x40]; 2705 u8 reserved_at_c0[0x40]; 2706 struct mlx5_ifc_rqc_bits ctx; 2707 }; 2708 2709 enum { 2710 MLX5_L3_PROT_TYPE_IPV4 = 0, 2711 MLX5_L3_PROT_TYPE_IPV6 = 1, 2712 }; 2713 2714 enum { 2715 MLX5_L4_PROT_TYPE_TCP = 0, 2716 MLX5_L4_PROT_TYPE_UDP = 1, 2717 }; 2718 2719 enum { 2720 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2721 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2722 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2723 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2724 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2725 }; 2726 2727 struct mlx5_ifc_rx_hash_field_select_bits { 2728 u8 l3_prot_type[0x1]; 2729 u8 l4_prot_type[0x1]; 2730 u8 selected_fields[0x1e]; 2731 }; 2732 2733 enum { 2734 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2735 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2736 }; 2737 2738 enum { 2739 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2740 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2741 }; 2742 2743 enum { 2744 MLX5_RX_HASH_FN_NONE = 0x0, 2745 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2746 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2747 }; 2748 2749 enum { 2750 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2751 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2752 }; 2753 2754 enum { 2755 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0, 2756 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1, 2757 }; 2758 2759 struct mlx5_ifc_tirc_bits { 2760 u8 reserved_at_0[0x20]; 2761 u8 disp_type[0x4]; 2762 u8 reserved_at_24[0x1c]; 2763 u8 reserved_at_40[0x40]; 2764 u8 reserved_at_80[0x4]; 2765 u8 lro_timeout_period_usecs[0x10]; 2766 u8 lro_enable_mask[0x4]; 2767 u8 lro_max_msg_sz[0x8]; 2768 u8 reserved_at_a0[0x40]; 2769 u8 reserved_at_e0[0x8]; 2770 u8 inline_rqn[0x18]; 2771 u8 rx_hash_symmetric[0x1]; 2772 u8 reserved_at_101[0x1]; 2773 u8 tunneled_offload_en[0x1]; 2774 u8 reserved_at_103[0x5]; 2775 u8 indirect_table[0x18]; 2776 u8 rx_hash_fn[0x4]; 2777 u8 reserved_at_124[0x2]; 2778 u8 self_lb_block[0x2]; 2779 u8 transport_domain[0x18]; 2780 u8 rx_hash_toeplitz_key[10][0x20]; 2781 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2782 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2783 u8 reserved_at_2c0[0x4c0]; 2784 }; 2785 2786 struct mlx5_ifc_create_tir_out_bits { 2787 u8 status[0x8]; 2788 u8 reserved_at_8[0x18]; 2789 u8 syndrome[0x20]; 2790 u8 reserved_at_40[0x8]; 2791 u8 tirn[0x18]; 2792 u8 reserved_at_60[0x20]; 2793 }; 2794 2795 struct mlx5_ifc_create_tir_in_bits { 2796 u8 opcode[0x10]; 2797 u8 uid[0x10]; 2798 u8 reserved_at_20[0x10]; 2799 u8 op_mod[0x10]; 2800 u8 reserved_at_40[0xc0]; 2801 struct mlx5_ifc_tirc_bits ctx; 2802 }; 2803 2804 enum { 2805 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0, 2806 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1, 2807 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2, 2808 /* bit 3 - tunneled_offload_en modify not supported. */ 2809 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4, 2810 }; 2811 2812 struct mlx5_ifc_modify_tir_out_bits { 2813 u8 status[0x8]; 2814 u8 reserved_at_8[0x18]; 2815 u8 syndrome[0x20]; 2816 u8 reserved_at_40[0x40]; 2817 }; 2818 2819 struct mlx5_ifc_modify_tir_in_bits { 2820 u8 opcode[0x10]; 2821 u8 uid[0x10]; 2822 u8 reserved_at_20[0x10]; 2823 u8 op_mod[0x10]; 2824 u8 reserved_at_40[0x8]; 2825 u8 tirn[0x18]; 2826 u8 reserved_at_60[0x20]; 2827 u8 modify_bitmask[0x40]; 2828 u8 reserved_at_c0[0x40]; 2829 struct mlx5_ifc_tirc_bits ctx; 2830 }; 2831 2832 enum { 2833 MLX5_INLINE_Q_TYPE_RQ = 0x0, 2834 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1, 2835 }; 2836 2837 struct mlx5_ifc_rq_num_bits { 2838 u8 reserved_at_0[0x8]; 2839 u8 rq_num[0x18]; 2840 }; 2841 2842 struct mlx5_ifc_rqtc_bits { 2843 u8 reserved_at_0[0xa5]; 2844 u8 list_q_type[0x3]; 2845 u8 reserved_at_a8[0x8]; 2846 u8 rqt_max_size[0x10]; 2847 u8 reserved_at_c0[0x10]; 2848 u8 rqt_actual_size[0x10]; 2849 u8 reserved_at_e0[0x6a0]; 2850 struct mlx5_ifc_rq_num_bits rq_num[]; 2851 }; 2852 2853 struct mlx5_ifc_create_rqt_out_bits { 2854 u8 status[0x8]; 2855 u8 reserved_at_8[0x18]; 2856 u8 syndrome[0x20]; 2857 u8 reserved_at_40[0x8]; 2858 u8 rqtn[0x18]; 2859 u8 reserved_at_60[0x20]; 2860 }; 2861 2862 #ifdef PEDANTIC 2863 #pragma GCC diagnostic ignored "-Wpedantic" 2864 #endif 2865 struct mlx5_ifc_create_rqt_in_bits { 2866 u8 opcode[0x10]; 2867 u8 uid[0x10]; 2868 u8 reserved_at_20[0x10]; 2869 u8 op_mod[0x10]; 2870 u8 reserved_at_40[0xc0]; 2871 struct mlx5_ifc_rqtc_bits rqt_context; 2872 }; 2873 2874 struct mlx5_ifc_modify_rqt_in_bits { 2875 u8 opcode[0x10]; 2876 u8 uid[0x10]; 2877 u8 reserved_at_20[0x10]; 2878 u8 op_mod[0x10]; 2879 u8 reserved_at_40[0x8]; 2880 u8 rqtn[0x18]; 2881 u8 reserved_at_60[0x20]; 2882 u8 modify_bitmask[0x40]; 2883 u8 reserved_at_c0[0x40]; 2884 struct mlx5_ifc_rqtc_bits rqt_context; 2885 }; 2886 #ifdef PEDANTIC 2887 #pragma GCC diagnostic error "-Wpedantic" 2888 #endif 2889 2890 struct mlx5_ifc_modify_rqt_out_bits { 2891 u8 status[0x8]; 2892 u8 reserved_at_8[0x18]; 2893 u8 syndrome[0x20]; 2894 u8 reserved_at_40[0x40]; 2895 }; 2896 2897 enum { 2898 MLX5_SQC_STATE_RST = 0x0, 2899 MLX5_SQC_STATE_RDY = 0x1, 2900 MLX5_SQC_STATE_ERR = 0x3, 2901 }; 2902 2903 enum { 2904 MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER = 0x0, 2905 MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY = 0x1, 2906 }; 2907 2908 struct mlx5_ifc_sqc_bits { 2909 u8 rlky[0x1]; 2910 u8 cd_master[0x1]; 2911 u8 fre[0x1]; 2912 u8 flush_in_error_en[0x1]; 2913 u8 allow_multi_pkt_send_wqe[0x1]; 2914 u8 min_wqe_inline_mode[0x3]; 2915 u8 state[0x4]; 2916 u8 reg_umr[0x1]; 2917 u8 allow_swp[0x1]; 2918 u8 hairpin[0x1]; 2919 u8 non_wire[0x1]; 2920 u8 static_sq_wq[0x1]; 2921 u8 reserved_at_11[0x4]; 2922 u8 hairpin_wq_buffer_type[0x3]; 2923 u8 reserved_at_18[0x2]; 2924 u8 ts_format[0x02]; 2925 u8 reserved_at_1c[0x4]; 2926 u8 reserved_at_20[0x8]; 2927 u8 user_index[0x18]; 2928 u8 reserved_at_40[0x8]; 2929 u8 cqn[0x18]; 2930 u8 reserved_at_60[0x8]; 2931 u8 hairpin_peer_rq[0x18]; 2932 u8 reserved_at_80[0x10]; 2933 u8 hairpin_peer_vhca[0x10]; 2934 u8 reserved_at_a0[0x50]; 2935 u8 packet_pacing_rate_limit_index[0x10]; 2936 u8 tis_lst_sz[0x10]; 2937 u8 reserved_at_110[0x10]; 2938 u8 reserved_at_120[0x40]; 2939 u8 reserved_at_160[0x8]; 2940 u8 tis_num_0[0x18]; 2941 struct mlx5_ifc_wq_bits wq; 2942 }; 2943 2944 struct mlx5_ifc_query_sq_in_bits { 2945 u8 opcode[0x10]; 2946 u8 reserved_at_10[0x10]; 2947 u8 reserved_at_20[0x10]; 2948 u8 op_mod[0x10]; 2949 u8 reserved_at_40[0x8]; 2950 u8 sqn[0x18]; 2951 u8 reserved_at_60[0x20]; 2952 }; 2953 2954 struct mlx5_ifc_modify_sq_out_bits { 2955 u8 status[0x8]; 2956 u8 reserved_at_8[0x18]; 2957 u8 syndrome[0x20]; 2958 u8 reserved_at_40[0x40]; 2959 }; 2960 2961 struct mlx5_ifc_modify_sq_in_bits { 2962 u8 opcode[0x10]; 2963 u8 uid[0x10]; 2964 u8 reserved_at_20[0x10]; 2965 u8 op_mod[0x10]; 2966 u8 sq_state[0x4]; 2967 u8 reserved_at_44[0x4]; 2968 u8 sqn[0x18]; 2969 u8 reserved_at_60[0x20]; 2970 u8 modify_bitmask[0x40]; 2971 u8 reserved_at_c0[0x40]; 2972 struct mlx5_ifc_sqc_bits ctx; 2973 }; 2974 2975 struct mlx5_ifc_create_sq_out_bits { 2976 u8 status[0x8]; 2977 u8 reserved_at_8[0x18]; 2978 u8 syndrome[0x20]; 2979 u8 reserved_at_40[0x8]; 2980 u8 sqn[0x18]; 2981 u8 reserved_at_60[0x20]; 2982 }; 2983 2984 struct mlx5_ifc_create_sq_in_bits { 2985 u8 opcode[0x10]; 2986 u8 uid[0x10]; 2987 u8 reserved_at_20[0x10]; 2988 u8 op_mod[0x10]; 2989 u8 reserved_at_40[0xc0]; 2990 struct mlx5_ifc_sqc_bits ctx; 2991 }; 2992 2993 enum { 2994 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0), 2995 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1), 2996 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2), 2997 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3), 2998 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4), 2999 }; 3000 3001 struct mlx5_ifc_flow_meter_parameters_bits { 3002 u8 valid[0x1]; 3003 u8 bucket_overflow[0x1]; 3004 u8 start_color[0x2]; 3005 u8 both_buckets_on_green[0x1]; 3006 u8 meter_mode[0x2]; 3007 u8 reserved_at_1[0x19]; 3008 u8 reserved_at_2[0x20]; 3009 u8 reserved_at_3[0x3]; 3010 u8 cbs_exponent[0x5]; 3011 u8 cbs_mantissa[0x8]; 3012 u8 reserved_at_4[0x3]; 3013 u8 cir_exponent[0x5]; 3014 u8 cir_mantissa[0x8]; 3015 u8 reserved_at_5[0x20]; 3016 u8 reserved_at_6[0x3]; 3017 u8 ebs_exponent[0x5]; 3018 u8 ebs_mantissa[0x8]; 3019 u8 reserved_at_7[0x3]; 3020 u8 eir_exponent[0x5]; 3021 u8 eir_mantissa[0x8]; 3022 u8 reserved_at_8[0x60]; 3023 }; 3024 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF) 3025 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8 3026 3027 enum { 3028 MLX5_METER_MODE_IP_LEN = 0x0, 3029 MLX5_METER_MODE_L2_LEN = 0x1, 3030 MLX5_METER_MODE_L2_IPG_LEN = 0x2, 3031 MLX5_METER_MODE_PKT = 0x3, 3032 }; 3033 3034 enum { 3035 MLX5_CQE_SIZE_64B = 0x0, 3036 MLX5_CQE_SIZE_128B = 0x1, 3037 }; 3038 3039 enum { 3040 MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER = 0x0, 3041 MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER = 0x1, 3042 }; 3043 3044 struct mlx5_ifc_cqc_bits { 3045 u8 status[0x4]; 3046 u8 as_notify[0x1]; 3047 u8 initiator_src_dct[0x1]; 3048 u8 dbr_umem_valid[0x1]; 3049 u8 reserved_at_7[0x1]; 3050 u8 cqe_sz[0x3]; 3051 u8 cc[0x1]; 3052 u8 reserved_at_c[0x1]; 3053 u8 scqe_break_moderation_en[0x1]; 3054 u8 oi[0x1]; 3055 u8 cq_period_mode[0x2]; 3056 u8 cqe_comp_en[0x1]; 3057 u8 mini_cqe_res_format[0x2]; 3058 u8 st[0x4]; 3059 u8 reserved_at_18[0x1]; 3060 u8 cqe_comp_layout[0x7]; 3061 u8 dbr_umem_id[0x20]; 3062 u8 reserved_at_40[0x14]; 3063 u8 page_offset[0x6]; 3064 u8 reserved_at_5a[0x2]; 3065 u8 mini_cqe_res_format_ext[0x2]; 3066 u8 cq_timestamp_format[0x2]; 3067 u8 reserved_at_60[0x3]; 3068 u8 log_cq_size[0x5]; 3069 u8 uar_page[0x18]; 3070 u8 reserved_at_80[0x4]; 3071 u8 cq_period[0xc]; 3072 u8 cq_max_count[0x10]; 3073 u8 reserved_at_a0[0x18]; 3074 u8 c_eqn[0x8]; 3075 u8 reserved_at_c0[0x3]; 3076 u8 log_page_size[0x5]; 3077 u8 reserved_at_c8[0x18]; 3078 u8 reserved_at_e0[0x20]; 3079 u8 reserved_at_100[0x8]; 3080 u8 last_notified_index[0x18]; 3081 u8 reserved_at_120[0x8]; 3082 u8 last_solicit_index[0x18]; 3083 u8 reserved_at_140[0x8]; 3084 u8 consumer_counter[0x18]; 3085 u8 reserved_at_160[0x8]; 3086 u8 producer_counter[0x18]; 3087 u8 local_partition_id[0xc]; 3088 u8 process_id[0x14]; 3089 u8 reserved_at_1A0[0x20]; 3090 u8 dbr_addr[0x40]; 3091 }; 3092 3093 struct mlx5_ifc_health_buffer_bits { 3094 u8 reserved_0[0x100]; 3095 u8 assert_existptr[0x20]; 3096 u8 assert_callra[0x20]; 3097 u8 reserved_1[0x40]; 3098 u8 fw_version[0x20]; 3099 u8 hw_id[0x20]; 3100 u8 reserved_2[0x20]; 3101 u8 irisc_index[0x8]; 3102 u8 synd[0x8]; 3103 u8 ext_synd[0x10]; 3104 }; 3105 3106 /* HCA PCI BAR resource structure. */ 3107 struct mlx5_ifc_initial_seg_bits { 3108 u8 fw_rev_minor[0x10]; 3109 u8 fw_rev_major[0x10]; 3110 u8 cmd_interface_rev[0x10]; 3111 u8 fw_rev_subminor[0x10]; 3112 u8 reserved_0[0x40]; 3113 u8 cmdq_phy_addr_63_32[0x20]; 3114 u8 cmdq_phy_addr_31_12[0x14]; 3115 u8 reserved_1[0x2]; 3116 u8 nic_interface[0x2]; 3117 u8 log_cmdq_size[0x4]; 3118 u8 log_cmdq_stride[0x4]; 3119 u8 command_doorbell_vector[0x20]; 3120 u8 reserved_2[0xf00]; 3121 u8 initializing[0x1]; 3122 u8 nic_interface_supported[0x7]; 3123 u8 reserved_4[0x18]; 3124 struct mlx5_ifc_health_buffer_bits health_buffer; 3125 u8 no_dram_nic_offset[0x20]; 3126 u8 reserved_5[0x6de0]; 3127 u8 internal_timer_h[0x20]; 3128 u8 internal_timer_l[0x20]; 3129 u8 reserved_6[0x20]; 3130 u8 reserved_7[0x1f]; 3131 u8 clear_int[0x1]; 3132 u8 health_syndrome[0x8]; 3133 u8 health_counter[0x18]; 3134 u8 reserved_8[0x160]; 3135 u8 real_time[0x40]; 3136 u8 reserved_9[0x17e20]; 3137 }; 3138 3139 struct mlx5_ifc_create_cq_out_bits { 3140 u8 status[0x8]; 3141 u8 reserved_at_8[0x18]; 3142 u8 syndrome[0x20]; 3143 u8 reserved_at_40[0x8]; 3144 u8 cqn[0x18]; 3145 u8 reserved_at_60[0x20]; 3146 }; 3147 3148 struct mlx5_ifc_create_cq_in_bits { 3149 u8 opcode[0x10]; 3150 u8 uid[0x10]; 3151 u8 reserved_at_20[0x10]; 3152 u8 op_mod[0x10]; 3153 u8 reserved_at_40[0x40]; 3154 struct mlx5_ifc_cqc_bits cq_context; 3155 u8 cq_umem_offset[0x40]; 3156 u8 cq_umem_id[0x20]; 3157 u8 cq_umem_valid[0x1]; 3158 u8 reserved_at_2e1[0x1f]; 3159 u8 reserved_at_300[0x580]; 3160 u8 pas[]; 3161 }; 3162 3163 enum { 3164 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 3165 MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c, 3166 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, 3167 MLX5_GENERAL_OBJ_TYPE_DEFINER = 0x0018, 3168 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 3169 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d, 3170 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e, 3171 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f, 3172 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, 3173 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, 3174 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, 3175 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031, 3176 MLX5_GENERAL_OBJ_TYPE_ARG = 0x0023, 3177 MLX5_GENERAL_OBJ_TYPE_STC = 0x0040, 3178 MLX5_GENERAL_OBJ_TYPE_RTC = 0x0041, 3179 MLX5_GENERAL_OBJ_TYPE_STE = 0x0042, 3180 MLX5_GENERAL_OBJ_TYPE_MODIFY_HEADER_PATTERN = 0x0043, 3181 MLX5_GENERAL_OBJ_TYPE_FT_ALIAS = 0xff15, 3182 MLX5_GENERAL_OBJ_TYPE_TIR_ALIAS = 0xff16, 3183 }; 3184 3185 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 3186 u8 opcode[0x10]; 3187 u8 reserved_at_10[0x20]; 3188 u8 obj_type[0x10]; 3189 u8 obj_id[0x20]; 3190 union { 3191 struct { 3192 u8 alias_object[0x1]; 3193 u8 reserved_at_61[0x2]; 3194 u8 log_obj_range[0x5]; 3195 u8 reserved_at_68[0x18]; 3196 }; 3197 u8 obj_offset[0x20]; 3198 }; 3199 }; 3200 3201 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 3202 u8 status[0x8]; 3203 u8 reserved_at_8[0x18]; 3204 u8 syndrome[0x20]; 3205 u8 obj_id[0x20]; 3206 u8 reserved_at_60[0x20]; 3207 }; 3208 3209 struct mlx5_ifc_allow_other_vhca_access_in_bits { 3210 u8 opcode[0x10]; 3211 u8 uid[0x10]; 3212 u8 reserved_at_20[0x10]; 3213 u8 op_mod[0x10]; 3214 u8 reserved_at_40[0x50]; 3215 u8 object_type_to_be_accessed[0x10]; 3216 u8 object_id_to_be_accessed[0x20]; 3217 u8 reserved_at_c0[0x40]; 3218 union { 3219 u8 access_key_raw[0x100]; 3220 u8 access_key[8][0x20]; 3221 }; 3222 }; 3223 3224 struct mlx5_ifc_allow_other_vhca_access_out_bits { 3225 u8 status[0x8]; 3226 u8 reserved_at_8[0x18]; 3227 u8 syndrome[0x20]; 3228 u8 reserved_at_40[0x40]; 3229 }; 3230 3231 struct mlx5_ifc_virtio_q_counters_bits { 3232 u8 modify_field_select[0x40]; 3233 u8 reserved_at_40[0x40]; 3234 u8 received_desc[0x40]; 3235 u8 completed_desc[0x40]; 3236 u8 error_cqes[0x20]; 3237 u8 bad_desc_errors[0x20]; 3238 u8 exceed_max_chain[0x20]; 3239 u8 invalid_buffer[0x20]; 3240 u8 reserved_at_180[0x50]; 3241 }; 3242 3243 struct mlx5_ifc_geneve_tlv_option_bits { 3244 u8 modify_field_select[0x40]; 3245 u8 reserved_at_40[0x18]; 3246 u8 geneve_option_fte_index[0x8]; 3247 u8 option_class[0x10]; 3248 u8 option_type[0x8]; 3249 u8 reserved_at_78[0x3]; 3250 u8 option_data_length[0x5]; 3251 u8 reserved_at_80[0x180]; 3252 }; 3253 3254 3255 enum mlx5_ifc_rtc_update_mode { 3256 MLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH = 0x0, 3257 MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET = 0x1, 3258 }; 3259 3260 enum mlx5_ifc_rtc_access_mode { 3261 MLX5_IFC_RTC_STE_ACCESS_MODE_BY_HASH = 0x0, 3262 MLX5_IFC_RTC_STE_ACCESS_MODE_LINEAR = 0x1, 3263 }; 3264 3265 enum mlx5_ifc_rtc_ste_format { 3266 MLX5_IFC_RTC_STE_FORMAT_8DW = 0x4, 3267 MLX5_IFC_RTC_STE_FORMAT_11DW = 0x5, 3268 MLX5_IFC_RTC_STE_FORMAT_RANGE = 0x7, 3269 }; 3270 3271 enum mlx5_ifc_rtc_reparse_mode { 3272 MLX5_IFC_RTC_REPARSE_NEVER = 0x0, 3273 MLX5_IFC_RTC_REPARSE_ALWAYS = 0x1, 3274 }; 3275 3276 #define MLX5_IFC_RTC_LINEAR_LOOKUP_TBL_LOG_MAX 16 3277 3278 struct mlx5_ifc_rtc_bits { 3279 u8 modify_field_select[0x40]; 3280 u8 reserved_at_40[0x40]; 3281 u8 update_index_mode[0x2]; 3282 u8 reparse_mode[0x2]; 3283 u8 num_match_ste[0x4]; 3284 u8 pd[0x18]; 3285 u8 reserved_at_a0[0x9]; 3286 u8 access_index_mode[0x3]; 3287 u8 num_hash_definer[0x4]; 3288 u8 update_method[0x1]; 3289 u8 reserved_at_b1[0x2]; 3290 u8 log_depth[0x5]; 3291 u8 log_hash_size[0x8]; 3292 u8 ste_format_0[0x8]; 3293 u8 table_type[0x8]; 3294 u8 ste_format_1[0x8]; 3295 u8 reserved_at_d8[0x8]; 3296 u8 match_definer_0[0x20]; 3297 u8 stc_id[0x20]; 3298 u8 ste_table_base_id[0x20]; 3299 u8 ste_table_offset[0x20]; 3300 u8 reserved_at_160[0x8]; 3301 u8 miss_flow_table_id[0x18]; 3302 u8 match_definer_1[0x20]; 3303 u8 reserved_at_1a0[0x260]; 3304 }; 3305 3306 struct mlx5_ifc_alias_context_bits { 3307 u8 vhca_id_to_be_accessed[0x10]; 3308 u8 reserved_at_10[0xd]; 3309 u8 status[0x3]; 3310 u8 object_id_to_be_accessed[0x20]; 3311 u8 reserved_at_40[0x40]; 3312 union { 3313 u8 access_key_raw[0x100]; 3314 u8 access_key[8][0x20]; 3315 }; 3316 u8 metadata[0x80]; 3317 }; 3318 3319 enum mlx5_ifc_stc_action_type { 3320 MLX5_IFC_STC_ACTION_TYPE_NOP = 0x00, 3321 MLX5_IFC_STC_ACTION_TYPE_COPY = 0x05, 3322 MLX5_IFC_STC_ACTION_TYPE_SET = 0x06, 3323 MLX5_IFC_STC_ACTION_TYPE_ADD = 0x07, 3324 MLX5_IFC_STC_ACTION_TYPE_REMOVE_WORDS = 0x08, 3325 MLX5_IFC_STC_ACTION_TYPE_HEADER_REMOVE = 0x09, 3326 MLX5_IFC_STC_ACTION_TYPE_HEADER_INSERT = 0x0b, 3327 MLX5_IFC_STC_ACTION_TYPE_TAG = 0x0c, 3328 MLX5_IFC_STC_ACTION_TYPE_ACC_MODIFY_LIST = 0x0e, 3329 MLX5_IFC_STC_ACTION_TYPE_ASO = 0x12, 3330 MLX5_IFC_STC_ACTION_TYPE_COUNTER = 0x14, 3331 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_STE_TABLE = 0x80, 3332 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_TIR = 0x81, 3333 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_FT = 0x82, 3334 MLX5_IFC_STC_ACTION_TYPE_DROP = 0x83, 3335 MLX5_IFC_STC_ACTION_TYPE_ALLOW = 0x84, 3336 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT = 0x85, 3337 MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_UPLINK = 0x86, 3338 }; 3339 3340 struct mlx5_ifc_stc_ste_param_ste_table_bits { 3341 u8 ste_obj_id[0x20]; 3342 u8 match_definer_id[0x20]; 3343 u8 reserved_at_40[0x3]; 3344 u8 log_hash_size[0x5]; 3345 u8 reserved_at_48[0x38]; 3346 }; 3347 3348 struct mlx5_ifc_stc_ste_param_tir_bits { 3349 u8 reserved_at_0[0x8]; 3350 u8 tirn[0x18]; 3351 u8 reserved_at_20[0x60]; 3352 }; 3353 3354 struct mlx5_ifc_stc_ste_param_table_bits { 3355 u8 reserved_at_0[0x8]; 3356 u8 table_id[0x18]; 3357 u8 reserved_at_20[0x60]; 3358 }; 3359 3360 struct mlx5_ifc_stc_ste_param_flow_counter_bits { 3361 u8 flow_counter_id[0x20]; 3362 }; 3363 3364 enum { 3365 MLX5_ASO_CT_NUM_PER_OBJ = 1, 3366 MLX5_ASO_METER_NUM_PER_OBJ = 2, 3367 }; 3368 3369 struct mlx5_ifc_stc_ste_param_execute_aso_bits { 3370 u8 aso_object_id[0x20]; 3371 u8 return_reg_id[0x4]; 3372 u8 aso_type[0x4]; 3373 u8 reserved_at_28[0x18]; 3374 }; 3375 3376 struct mlx5_ifc_stc_ste_param_header_modify_list_bits { 3377 u8 header_modify_pattern_id[0x20]; 3378 u8 header_modify_argument_id[0x20]; 3379 }; 3380 3381 enum mlx5_ifc_header_anchors { 3382 MLX5_HEADER_ANCHOR_PACKET_START = 0x0, 3383 MLX5_HEADER_ANCHOR_FIRST_VLAN_START = 0x2, 3384 MLX5_HEADER_ANCHOR_IPV6_IPV4 = 0x07, 3385 MLX5_HEADER_ANCHOR_INNER_MAC = 0x13, 3386 MLX5_HEADER_ANCHOR_INNER_IPV6_IPV4 = 0x19, 3387 }; 3388 3389 struct mlx5_ifc_stc_ste_param_remove_bits { 3390 u8 action_type[0x4]; 3391 u8 decap[0x1]; 3392 u8 reserved_at_5[0x5]; 3393 u8 remove_start_anchor[0x6]; 3394 u8 reserved_at_10[0x2]; 3395 u8 remove_end_anchor[0x6]; 3396 u8 reserved_at_18[0x8]; 3397 }; 3398 3399 struct mlx5_ifc_stc_ste_param_remove_words_bits { 3400 u8 action_type[0x4]; 3401 u8 reserved_at_4[0x6]; 3402 u8 remove_start_anchor[0x6]; 3403 u8 reserved_at_10[0x1]; 3404 u8 remove_offset[0x7]; 3405 u8 reserved_at_18[0x2]; 3406 u8 remove_size[0x6]; 3407 }; 3408 3409 struct mlx5_ifc_stc_ste_param_insert_bits { 3410 u8 action_type[0x4]; 3411 u8 encap[0x1]; 3412 u8 inline_data[0x1]; 3413 u8 reserved_at_6[0x4]; 3414 u8 insert_anchor[0x6]; 3415 u8 reserved_at_10[0x1]; 3416 u8 insert_offset[0x7]; 3417 u8 reserved_at_18[0x1]; 3418 u8 insert_size[0x7]; 3419 u8 insert_argument[0x20]; 3420 }; 3421 3422 struct mlx5_ifc_stc_ste_param_vport_bits { 3423 u8 eswitch_owner_vhca_id[0x10]; 3424 u8 vport_number[0x10]; 3425 u8 eswitch_owner_vhca_id_valid[0x1]; 3426 u8 reserved_at_21[0x59]; 3427 }; 3428 3429 union mlx5_ifc_stc_param_bits { 3430 struct mlx5_ifc_stc_ste_param_ste_table_bits ste_table; 3431 struct mlx5_ifc_stc_ste_param_tir_bits tir; 3432 struct mlx5_ifc_stc_ste_param_table_bits table; 3433 struct mlx5_ifc_stc_ste_param_flow_counter_bits counter; 3434 struct mlx5_ifc_stc_ste_param_header_modify_list_bits modify_header; 3435 struct mlx5_ifc_stc_ste_param_execute_aso_bits aso; 3436 struct mlx5_ifc_stc_ste_param_remove_bits remove_header; 3437 struct mlx5_ifc_stc_ste_param_insert_bits insert_header; 3438 struct mlx5_ifc_set_action_in_bits add; 3439 struct mlx5_ifc_set_action_in_bits set; 3440 struct mlx5_ifc_copy_action_in_bits copy; 3441 struct mlx5_ifc_stc_ste_param_vport_bits vport; 3442 u8 reserved_at_0[0x80]; 3443 }; 3444 3445 enum { 3446 MLX5_IFC_MODIFY_STC_FIELD_SELECT_NEW_STC = 1 << 0, 3447 }; 3448 3449 struct mlx5_ifc_stc_bits { 3450 u8 modify_field_select[0x40]; 3451 u8 reserved_at_40[0x48]; 3452 u8 table_type[0x8]; 3453 u8 ste_action_offset[0x8]; 3454 u8 action_type[0x8]; 3455 u8 reserved_at_a0[0x60]; 3456 union mlx5_ifc_stc_param_bits stc_param; 3457 u8 reserved_at_180[0x280]; 3458 }; 3459 3460 struct mlx5_ifc_ste_bits { 3461 u8 modify_field_select[0x40]; 3462 u8 reserved_at_40[0x48]; 3463 u8 table_type[0x8]; 3464 u8 reserved_at_90[0x370]; 3465 }; 3466 3467 enum { 3468 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61, 3469 }; 3470 3471 struct mlx5_ifc_definer_bits { 3472 u8 modify_field_select[0x40]; 3473 u8 reserved_at_40[0x50]; 3474 u8 format_id[0x10]; 3475 u8 reserved_at_60[0x60]; 3476 u8 format_select_dw3[0x8]; 3477 u8 format_select_dw2[0x8]; 3478 u8 format_select_dw1[0x8]; 3479 u8 format_select_dw0[0x8]; 3480 u8 format_select_dw7[0x8]; 3481 u8 format_select_dw6[0x8]; 3482 u8 format_select_dw5[0x8]; 3483 u8 format_select_dw4[0x8]; 3484 u8 reserved_at_100[0x18]; 3485 u8 format_select_dw8[0x8]; 3486 u8 reserved_at_120[0x20]; 3487 u8 format_select_byte3[0x8]; 3488 u8 format_select_byte2[0x8]; 3489 u8 format_select_byte1[0x8]; 3490 u8 format_select_byte0[0x8]; 3491 u8 format_select_byte7[0x8]; 3492 u8 format_select_byte6[0x8]; 3493 u8 format_select_byte5[0x8]; 3494 u8 format_select_byte4[0x8]; 3495 u8 reserved_at_180[0x40]; 3496 u8 ctrl[0xa0]; 3497 u8 match_mask[0x160]; 3498 }; 3499 3500 struct mlx5_ifc_arg_bits { 3501 u8 rsvd0[0x88]; 3502 u8 access_pd[0x18]; 3503 }; 3504 3505 struct mlx5_ifc_header_modify_pattern_in_bits { 3506 u8 modify_field_select[0x40]; 3507 3508 u8 reserved_at_40[0x40]; 3509 3510 u8 pattern_length[0x8]; 3511 u8 reserved_at_88[0x18]; 3512 3513 u8 reserved_at_a0[0x60]; 3514 3515 u8 pattern_data[MAX_ACTIONS_DATA_IN_HEADER_MODIFY * 8]; 3516 }; 3517 3518 struct mlx5_ifc_create_virtio_q_counters_in_bits { 3519 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3520 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 3521 }; 3522 3523 struct mlx5_ifc_query_virtio_q_counters_out_bits { 3524 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3525 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 3526 }; 3527 3528 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 3529 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3530 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 3531 }; 3532 3533 struct mlx5_ifc_create_rtc_in_bits { 3534 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3535 struct mlx5_ifc_rtc_bits rtc; 3536 }; 3537 3538 struct mlx5_ifc_create_stc_in_bits { 3539 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3540 struct mlx5_ifc_stc_bits stc; 3541 }; 3542 3543 struct mlx5_ifc_create_ste_in_bits { 3544 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3545 struct mlx5_ifc_ste_bits ste; 3546 }; 3547 3548 struct mlx5_ifc_create_definer_in_bits { 3549 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3550 struct mlx5_ifc_definer_bits definer; 3551 }; 3552 3553 struct mlx5_ifc_create_arg_in_bits { 3554 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3555 struct mlx5_ifc_arg_bits arg; 3556 }; 3557 3558 struct mlx5_ifc_create_header_modify_pattern_in_bits { 3559 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3560 struct mlx5_ifc_header_modify_pattern_in_bits pattern; 3561 }; 3562 3563 struct mlx5_ifc_create_alias_obj_in_bits { 3564 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3565 struct mlx5_ifc_alias_context_bits alias_ctx; 3566 }; 3567 3568 struct mlx5_ifc_generate_wqe_in_bits { 3569 u8 opcode[0x10]; 3570 u8 uid[0x10]; 3571 u8 reserved_at_20[0x10]; 3572 u8 op_mode[0x10]; 3573 u8 reserved_at_40[0x40]; 3574 u8 reserved_at_80[0x8]; 3575 u8 pdn[0x18]; 3576 u8 reserved_at_a0[0x160]; 3577 u8 wqe_ctrl[0x80]; 3578 u8 wqe_gta_ctrl[0x180]; 3579 u8 wqe_gta_data_0[0x200]; 3580 u8 wqe_gta_data_1[0x200]; 3581 }; 3582 3583 struct mlx5_ifc_generate_wqe_out_bits { 3584 u8 status[0x8]; 3585 u8 reserved_at_8[0x18]; 3586 u8 syndrome[0x20]; 3587 u8 reserved_at_40[0x1c0]; 3588 u8 cqe_data[0x200]; 3589 }; 3590 3591 enum { 3592 MLX5_CRYPTO_KEY_SIZE_128b = 0x0, 3593 MLX5_CRYPTO_KEY_SIZE_256b = 0x1, 3594 }; 3595 3596 enum { 3597 MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1, 3598 MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2, 3599 MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3, 3600 MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4, 3601 MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5, 3602 MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6, 3603 }; 3604 3605 struct mlx5_ifc_dek_bits { 3606 u8 modify_field_select[0x40]; 3607 u8 state[0x8]; 3608 u8 reserved_at_48[0xc]; 3609 u8 key_size[0x4]; 3610 u8 has_keytag[0x1]; 3611 u8 reserved_at_59[0x3]; 3612 u8 key_purpose[0x4]; 3613 u8 reserved_at_60[0x8]; 3614 u8 pd[0x18]; 3615 u8 reserved_at_80[0x100]; 3616 u8 opaque[0x40]; 3617 u8 reserved_at_1c0[0x40]; 3618 u8 key[0x400]; 3619 u8 reserved_at_600[0x200]; 3620 }; 3621 3622 struct mlx5_ifc_create_dek_in_bits { 3623 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3624 struct mlx5_ifc_dek_bits dek; 3625 }; 3626 3627 struct mlx5_ifc_import_kek_bits { 3628 u8 modify_field_select[0x40]; 3629 u8 state[0x8]; 3630 u8 reserved_at_48[0xc]; 3631 u8 key_size[0x4]; 3632 u8 reserved_at_58[0x1a8]; 3633 u8 key[0x400]; 3634 u8 reserved_at_600[0x200]; 3635 }; 3636 3637 struct mlx5_ifc_create_import_kek_in_bits { 3638 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3639 struct mlx5_ifc_import_kek_bits import_kek; 3640 }; 3641 3642 enum { 3643 MLX5_CREDENTIAL_ROLE_OFFICER = 0x0, 3644 MLX5_CREDENTIAL_ROLE_USER = 0x1, 3645 }; 3646 3647 struct mlx5_ifc_credential_bits { 3648 u8 modify_field_select[0x40]; 3649 u8 state[0x8]; 3650 u8 reserved_at_48[0x10]; 3651 u8 credential_role[0x8]; 3652 u8 reserved_at_60[0x1a0]; 3653 u8 credential[0x180]; 3654 u8 reserved_at_380[0x480]; 3655 }; 3656 3657 struct mlx5_ifc_create_credential_in_bits { 3658 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3659 struct mlx5_ifc_credential_bits credential; 3660 }; 3661 3662 struct mlx5_ifc_crypto_login_bits { 3663 u8 modify_field_select[0x40]; 3664 u8 reserved_at_40[0x48]; 3665 u8 credential_pointer[0x18]; 3666 u8 reserved_at_a0[0x8]; 3667 u8 session_import_kek_ptr[0x18]; 3668 u8 reserved_at_c0[0x140]; 3669 u8 credential[0x180]; 3670 u8 reserved_at_380[0x480]; 3671 }; 3672 3673 struct mlx5_ifc_create_crypto_login_in_bits { 3674 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3675 struct mlx5_ifc_crypto_login_bits crypto_login; 3676 }; 3677 3678 enum { 3679 MLX5_VIRTQ_STATE_INIT = 0, 3680 MLX5_VIRTQ_STATE_RDY = 1, 3681 MLX5_VIRTQ_STATE_SUSPEND = 2, 3682 MLX5_VIRTQ_STATE_ERROR = 3, 3683 }; 3684 3685 enum { 3686 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0), 3687 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3), 3688 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4), 3689 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD = (1UL << 5), 3690 MLX5_VIRTQ_MODIFY_TYPE_ADDR = (1UL << 6), 3691 MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX = (1UL << 7), 3692 MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX = (1UL << 8), 3693 MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE = (1UL << 9), 3694 MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0 = (1UL << 10), 3695 MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY = (1UL << 11), 3696 MLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK = (1UL << 12), 3697 MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE = (1UL << 13), 3698 }; 3699 3700 struct mlx5_ifc_virtio_q_bits { 3701 u8 virtio_q_type[0x8]; 3702 u8 reserved_at_8[0x5]; 3703 u8 event_mode[0x3]; 3704 u8 queue_index[0x10]; 3705 u8 full_emulation[0x1]; 3706 u8 virtio_version_1_0[0x1]; 3707 u8 reserved_at_22[0x2]; 3708 u8 offload_type[0x4]; 3709 u8 event_qpn_or_msix[0x18]; 3710 u8 doorbell_stride_idx[0x10]; 3711 u8 queue_size[0x10]; 3712 u8 device_emulation_id[0x20]; 3713 u8 desc_addr[0x40]; 3714 u8 used_addr[0x40]; 3715 u8 available_addr[0x40]; 3716 u8 virtio_q_mkey[0x20]; 3717 u8 reserved_at_160[0x18]; 3718 u8 error_type[0x8]; 3719 u8 umem_1_id[0x20]; 3720 u8 umem_1_size[0x20]; 3721 u8 umem_1_offset[0x40]; 3722 u8 umem_2_id[0x20]; 3723 u8 umem_2_size[0x20]; 3724 u8 umem_2_offset[0x40]; 3725 u8 umem_3_id[0x20]; 3726 u8 umem_3_size[0x20]; 3727 u8 umem_3_offset[0x40]; 3728 u8 counter_set_id[0x20]; 3729 u8 reserved_at_320[0x8]; 3730 u8 pd[0x18]; 3731 u8 reserved_at_340[0x2]; 3732 u8 queue_period_mode[0x2]; 3733 u8 queue_period_us[0xc]; 3734 u8 queue_max_count[0x10]; 3735 u8 reserved_at_360[0xa0]; 3736 }; 3737 3738 struct mlx5_ifc_virtio_net_q_bits { 3739 u8 modify_field_select[0x40]; 3740 u8 reserved_at_40[0x40]; 3741 u8 tso_ipv4[0x1]; 3742 u8 tso_ipv6[0x1]; 3743 u8 tx_csum[0x1]; 3744 u8 rx_csum[0x1]; 3745 u8 reserved_at_84[0x6]; 3746 u8 dirty_bitmap_dump_enable[0x1]; 3747 u8 vhost_log_page[0x5]; 3748 u8 reserved_at_90[0xc]; 3749 u8 state[0x4]; 3750 u8 reserved_at_a0[0x8]; 3751 u8 tisn_or_qpn[0x18]; 3752 u8 dirty_bitmap_mkey[0x20]; 3753 u8 dirty_bitmap_size[0x20]; 3754 u8 dirty_bitmap_addr[0x40]; 3755 u8 hw_available_index[0x10]; 3756 u8 hw_used_index[0x10]; 3757 u8 reserved_at_160[0xa0]; 3758 struct mlx5_ifc_virtio_q_bits virtio_q_context; 3759 }; 3760 3761 struct mlx5_ifc_create_virtq_in_bits { 3762 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3763 struct mlx5_ifc_virtio_net_q_bits virtq; 3764 }; 3765 3766 struct mlx5_ifc_query_virtq_out_bits { 3767 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3768 struct mlx5_ifc_virtio_net_q_bits virtq; 3769 }; 3770 3771 struct mlx5_ifc_flow_hit_aso_bits { 3772 u8 modify_field_select[0x40]; 3773 u8 reserved_at_40[0x48]; 3774 u8 access_pd[0x18]; 3775 u8 reserved_at_a0[0x160]; 3776 u8 flag[0x200]; 3777 }; 3778 3779 struct mlx5_ifc_create_flow_hit_aso_in_bits { 3780 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3781 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso; 3782 }; 3783 3784 struct mlx5_ifc_flow_meter_aso_bits { 3785 u8 modify_field_select[0x40]; 3786 u8 reserved_at_40[0x48]; 3787 u8 access_pd[0x18]; 3788 u8 reserved_at_a0[0x160]; 3789 u8 parameters[0x200]; 3790 }; 3791 3792 struct mlx5_ifc_create_flow_meter_aso_in_bits { 3793 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3794 struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso; 3795 }; 3796 3797 struct mlx5_ifc_tcp_window_params_bits { 3798 u8 max_ack[0x20]; 3799 u8 max_win[0x20]; 3800 u8 reply_end[0x20]; 3801 u8 sent_end[0x20]; 3802 }; 3803 3804 struct mlx5_ifc_conn_track_aso_bits { 3805 struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */ 3806 struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */ 3807 u8 last_end[0x20]; /* End of DW8. */ 3808 u8 last_ack[0x20]; /* End of DW9. */ 3809 u8 last_seq[0x20]; /* End of DW10. */ 3810 u8 last_win[0x10]; 3811 u8 reserved_at_170[0xa]; 3812 u8 last_dir[0x1]; 3813 u8 last_index[0x5]; /* End of DW11. */ 3814 u8 reserved_at_180[0x40]; /* End of DW13. */ 3815 u8 reply_direction_tcp_scale[0x4]; 3816 u8 reply_direction_tcp_close_initiated[0x1]; 3817 u8 reply_direction_tcp_liberal_enabled[0x1]; 3818 u8 reply_direction_tcp_data_unacked[0x1]; 3819 u8 reply_direction_tcp_max_ack[0x1]; 3820 u8 reserved_at_1c8[0x8]; 3821 u8 original_direction_tcp_scale[0x4]; 3822 u8 original_direction_tcp_close_initiated[0x1]; 3823 u8 original_direction_tcp_liberal_enabled[0x1]; 3824 u8 original_direction_tcp_data_unacked[0x1]; 3825 u8 original_direction_tcp_max_ack[0x1]; 3826 u8 reserved_at_1d8[0x8]; /* End of DW14. */ 3827 u8 valid[0x1]; 3828 u8 state[0x3]; 3829 u8 freeze_track[0x1]; 3830 u8 reserved_at_1e5[0xb]; 3831 u8 reserved_at_1f0[0x1]; 3832 u8 connection_assured[0x1]; 3833 u8 sack_permitted[0x1]; 3834 u8 challenged_acked[0x1]; 3835 u8 heartbeat[0x1]; 3836 u8 max_ack_window[0x3]; 3837 u8 reserved_at_1f8[0x1]; 3838 u8 retransmission_counter[0x3]; 3839 u8 retranmission_limit_exceeded[0x1]; 3840 u8 retranmission_limit[0x3]; /* End of DW15. */ 3841 }; 3842 3843 struct mlx5_ifc_conn_track_offload_bits { 3844 u8 modify_field_select[0x40]; 3845 u8 reserved_at_40[0x40]; 3846 u8 reserved_at_80[0x8]; 3847 u8 conn_track_aso_access_pd[0x18]; 3848 u8 reserved_at_a0[0x160]; 3849 struct mlx5_ifc_conn_track_aso_bits conn_track_aso; 3850 }; 3851 3852 struct mlx5_ifc_create_conn_track_aso_in_bits { 3853 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3854 struct mlx5_ifc_conn_track_offload_bits conn_track_offload; 3855 }; 3856 3857 enum mlx5_access_aso_opc_mod { 3858 ASO_OPC_MOD_IPSEC = 0x0, 3859 ASO_OPC_MOD_CONNECTION_TRACKING = 0x1, 3860 ASO_OPC_MOD_POLICER = 0x2, 3861 ASO_OPC_MOD_RACE_AVOIDANCE = 0x3, 3862 ASO_OPC_MOD_FLOW_HIT = 0x4, 3863 }; 3864 3865 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30 3866 3867 enum mlx5_aso_data_mask_mode { 3868 BITWISE_64BIT = 0x0, 3869 BYTEWISE_64BYTE = 0x1, 3870 CALCULATED_64BYTE = 0x2, 3871 }; 3872 3873 #define ASO_CSEG_COND_0_OPER_OFFSET 20 3874 #define ASO_CSEG_COND_1_OPER_OFFSET 16 3875 3876 enum mlx5_aso_pre_cond_op { 3877 ASO_OP_ALWAYS_FALSE = 0x0, 3878 ASO_OP_ALWAYS_TRUE = 0x1, 3879 ASO_OP_EQUAL = 0x2, 3880 ASO_OP_NOT_EQUAL = 0x3, 3881 ASO_OP_GREATER_OR_EQUAL = 0x4, 3882 ASO_OP_LESSER_OR_EQUAL = 0x5, 3883 ASO_OP_LESSER = 0x6, 3884 ASO_OP_GREATER = 0x7, 3885 ASO_OP_CYCLIC_GREATER = 0x8, 3886 ASO_OP_CYCLIC_LESSER = 0x9, 3887 }; 3888 3889 #define ASO_CSEG_COND_OPER_OFFSET 6 3890 3891 enum mlx5_aso_op { 3892 ASO_OPER_LOGICAL_AND = 0x0, 3893 ASO_OPER_LOGICAL_OR = 0x1, 3894 }; 3895 3896 /* ASO WQE CTRL segment. */ 3897 struct mlx5_aso_cseg { 3898 uint32_t va_h; 3899 uint32_t va_l_r; 3900 uint32_t lkey; 3901 uint32_t operand_masks; 3902 uint32_t condition_0_data; 3903 uint32_t condition_0_mask; 3904 uint32_t condition_1_data; 3905 uint32_t condition_1_mask; 3906 uint64_t bitwise_data; 3907 uint64_t data_mask; 3908 } __rte_packed; 3909 3910 /* A meter data segment - 2 per ASO WQE. */ 3911 struct mlx5_aso_mtr_dseg { 3912 uint32_t v_bo_sc_bbog_mm; 3913 /* 3914 * bit 31: valid, 30: bucket overflow, 28-29: start color, 3915 * 27: both buckets on green, 24-25: meter mode. 3916 */ 3917 uint32_t reserved; 3918 uint32_t cbs_cir; 3919 /* 3920 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 3921 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 3922 */ 3923 uint32_t c_tokens; 3924 uint32_t ebs_eir; 3925 /* 3926 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 3927 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 3928 */ 3929 uint32_t e_tokens; 3930 uint64_t timestamp; 3931 } __rte_packed; 3932 3933 #define ASO_DSEG_VALID_OFFSET 31 3934 #define ASO_DSEG_BO_OFFSET 30 3935 #define ASO_DSEG_SC_OFFSET 28 3936 #define ASO_DSEG_BBOG_OFFSET 27 3937 #define ASO_DSEG_MTR_MODE 24 3938 #define ASO_DSEG_CBS_EXP_OFFSET 24 3939 #define ASO_DSEG_CBS_MAN_OFFSET 16 3940 #define ASO_DSEG_XIR_EXP_MASK 0x1F 3941 #define ASO_DSEG_XIR_EXP_OFFSET 8 3942 #define ASO_DSEG_EBS_EXP_OFFSET 24 3943 #define ASO_DSEG_EBS_MAN_OFFSET 16 3944 #define ASO_DSEG_EXP_MASK 0x1F 3945 #define ASO_DSEG_MAN_MASK 0xFF 3946 3947 #define MLX5_ASO_WQE_DSEG_SIZE 0x40 3948 #define MLX5_ASO_METERS_PER_WQE 2 3949 #define MLX5_ASO_MTRS_PER_POOL 128 3950 3951 /* ASO WQE data segment. */ 3952 struct mlx5_aso_dseg { 3953 union { 3954 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE]; 3955 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE]; 3956 }; 3957 } __rte_packed; 3958 3959 /* ASO WQE. */ 3960 struct mlx5_aso_wqe { 3961 struct mlx5_wqe_cseg general_cseg; 3962 struct mlx5_aso_cseg aso_cseg; 3963 struct mlx5_aso_dseg aso_dseg; 3964 } __rte_packed; 3965 3966 enum { 3967 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, 3968 MLX5_EVENT_TYPE_SRQ_LIMIT_REACHED = 0x14, 3969 }; 3970 3971 enum { 3972 MLX5_QP_ST_RC = 0x0, 3973 }; 3974 3975 enum { 3976 MLX5_QP_PM_MIGRATED = 0x3, 3977 }; 3978 3979 enum { 3980 MLX5_NON_ZERO_RQ = 0x0, 3981 MLX5_SRQ_RQ = 0x1, 3982 MLX5_CRQ_RQ = 0x2, 3983 MLX5_ZERO_LEN_RQ = 0x3, 3984 }; 3985 3986 struct mlx5_ifc_ads_bits { 3987 u8 fl[0x1]; 3988 u8 free_ar[0x1]; 3989 u8 reserved_at_2[0xe]; 3990 u8 pkey_index[0x10]; 3991 u8 reserved_at_20[0x8]; 3992 u8 grh[0x1]; 3993 u8 mlid[0x7]; 3994 u8 rlid[0x10]; 3995 u8 ack_timeout[0x5]; 3996 u8 reserved_at_45[0x3]; 3997 u8 src_addr_index[0x8]; 3998 u8 reserved_at_50[0x4]; 3999 u8 stat_rate[0x4]; 4000 u8 hop_limit[0x8]; 4001 u8 reserved_at_60[0x4]; 4002 u8 tclass[0x8]; 4003 u8 flow_label[0x14]; 4004 u8 rgid_rip[16][0x8]; 4005 u8 reserved_at_100[0x4]; 4006 u8 f_dscp[0x1]; 4007 u8 f_ecn[0x1]; 4008 u8 reserved_at_106[0x1]; 4009 u8 f_eth_prio[0x1]; 4010 u8 ecn[0x2]; 4011 u8 dscp[0x6]; 4012 u8 udp_sport[0x10]; 4013 u8 dei_cfi[0x1]; 4014 u8 eth_prio[0x3]; 4015 u8 sl[0x4]; 4016 u8 vhca_port_num[0x8]; 4017 u8 rmac_47_32[0x10]; 4018 u8 rmac_31_0[0x20]; 4019 }; 4020 4021 struct mlx5_ifc_qpc_bits { 4022 u8 state[0x4]; 4023 u8 lag_tx_port_affinity[0x4]; 4024 u8 st[0x8]; 4025 u8 reserved_at_10[0x3]; 4026 u8 pm_state[0x2]; 4027 u8 reserved_at_15[0x1]; 4028 u8 req_e2e_credit_mode[0x2]; 4029 u8 offload_type[0x4]; 4030 u8 end_padding_mode[0x2]; 4031 u8 reserved_at_1e[0x2]; 4032 u8 wq_signature[0x1]; 4033 u8 block_lb_mc[0x1]; 4034 u8 atomic_like_write_en[0x1]; 4035 u8 latency_sensitive[0x1]; 4036 u8 reserved_at_24[0x1]; 4037 u8 drain_sigerr[0x1]; 4038 u8 reserved_at_26[0x2]; 4039 u8 pd[0x18]; 4040 u8 mtu[0x3]; 4041 u8 log_msg_max[0x5]; 4042 u8 reserved_at_48[0x1]; 4043 u8 log_rq_size[0x4]; 4044 u8 log_rq_stride[0x3]; 4045 u8 no_sq[0x1]; 4046 u8 log_sq_size[0x4]; 4047 u8 reserved_at_55[0x3]; 4048 u8 ts_format[0x2]; 4049 u8 reserved_at_5a[0x1]; 4050 u8 rlky[0x1]; 4051 u8 ulp_stateless_offload_mode[0x4]; 4052 u8 counter_set_id[0x8]; 4053 u8 uar_page[0x18]; 4054 u8 reserved_at_80[0x8]; 4055 u8 user_index[0x18]; 4056 u8 reserved_at_a0[0x3]; 4057 u8 log_page_size[0x5]; 4058 u8 remote_qpn[0x18]; 4059 struct mlx5_ifc_ads_bits primary_address_path; 4060 struct mlx5_ifc_ads_bits secondary_address_path; 4061 u8 log_ack_req_freq[0x4]; 4062 u8 reserved_at_384[0x4]; 4063 u8 log_sra_max[0x3]; 4064 u8 reserved_at_38b[0x2]; 4065 u8 retry_count[0x3]; 4066 u8 rnr_retry[0x3]; 4067 u8 reserved_at_393[0x1]; 4068 u8 fre[0x1]; 4069 u8 cur_rnr_retry[0x3]; 4070 u8 cur_retry_count[0x3]; 4071 u8 reserved_at_39b[0x5]; 4072 u8 reserved_at_3a0[0x20]; 4073 u8 reserved_at_3c0[0x8]; 4074 u8 next_send_psn[0x18]; 4075 u8 reserved_at_3e0[0x8]; 4076 u8 cqn_snd[0x18]; 4077 u8 reserved_at_400[0x8]; 4078 u8 deth_sqpn[0x18]; 4079 u8 reserved_at_420[0x20]; 4080 u8 reserved_at_440[0x8]; 4081 u8 last_acked_psn[0x18]; 4082 u8 reserved_at_460[0x8]; 4083 u8 ssn[0x18]; 4084 u8 reserved_at_480[0x8]; 4085 u8 log_rra_max[0x3]; 4086 u8 reserved_at_48b[0x1]; 4087 u8 atomic_mode[0x4]; 4088 u8 rre[0x1]; 4089 u8 rwe[0x1]; 4090 u8 rae[0x1]; 4091 u8 reserved_at_493[0x1]; 4092 u8 page_offset[0x6]; 4093 u8 reserved_at_49a[0x3]; 4094 u8 cd_slave_receive[0x1]; 4095 u8 cd_slave_send[0x1]; 4096 u8 cd_master[0x1]; 4097 u8 reserved_at_4a0[0x3]; 4098 u8 min_rnr_nak[0x5]; 4099 u8 next_rcv_psn[0x18]; 4100 u8 reserved_at_4c0[0x8]; 4101 u8 xrcd[0x18]; 4102 u8 reserved_at_4e0[0x8]; 4103 u8 cqn_rcv[0x18]; 4104 u8 dbr_addr[0x40]; 4105 u8 q_key[0x20]; 4106 u8 reserved_at_560[0x5]; 4107 u8 rq_type[0x3]; 4108 u8 srqn_rmpn_xrqn[0x18]; 4109 u8 reserved_at_580[0x8]; 4110 u8 rmsn[0x18]; 4111 u8 hw_sq_wqebb_counter[0x10]; 4112 u8 sw_sq_wqebb_counter[0x10]; 4113 u8 hw_rq_counter[0x20]; 4114 u8 sw_rq_counter[0x20]; 4115 u8 reserved_at_600[0x20]; 4116 u8 reserved_at_620[0xf]; 4117 u8 cgs[0x1]; 4118 u8 cs_req[0x8]; 4119 u8 cs_res[0x8]; 4120 u8 dc_access_key[0x40]; 4121 u8 reserved_at_680[0x3]; 4122 u8 dbr_umem_valid[0x1]; 4123 u8 reserved_at_684[0x9c]; 4124 u8 dbr_umem_id[0x20]; 4125 }; 4126 4127 struct mlx5_ifc_create_qp_out_bits { 4128 u8 status[0x8]; 4129 u8 reserved_at_8[0x18]; 4130 u8 syndrome[0x20]; 4131 u8 reserved_at_40[0x8]; 4132 u8 qpn[0x18]; 4133 u8 reserved_at_60[0x20]; 4134 }; 4135 4136 struct mlx5_ifc_qpc_extension_bits { 4137 u8 reserved_at_0[0x2]; 4138 u8 mmo[0x1]; 4139 u8 reserved_at_3[0x5fd]; 4140 }; 4141 4142 #ifdef PEDANTIC 4143 #pragma GCC diagnostic ignored "-Wpedantic" 4144 #endif 4145 struct mlx5_ifc_qpc_pas_list_bits { 4146 u8 pas[0][0x40]; 4147 }; 4148 4149 #ifdef PEDANTIC 4150 #pragma GCC diagnostic ignored "-Wpedantic" 4151 #endif 4152 struct mlx5_ifc_qpc_extension_and_pas_list_bits { 4153 struct mlx5_ifc_qpc_extension_bits qpc_data_extension; 4154 u8 pas[][0x40]; 4155 }; 4156 4157 4158 #ifdef PEDANTIC 4159 #pragma GCC diagnostic ignored "-Wpedantic" 4160 #endif 4161 struct mlx5_ifc_create_qp_in_bits { 4162 u8 opcode[0x10]; 4163 u8 uid[0x10]; 4164 u8 reserved_at_20[0x10]; 4165 u8 op_mod[0x10]; 4166 u8 qpc_ext[0x1]; 4167 u8 reserved_at_41[0x3f]; 4168 u8 opt_param_mask[0x20]; 4169 u8 reserved_at_a0[0x20]; 4170 struct mlx5_ifc_qpc_bits qpc; 4171 u8 wq_umem_offset[0x40]; 4172 u8 wq_umem_id[0x20]; 4173 u8 wq_umem_valid[0x1]; 4174 u8 reserved_at_861[0x1f]; 4175 union { 4176 struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list; 4177 struct mlx5_ifc_qpc_extension_and_pas_list_bits 4178 qpc_extension_and_pas_list; 4179 }; 4180 }; 4181 #ifdef PEDANTIC 4182 #pragma GCC diagnostic error "-Wpedantic" 4183 #endif 4184 4185 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4186 u8 status[0x8]; 4187 u8 reserved_at_8[0x18]; 4188 u8 syndrome[0x20]; 4189 u8 reserved_at_40[0x40]; 4190 }; 4191 4192 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4193 u8 opcode[0x10]; 4194 u8 uid[0x10]; 4195 u8 reserved_at_20[0x10]; 4196 u8 op_mod[0x10]; 4197 u8 reserved_at_40[0x8]; 4198 u8 qpn[0x18]; 4199 u8 reserved_at_60[0x20]; 4200 u8 opt_param_mask[0x20]; 4201 u8 reserved_at_a0[0x20]; 4202 struct mlx5_ifc_qpc_bits qpc; 4203 u8 reserved_at_800[0x80]; 4204 }; 4205 4206 struct mlx5_ifc_sqd2rts_qp_out_bits { 4207 u8 status[0x8]; 4208 u8 reserved_at_8[0x18]; 4209 u8 syndrome[0x20]; 4210 u8 reserved_at_40[0x40]; 4211 }; 4212 4213 struct mlx5_ifc_sqd2rts_qp_in_bits { 4214 u8 opcode[0x10]; 4215 u8 uid[0x10]; 4216 u8 reserved_at_20[0x10]; 4217 u8 op_mod[0x10]; 4218 u8 reserved_at_40[0x8]; 4219 u8 qpn[0x18]; 4220 u8 reserved_at_60[0x20]; 4221 u8 opt_param_mask[0x20]; 4222 u8 reserved_at_a0[0x20]; 4223 struct mlx5_ifc_qpc_bits qpc; 4224 u8 reserved_at_800[0x80]; 4225 }; 4226 4227 struct mlx5_ifc_rts2rts_qp_out_bits { 4228 u8 status[0x8]; 4229 u8 reserved_at_8[0x18]; 4230 u8 syndrome[0x20]; 4231 u8 reserved_at_40[0x40]; 4232 }; 4233 4234 struct mlx5_ifc_rts2rts_qp_in_bits { 4235 u8 opcode[0x10]; 4236 u8 uid[0x10]; 4237 u8 reserved_at_20[0x10]; 4238 u8 op_mod[0x10]; 4239 u8 reserved_at_40[0x8]; 4240 u8 qpn[0x18]; 4241 u8 reserved_at_60[0x20]; 4242 u8 opt_param_mask[0x20]; 4243 u8 reserved_at_a0[0x20]; 4244 struct mlx5_ifc_qpc_bits qpc; 4245 u8 reserved_at_800[0x80]; 4246 }; 4247 4248 struct mlx5_ifc_rtr2rts_qp_out_bits { 4249 u8 status[0x8]; 4250 u8 reserved_at_8[0x18]; 4251 u8 syndrome[0x20]; 4252 u8 reserved_at_40[0x40]; 4253 }; 4254 4255 struct mlx5_ifc_rtr2rts_qp_in_bits { 4256 u8 opcode[0x10]; 4257 u8 uid[0x10]; 4258 u8 reserved_at_20[0x10]; 4259 u8 op_mod[0x10]; 4260 u8 reserved_at_40[0x8]; 4261 u8 qpn[0x18]; 4262 u8 reserved_at_60[0x20]; 4263 u8 opt_param_mask[0x20]; 4264 u8 reserved_at_a0[0x20]; 4265 struct mlx5_ifc_qpc_bits qpc; 4266 u8 reserved_at_800[0x80]; 4267 }; 4268 4269 struct mlx5_ifc_rst2init_qp_out_bits { 4270 u8 status[0x8]; 4271 u8 reserved_at_8[0x18]; 4272 u8 syndrome[0x20]; 4273 u8 reserved_at_40[0x40]; 4274 }; 4275 4276 struct mlx5_ifc_rst2init_qp_in_bits { 4277 u8 opcode[0x10]; 4278 u8 uid[0x10]; 4279 u8 reserved_at_20[0x10]; 4280 u8 op_mod[0x10]; 4281 u8 reserved_at_40[0x8]; 4282 u8 qpn[0x18]; 4283 u8 reserved_at_60[0x20]; 4284 u8 opt_param_mask[0x20]; 4285 u8 reserved_at_a0[0x20]; 4286 struct mlx5_ifc_qpc_bits qpc; 4287 u8 reserved_at_800[0x80]; 4288 }; 4289 4290 struct mlx5_ifc_init2rtr_qp_out_bits { 4291 u8 status[0x8]; 4292 u8 reserved_at_8[0x18]; 4293 u8 syndrome[0x20]; 4294 u8 reserved_at_40[0x40]; 4295 }; 4296 4297 struct mlx5_ifc_init2rtr_qp_in_bits { 4298 u8 opcode[0x10]; 4299 u8 uid[0x10]; 4300 u8 reserved_at_20[0x10]; 4301 u8 op_mod[0x10]; 4302 u8 reserved_at_40[0x8]; 4303 u8 qpn[0x18]; 4304 u8 reserved_at_60[0x20]; 4305 u8 opt_param_mask[0x20]; 4306 u8 reserved_at_a0[0x20]; 4307 struct mlx5_ifc_qpc_bits qpc; 4308 u8 reserved_at_800[0x80]; 4309 }; 4310 4311 struct mlx5_ifc_init2init_qp_out_bits { 4312 u8 status[0x8]; 4313 u8 reserved_at_8[0x18]; 4314 u8 syndrome[0x20]; 4315 u8 reserved_at_40[0x40]; 4316 }; 4317 4318 struct mlx5_ifc_init2init_qp_in_bits { 4319 u8 opcode[0x10]; 4320 u8 uid[0x10]; 4321 u8 reserved_at_20[0x10]; 4322 u8 op_mod[0x10]; 4323 u8 reserved_at_40[0x8]; 4324 u8 qpn[0x18]; 4325 u8 reserved_at_60[0x20]; 4326 u8 opt_param_mask[0x20]; 4327 u8 reserved_at_a0[0x20]; 4328 struct mlx5_ifc_qpc_bits qpc; 4329 u8 reserved_at_800[0x80]; 4330 }; 4331 4332 struct mlx5_ifc_2rst_qp_out_bits { 4333 u8 status[0x8]; 4334 u8 reserved_at_8[0x18]; 4335 u8 syndrome[0x20]; 4336 u8 reserved_at_40[0x40]; 4337 }; 4338 4339 struct mlx5_ifc_2rst_qp_in_bits { 4340 u8 opcode[0x10]; 4341 u8 uid[0x10]; 4342 u8 vhca_tunnel_id[0x10]; 4343 u8 op_mod[0x10]; 4344 u8 reserved_at_80[0x8]; 4345 u8 qpn[0x18]; 4346 u8 reserved_at_a0[0x20]; 4347 }; 4348 4349 struct mlx5_ifc_dealloc_pd_out_bits { 4350 u8 status[0x8]; 4351 u8 reserved_0[0x18]; 4352 u8 syndrome[0x20]; 4353 u8 reserved_1[0x40]; 4354 }; 4355 4356 struct mlx5_ifc_dealloc_pd_in_bits { 4357 u8 opcode[0x10]; 4358 u8 reserved_0[0x10]; 4359 u8 reserved_1[0x10]; 4360 u8 op_mod[0x10]; 4361 u8 reserved_2[0x8]; 4362 u8 pd[0x18]; 4363 u8 reserved_3[0x20]; 4364 }; 4365 4366 struct mlx5_ifc_alloc_pd_out_bits { 4367 u8 status[0x8]; 4368 u8 reserved_0[0x18]; 4369 u8 syndrome[0x20]; 4370 u8 reserved_1[0x8]; 4371 u8 pd[0x18]; 4372 u8 reserved_2[0x20]; 4373 }; 4374 4375 struct mlx5_ifc_alloc_pd_in_bits { 4376 u8 opcode[0x10]; 4377 u8 reserved_0[0x10]; 4378 u8 reserved_1[0x10]; 4379 u8 op_mod[0x10]; 4380 u8 reserved_2[0x40]; 4381 }; 4382 4383 #ifdef PEDANTIC 4384 #pragma GCC diagnostic ignored "-Wpedantic" 4385 #endif 4386 struct mlx5_ifc_query_qp_out_bits { 4387 u8 status[0x8]; 4388 u8 reserved_at_8[0x18]; 4389 u8 syndrome[0x20]; 4390 u8 reserved_at_40[0x40]; 4391 u8 opt_param_mask[0x20]; 4392 u8 reserved_at_a0[0x20]; 4393 struct mlx5_ifc_qpc_bits qpc; 4394 u8 reserved_at_800[0x80]; 4395 u8 pas[][0x40]; 4396 }; 4397 #ifdef PEDANTIC 4398 #pragma GCC diagnostic error "-Wpedantic" 4399 #endif 4400 4401 struct mlx5_ifc_query_qp_in_bits { 4402 u8 opcode[0x10]; 4403 u8 reserved_at_10[0x10]; 4404 u8 reserved_at_20[0x10]; 4405 u8 op_mod[0x10]; 4406 u8 reserved_at_40[0x8]; 4407 u8 qpn[0x18]; 4408 u8 reserved_at_60[0x20]; 4409 }; 4410 4411 enum { 4412 MLX5_DATA_RATE = 0x0, 4413 MLX5_WQE_RATE = 0x1, 4414 }; 4415 4416 struct mlx5_ifc_set_pp_rate_limit_context_bits { 4417 u8 rate_limit[0x20]; 4418 u8 burst_upper_bound[0x20]; 4419 u8 reserved_at_40[0xC]; 4420 u8 rate_mode[0x4]; 4421 u8 typical_packet_size[0x10]; 4422 u8 reserved_at_60[0x120]; 4423 }; 4424 4425 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u 4426 4427 #ifdef PEDANTIC 4428 #pragma GCC diagnostic ignored "-Wpedantic" 4429 #endif 4430 struct mlx5_ifc_access_register_out_bits { 4431 u8 status[0x8]; 4432 u8 reserved_at_8[0x18]; 4433 u8 syndrome[0x20]; 4434 u8 reserved_at_40[0x40]; 4435 u8 register_data[][0x20]; 4436 }; 4437 4438 struct mlx5_ifc_access_register_in_bits { 4439 u8 opcode[0x10]; 4440 u8 reserved_at_10[0x10]; 4441 u8 reserved_at_20[0x10]; 4442 u8 op_mod[0x10]; 4443 u8 reserved_at_40[0x10]; 4444 u8 register_id[0x10]; 4445 u8 argument[0x20]; 4446 u8 register_data[][0x20]; 4447 }; 4448 #ifdef PEDANTIC 4449 #pragma GCC diagnostic error "-Wpedantic" 4450 #endif 4451 4452 enum { 4453 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 4454 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 4455 }; 4456 4457 enum { 4458 MLX5_REGISTER_ID_MTUTC = 0x9055, 4459 MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002, 4460 MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, 4461 MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, 4462 MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, 4463 MLX5_QSHR_REGISTER_ID = 0x4030, 4464 }; 4465 4466 struct mlx5_ifc_register_mtutc_bits { 4467 u8 time_stamp_mode[0x2]; 4468 u8 time_stamp_state[0x2]; 4469 u8 reserved_at_4[0x18]; 4470 u8 operation[0x4]; 4471 u8 freq_adjustment[0x20]; 4472 u8 reserved_at_40[0x40]; 4473 u8 utc_sec[0x20]; 4474 u8 utc_nsec[0x20]; 4475 u8 time_adjustment[0x20]; 4476 }; 4477 4478 struct mlx5_ifc_ets_global_config_register_bits { 4479 u8 reserved_at_0[0x2]; 4480 u8 rate_limit_update[0x1]; 4481 u8 reserved_at_3[0x29]; 4482 u8 max_bw_units[0x4]; 4483 u8 reserved_at_48[0x8]; 4484 u8 max_bw_value[0x8]; 4485 }; 4486 4487 #define ETS_GLOBAL_CONFIG_BW_UNIT_DISABLED 0x0 4488 #define ETS_GLOBAL_CONFIG_BW_UNIT_HUNDREDS_MBPS 0x3 4489 #define ETS_GLOBAL_CONFIG_BW_UNIT_GBPS 0x4 4490 4491 struct mlx5_ifc_register_qshr_bits { 4492 u8 reserved_at_0[0x4]; 4493 u8 connected_host[0x1]; 4494 u8 vqos[0x1]; 4495 u8 fast_response[0x1]; 4496 u8 reserved_at_7[0x1]; 4497 u8 local_port[0x8]; 4498 u8 reserved_at_16[0x230]; 4499 struct mlx5_ifc_ets_global_config_register_bits global_config; 4500 }; 4501 4502 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 4503 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 4504 4505 struct mlx5_ifc_crypto_operational_register_bits { 4506 u8 wrapped_crypto_operational[0x1]; 4507 u8 reserved_at_1[0x1b]; 4508 u8 kek_size[0x4]; 4509 u8 reserved_at_20[0x20]; 4510 u8 credential[0x140]; 4511 u8 kek[0x100]; 4512 u8 reserved_at_280[0x180]; 4513 }; 4514 4515 struct mlx5_ifc_crypto_caps_bits { 4516 u8 wrapped_crypto_operational[0x1]; 4517 u8 wrapped_crypto_going_to_commissioning[0x1]; 4518 u8 sw_wrapped_dek[0x1]; 4519 u8 synchronize_dek[0x1]; 4520 u8 int_kek_manual[0x1]; 4521 u8 int_kek_auto[0x1]; 4522 u8 reserved_at_6[0x12]; 4523 u8 wrapped_import_method[0x8]; 4524 u8 reserved_at_20[0x3]; 4525 u8 log_dek_max_alloc[0x5]; 4526 u8 reserved_at_28[0x3]; 4527 u8 log_max_num_deks[0x5]; 4528 u8 reserved_at_30[0x3]; 4529 u8 log_max_num_import_keks[0x5]; 4530 u8 reserved_at_38[0x3]; 4531 u8 log_max_num_creds[0x5]; 4532 u8 failed_selftests[0x10]; 4533 u8 num_nv_import_keks[0x8]; 4534 u8 num_nv_credentials[0x8]; 4535 u8 reserved_at_60[0x3]; 4536 u8 log_dek_granularity[0x5]; 4537 u8 reserved_at_68[0x3]; 4538 u8 log_max_num_int_kek[0x5]; 4539 u8 reserved_at_70[0x10]; 4540 u8 reserved_at_80[0x780]; 4541 }; 4542 4543 struct mlx5_ifc_crypto_commissioning_register_bits { 4544 u8 token[0x1]; /* TODO: add size after PRM update */ 4545 }; 4546 4547 struct mlx5_ifc_import_kek_handle_register_bits { 4548 struct mlx5_ifc_crypto_login_bits crypto_login_object; 4549 struct mlx5_ifc_import_kek_bits import_kek_object; 4550 u8 reserved_at_200[0x4]; 4551 u8 write_operation[0x4]; 4552 u8 import_kek_id[0x18]; 4553 u8 reserved_at_220[0xe0]; 4554 }; 4555 4556 struct mlx5_ifc_credential_handle_register_bits { 4557 struct mlx5_ifc_crypto_login_bits crypto_login_object; 4558 struct mlx5_ifc_credential_bits credential_object; 4559 u8 reserved_at_200[0x4]; 4560 u8 write_operation[0x4]; 4561 u8 credential_id[0x18]; 4562 u8 reserved_at_220[0xe0]; 4563 }; 4564 4565 enum { 4566 MLX5_REGISTER_ADD_OPERATION = 0x1, 4567 MLX5_REGISTER_DELETE_OPERATION = 0x2, 4568 }; 4569 4570 struct mlx5_ifc_parse_graph_arc_bits { 4571 u8 start_inner_tunnel[0x1]; 4572 u8 reserved_at_1[0x7]; 4573 u8 arc_parse_graph_node[0x8]; 4574 u8 compare_condition_value[0x10]; 4575 u8 parse_graph_node_handle[0x20]; 4576 u8 reserved_at_40[0x40]; 4577 }; 4578 4579 struct mlx5_ifc_parse_graph_flow_match_sample_bits { 4580 u8 flow_match_sample_en[0x1]; 4581 u8 reserved_at_1[0x3]; 4582 u8 flow_match_sample_offset_mode[0x4]; 4583 u8 reserved_at_5[0x8]; 4584 u8 flow_match_sample_field_offset[0x10]; 4585 u8 reserved_at_32[0x4]; 4586 u8 flow_match_sample_field_offset_shift[0x4]; 4587 u8 flow_match_sample_field_base_offset[0x8]; 4588 u8 reserved_at_48[0xd]; 4589 u8 flow_match_sample_tunnel_mode[0x3]; 4590 u8 flow_match_sample_field_offset_mask[0x20]; 4591 u8 flow_match_sample_field_id[0x20]; 4592 }; 4593 4594 struct mlx5_ifc_parse_graph_flex_bits { 4595 u8 modify_field_select[0x40]; 4596 u8 reserved_at_64[0x20]; 4597 u8 header_length_base_value[0x10]; 4598 u8 reserved_at_112[0x4]; 4599 u8 header_length_field_shift[0x4]; 4600 u8 reserved_at_120[0x4]; 4601 u8 header_length_mode[0x4]; 4602 u8 header_length_field_offset[0x10]; 4603 u8 next_header_field_offset[0x10]; 4604 u8 reserved_at_160[0x12]; 4605 u8 head_anchor_id[0x6]; 4606 u8 reserved_at_178[0x3]; 4607 u8 next_header_field_size[0x5]; 4608 u8 header_length_field_mask[0x20]; 4609 u8 reserved_at_224[0x20]; 4610 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8]; 4611 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8]; 4612 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8]; 4613 }; 4614 4615 struct mlx5_ifc_create_flex_parser_in_bits { 4616 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4617 struct mlx5_ifc_parse_graph_flex_bits flex; 4618 }; 4619 4620 struct mlx5_ifc_create_flex_parser_out_bits { 4621 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 4622 struct mlx5_ifc_parse_graph_flex_bits flex; 4623 }; 4624 4625 struct mlx5_ifc_parse_graph_flex_out_bits { 4626 u8 status[0x8]; 4627 u8 reserved_at_8[0x18]; 4628 u8 syndrome[0x20]; 4629 u8 reserved_at_40[0x40]; 4630 struct mlx5_ifc_parse_graph_flex_bits capability; 4631 }; 4632 4633 struct regexp_params_field_select_bits { 4634 u8 reserved_at_0[0x1d]; 4635 u8 rof_mkey[0x1]; 4636 u8 stop_engine[0x1]; 4637 u8 reserved_at_1f[0x1]; 4638 }; 4639 4640 struct mlx5_ifc_regexp_params_bits { 4641 u8 reserved_at_0[0x1f]; 4642 u8 stop_engine[0x1]; 4643 u8 reserved_at_20[0x60]; 4644 u8 rof_mkey[0x20]; 4645 u8 rof_size[0x20]; 4646 u8 rof_mkey_va[0x40]; 4647 u8 reserved_at_100[0x80]; 4648 }; 4649 4650 struct mlx5_ifc_set_regexp_params_in_bits { 4651 u8 opcode[0x10]; 4652 u8 uid[0x10]; 4653 u8 reserved_at_20[0x10]; 4654 u8 op_mod[0x10]; 4655 u8 reserved_at_40[0x18]; 4656 u8 engine_id[0x8]; 4657 struct regexp_params_field_select_bits field_select; 4658 struct mlx5_ifc_regexp_params_bits regexp_params; 4659 }; 4660 4661 struct mlx5_ifc_set_regexp_params_out_bits { 4662 u8 status[0x8]; 4663 u8 reserved_at_8[0x18]; 4664 u8 syndrome[0x20]; 4665 u8 reserved_at_18[0x40]; 4666 }; 4667 4668 struct mlx5_ifc_query_regexp_params_in_bits { 4669 u8 opcode[0x10]; 4670 u8 uid[0x10]; 4671 u8 reserved_at_20[0x10]; 4672 u8 op_mod[0x10]; 4673 u8 reserved_at_40[0x18]; 4674 u8 engine_id[0x8]; 4675 u8 reserved[0x20]; 4676 }; 4677 4678 struct mlx5_ifc_query_regexp_params_out_bits { 4679 u8 status[0x8]; 4680 u8 reserved_at_8[0x18]; 4681 u8 syndrome[0x20]; 4682 u8 reserved[0x40]; 4683 struct mlx5_ifc_regexp_params_bits regexp_params; 4684 }; 4685 4686 struct mlx5_ifc_set_regexp_register_in_bits { 4687 u8 opcode[0x10]; 4688 u8 uid[0x10]; 4689 u8 reserved_at_20[0x10]; 4690 u8 op_mod[0x10]; 4691 u8 reserved_at_40[0x18]; 4692 u8 engine_id[0x8]; 4693 u8 register_address[0x20]; 4694 u8 register_data[0x20]; 4695 u8 reserved[0x60]; 4696 }; 4697 4698 struct mlx5_ifc_set_regexp_register_out_bits { 4699 u8 status[0x8]; 4700 u8 reserved_at_8[0x18]; 4701 u8 syndrome[0x20]; 4702 u8 reserved[0x40]; 4703 }; 4704 4705 struct mlx5_ifc_query_regexp_register_in_bits { 4706 u8 opcode[0x10]; 4707 u8 uid[0x10]; 4708 u8 reserved_at_20[0x10]; 4709 u8 op_mod[0x10]; 4710 u8 reserved_at_40[0x18]; 4711 u8 engine_id[0x8]; 4712 u8 register_address[0x20]; 4713 }; 4714 4715 struct mlx5_ifc_query_regexp_register_out_bits { 4716 u8 status[0x8]; 4717 u8 reserved_at_8[0x18]; 4718 u8 syndrome[0x20]; 4719 u8 reserved[0x20]; 4720 u8 register_data[0x20]; 4721 }; 4722 4723 /* Queue counters. */ 4724 struct mlx5_ifc_alloc_q_counter_out_bits { 4725 u8 status[0x8]; 4726 u8 reserved_at_8[0x18]; 4727 u8 syndrome[0x20]; 4728 u8 reserved_at_40[0x18]; 4729 u8 counter_set_id[0x8]; 4730 u8 reserved_at_60[0x20]; 4731 }; 4732 4733 struct mlx5_ifc_alloc_q_counter_in_bits { 4734 u8 opcode[0x10]; 4735 u8 uid[0x10]; 4736 u8 reserved_at_20[0x10]; 4737 u8 op_mod[0x10]; 4738 u8 reserved_at_40[0x40]; 4739 }; 4740 4741 struct mlx5_ifc_query_q_counter_out_bits { 4742 u8 status[0x8]; 4743 u8 reserved_at_8[0x18]; 4744 u8 syndrome[0x20]; 4745 u8 reserved_at_40[0x40]; 4746 u8 rx_write_requests[0x20]; 4747 u8 reserved_at_a0[0x20]; 4748 u8 rx_read_requests[0x20]; 4749 u8 reserved_at_e0[0x20]; 4750 u8 rx_atomic_requests[0x20]; 4751 u8 reserved_at_120[0x20]; 4752 u8 rx_dct_connect[0x20]; 4753 u8 reserved_at_160[0x20]; 4754 u8 out_of_buffer[0x20]; 4755 u8 reserved_at_1a0[0x20]; 4756 u8 out_of_sequence[0x20]; 4757 u8 reserved_at_1e0[0x20]; 4758 u8 duplicate_request[0x20]; 4759 u8 reserved_at_220[0x20]; 4760 u8 rnr_nak_retry_err[0x20]; 4761 u8 reserved_at_260[0x20]; 4762 u8 packet_seq_err[0x20]; 4763 u8 reserved_at_2a0[0x20]; 4764 u8 implied_nak_seq_err[0x20]; 4765 u8 reserved_at_2e0[0x20]; 4766 u8 local_ack_timeout_err[0x20]; 4767 u8 reserved_at_320[0xa0]; 4768 u8 resp_local_length_error[0x20]; 4769 u8 req_local_length_error[0x20]; 4770 u8 resp_local_qp_error[0x20]; 4771 u8 local_operation_error[0x20]; 4772 u8 resp_local_protection[0x20]; 4773 u8 req_local_protection[0x20]; 4774 u8 resp_cqe_error[0x20]; 4775 u8 req_cqe_error[0x20]; 4776 u8 req_mw_binding[0x20]; 4777 u8 req_bad_response[0x20]; 4778 u8 req_remote_invalid_request[0x20]; 4779 u8 resp_remote_invalid_request[0x20]; 4780 u8 req_remote_access_errors[0x20]; 4781 u8 resp_remote_access_errors[0x20]; 4782 u8 req_remote_operation_errors[0x20]; 4783 u8 req_transport_retries_exceeded[0x20]; 4784 u8 cq_overflow[0x20]; 4785 u8 resp_cqe_flush_error[0x20]; 4786 u8 req_cqe_flush_error[0x20]; 4787 u8 reserved_at_620[0x1e0]; 4788 }; 4789 4790 struct mlx5_ifc_query_q_counter_in_bits { 4791 u8 opcode[0x10]; 4792 u8 uid[0x10]; 4793 u8 reserved_at_20[0x10]; 4794 u8 op_mod[0x10]; 4795 u8 reserved_at_40[0x80]; 4796 u8 clear[0x1]; 4797 u8 reserved_at_c1[0x1f]; 4798 u8 reserved_at_e0[0x18]; 4799 u8 counter_set_id[0x8]; 4800 }; 4801 4802 enum { 4803 FS_FT_NIC_RX = 0x0, 4804 FS_FT_NIC_TX = 0x1, 4805 FS_FT_FDB = 0x4, 4806 FS_FT_FDB_RX = 0xa, 4807 FS_FT_FDB_TX = 0xb, 4808 }; 4809 4810 struct mlx5_ifc_flow_table_context_bits { 4811 u8 reformat_en[0x1]; 4812 u8 decap_en[0x1]; 4813 u8 sw_owner[0x1]; 4814 u8 termination_table[0x1]; 4815 u8 table_miss_action[0x4]; 4816 u8 level[0x8]; 4817 u8 rtc_valid[0x1]; 4818 u8 reserved_at_11[0x7]; 4819 u8 log_size[0x8]; 4820 4821 u8 reserved_at_20[0x8]; 4822 u8 table_miss_id[0x18]; 4823 4824 u8 reserved_at_40[0x8]; 4825 u8 lag_master_next_table_id[0x18]; 4826 4827 u8 reserved_at_60[0x60]; 4828 4829 u8 rtc_id_0[0x20]; 4830 4831 u8 rtc_id_1[0x20]; 4832 4833 u8 reserved_at_100[0x40]; 4834 }; 4835 4836 struct mlx5_ifc_create_flow_table_in_bits { 4837 u8 opcode[0x10]; 4838 u8 uid[0x10]; 4839 4840 u8 reserved_at_20[0x10]; 4841 u8 op_mod[0x10]; 4842 4843 u8 other_vport[0x1]; 4844 u8 reserved_at_41[0xf]; 4845 u8 vport_number[0x10]; 4846 4847 u8 reserved_at_60[0x20]; 4848 4849 u8 table_type[0x8]; 4850 u8 reserved_at_88[0x18]; 4851 4852 u8 reserved_at_a0[0x20]; 4853 4854 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4855 }; 4856 4857 struct mlx5_ifc_create_flow_table_out_bits { 4858 u8 status[0x8]; 4859 u8 icm_address_63_40[0x18]; 4860 u8 syndrome[0x20]; 4861 u8 icm_address_39_32[0x8]; 4862 u8 table_id[0x18]; 4863 u8 icm_address_31_0[0x20]; 4864 }; 4865 4866 enum mlx5_flow_destination_type { 4867 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 4868 }; 4869 4870 enum { 4871 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 4872 }; 4873 4874 struct mlx5_ifc_set_fte_out_bits { 4875 u8 status[0x8]; 4876 u8 reserved_at_8[0x18]; 4877 u8 syndrome[0x20]; 4878 u8 reserved_at_40[0x40]; 4879 }; 4880 4881 struct mlx5_ifc_dest_format_bits { 4882 u8 destination_type[0x8]; 4883 u8 destination_id[0x18]; 4884 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 4885 u8 packet_reformat[0x1]; 4886 u8 reserved_at_22[0xe]; 4887 u8 destination_eswitch_owner_vhca_id[0x10]; 4888 }; 4889 4890 struct mlx5_ifc_flow_counter_list_bits { 4891 u8 flow_counter_id[0x20]; 4892 u8 reserved_at_20[0x20]; 4893 }; 4894 4895 union mlx5_ifc_dest_format_flow_counter_list_auto_bits { 4896 struct mlx5_ifc_dest_format_bits dest_format; 4897 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 4898 u8 reserved_at_0[0x40]; 4899 }; 4900 4901 struct mlx5_ifc_flow_context_bits { 4902 u8 reserved_at_00[0x20]; 4903 u8 group_id[0x20]; 4904 u8 reserved_at_40[0x8]; 4905 u8 flow_tag[0x18]; 4906 u8 reserved_at_60[0x10]; 4907 u8 action[0x10]; 4908 u8 extended_destination[0x1]; 4909 u8 reserved_at_81[0x7]; 4910 u8 destination_list_size[0x18]; 4911 u8 reserved_at_a0[0x8]; 4912 u8 flow_counter_list_size[0x18]; 4913 u8 reserved_at_c0[0x1740]; 4914 /* Currently only one destnation */ 4915 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[1]; 4916 }; 4917 4918 struct mlx5_ifc_set_fte_in_bits { 4919 u8 opcode[0x10]; 4920 u8 reserved_at_10[0x10]; 4921 u8 reserved_at_20[0x10]; 4922 u8 op_mod[0x10]; 4923 u8 other_vport[0x1]; 4924 u8 reserved_at_41[0xf]; 4925 u8 vport_number[0x10]; 4926 u8 reserved_at_60[0x20]; 4927 u8 table_type[0x8]; 4928 u8 reserved_at_88[0x18]; 4929 u8 reserved_at_a0[0x8]; 4930 u8 table_id[0x18]; 4931 u8 ignore_flow_level[0x1]; 4932 u8 reserved_at_c1[0x17]; 4933 u8 modify_enable_mask[0x8]; 4934 u8 reserved_at_e0[0x20]; 4935 u8 flow_index[0x20]; 4936 u8 reserved_at_120[0xe0]; 4937 struct mlx5_ifc_flow_context_bits flow_context; 4938 }; 4939 4940 struct mlx5_ifc_create_flow_group_in_bits { 4941 u8 opcode[0x10]; 4942 u8 reserved_at_10[0x10]; 4943 u8 reserved_at_20[0x20]; 4944 u8 other_vport[0x1]; 4945 u8 reserved_at_41[0xf]; 4946 u8 vport_number[0x10]; 4947 u8 reserved_at_60[0x20]; 4948 u8 table_type[0x8]; 4949 u8 reserved_at_88[0x18]; 4950 u8 reserved_at_a0[0x8]; 4951 u8 table_id[0x18]; 4952 u8 reserved_at_c0[0x1f40]; 4953 }; 4954 4955 struct mlx5_ifc_create_flow_group_out_bits { 4956 u8 status[0x8]; 4957 u8 reserved_at_8[0x18]; 4958 u8 syndrome[0x20]; 4959 u8 reserved_at_40[0x8]; 4960 u8 group_id[0x18]; 4961 u8 reserved_at_60[0x20]; 4962 }; 4963 4964 enum { 4965 MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION = 1 << 0, 4966 MLX5_IFC_MODIFY_FLOW_TABLE_RTC_ID = 1 << 1, 4967 }; 4968 4969 enum { 4970 MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_DEFAULT = 0, 4971 MLX5_IFC_MODIFY_FLOW_TABLE_MISS_ACTION_GOTO_TBL = 1, 4972 }; 4973 4974 struct mlx5_ifc_modify_flow_table_in_bits { 4975 u8 opcode[0x10]; 4976 u8 uid[0x10]; 4977 4978 u8 reserved_at_20[0x10]; 4979 u8 op_mod[0x10]; 4980 4981 u8 reserved_at_40[0x10]; 4982 u8 vport_number[0x10]; 4983 4984 u8 reserved_at_60[0x10]; 4985 u8 modify_field_select[0x10]; 4986 4987 u8 table_type[0x8]; 4988 u8 reserved_at_88[0x18]; 4989 4990 u8 reserved_at_a0[0x8]; 4991 u8 table_id[0x18]; 4992 4993 struct mlx5_ifc_flow_table_context_bits flow_table_context; 4994 }; 4995 4996 struct mlx5_ifc_modify_flow_table_out_bits { 4997 u8 status[0x8]; 4998 u8 reserved_at_8[0x18]; 4999 5000 u8 syndrome[0x20]; 5001 5002 u8 reserved_at_40[0x60]; 5003 }; 5004 5005 /* CQE format mask. */ 5006 #define MLX5E_CQE_FORMAT_MASK 0xc 5007 5008 /* MPW opcode. */ 5009 #define MLX5_OPC_MOD_MPW 0x01 5010 5011 /* Compressed Rx CQE structure. */ 5012 struct mlx5_mini_cqe8 { 5013 union { 5014 uint32_t rx_hash_result; 5015 struct { 5016 union { 5017 uint16_t checksum; 5018 uint16_t flow_tag_high; 5019 struct { 5020 uint8_t reserved; 5021 uint8_t hdr_type; 5022 }; 5023 }; 5024 uint16_t stride_idx; 5025 }; 5026 struct { 5027 uint16_t wqe_counter; 5028 uint8_t s_wqe_opcode; 5029 uint8_t reserved; 5030 } s_wqe_info; 5031 }; 5032 union { 5033 uint32_t byte_cnt_flow; 5034 uint32_t byte_cnt; 5035 }; 5036 }; 5037 5038 /* Mini CQE responder format. */ 5039 enum { 5040 MLX5_CQE_RESP_FORMAT_HASH = 0x0, 5041 MLX5_CQE_RESP_FORMAT_CSUM = 0x1, 5042 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2, 5043 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3, 5044 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4, 5045 }; 5046 5047 /* srTCM PRM flow meter parameters. */ 5048 enum { 5049 MLX5_FLOW_COLOR_RED = 0, 5050 MLX5_FLOW_COLOR_YELLOW, 5051 MLX5_FLOW_COLOR_GREEN, 5052 MLX5_FLOW_COLOR_UNDEFINED, 5053 }; 5054 5055 /* Maximum value of srTCM & trTCM metering parameters. */ 5056 #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F)) 5057 #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF) 5058 5059 /* The bits meter color use. */ 5060 #define MLX5_MTR_COLOR_BITS 8 5061 5062 /* The bit size of one register. */ 5063 #define MLX5_REG_BITS 32 5064 5065 /* Idle bits for non-color usage in color register. */ 5066 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS) 5067 5068 /* Length mode of dynamic flex parser graph node. */ 5069 enum mlx5_parse_graph_node_len_mode { 5070 MLX5_GRAPH_NODE_LEN_FIXED = 0x0, 5071 MLX5_GRAPH_NODE_LEN_FIELD = 0x1, 5072 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2, 5073 }; 5074 5075 /* Offset mode of the samples of flex parser. */ 5076 enum mlx5_parse_graph_flow_match_sample_offset_mode { 5077 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0, 5078 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1, 5079 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, 5080 }; 5081 5082 enum mlx5_parse_graph_flow_match_sample_tunnel_mode { 5083 MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0, 5084 MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1, 5085 MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2 5086 }; 5087 5088 /* Node index for an input / output arc of the flex parser graph. */ 5089 enum mlx5_parse_graph_arc_node_index { 5090 MLX5_GRAPH_ARC_NODE_NULL = 0x0, 5091 MLX5_GRAPH_ARC_NODE_HEAD = 0x1, 5092 MLX5_GRAPH_ARC_NODE_MAC = 0x2, 5093 MLX5_GRAPH_ARC_NODE_IP = 0x3, 5094 MLX5_GRAPH_ARC_NODE_GRE = 0x4, 5095 MLX5_GRAPH_ARC_NODE_UDP = 0x5, 5096 MLX5_GRAPH_ARC_NODE_MPLS = 0x6, 5097 MLX5_GRAPH_ARC_NODE_TCP = 0x7, 5098 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, 5099 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, 5100 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, 5101 MLX5_GRAPH_ARC_NODE_IPV4 = 0xb, 5102 MLX5_GRAPH_ARC_NODE_IPV6 = 0xc, 5103 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, 5104 }; 5105 5106 #define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8 5107 #define MLX5_PARSE_GRAPH_IN_ARC_MAX 8 5108 #define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8 5109 5110 /** 5111 * Convert a user mark to flow mark. 5112 * 5113 * @param val 5114 * Mark value to convert. 5115 * 5116 * @return 5117 * Converted mark value. 5118 */ 5119 static inline uint32_t 5120 mlx5_flow_mark_set(uint32_t val) 5121 { 5122 uint32_t ret; 5123 5124 /* 5125 * Add one to the user value to differentiate un-marked flows from 5126 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it 5127 * remains untouched. 5128 */ 5129 if (val != MLX5_FLOW_MARK_DEFAULT) 5130 ++val; 5131 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 5132 /* 5133 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit 5134 * word, byte-swapped by the kernel on little-endian systems. In this 5135 * case, left-shifting the resulting big-endian value ensures the 5136 * least significant 24 bits are retained when converting it back. 5137 */ 5138 ret = rte_cpu_to_be_32(val) >> 8; 5139 #else 5140 ret = val; 5141 #endif 5142 return ret; 5143 } 5144 5145 /** 5146 * Convert a mark to user mark. 5147 * 5148 * @param val 5149 * Mark value to convert. 5150 * 5151 * @return 5152 * Converted mark value. 5153 */ 5154 static inline uint32_t 5155 mlx5_flow_mark_get(uint32_t val) 5156 { 5157 /* 5158 * Subtract one from the retrieved value. It was added by 5159 * mlx5_flow_mark_set() to distinguish unmarked flows. 5160 */ 5161 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 5162 return (val >> 8) - 1; 5163 #else 5164 return val - 1; 5165 #endif 5166 } 5167 5168 /** 5169 * Convert a timestamp format to configure settings in the queue context. 5170 * 5171 * @param val 5172 * timestamp format supported by the queue. 5173 * 5174 * @return 5175 * Converted timestamp format settings. 5176 */ 5177 static inline uint32_t 5178 mlx5_ts_format_conv(uint32_t ts_format) 5179 { 5180 return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ? 5181 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : 5182 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; 5183 } 5184 5185 #endif /* RTE_PMD_MLX5_PRM_H_ */ 5186