1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_PRM_H_ 7 #define RTE_PMD_MLX5_PRM_H_ 8 9 #include <unistd.h> 10 11 #include <rte_vect.h> 12 #include <rte_byteorder.h> 13 14 #include <mlx5_glue.h> 15 #include "mlx5_autoconf.h" 16 17 /* RSS hash key size. */ 18 #define MLX5_RSS_HASH_KEY_LEN 40 19 20 /* Get CQE owner bit. */ 21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK) 22 23 /* Get CQE format. */ 24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2) 25 26 /* Get CQE opcode. */ 27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4) 28 29 /* Get CQE solicited event. */ 30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1) 31 32 /* Invalidate a CQE. */ 33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4) 34 35 /* Hardware index widths. */ 36 #define MLX5_CQ_INDEX_WIDTH 24 37 #define MLX5_WQ_INDEX_WIDTH 16 38 39 /* WQE Segment sizes in bytes. */ 40 #define MLX5_WSEG_SIZE 16u 41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg) 42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg) 43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg) 44 45 /* WQE/WQEBB size in bytes. */ 46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe) 47 48 /* 49 * Max size of a WQE session. 50 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments, 51 * the WQE size field in Control Segment is 6 bits wide. 52 */ 53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE) 54 55 /* 56 * Default minimum number of Tx queues for inlining packets. 57 * If there are less queues as specified we assume we have 58 * no enough CPU resources (cycles) to perform inlining, 59 * the PCIe throughput is not supposed as bottleneck and 60 * inlining is disabled. 61 */ 62 #define MLX5_INLINE_MAX_TXQS 8u 63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u 64 65 /* 66 * Default packet length threshold to be inlined with 67 * enhanced MPW. If packet length exceeds the threshold 68 * the data are not inlined. Should be aligned in WQEBB 69 * boundary with accounting the title Control and Ethernet 70 * segments. 71 */ 72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \ 73 MLX5_DSEG_MIN_INLINE_SIZE) 74 /* 75 * Maximal inline data length sent with enhanced MPW. 76 * Is based on maximal WQE size. 77 */ 78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 79 MLX5_WQE_CSEG_SIZE - \ 80 MLX5_WQE_ESEG_SIZE - \ 81 MLX5_WQE_DSEG_SIZE + \ 82 MLX5_DSEG_MIN_INLINE_SIZE) 83 /* 84 * Minimal amount of packets to be sent with EMPW. 85 * This limits the minimal required size of sent EMPW. 86 * If there are no enough resources to built minimal 87 * EMPW the sending loop exits. 88 */ 89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u) 90 /* 91 * Maximal amount of packets to be sent with EMPW. 92 * This value is not recommended to exceed MLX5_TX_COMP_THRESH, 93 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs 94 * without CQE generation request, being multiplied by 95 * MLX5_TX_COMP_MAX_CQE it may cause significant latency 96 * in tx burst routine at the moment of freeing multiple mbufs. 97 */ 98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH 99 #define MLX5_MPW_MAX_PACKETS 6 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6 101 102 /* 103 * Default packet length threshold to be inlined with 104 * ordinary SEND. Inlining saves the MR key search 105 * and extra PCIe data fetch transaction, but eats the 106 * CPU cycles. 107 */ 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \ 109 MLX5_ESEG_MIN_INLINE_SIZE - \ 110 MLX5_WQE_CSEG_SIZE - \ 111 MLX5_WQE_ESEG_SIZE - \ 112 MLX5_WQE_DSEG_SIZE) 113 /* 114 * Maximal inline data length sent with ordinary SEND. 115 * Is based on maximal WQE size. 116 */ 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 118 MLX5_WQE_CSEG_SIZE - \ 119 MLX5_WQE_ESEG_SIZE - \ 120 MLX5_WQE_DSEG_SIZE + \ 121 MLX5_ESEG_MIN_INLINE_SIZE) 122 123 /* Missed in mlx5dv.h, should define here. */ 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u 126 #endif 127 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN 129 #define MLX5_OPCODE_SEND_EN 0x17u 130 #endif 131 132 #ifndef HAVE_MLX5_OPCODE_WAIT 133 #define MLX5_OPCODE_WAIT 0x0fu 134 #endif 135 136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO 137 #define MLX5_OPCODE_ACCESS_ASO 0x2du 138 #endif 139 140 /* CQE value to inform that VLAN is stripped. */ 141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0) 142 143 /* IPv4 options. */ 144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1) 145 146 /* IPv6 packet. */ 147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2) 148 149 /* IPv4 packet. */ 150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3) 151 152 /* TCP packet. */ 153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4) 154 155 /* UDP packet. */ 156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5) 157 158 /* IP is fragmented. */ 159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7) 160 161 /* L2 header is valid. */ 162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8) 163 164 /* L3 header is valid. */ 165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9) 166 167 /* L4 header is valid. */ 168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10) 169 170 /* Outer packet, 0 IPv4, 1 IPv6. */ 171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1) 172 173 /* Tunnel packet bit in the CQE. */ 174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0) 175 176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */ 177 #define MLX5_CQE_LRO_PUSH_MASK 0x40 178 179 /* Mask for L4 type in the CQE hdr_type_etc field. */ 180 #define MLX5_CQE_L4_TYPE_MASK 0x70 181 182 /* The bit index of L4 type in CQE hdr_type_etc field. */ 183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4 184 185 /* L4 type to indicate TCP packet without acknowledgment. */ 186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3 187 188 /* L4 type to indicate TCP packet with acknowledgment. */ 189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4 190 191 /* Inner L3 checksum offload (Tunneled packets only). */ 192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4) 193 194 /* Inner L4 checksum offload (Tunneled packets only). */ 195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5) 196 197 /* Outer L4 type is TCP. */ 198 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5) 199 200 /* Outer L4 type is UDP. */ 201 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5) 202 203 /* Outer L3 type is IPV4. */ 204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4) 205 206 /* Outer L3 type is IPV6. */ 207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4) 208 209 /* Inner L4 type is TCP. */ 210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1) 211 212 /* Inner L4 type is UDP. */ 213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1) 214 215 /* Inner L3 type is IPV4. */ 216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0) 217 218 /* Inner L3 type is IPV6. */ 219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0) 220 221 /* VLAN insertion flag. */ 222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31) 223 224 /* Data inline segment flag. */ 225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31) 226 227 /* Is flow mark valid. */ 228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00) 230 #else 231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff) 232 #endif 233 234 /* INVALID is used by packets matching no flow rules. */ 235 #define MLX5_FLOW_MARK_INVALID 0 236 237 /* Maximum allowed value to mark a packet. */ 238 #define MLX5_FLOW_MARK_MAX 0xfffff0 239 240 /* Default mark value used when none is provided. */ 241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff 242 243 /* Default mark mask for metadata legacy mode. */ 244 #define MLX5_FLOW_MARK_MASK 0xffffff 245 246 /* Byte length mask when mark is enable in miniCQE */ 247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00 248 249 /* Maximum number of DS in WQE. Limited by 6-bit field. */ 250 #define MLX5_DSEG_MAX 63 251 252 /* The completion mode offset in the WQE control segment line 2. */ 253 #define MLX5_COMP_MODE_OFFSET 2 254 255 /* Amount of data bytes in minimal inline data segment. */ 256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u 257 258 /* Amount of data bytes in minimal inline eth segment. */ 259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u 260 261 /* Amount of data bytes after eth data segment. */ 262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u 263 264 /* The maximum log value of segments per RQ WQE. */ 265 #define MLX5_MAX_LOG_RQ_SEGS 5u 266 267 /* The alignment needed for WQ buffer. */ 268 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size() 269 270 /* The alignment needed for CQ buffer. */ 271 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size() 272 273 /* Completion mode. */ 274 enum mlx5_completion_mode { 275 MLX5_COMP_ONLY_ERR = 0x0, 276 MLX5_COMP_ONLY_FIRST_ERR = 0x1, 277 MLX5_COMP_ALWAYS = 0x2, 278 MLX5_COMP_CQE_AND_EQE = 0x3, 279 }; 280 281 /* MPW mode. */ 282 enum mlx5_mpw_mode { 283 MLX5_MPW_DISABLED, 284 MLX5_MPW, 285 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */ 286 }; 287 288 /* WQE Control segment. */ 289 struct mlx5_wqe_cseg { 290 uint32_t opcode; 291 uint32_t sq_ds; 292 uint32_t flags; 293 uint32_t misc; 294 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE); 295 296 /* 297 * WQE CSEG opcode field size is 32 bits, divided: 298 * Bits 31:24 OPC_MOD 299 * Bits 23:8 wqe_index 300 * Bits 7:0 OPCODE 301 */ 302 #define WQE_CSEG_OPC_MOD_OFFSET 24 303 #define WQE_CSEG_WQE_INDEX_OFFSET 8 304 305 /* Header of data segment. Minimal size Data Segment */ 306 struct mlx5_wqe_dseg { 307 uint32_t bcount; 308 union { 309 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE]; 310 struct { 311 uint32_t lkey; 312 uint64_t pbuf; 313 } __rte_packed; 314 }; 315 } __rte_packed; 316 317 /* Subset of struct WQE Ethernet Segment. */ 318 struct mlx5_wqe_eseg { 319 union { 320 struct { 321 uint32_t swp_offs; 322 uint8_t cs_flags; 323 uint8_t swp_flags; 324 uint16_t mss; 325 uint32_t metadata; 326 uint16_t inline_hdr_sz; 327 union { 328 uint16_t inline_data; 329 uint16_t vlan_tag; 330 }; 331 } __rte_packed; 332 struct { 333 uint32_t offsets; 334 uint32_t flags; 335 uint32_t flow_metadata; 336 uint32_t inline_hdr; 337 } __rte_packed; 338 }; 339 } __rte_packed; 340 341 struct mlx5_wqe_qseg { 342 uint32_t reserved0; 343 uint32_t reserved1; 344 uint32_t max_index; 345 uint32_t qpn_cqn; 346 } __rte_packed; 347 348 /* The title WQEBB, header of WQE. */ 349 struct mlx5_wqe { 350 union { 351 struct mlx5_wqe_cseg cseg; 352 uint32_t ctrl[4]; 353 }; 354 struct mlx5_wqe_eseg eseg; 355 union { 356 struct mlx5_wqe_dseg dseg[2]; 357 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE]; 358 }; 359 } __rte_packed; 360 361 /* WQE for Multi-Packet RQ. */ 362 struct mlx5_wqe_mprq { 363 struct mlx5_wqe_srq_next_seg next_seg; 364 struct mlx5_wqe_data_seg dseg; 365 }; 366 367 #define MLX5_MPRQ_LEN_MASK 0x000ffff 368 #define MLX5_MPRQ_LEN_SHIFT 0 369 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000 370 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16 371 #define MLX5_MPRQ_FILLER_MASK 0x80000000 372 #define MLX5_MPRQ_FILLER_SHIFT 31 373 374 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2 375 376 /* CQ element structure - should be equal to the cache line size */ 377 struct mlx5_cqe { 378 #if (RTE_CACHE_LINE_SIZE == 128) 379 uint8_t padding[64]; 380 #endif 381 uint8_t pkt_info; 382 uint8_t rsvd0; 383 uint16_t wqe_id; 384 uint8_t lro_tcppsh_abort_dupack; 385 uint8_t lro_min_ttl; 386 uint16_t lro_tcp_win; 387 uint32_t lro_ack_seq_num; 388 uint32_t rx_hash_res; 389 uint8_t rx_hash_type; 390 uint8_t rsvd1[3]; 391 uint16_t csum; 392 uint8_t rsvd2[6]; 393 uint16_t hdr_type_etc; 394 uint16_t vlan_info; 395 uint8_t lro_num_seg; 396 union { 397 uint8_t user_index_bytes[3]; 398 struct { 399 uint8_t user_index_hi; 400 uint16_t user_index_low; 401 } __rte_packed; 402 }; 403 uint32_t flow_table_metadata; 404 uint8_t rsvd4[4]; 405 uint32_t byte_cnt; 406 uint64_t timestamp; 407 uint32_t sop_drop_qpn; 408 uint16_t wqe_counter; 409 uint8_t rsvd5; 410 uint8_t op_own; 411 }; 412 413 struct mlx5_cqe_ts { 414 uint64_t timestamp; 415 uint32_t sop_drop_qpn; 416 uint16_t wqe_counter; 417 uint8_t rsvd5; 418 uint8_t op_own; 419 }; 420 421 struct mlx5_wqe_rseg { 422 uint64_t raddr; 423 uint32_t rkey; 424 uint32_t reserved; 425 } __rte_packed; 426 427 #define MLX5_UMRC_IF_OFFSET 31u 428 #define MLX5_UMRC_KO_OFFSET 16u 429 #define MLX5_UMRC_TO_BS_OFFSET 0u 430 431 struct mlx5_wqe_umr_cseg { 432 uint32_t if_cf_toe_cq_res; 433 uint32_t ko_to_bs; 434 uint64_t mkey_mask; 435 uint32_t rsvd1[8]; 436 } __rte_packed; 437 438 struct mlx5_wqe_mkey_cseg { 439 uint32_t fr_res_af_sf; 440 uint32_t qpn_mkey; 441 uint32_t reserved2; 442 uint32_t flags_pd; 443 uint64_t start_addr; 444 uint64_t len; 445 uint32_t bsf_octword_size; 446 uint32_t reserved3[4]; 447 uint32_t translations_octword_size; 448 uint32_t res4_lps; 449 uint32_t reserved; 450 } __rte_packed; 451 452 enum { 453 MLX5_BSF_SIZE_16B = 0x0, 454 MLX5_BSF_SIZE_32B = 0x1, 455 MLX5_BSF_SIZE_64B = 0x2, 456 MLX5_BSF_SIZE_128B = 0x3, 457 }; 458 459 enum { 460 MLX5_BSF_P_TYPE_SIGNATURE = 0x0, 461 MLX5_BSF_P_TYPE_CRYPTO = 0x1, 462 }; 463 464 enum { 465 MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, 466 MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, 467 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, 468 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, 469 }; 470 471 enum { 472 MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, 473 }; 474 475 enum { 476 MLX5_BLOCK_SIZE_512B = 0x1, 477 MLX5_BLOCK_SIZE_520B = 0x2, 478 MLX5_BLOCK_SIZE_4096B = 0x3, 479 MLX5_BLOCK_SIZE_4160B = 0x4, 480 MLX5_BLOCK_SIZE_1MB = 0x5, 481 MLX5_BLOCK_SIZE_4048B = 0x6, 482 }; 483 484 #define MLX5_BSF_SIZE_OFFSET 30 485 #define MLX5_BSF_P_TYPE_OFFSET 24 486 #define MLX5_ENCRYPTION_ORDER_OFFSET 16 487 #define MLX5_BLOCK_SIZE_OFFSET 24 488 489 struct mlx5_wqe_umr_bsf_seg { 490 /* 491 * bs_bpt_eo_es contains: 492 * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET 493 * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET 494 * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET 495 * es encryption_standard 4 bits at offset 0 496 */ 497 uint32_t bs_bpt_eo_es; 498 uint32_t raw_data_size; 499 /* 500 * bsp_res contains: 501 * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET 502 * res reserved 24 bits 503 */ 504 uint32_t bsp_res; 505 uint32_t reserved0; 506 uint8_t xts_initial_tweak[16]; 507 /* 508 * res_dp contains: 509 * res reserved 8 bits 510 * dp dek_pointer 24 bits at offset 0 511 */ 512 uint32_t res_dp; 513 uint32_t reserved1; 514 uint64_t keytag; 515 uint32_t reserved2[4]; 516 } __rte_packed; 517 518 #ifdef PEDANTIC 519 #pragma GCC diagnostic ignored "-Wpedantic" 520 #endif 521 522 struct mlx5_umr_wqe { 523 struct mlx5_wqe_cseg ctr; 524 struct mlx5_wqe_umr_cseg ucseg; 525 struct mlx5_wqe_mkey_cseg mkc; 526 union { 527 struct mlx5_wqe_dseg kseg[0]; 528 struct mlx5_wqe_umr_bsf_seg bsf[0]; 529 }; 530 } __rte_packed; 531 532 struct mlx5_rdma_write_wqe { 533 struct mlx5_wqe_cseg ctr; 534 struct mlx5_wqe_rseg rseg; 535 struct mlx5_wqe_dseg dseg[0]; 536 } __rte_packed; 537 538 #ifdef PEDANTIC 539 #pragma GCC diagnostic error "-Wpedantic" 540 #endif 541 542 /* GGA */ 543 /* MMO metadata segment */ 544 545 #define MLX5_OPCODE_MMO 0x2fu 546 #define MLX5_OPC_MOD_MMO_REGEX 0x4u 547 #define MLX5_OPC_MOD_MMO_COMP 0x2u 548 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u 549 #define MLX5_OPC_MOD_MMO_DMA 0x1u 550 551 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u 552 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u 553 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u 554 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u 555 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) 556 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u 557 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u 558 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u 559 560 struct mlx5_wqe_metadata_seg { 561 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */ 562 uint32_t lkey; 563 uint64_t addr; 564 }; 565 566 struct mlx5_gga_wqe { 567 uint32_t opcode; 568 uint32_t sq_ds; 569 uint32_t flags; 570 uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */ 571 uint32_t gga_ctrl2; 572 uint32_t opaque_lkey; 573 uint64_t opaque_vaddr; 574 struct mlx5_wqe_dseg gather; 575 struct mlx5_wqe_dseg scatter; 576 } __rte_packed; 577 578 struct mlx5_gga_compress_opaque { 579 uint32_t syndrom; 580 uint32_t reserved0; 581 uint32_t scattered_length; 582 uint32_t gathered_length; 583 uint64_t scatter_crc; 584 uint64_t gather_crc; 585 uint32_t crc32; 586 uint32_t adler32; 587 uint8_t reserved1[216]; 588 } __rte_packed; 589 590 struct mlx5_ifc_regexp_mmo_control_bits { 591 uint8_t reserved_at_31[0x2]; 592 uint8_t le[0x1]; 593 uint8_t reserved_at_28[0x1]; 594 uint8_t subset_id_0[0xc]; 595 uint8_t reserved_at_16[0x4]; 596 uint8_t subset_id_1[0xc]; 597 uint8_t ctrl[0x4]; 598 uint8_t subset_id_2[0xc]; 599 uint8_t reserved_at_16_1[0x4]; 600 uint8_t subset_id_3[0xc]; 601 }; 602 603 struct mlx5_ifc_regexp_metadata_bits { 604 uint8_t rof_version[0x10]; 605 uint8_t latency_count[0x10]; 606 uint8_t instruction_count[0x10]; 607 uint8_t primary_thread_count[0x10]; 608 uint8_t match_count[0x8]; 609 uint8_t detected_match_count[0x8]; 610 uint8_t status[0x10]; 611 uint8_t job_id[0x20]; 612 uint8_t reserved[0x80]; 613 }; 614 615 struct mlx5_ifc_regexp_match_tuple_bits { 616 uint8_t length[0x10]; 617 uint8_t start_ptr[0x10]; 618 uint8_t rule_id[0x20]; 619 }; 620 621 /* Adding direct verbs to data-path. */ 622 623 /* CQ sequence number mask. */ 624 #define MLX5_CQ_SQN_MASK 0x3 625 626 /* CQ sequence number index. */ 627 #define MLX5_CQ_SQN_OFFSET 28 628 629 /* CQ doorbell index mask. */ 630 #define MLX5_CI_MASK 0xffffff 631 632 /* CQ doorbell offset. */ 633 #define MLX5_CQ_ARM_DB 1 634 635 /* CQ doorbell offset*/ 636 #define MLX5_CQ_DOORBELL 0x20 637 638 /* CQE format value. */ 639 #define MLX5_COMPRESSED 0x3 640 641 /* CQ doorbell cmd types. */ 642 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24) 643 #define MLX5_CQ_DBR_CMD_ALL (0 << 24) 644 645 /* Action type of header modification. */ 646 enum { 647 MLX5_MODIFICATION_TYPE_SET = 0x1, 648 MLX5_MODIFICATION_TYPE_ADD = 0x2, 649 MLX5_MODIFICATION_TYPE_COPY = 0x3, 650 }; 651 652 /* The field of packet to be modified. */ 653 enum mlx5_modification_field { 654 MLX5_MODI_OUT_NONE = -1, 655 MLX5_MODI_OUT_SMAC_47_16 = 1, 656 MLX5_MODI_OUT_SMAC_15_0, 657 MLX5_MODI_OUT_ETHERTYPE, 658 MLX5_MODI_OUT_DMAC_47_16, 659 MLX5_MODI_OUT_DMAC_15_0, 660 MLX5_MODI_OUT_IP_DSCP, 661 MLX5_MODI_OUT_TCP_FLAGS, 662 MLX5_MODI_OUT_TCP_SPORT, 663 MLX5_MODI_OUT_TCP_DPORT, 664 MLX5_MODI_OUT_IPV4_TTL, 665 MLX5_MODI_OUT_UDP_SPORT, 666 MLX5_MODI_OUT_UDP_DPORT, 667 MLX5_MODI_OUT_SIPV6_127_96, 668 MLX5_MODI_OUT_SIPV6_95_64, 669 MLX5_MODI_OUT_SIPV6_63_32, 670 MLX5_MODI_OUT_SIPV6_31_0, 671 MLX5_MODI_OUT_DIPV6_127_96, 672 MLX5_MODI_OUT_DIPV6_95_64, 673 MLX5_MODI_OUT_DIPV6_63_32, 674 MLX5_MODI_OUT_DIPV6_31_0, 675 MLX5_MODI_OUT_SIPV4, 676 MLX5_MODI_OUT_DIPV4, 677 MLX5_MODI_OUT_FIRST_VID, 678 MLX5_MODI_IN_SMAC_47_16 = 0x31, 679 MLX5_MODI_IN_SMAC_15_0, 680 MLX5_MODI_IN_ETHERTYPE, 681 MLX5_MODI_IN_DMAC_47_16, 682 MLX5_MODI_IN_DMAC_15_0, 683 MLX5_MODI_IN_IP_DSCP, 684 MLX5_MODI_IN_TCP_FLAGS, 685 MLX5_MODI_IN_TCP_SPORT, 686 MLX5_MODI_IN_TCP_DPORT, 687 MLX5_MODI_IN_IPV4_TTL, 688 MLX5_MODI_IN_UDP_SPORT, 689 MLX5_MODI_IN_UDP_DPORT, 690 MLX5_MODI_IN_SIPV6_127_96, 691 MLX5_MODI_IN_SIPV6_95_64, 692 MLX5_MODI_IN_SIPV6_63_32, 693 MLX5_MODI_IN_SIPV6_31_0, 694 MLX5_MODI_IN_DIPV6_127_96, 695 MLX5_MODI_IN_DIPV6_95_64, 696 MLX5_MODI_IN_DIPV6_63_32, 697 MLX5_MODI_IN_DIPV6_31_0, 698 MLX5_MODI_IN_SIPV4, 699 MLX5_MODI_IN_DIPV4, 700 MLX5_MODI_OUT_IPV6_HOPLIMIT, 701 MLX5_MODI_IN_IPV6_HOPLIMIT, 702 MLX5_MODI_META_DATA_REG_A, 703 MLX5_MODI_META_DATA_REG_B = 0x50, 704 MLX5_MODI_META_REG_C_0, 705 MLX5_MODI_META_REG_C_1, 706 MLX5_MODI_META_REG_C_2, 707 MLX5_MODI_META_REG_C_3, 708 MLX5_MODI_META_REG_C_4, 709 MLX5_MODI_META_REG_C_5, 710 MLX5_MODI_META_REG_C_6, 711 MLX5_MODI_META_REG_C_7, 712 MLX5_MODI_OUT_TCP_SEQ_NUM, 713 MLX5_MODI_IN_TCP_SEQ_NUM, 714 MLX5_MODI_OUT_TCP_ACK_NUM, 715 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C, 716 MLX5_MODI_GTP_TEID = 0x6E, 717 }; 718 719 /* Total number of metadata reg_c's. */ 720 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1) 721 722 enum modify_reg { 723 REG_NON = 0, 724 REG_A, 725 REG_B, 726 REG_C_0, 727 REG_C_1, 728 REG_C_2, 729 REG_C_3, 730 REG_C_4, 731 REG_C_5, 732 REG_C_6, 733 REG_C_7, 734 }; 735 736 /* Modification sub command. */ 737 struct mlx5_modification_cmd { 738 union { 739 uint32_t data0; 740 struct { 741 unsigned int length:5; 742 unsigned int rsvd0:3; 743 unsigned int offset:5; 744 unsigned int rsvd1:3; 745 unsigned int field:12; 746 unsigned int action_type:4; 747 }; 748 }; 749 union { 750 uint32_t data1; 751 uint8_t data[4]; 752 struct { 753 unsigned int rsvd2:8; 754 unsigned int dst_offset:5; 755 unsigned int rsvd3:3; 756 unsigned int dst_field:12; 757 unsigned int rsvd4:4; 758 }; 759 }; 760 }; 761 762 typedef uint64_t u64; 763 typedef uint32_t u32; 764 typedef uint16_t u16; 765 typedef uint8_t u8; 766 767 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 768 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 769 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \ 770 (&(__mlx5_nullp(typ)->fld))) 771 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \ 772 (__mlx5_bit_off(typ, fld) & 0x1f)) 773 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 774 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 775 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \ 776 __mlx5_dw_bit_off(typ, fld)) 777 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 778 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 779 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \ 780 (__mlx5_bit_off(typ, fld) & 0xf)) 781 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 782 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \ 783 __mlx5_16_bit_off(typ, fld)) 784 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 785 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 786 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 787 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 788 789 /* insert a value to a struct */ 790 #define MLX5_SET(typ, p, fld, v) \ 791 do { \ 792 u32 _v = v; \ 793 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \ 794 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \ 795 __mlx5_dw_off(typ, fld))) & \ 796 (~__mlx5_dw_mask(typ, fld))) | \ 797 (((_v) & __mlx5_mask(typ, fld)) << \ 798 __mlx5_dw_bit_off(typ, fld))); \ 799 } while (0) 800 801 #define MLX5_SET64(typ, p, fld, v) \ 802 do { \ 803 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \ 804 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \ 805 rte_cpu_to_be_64(v); \ 806 } while (0) 807 808 #define MLX5_SET16(typ, p, fld, v) \ 809 do { \ 810 u16 _v = v; \ 811 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \ 812 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 813 __mlx5_16_off(typ, fld))) & \ 814 (~__mlx5_16_mask(typ, fld))) | \ 815 (((_v) & __mlx5_mask16(typ, fld)) << \ 816 __mlx5_16_bit_off(typ, fld))); \ 817 } while (0) 818 819 #define MLX5_GET_VOLATILE(typ, p, fld) \ 820 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\ 821 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 822 __mlx5_mask(typ, fld)) 823 #define MLX5_GET(typ, p, fld) \ 824 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\ 825 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 826 __mlx5_mask(typ, fld)) 827 #define MLX5_GET16(typ, p, fld) \ 828 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 829 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 830 __mlx5_mask16(typ, fld)) 831 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \ 832 __mlx5_64_off(typ, fld))) 833 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 834 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 835 836 struct mlx5_ifc_fte_match_set_misc_bits { 837 u8 gre_c_present[0x1]; 838 u8 reserved_at_1[0x1]; 839 u8 gre_k_present[0x1]; 840 u8 gre_s_present[0x1]; 841 u8 source_vhci_port[0x4]; 842 u8 source_sqn[0x18]; 843 u8 reserved_at_20[0x10]; 844 u8 source_port[0x10]; 845 u8 outer_second_prio[0x3]; 846 u8 outer_second_cfi[0x1]; 847 u8 outer_second_vid[0xc]; 848 u8 inner_second_prio[0x3]; 849 u8 inner_second_cfi[0x1]; 850 u8 inner_second_vid[0xc]; 851 u8 outer_second_cvlan_tag[0x1]; 852 u8 inner_second_cvlan_tag[0x1]; 853 u8 outer_second_svlan_tag[0x1]; 854 u8 inner_second_svlan_tag[0x1]; 855 u8 reserved_at_64[0xc]; 856 u8 gre_protocol[0x10]; 857 u8 gre_key_h[0x18]; 858 u8 gre_key_l[0x8]; 859 u8 vxlan_vni[0x18]; 860 u8 reserved_at_b8[0x8]; 861 u8 geneve_vni[0x18]; 862 u8 reserved_at_e4[0x6]; 863 u8 geneve_tlv_option_0_exist[0x1]; 864 u8 geneve_oam[0x1]; 865 u8 reserved_at_e0[0xc]; 866 u8 outer_ipv6_flow_label[0x14]; 867 u8 reserved_at_100[0xc]; 868 u8 inner_ipv6_flow_label[0x14]; 869 u8 reserved_at_120[0xa]; 870 u8 geneve_opt_len[0x6]; 871 u8 geneve_protocol_type[0x10]; 872 u8 reserved_at_140[0xc0]; 873 }; 874 875 struct mlx5_ifc_ipv4_layout_bits { 876 u8 reserved_at_0[0x60]; 877 u8 ipv4[0x20]; 878 }; 879 880 struct mlx5_ifc_ipv6_layout_bits { 881 u8 ipv6[16][0x8]; 882 }; 883 884 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 885 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 886 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 887 u8 reserved_at_0[0x80]; 888 }; 889 890 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 891 u8 smac_47_16[0x20]; 892 u8 smac_15_0[0x10]; 893 u8 ethertype[0x10]; 894 u8 dmac_47_16[0x20]; 895 u8 dmac_15_0[0x10]; 896 u8 first_prio[0x3]; 897 u8 first_cfi[0x1]; 898 u8 first_vid[0xc]; 899 u8 ip_protocol[0x8]; 900 u8 ip_dscp[0x6]; 901 u8 ip_ecn[0x2]; 902 u8 cvlan_tag[0x1]; 903 u8 svlan_tag[0x1]; 904 u8 frag[0x1]; 905 u8 ip_version[0x4]; 906 u8 tcp_flags[0x9]; 907 u8 tcp_sport[0x10]; 908 u8 tcp_dport[0x10]; 909 u8 reserved_at_c0[0x10]; 910 u8 ipv4_ihl[0x4]; 911 u8 l3_ok[0x1]; 912 u8 l4_ok[0x1]; 913 u8 ipv4_checksum_ok[0x1]; 914 u8 l4_checksum_ok[0x1]; 915 u8 ip_ttl_hoplimit[0x8]; 916 u8 udp_sport[0x10]; 917 u8 udp_dport[0x10]; 918 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 919 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 920 }; 921 922 struct mlx5_ifc_fte_match_mpls_bits { 923 u8 mpls_label[0x14]; 924 u8 mpls_exp[0x3]; 925 u8 mpls_s_bos[0x1]; 926 u8 mpls_ttl[0x8]; 927 }; 928 929 struct mlx5_ifc_fte_match_set_misc2_bits { 930 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 931 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 932 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 933 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 934 u8 metadata_reg_c_7[0x20]; 935 u8 metadata_reg_c_6[0x20]; 936 u8 metadata_reg_c_5[0x20]; 937 u8 metadata_reg_c_4[0x20]; 938 u8 metadata_reg_c_3[0x20]; 939 u8 metadata_reg_c_2[0x20]; 940 u8 metadata_reg_c_1[0x20]; 941 u8 metadata_reg_c_0[0x20]; 942 u8 metadata_reg_a[0x20]; 943 u8 metadata_reg_b[0x20]; 944 u8 reserved_at_1c0[0x40]; 945 }; 946 947 struct mlx5_ifc_fte_match_set_misc3_bits { 948 u8 inner_tcp_seq_num[0x20]; 949 u8 outer_tcp_seq_num[0x20]; 950 u8 inner_tcp_ack_num[0x20]; 951 u8 outer_tcp_ack_num[0x20]; 952 u8 reserved_at_auto1[0x8]; 953 u8 outer_vxlan_gpe_vni[0x18]; 954 u8 outer_vxlan_gpe_next_protocol[0x8]; 955 u8 outer_vxlan_gpe_flags[0x8]; 956 u8 reserved_at_a8[0x10]; 957 u8 icmp_header_data[0x20]; 958 u8 icmpv6_header_data[0x20]; 959 u8 icmp_type[0x8]; 960 u8 icmp_code[0x8]; 961 u8 icmpv6_type[0x8]; 962 u8 icmpv6_code[0x8]; 963 u8 geneve_tlv_option_0_data[0x20]; 964 u8 gtpu_teid[0x20]; 965 u8 gtpu_msg_type[0x08]; 966 u8 gtpu_msg_flags[0x08]; 967 u8 reserved_at_170[0x10]; 968 u8 gtpu_dw_2[0x20]; 969 u8 gtpu_first_ext_dw_0[0x20]; 970 u8 gtpu_dw_0[0x20]; 971 u8 reserved_at_240[0x20]; 972 973 }; 974 975 struct mlx5_ifc_fte_match_set_misc4_bits { 976 u8 prog_sample_field_value_0[0x20]; 977 u8 prog_sample_field_id_0[0x20]; 978 u8 prog_sample_field_value_1[0x20]; 979 u8 prog_sample_field_id_1[0x20]; 980 u8 prog_sample_field_value_2[0x20]; 981 u8 prog_sample_field_id_2[0x20]; 982 u8 prog_sample_field_value_3[0x20]; 983 u8 prog_sample_field_id_3[0x20]; 984 u8 prog_sample_field_value_4[0x20]; 985 u8 prog_sample_field_id_4[0x20]; 986 u8 prog_sample_field_value_5[0x20]; 987 u8 prog_sample_field_id_5[0x20]; 988 u8 prog_sample_field_value_6[0x20]; 989 u8 prog_sample_field_id_6[0x20]; 990 u8 prog_sample_field_value_7[0x20]; 991 u8 prog_sample_field_id_7[0x20]; 992 }; 993 994 struct mlx5_ifc_fte_match_set_misc5_bits { 995 u8 macsec_tag_0[0x20]; 996 u8 macsec_tag_1[0x20]; 997 u8 macsec_tag_2[0x20]; 998 u8 macsec_tag_3[0x20]; 999 u8 tunnel_header_0[0x20]; 1000 u8 tunnel_header_1[0x20]; 1001 u8 tunnel_header_2[0x20]; 1002 u8 tunnel_header_3[0x20]; 1003 u8 reserved[0x100]; 1004 }; 1005 1006 /* Flow matcher. */ 1007 struct mlx5_ifc_fte_match_param_bits { 1008 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1009 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1010 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1011 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1012 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1013 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1014 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1015 /* 1016 * Add reserved bit to match the struct size with the size defined in PRM. 1017 * This extension is not required in Linux. 1018 */ 1019 #ifndef HAVE_INFINIBAND_VERBS_H 1020 u8 reserved_0[0x200]; 1021 #endif 1022 }; 1023 1024 struct mlx5_ifc_dest_format_struct_bits { 1025 u8 destination_type[0x8]; 1026 u8 destination_id[0x18]; 1027 u8 reserved_0[0x20]; 1028 }; 1029 1030 enum { 1031 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 1032 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT, 1033 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT, 1034 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT, 1035 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT, 1036 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT, 1037 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT, 1038 }; 1039 1040 enum { 1041 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 1042 MLX5_CMD_OP_CREATE_MKEY = 0x200, 1043 MLX5_CMD_OP_CREATE_CQ = 0x400, 1044 MLX5_CMD_OP_CREATE_QP = 0x500, 1045 MLX5_CMD_OP_RST2INIT_QP = 0x502, 1046 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 1047 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 1048 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 1049 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 1050 MLX5_CMD_OP_QP_2ERR = 0x507, 1051 MLX5_CMD_OP_QP_2RST = 0x50A, 1052 MLX5_CMD_OP_QUERY_QP = 0x50B, 1053 MLX5_CMD_OP_SQD2RTS_QP = 0x50C, 1054 MLX5_CMD_OP_INIT2INIT_QP = 0x50E, 1055 MLX5_CMD_OP_SUSPEND_QP = 0x50F, 1056 MLX5_CMD_OP_RESUME_QP = 0x510, 1057 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 1058 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 1059 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 1060 MLX5_CMD_OP_ALLOC_PD = 0x800, 1061 MLX5_CMD_OP_DEALLOC_PD = 0x801, 1062 MLX5_CMD_OP_ACCESS_REGISTER = 0x805, 1063 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 1064 MLX5_CMD_OP_QUERY_LAG = 0x842, 1065 MLX5_CMD_OP_CREATE_TIR = 0x900, 1066 MLX5_CMD_OP_MODIFY_TIR = 0x901, 1067 MLX5_CMD_OP_CREATE_SQ = 0X904, 1068 MLX5_CMD_OP_MODIFY_SQ = 0X905, 1069 MLX5_CMD_OP_CREATE_RQ = 0x908, 1070 MLX5_CMD_OP_MODIFY_RQ = 0x909, 1071 MLX5_CMD_OP_QUERY_RQ = 0x90b, 1072 MLX5_CMD_OP_CREATE_RMP = 0x90c, 1073 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 1074 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 1075 MLX5_CMD_OP_QUERY_RMP = 0x90f, 1076 MLX5_CMD_OP_CREATE_TIS = 0x912, 1077 MLX5_CMD_OP_QUERY_TIS = 0x915, 1078 MLX5_CMD_OP_CREATE_RQT = 0x916, 1079 MLX5_CMD_OP_MODIFY_RQT = 0x917, 1080 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 1081 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 1082 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 1083 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 1084 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 1085 MLX5_CMD_SET_REGEX_PARAMS = 0xb04, 1086 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05, 1087 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06, 1088 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07, 1089 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c, 1090 }; 1091 1092 enum { 1093 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 1094 MLX5_MKC_ACCESS_MODE_KLM = 0x2, 1095 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3, 1096 }; 1097 1098 #define MLX5_ADAPTER_PAGE_SHIFT 12 1099 #define MLX5_LOG_RQ_STRIDE_SHIFT 4 1100 /** 1101 * The batch counter dcs id starts from 0x800000 and none batch counter 1102 * starts from 0. As currently, the counter is changed to be indexed by 1103 * pool index and the offset of the counter in the pool counters_raw array. 1104 * It means now the counter index is same for batch and none batch counter. 1105 * Add the 0x800000 batch counter offset to the batch counter index helps 1106 * indicate the counter index is from batch or none batch container pool. 1107 */ 1108 #define MLX5_CNT_BATCH_OFFSET 0x800000 1109 1110 /* The counter batch query requires ID align with 4. */ 1111 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4 1112 1113 /* Flow counters. */ 1114 struct mlx5_ifc_alloc_flow_counter_out_bits { 1115 u8 status[0x8]; 1116 u8 reserved_at_8[0x18]; 1117 u8 syndrome[0x20]; 1118 u8 flow_counter_id[0x20]; 1119 u8 reserved_at_60[0x20]; 1120 }; 1121 1122 struct mlx5_ifc_alloc_flow_counter_in_bits { 1123 u8 opcode[0x10]; 1124 u8 reserved_at_10[0x10]; 1125 u8 reserved_at_20[0x10]; 1126 u8 op_mod[0x10]; 1127 u8 flow_counter_id[0x20]; 1128 u8 reserved_at_40[0x18]; 1129 u8 flow_counter_bulk[0x8]; 1130 }; 1131 1132 struct mlx5_ifc_dealloc_flow_counter_out_bits { 1133 u8 status[0x8]; 1134 u8 reserved_at_8[0x18]; 1135 u8 syndrome[0x20]; 1136 u8 reserved_at_40[0x40]; 1137 }; 1138 1139 struct mlx5_ifc_dealloc_flow_counter_in_bits { 1140 u8 opcode[0x10]; 1141 u8 reserved_at_10[0x10]; 1142 u8 reserved_at_20[0x10]; 1143 u8 op_mod[0x10]; 1144 u8 flow_counter_id[0x20]; 1145 u8 reserved_at_60[0x20]; 1146 }; 1147 1148 struct mlx5_ifc_traffic_counter_bits { 1149 u8 packets[0x40]; 1150 u8 octets[0x40]; 1151 }; 1152 1153 struct mlx5_ifc_query_flow_counter_out_bits { 1154 u8 status[0x8]; 1155 u8 reserved_at_8[0x18]; 1156 u8 syndrome[0x20]; 1157 u8 reserved_at_40[0x40]; 1158 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 1159 }; 1160 1161 struct mlx5_ifc_query_flow_counter_in_bits { 1162 u8 opcode[0x10]; 1163 u8 reserved_at_10[0x10]; 1164 u8 reserved_at_20[0x10]; 1165 u8 op_mod[0x10]; 1166 u8 reserved_at_40[0x20]; 1167 u8 mkey[0x20]; 1168 u8 address[0x40]; 1169 u8 clear[0x1]; 1170 u8 dump_to_memory[0x1]; 1171 u8 num_of_counters[0x1e]; 1172 u8 flow_counter_id[0x20]; 1173 }; 1174 1175 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u 1176 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u 1177 1178 struct mlx5_ifc_klm_bits { 1179 u8 byte_count[0x20]; 1180 u8 mkey[0x20]; 1181 u8 address[0x40]; 1182 }; 1183 1184 struct mlx5_ifc_mkc_bits { 1185 u8 reserved_at_0[0x1]; 1186 u8 free[0x1]; 1187 u8 reserved_at_2[0x1]; 1188 u8 access_mode_4_2[0x3]; 1189 u8 reserved_at_6[0x7]; 1190 u8 relaxed_ordering_write[0x1]; 1191 u8 reserved_at_e[0x1]; 1192 u8 small_fence_on_rdma_read_response[0x1]; 1193 u8 umr_en[0x1]; 1194 u8 a[0x1]; 1195 u8 rw[0x1]; 1196 u8 rr[0x1]; 1197 u8 lw[0x1]; 1198 u8 lr[0x1]; 1199 u8 access_mode_1_0[0x2]; 1200 u8 reserved_at_18[0x8]; 1201 u8 qpn[0x18]; 1202 u8 mkey_7_0[0x8]; 1203 u8 reserved_at_40[0x20]; 1204 u8 length64[0x1]; 1205 u8 bsf_en[0x1]; 1206 u8 sync_umr[0x1]; 1207 u8 reserved_at_63[0x2]; 1208 u8 expected_sigerr_count[0x1]; 1209 u8 reserved_at_66[0x1]; 1210 u8 en_rinval[0x1]; 1211 u8 pd[0x18]; 1212 u8 start_addr[0x40]; 1213 u8 len[0x40]; 1214 u8 bsf_octword_size[0x20]; 1215 u8 reserved_at_120[0x80]; 1216 u8 translations_octword_size[0x20]; 1217 u8 reserved_at_1c0[0x19]; 1218 u8 relaxed_ordering_read[0x1]; 1219 u8 reserved_at_1da[0x1]; 1220 u8 log_page_size[0x5]; 1221 u8 reserved_at_1e0[0x3]; 1222 u8 crypto_en[0x2]; 1223 u8 reserved_at_1e5[0x1b]; 1224 }; 1225 1226 /* Range of values for MKEY context crypto_en field. */ 1227 enum { 1228 MLX5_MKEY_CRYPTO_DISABLED = 0x0, 1229 MLX5_MKEY_CRYPTO_ENABLED = 0x1, 1230 }; 1231 1232 struct mlx5_ifc_create_mkey_out_bits { 1233 u8 status[0x8]; 1234 u8 reserved_at_8[0x18]; 1235 u8 syndrome[0x20]; 1236 u8 reserved_at_40[0x8]; 1237 u8 mkey_index[0x18]; 1238 u8 reserved_at_60[0x20]; 1239 }; 1240 1241 struct mlx5_ifc_create_mkey_in_bits { 1242 u8 opcode[0x10]; 1243 u8 reserved_at_10[0x10]; 1244 u8 reserved_at_20[0x10]; 1245 u8 op_mod[0x10]; 1246 u8 reserved_at_40[0x20]; 1247 u8 pg_access[0x1]; 1248 u8 reserved_at_61[0x1f]; 1249 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 1250 u8 reserved_at_280[0x80]; 1251 u8 translations_octword_actual_size[0x20]; 1252 u8 mkey_umem_id[0x20]; 1253 u8 mkey_umem_offset[0x40]; 1254 u8 reserved_at_380[0x500]; 1255 u8 klm_pas_mtt[][0x20]; 1256 }; 1257 1258 enum { 1259 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, 1260 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, 1261 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1, 1262 MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, 1263 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, 1264 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, 1265 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1, 1266 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, 1267 }; 1268 1269 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \ 1270 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ) 1271 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \ 1272 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS) 1273 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \ 1274 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH) 1275 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \ 1276 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO) 1277 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \ 1278 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO) 1279 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ 1280 (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT) 1281 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \ 1282 (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD) 1283 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \ 1284 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK) 1285 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \ 1286 (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK) 1287 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \ 1288 (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL) 1289 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \ 1290 (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN) 1291 1292 enum { 1293 MLX5_HCA_CAP_OPMOD_GET_MAX = 0, 1294 MLX5_HCA_CAP_OPMOD_GET_CUR = 1, 1295 }; 1296 1297 enum { 1298 MLX5_CAP_INLINE_MODE_L2, 1299 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT, 1300 MLX5_CAP_INLINE_MODE_NOT_REQUIRED, 1301 }; 1302 1303 enum { 1304 MLX5_INLINE_MODE_NONE, 1305 MLX5_INLINE_MODE_L2, 1306 MLX5_INLINE_MODE_IP, 1307 MLX5_INLINE_MODE_TCP_UDP, 1308 MLX5_INLINE_MODE_RESERVED4, 1309 MLX5_INLINE_MODE_INNER_L2, 1310 MLX5_INLINE_MODE_INNER_IP, 1311 MLX5_INLINE_MODE_INNER_TCP_UDP, 1312 }; 1313 1314 /* The supported timestamp formats reported in HCA attributes. */ 1315 enum { 1316 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0, 1317 MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1, 1318 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2, 1319 }; 1320 1321 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */ 1322 enum { 1323 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 1324 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 1325 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 1326 }; 1327 1328 /* HCA bit masks indicating which Flex parser protocols are already enabled. */ 1329 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0) 1330 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1) 1331 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2) 1332 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3) 1333 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4) 1334 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5) 1335 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6) 1336 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7) 1337 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8) 1338 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9) 1339 1340 /* The device steering logic format. */ 1341 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0 1342 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1 1343 1344 struct mlx5_ifc_cmd_hca_cap_bits { 1345 u8 reserved_at_0[0x30]; 1346 u8 vhca_id[0x10]; 1347 u8 reserved_at_40[0x20]; 1348 u8 reserved_at_60[0x3]; 1349 u8 log_regexp_scatter_gather_size[0x5]; 1350 u8 reserved_at_68[0x3]; 1351 u8 log_dma_mmo_size[0x5]; 1352 u8 reserved_at_70[0x3]; 1353 u8 log_compress_mmo_size[0x5]; 1354 u8 reserved_at_78[0x3]; 1355 u8 log_decompress_mmo_size[0x5]; 1356 u8 log_max_srq_sz[0x8]; 1357 u8 log_max_qp_sz[0x8]; 1358 u8 reserved_at_90[0x9]; 1359 u8 wqe_index_ignore_cap[0x1]; 1360 u8 dynamic_qp_allocation[0x1]; 1361 u8 log_max_qp[0x5]; 1362 u8 reserved_at_a0[0x4]; 1363 u8 regexp_num_of_engines[0x4]; 1364 u8 reserved_at_a8[0x1]; 1365 u8 reg_c_preserve[0x1]; 1366 u8 reserved_at_aa[0x1]; 1367 u8 log_max_srq[0x5]; 1368 u8 reserved_at_b0[0xb]; 1369 u8 scatter_fcs_w_decap_disable[0x1]; 1370 u8 reserved_at_bc[0x4]; 1371 u8 reserved_at_c0[0x8]; 1372 u8 log_max_cq_sz[0x8]; 1373 u8 reserved_at_d0[0xb]; 1374 u8 log_max_cq[0x5]; 1375 u8 log_max_eq_sz[0x8]; 1376 u8 relaxed_ordering_write[0x1]; 1377 u8 relaxed_ordering_read[0x1]; 1378 u8 access_register_user[0x1]; 1379 u8 log_max_mkey[0x5]; 1380 u8 reserved_at_f0[0x8]; 1381 u8 dump_fill_mkey[0x1]; 1382 u8 reserved_at_f9[0x3]; 1383 u8 log_max_eq[0x4]; 1384 u8 max_indirection[0x8]; 1385 u8 fixed_buffer_size[0x1]; 1386 u8 log_max_mrw_sz[0x7]; 1387 u8 force_teardown[0x1]; 1388 u8 reserved_at_111[0x1]; 1389 u8 log_max_bsf_list_size[0x6]; 1390 u8 umr_extended_translation_offset[0x1]; 1391 u8 null_mkey[0x1]; 1392 u8 log_max_klm_list_size[0x6]; 1393 u8 non_wire_sq[0x1]; 1394 u8 reserved_at_121[0x9]; 1395 u8 log_max_ra_req_dc[0x6]; 1396 u8 reserved_at_130[0x3]; 1397 u8 log_max_static_sq_wq[0x5]; 1398 u8 reserved_at_138[0x2]; 1399 u8 log_max_ra_res_dc[0x6]; 1400 u8 reserved_at_140[0xa]; 1401 u8 log_max_ra_req_qp[0x6]; 1402 u8 rtr2rts_qp_counters_set_id[0x1]; 1403 u8 rts2rts_udp_sport[0x1]; 1404 u8 rts2rts_lag_tx_port_affinity[0x1]; 1405 u8 dma_mmo_sq[0x1]; 1406 u8 compress_min_block_size[0x4]; 1407 u8 compress_mmo_sq[0x1]; 1408 u8 decompress_mmo_sq[0x1]; 1409 u8 log_max_ra_res_qp[0x6]; 1410 u8 end_pad[0x1]; 1411 u8 cc_query_allowed[0x1]; 1412 u8 cc_modify_allowed[0x1]; 1413 u8 start_pad[0x1]; 1414 u8 cache_line_128byte[0x1]; 1415 u8 reserved_at_165[0xa]; 1416 u8 qcam_reg[0x1]; 1417 u8 gid_table_size[0x10]; 1418 u8 out_of_seq_cnt[0x1]; 1419 u8 vport_counters[0x1]; 1420 u8 retransmission_q_counters[0x1]; 1421 u8 debug[0x1]; 1422 u8 modify_rq_counter_set_id[0x1]; 1423 u8 rq_delay_drop[0x1]; 1424 u8 max_qp_cnt[0xa]; 1425 u8 pkey_table_size[0x10]; 1426 u8 vport_group_manager[0x1]; 1427 u8 vhca_group_manager[0x1]; 1428 u8 ib_virt[0x1]; 1429 u8 eth_virt[0x1]; 1430 u8 vnic_env_queue_counters[0x1]; 1431 u8 ets[0x1]; 1432 u8 nic_flow_table[0x1]; 1433 u8 eswitch_manager[0x1]; 1434 u8 device_memory[0x1]; 1435 u8 mcam_reg[0x1]; 1436 u8 pcam_reg[0x1]; 1437 u8 local_ca_ack_delay[0x5]; 1438 u8 port_module_event[0x1]; 1439 u8 enhanced_error_q_counters[0x1]; 1440 u8 ports_check[0x1]; 1441 u8 reserved_at_1b3[0x1]; 1442 u8 disable_link_up[0x1]; 1443 u8 beacon_led[0x1]; 1444 u8 port_type[0x2]; 1445 u8 num_ports[0x8]; 1446 u8 reserved_at_1c0[0x1]; 1447 u8 pps[0x1]; 1448 u8 pps_modify[0x1]; 1449 u8 log_max_msg[0x5]; 1450 u8 reserved_at_1c8[0x4]; 1451 u8 max_tc[0x4]; 1452 u8 temp_warn_event[0x1]; 1453 u8 dcbx[0x1]; 1454 u8 general_notification_event[0x1]; 1455 u8 reserved_at_1d3[0x2]; 1456 u8 fpga[0x1]; 1457 u8 rol_s[0x1]; 1458 u8 rol_g[0x1]; 1459 u8 reserved_at_1d8[0x1]; 1460 u8 wol_s[0x1]; 1461 u8 wol_g[0x1]; 1462 u8 wol_a[0x1]; 1463 u8 wol_b[0x1]; 1464 u8 wol_m[0x1]; 1465 u8 wol_u[0x1]; 1466 u8 wol_p[0x1]; 1467 u8 stat_rate_support[0x10]; 1468 u8 reserved_at_1f0[0xc]; 1469 u8 cqe_version[0x4]; 1470 u8 compact_address_vector[0x1]; 1471 u8 striding_rq[0x1]; 1472 u8 reserved_at_202[0x1]; 1473 u8 ipoib_enhanced_offloads[0x1]; 1474 u8 ipoib_basic_offloads[0x1]; 1475 u8 reserved_at_205[0x1]; 1476 u8 repeated_block_disabled[0x1]; 1477 u8 umr_modify_entity_size_disabled[0x1]; 1478 u8 umr_modify_atomic_disabled[0x1]; 1479 u8 umr_indirect_mkey_disabled[0x1]; 1480 u8 umr_fence[0x2]; 1481 u8 reserved_at_20c[0x3]; 1482 u8 drain_sigerr[0x1]; 1483 u8 cmdif_checksum[0x2]; 1484 u8 sigerr_cqe[0x1]; 1485 u8 reserved_at_213[0x1]; 1486 u8 wq_signature[0x1]; 1487 u8 sctr_data_cqe[0x1]; 1488 u8 reserved_at_216[0x1]; 1489 u8 sho[0x1]; 1490 u8 tph[0x1]; 1491 u8 rf[0x1]; 1492 u8 dct[0x1]; 1493 u8 qos[0x1]; 1494 u8 eth_net_offloads[0x1]; 1495 u8 roce[0x1]; 1496 u8 atomic[0x1]; 1497 u8 reserved_at_21f[0x1]; 1498 u8 cq_oi[0x1]; 1499 u8 cq_resize[0x1]; 1500 u8 cq_moderation[0x1]; 1501 u8 reserved_at_223[0x3]; 1502 u8 cq_eq_remap[0x1]; 1503 u8 pg[0x1]; 1504 u8 block_lb_mc[0x1]; 1505 u8 reserved_at_229[0x1]; 1506 u8 scqe_break_moderation[0x1]; 1507 u8 cq_period_start_from_cqe[0x1]; 1508 u8 cd[0x1]; 1509 u8 reserved_at_22d[0x1]; 1510 u8 apm[0x1]; 1511 u8 vector_calc[0x1]; 1512 u8 umr_ptr_rlky[0x1]; 1513 u8 imaicl[0x1]; 1514 u8 reserved_at_232[0x4]; 1515 u8 qkv[0x1]; 1516 u8 pkv[0x1]; 1517 u8 set_deth_sqpn[0x1]; 1518 u8 reserved_at_239[0x3]; 1519 u8 xrc[0x1]; 1520 u8 ud[0x1]; 1521 u8 uc[0x1]; 1522 u8 rc[0x1]; 1523 u8 uar_4k[0x1]; 1524 u8 reserved_at_241[0x8]; 1525 u8 regexp_params[0x1]; 1526 u8 uar_sz[0x6]; 1527 u8 port_selection_cap[0x1]; 1528 u8 reserved_at_251[0x7]; 1529 u8 log_pg_sz[0x8]; 1530 u8 bf[0x1]; 1531 u8 driver_version[0x1]; 1532 u8 pad_tx_eth_packet[0x1]; 1533 u8 reserved_at_263[0x8]; 1534 u8 log_bf_reg_size[0x5]; 1535 u8 reserved_at_270[0xb]; 1536 u8 lag_master[0x1]; 1537 u8 num_lag_ports[0x4]; 1538 u8 reserved_at_280[0x10]; 1539 u8 max_wqe_sz_sq[0x10]; 1540 u8 reserved_at_2a0[0xc]; 1541 u8 regexp_mmo_sq[0x1]; 1542 u8 regexp_version[0x3]; 1543 u8 max_wqe_sz_rq[0x10]; 1544 u8 max_flow_counter_31_16[0x10]; 1545 u8 max_wqe_sz_sq_dc[0x10]; 1546 u8 reserved_at_2e0[0x7]; 1547 u8 max_qp_mcg[0x19]; 1548 u8 reserved_at_300[0x10]; 1549 u8 flow_counter_bulk_alloc[0x08]; 1550 u8 log_max_mcg[0x8]; 1551 u8 reserved_at_320[0x3]; 1552 u8 log_max_transport_domain[0x5]; 1553 u8 reserved_at_328[0x3]; 1554 u8 log_max_pd[0x5]; 1555 u8 reserved_at_330[0xb]; 1556 u8 log_max_xrcd[0x5]; 1557 u8 nic_receive_steering_discard[0x1]; 1558 u8 receive_discard_vport_down[0x1]; 1559 u8 transmit_discard_vport_down[0x1]; 1560 u8 reserved_at_343[0x5]; 1561 u8 log_max_flow_counter_bulk[0x8]; 1562 u8 max_flow_counter_15_0[0x10]; 1563 u8 modify_tis[0x1]; 1564 u8 flow_counters_dump[0x1]; 1565 u8 reserved_at_360[0x1]; 1566 u8 log_max_rq[0x5]; 1567 u8 reserved_at_368[0x3]; 1568 u8 log_max_sq[0x5]; 1569 u8 reserved_at_370[0x3]; 1570 u8 log_max_tir[0x5]; 1571 u8 reserved_at_378[0x3]; 1572 u8 log_max_tis[0x5]; 1573 u8 basic_cyclic_rcv_wqe[0x1]; 1574 u8 reserved_at_381[0x1]; 1575 u8 mem_rq_rmp[0x1]; 1576 u8 log_max_rmp[0x5]; 1577 u8 reserved_at_388[0x3]; 1578 u8 log_max_rqt[0x5]; 1579 u8 reserved_at_390[0x3]; 1580 u8 log_max_rqt_size[0x5]; 1581 u8 reserved_at_398[0x3]; 1582 u8 log_max_tis_per_sq[0x5]; 1583 u8 ext_stride_num_range[0x1]; 1584 u8 reserved_at_3a1[0x2]; 1585 u8 log_max_stride_sz_rq[0x5]; 1586 u8 reserved_at_3a8[0x3]; 1587 u8 log_min_stride_sz_rq[0x5]; 1588 u8 reserved_at_3b0[0x3]; 1589 u8 log_max_stride_sz_sq[0x5]; 1590 u8 reserved_at_3b8[0x3]; 1591 u8 log_min_stride_sz_sq[0x5]; 1592 u8 hairpin[0x1]; 1593 u8 reserved_at_3c1[0x2]; 1594 u8 log_max_hairpin_queues[0x5]; 1595 u8 reserved_at_3c8[0x3]; 1596 u8 log_max_hairpin_wq_data_sz[0x5]; 1597 u8 reserved_at_3d0[0x3]; 1598 u8 log_max_hairpin_num_packets[0x5]; 1599 u8 reserved_at_3d8[0x3]; 1600 u8 log_max_wq_sz[0x5]; 1601 u8 nic_vport_change_event[0x1]; 1602 u8 disable_local_lb_uc[0x1]; 1603 u8 disable_local_lb_mc[0x1]; 1604 u8 log_min_hairpin_wq_data_sz[0x5]; 1605 u8 reserved_at_3e8[0x3]; 1606 u8 log_max_vlan_list[0x5]; 1607 u8 reserved_at_3f0[0x3]; 1608 u8 log_max_current_mc_list[0x5]; 1609 u8 reserved_at_3f8[0x3]; 1610 u8 log_max_current_uc_list[0x5]; 1611 u8 general_obj_types[0x40]; 1612 u8 sq_ts_format[0x2]; 1613 u8 rq_ts_format[0x2]; 1614 u8 steering_format_version[0x4]; 1615 u8 reserved_at_448[0x18]; 1616 u8 reserved_at_460[0x8]; 1617 u8 aes_xts[0x1]; 1618 u8 crypto[0x1]; 1619 u8 reserved_at_46a[0x6]; 1620 u8 max_num_eqs[0x10]; 1621 u8 reserved_at_480[0x3]; 1622 u8 log_max_l2_table[0x5]; 1623 u8 reserved_at_488[0x8]; 1624 u8 log_uar_page_sz[0x10]; 1625 u8 reserved_at_4a0[0x20]; 1626 u8 device_frequency_mhz[0x20]; 1627 u8 device_frequency_khz[0x20]; 1628 u8 reserved_at_500[0x20]; 1629 u8 num_of_uars_per_page[0x20]; 1630 u8 flex_parser_protocols[0x20]; 1631 u8 max_geneve_tlv_options[0x8]; 1632 u8 reserved_at_568[0x3]; 1633 u8 max_geneve_tlv_option_data_len[0x5]; 1634 u8 reserved_at_570[0x49]; 1635 u8 mini_cqe_resp_l3_l4_tag[0x1]; 1636 u8 mini_cqe_resp_flow_tag[0x1]; 1637 u8 enhanced_cqe_compression[0x1]; 1638 u8 mini_cqe_resp_stride_index[0x1]; 1639 u8 cqe_128_always[0x1]; 1640 u8 cqe_compression_128[0x1]; 1641 u8 cqe_compression[0x1]; 1642 u8 cqe_compression_timeout[0x10]; 1643 u8 cqe_compression_max_num[0x10]; 1644 u8 reserved_at_5e0[0x10]; 1645 u8 tag_matching[0x1]; 1646 u8 rndv_offload_rc[0x1]; 1647 u8 rndv_offload_dc[0x1]; 1648 u8 log_tag_matching_list_sz[0x5]; 1649 u8 reserved_at_5f8[0x3]; 1650 u8 log_max_xrq[0x5]; 1651 u8 affiliate_nic_vport_criteria[0x8]; 1652 u8 native_port_num[0x8]; 1653 u8 num_vhca_ports[0x8]; 1654 u8 reserved_at_618[0x6]; 1655 u8 sw_owner_id[0x1]; 1656 u8 reserved_at_61f[0x129]; 1657 u8 dma_mmo_qp[0x1]; 1658 u8 regexp_mmo_qp[0x1]; 1659 u8 compress_mmo_qp[0x1]; 1660 u8 decompress_mmo_qp[0x1]; 1661 u8 reserved_at_624[0xd4]; 1662 }; 1663 1664 struct mlx5_ifc_qos_cap_bits { 1665 u8 packet_pacing[0x1]; 1666 u8 esw_scheduling[0x1]; 1667 u8 esw_bw_share[0x1]; 1668 u8 esw_rate_limit[0x1]; 1669 u8 reserved_at_4[0x1]; 1670 u8 packet_pacing_burst_bound[0x1]; 1671 u8 packet_pacing_typical_size[0x1]; 1672 u8 flow_meter_old[0x1]; 1673 u8 reserved_at_8[0x8]; 1674 u8 log_max_flow_meter[0x8]; 1675 u8 flow_meter_reg_id[0x8]; 1676 u8 wqe_rate_pp[0x1]; 1677 u8 reserved_at_25[0x7]; 1678 u8 flow_meter[0x1]; 1679 u8 reserved_at_2e[0x17]; 1680 u8 packet_pacing_max_rate[0x20]; 1681 u8 packet_pacing_min_rate[0x20]; 1682 u8 reserved_at_80[0x10]; 1683 u8 packet_pacing_rate_table_size[0x10]; 1684 u8 esw_element_type[0x10]; 1685 u8 esw_tsar_type[0x10]; 1686 u8 reserved_at_c0[0x10]; 1687 u8 max_qos_para_vport[0x10]; 1688 u8 max_tsar_bw_share[0x20]; 1689 u8 nic_element_type[0x10]; 1690 u8 nic_tsar_type[0x10]; 1691 u8 reserved_at_120[0x3]; 1692 u8 log_meter_aso_granularity[0x5]; 1693 u8 reserved_at_128[0x3]; 1694 u8 log_meter_aso_max_alloc[0x5]; 1695 u8 reserved_at_130[0x3]; 1696 u8 log_max_num_meter_aso[0x5]; 1697 u8 reserved_at_138[0x6b0]; 1698 }; 1699 1700 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1701 u8 csum_cap[0x1]; 1702 u8 vlan_cap[0x1]; 1703 u8 lro_cap[0x1]; 1704 u8 lro_psh_flag[0x1]; 1705 u8 lro_time_stamp[0x1]; 1706 u8 lro_max_msg_sz_mode[0x2]; 1707 u8 wqe_vlan_insert[0x1]; 1708 u8 self_lb_en_modifiable[0x1]; 1709 u8 self_lb_mc[0x1]; 1710 u8 self_lb_uc[0x1]; 1711 u8 max_lso_cap[0x5]; 1712 u8 multi_pkt_send_wqe[0x2]; 1713 u8 wqe_inline_mode[0x2]; 1714 u8 rss_ind_tbl_cap[0x4]; 1715 u8 reg_umr_sq[0x1]; 1716 u8 scatter_fcs[0x1]; 1717 u8 enhanced_multi_pkt_send_wqe[0x1]; 1718 u8 tunnel_lso_const_out_ip_id[0x1]; 1719 u8 tunnel_lro_gre[0x1]; 1720 u8 tunnel_lro_vxlan[0x1]; 1721 u8 tunnel_stateless_gre[0x1]; 1722 u8 tunnel_stateless_vxlan[0x1]; 1723 u8 swp[0x1]; 1724 u8 swp_csum[0x1]; 1725 u8 swp_lso[0x1]; 1726 u8 reserved_at_23[0x8]; 1727 u8 tunnel_stateless_gtp[0x1]; 1728 u8 reserved_at_25[0x4]; 1729 u8 max_vxlan_udp_ports[0x8]; 1730 u8 reserved_at_38[0x6]; 1731 u8 max_geneve_opt_len[0x1]; 1732 u8 tunnel_stateless_geneve_rx[0x1]; 1733 u8 reserved_at_40[0x10]; 1734 u8 lro_min_mss_size[0x10]; 1735 u8 reserved_at_60[0x120]; 1736 u8 lro_timer_supported_periods[4][0x20]; 1737 u8 reserved_at_200[0x600]; 1738 }; 1739 1740 enum { 1741 MLX5_VIRTQ_TYPE_SPLIT = 0, 1742 MLX5_VIRTQ_TYPE_PACKED = 1, 1743 }; 1744 1745 enum { 1746 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0, 1747 MLX5_VIRTQ_EVENT_MODE_QP = 1, 1748 MLX5_VIRTQ_EVENT_MODE_MSIX = 2, 1749 }; 1750 1751 struct mlx5_ifc_virtio_emulation_cap_bits { 1752 u8 desc_tunnel_offload_type[0x1]; 1753 u8 eth_frame_offload_type[0x1]; 1754 u8 virtio_version_1_0[0x1]; 1755 u8 tso_ipv4[0x1]; 1756 u8 tso_ipv6[0x1]; 1757 u8 tx_csum[0x1]; 1758 u8 rx_csum[0x1]; 1759 u8 reserved_at_7[0x1][0x9]; 1760 u8 event_mode[0x8]; 1761 u8 virtio_queue_type[0x8]; 1762 u8 reserved_at_20[0x13]; 1763 u8 log_doorbell_stride[0x5]; 1764 u8 reserved_at_3b[0x3]; 1765 u8 log_doorbell_bar_size[0x5]; 1766 u8 doorbell_bar_offset[0x40]; 1767 u8 reserved_at_80[0x8]; 1768 u8 max_num_virtio_queues[0x18]; 1769 u8 reserved_at_a0[0x60]; 1770 u8 umem_1_buffer_param_a[0x20]; 1771 u8 umem_1_buffer_param_b[0x20]; 1772 u8 umem_2_buffer_param_a[0x20]; 1773 u8 umem_2_buffer_param_b[0x20]; 1774 u8 umem_3_buffer_param_a[0x20]; 1775 u8 umem_3_buffer_param_b[0x20]; 1776 u8 reserved_at_1c0[0x620]; 1777 }; 1778 1779 /** 1780 * PARSE_GRAPH_NODE Capabilities Field Descriptions 1781 */ 1782 struct mlx5_ifc_parse_graph_node_cap_bits { 1783 u8 node_in[0x20]; 1784 u8 node_out[0x20]; 1785 u8 header_length_mode[0x10]; 1786 u8 sample_offset_mode[0x10]; 1787 u8 max_num_arc_in[0x08]; 1788 u8 max_num_arc_out[0x08]; 1789 u8 max_num_sample[0x08]; 1790 u8 reserved_at_78[0x07]; 1791 u8 sample_id_in_out[0x1]; 1792 u8 max_base_header_length[0x10]; 1793 u8 reserved_at_90[0x08]; 1794 u8 max_sample_base_offset[0x08]; 1795 u8 max_next_header_offset[0x10]; 1796 u8 reserved_at_b0[0x08]; 1797 u8 header_length_mask_width[0x08]; 1798 }; 1799 1800 struct mlx5_ifc_flow_table_prop_layout_bits { 1801 u8 ft_support[0x1]; 1802 u8 flow_tag[0x1]; 1803 u8 flow_counter[0x1]; 1804 u8 flow_modify_en[0x1]; 1805 u8 modify_root[0x1]; 1806 u8 identified_miss_table[0x1]; 1807 u8 flow_table_modify[0x1]; 1808 u8 reformat[0x1]; 1809 u8 decap[0x1]; 1810 u8 reset_root_to_default[0x1]; 1811 u8 pop_vlan[0x1]; 1812 u8 push_vlan[0x1]; 1813 u8 fpga_vendor_acceleration[0x1]; 1814 u8 pop_vlan_2[0x1]; 1815 u8 push_vlan_2[0x1]; 1816 u8 reformat_and_vlan_action[0x1]; 1817 u8 modify_and_vlan_action[0x1]; 1818 u8 sw_owner[0x1]; 1819 u8 reformat_l3_tunnel_to_l2[0x1]; 1820 u8 reformat_l2_to_l3_tunnel[0x1]; 1821 u8 reformat_and_modify_action[0x1]; 1822 u8 reserved_at_15[0x9]; 1823 u8 sw_owner_v2[0x1]; 1824 u8 reserved_at_1f[0x1]; 1825 u8 reserved_at_20[0x2]; 1826 u8 log_max_ft_size[0x6]; 1827 u8 log_max_modify_header_context[0x8]; 1828 u8 max_modify_header_actions[0x8]; 1829 u8 max_ft_level[0x8]; 1830 u8 reserved_at_40[0x8]; 1831 u8 log_max_ft_sampler_num[8]; 1832 u8 metadata_reg_b_width[0x8]; 1833 u8 metadata_reg_a_width[0x8]; 1834 u8 reserved_at_60[0x18]; 1835 u8 log_max_ft_num[0x8]; 1836 u8 reserved_at_80[0x10]; 1837 u8 log_max_flow_counter[0x8]; 1838 u8 log_max_destination[0x8]; 1839 u8 reserved_at_a0[0x18]; 1840 u8 log_max_flow[0x8]; 1841 u8 reserved_at_c0[0x140]; 1842 }; 1843 1844 struct mlx5_ifc_roce_caps_bits { 1845 u8 reserved_0[0x1e]; 1846 u8 qp_ts_format[0x2]; 1847 u8 reserved_at_20[0x7e0]; 1848 }; 1849 1850 /* 1851 * Table 1872 - Flow Table Fields Supported 2 Format 1852 */ 1853 struct mlx5_ifc_ft_fields_support_2_bits { 1854 u8 reserved_at_0[0xf]; 1855 u8 tunnel_header_2_3[0x1]; 1856 u8 tunnel_header_0_1[0x1]; 1857 u8 macsec_syndrome[0x1]; 1858 u8 macsec_tag[0x1]; 1859 u8 outer_lrh_sl[0x1]; 1860 u8 inner_ipv4_ihl[0x1]; 1861 u8 outer_ipv4_ihl[0x1]; 1862 u8 psp_syndrome[0x1]; 1863 u8 inner_l3_ok[0x1]; 1864 u8 inner_l4_ok[0x1]; 1865 u8 outer_l3_ok[0x1]; 1866 u8 outer_l4_ok[0x1]; 1867 u8 psp_header[0x1]; 1868 u8 inner_ipv4_checksum_ok[0x1]; 1869 u8 inner_l4_checksum_ok[0x1]; 1870 u8 outer_ipv4_checksum_ok[0x1]; 1871 u8 outer_l4_checksum_ok[0x1]; 1872 u8 reserved_at_20[0x60]; 1873 }; 1874 1875 struct mlx5_ifc_flow_table_nic_cap_bits { 1876 u8 reserved_at_0[0x200]; 1877 struct mlx5_ifc_flow_table_prop_layout_bits 1878 flow_table_properties_nic_receive; 1879 struct mlx5_ifc_flow_table_prop_layout_bits 1880 flow_table_properties_nic_receive_rdma; 1881 struct mlx5_ifc_flow_table_prop_layout_bits 1882 flow_table_properties_nic_receive_sniffer; 1883 struct mlx5_ifc_flow_table_prop_layout_bits 1884 flow_table_properties_nic_transmit; 1885 struct mlx5_ifc_flow_table_prop_layout_bits 1886 flow_table_properties_nic_transmit_rdma; 1887 struct mlx5_ifc_flow_table_prop_layout_bits 1888 flow_table_properties_nic_transmit_sniffer; 1889 u8 reserved_at_e00[0x600]; 1890 struct mlx5_ifc_ft_fields_support_2_bits 1891 ft_field_support_2_nic_receive; 1892 }; 1893 1894 /* 1895 * HCA Capabilities 2 1896 */ 1897 struct mlx5_ifc_cmd_hca_cap_2_bits { 1898 u8 reserved_at_0[0x80]; /* End of DW4. */ 1899 u8 reserved_at_80[0x3]; 1900 u8 max_num_prog_sample_field[0x5]; 1901 u8 reserved_at_88[0x3]; 1902 u8 log_max_num_reserved_qpn[0x5]; 1903 u8 reserved_at_90[0x3]; 1904 u8 log_reserved_qpn_granularity[0x5]; 1905 u8 reserved_at_98[0x3]; 1906 u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */ 1907 u8 max_reformat_insert_size[0x8]; 1908 u8 max_reformat_insert_offset[0x8]; 1909 u8 max_reformat_remove_size[0x8]; 1910 u8 max_reformat_remove_offset[0x8]; /* End of DW6. */ 1911 u8 aso_conntrack_reg_id[0x8]; 1912 u8 reserved_at_c8[0x3]; 1913 u8 log_conn_track_granularity[0x5]; 1914 u8 reserved_at_d0[0x3]; 1915 u8 log_conn_track_max_alloc[0x5]; 1916 u8 reserved_at_d8[0x3]; 1917 u8 log_max_conn_track_offload[0x5]; 1918 u8 reserved_at_e0[0x20]; /* End of DW7. */ 1919 u8 reserved_at_100[0x700]; 1920 }; 1921 1922 union mlx5_ifc_hca_cap_union_bits { 1923 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 1924 struct mlx5_ifc_per_protocol_networking_offload_caps_bits 1925 per_protocol_networking_offload_caps; 1926 struct mlx5_ifc_qos_cap_bits qos_cap; 1927 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps; 1928 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 1929 struct mlx5_ifc_roce_caps_bits roce_caps; 1930 u8 reserved_at_0[0x8000]; 1931 }; 1932 1933 struct mlx5_ifc_set_action_in_bits { 1934 u8 action_type[0x4]; 1935 u8 field[0xc]; 1936 u8 reserved_at_10[0x3]; 1937 u8 offset[0x5]; 1938 u8 reserved_at_18[0x3]; 1939 u8 length[0x5]; 1940 u8 data[0x20]; 1941 }; 1942 1943 struct mlx5_ifc_query_hca_cap_out_bits { 1944 u8 status[0x8]; 1945 u8 reserved_at_8[0x18]; 1946 u8 syndrome[0x20]; 1947 u8 reserved_at_40[0x40]; 1948 union mlx5_ifc_hca_cap_union_bits capability; 1949 }; 1950 1951 struct mlx5_ifc_query_hca_cap_in_bits { 1952 u8 opcode[0x10]; 1953 u8 reserved_at_10[0x10]; 1954 u8 reserved_at_20[0x10]; 1955 u8 op_mod[0x10]; 1956 u8 reserved_at_40[0x40]; 1957 }; 1958 1959 struct mlx5_ifc_mac_address_layout_bits { 1960 u8 reserved_at_0[0x10]; 1961 u8 mac_addr_47_32[0x10]; 1962 u8 mac_addr_31_0[0x20]; 1963 }; 1964 1965 struct mlx5_ifc_nic_vport_context_bits { 1966 u8 reserved_at_0[0x5]; 1967 u8 min_wqe_inline_mode[0x3]; 1968 u8 reserved_at_8[0x15]; 1969 u8 disable_mc_local_lb[0x1]; 1970 u8 disable_uc_local_lb[0x1]; 1971 u8 roce_en[0x1]; 1972 u8 arm_change_event[0x1]; 1973 u8 reserved_at_21[0x1a]; 1974 u8 event_on_mtu[0x1]; 1975 u8 event_on_promisc_change[0x1]; 1976 u8 event_on_vlan_change[0x1]; 1977 u8 event_on_mc_address_change[0x1]; 1978 u8 event_on_uc_address_change[0x1]; 1979 u8 reserved_at_40[0xc]; 1980 u8 affiliation_criteria[0x4]; 1981 u8 affiliated_vhca_id[0x10]; 1982 u8 reserved_at_60[0xd0]; 1983 u8 mtu[0x10]; 1984 u8 system_image_guid[0x40]; 1985 u8 port_guid[0x40]; 1986 u8 node_guid[0x40]; 1987 u8 reserved_at_200[0x140]; 1988 u8 qkey_violation_counter[0x10]; 1989 u8 reserved_at_350[0x430]; 1990 u8 promisc_uc[0x1]; 1991 u8 promisc_mc[0x1]; 1992 u8 promisc_all[0x1]; 1993 u8 reserved_at_783[0x2]; 1994 u8 allowed_list_type[0x3]; 1995 u8 reserved_at_788[0xc]; 1996 u8 allowed_list_size[0xc]; 1997 struct mlx5_ifc_mac_address_layout_bits permanent_address; 1998 u8 reserved_at_7e0[0x20]; 1999 }; 2000 2001 struct mlx5_ifc_query_nic_vport_context_out_bits { 2002 u8 status[0x8]; 2003 u8 reserved_at_8[0x18]; 2004 u8 syndrome[0x20]; 2005 u8 reserved_at_40[0x40]; 2006 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 2007 }; 2008 2009 struct mlx5_ifc_query_nic_vport_context_in_bits { 2010 u8 opcode[0x10]; 2011 u8 reserved_at_10[0x10]; 2012 u8 reserved_at_20[0x10]; 2013 u8 op_mod[0x10]; 2014 u8 other_vport[0x1]; 2015 u8 reserved_at_41[0xf]; 2016 u8 vport_number[0x10]; 2017 u8 reserved_at_60[0x5]; 2018 u8 allowed_list_type[0x3]; 2019 u8 reserved_at_68[0x18]; 2020 }; 2021 2022 /* 2023 * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa. 2024 * Each TIS binds to one PF by setting lag_tx_port_affinity (>0). 2025 * Once LAG enabled, we create multiple TISs and bind each one to 2026 * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1. 2027 */ 2028 #define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \ 2029 (index) % (num) + 1 : 0) 2030 struct mlx5_ifc_tisc_bits { 2031 u8 strict_lag_tx_port_affinity[0x1]; 2032 u8 reserved_at_1[0x3]; 2033 u8 lag_tx_port_affinity[0x04]; 2034 u8 reserved_at_8[0x4]; 2035 u8 prio[0x4]; 2036 u8 reserved_at_10[0x10]; 2037 u8 reserved_at_20[0x100]; 2038 u8 reserved_at_120[0x8]; 2039 u8 transport_domain[0x18]; 2040 u8 reserved_at_140[0x8]; 2041 u8 underlay_qpn[0x18]; 2042 u8 reserved_at_160[0x3a0]; 2043 }; 2044 2045 struct mlx5_ifc_query_tis_out_bits { 2046 u8 status[0x8]; 2047 u8 reserved_at_8[0x18]; 2048 u8 syndrome[0x20]; 2049 u8 reserved_at_40[0x40]; 2050 struct mlx5_ifc_tisc_bits tis_context; 2051 }; 2052 2053 struct mlx5_ifc_query_tis_in_bits { 2054 u8 opcode[0x10]; 2055 u8 reserved_at_10[0x10]; 2056 u8 reserved_at_20[0x10]; 2057 u8 op_mod[0x10]; 2058 u8 reserved_at_40[0x8]; 2059 u8 tisn[0x18]; 2060 u8 reserved_at_60[0x20]; 2061 }; 2062 2063 /* port_select_mode definition. */ 2064 enum mlx5_lag_mode_type { 2065 MLX5_LAG_MODE_TIS = 0, 2066 MLX5_LAG_MODE_HASH = 1, 2067 }; 2068 2069 struct mlx5_ifc_lag_context_bits { 2070 u8 fdb_selection_mode[0x1]; 2071 u8 reserved_at_1[0x14]; 2072 u8 port_select_mode[0x3]; 2073 u8 reserved_at_18[0x5]; 2074 u8 lag_state[0x3]; 2075 u8 reserved_at_20[0x14]; 2076 u8 tx_remap_affinity_2[0x4]; 2077 u8 reserved_at_38[0x4]; 2078 u8 tx_remap_affinity_1[0x4]; 2079 }; 2080 2081 struct mlx5_ifc_query_lag_in_bits { 2082 u8 opcode[0x10]; 2083 u8 uid[0x10]; 2084 u8 reserved_at_20[0x10]; 2085 u8 op_mod[0x10]; 2086 u8 reserved_at_40[0x40]; 2087 }; 2088 2089 struct mlx5_ifc_query_lag_out_bits { 2090 u8 status[0x8]; 2091 u8 reserved_at_8[0x18]; 2092 u8 syndrome[0x20]; 2093 struct mlx5_ifc_lag_context_bits context; 2094 }; 2095 2096 struct mlx5_ifc_alloc_transport_domain_out_bits { 2097 u8 status[0x8]; 2098 u8 reserved_at_8[0x18]; 2099 u8 syndrome[0x20]; 2100 u8 reserved_at_40[0x8]; 2101 u8 transport_domain[0x18]; 2102 u8 reserved_at_60[0x20]; 2103 }; 2104 2105 struct mlx5_ifc_alloc_transport_domain_in_bits { 2106 u8 opcode[0x10]; 2107 u8 reserved_at_10[0x10]; 2108 u8 reserved_at_20[0x10]; 2109 u8 op_mod[0x10]; 2110 u8 reserved_at_40[0x40]; 2111 }; 2112 2113 enum { 2114 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 2115 MLX5_WQ_TYPE_CYCLIC = 0x1, 2116 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 2117 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 2118 }; 2119 2120 enum { 2121 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 2122 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 2123 }; 2124 2125 struct mlx5_ifc_wq_bits { 2126 u8 wq_type[0x4]; 2127 u8 wq_signature[0x1]; 2128 u8 end_padding_mode[0x2]; 2129 u8 cd_slave[0x1]; 2130 u8 reserved_at_8[0x18]; 2131 u8 hds_skip_first_sge[0x1]; 2132 u8 log2_hds_buf_size[0x3]; 2133 u8 reserved_at_24[0x7]; 2134 u8 page_offset[0x5]; 2135 u8 lwm[0x10]; 2136 u8 reserved_at_40[0x8]; 2137 u8 pd[0x18]; 2138 u8 reserved_at_60[0x8]; 2139 u8 uar_page[0x18]; 2140 u8 dbr_addr[0x40]; 2141 u8 hw_counter[0x20]; 2142 u8 sw_counter[0x20]; 2143 u8 reserved_at_100[0xc]; 2144 u8 log_wq_stride[0x4]; 2145 u8 reserved_at_110[0x3]; 2146 u8 log_wq_pg_sz[0x5]; 2147 u8 reserved_at_118[0x3]; 2148 u8 log_wq_sz[0x5]; 2149 u8 dbr_umem_valid[0x1]; 2150 u8 wq_umem_valid[0x1]; 2151 u8 reserved_at_122[0x1]; 2152 u8 log_hairpin_num_packets[0x5]; 2153 u8 reserved_at_128[0x3]; 2154 u8 log_hairpin_data_sz[0x5]; 2155 u8 reserved_at_130[0x4]; 2156 u8 single_wqe_log_num_of_strides[0x4]; 2157 u8 two_byte_shift_en[0x1]; 2158 u8 reserved_at_139[0x4]; 2159 u8 single_stride_log_num_of_bytes[0x3]; 2160 u8 dbr_umem_id[0x20]; 2161 u8 wq_umem_id[0x20]; 2162 u8 wq_umem_offset[0x40]; 2163 u8 reserved_at_1c0[0x440]; 2164 }; 2165 2166 enum { 2167 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2168 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2169 }; 2170 2171 enum { 2172 MLX5_RQC_STATE_RST = 0x0, 2173 MLX5_RQC_STATE_RDY = 0x1, 2174 MLX5_RQC_STATE_ERR = 0x3, 2175 }; 2176 2177 struct mlx5_ifc_rqc_bits { 2178 u8 rlky[0x1]; 2179 u8 delay_drop_en[0x1]; 2180 u8 scatter_fcs[0x1]; 2181 u8 vsd[0x1]; 2182 u8 mem_rq_type[0x4]; 2183 u8 state[0x4]; 2184 u8 reserved_at_c[0x1]; 2185 u8 flush_in_error_en[0x1]; 2186 u8 hairpin[0x1]; 2187 u8 reserved_at_f[0xB]; 2188 u8 ts_format[0x02]; 2189 u8 reserved_at_1c[0x4]; 2190 u8 reserved_at_20[0x8]; 2191 u8 user_index[0x18]; 2192 u8 reserved_at_40[0x8]; 2193 u8 cqn[0x18]; 2194 u8 counter_set_id[0x8]; 2195 u8 reserved_at_68[0x18]; 2196 u8 reserved_at_80[0x8]; 2197 u8 rmpn[0x18]; 2198 u8 reserved_at_a0[0x8]; 2199 u8 hairpin_peer_sq[0x18]; 2200 u8 reserved_at_c0[0x10]; 2201 u8 hairpin_peer_vhca[0x10]; 2202 u8 reserved_at_e0[0xa0]; 2203 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */ 2204 }; 2205 2206 struct mlx5_ifc_create_rq_out_bits { 2207 u8 status[0x8]; 2208 u8 reserved_at_8[0x18]; 2209 u8 syndrome[0x20]; 2210 u8 reserved_at_40[0x8]; 2211 u8 rqn[0x18]; 2212 u8 reserved_at_60[0x20]; 2213 }; 2214 2215 struct mlx5_ifc_create_rq_in_bits { 2216 u8 opcode[0x10]; 2217 u8 uid[0x10]; 2218 u8 reserved_at_20[0x10]; 2219 u8 op_mod[0x10]; 2220 u8 reserved_at_40[0xc0]; 2221 struct mlx5_ifc_rqc_bits ctx; 2222 }; 2223 2224 struct mlx5_ifc_modify_rq_out_bits { 2225 u8 status[0x8]; 2226 u8 reserved_at_8[0x18]; 2227 u8 syndrome[0x20]; 2228 u8 reserved_at_40[0x40]; 2229 }; 2230 2231 struct mlx5_ifc_query_rq_out_bits { 2232 u8 status[0x8]; 2233 u8 reserved_at_8[0x18]; 2234 u8 syndrome[0x20]; 2235 u8 reserved_at_40[0xc0]; 2236 struct mlx5_ifc_rqc_bits rq_context; 2237 }; 2238 2239 struct mlx5_ifc_query_rq_in_bits { 2240 u8 opcode[0x10]; 2241 u8 reserved_at_10[0x10]; 2242 u8 reserved_at_20[0x10]; 2243 u8 op_mod[0x10]; 2244 u8 reserved_at_40[0x8]; 2245 u8 rqn[0x18]; 2246 u8 reserved_at_60[0x20]; 2247 }; 2248 2249 enum { 2250 MLX5_RMPC_STATE_RDY = 0x1, 2251 MLX5_RMPC_STATE_ERR = 0x3, 2252 }; 2253 2254 struct mlx5_ifc_rmpc_bits { 2255 u8 reserved_at_0[0x8]; 2256 u8 state[0x4]; 2257 u8 reserved_at_c[0x14]; 2258 u8 basic_cyclic_rcv_wqe[0x1]; 2259 u8 reserved_at_21[0x1f]; 2260 u8 reserved_at_40[0x140]; 2261 struct mlx5_ifc_wq_bits wq; 2262 }; 2263 2264 struct mlx5_ifc_query_rmp_out_bits { 2265 u8 status[0x8]; 2266 u8 reserved_at_8[0x18]; 2267 u8 syndrome[0x20]; 2268 u8 reserved_at_40[0xc0]; 2269 struct mlx5_ifc_rmpc_bits rmp_context; 2270 }; 2271 2272 struct mlx5_ifc_query_rmp_in_bits { 2273 u8 opcode[0x10]; 2274 u8 reserved_at_10[0x10]; 2275 u8 reserved_at_20[0x10]; 2276 u8 op_mod[0x10]; 2277 u8 reserved_at_40[0x8]; 2278 u8 rmpn[0x18]; 2279 u8 reserved_at_60[0x20]; 2280 }; 2281 2282 struct mlx5_ifc_modify_rmp_out_bits { 2283 u8 status[0x8]; 2284 u8 reserved_at_8[0x18]; 2285 u8 syndrome[0x20]; 2286 u8 reserved_at_40[0x40]; 2287 }; 2288 2289 struct mlx5_ifc_rmp_bitmask_bits { 2290 u8 reserved_at_0[0x20]; 2291 u8 reserved_at_20[0x1f]; 2292 u8 lwm[0x1]; 2293 }; 2294 2295 struct mlx5_ifc_modify_rmp_in_bits { 2296 u8 opcode[0x10]; 2297 u8 uid[0x10]; 2298 u8 reserved_at_20[0x10]; 2299 u8 op_mod[0x10]; 2300 u8 rmp_state[0x4]; 2301 u8 reserved_at_44[0x4]; 2302 u8 rmpn[0x18]; 2303 u8 reserved_at_60[0x20]; 2304 struct mlx5_ifc_rmp_bitmask_bits bitmask; 2305 u8 reserved_at_c0[0x40]; 2306 struct mlx5_ifc_rmpc_bits ctx; 2307 }; 2308 2309 struct mlx5_ifc_create_rmp_out_bits { 2310 u8 status[0x8]; 2311 u8 reserved_at_8[0x18]; 2312 u8 syndrome[0x20]; 2313 u8 reserved_at_40[0x8]; 2314 u8 rmpn[0x18]; 2315 u8 reserved_at_60[0x20]; 2316 }; 2317 2318 struct mlx5_ifc_create_rmp_in_bits { 2319 u8 opcode[0x10]; 2320 u8 uid[0x10]; 2321 u8 reserved_at_20[0x10]; 2322 u8 op_mod[0x10]; 2323 u8 reserved_at_40[0xc0]; 2324 struct mlx5_ifc_rmpc_bits ctx; 2325 }; 2326 2327 struct mlx5_ifc_create_tis_out_bits { 2328 u8 status[0x8]; 2329 u8 reserved_at_8[0x18]; 2330 u8 syndrome[0x20]; 2331 u8 reserved_at_40[0x8]; 2332 u8 tisn[0x18]; 2333 u8 reserved_at_60[0x20]; 2334 }; 2335 2336 struct mlx5_ifc_create_tis_in_bits { 2337 u8 opcode[0x10]; 2338 u8 uid[0x10]; 2339 u8 reserved_at_20[0x10]; 2340 u8 op_mod[0x10]; 2341 u8 reserved_at_40[0xc0]; 2342 struct mlx5_ifc_tisc_bits ctx; 2343 }; 2344 2345 enum { 2346 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0, 2347 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 2348 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 2349 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 2350 }; 2351 2352 struct mlx5_ifc_modify_rq_in_bits { 2353 u8 opcode[0x10]; 2354 u8 uid[0x10]; 2355 u8 reserved_at_20[0x10]; 2356 u8 op_mod[0x10]; 2357 u8 rq_state[0x4]; 2358 u8 reserved_at_44[0x4]; 2359 u8 rqn[0x18]; 2360 u8 reserved_at_60[0x20]; 2361 u8 modify_bitmask[0x40]; 2362 u8 reserved_at_c0[0x40]; 2363 struct mlx5_ifc_rqc_bits ctx; 2364 }; 2365 2366 enum { 2367 MLX5_L3_PROT_TYPE_IPV4 = 0, 2368 MLX5_L3_PROT_TYPE_IPV6 = 1, 2369 }; 2370 2371 enum { 2372 MLX5_L4_PROT_TYPE_TCP = 0, 2373 MLX5_L4_PROT_TYPE_UDP = 1, 2374 }; 2375 2376 enum { 2377 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2378 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2379 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2380 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2381 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2382 }; 2383 2384 struct mlx5_ifc_rx_hash_field_select_bits { 2385 u8 l3_prot_type[0x1]; 2386 u8 l4_prot_type[0x1]; 2387 u8 selected_fields[0x1e]; 2388 }; 2389 2390 enum { 2391 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2392 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2393 }; 2394 2395 enum { 2396 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2397 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2398 }; 2399 2400 enum { 2401 MLX5_RX_HASH_FN_NONE = 0x0, 2402 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2403 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2404 }; 2405 2406 enum { 2407 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2408 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2409 }; 2410 2411 enum { 2412 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0, 2413 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1, 2414 }; 2415 2416 struct mlx5_ifc_tirc_bits { 2417 u8 reserved_at_0[0x20]; 2418 u8 disp_type[0x4]; 2419 u8 reserved_at_24[0x1c]; 2420 u8 reserved_at_40[0x40]; 2421 u8 reserved_at_80[0x4]; 2422 u8 lro_timeout_period_usecs[0x10]; 2423 u8 lro_enable_mask[0x4]; 2424 u8 lro_max_msg_sz[0x8]; 2425 u8 reserved_at_a0[0x40]; 2426 u8 reserved_at_e0[0x8]; 2427 u8 inline_rqn[0x18]; 2428 u8 rx_hash_symmetric[0x1]; 2429 u8 reserved_at_101[0x1]; 2430 u8 tunneled_offload_en[0x1]; 2431 u8 reserved_at_103[0x5]; 2432 u8 indirect_table[0x18]; 2433 u8 rx_hash_fn[0x4]; 2434 u8 reserved_at_124[0x2]; 2435 u8 self_lb_block[0x2]; 2436 u8 transport_domain[0x18]; 2437 u8 rx_hash_toeplitz_key[10][0x20]; 2438 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2439 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2440 u8 reserved_at_2c0[0x4c0]; 2441 }; 2442 2443 struct mlx5_ifc_create_tir_out_bits { 2444 u8 status[0x8]; 2445 u8 reserved_at_8[0x18]; 2446 u8 syndrome[0x20]; 2447 u8 reserved_at_40[0x8]; 2448 u8 tirn[0x18]; 2449 u8 reserved_at_60[0x20]; 2450 }; 2451 2452 struct mlx5_ifc_create_tir_in_bits { 2453 u8 opcode[0x10]; 2454 u8 uid[0x10]; 2455 u8 reserved_at_20[0x10]; 2456 u8 op_mod[0x10]; 2457 u8 reserved_at_40[0xc0]; 2458 struct mlx5_ifc_tirc_bits ctx; 2459 }; 2460 2461 enum { 2462 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0, 2463 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1, 2464 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2, 2465 /* bit 3 - tunneled_offload_en modify not supported. */ 2466 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4, 2467 }; 2468 2469 struct mlx5_ifc_modify_tir_out_bits { 2470 u8 status[0x8]; 2471 u8 reserved_at_8[0x18]; 2472 u8 syndrome[0x20]; 2473 u8 reserved_at_40[0x40]; 2474 }; 2475 2476 struct mlx5_ifc_modify_tir_in_bits { 2477 u8 opcode[0x10]; 2478 u8 uid[0x10]; 2479 u8 reserved_at_20[0x10]; 2480 u8 op_mod[0x10]; 2481 u8 reserved_at_40[0x8]; 2482 u8 tirn[0x18]; 2483 u8 reserved_at_60[0x20]; 2484 u8 modify_bitmask[0x40]; 2485 u8 reserved_at_c0[0x40]; 2486 struct mlx5_ifc_tirc_bits ctx; 2487 }; 2488 2489 enum { 2490 MLX5_INLINE_Q_TYPE_RQ = 0x0, 2491 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1, 2492 }; 2493 2494 struct mlx5_ifc_rq_num_bits { 2495 u8 reserved_at_0[0x8]; 2496 u8 rq_num[0x18]; 2497 }; 2498 2499 struct mlx5_ifc_rqtc_bits { 2500 u8 reserved_at_0[0xa5]; 2501 u8 list_q_type[0x3]; 2502 u8 reserved_at_a8[0x8]; 2503 u8 rqt_max_size[0x10]; 2504 u8 reserved_at_c0[0x10]; 2505 u8 rqt_actual_size[0x10]; 2506 u8 reserved_at_e0[0x6a0]; 2507 struct mlx5_ifc_rq_num_bits rq_num[]; 2508 }; 2509 2510 struct mlx5_ifc_create_rqt_out_bits { 2511 u8 status[0x8]; 2512 u8 reserved_at_8[0x18]; 2513 u8 syndrome[0x20]; 2514 u8 reserved_at_40[0x8]; 2515 u8 rqtn[0x18]; 2516 u8 reserved_at_60[0x20]; 2517 }; 2518 2519 #ifdef PEDANTIC 2520 #pragma GCC diagnostic ignored "-Wpedantic" 2521 #endif 2522 struct mlx5_ifc_create_rqt_in_bits { 2523 u8 opcode[0x10]; 2524 u8 uid[0x10]; 2525 u8 reserved_at_20[0x10]; 2526 u8 op_mod[0x10]; 2527 u8 reserved_at_40[0xc0]; 2528 struct mlx5_ifc_rqtc_bits rqt_context; 2529 }; 2530 2531 struct mlx5_ifc_modify_rqt_in_bits { 2532 u8 opcode[0x10]; 2533 u8 uid[0x10]; 2534 u8 reserved_at_20[0x10]; 2535 u8 op_mod[0x10]; 2536 u8 reserved_at_40[0x8]; 2537 u8 rqtn[0x18]; 2538 u8 reserved_at_60[0x20]; 2539 u8 modify_bitmask[0x40]; 2540 u8 reserved_at_c0[0x40]; 2541 struct mlx5_ifc_rqtc_bits rqt_context; 2542 }; 2543 #ifdef PEDANTIC 2544 #pragma GCC diagnostic error "-Wpedantic" 2545 #endif 2546 2547 struct mlx5_ifc_modify_rqt_out_bits { 2548 u8 status[0x8]; 2549 u8 reserved_at_8[0x18]; 2550 u8 syndrome[0x20]; 2551 u8 reserved_at_40[0x40]; 2552 }; 2553 2554 enum { 2555 MLX5_SQC_STATE_RST = 0x0, 2556 MLX5_SQC_STATE_RDY = 0x1, 2557 MLX5_SQC_STATE_ERR = 0x3, 2558 }; 2559 2560 struct mlx5_ifc_sqc_bits { 2561 u8 rlky[0x1]; 2562 u8 cd_master[0x1]; 2563 u8 fre[0x1]; 2564 u8 flush_in_error_en[0x1]; 2565 u8 allow_multi_pkt_send_wqe[0x1]; 2566 u8 min_wqe_inline_mode[0x3]; 2567 u8 state[0x4]; 2568 u8 reg_umr[0x1]; 2569 u8 allow_swp[0x1]; 2570 u8 hairpin[0x1]; 2571 u8 non_wire[0x1]; 2572 u8 static_sq_wq[0x1]; 2573 u8 reserved_at_11[0x9]; 2574 u8 ts_format[0x02]; 2575 u8 reserved_at_1c[0x4]; 2576 u8 reserved_at_20[0x8]; 2577 u8 user_index[0x18]; 2578 u8 reserved_at_40[0x8]; 2579 u8 cqn[0x18]; 2580 u8 reserved_at_60[0x8]; 2581 u8 hairpin_peer_rq[0x18]; 2582 u8 reserved_at_80[0x10]; 2583 u8 hairpin_peer_vhca[0x10]; 2584 u8 reserved_at_a0[0x50]; 2585 u8 packet_pacing_rate_limit_index[0x10]; 2586 u8 tis_lst_sz[0x10]; 2587 u8 reserved_at_110[0x10]; 2588 u8 reserved_at_120[0x40]; 2589 u8 reserved_at_160[0x8]; 2590 u8 tis_num_0[0x18]; 2591 struct mlx5_ifc_wq_bits wq; 2592 }; 2593 2594 struct mlx5_ifc_query_sq_in_bits { 2595 u8 opcode[0x10]; 2596 u8 reserved_at_10[0x10]; 2597 u8 reserved_at_20[0x10]; 2598 u8 op_mod[0x10]; 2599 u8 reserved_at_40[0x8]; 2600 u8 sqn[0x18]; 2601 u8 reserved_at_60[0x20]; 2602 }; 2603 2604 struct mlx5_ifc_modify_sq_out_bits { 2605 u8 status[0x8]; 2606 u8 reserved_at_8[0x18]; 2607 u8 syndrome[0x20]; 2608 u8 reserved_at_40[0x40]; 2609 }; 2610 2611 struct mlx5_ifc_modify_sq_in_bits { 2612 u8 opcode[0x10]; 2613 u8 uid[0x10]; 2614 u8 reserved_at_20[0x10]; 2615 u8 op_mod[0x10]; 2616 u8 sq_state[0x4]; 2617 u8 reserved_at_44[0x4]; 2618 u8 sqn[0x18]; 2619 u8 reserved_at_60[0x20]; 2620 u8 modify_bitmask[0x40]; 2621 u8 reserved_at_c0[0x40]; 2622 struct mlx5_ifc_sqc_bits ctx; 2623 }; 2624 2625 struct mlx5_ifc_create_sq_out_bits { 2626 u8 status[0x8]; 2627 u8 reserved_at_8[0x18]; 2628 u8 syndrome[0x20]; 2629 u8 reserved_at_40[0x8]; 2630 u8 sqn[0x18]; 2631 u8 reserved_at_60[0x20]; 2632 }; 2633 2634 struct mlx5_ifc_create_sq_in_bits { 2635 u8 opcode[0x10]; 2636 u8 uid[0x10]; 2637 u8 reserved_at_20[0x10]; 2638 u8 op_mod[0x10]; 2639 u8 reserved_at_40[0xc0]; 2640 struct mlx5_ifc_sqc_bits ctx; 2641 }; 2642 2643 enum { 2644 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0), 2645 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1), 2646 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2), 2647 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3), 2648 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4), 2649 }; 2650 2651 struct mlx5_ifc_flow_meter_parameters_bits { 2652 u8 valid[0x1]; 2653 u8 bucket_overflow[0x1]; 2654 u8 start_color[0x2]; 2655 u8 both_buckets_on_green[0x1]; 2656 u8 meter_mode[0x2]; 2657 u8 reserved_at_1[0x19]; 2658 u8 reserved_at_2[0x20]; 2659 u8 reserved_at_3[0x3]; 2660 u8 cbs_exponent[0x5]; 2661 u8 cbs_mantissa[0x8]; 2662 u8 reserved_at_4[0x3]; 2663 u8 cir_exponent[0x5]; 2664 u8 cir_mantissa[0x8]; 2665 u8 reserved_at_5[0x20]; 2666 u8 reserved_at_6[0x3]; 2667 u8 ebs_exponent[0x5]; 2668 u8 ebs_mantissa[0x8]; 2669 u8 reserved_at_7[0x3]; 2670 u8 eir_exponent[0x5]; 2671 u8 eir_mantissa[0x8]; 2672 u8 reserved_at_8[0x60]; 2673 }; 2674 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF) 2675 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8 2676 2677 enum { 2678 MLX5_METER_MODE_IP_LEN = 0x0, 2679 MLX5_METER_MODE_L2_LEN = 0x1, 2680 MLX5_METER_MODE_L2_IPG_LEN = 0x2, 2681 MLX5_METER_MODE_PKT = 0x3, 2682 }; 2683 2684 enum { 2685 MLX5_CQE_SIZE_64B = 0x0, 2686 MLX5_CQE_SIZE_128B = 0x1, 2687 }; 2688 2689 struct mlx5_ifc_cqc_bits { 2690 u8 status[0x4]; 2691 u8 as_notify[0x1]; 2692 u8 initiator_src_dct[0x1]; 2693 u8 dbr_umem_valid[0x1]; 2694 u8 reserved_at_7[0x1]; 2695 u8 cqe_sz[0x3]; 2696 u8 cc[0x1]; 2697 u8 reserved_at_c[0x1]; 2698 u8 scqe_break_moderation_en[0x1]; 2699 u8 oi[0x1]; 2700 u8 cq_period_mode[0x2]; 2701 u8 cqe_comp_en[0x1]; 2702 u8 mini_cqe_res_format[0x2]; 2703 u8 st[0x4]; 2704 u8 reserved_at_18[0x1]; 2705 u8 cqe_comp_layout[0x7]; 2706 u8 dbr_umem_id[0x20]; 2707 u8 reserved_at_40[0x14]; 2708 u8 page_offset[0x6]; 2709 u8 reserved_at_5a[0x2]; 2710 u8 mini_cqe_res_format_ext[0x2]; 2711 u8 cq_timestamp_format[0x2]; 2712 u8 reserved_at_60[0x3]; 2713 u8 log_cq_size[0x5]; 2714 u8 uar_page[0x18]; 2715 u8 reserved_at_80[0x4]; 2716 u8 cq_period[0xc]; 2717 u8 cq_max_count[0x10]; 2718 u8 reserved_at_a0[0x18]; 2719 u8 c_eqn[0x8]; 2720 u8 reserved_at_c0[0x3]; 2721 u8 log_page_size[0x5]; 2722 u8 reserved_at_c8[0x18]; 2723 u8 reserved_at_e0[0x20]; 2724 u8 reserved_at_100[0x8]; 2725 u8 last_notified_index[0x18]; 2726 u8 reserved_at_120[0x8]; 2727 u8 last_solicit_index[0x18]; 2728 u8 reserved_at_140[0x8]; 2729 u8 consumer_counter[0x18]; 2730 u8 reserved_at_160[0x8]; 2731 u8 producer_counter[0x18]; 2732 u8 local_partition_id[0xc]; 2733 u8 process_id[0x14]; 2734 u8 reserved_at_1A0[0x20]; 2735 u8 dbr_addr[0x40]; 2736 }; 2737 2738 struct mlx5_ifc_health_buffer_bits { 2739 u8 reserved_0[0x100]; 2740 u8 assert_existptr[0x20]; 2741 u8 assert_callra[0x20]; 2742 u8 reserved_1[0x40]; 2743 u8 fw_version[0x20]; 2744 u8 hw_id[0x20]; 2745 u8 reserved_2[0x20]; 2746 u8 irisc_index[0x8]; 2747 u8 synd[0x8]; 2748 u8 ext_synd[0x10]; 2749 }; 2750 2751 struct mlx5_ifc_initial_seg_bits { 2752 u8 fw_rev_minor[0x10]; 2753 u8 fw_rev_major[0x10]; 2754 u8 cmd_interface_rev[0x10]; 2755 u8 fw_rev_subminor[0x10]; 2756 u8 reserved_0[0x40]; 2757 u8 cmdq_phy_addr_63_32[0x20]; 2758 u8 cmdq_phy_addr_31_12[0x14]; 2759 u8 reserved_1[0x2]; 2760 u8 nic_interface[0x2]; 2761 u8 log_cmdq_size[0x4]; 2762 u8 log_cmdq_stride[0x4]; 2763 u8 command_doorbell_vector[0x20]; 2764 u8 reserved_2[0xf00]; 2765 u8 initializing[0x1]; 2766 u8 nic_interface_supported[0x7]; 2767 u8 reserved_4[0x18]; 2768 struct mlx5_ifc_health_buffer_bits health_buffer; 2769 u8 no_dram_nic_offset[0x20]; 2770 u8 reserved_5[0x6de0]; 2771 u8 internal_timer_h[0x20]; 2772 u8 internal_timer_l[0x20]; 2773 u8 reserved_6[0x20]; 2774 u8 reserved_7[0x1f]; 2775 u8 clear_int[0x1]; 2776 u8 health_syndrome[0x8]; 2777 u8 health_counter[0x18]; 2778 u8 reserved_8[0x17fc0]; 2779 }; 2780 2781 struct mlx5_ifc_create_cq_out_bits { 2782 u8 status[0x8]; 2783 u8 reserved_at_8[0x18]; 2784 u8 syndrome[0x20]; 2785 u8 reserved_at_40[0x8]; 2786 u8 cqn[0x18]; 2787 u8 reserved_at_60[0x20]; 2788 }; 2789 2790 struct mlx5_ifc_create_cq_in_bits { 2791 u8 opcode[0x10]; 2792 u8 uid[0x10]; 2793 u8 reserved_at_20[0x10]; 2794 u8 op_mod[0x10]; 2795 u8 reserved_at_40[0x40]; 2796 struct mlx5_ifc_cqc_bits cq_context; 2797 u8 cq_umem_offset[0x40]; 2798 u8 cq_umem_id[0x20]; 2799 u8 cq_umem_valid[0x1]; 2800 u8 reserved_at_2e1[0x1f]; 2801 u8 reserved_at_300[0x580]; 2802 u8 pas[]; 2803 }; 2804 2805 enum { 2806 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 2807 MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c, 2808 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, 2809 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 2810 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d, 2811 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e, 2812 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f, 2813 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, 2814 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, 2815 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, 2816 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031, 2817 }; 2818 2819 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 2820 u8 opcode[0x10]; 2821 u8 reserved_at_10[0x20]; 2822 u8 obj_type[0x10]; 2823 u8 obj_id[0x20]; 2824 u8 reserved_at_60[0x3]; 2825 u8 log_obj_range[0x5]; 2826 u8 reserved_at_58[0x18]; 2827 }; 2828 2829 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 2830 u8 status[0x8]; 2831 u8 reserved_at_8[0x18]; 2832 u8 syndrome[0x20]; 2833 u8 obj_id[0x20]; 2834 u8 reserved_at_60[0x20]; 2835 }; 2836 2837 struct mlx5_ifc_virtio_q_counters_bits { 2838 u8 modify_field_select[0x40]; 2839 u8 reserved_at_40[0x40]; 2840 u8 received_desc[0x40]; 2841 u8 completed_desc[0x40]; 2842 u8 error_cqes[0x20]; 2843 u8 bad_desc_errors[0x20]; 2844 u8 exceed_max_chain[0x20]; 2845 u8 invalid_buffer[0x20]; 2846 u8 reserved_at_180[0x50]; 2847 }; 2848 2849 struct mlx5_ifc_geneve_tlv_option_bits { 2850 u8 modify_field_select[0x40]; 2851 u8 reserved_at_40[0x18]; 2852 u8 geneve_option_fte_index[0x8]; 2853 u8 option_class[0x10]; 2854 u8 option_type[0x8]; 2855 u8 reserved_at_78[0x3]; 2856 u8 option_data_length[0x5]; 2857 u8 reserved_at_80[0x180]; 2858 }; 2859 2860 struct mlx5_ifc_create_virtio_q_counters_in_bits { 2861 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2862 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 2863 }; 2864 2865 struct mlx5_ifc_query_virtio_q_counters_out_bits { 2866 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2867 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 2868 }; 2869 2870 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 2871 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2872 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 2873 }; 2874 2875 enum { 2876 MLX5_CRYPTO_KEY_SIZE_128b = 0x0, 2877 MLX5_CRYPTO_KEY_SIZE_256b = 0x1, 2878 }; 2879 2880 enum { 2881 MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1, 2882 MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2, 2883 MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3, 2884 MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4, 2885 MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5, 2886 MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6, 2887 }; 2888 2889 struct mlx5_ifc_dek_bits { 2890 u8 modify_field_select[0x40]; 2891 u8 state[0x8]; 2892 u8 reserved_at_48[0xc]; 2893 u8 key_size[0x4]; 2894 u8 has_keytag[0x1]; 2895 u8 reserved_at_59[0x3]; 2896 u8 key_purpose[0x4]; 2897 u8 reserved_at_60[0x8]; 2898 u8 pd[0x18]; 2899 u8 reserved_at_80[0x100]; 2900 u8 opaque[0x40]; 2901 u8 reserved_at_1c0[0x40]; 2902 u8 key[0x400]; 2903 u8 reserved_at_600[0x200]; 2904 }; 2905 2906 struct mlx5_ifc_create_dek_in_bits { 2907 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2908 struct mlx5_ifc_dek_bits dek; 2909 }; 2910 2911 struct mlx5_ifc_import_kek_bits { 2912 u8 modify_field_select[0x40]; 2913 u8 state[0x8]; 2914 u8 reserved_at_48[0xc]; 2915 u8 key_size[0x4]; 2916 u8 reserved_at_58[0x1a8]; 2917 u8 key[0x400]; 2918 u8 reserved_at_600[0x200]; 2919 }; 2920 2921 struct mlx5_ifc_create_import_kek_in_bits { 2922 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2923 struct mlx5_ifc_import_kek_bits import_kek; 2924 }; 2925 2926 enum { 2927 MLX5_CREDENTIAL_ROLE_OFFICER = 0x0, 2928 MLX5_CREDENTIAL_ROLE_USER = 0x1, 2929 }; 2930 2931 struct mlx5_ifc_credential_bits { 2932 u8 modify_field_select[0x40]; 2933 u8 state[0x8]; 2934 u8 reserved_at_48[0x10]; 2935 u8 credential_role[0x8]; 2936 u8 reserved_at_60[0x1a0]; 2937 u8 credential[0x180]; 2938 u8 reserved_at_380[0x480]; 2939 }; 2940 2941 struct mlx5_ifc_create_credential_in_bits { 2942 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2943 struct mlx5_ifc_credential_bits credential; 2944 }; 2945 2946 struct mlx5_ifc_crypto_login_bits { 2947 u8 modify_field_select[0x40]; 2948 u8 reserved_at_40[0x48]; 2949 u8 credential_pointer[0x18]; 2950 u8 reserved_at_a0[0x8]; 2951 u8 session_import_kek_ptr[0x18]; 2952 u8 reserved_at_c0[0x140]; 2953 u8 credential[0x180]; 2954 u8 reserved_at_380[0x480]; 2955 }; 2956 2957 struct mlx5_ifc_create_crypto_login_in_bits { 2958 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2959 struct mlx5_ifc_crypto_login_bits crypto_login; 2960 }; 2961 2962 enum { 2963 MLX5_VIRTQ_STATE_INIT = 0, 2964 MLX5_VIRTQ_STATE_RDY = 1, 2965 MLX5_VIRTQ_STATE_SUSPEND = 2, 2966 MLX5_VIRTQ_STATE_ERROR = 3, 2967 }; 2968 2969 enum { 2970 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0), 2971 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3), 2972 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4), 2973 }; 2974 2975 struct mlx5_ifc_virtio_q_bits { 2976 u8 virtio_q_type[0x8]; 2977 u8 reserved_at_8[0x5]; 2978 u8 event_mode[0x3]; 2979 u8 queue_index[0x10]; 2980 u8 full_emulation[0x1]; 2981 u8 virtio_version_1_0[0x1]; 2982 u8 reserved_at_22[0x2]; 2983 u8 offload_type[0x4]; 2984 u8 event_qpn_or_msix[0x18]; 2985 u8 doorbell_stride_idx[0x10]; 2986 u8 queue_size[0x10]; 2987 u8 device_emulation_id[0x20]; 2988 u8 desc_addr[0x40]; 2989 u8 used_addr[0x40]; 2990 u8 available_addr[0x40]; 2991 u8 virtio_q_mkey[0x20]; 2992 u8 reserved_at_160[0x18]; 2993 u8 error_type[0x8]; 2994 u8 umem_1_id[0x20]; 2995 u8 umem_1_size[0x20]; 2996 u8 umem_1_offset[0x40]; 2997 u8 umem_2_id[0x20]; 2998 u8 umem_2_size[0x20]; 2999 u8 umem_2_offset[0x40]; 3000 u8 umem_3_id[0x20]; 3001 u8 umem_3_size[0x20]; 3002 u8 umem_3_offset[0x40]; 3003 u8 counter_set_id[0x20]; 3004 u8 reserved_at_320[0x8]; 3005 u8 pd[0x18]; 3006 u8 reserved_at_340[0x2]; 3007 u8 queue_period_mode[0x2]; 3008 u8 queue_period_us[0xc]; 3009 u8 queue_max_count[0x10]; 3010 u8 reserved_at_360[0xa0]; 3011 }; 3012 3013 struct mlx5_ifc_virtio_net_q_bits { 3014 u8 modify_field_select[0x40]; 3015 u8 reserved_at_40[0x40]; 3016 u8 tso_ipv4[0x1]; 3017 u8 tso_ipv6[0x1]; 3018 u8 tx_csum[0x1]; 3019 u8 rx_csum[0x1]; 3020 u8 reserved_at_84[0x6]; 3021 u8 dirty_bitmap_dump_enable[0x1]; 3022 u8 vhost_log_page[0x5]; 3023 u8 reserved_at_90[0xc]; 3024 u8 state[0x4]; 3025 u8 reserved_at_a0[0x8]; 3026 u8 tisn_or_qpn[0x18]; 3027 u8 dirty_bitmap_mkey[0x20]; 3028 u8 dirty_bitmap_size[0x20]; 3029 u8 dirty_bitmap_addr[0x40]; 3030 u8 hw_available_index[0x10]; 3031 u8 hw_used_index[0x10]; 3032 u8 reserved_at_160[0xa0]; 3033 struct mlx5_ifc_virtio_q_bits virtio_q_context; 3034 }; 3035 3036 struct mlx5_ifc_create_virtq_in_bits { 3037 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3038 struct mlx5_ifc_virtio_net_q_bits virtq; 3039 }; 3040 3041 struct mlx5_ifc_query_virtq_out_bits { 3042 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3043 struct mlx5_ifc_virtio_net_q_bits virtq; 3044 }; 3045 3046 struct mlx5_ifc_flow_hit_aso_bits { 3047 u8 modify_field_select[0x40]; 3048 u8 reserved_at_40[0x48]; 3049 u8 access_pd[0x18]; 3050 u8 reserved_at_a0[0x160]; 3051 u8 flag[0x200]; 3052 }; 3053 3054 struct mlx5_ifc_create_flow_hit_aso_in_bits { 3055 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3056 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso; 3057 }; 3058 3059 struct mlx5_ifc_flow_meter_aso_bits { 3060 u8 modify_field_select[0x40]; 3061 u8 reserved_at_40[0x48]; 3062 u8 access_pd[0x18]; 3063 u8 reserved_at_a0[0x160]; 3064 u8 parameters[0x200]; 3065 }; 3066 3067 struct mlx5_ifc_create_flow_meter_aso_in_bits { 3068 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3069 struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso; 3070 }; 3071 3072 struct mlx5_ifc_tcp_window_params_bits { 3073 u8 max_ack[0x20]; 3074 u8 max_win[0x20]; 3075 u8 reply_end[0x20]; 3076 u8 sent_end[0x20]; 3077 }; 3078 3079 struct mlx5_ifc_conn_track_aso_bits { 3080 struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */ 3081 struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */ 3082 u8 last_end[0x20]; /* End of DW8. */ 3083 u8 last_ack[0x20]; /* End of DW9. */ 3084 u8 last_seq[0x20]; /* End of DW10. */ 3085 u8 last_win[0x10]; 3086 u8 reserved_at_170[0xa]; 3087 u8 last_dir[0x1]; 3088 u8 last_index[0x5]; /* End of DW11. */ 3089 u8 reserved_at_180[0x40]; /* End of DW13. */ 3090 u8 reply_direction_tcp_scale[0x4]; 3091 u8 reply_direction_tcp_close_initiated[0x1]; 3092 u8 reply_direction_tcp_liberal_enabled[0x1]; 3093 u8 reply_direction_tcp_data_unacked[0x1]; 3094 u8 reply_direction_tcp_max_ack[0x1]; 3095 u8 reserved_at_1c8[0x8]; 3096 u8 original_direction_tcp_scale[0x4]; 3097 u8 original_direction_tcp_close_initiated[0x1]; 3098 u8 original_direction_tcp_liberal_enabled[0x1]; 3099 u8 original_direction_tcp_data_unacked[0x1]; 3100 u8 original_direction_tcp_max_ack[0x1]; 3101 u8 reserved_at_1d8[0x8]; /* End of DW14. */ 3102 u8 valid[0x1]; 3103 u8 state[0x3]; 3104 u8 freeze_track[0x1]; 3105 u8 reserved_at_1e5[0xb]; 3106 u8 reserved_at_1f0[0x1]; 3107 u8 connection_assured[0x1]; 3108 u8 sack_permitted[0x1]; 3109 u8 challenged_acked[0x1]; 3110 u8 heartbeat[0x1]; 3111 u8 max_ack_window[0x3]; 3112 u8 reserved_at_1f8[0x1]; 3113 u8 retransmission_counter[0x3]; 3114 u8 retranmission_limit_exceeded[0x1]; 3115 u8 retranmission_limit[0x3]; /* End of DW15. */ 3116 }; 3117 3118 struct mlx5_ifc_conn_track_offload_bits { 3119 u8 modify_field_select[0x40]; 3120 u8 reserved_at_40[0x40]; 3121 u8 reserved_at_80[0x8]; 3122 u8 conn_track_aso_access_pd[0x18]; 3123 u8 reserved_at_a0[0x160]; 3124 struct mlx5_ifc_conn_track_aso_bits conn_track_aso; 3125 }; 3126 3127 struct mlx5_ifc_create_conn_track_aso_in_bits { 3128 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3129 struct mlx5_ifc_conn_track_offload_bits conn_track_offload; 3130 }; 3131 3132 enum mlx5_access_aso_opc_mod { 3133 ASO_OPC_MOD_IPSEC = 0x0, 3134 ASO_OPC_MOD_CONNECTION_TRACKING = 0x1, 3135 ASO_OPC_MOD_POLICER = 0x2, 3136 ASO_OPC_MOD_RACE_AVOIDANCE = 0x3, 3137 ASO_OPC_MOD_FLOW_HIT = 0x4, 3138 }; 3139 3140 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30 3141 3142 enum mlx5_aso_data_mask_mode { 3143 BITWISE_64BIT = 0x0, 3144 BYTEWISE_64BYTE = 0x1, 3145 CALCULATED_64BYTE = 0x2, 3146 }; 3147 3148 #define ASO_CSEG_COND_0_OPER_OFFSET 20 3149 #define ASO_CSEG_COND_1_OPER_OFFSET 16 3150 3151 enum mlx5_aso_pre_cond_op { 3152 ASO_OP_ALWAYS_FALSE = 0x0, 3153 ASO_OP_ALWAYS_TRUE = 0x1, 3154 ASO_OP_EQUAL = 0x2, 3155 ASO_OP_NOT_EQUAL = 0x3, 3156 ASO_OP_GREATER_OR_EQUAL = 0x4, 3157 ASO_OP_LESSER_OR_EQUAL = 0x5, 3158 ASO_OP_LESSER = 0x6, 3159 ASO_OP_GREATER = 0x7, 3160 ASO_OP_CYCLIC_GREATER = 0x8, 3161 ASO_OP_CYCLIC_LESSER = 0x9, 3162 }; 3163 3164 #define ASO_CSEG_COND_OPER_OFFSET 6 3165 3166 enum mlx5_aso_op { 3167 ASO_OPER_LOGICAL_AND = 0x0, 3168 ASO_OPER_LOGICAL_OR = 0x1, 3169 }; 3170 3171 /* ASO WQE CTRL segment. */ 3172 struct mlx5_aso_cseg { 3173 uint32_t va_h; 3174 uint32_t va_l_r; 3175 uint32_t lkey; 3176 uint32_t operand_masks; 3177 uint32_t condition_0_data; 3178 uint32_t condition_0_mask; 3179 uint32_t condition_1_data; 3180 uint32_t condition_1_mask; 3181 uint64_t bitwise_data; 3182 uint64_t data_mask; 3183 } __rte_packed; 3184 3185 /* A meter data segment - 2 per ASO WQE. */ 3186 struct mlx5_aso_mtr_dseg { 3187 uint32_t v_bo_sc_bbog_mm; 3188 /* 3189 * bit 31: valid, 30: bucket overflow, 28-29: start color, 3190 * 27: both buckets on green, 24-25: meter mode. 3191 */ 3192 uint32_t reserved; 3193 uint32_t cbs_cir; 3194 /* 3195 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 3196 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 3197 */ 3198 uint32_t c_tokens; 3199 uint32_t ebs_eir; 3200 /* 3201 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 3202 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 3203 */ 3204 uint32_t e_tokens; 3205 uint64_t timestamp; 3206 } __rte_packed; 3207 3208 #define ASO_DSEG_VALID_OFFSET 31 3209 #define ASO_DSEG_BO_OFFSET 30 3210 #define ASO_DSEG_SC_OFFSET 28 3211 #define ASO_DSEG_BBOG_OFFSET 27 3212 #define ASO_DSEG_MTR_MODE 24 3213 #define ASO_DSEG_CBS_EXP_OFFSET 24 3214 #define ASO_DSEG_CBS_MAN_OFFSET 16 3215 #define ASO_DSEG_XIR_EXP_MASK 0x1F 3216 #define ASO_DSEG_XIR_EXP_OFFSET 8 3217 #define ASO_DSEG_EBS_EXP_OFFSET 24 3218 #define ASO_DSEG_EBS_MAN_OFFSET 16 3219 #define ASO_DSEG_EXP_MASK 0x1F 3220 #define ASO_DSEG_MAN_MASK 0xFF 3221 3222 #define MLX5_ASO_WQE_DSEG_SIZE 0x40 3223 #define MLX5_ASO_METERS_PER_WQE 2 3224 #define MLX5_ASO_MTRS_PER_POOL 128 3225 3226 /* ASO WQE data segment. */ 3227 struct mlx5_aso_dseg { 3228 union { 3229 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE]; 3230 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE]; 3231 }; 3232 } __rte_packed; 3233 3234 /* ASO WQE. */ 3235 struct mlx5_aso_wqe { 3236 struct mlx5_wqe_cseg general_cseg; 3237 struct mlx5_aso_cseg aso_cseg; 3238 struct mlx5_aso_dseg aso_dseg; 3239 } __rte_packed; 3240 3241 enum { 3242 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, 3243 }; 3244 3245 enum { 3246 MLX5_QP_ST_RC = 0x0, 3247 }; 3248 3249 enum { 3250 MLX5_QP_PM_MIGRATED = 0x3, 3251 }; 3252 3253 enum { 3254 MLX5_NON_ZERO_RQ = 0x0, 3255 MLX5_SRQ_RQ = 0x1, 3256 MLX5_CRQ_RQ = 0x2, 3257 MLX5_ZERO_LEN_RQ = 0x3, 3258 }; 3259 3260 struct mlx5_ifc_ads_bits { 3261 u8 fl[0x1]; 3262 u8 free_ar[0x1]; 3263 u8 reserved_at_2[0xe]; 3264 u8 pkey_index[0x10]; 3265 u8 reserved_at_20[0x8]; 3266 u8 grh[0x1]; 3267 u8 mlid[0x7]; 3268 u8 rlid[0x10]; 3269 u8 ack_timeout[0x5]; 3270 u8 reserved_at_45[0x3]; 3271 u8 src_addr_index[0x8]; 3272 u8 reserved_at_50[0x4]; 3273 u8 stat_rate[0x4]; 3274 u8 hop_limit[0x8]; 3275 u8 reserved_at_60[0x4]; 3276 u8 tclass[0x8]; 3277 u8 flow_label[0x14]; 3278 u8 rgid_rip[16][0x8]; 3279 u8 reserved_at_100[0x4]; 3280 u8 f_dscp[0x1]; 3281 u8 f_ecn[0x1]; 3282 u8 reserved_at_106[0x1]; 3283 u8 f_eth_prio[0x1]; 3284 u8 ecn[0x2]; 3285 u8 dscp[0x6]; 3286 u8 udp_sport[0x10]; 3287 u8 dei_cfi[0x1]; 3288 u8 eth_prio[0x3]; 3289 u8 sl[0x4]; 3290 u8 vhca_port_num[0x8]; 3291 u8 rmac_47_32[0x10]; 3292 u8 rmac_31_0[0x20]; 3293 }; 3294 3295 struct mlx5_ifc_qpc_bits { 3296 u8 state[0x4]; 3297 u8 lag_tx_port_affinity[0x4]; 3298 u8 st[0x8]; 3299 u8 reserved_at_10[0x3]; 3300 u8 pm_state[0x2]; 3301 u8 reserved_at_15[0x1]; 3302 u8 req_e2e_credit_mode[0x2]; 3303 u8 offload_type[0x4]; 3304 u8 end_padding_mode[0x2]; 3305 u8 reserved_at_1e[0x2]; 3306 u8 wq_signature[0x1]; 3307 u8 block_lb_mc[0x1]; 3308 u8 atomic_like_write_en[0x1]; 3309 u8 latency_sensitive[0x1]; 3310 u8 reserved_at_24[0x1]; 3311 u8 drain_sigerr[0x1]; 3312 u8 reserved_at_26[0x2]; 3313 u8 pd[0x18]; 3314 u8 mtu[0x3]; 3315 u8 log_msg_max[0x5]; 3316 u8 reserved_at_48[0x1]; 3317 u8 log_rq_size[0x4]; 3318 u8 log_rq_stride[0x3]; 3319 u8 no_sq[0x1]; 3320 u8 log_sq_size[0x4]; 3321 u8 reserved_at_55[0x3]; 3322 u8 ts_format[0x2]; 3323 u8 reserved_at_5a[0x1]; 3324 u8 rlky[0x1]; 3325 u8 ulp_stateless_offload_mode[0x4]; 3326 u8 counter_set_id[0x8]; 3327 u8 uar_page[0x18]; 3328 u8 reserved_at_80[0x8]; 3329 u8 user_index[0x18]; 3330 u8 reserved_at_a0[0x3]; 3331 u8 log_page_size[0x5]; 3332 u8 remote_qpn[0x18]; 3333 struct mlx5_ifc_ads_bits primary_address_path; 3334 struct mlx5_ifc_ads_bits secondary_address_path; 3335 u8 log_ack_req_freq[0x4]; 3336 u8 reserved_at_384[0x4]; 3337 u8 log_sra_max[0x3]; 3338 u8 reserved_at_38b[0x2]; 3339 u8 retry_count[0x3]; 3340 u8 rnr_retry[0x3]; 3341 u8 reserved_at_393[0x1]; 3342 u8 fre[0x1]; 3343 u8 cur_rnr_retry[0x3]; 3344 u8 cur_retry_count[0x3]; 3345 u8 reserved_at_39b[0x5]; 3346 u8 reserved_at_3a0[0x20]; 3347 u8 reserved_at_3c0[0x8]; 3348 u8 next_send_psn[0x18]; 3349 u8 reserved_at_3e0[0x8]; 3350 u8 cqn_snd[0x18]; 3351 u8 reserved_at_400[0x8]; 3352 u8 deth_sqpn[0x18]; 3353 u8 reserved_at_420[0x20]; 3354 u8 reserved_at_440[0x8]; 3355 u8 last_acked_psn[0x18]; 3356 u8 reserved_at_460[0x8]; 3357 u8 ssn[0x18]; 3358 u8 reserved_at_480[0x8]; 3359 u8 log_rra_max[0x3]; 3360 u8 reserved_at_48b[0x1]; 3361 u8 atomic_mode[0x4]; 3362 u8 rre[0x1]; 3363 u8 rwe[0x1]; 3364 u8 rae[0x1]; 3365 u8 reserved_at_493[0x1]; 3366 u8 page_offset[0x6]; 3367 u8 reserved_at_49a[0x3]; 3368 u8 cd_slave_receive[0x1]; 3369 u8 cd_slave_send[0x1]; 3370 u8 cd_master[0x1]; 3371 u8 reserved_at_4a0[0x3]; 3372 u8 min_rnr_nak[0x5]; 3373 u8 next_rcv_psn[0x18]; 3374 u8 reserved_at_4c0[0x8]; 3375 u8 xrcd[0x18]; 3376 u8 reserved_at_4e0[0x8]; 3377 u8 cqn_rcv[0x18]; 3378 u8 dbr_addr[0x40]; 3379 u8 q_key[0x20]; 3380 u8 reserved_at_560[0x5]; 3381 u8 rq_type[0x3]; 3382 u8 srqn_rmpn_xrqn[0x18]; 3383 u8 reserved_at_580[0x8]; 3384 u8 rmsn[0x18]; 3385 u8 hw_sq_wqebb_counter[0x10]; 3386 u8 sw_sq_wqebb_counter[0x10]; 3387 u8 hw_rq_counter[0x20]; 3388 u8 sw_rq_counter[0x20]; 3389 u8 reserved_at_600[0x20]; 3390 u8 reserved_at_620[0xf]; 3391 u8 cgs[0x1]; 3392 u8 cs_req[0x8]; 3393 u8 cs_res[0x8]; 3394 u8 dc_access_key[0x40]; 3395 u8 reserved_at_680[0x3]; 3396 u8 dbr_umem_valid[0x1]; 3397 u8 reserved_at_684[0x9c]; 3398 u8 dbr_umem_id[0x20]; 3399 }; 3400 3401 struct mlx5_ifc_create_qp_out_bits { 3402 u8 status[0x8]; 3403 u8 reserved_at_8[0x18]; 3404 u8 syndrome[0x20]; 3405 u8 reserved_at_40[0x8]; 3406 u8 qpn[0x18]; 3407 u8 reserved_at_60[0x20]; 3408 }; 3409 3410 struct mlx5_ifc_qpc_extension_bits { 3411 u8 reserved_at_0[0x2]; 3412 u8 mmo[0x1]; 3413 u8 reserved_at_3[0x5fd]; 3414 }; 3415 3416 #ifdef PEDANTIC 3417 #pragma GCC diagnostic ignored "-Wpedantic" 3418 #endif 3419 struct mlx5_ifc_qpc_pas_list_bits { 3420 u8 pas[0][0x40]; 3421 }; 3422 3423 #ifdef PEDANTIC 3424 #pragma GCC diagnostic ignored "-Wpedantic" 3425 #endif 3426 struct mlx5_ifc_qpc_extension_and_pas_list_bits { 3427 struct mlx5_ifc_qpc_extension_bits qpc_data_extension; 3428 u8 pas[0][0x40]; 3429 }; 3430 3431 3432 #ifdef PEDANTIC 3433 #pragma GCC diagnostic ignored "-Wpedantic" 3434 #endif 3435 struct mlx5_ifc_create_qp_in_bits { 3436 u8 opcode[0x10]; 3437 u8 uid[0x10]; 3438 u8 reserved_at_20[0x10]; 3439 u8 op_mod[0x10]; 3440 u8 qpc_ext[0x1]; 3441 u8 reserved_at_41[0x3f]; 3442 u8 opt_param_mask[0x20]; 3443 u8 reserved_at_a0[0x20]; 3444 struct mlx5_ifc_qpc_bits qpc; 3445 u8 wq_umem_offset[0x40]; 3446 u8 wq_umem_id[0x20]; 3447 u8 wq_umem_valid[0x1]; 3448 u8 reserved_at_861[0x1f]; 3449 union { 3450 struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list; 3451 struct mlx5_ifc_qpc_extension_and_pas_list_bits 3452 qpc_extension_and_pas_list; 3453 }; 3454 }; 3455 #ifdef PEDANTIC 3456 #pragma GCC diagnostic error "-Wpedantic" 3457 #endif 3458 3459 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3460 u8 status[0x8]; 3461 u8 reserved_at_8[0x18]; 3462 u8 syndrome[0x20]; 3463 u8 reserved_at_40[0x40]; 3464 }; 3465 3466 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3467 u8 opcode[0x10]; 3468 u8 uid[0x10]; 3469 u8 reserved_at_20[0x10]; 3470 u8 op_mod[0x10]; 3471 u8 reserved_at_40[0x8]; 3472 u8 qpn[0x18]; 3473 u8 reserved_at_60[0x20]; 3474 u8 opt_param_mask[0x20]; 3475 u8 reserved_at_a0[0x20]; 3476 struct mlx5_ifc_qpc_bits qpc; 3477 u8 reserved_at_800[0x80]; 3478 }; 3479 3480 struct mlx5_ifc_sqd2rts_qp_out_bits { 3481 u8 status[0x8]; 3482 u8 reserved_at_8[0x18]; 3483 u8 syndrome[0x20]; 3484 u8 reserved_at_40[0x40]; 3485 }; 3486 3487 struct mlx5_ifc_sqd2rts_qp_in_bits { 3488 u8 opcode[0x10]; 3489 u8 uid[0x10]; 3490 u8 reserved_at_20[0x10]; 3491 u8 op_mod[0x10]; 3492 u8 reserved_at_40[0x8]; 3493 u8 qpn[0x18]; 3494 u8 reserved_at_60[0x20]; 3495 u8 opt_param_mask[0x20]; 3496 u8 reserved_at_a0[0x20]; 3497 struct mlx5_ifc_qpc_bits qpc; 3498 u8 reserved_at_800[0x80]; 3499 }; 3500 3501 struct mlx5_ifc_rts2rts_qp_out_bits { 3502 u8 status[0x8]; 3503 u8 reserved_at_8[0x18]; 3504 u8 syndrome[0x20]; 3505 u8 reserved_at_40[0x40]; 3506 }; 3507 3508 struct mlx5_ifc_rts2rts_qp_in_bits { 3509 u8 opcode[0x10]; 3510 u8 uid[0x10]; 3511 u8 reserved_at_20[0x10]; 3512 u8 op_mod[0x10]; 3513 u8 reserved_at_40[0x8]; 3514 u8 qpn[0x18]; 3515 u8 reserved_at_60[0x20]; 3516 u8 opt_param_mask[0x20]; 3517 u8 reserved_at_a0[0x20]; 3518 struct mlx5_ifc_qpc_bits qpc; 3519 u8 reserved_at_800[0x80]; 3520 }; 3521 3522 struct mlx5_ifc_rtr2rts_qp_out_bits { 3523 u8 status[0x8]; 3524 u8 reserved_at_8[0x18]; 3525 u8 syndrome[0x20]; 3526 u8 reserved_at_40[0x40]; 3527 }; 3528 3529 struct mlx5_ifc_rtr2rts_qp_in_bits { 3530 u8 opcode[0x10]; 3531 u8 uid[0x10]; 3532 u8 reserved_at_20[0x10]; 3533 u8 op_mod[0x10]; 3534 u8 reserved_at_40[0x8]; 3535 u8 qpn[0x18]; 3536 u8 reserved_at_60[0x20]; 3537 u8 opt_param_mask[0x20]; 3538 u8 reserved_at_a0[0x20]; 3539 struct mlx5_ifc_qpc_bits qpc; 3540 u8 reserved_at_800[0x80]; 3541 }; 3542 3543 struct mlx5_ifc_rst2init_qp_out_bits { 3544 u8 status[0x8]; 3545 u8 reserved_at_8[0x18]; 3546 u8 syndrome[0x20]; 3547 u8 reserved_at_40[0x40]; 3548 }; 3549 3550 struct mlx5_ifc_rst2init_qp_in_bits { 3551 u8 opcode[0x10]; 3552 u8 uid[0x10]; 3553 u8 reserved_at_20[0x10]; 3554 u8 op_mod[0x10]; 3555 u8 reserved_at_40[0x8]; 3556 u8 qpn[0x18]; 3557 u8 reserved_at_60[0x20]; 3558 u8 opt_param_mask[0x20]; 3559 u8 reserved_at_a0[0x20]; 3560 struct mlx5_ifc_qpc_bits qpc; 3561 u8 reserved_at_800[0x80]; 3562 }; 3563 3564 struct mlx5_ifc_init2rtr_qp_out_bits { 3565 u8 status[0x8]; 3566 u8 reserved_at_8[0x18]; 3567 u8 syndrome[0x20]; 3568 u8 reserved_at_40[0x40]; 3569 }; 3570 3571 struct mlx5_ifc_init2rtr_qp_in_bits { 3572 u8 opcode[0x10]; 3573 u8 uid[0x10]; 3574 u8 reserved_at_20[0x10]; 3575 u8 op_mod[0x10]; 3576 u8 reserved_at_40[0x8]; 3577 u8 qpn[0x18]; 3578 u8 reserved_at_60[0x20]; 3579 u8 opt_param_mask[0x20]; 3580 u8 reserved_at_a0[0x20]; 3581 struct mlx5_ifc_qpc_bits qpc; 3582 u8 reserved_at_800[0x80]; 3583 }; 3584 3585 struct mlx5_ifc_init2init_qp_out_bits { 3586 u8 status[0x8]; 3587 u8 reserved_at_8[0x18]; 3588 u8 syndrome[0x20]; 3589 u8 reserved_at_40[0x40]; 3590 }; 3591 3592 struct mlx5_ifc_init2init_qp_in_bits { 3593 u8 opcode[0x10]; 3594 u8 uid[0x10]; 3595 u8 reserved_at_20[0x10]; 3596 u8 op_mod[0x10]; 3597 u8 reserved_at_40[0x8]; 3598 u8 qpn[0x18]; 3599 u8 reserved_at_60[0x20]; 3600 u8 opt_param_mask[0x20]; 3601 u8 reserved_at_a0[0x20]; 3602 struct mlx5_ifc_qpc_bits qpc; 3603 u8 reserved_at_800[0x80]; 3604 }; 3605 3606 struct mlx5_ifc_dealloc_pd_out_bits { 3607 u8 status[0x8]; 3608 u8 reserved_0[0x18]; 3609 u8 syndrome[0x20]; 3610 u8 reserved_1[0x40]; 3611 }; 3612 3613 struct mlx5_ifc_dealloc_pd_in_bits { 3614 u8 opcode[0x10]; 3615 u8 reserved_0[0x10]; 3616 u8 reserved_1[0x10]; 3617 u8 op_mod[0x10]; 3618 u8 reserved_2[0x8]; 3619 u8 pd[0x18]; 3620 u8 reserved_3[0x20]; 3621 }; 3622 3623 struct mlx5_ifc_alloc_pd_out_bits { 3624 u8 status[0x8]; 3625 u8 reserved_0[0x18]; 3626 u8 syndrome[0x20]; 3627 u8 reserved_1[0x8]; 3628 u8 pd[0x18]; 3629 u8 reserved_2[0x20]; 3630 }; 3631 3632 struct mlx5_ifc_alloc_pd_in_bits { 3633 u8 opcode[0x10]; 3634 u8 reserved_0[0x10]; 3635 u8 reserved_1[0x10]; 3636 u8 op_mod[0x10]; 3637 u8 reserved_2[0x40]; 3638 }; 3639 3640 #ifdef PEDANTIC 3641 #pragma GCC diagnostic ignored "-Wpedantic" 3642 #endif 3643 struct mlx5_ifc_query_qp_out_bits { 3644 u8 status[0x8]; 3645 u8 reserved_at_8[0x18]; 3646 u8 syndrome[0x20]; 3647 u8 reserved_at_40[0x40]; 3648 u8 opt_param_mask[0x20]; 3649 u8 reserved_at_a0[0x20]; 3650 struct mlx5_ifc_qpc_bits qpc; 3651 u8 reserved_at_800[0x80]; 3652 u8 pas[0][0x40]; 3653 }; 3654 #ifdef PEDANTIC 3655 #pragma GCC diagnostic error "-Wpedantic" 3656 #endif 3657 3658 struct mlx5_ifc_query_qp_in_bits { 3659 u8 opcode[0x10]; 3660 u8 reserved_at_10[0x10]; 3661 u8 reserved_at_20[0x10]; 3662 u8 op_mod[0x10]; 3663 u8 reserved_at_40[0x8]; 3664 u8 qpn[0x18]; 3665 u8 reserved_at_60[0x20]; 3666 }; 3667 3668 enum { 3669 MLX5_DATA_RATE = 0x0, 3670 MLX5_WQE_RATE = 0x1, 3671 }; 3672 3673 struct mlx5_ifc_set_pp_rate_limit_context_bits { 3674 u8 rate_limit[0x20]; 3675 u8 burst_upper_bound[0x20]; 3676 u8 reserved_at_40[0xC]; 3677 u8 rate_mode[0x4]; 3678 u8 typical_packet_size[0x10]; 3679 u8 reserved_at_60[0x120]; 3680 }; 3681 3682 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u 3683 3684 #ifdef PEDANTIC 3685 #pragma GCC diagnostic ignored "-Wpedantic" 3686 #endif 3687 struct mlx5_ifc_access_register_out_bits { 3688 u8 status[0x8]; 3689 u8 reserved_at_8[0x18]; 3690 u8 syndrome[0x20]; 3691 u8 reserved_at_40[0x40]; 3692 u8 register_data[0][0x20]; 3693 }; 3694 3695 struct mlx5_ifc_access_register_in_bits { 3696 u8 opcode[0x10]; 3697 u8 reserved_at_10[0x10]; 3698 u8 reserved_at_20[0x10]; 3699 u8 op_mod[0x10]; 3700 u8 reserved_at_40[0x10]; 3701 u8 register_id[0x10]; 3702 u8 argument[0x20]; 3703 u8 register_data[0][0x20]; 3704 }; 3705 #ifdef PEDANTIC 3706 #pragma GCC diagnostic error "-Wpedantic" 3707 #endif 3708 3709 enum { 3710 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 3711 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 3712 }; 3713 3714 enum { 3715 MLX5_REGISTER_ID_MTUTC = 0x9055, 3716 MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002, 3717 MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, 3718 MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, 3719 MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, 3720 }; 3721 3722 struct mlx5_ifc_register_mtutc_bits { 3723 u8 time_stamp_mode[0x2]; 3724 u8 time_stamp_state[0x2]; 3725 u8 reserved_at_4[0x18]; 3726 u8 operation[0x4]; 3727 u8 freq_adjustment[0x20]; 3728 u8 reserved_at_40[0x40]; 3729 u8 utc_sec[0x20]; 3730 u8 utc_nsec[0x20]; 3731 u8 time_adjustment[0x20]; 3732 }; 3733 3734 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 3735 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 3736 3737 struct mlx5_ifc_crypto_operational_register_bits { 3738 u8 wrapped_crypto_operational[0x1]; 3739 u8 reserved_at_1[0x1b]; 3740 u8 kek_size[0x4]; 3741 u8 reserved_at_20[0x20]; 3742 u8 credential[0x140]; 3743 u8 kek[0x100]; 3744 u8 reserved_at_280[0x180]; 3745 }; 3746 3747 struct mlx5_ifc_crypto_commissioning_register_bits { 3748 u8 token[0x1]; /* TODO: add size after PRM update */ 3749 }; 3750 3751 struct mlx5_ifc_import_kek_handle_register_bits { 3752 struct mlx5_ifc_crypto_login_bits crypto_login_object; 3753 struct mlx5_ifc_import_kek_bits import_kek_object; 3754 u8 reserved_at_200[0x4]; 3755 u8 write_operation[0x4]; 3756 u8 import_kek_id[0x18]; 3757 u8 reserved_at_220[0xe0]; 3758 }; 3759 3760 struct mlx5_ifc_credential_handle_register_bits { 3761 struct mlx5_ifc_crypto_login_bits crypto_login_object; 3762 struct mlx5_ifc_credential_bits credential_object; 3763 u8 reserved_at_200[0x4]; 3764 u8 write_operation[0x4]; 3765 u8 credential_id[0x18]; 3766 u8 reserved_at_220[0xe0]; 3767 }; 3768 3769 enum { 3770 MLX5_REGISTER_ADD_OPERATION = 0x1, 3771 MLX5_REGISTER_DELETE_OPERATION = 0x2, 3772 }; 3773 3774 struct mlx5_ifc_parse_graph_arc_bits { 3775 u8 start_inner_tunnel[0x1]; 3776 u8 reserved_at_1[0x7]; 3777 u8 arc_parse_graph_node[0x8]; 3778 u8 compare_condition_value[0x10]; 3779 u8 parse_graph_node_handle[0x20]; 3780 u8 reserved_at_40[0x40]; 3781 }; 3782 3783 struct mlx5_ifc_parse_graph_flow_match_sample_bits { 3784 u8 flow_match_sample_en[0x1]; 3785 u8 reserved_at_1[0x3]; 3786 u8 flow_match_sample_offset_mode[0x4]; 3787 u8 reserved_at_5[0x8]; 3788 u8 flow_match_sample_field_offset[0x10]; 3789 u8 reserved_at_32[0x4]; 3790 u8 flow_match_sample_field_offset_shift[0x4]; 3791 u8 flow_match_sample_field_base_offset[0x8]; 3792 u8 reserved_at_48[0xd]; 3793 u8 flow_match_sample_tunnel_mode[0x3]; 3794 u8 flow_match_sample_field_offset_mask[0x20]; 3795 u8 flow_match_sample_field_id[0x20]; 3796 }; 3797 3798 struct mlx5_ifc_parse_graph_flex_bits { 3799 u8 modify_field_select[0x40]; 3800 u8 reserved_at_64[0x20]; 3801 u8 header_length_base_value[0x10]; 3802 u8 reserved_at_112[0x4]; 3803 u8 header_length_field_shift[0x4]; 3804 u8 reserved_at_120[0x4]; 3805 u8 header_length_mode[0x4]; 3806 u8 header_length_field_offset[0x10]; 3807 u8 next_header_field_offset[0x10]; 3808 u8 reserved_at_160[0x1b]; 3809 u8 next_header_field_size[0x5]; 3810 u8 header_length_field_mask[0x20]; 3811 u8 reserved_at_224[0x20]; 3812 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8]; 3813 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8]; 3814 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8]; 3815 }; 3816 3817 struct mlx5_ifc_create_flex_parser_in_bits { 3818 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3819 struct mlx5_ifc_parse_graph_flex_bits flex; 3820 }; 3821 3822 struct mlx5_ifc_create_flex_parser_out_bits { 3823 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3824 struct mlx5_ifc_parse_graph_flex_bits flex; 3825 }; 3826 3827 struct mlx5_ifc_parse_graph_flex_out_bits { 3828 u8 status[0x8]; 3829 u8 reserved_at_8[0x18]; 3830 u8 syndrome[0x20]; 3831 u8 reserved_at_40[0x40]; 3832 struct mlx5_ifc_parse_graph_flex_bits capability; 3833 }; 3834 3835 struct regexp_params_field_select_bits { 3836 u8 reserved_at_0[0x1d]; 3837 u8 rof_mkey[0x1]; 3838 u8 stop_engine[0x1]; 3839 u8 reserved_at_1f[0x1]; 3840 }; 3841 3842 struct mlx5_ifc_regexp_params_bits { 3843 u8 reserved_at_0[0x1f]; 3844 u8 stop_engine[0x1]; 3845 u8 reserved_at_20[0x60]; 3846 u8 rof_mkey[0x20]; 3847 u8 rof_size[0x20]; 3848 u8 rof_mkey_va[0x40]; 3849 u8 reserved_at_100[0x80]; 3850 }; 3851 3852 struct mlx5_ifc_set_regexp_params_in_bits { 3853 u8 opcode[0x10]; 3854 u8 uid[0x10]; 3855 u8 reserved_at_20[0x10]; 3856 u8 op_mod[0x10]; 3857 u8 reserved_at_40[0x18]; 3858 u8 engine_id[0x8]; 3859 struct regexp_params_field_select_bits field_select; 3860 struct mlx5_ifc_regexp_params_bits regexp_params; 3861 }; 3862 3863 struct mlx5_ifc_set_regexp_params_out_bits { 3864 u8 status[0x8]; 3865 u8 reserved_at_8[0x18]; 3866 u8 syndrome[0x20]; 3867 u8 reserved_at_18[0x40]; 3868 }; 3869 3870 struct mlx5_ifc_query_regexp_params_in_bits { 3871 u8 opcode[0x10]; 3872 u8 uid[0x10]; 3873 u8 reserved_at_20[0x10]; 3874 u8 op_mod[0x10]; 3875 u8 reserved_at_40[0x18]; 3876 u8 engine_id[0x8]; 3877 u8 reserved[0x20]; 3878 }; 3879 3880 struct mlx5_ifc_query_regexp_params_out_bits { 3881 u8 status[0x8]; 3882 u8 reserved_at_8[0x18]; 3883 u8 syndrome[0x20]; 3884 u8 reserved[0x40]; 3885 struct mlx5_ifc_regexp_params_bits regexp_params; 3886 }; 3887 3888 struct mlx5_ifc_set_regexp_register_in_bits { 3889 u8 opcode[0x10]; 3890 u8 uid[0x10]; 3891 u8 reserved_at_20[0x10]; 3892 u8 op_mod[0x10]; 3893 u8 reserved_at_40[0x18]; 3894 u8 engine_id[0x8]; 3895 u8 register_address[0x20]; 3896 u8 register_data[0x20]; 3897 u8 reserved[0x60]; 3898 }; 3899 3900 struct mlx5_ifc_set_regexp_register_out_bits { 3901 u8 status[0x8]; 3902 u8 reserved_at_8[0x18]; 3903 u8 syndrome[0x20]; 3904 u8 reserved[0x40]; 3905 }; 3906 3907 struct mlx5_ifc_query_regexp_register_in_bits { 3908 u8 opcode[0x10]; 3909 u8 uid[0x10]; 3910 u8 reserved_at_20[0x10]; 3911 u8 op_mod[0x10]; 3912 u8 reserved_at_40[0x18]; 3913 u8 engine_id[0x8]; 3914 u8 register_address[0x20]; 3915 }; 3916 3917 struct mlx5_ifc_query_regexp_register_out_bits { 3918 u8 status[0x8]; 3919 u8 reserved_at_8[0x18]; 3920 u8 syndrome[0x20]; 3921 u8 reserved[0x20]; 3922 u8 register_data[0x20]; 3923 }; 3924 3925 /* Queue counters. */ 3926 struct mlx5_ifc_alloc_q_counter_out_bits { 3927 u8 status[0x8]; 3928 u8 reserved_at_8[0x18]; 3929 u8 syndrome[0x20]; 3930 u8 reserved_at_40[0x18]; 3931 u8 counter_set_id[0x8]; 3932 u8 reserved_at_60[0x20]; 3933 }; 3934 3935 struct mlx5_ifc_alloc_q_counter_in_bits { 3936 u8 opcode[0x10]; 3937 u8 uid[0x10]; 3938 u8 reserved_at_20[0x10]; 3939 u8 op_mod[0x10]; 3940 u8 reserved_at_40[0x40]; 3941 }; 3942 3943 struct mlx5_ifc_query_q_counter_out_bits { 3944 u8 status[0x8]; 3945 u8 reserved_at_8[0x18]; 3946 u8 syndrome[0x20]; 3947 u8 reserved_at_40[0x40]; 3948 u8 rx_write_requests[0x20]; 3949 u8 reserved_at_a0[0x20]; 3950 u8 rx_read_requests[0x20]; 3951 u8 reserved_at_e0[0x20]; 3952 u8 rx_atomic_requests[0x20]; 3953 u8 reserved_at_120[0x20]; 3954 u8 rx_dct_connect[0x20]; 3955 u8 reserved_at_160[0x20]; 3956 u8 out_of_buffer[0x20]; 3957 u8 reserved_at_1a0[0x20]; 3958 u8 out_of_sequence[0x20]; 3959 u8 reserved_at_1e0[0x20]; 3960 u8 duplicate_request[0x20]; 3961 u8 reserved_at_220[0x20]; 3962 u8 rnr_nak_retry_err[0x20]; 3963 u8 reserved_at_260[0x20]; 3964 u8 packet_seq_err[0x20]; 3965 u8 reserved_at_2a0[0x20]; 3966 u8 implied_nak_seq_err[0x20]; 3967 u8 reserved_at_2e0[0x20]; 3968 u8 local_ack_timeout_err[0x20]; 3969 u8 reserved_at_320[0xa0]; 3970 u8 resp_local_length_error[0x20]; 3971 u8 req_local_length_error[0x20]; 3972 u8 resp_local_qp_error[0x20]; 3973 u8 local_operation_error[0x20]; 3974 u8 resp_local_protection[0x20]; 3975 u8 req_local_protection[0x20]; 3976 u8 resp_cqe_error[0x20]; 3977 u8 req_cqe_error[0x20]; 3978 u8 req_mw_binding[0x20]; 3979 u8 req_bad_response[0x20]; 3980 u8 req_remote_invalid_request[0x20]; 3981 u8 resp_remote_invalid_request[0x20]; 3982 u8 req_remote_access_errors[0x20]; 3983 u8 resp_remote_access_errors[0x20]; 3984 u8 req_remote_operation_errors[0x20]; 3985 u8 req_transport_retries_exceeded[0x20]; 3986 u8 cq_overflow[0x20]; 3987 u8 resp_cqe_flush_error[0x20]; 3988 u8 req_cqe_flush_error[0x20]; 3989 u8 reserved_at_620[0x1e0]; 3990 }; 3991 3992 struct mlx5_ifc_query_q_counter_in_bits { 3993 u8 opcode[0x10]; 3994 u8 uid[0x10]; 3995 u8 reserved_at_20[0x10]; 3996 u8 op_mod[0x10]; 3997 u8 reserved_at_40[0x80]; 3998 u8 clear[0x1]; 3999 u8 reserved_at_c1[0x1f]; 4000 u8 reserved_at_e0[0x18]; 4001 u8 counter_set_id[0x8]; 4002 }; 4003 4004 /* CQE format mask. */ 4005 #define MLX5E_CQE_FORMAT_MASK 0xc 4006 4007 /* MPW opcode. */ 4008 #define MLX5_OPC_MOD_MPW 0x01 4009 4010 /* Compressed Rx CQE structure. */ 4011 struct mlx5_mini_cqe8 { 4012 union { 4013 uint32_t rx_hash_result; 4014 struct { 4015 union { 4016 uint16_t checksum; 4017 uint16_t flow_tag_high; 4018 struct { 4019 uint8_t reserved; 4020 uint8_t hdr_type; 4021 }; 4022 }; 4023 uint16_t stride_idx; 4024 }; 4025 struct { 4026 uint16_t wqe_counter; 4027 uint8_t s_wqe_opcode; 4028 uint8_t reserved; 4029 } s_wqe_info; 4030 }; 4031 union { 4032 uint32_t byte_cnt_flow; 4033 uint32_t byte_cnt; 4034 }; 4035 }; 4036 4037 /* Mini CQE responder format. */ 4038 enum { 4039 MLX5_CQE_RESP_FORMAT_HASH = 0x0, 4040 MLX5_CQE_RESP_FORMAT_CSUM = 0x1, 4041 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2, 4042 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3, 4043 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4, 4044 }; 4045 4046 /* srTCM PRM flow meter parameters. */ 4047 enum { 4048 MLX5_FLOW_COLOR_RED = 0, 4049 MLX5_FLOW_COLOR_YELLOW, 4050 MLX5_FLOW_COLOR_GREEN, 4051 MLX5_FLOW_COLOR_UNDEFINED, 4052 }; 4053 4054 /* Maximum value of srTCM & trTCM metering parameters. */ 4055 #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F)) 4056 #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF) 4057 4058 /* The bits meter color use. */ 4059 #define MLX5_MTR_COLOR_BITS 8 4060 4061 /* The bit size of one register. */ 4062 #define MLX5_REG_BITS 32 4063 4064 /* Idle bits for non-color usage in color register. */ 4065 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS) 4066 4067 /* Length mode of dynamic flex parser graph node. */ 4068 enum mlx5_parse_graph_node_len_mode { 4069 MLX5_GRAPH_NODE_LEN_FIXED = 0x0, 4070 MLX5_GRAPH_NODE_LEN_FIELD = 0x1, 4071 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2, 4072 }; 4073 4074 /* Offset mode of the samples of flex parser. */ 4075 enum mlx5_parse_graph_flow_match_sample_offset_mode { 4076 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0, 4077 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1, 4078 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, 4079 }; 4080 4081 enum mlx5_parse_graph_flow_match_sample_tunnel_mode { 4082 MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0, 4083 MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1, 4084 MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2 4085 }; 4086 4087 /* Node index for an input / output arc of the flex parser graph. */ 4088 enum mlx5_parse_graph_arc_node_index { 4089 MLX5_GRAPH_ARC_NODE_NULL = 0x0, 4090 MLX5_GRAPH_ARC_NODE_HEAD = 0x1, 4091 MLX5_GRAPH_ARC_NODE_MAC = 0x2, 4092 MLX5_GRAPH_ARC_NODE_IP = 0x3, 4093 MLX5_GRAPH_ARC_NODE_GRE = 0x4, 4094 MLX5_GRAPH_ARC_NODE_UDP = 0x5, 4095 MLX5_GRAPH_ARC_NODE_MPLS = 0x6, 4096 MLX5_GRAPH_ARC_NODE_TCP = 0x7, 4097 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, 4098 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, 4099 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, 4100 MLX5_GRAPH_ARC_NODE_IPV4 = 0xb, 4101 MLX5_GRAPH_ARC_NODE_IPV6 = 0xc, 4102 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, 4103 }; 4104 4105 #define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8 4106 #define MLX5_PARSE_GRAPH_IN_ARC_MAX 8 4107 #define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8 4108 4109 /** 4110 * Convert a user mark to flow mark. 4111 * 4112 * @param val 4113 * Mark value to convert. 4114 * 4115 * @return 4116 * Converted mark value. 4117 */ 4118 static inline uint32_t 4119 mlx5_flow_mark_set(uint32_t val) 4120 { 4121 uint32_t ret; 4122 4123 /* 4124 * Add one to the user value to differentiate un-marked flows from 4125 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it 4126 * remains untouched. 4127 */ 4128 if (val != MLX5_FLOW_MARK_DEFAULT) 4129 ++val; 4130 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 4131 /* 4132 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit 4133 * word, byte-swapped by the kernel on little-endian systems. In this 4134 * case, left-shifting the resulting big-endian value ensures the 4135 * least significant 24 bits are retained when converting it back. 4136 */ 4137 ret = rte_cpu_to_be_32(val) >> 8; 4138 #else 4139 ret = val; 4140 #endif 4141 return ret; 4142 } 4143 4144 /** 4145 * Convert a mark to user mark. 4146 * 4147 * @param val 4148 * Mark value to convert. 4149 * 4150 * @return 4151 * Converted mark value. 4152 */ 4153 static inline uint32_t 4154 mlx5_flow_mark_get(uint32_t val) 4155 { 4156 /* 4157 * Subtract one from the retrieved value. It was added by 4158 * mlx5_flow_mark_set() to distinguish unmarked flows. 4159 */ 4160 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 4161 return (val >> 8) - 1; 4162 #else 4163 return val - 1; 4164 #endif 4165 } 4166 4167 /** 4168 * Convert a timestamp format to configure settings in the queue context. 4169 * 4170 * @param val 4171 * timestamp format supported by the queue. 4172 * 4173 * @return 4174 * Converted timstamp format settings. 4175 */ 4176 static inline uint32_t 4177 mlx5_ts_format_conv(uint32_t ts_format) 4178 { 4179 return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ? 4180 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : 4181 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; 4182 } 4183 4184 #endif /* RTE_PMD_MLX5_PRM_H_ */ 4185