1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_PRM_H_ 7 #define RTE_PMD_MLX5_PRM_H_ 8 9 #include <unistd.h> 10 11 #include <rte_vect.h> 12 #include <rte_byteorder.h> 13 14 #include <mlx5_glue.h> 15 #include "mlx5_autoconf.h" 16 17 /* RSS hash key size. */ 18 #define MLX5_RSS_HASH_KEY_LEN 40 19 20 /* Get CQE owner bit. */ 21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK) 22 23 /* Get CQE format. */ 24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2) 25 26 /* Get CQE opcode. */ 27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4) 28 29 /* Get CQE solicited event. */ 30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1) 31 32 /* Invalidate a CQE. */ 33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4) 34 35 /* Hardware index widths. */ 36 #define MLX5_CQ_INDEX_WIDTH 24 37 #define MLX5_WQ_INDEX_WIDTH 16 38 39 /* WQE Segment sizes in bytes. */ 40 #define MLX5_WSEG_SIZE 16u 41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg) 42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg) 43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg) 44 45 /* WQE/WQEBB size in bytes. */ 46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe) 47 48 /* 49 * Max size of a WQE session. 50 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments, 51 * the WQE size field in Control Segment is 6 bits wide. 52 */ 53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE) 54 55 /* 56 * Default minimum number of Tx queues for inlining packets. 57 * If there are less queues as specified we assume we have 58 * no enough CPU resources (cycles) to perform inlining, 59 * the PCIe throughput is not supposed as bottleneck and 60 * inlining is disabled. 61 */ 62 #define MLX5_INLINE_MAX_TXQS 8u 63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u 64 65 /* 66 * Default packet length threshold to be inlined with 67 * enhanced MPW. If packet length exceeds the threshold 68 * the data are not inlined. Should be aligned in WQEBB 69 * boundary with accounting the title Control and Ethernet 70 * segments. 71 */ 72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \ 73 MLX5_DSEG_MIN_INLINE_SIZE) 74 /* 75 * Maximal inline data length sent with enhanced MPW. 76 * Is based on maximal WQE size. 77 */ 78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 79 MLX5_WQE_CSEG_SIZE - \ 80 MLX5_WQE_ESEG_SIZE - \ 81 MLX5_WQE_DSEG_SIZE + \ 82 MLX5_DSEG_MIN_INLINE_SIZE) 83 /* 84 * Minimal amount of packets to be sent with EMPW. 85 * This limits the minimal required size of sent EMPW. 86 * If there are no enough resources to built minimal 87 * EMPW the sending loop exits. 88 */ 89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u) 90 /* 91 * Maximal amount of packets to be sent with EMPW. 92 * This value is not recommended to exceed MLX5_TX_COMP_THRESH, 93 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs 94 * without CQE generation request, being multiplied by 95 * MLX5_TX_COMP_MAX_CQE it may cause significant latency 96 * in tx burst routine at the moment of freeing multiple mbufs. 97 */ 98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH 99 #define MLX5_MPW_MAX_PACKETS 6 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6 101 102 /* 103 * Default packet length threshold to be inlined with 104 * ordinary SEND. Inlining saves the MR key search 105 * and extra PCIe data fetch transaction, but eats the 106 * CPU cycles. 107 */ 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \ 109 MLX5_ESEG_MIN_INLINE_SIZE - \ 110 MLX5_WQE_CSEG_SIZE - \ 111 MLX5_WQE_ESEG_SIZE - \ 112 MLX5_WQE_DSEG_SIZE) 113 /* 114 * Maximal inline data length sent with ordinary SEND. 115 * Is based on maximal WQE size. 116 */ 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \ 118 MLX5_WQE_CSEG_SIZE - \ 119 MLX5_WQE_ESEG_SIZE - \ 120 MLX5_WQE_DSEG_SIZE + \ 121 MLX5_ESEG_MIN_INLINE_SIZE) 122 123 /* Missed in mlx5dv.h, should define here. */ 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u 126 #endif 127 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN 129 #define MLX5_OPCODE_SEND_EN 0x17u 130 #endif 131 132 #ifndef HAVE_MLX5_OPCODE_WAIT 133 #define MLX5_OPCODE_WAIT 0x0fu 134 #endif 135 136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO 137 #define MLX5_OPCODE_ACCESS_ASO 0x2du 138 #endif 139 140 /* CQE value to inform that VLAN is stripped. */ 141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0) 142 143 /* IPv4 options. */ 144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1) 145 146 /* IPv6 packet. */ 147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2) 148 149 /* IPv4 packet. */ 150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3) 151 152 /* TCP packet. */ 153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4) 154 155 /* UDP packet. */ 156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5) 157 158 /* IP is fragmented. */ 159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7) 160 161 /* L2 header is valid. */ 162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8) 163 164 /* L3 header is valid. */ 165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9) 166 167 /* L4 header is valid. */ 168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10) 169 170 /* Outer packet, 0 IPv4, 1 IPv6. */ 171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1) 172 173 /* Tunnel packet bit in the CQE. */ 174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0) 175 176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */ 177 #define MLX5_CQE_LRO_PUSH_MASK 0x40 178 179 /* Mask for L4 type in the CQE hdr_type_etc field. */ 180 #define MLX5_CQE_L4_TYPE_MASK 0x70 181 182 /* The bit index of L4 type in CQE hdr_type_etc field. */ 183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4 184 185 /* L4 type to indicate TCP packet without acknowledgment. */ 186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3 187 188 /* L4 type to indicate TCP packet with acknowledgment. */ 189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4 190 191 /* Inner L3 checksum offload (Tunneled packets only). */ 192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4) 193 194 /* Inner L4 checksum offload (Tunneled packets only). */ 195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5) 196 197 /* Outer L4 type is TCP. */ 198 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5) 199 200 /* Outer L4 type is UDP. */ 201 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5) 202 203 /* Outer L3 type is IPV4. */ 204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4) 205 206 /* Outer L3 type is IPV6. */ 207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4) 208 209 /* Inner L4 type is TCP. */ 210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1) 211 212 /* Inner L4 type is UDP. */ 213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1) 214 215 /* Inner L3 type is IPV4. */ 216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0) 217 218 /* Inner L3 type is IPV6. */ 219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0) 220 221 /* VLAN insertion flag. */ 222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31) 223 224 /* Data inline segment flag. */ 225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31) 226 227 /* Is flow mark valid. */ 228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00) 230 #else 231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff) 232 #endif 233 234 /* INVALID is used by packets matching no flow rules. */ 235 #define MLX5_FLOW_MARK_INVALID 0 236 237 /* Maximum allowed value to mark a packet. */ 238 #define MLX5_FLOW_MARK_MAX 0xfffff0 239 240 /* Default mark value used when none is provided. */ 241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff 242 243 /* Default mark mask for metadata legacy mode. */ 244 #define MLX5_FLOW_MARK_MASK 0xffffff 245 246 /* Byte length mask when mark is enable in miniCQE */ 247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00 248 249 /* Maximum number of DS in WQE. Limited by 6-bit field. */ 250 #define MLX5_DSEG_MAX 63 251 252 /* The completion mode offset in the WQE control segment line 2. */ 253 #define MLX5_COMP_MODE_OFFSET 2 254 255 /* Amount of data bytes in minimal inline data segment. */ 256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u 257 258 /* Amount of data bytes in minimal inline eth segment. */ 259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u 260 261 /* Amount of data bytes after eth data segment. */ 262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u 263 264 /* The maximum log value of segments per RQ WQE. */ 265 #define MLX5_MAX_LOG_RQ_SEGS 5u 266 267 /* The alignment needed for WQ buffer. */ 268 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size() 269 270 /* The alignment needed for CQ buffer. */ 271 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size() 272 273 /* Completion mode. */ 274 enum mlx5_completion_mode { 275 MLX5_COMP_ONLY_ERR = 0x0, 276 MLX5_COMP_ONLY_FIRST_ERR = 0x1, 277 MLX5_COMP_ALWAYS = 0x2, 278 MLX5_COMP_CQE_AND_EQE = 0x3, 279 }; 280 281 /* MPW mode. */ 282 enum mlx5_mpw_mode { 283 MLX5_MPW_DISABLED, 284 MLX5_MPW, 285 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */ 286 }; 287 288 /* WQE Control segment. */ 289 struct mlx5_wqe_cseg { 290 uint32_t opcode; 291 uint32_t sq_ds; 292 uint32_t flags; 293 uint32_t misc; 294 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE); 295 296 /* 297 * WQE CSEG opcode field size is 32 bits, divided: 298 * Bits 31:24 OPC_MOD 299 * Bits 23:8 wqe_index 300 * Bits 7:0 OPCODE 301 */ 302 #define WQE_CSEG_OPC_MOD_OFFSET 24 303 #define WQE_CSEG_WQE_INDEX_OFFSET 8 304 305 /* Header of data segment. Minimal size Data Segment */ 306 struct mlx5_wqe_dseg { 307 uint32_t bcount; 308 union { 309 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE]; 310 struct { 311 uint32_t lkey; 312 uint64_t pbuf; 313 } __rte_packed; 314 }; 315 } __rte_packed; 316 317 /* Subset of struct WQE Ethernet Segment. */ 318 struct mlx5_wqe_eseg { 319 union { 320 struct { 321 uint32_t swp_offs; 322 uint8_t cs_flags; 323 uint8_t swp_flags; 324 uint16_t mss; 325 uint32_t metadata; 326 uint16_t inline_hdr_sz; 327 union { 328 uint16_t inline_data; 329 uint16_t vlan_tag; 330 }; 331 } __rte_packed; 332 struct { 333 uint32_t offsets; 334 uint32_t flags; 335 uint32_t flow_metadata; 336 uint32_t inline_hdr; 337 } __rte_packed; 338 }; 339 } __rte_packed; 340 341 struct mlx5_wqe_qseg { 342 uint32_t reserved0; 343 uint32_t reserved1; 344 uint32_t max_index; 345 uint32_t qpn_cqn; 346 } __rte_packed; 347 348 /* The title WQEBB, header of WQE. */ 349 struct mlx5_wqe { 350 union { 351 struct mlx5_wqe_cseg cseg; 352 uint32_t ctrl[4]; 353 }; 354 struct mlx5_wqe_eseg eseg; 355 union { 356 struct mlx5_wqe_dseg dseg[2]; 357 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE]; 358 }; 359 } __rte_packed; 360 361 /* WQE for Multi-Packet RQ. */ 362 struct mlx5_wqe_mprq { 363 struct mlx5_wqe_srq_next_seg next_seg; 364 struct mlx5_wqe_data_seg dseg; 365 }; 366 367 #define MLX5_MPRQ_LEN_MASK 0x000ffff 368 #define MLX5_MPRQ_LEN_SHIFT 0 369 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000 370 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16 371 #define MLX5_MPRQ_FILLER_MASK 0x80000000 372 #define MLX5_MPRQ_FILLER_SHIFT 31 373 374 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2 375 376 /* CQ element structure - should be equal to the cache line size */ 377 struct mlx5_cqe { 378 #if (RTE_CACHE_LINE_SIZE == 128) 379 uint8_t padding[64]; 380 #endif 381 uint8_t pkt_info; 382 uint8_t rsvd0; 383 uint16_t wqe_id; 384 uint8_t lro_tcppsh_abort_dupack; 385 uint8_t lro_min_ttl; 386 uint16_t lro_tcp_win; 387 uint32_t lro_ack_seq_num; 388 uint32_t rx_hash_res; 389 uint8_t rx_hash_type; 390 uint8_t rsvd1[3]; 391 uint16_t csum; 392 uint8_t rsvd2[6]; 393 uint16_t hdr_type_etc; 394 uint16_t vlan_info; 395 uint8_t lro_num_seg; 396 uint8_t rsvd3[3]; 397 uint32_t flow_table_metadata; 398 uint8_t rsvd4[4]; 399 uint32_t byte_cnt; 400 uint64_t timestamp; 401 uint32_t sop_drop_qpn; 402 uint16_t wqe_counter; 403 uint8_t rsvd5; 404 uint8_t op_own; 405 }; 406 407 struct mlx5_cqe_ts { 408 uint64_t timestamp; 409 uint32_t sop_drop_qpn; 410 uint16_t wqe_counter; 411 uint8_t rsvd5; 412 uint8_t op_own; 413 }; 414 415 struct mlx5_wqe_rseg { 416 uint64_t raddr; 417 uint32_t rkey; 418 uint32_t reserved; 419 } __rte_packed; 420 421 #define MLX5_UMRC_IF_OFFSET 31u 422 #define MLX5_UMRC_KO_OFFSET 16u 423 #define MLX5_UMRC_TO_BS_OFFSET 0u 424 425 struct mlx5_wqe_umr_cseg { 426 uint32_t if_cf_toe_cq_res; 427 uint32_t ko_to_bs; 428 uint64_t mkey_mask; 429 uint32_t rsvd1[8]; 430 } __rte_packed; 431 432 struct mlx5_wqe_mkey_cseg { 433 uint32_t fr_res_af_sf; 434 uint32_t qpn_mkey; 435 uint32_t reserved2; 436 uint32_t flags_pd; 437 uint64_t start_addr; 438 uint64_t len; 439 uint32_t bsf_octword_size; 440 uint32_t reserved3[4]; 441 uint32_t translations_octword_size; 442 uint32_t res4_lps; 443 uint32_t reserved; 444 } __rte_packed; 445 446 enum { 447 MLX5_BSF_SIZE_16B = 0x0, 448 MLX5_BSF_SIZE_32B = 0x1, 449 MLX5_BSF_SIZE_64B = 0x2, 450 MLX5_BSF_SIZE_128B = 0x3, 451 }; 452 453 enum { 454 MLX5_BSF_P_TYPE_SIGNATURE = 0x0, 455 MLX5_BSF_P_TYPE_CRYPTO = 0x1, 456 }; 457 458 enum { 459 MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0, 460 MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1, 461 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2, 462 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3, 463 }; 464 465 enum { 466 MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0, 467 }; 468 469 enum { 470 MLX5_BLOCK_SIZE_512B = 0x1, 471 MLX5_BLOCK_SIZE_520B = 0x2, 472 MLX5_BLOCK_SIZE_4096B = 0x3, 473 MLX5_BLOCK_SIZE_4160B = 0x4, 474 MLX5_BLOCK_SIZE_1MB = 0x5, 475 MLX5_BLOCK_SIZE_4048B = 0x6, 476 }; 477 478 #define MLX5_BSF_SIZE_OFFSET 30 479 #define MLX5_BSF_P_TYPE_OFFSET 24 480 #define MLX5_ENCRYPTION_ORDER_OFFSET 16 481 #define MLX5_BLOCK_SIZE_OFFSET 24 482 483 struct mlx5_wqe_umr_bsf_seg { 484 /* 485 * bs_bpt_eo_es contains: 486 * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET 487 * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET 488 * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET 489 * es encryption_standard 4 bits at offset 0 490 */ 491 uint32_t bs_bpt_eo_es; 492 uint32_t raw_data_size; 493 /* 494 * bsp_res contains: 495 * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET 496 * res reserved 24 bits 497 */ 498 uint32_t bsp_res; 499 uint32_t reserved0; 500 uint8_t xts_initial_tweak[16]; 501 /* 502 * res_dp contains: 503 * res reserved 8 bits 504 * dp dek_pointer 24 bits at offset 0 505 */ 506 uint32_t res_dp; 507 uint32_t reserved1; 508 uint64_t keytag; 509 uint32_t reserved2[4]; 510 } __rte_packed; 511 512 #ifdef PEDANTIC 513 #pragma GCC diagnostic ignored "-Wpedantic" 514 #endif 515 516 struct mlx5_umr_wqe { 517 struct mlx5_wqe_cseg ctr; 518 struct mlx5_wqe_umr_cseg ucseg; 519 struct mlx5_wqe_mkey_cseg mkc; 520 union { 521 struct mlx5_wqe_dseg kseg[0]; 522 struct mlx5_wqe_umr_bsf_seg bsf[0]; 523 }; 524 } __rte_packed; 525 526 struct mlx5_rdma_write_wqe { 527 struct mlx5_wqe_cseg ctr; 528 struct mlx5_wqe_rseg rseg; 529 struct mlx5_wqe_dseg dseg[0]; 530 } __rte_packed; 531 532 #ifdef PEDANTIC 533 #pragma GCC diagnostic error "-Wpedantic" 534 #endif 535 536 /* GGA */ 537 /* MMO metadata segment */ 538 539 #define MLX5_OPCODE_MMO 0x2fu 540 #define MLX5_OPC_MOD_MMO_REGEX 0x4u 541 #define MLX5_OPC_MOD_MMO_COMP 0x2u 542 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u 543 #define MLX5_OPC_MOD_MMO_DMA 0x1u 544 545 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u 546 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u 547 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u 548 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u 549 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) 550 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u 551 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u 552 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u 553 554 struct mlx5_wqe_metadata_seg { 555 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */ 556 uint32_t lkey; 557 uint64_t addr; 558 }; 559 560 struct mlx5_gga_wqe { 561 uint32_t opcode; 562 uint32_t sq_ds; 563 uint32_t flags; 564 uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */ 565 uint32_t gga_ctrl2; 566 uint32_t opaque_lkey; 567 uint64_t opaque_vaddr; 568 struct mlx5_wqe_dseg gather; 569 struct mlx5_wqe_dseg scatter; 570 } __rte_packed; 571 572 struct mlx5_gga_compress_opaque { 573 uint32_t syndrom; 574 uint32_t reserved0; 575 uint32_t scattered_length; 576 uint32_t gathered_length; 577 uint64_t scatter_crc; 578 uint64_t gather_crc; 579 uint32_t crc32; 580 uint32_t adler32; 581 uint8_t reserved1[216]; 582 } __rte_packed; 583 584 struct mlx5_ifc_regexp_mmo_control_bits { 585 uint8_t reserved_at_31[0x2]; 586 uint8_t le[0x1]; 587 uint8_t reserved_at_28[0x1]; 588 uint8_t subset_id_0[0xc]; 589 uint8_t reserved_at_16[0x4]; 590 uint8_t subset_id_1[0xc]; 591 uint8_t ctrl[0x4]; 592 uint8_t subset_id_2[0xc]; 593 uint8_t reserved_at_16_1[0x4]; 594 uint8_t subset_id_3[0xc]; 595 }; 596 597 struct mlx5_ifc_regexp_metadata_bits { 598 uint8_t rof_version[0x10]; 599 uint8_t latency_count[0x10]; 600 uint8_t instruction_count[0x10]; 601 uint8_t primary_thread_count[0x10]; 602 uint8_t match_count[0x8]; 603 uint8_t detected_match_count[0x8]; 604 uint8_t status[0x10]; 605 uint8_t job_id[0x20]; 606 uint8_t reserved[0x80]; 607 }; 608 609 struct mlx5_ifc_regexp_match_tuple_bits { 610 uint8_t length[0x10]; 611 uint8_t start_ptr[0x10]; 612 uint8_t rule_id[0x20]; 613 }; 614 615 /* Adding direct verbs to data-path. */ 616 617 /* CQ sequence number mask. */ 618 #define MLX5_CQ_SQN_MASK 0x3 619 620 /* CQ sequence number index. */ 621 #define MLX5_CQ_SQN_OFFSET 28 622 623 /* CQ doorbell index mask. */ 624 #define MLX5_CI_MASK 0xffffff 625 626 /* CQ doorbell offset. */ 627 #define MLX5_CQ_ARM_DB 1 628 629 /* CQ doorbell offset*/ 630 #define MLX5_CQ_DOORBELL 0x20 631 632 /* CQE format value. */ 633 #define MLX5_COMPRESSED 0x3 634 635 /* CQ doorbell cmd types. */ 636 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24) 637 #define MLX5_CQ_DBR_CMD_ALL (0 << 24) 638 639 /* Action type of header modification. */ 640 enum { 641 MLX5_MODIFICATION_TYPE_SET = 0x1, 642 MLX5_MODIFICATION_TYPE_ADD = 0x2, 643 MLX5_MODIFICATION_TYPE_COPY = 0x3, 644 }; 645 646 /* The field of packet to be modified. */ 647 enum mlx5_modification_field { 648 MLX5_MODI_OUT_NONE = -1, 649 MLX5_MODI_OUT_SMAC_47_16 = 1, 650 MLX5_MODI_OUT_SMAC_15_0, 651 MLX5_MODI_OUT_ETHERTYPE, 652 MLX5_MODI_OUT_DMAC_47_16, 653 MLX5_MODI_OUT_DMAC_15_0, 654 MLX5_MODI_OUT_IP_DSCP, 655 MLX5_MODI_OUT_TCP_FLAGS, 656 MLX5_MODI_OUT_TCP_SPORT, 657 MLX5_MODI_OUT_TCP_DPORT, 658 MLX5_MODI_OUT_IPV4_TTL, 659 MLX5_MODI_OUT_UDP_SPORT, 660 MLX5_MODI_OUT_UDP_DPORT, 661 MLX5_MODI_OUT_SIPV6_127_96, 662 MLX5_MODI_OUT_SIPV6_95_64, 663 MLX5_MODI_OUT_SIPV6_63_32, 664 MLX5_MODI_OUT_SIPV6_31_0, 665 MLX5_MODI_OUT_DIPV6_127_96, 666 MLX5_MODI_OUT_DIPV6_95_64, 667 MLX5_MODI_OUT_DIPV6_63_32, 668 MLX5_MODI_OUT_DIPV6_31_0, 669 MLX5_MODI_OUT_SIPV4, 670 MLX5_MODI_OUT_DIPV4, 671 MLX5_MODI_OUT_FIRST_VID, 672 MLX5_MODI_IN_SMAC_47_16 = 0x31, 673 MLX5_MODI_IN_SMAC_15_0, 674 MLX5_MODI_IN_ETHERTYPE, 675 MLX5_MODI_IN_DMAC_47_16, 676 MLX5_MODI_IN_DMAC_15_0, 677 MLX5_MODI_IN_IP_DSCP, 678 MLX5_MODI_IN_TCP_FLAGS, 679 MLX5_MODI_IN_TCP_SPORT, 680 MLX5_MODI_IN_TCP_DPORT, 681 MLX5_MODI_IN_IPV4_TTL, 682 MLX5_MODI_IN_UDP_SPORT, 683 MLX5_MODI_IN_UDP_DPORT, 684 MLX5_MODI_IN_SIPV6_127_96, 685 MLX5_MODI_IN_SIPV6_95_64, 686 MLX5_MODI_IN_SIPV6_63_32, 687 MLX5_MODI_IN_SIPV6_31_0, 688 MLX5_MODI_IN_DIPV6_127_96, 689 MLX5_MODI_IN_DIPV6_95_64, 690 MLX5_MODI_IN_DIPV6_63_32, 691 MLX5_MODI_IN_DIPV6_31_0, 692 MLX5_MODI_IN_SIPV4, 693 MLX5_MODI_IN_DIPV4, 694 MLX5_MODI_OUT_IPV6_HOPLIMIT, 695 MLX5_MODI_IN_IPV6_HOPLIMIT, 696 MLX5_MODI_META_DATA_REG_A, 697 MLX5_MODI_META_DATA_REG_B = 0x50, 698 MLX5_MODI_META_REG_C_0, 699 MLX5_MODI_META_REG_C_1, 700 MLX5_MODI_META_REG_C_2, 701 MLX5_MODI_META_REG_C_3, 702 MLX5_MODI_META_REG_C_4, 703 MLX5_MODI_META_REG_C_5, 704 MLX5_MODI_META_REG_C_6, 705 MLX5_MODI_META_REG_C_7, 706 MLX5_MODI_OUT_TCP_SEQ_NUM, 707 MLX5_MODI_IN_TCP_SEQ_NUM, 708 MLX5_MODI_OUT_TCP_ACK_NUM, 709 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C, 710 MLX5_MODI_GTP_TEID = 0x6E, 711 }; 712 713 /* Total number of metadata reg_c's. */ 714 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1) 715 716 enum modify_reg { 717 REG_NON = 0, 718 REG_A, 719 REG_B, 720 REG_C_0, 721 REG_C_1, 722 REG_C_2, 723 REG_C_3, 724 REG_C_4, 725 REG_C_5, 726 REG_C_6, 727 REG_C_7, 728 }; 729 730 /* Modification sub command. */ 731 struct mlx5_modification_cmd { 732 union { 733 uint32_t data0; 734 struct { 735 unsigned int length:5; 736 unsigned int rsvd0:3; 737 unsigned int offset:5; 738 unsigned int rsvd1:3; 739 unsigned int field:12; 740 unsigned int action_type:4; 741 }; 742 }; 743 union { 744 uint32_t data1; 745 uint8_t data[4]; 746 struct { 747 unsigned int rsvd2:8; 748 unsigned int dst_offset:5; 749 unsigned int rsvd3:3; 750 unsigned int dst_field:12; 751 unsigned int rsvd4:4; 752 }; 753 }; 754 }; 755 756 typedef uint64_t u64; 757 typedef uint32_t u32; 758 typedef uint16_t u16; 759 typedef uint8_t u8; 760 761 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 762 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 763 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \ 764 (&(__mlx5_nullp(typ)->fld))) 765 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \ 766 (__mlx5_bit_off(typ, fld) & 0x1f)) 767 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 768 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 769 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \ 770 __mlx5_dw_bit_off(typ, fld)) 771 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 772 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16) 773 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \ 774 (__mlx5_bit_off(typ, fld) & 0xf)) 775 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 776 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \ 777 __mlx5_16_bit_off(typ, fld)) 778 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 779 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 780 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 781 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 782 783 /* insert a value to a struct */ 784 #define MLX5_SET(typ, p, fld, v) \ 785 do { \ 786 u32 _v = v; \ 787 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \ 788 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \ 789 __mlx5_dw_off(typ, fld))) & \ 790 (~__mlx5_dw_mask(typ, fld))) | \ 791 (((_v) & __mlx5_mask(typ, fld)) << \ 792 __mlx5_dw_bit_off(typ, fld))); \ 793 } while (0) 794 795 #define MLX5_SET64(typ, p, fld, v) \ 796 do { \ 797 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \ 798 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \ 799 rte_cpu_to_be_64(v); \ 800 } while (0) 801 802 #define MLX5_SET16(typ, p, fld, v) \ 803 do { \ 804 u16 _v = v; \ 805 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \ 806 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 807 __mlx5_16_off(typ, fld))) & \ 808 (~__mlx5_16_mask(typ, fld))) | \ 809 (((_v) & __mlx5_mask16(typ, fld)) << \ 810 __mlx5_16_bit_off(typ, fld))); \ 811 } while (0) 812 813 #define MLX5_GET_VOLATILE(typ, p, fld) \ 814 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\ 815 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 816 __mlx5_mask(typ, fld)) 817 #define MLX5_GET(typ, p, fld) \ 818 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\ 819 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 820 __mlx5_mask(typ, fld)) 821 #define MLX5_GET16(typ, p, fld) \ 822 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \ 823 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \ 824 __mlx5_mask16(typ, fld)) 825 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \ 826 __mlx5_64_off(typ, fld))) 827 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 828 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 829 830 struct mlx5_ifc_fte_match_set_misc_bits { 831 u8 gre_c_present[0x1]; 832 u8 reserved_at_1[0x1]; 833 u8 gre_k_present[0x1]; 834 u8 gre_s_present[0x1]; 835 u8 source_vhci_port[0x4]; 836 u8 source_sqn[0x18]; 837 u8 reserved_at_20[0x10]; 838 u8 source_port[0x10]; 839 u8 outer_second_prio[0x3]; 840 u8 outer_second_cfi[0x1]; 841 u8 outer_second_vid[0xc]; 842 u8 inner_second_prio[0x3]; 843 u8 inner_second_cfi[0x1]; 844 u8 inner_second_vid[0xc]; 845 u8 outer_second_cvlan_tag[0x1]; 846 u8 inner_second_cvlan_tag[0x1]; 847 u8 outer_second_svlan_tag[0x1]; 848 u8 inner_second_svlan_tag[0x1]; 849 u8 reserved_at_64[0xc]; 850 u8 gre_protocol[0x10]; 851 u8 gre_key_h[0x18]; 852 u8 gre_key_l[0x8]; 853 u8 vxlan_vni[0x18]; 854 u8 reserved_at_b8[0x8]; 855 u8 geneve_vni[0x18]; 856 u8 reserved_at_e4[0x6]; 857 u8 geneve_tlv_option_0_exist[0x1]; 858 u8 geneve_oam[0x1]; 859 u8 reserved_at_e0[0xc]; 860 u8 outer_ipv6_flow_label[0x14]; 861 u8 reserved_at_100[0xc]; 862 u8 inner_ipv6_flow_label[0x14]; 863 u8 reserved_at_120[0xa]; 864 u8 geneve_opt_len[0x6]; 865 u8 geneve_protocol_type[0x10]; 866 u8 reserved_at_140[0xc0]; 867 }; 868 869 struct mlx5_ifc_ipv4_layout_bits { 870 u8 reserved_at_0[0x60]; 871 u8 ipv4[0x20]; 872 }; 873 874 struct mlx5_ifc_ipv6_layout_bits { 875 u8 ipv6[16][0x8]; 876 }; 877 878 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 879 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 880 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 881 u8 reserved_at_0[0x80]; 882 }; 883 884 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 885 u8 smac_47_16[0x20]; 886 u8 smac_15_0[0x10]; 887 u8 ethertype[0x10]; 888 u8 dmac_47_16[0x20]; 889 u8 dmac_15_0[0x10]; 890 u8 first_prio[0x3]; 891 u8 first_cfi[0x1]; 892 u8 first_vid[0xc]; 893 u8 ip_protocol[0x8]; 894 u8 ip_dscp[0x6]; 895 u8 ip_ecn[0x2]; 896 u8 cvlan_tag[0x1]; 897 u8 svlan_tag[0x1]; 898 u8 frag[0x1]; 899 u8 ip_version[0x4]; 900 u8 tcp_flags[0x9]; 901 u8 tcp_sport[0x10]; 902 u8 tcp_dport[0x10]; 903 u8 reserved_at_c0[0x10]; 904 u8 ipv4_ihl[0x4]; 905 u8 l3_ok[0x1]; 906 u8 l4_ok[0x1]; 907 u8 ipv4_checksum_ok[0x1]; 908 u8 l4_checksum_ok[0x1]; 909 u8 ip_ttl_hoplimit[0x8]; 910 u8 udp_sport[0x10]; 911 u8 udp_dport[0x10]; 912 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 913 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 914 }; 915 916 struct mlx5_ifc_fte_match_mpls_bits { 917 u8 mpls_label[0x14]; 918 u8 mpls_exp[0x3]; 919 u8 mpls_s_bos[0x1]; 920 u8 mpls_ttl[0x8]; 921 }; 922 923 struct mlx5_ifc_fte_match_set_misc2_bits { 924 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 925 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 926 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 927 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 928 u8 metadata_reg_c_7[0x20]; 929 u8 metadata_reg_c_6[0x20]; 930 u8 metadata_reg_c_5[0x20]; 931 u8 metadata_reg_c_4[0x20]; 932 u8 metadata_reg_c_3[0x20]; 933 u8 metadata_reg_c_2[0x20]; 934 u8 metadata_reg_c_1[0x20]; 935 u8 metadata_reg_c_0[0x20]; 936 u8 metadata_reg_a[0x20]; 937 u8 metadata_reg_b[0x20]; 938 u8 reserved_at_1c0[0x40]; 939 }; 940 941 struct mlx5_ifc_fte_match_set_misc3_bits { 942 u8 inner_tcp_seq_num[0x20]; 943 u8 outer_tcp_seq_num[0x20]; 944 u8 inner_tcp_ack_num[0x20]; 945 u8 outer_tcp_ack_num[0x20]; 946 u8 reserved_at_auto1[0x8]; 947 u8 outer_vxlan_gpe_vni[0x18]; 948 u8 outer_vxlan_gpe_next_protocol[0x8]; 949 u8 outer_vxlan_gpe_flags[0x8]; 950 u8 reserved_at_a8[0x10]; 951 u8 icmp_header_data[0x20]; 952 u8 icmpv6_header_data[0x20]; 953 u8 icmp_type[0x8]; 954 u8 icmp_code[0x8]; 955 u8 icmpv6_type[0x8]; 956 u8 icmpv6_code[0x8]; 957 u8 geneve_tlv_option_0_data[0x20]; 958 u8 gtpu_teid[0x20]; 959 u8 gtpu_msg_type[0x08]; 960 u8 gtpu_msg_flags[0x08]; 961 u8 reserved_at_170[0x10]; 962 u8 gtpu_dw_2[0x20]; 963 u8 gtpu_first_ext_dw_0[0x20]; 964 u8 gtpu_dw_0[0x20]; 965 u8 reserved_at_240[0x20]; 966 967 }; 968 969 struct mlx5_ifc_fte_match_set_misc4_bits { 970 u8 prog_sample_field_value_0[0x20]; 971 u8 prog_sample_field_id_0[0x20]; 972 u8 prog_sample_field_value_1[0x20]; 973 u8 prog_sample_field_id_1[0x20]; 974 u8 prog_sample_field_value_2[0x20]; 975 u8 prog_sample_field_id_2[0x20]; 976 u8 prog_sample_field_value_3[0x20]; 977 u8 prog_sample_field_id_3[0x20]; 978 u8 reserved_at_100[0x100]; 979 }; 980 981 struct mlx5_ifc_fte_match_set_misc5_bits { 982 u8 macsec_tag_0[0x20]; 983 u8 macsec_tag_1[0x20]; 984 u8 macsec_tag_2[0x20]; 985 u8 macsec_tag_3[0x20]; 986 u8 tunnel_header_0[0x20]; 987 u8 tunnel_header_1[0x20]; 988 u8 tunnel_header_2[0x20]; 989 u8 tunnel_header_3[0x20]; 990 u8 reserved[0x100]; 991 }; 992 993 /* Flow matcher. */ 994 struct mlx5_ifc_fte_match_param_bits { 995 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 996 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 997 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 998 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 999 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1000 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1001 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1002 /* 1003 * Add reserved bit to match the struct size with the size defined in PRM. 1004 * This extension is not required in Linux. 1005 */ 1006 #ifndef HAVE_INFINIBAND_VERBS_H 1007 u8 reserved_0[0x200]; 1008 #endif 1009 }; 1010 1011 struct mlx5_ifc_dest_format_struct_bits { 1012 u8 destination_type[0x8]; 1013 u8 destination_id[0x18]; 1014 u8 reserved_0[0x20]; 1015 }; 1016 1017 enum { 1018 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT, 1019 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT, 1020 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT, 1021 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT, 1022 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT, 1023 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT, 1024 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT, 1025 }; 1026 1027 enum { 1028 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 1029 MLX5_CMD_OP_CREATE_MKEY = 0x200, 1030 MLX5_CMD_OP_CREATE_CQ = 0x400, 1031 MLX5_CMD_OP_CREATE_QP = 0x500, 1032 MLX5_CMD_OP_RST2INIT_QP = 0x502, 1033 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 1034 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 1035 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 1036 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 1037 MLX5_CMD_OP_QP_2ERR = 0x507, 1038 MLX5_CMD_OP_QP_2RST = 0x50A, 1039 MLX5_CMD_OP_QUERY_QP = 0x50B, 1040 MLX5_CMD_OP_SQD2RTS_QP = 0x50C, 1041 MLX5_CMD_OP_INIT2INIT_QP = 0x50E, 1042 MLX5_CMD_OP_SUSPEND_QP = 0x50F, 1043 MLX5_CMD_OP_RESUME_QP = 0x510, 1044 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 1045 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 1046 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 1047 MLX5_CMD_OP_ALLOC_PD = 0x800, 1048 MLX5_CMD_OP_DEALLOC_PD = 0x801, 1049 MLX5_CMD_OP_ACCESS_REGISTER = 0x805, 1050 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 1051 MLX5_CMD_OP_CREATE_TIR = 0x900, 1052 MLX5_CMD_OP_MODIFY_TIR = 0x901, 1053 MLX5_CMD_OP_CREATE_SQ = 0X904, 1054 MLX5_CMD_OP_MODIFY_SQ = 0X905, 1055 MLX5_CMD_OP_CREATE_RQ = 0x908, 1056 MLX5_CMD_OP_MODIFY_RQ = 0x909, 1057 MLX5_CMD_OP_QUERY_RQ = 0x90b, 1058 MLX5_CMD_OP_CREATE_TIS = 0x912, 1059 MLX5_CMD_OP_QUERY_TIS = 0x915, 1060 MLX5_CMD_OP_CREATE_RQT = 0x916, 1061 MLX5_CMD_OP_MODIFY_RQT = 0x917, 1062 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 1063 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 1064 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 1065 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 1066 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 1067 MLX5_CMD_SET_REGEX_PARAMS = 0xb04, 1068 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05, 1069 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06, 1070 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07, 1071 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c, 1072 }; 1073 1074 enum { 1075 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 1076 MLX5_MKC_ACCESS_MODE_KLM = 0x2, 1077 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3, 1078 }; 1079 1080 #define MLX5_ADAPTER_PAGE_SHIFT 12 1081 #define MLX5_LOG_RQ_STRIDE_SHIFT 4 1082 /** 1083 * The batch counter dcs id starts from 0x800000 and none batch counter 1084 * starts from 0. As currently, the counter is changed to be indexed by 1085 * pool index and the offset of the counter in the pool counters_raw array. 1086 * It means now the counter index is same for batch and none batch counter. 1087 * Add the 0x800000 batch counter offset to the batch counter index helps 1088 * indicate the counter index is from batch or none batch container pool. 1089 */ 1090 #define MLX5_CNT_BATCH_OFFSET 0x800000 1091 1092 /* The counter batch query requires ID align with 4. */ 1093 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4 1094 1095 /* Flow counters. */ 1096 struct mlx5_ifc_alloc_flow_counter_out_bits { 1097 u8 status[0x8]; 1098 u8 reserved_at_8[0x18]; 1099 u8 syndrome[0x20]; 1100 u8 flow_counter_id[0x20]; 1101 u8 reserved_at_60[0x20]; 1102 }; 1103 1104 struct mlx5_ifc_alloc_flow_counter_in_bits { 1105 u8 opcode[0x10]; 1106 u8 reserved_at_10[0x10]; 1107 u8 reserved_at_20[0x10]; 1108 u8 op_mod[0x10]; 1109 u8 flow_counter_id[0x20]; 1110 u8 reserved_at_40[0x18]; 1111 u8 flow_counter_bulk[0x8]; 1112 }; 1113 1114 struct mlx5_ifc_dealloc_flow_counter_out_bits { 1115 u8 status[0x8]; 1116 u8 reserved_at_8[0x18]; 1117 u8 syndrome[0x20]; 1118 u8 reserved_at_40[0x40]; 1119 }; 1120 1121 struct mlx5_ifc_dealloc_flow_counter_in_bits { 1122 u8 opcode[0x10]; 1123 u8 reserved_at_10[0x10]; 1124 u8 reserved_at_20[0x10]; 1125 u8 op_mod[0x10]; 1126 u8 flow_counter_id[0x20]; 1127 u8 reserved_at_60[0x20]; 1128 }; 1129 1130 struct mlx5_ifc_traffic_counter_bits { 1131 u8 packets[0x40]; 1132 u8 octets[0x40]; 1133 }; 1134 1135 struct mlx5_ifc_query_flow_counter_out_bits { 1136 u8 status[0x8]; 1137 u8 reserved_at_8[0x18]; 1138 u8 syndrome[0x20]; 1139 u8 reserved_at_40[0x40]; 1140 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 1141 }; 1142 1143 struct mlx5_ifc_query_flow_counter_in_bits { 1144 u8 opcode[0x10]; 1145 u8 reserved_at_10[0x10]; 1146 u8 reserved_at_20[0x10]; 1147 u8 op_mod[0x10]; 1148 u8 reserved_at_40[0x20]; 1149 u8 mkey[0x20]; 1150 u8 address[0x40]; 1151 u8 clear[0x1]; 1152 u8 dump_to_memory[0x1]; 1153 u8 num_of_counters[0x1e]; 1154 u8 flow_counter_id[0x20]; 1155 }; 1156 1157 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u 1158 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u 1159 1160 struct mlx5_ifc_klm_bits { 1161 u8 byte_count[0x20]; 1162 u8 mkey[0x20]; 1163 u8 address[0x40]; 1164 }; 1165 1166 struct mlx5_ifc_mkc_bits { 1167 u8 reserved_at_0[0x1]; 1168 u8 free[0x1]; 1169 u8 reserved_at_2[0x1]; 1170 u8 access_mode_4_2[0x3]; 1171 u8 reserved_at_6[0x7]; 1172 u8 relaxed_ordering_write[0x1]; 1173 u8 reserved_at_e[0x1]; 1174 u8 small_fence_on_rdma_read_response[0x1]; 1175 u8 umr_en[0x1]; 1176 u8 a[0x1]; 1177 u8 rw[0x1]; 1178 u8 rr[0x1]; 1179 u8 lw[0x1]; 1180 u8 lr[0x1]; 1181 u8 access_mode_1_0[0x2]; 1182 u8 reserved_at_18[0x8]; 1183 u8 qpn[0x18]; 1184 u8 mkey_7_0[0x8]; 1185 u8 reserved_at_40[0x20]; 1186 u8 length64[0x1]; 1187 u8 bsf_en[0x1]; 1188 u8 sync_umr[0x1]; 1189 u8 reserved_at_63[0x2]; 1190 u8 expected_sigerr_count[0x1]; 1191 u8 reserved_at_66[0x1]; 1192 u8 en_rinval[0x1]; 1193 u8 pd[0x18]; 1194 u8 start_addr[0x40]; 1195 u8 len[0x40]; 1196 u8 bsf_octword_size[0x20]; 1197 u8 reserved_at_120[0x80]; 1198 u8 translations_octword_size[0x20]; 1199 u8 reserved_at_1c0[0x19]; 1200 u8 relaxed_ordering_read[0x1]; 1201 u8 reserved_at_1da[0x1]; 1202 u8 log_page_size[0x5]; 1203 u8 reserved_at_1e0[0x3]; 1204 u8 crypto_en[0x2]; 1205 u8 reserved_at_1e5[0x1b]; 1206 }; 1207 1208 /* Range of values for MKEY context crypto_en field. */ 1209 enum { 1210 MLX5_MKEY_CRYPTO_DISABLED = 0x0, 1211 MLX5_MKEY_CRYPTO_ENABLED = 0x1, 1212 }; 1213 1214 struct mlx5_ifc_create_mkey_out_bits { 1215 u8 status[0x8]; 1216 u8 reserved_at_8[0x18]; 1217 u8 syndrome[0x20]; 1218 u8 reserved_at_40[0x8]; 1219 u8 mkey_index[0x18]; 1220 u8 reserved_at_60[0x20]; 1221 }; 1222 1223 struct mlx5_ifc_create_mkey_in_bits { 1224 u8 opcode[0x10]; 1225 u8 reserved_at_10[0x10]; 1226 u8 reserved_at_20[0x10]; 1227 u8 op_mod[0x10]; 1228 u8 reserved_at_40[0x20]; 1229 u8 pg_access[0x1]; 1230 u8 reserved_at_61[0x1f]; 1231 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 1232 u8 reserved_at_280[0x80]; 1233 u8 translations_octword_actual_size[0x20]; 1234 u8 mkey_umem_id[0x20]; 1235 u8 mkey_umem_offset[0x40]; 1236 u8 reserved_at_380[0x500]; 1237 u8 klm_pas_mtt[][0x20]; 1238 }; 1239 1240 enum { 1241 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1, 1242 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1, 1243 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1, 1244 MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, 1245 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, 1246 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, 1247 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, 1248 }; 1249 1250 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \ 1251 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ) 1252 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \ 1253 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS) 1254 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \ 1255 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH) 1256 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \ 1257 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO) 1258 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \ 1259 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO) 1260 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ 1261 (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT) 1262 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \ 1263 (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD) 1264 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \ 1265 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK) 1266 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \ 1267 (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK) 1268 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \ 1269 (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL) 1270 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \ 1271 (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN) 1272 1273 enum { 1274 MLX5_HCA_CAP_OPMOD_GET_MAX = 0, 1275 MLX5_HCA_CAP_OPMOD_GET_CUR = 1, 1276 }; 1277 1278 enum { 1279 MLX5_CAP_INLINE_MODE_L2, 1280 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT, 1281 MLX5_CAP_INLINE_MODE_NOT_REQUIRED, 1282 }; 1283 1284 enum { 1285 MLX5_INLINE_MODE_NONE, 1286 MLX5_INLINE_MODE_L2, 1287 MLX5_INLINE_MODE_IP, 1288 MLX5_INLINE_MODE_TCP_UDP, 1289 MLX5_INLINE_MODE_RESERVED4, 1290 MLX5_INLINE_MODE_INNER_L2, 1291 MLX5_INLINE_MODE_INNER_IP, 1292 MLX5_INLINE_MODE_INNER_TCP_UDP, 1293 }; 1294 1295 /* The supported timestamp formats reported in HCA attributes. */ 1296 enum { 1297 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0, 1298 MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1, 1299 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2, 1300 }; 1301 1302 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */ 1303 enum { 1304 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 1305 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 1306 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 1307 }; 1308 1309 /* HCA bit masks indicating which Flex parser protocols are already enabled. */ 1310 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0) 1311 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1) 1312 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2) 1313 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3) 1314 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4) 1315 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5) 1316 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6) 1317 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7) 1318 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8) 1319 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9) 1320 1321 /* The device steering logic format. */ 1322 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0 1323 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1 1324 1325 struct mlx5_ifc_cmd_hca_cap_bits { 1326 u8 reserved_at_0[0x30]; 1327 u8 vhca_id[0x10]; 1328 u8 reserved_at_40[0x20]; 1329 u8 reserved_at_60[0x3]; 1330 u8 log_regexp_scatter_gather_size[0x5]; 1331 u8 reserved_at_68[0x3]; 1332 u8 log_dma_mmo_size[0x5]; 1333 u8 reserved_at_70[0x3]; 1334 u8 log_compress_mmo_size[0x5]; 1335 u8 reserved_at_78[0x3]; 1336 u8 log_decompress_mmo_size[0x5]; 1337 u8 log_max_srq_sz[0x8]; 1338 u8 log_max_qp_sz[0x8]; 1339 u8 reserved_at_90[0x9]; 1340 u8 wqe_index_ignore_cap[0x1]; 1341 u8 dynamic_qp_allocation[0x1]; 1342 u8 log_max_qp[0x5]; 1343 u8 regexp[0x1]; 1344 u8 reserved_at_a1[0x3]; 1345 u8 regexp_num_of_engines[0x4]; 1346 u8 reserved_at_a8[0x1]; 1347 u8 reg_c_preserve[0x1]; 1348 u8 reserved_at_aa[0x1]; 1349 u8 log_max_srq[0x5]; 1350 u8 reserved_at_b0[0x3]; 1351 u8 regexp_log_crspace_size[0x5]; 1352 u8 reserved_at_b8[0x3]; 1353 u8 scatter_fcs_w_decap_disable[0x1]; 1354 u8 reserved_at_bc[0x4]; 1355 u8 reserved_at_c0[0x8]; 1356 u8 log_max_cq_sz[0x8]; 1357 u8 reserved_at_d0[0xb]; 1358 u8 log_max_cq[0x5]; 1359 u8 log_max_eq_sz[0x8]; 1360 u8 relaxed_ordering_write[0x1]; 1361 u8 relaxed_ordering_read[0x1]; 1362 u8 access_register_user[0x1]; 1363 u8 log_max_mkey[0x5]; 1364 u8 reserved_at_f0[0x8]; 1365 u8 dump_fill_mkey[0x1]; 1366 u8 reserved_at_f9[0x3]; 1367 u8 log_max_eq[0x4]; 1368 u8 max_indirection[0x8]; 1369 u8 fixed_buffer_size[0x1]; 1370 u8 log_max_mrw_sz[0x7]; 1371 u8 force_teardown[0x1]; 1372 u8 reserved_at_111[0x1]; 1373 u8 log_max_bsf_list_size[0x6]; 1374 u8 umr_extended_translation_offset[0x1]; 1375 u8 null_mkey[0x1]; 1376 u8 log_max_klm_list_size[0x6]; 1377 u8 non_wire_sq[0x1]; 1378 u8 reserved_at_121[0x9]; 1379 u8 log_max_ra_req_dc[0x6]; 1380 u8 reserved_at_130[0x3]; 1381 u8 log_max_static_sq_wq[0x5]; 1382 u8 reserved_at_138[0x2]; 1383 u8 log_max_ra_res_dc[0x6]; 1384 u8 reserved_at_140[0xa]; 1385 u8 log_max_ra_req_qp[0x6]; 1386 u8 rtr2rts_qp_counters_set_id[0x1]; 1387 u8 rts2rts_udp_sport[0x1]; 1388 u8 rts2rts_lag_tx_port_affinity[0x1]; 1389 u8 dma_mmo_sq[0x1]; 1390 u8 compress_min_block_size[0x4]; 1391 u8 compress_mmo_sq[0x1]; 1392 u8 decompress_mmo_sq[0x1]; 1393 u8 log_max_ra_res_qp[0x6]; 1394 u8 end_pad[0x1]; 1395 u8 cc_query_allowed[0x1]; 1396 u8 cc_modify_allowed[0x1]; 1397 u8 start_pad[0x1]; 1398 u8 cache_line_128byte[0x1]; 1399 u8 reserved_at_165[0xa]; 1400 u8 qcam_reg[0x1]; 1401 u8 gid_table_size[0x10]; 1402 u8 out_of_seq_cnt[0x1]; 1403 u8 vport_counters[0x1]; 1404 u8 retransmission_q_counters[0x1]; 1405 u8 debug[0x1]; 1406 u8 modify_rq_counter_set_id[0x1]; 1407 u8 rq_delay_drop[0x1]; 1408 u8 max_qp_cnt[0xa]; 1409 u8 pkey_table_size[0x10]; 1410 u8 vport_group_manager[0x1]; 1411 u8 vhca_group_manager[0x1]; 1412 u8 ib_virt[0x1]; 1413 u8 eth_virt[0x1]; 1414 u8 vnic_env_queue_counters[0x1]; 1415 u8 ets[0x1]; 1416 u8 nic_flow_table[0x1]; 1417 u8 eswitch_manager[0x1]; 1418 u8 device_memory[0x1]; 1419 u8 mcam_reg[0x1]; 1420 u8 pcam_reg[0x1]; 1421 u8 local_ca_ack_delay[0x5]; 1422 u8 port_module_event[0x1]; 1423 u8 enhanced_error_q_counters[0x1]; 1424 u8 ports_check[0x1]; 1425 u8 reserved_at_1b3[0x1]; 1426 u8 disable_link_up[0x1]; 1427 u8 beacon_led[0x1]; 1428 u8 port_type[0x2]; 1429 u8 num_ports[0x8]; 1430 u8 reserved_at_1c0[0x1]; 1431 u8 pps[0x1]; 1432 u8 pps_modify[0x1]; 1433 u8 log_max_msg[0x5]; 1434 u8 reserved_at_1c8[0x4]; 1435 u8 max_tc[0x4]; 1436 u8 temp_warn_event[0x1]; 1437 u8 dcbx[0x1]; 1438 u8 general_notification_event[0x1]; 1439 u8 reserved_at_1d3[0x2]; 1440 u8 fpga[0x1]; 1441 u8 rol_s[0x1]; 1442 u8 rol_g[0x1]; 1443 u8 reserved_at_1d8[0x1]; 1444 u8 wol_s[0x1]; 1445 u8 wol_g[0x1]; 1446 u8 wol_a[0x1]; 1447 u8 wol_b[0x1]; 1448 u8 wol_m[0x1]; 1449 u8 wol_u[0x1]; 1450 u8 wol_p[0x1]; 1451 u8 stat_rate_support[0x10]; 1452 u8 reserved_at_1f0[0xc]; 1453 u8 cqe_version[0x4]; 1454 u8 compact_address_vector[0x1]; 1455 u8 striding_rq[0x1]; 1456 u8 reserved_at_202[0x1]; 1457 u8 ipoib_enhanced_offloads[0x1]; 1458 u8 ipoib_basic_offloads[0x1]; 1459 u8 reserved_at_205[0x1]; 1460 u8 repeated_block_disabled[0x1]; 1461 u8 umr_modify_entity_size_disabled[0x1]; 1462 u8 umr_modify_atomic_disabled[0x1]; 1463 u8 umr_indirect_mkey_disabled[0x1]; 1464 u8 umr_fence[0x2]; 1465 u8 reserved_at_20c[0x3]; 1466 u8 drain_sigerr[0x1]; 1467 u8 cmdif_checksum[0x2]; 1468 u8 sigerr_cqe[0x1]; 1469 u8 reserved_at_213[0x1]; 1470 u8 wq_signature[0x1]; 1471 u8 sctr_data_cqe[0x1]; 1472 u8 reserved_at_216[0x1]; 1473 u8 sho[0x1]; 1474 u8 tph[0x1]; 1475 u8 rf[0x1]; 1476 u8 dct[0x1]; 1477 u8 qos[0x1]; 1478 u8 eth_net_offloads[0x1]; 1479 u8 roce[0x1]; 1480 u8 atomic[0x1]; 1481 u8 reserved_at_21f[0x1]; 1482 u8 cq_oi[0x1]; 1483 u8 cq_resize[0x1]; 1484 u8 cq_moderation[0x1]; 1485 u8 reserved_at_223[0x3]; 1486 u8 cq_eq_remap[0x1]; 1487 u8 pg[0x1]; 1488 u8 block_lb_mc[0x1]; 1489 u8 reserved_at_229[0x1]; 1490 u8 scqe_break_moderation[0x1]; 1491 u8 cq_period_start_from_cqe[0x1]; 1492 u8 cd[0x1]; 1493 u8 reserved_at_22d[0x1]; 1494 u8 apm[0x1]; 1495 u8 vector_calc[0x1]; 1496 u8 umr_ptr_rlky[0x1]; 1497 u8 imaicl[0x1]; 1498 u8 reserved_at_232[0x4]; 1499 u8 qkv[0x1]; 1500 u8 pkv[0x1]; 1501 u8 set_deth_sqpn[0x1]; 1502 u8 reserved_at_239[0x3]; 1503 u8 xrc[0x1]; 1504 u8 ud[0x1]; 1505 u8 uc[0x1]; 1506 u8 rc[0x1]; 1507 u8 uar_4k[0x1]; 1508 u8 reserved_at_241[0x9]; 1509 u8 uar_sz[0x6]; 1510 u8 reserved_at_250[0x8]; 1511 u8 log_pg_sz[0x8]; 1512 u8 bf[0x1]; 1513 u8 driver_version[0x1]; 1514 u8 pad_tx_eth_packet[0x1]; 1515 u8 reserved_at_263[0x8]; 1516 u8 log_bf_reg_size[0x5]; 1517 u8 reserved_at_270[0xb]; 1518 u8 lag_master[0x1]; 1519 u8 num_lag_ports[0x4]; 1520 u8 reserved_at_280[0x10]; 1521 u8 max_wqe_sz_sq[0x10]; 1522 u8 reserved_at_2a0[0xc]; 1523 u8 regexp_mmo_sq[0x1]; 1524 u8 reserved_at_2b0[0x3]; 1525 u8 max_wqe_sz_rq[0x10]; 1526 u8 max_flow_counter_31_16[0x10]; 1527 u8 max_wqe_sz_sq_dc[0x10]; 1528 u8 reserved_at_2e0[0x7]; 1529 u8 max_qp_mcg[0x19]; 1530 u8 reserved_at_300[0x10]; 1531 u8 flow_counter_bulk_alloc[0x08]; 1532 u8 log_max_mcg[0x8]; 1533 u8 reserved_at_320[0x3]; 1534 u8 log_max_transport_domain[0x5]; 1535 u8 reserved_at_328[0x3]; 1536 u8 log_max_pd[0x5]; 1537 u8 reserved_at_330[0xb]; 1538 u8 log_max_xrcd[0x5]; 1539 u8 nic_receive_steering_discard[0x1]; 1540 u8 receive_discard_vport_down[0x1]; 1541 u8 transmit_discard_vport_down[0x1]; 1542 u8 reserved_at_343[0x5]; 1543 u8 log_max_flow_counter_bulk[0x8]; 1544 u8 max_flow_counter_15_0[0x10]; 1545 u8 modify_tis[0x1]; 1546 u8 flow_counters_dump[0x1]; 1547 u8 reserved_at_360[0x1]; 1548 u8 log_max_rq[0x5]; 1549 u8 reserved_at_368[0x3]; 1550 u8 log_max_sq[0x5]; 1551 u8 reserved_at_370[0x3]; 1552 u8 log_max_tir[0x5]; 1553 u8 reserved_at_378[0x3]; 1554 u8 log_max_tis[0x5]; 1555 u8 basic_cyclic_rcv_wqe[0x1]; 1556 u8 reserved_at_381[0x2]; 1557 u8 log_max_rmp[0x5]; 1558 u8 reserved_at_388[0x3]; 1559 u8 log_max_rqt[0x5]; 1560 u8 reserved_at_390[0x3]; 1561 u8 log_max_rqt_size[0x5]; 1562 u8 reserved_at_398[0x3]; 1563 u8 log_max_tis_per_sq[0x5]; 1564 u8 ext_stride_num_range[0x1]; 1565 u8 reserved_at_3a1[0x2]; 1566 u8 log_max_stride_sz_rq[0x5]; 1567 u8 reserved_at_3a8[0x3]; 1568 u8 log_min_stride_sz_rq[0x5]; 1569 u8 reserved_at_3b0[0x3]; 1570 u8 log_max_stride_sz_sq[0x5]; 1571 u8 reserved_at_3b8[0x3]; 1572 u8 log_min_stride_sz_sq[0x5]; 1573 u8 hairpin[0x1]; 1574 u8 reserved_at_3c1[0x2]; 1575 u8 log_max_hairpin_queues[0x5]; 1576 u8 reserved_at_3c8[0x3]; 1577 u8 log_max_hairpin_wq_data_sz[0x5]; 1578 u8 reserved_at_3d0[0x3]; 1579 u8 log_max_hairpin_num_packets[0x5]; 1580 u8 reserved_at_3d8[0x3]; 1581 u8 log_max_wq_sz[0x5]; 1582 u8 nic_vport_change_event[0x1]; 1583 u8 disable_local_lb_uc[0x1]; 1584 u8 disable_local_lb_mc[0x1]; 1585 u8 log_min_hairpin_wq_data_sz[0x5]; 1586 u8 reserved_at_3e8[0x3]; 1587 u8 log_max_vlan_list[0x5]; 1588 u8 reserved_at_3f0[0x3]; 1589 u8 log_max_current_mc_list[0x5]; 1590 u8 reserved_at_3f8[0x3]; 1591 u8 log_max_current_uc_list[0x5]; 1592 u8 general_obj_types[0x40]; 1593 u8 sq_ts_format[0x2]; 1594 u8 rq_ts_format[0x2]; 1595 u8 steering_format_version[0x4]; 1596 u8 reserved_at_448[0x18]; 1597 u8 reserved_at_460[0x8]; 1598 u8 aes_xts[0x1]; 1599 u8 crypto[0x1]; 1600 u8 reserved_at_46a[0x6]; 1601 u8 max_num_eqs[0x10]; 1602 u8 reserved_at_480[0x3]; 1603 u8 log_max_l2_table[0x5]; 1604 u8 reserved_at_488[0x8]; 1605 u8 log_uar_page_sz[0x10]; 1606 u8 reserved_at_4a0[0x20]; 1607 u8 device_frequency_mhz[0x20]; 1608 u8 device_frequency_khz[0x20]; 1609 u8 reserved_at_500[0x20]; 1610 u8 num_of_uars_per_page[0x20]; 1611 u8 flex_parser_protocols[0x20]; 1612 u8 max_geneve_tlv_options[0x8]; 1613 u8 reserved_at_568[0x3]; 1614 u8 max_geneve_tlv_option_data_len[0x5]; 1615 u8 reserved_at_570[0x49]; 1616 u8 mini_cqe_resp_l3_l4_tag[0x1]; 1617 u8 mini_cqe_resp_flow_tag[0x1]; 1618 u8 enhanced_cqe_compression[0x1]; 1619 u8 mini_cqe_resp_stride_index[0x1]; 1620 u8 cqe_128_always[0x1]; 1621 u8 cqe_compression_128[0x1]; 1622 u8 cqe_compression[0x1]; 1623 u8 cqe_compression_timeout[0x10]; 1624 u8 cqe_compression_max_num[0x10]; 1625 u8 reserved_at_5e0[0x10]; 1626 u8 tag_matching[0x1]; 1627 u8 rndv_offload_rc[0x1]; 1628 u8 rndv_offload_dc[0x1]; 1629 u8 log_tag_matching_list_sz[0x5]; 1630 u8 reserved_at_5f8[0x3]; 1631 u8 log_max_xrq[0x5]; 1632 u8 affiliate_nic_vport_criteria[0x8]; 1633 u8 native_port_num[0x8]; 1634 u8 num_vhca_ports[0x8]; 1635 u8 reserved_at_618[0x6]; 1636 u8 sw_owner_id[0x1]; 1637 u8 reserved_at_61f[0x109]; 1638 u8 dma_mmo_qp[0x1]; 1639 u8 regexp_mmo_qp[0x1]; 1640 u8 compress_mmo_qp[0x1]; 1641 u8 decompress_mmo_qp[0x1]; 1642 u8 reserved_at_624[0xd4]; 1643 }; 1644 1645 struct mlx5_ifc_qos_cap_bits { 1646 u8 packet_pacing[0x1]; 1647 u8 esw_scheduling[0x1]; 1648 u8 esw_bw_share[0x1]; 1649 u8 esw_rate_limit[0x1]; 1650 u8 reserved_at_4[0x1]; 1651 u8 packet_pacing_burst_bound[0x1]; 1652 u8 packet_pacing_typical_size[0x1]; 1653 u8 flow_meter_old[0x1]; 1654 u8 reserved_at_8[0x8]; 1655 u8 log_max_flow_meter[0x8]; 1656 u8 flow_meter_reg_id[0x8]; 1657 u8 wqe_rate_pp[0x1]; 1658 u8 reserved_at_25[0x7]; 1659 u8 flow_meter[0x1]; 1660 u8 reserved_at_2e[0x17]; 1661 u8 packet_pacing_max_rate[0x20]; 1662 u8 packet_pacing_min_rate[0x20]; 1663 u8 reserved_at_80[0x10]; 1664 u8 packet_pacing_rate_table_size[0x10]; 1665 u8 esw_element_type[0x10]; 1666 u8 esw_tsar_type[0x10]; 1667 u8 reserved_at_c0[0x10]; 1668 u8 max_qos_para_vport[0x10]; 1669 u8 max_tsar_bw_share[0x20]; 1670 u8 nic_element_type[0x10]; 1671 u8 nic_tsar_type[0x10]; 1672 u8 reserved_at_120[0x3]; 1673 u8 log_meter_aso_granularity[0x5]; 1674 u8 reserved_at_128[0x3]; 1675 u8 log_meter_aso_max_alloc[0x5]; 1676 u8 reserved_at_130[0x3]; 1677 u8 log_max_num_meter_aso[0x5]; 1678 u8 reserved_at_138[0x6b0]; 1679 }; 1680 1681 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1682 u8 csum_cap[0x1]; 1683 u8 vlan_cap[0x1]; 1684 u8 lro_cap[0x1]; 1685 u8 lro_psh_flag[0x1]; 1686 u8 lro_time_stamp[0x1]; 1687 u8 lro_max_msg_sz_mode[0x2]; 1688 u8 wqe_vlan_insert[0x1]; 1689 u8 self_lb_en_modifiable[0x1]; 1690 u8 self_lb_mc[0x1]; 1691 u8 self_lb_uc[0x1]; 1692 u8 max_lso_cap[0x5]; 1693 u8 multi_pkt_send_wqe[0x2]; 1694 u8 wqe_inline_mode[0x2]; 1695 u8 rss_ind_tbl_cap[0x4]; 1696 u8 reg_umr_sq[0x1]; 1697 u8 scatter_fcs[0x1]; 1698 u8 enhanced_multi_pkt_send_wqe[0x1]; 1699 u8 tunnel_lso_const_out_ip_id[0x1]; 1700 u8 tunnel_lro_gre[0x1]; 1701 u8 tunnel_lro_vxlan[0x1]; 1702 u8 tunnel_stateless_gre[0x1]; 1703 u8 tunnel_stateless_vxlan[0x1]; 1704 u8 swp[0x1]; 1705 u8 swp_csum[0x1]; 1706 u8 swp_lso[0x1]; 1707 u8 reserved_at_23[0x8]; 1708 u8 tunnel_stateless_gtp[0x1]; 1709 u8 reserved_at_25[0x4]; 1710 u8 max_vxlan_udp_ports[0x8]; 1711 u8 reserved_at_38[0x6]; 1712 u8 max_geneve_opt_len[0x1]; 1713 u8 tunnel_stateless_geneve_rx[0x1]; 1714 u8 reserved_at_40[0x10]; 1715 u8 lro_min_mss_size[0x10]; 1716 u8 reserved_at_60[0x120]; 1717 u8 lro_timer_supported_periods[4][0x20]; 1718 u8 reserved_at_200[0x600]; 1719 }; 1720 1721 enum { 1722 MLX5_VIRTQ_TYPE_SPLIT = 0, 1723 MLX5_VIRTQ_TYPE_PACKED = 1, 1724 }; 1725 1726 enum { 1727 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0, 1728 MLX5_VIRTQ_EVENT_MODE_QP = 1, 1729 MLX5_VIRTQ_EVENT_MODE_MSIX = 2, 1730 }; 1731 1732 struct mlx5_ifc_virtio_emulation_cap_bits { 1733 u8 desc_tunnel_offload_type[0x1]; 1734 u8 eth_frame_offload_type[0x1]; 1735 u8 virtio_version_1_0[0x1]; 1736 u8 tso_ipv4[0x1]; 1737 u8 tso_ipv6[0x1]; 1738 u8 tx_csum[0x1]; 1739 u8 rx_csum[0x1]; 1740 u8 reserved_at_7[0x1][0x9]; 1741 u8 event_mode[0x8]; 1742 u8 virtio_queue_type[0x8]; 1743 u8 reserved_at_20[0x13]; 1744 u8 log_doorbell_stride[0x5]; 1745 u8 reserved_at_3b[0x3]; 1746 u8 log_doorbell_bar_size[0x5]; 1747 u8 doorbell_bar_offset[0x40]; 1748 u8 reserved_at_80[0x8]; 1749 u8 max_num_virtio_queues[0x18]; 1750 u8 reserved_at_a0[0x60]; 1751 u8 umem_1_buffer_param_a[0x20]; 1752 u8 umem_1_buffer_param_b[0x20]; 1753 u8 umem_2_buffer_param_a[0x20]; 1754 u8 umem_2_buffer_param_b[0x20]; 1755 u8 umem_3_buffer_param_a[0x20]; 1756 u8 umem_3_buffer_param_b[0x20]; 1757 u8 reserved_at_1c0[0x620]; 1758 }; 1759 1760 struct mlx5_ifc_flow_table_prop_layout_bits { 1761 u8 ft_support[0x1]; 1762 u8 flow_tag[0x1]; 1763 u8 flow_counter[0x1]; 1764 u8 flow_modify_en[0x1]; 1765 u8 modify_root[0x1]; 1766 u8 identified_miss_table[0x1]; 1767 u8 flow_table_modify[0x1]; 1768 u8 reformat[0x1]; 1769 u8 decap[0x1]; 1770 u8 reset_root_to_default[0x1]; 1771 u8 pop_vlan[0x1]; 1772 u8 push_vlan[0x1]; 1773 u8 fpga_vendor_acceleration[0x1]; 1774 u8 pop_vlan_2[0x1]; 1775 u8 push_vlan_2[0x1]; 1776 u8 reformat_and_vlan_action[0x1]; 1777 u8 modify_and_vlan_action[0x1]; 1778 u8 sw_owner[0x1]; 1779 u8 reformat_l3_tunnel_to_l2[0x1]; 1780 u8 reformat_l2_to_l3_tunnel[0x1]; 1781 u8 reformat_and_modify_action[0x1]; 1782 u8 reserved_at_15[0x9]; 1783 u8 sw_owner_v2[0x1]; 1784 u8 reserved_at_1f[0x1]; 1785 u8 reserved_at_20[0x2]; 1786 u8 log_max_ft_size[0x6]; 1787 u8 log_max_modify_header_context[0x8]; 1788 u8 max_modify_header_actions[0x8]; 1789 u8 max_ft_level[0x8]; 1790 u8 reserved_at_40[0x8]; 1791 u8 log_max_ft_sampler_num[8]; 1792 u8 metadata_reg_b_width[0x8]; 1793 u8 metadata_reg_a_width[0x8]; 1794 u8 reserved_at_60[0x18]; 1795 u8 log_max_ft_num[0x8]; 1796 u8 reserved_at_80[0x10]; 1797 u8 log_max_flow_counter[0x8]; 1798 u8 log_max_destination[0x8]; 1799 u8 reserved_at_a0[0x18]; 1800 u8 log_max_flow[0x8]; 1801 u8 reserved_at_c0[0x140]; 1802 }; 1803 1804 struct mlx5_ifc_roce_caps_bits { 1805 u8 reserved_0[0x1e]; 1806 u8 qp_ts_format[0x2]; 1807 u8 reserved_at_20[0x7e0]; 1808 }; 1809 1810 /* 1811 * Table 1872 - Flow Table Fields Supported 2 Format 1812 */ 1813 struct mlx5_ifc_ft_fields_support_2_bits { 1814 u8 reserved_at_0[0xf]; 1815 u8 tunnel_header_2_3[0x1]; 1816 u8 tunnel_header_0_1[0x1]; 1817 u8 macsec_syndrome[0x1]; 1818 u8 macsec_tag[0x1]; 1819 u8 outer_lrh_sl[0x1]; 1820 u8 inner_ipv4_ihl[0x1]; 1821 u8 outer_ipv4_ihl[0x1]; 1822 u8 psp_syndrome[0x1]; 1823 u8 inner_l3_ok[0x1]; 1824 u8 inner_l4_ok[0x1]; 1825 u8 outer_l3_ok[0x1]; 1826 u8 outer_l4_ok[0x1]; 1827 u8 psp_header[0x1]; 1828 u8 inner_ipv4_checksum_ok[0x1]; 1829 u8 inner_l4_checksum_ok[0x1]; 1830 u8 outer_ipv4_checksum_ok[0x1]; 1831 u8 outer_l4_checksum_ok[0x1]; 1832 u8 reserved_at_20[0x60]; 1833 }; 1834 1835 struct mlx5_ifc_flow_table_nic_cap_bits { 1836 u8 reserved_at_0[0x200]; 1837 struct mlx5_ifc_flow_table_prop_layout_bits 1838 flow_table_properties_nic_receive; 1839 struct mlx5_ifc_flow_table_prop_layout_bits 1840 flow_table_properties_nic_receive_rdma; 1841 struct mlx5_ifc_flow_table_prop_layout_bits 1842 flow_table_properties_nic_receive_sniffer; 1843 struct mlx5_ifc_flow_table_prop_layout_bits 1844 flow_table_properties_nic_transmit; 1845 struct mlx5_ifc_flow_table_prop_layout_bits 1846 flow_table_properties_nic_transmit_rdma; 1847 struct mlx5_ifc_flow_table_prop_layout_bits 1848 flow_table_properties_nic_transmit_sniffer; 1849 u8 reserved_at_e00[0x600]; 1850 struct mlx5_ifc_ft_fields_support_2_bits 1851 ft_field_support_2_nic_receive; 1852 }; 1853 1854 struct mlx5_ifc_cmd_hca_cap_2_bits { 1855 u8 reserved_at_0[0x80]; /* End of DW4. */ 1856 u8 reserved_at_80[0xb]; 1857 u8 log_max_num_reserved_qpn[0x5]; 1858 u8 reserved_at_90[0x3]; 1859 u8 log_reserved_qpn_granularity[0x5]; 1860 u8 reserved_at_98[0x3]; 1861 u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */ 1862 u8 max_reformat_insert_size[0x8]; 1863 u8 max_reformat_insert_offset[0x8]; 1864 u8 max_reformat_remove_size[0x8]; 1865 u8 max_reformat_remove_offset[0x8]; /* End of DW6. */ 1866 u8 aso_conntrack_reg_id[0x8]; 1867 u8 reserved_at_c8[0x3]; 1868 u8 log_conn_track_granularity[0x5]; 1869 u8 reserved_at_d0[0x3]; 1870 u8 log_conn_track_max_alloc[0x5]; 1871 u8 reserved_at_d8[0x3]; 1872 u8 log_max_conn_track_offload[0x5]; 1873 u8 reserved_at_e0[0x20]; /* End of DW7. */ 1874 u8 reserved_at_100[0x700]; 1875 }; 1876 1877 union mlx5_ifc_hca_cap_union_bits { 1878 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 1879 struct mlx5_ifc_per_protocol_networking_offload_caps_bits 1880 per_protocol_networking_offload_caps; 1881 struct mlx5_ifc_qos_cap_bits qos_cap; 1882 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps; 1883 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 1884 struct mlx5_ifc_roce_caps_bits roce_caps; 1885 u8 reserved_at_0[0x8000]; 1886 }; 1887 1888 struct mlx5_ifc_set_action_in_bits { 1889 u8 action_type[0x4]; 1890 u8 field[0xc]; 1891 u8 reserved_at_10[0x3]; 1892 u8 offset[0x5]; 1893 u8 reserved_at_18[0x3]; 1894 u8 length[0x5]; 1895 u8 data[0x20]; 1896 }; 1897 1898 struct mlx5_ifc_query_hca_cap_out_bits { 1899 u8 status[0x8]; 1900 u8 reserved_at_8[0x18]; 1901 u8 syndrome[0x20]; 1902 u8 reserved_at_40[0x40]; 1903 union mlx5_ifc_hca_cap_union_bits capability; 1904 }; 1905 1906 struct mlx5_ifc_query_hca_cap_in_bits { 1907 u8 opcode[0x10]; 1908 u8 reserved_at_10[0x10]; 1909 u8 reserved_at_20[0x10]; 1910 u8 op_mod[0x10]; 1911 u8 reserved_at_40[0x40]; 1912 }; 1913 1914 struct mlx5_ifc_mac_address_layout_bits { 1915 u8 reserved_at_0[0x10]; 1916 u8 mac_addr_47_32[0x10]; 1917 u8 mac_addr_31_0[0x20]; 1918 }; 1919 1920 struct mlx5_ifc_nic_vport_context_bits { 1921 u8 reserved_at_0[0x5]; 1922 u8 min_wqe_inline_mode[0x3]; 1923 u8 reserved_at_8[0x15]; 1924 u8 disable_mc_local_lb[0x1]; 1925 u8 disable_uc_local_lb[0x1]; 1926 u8 roce_en[0x1]; 1927 u8 arm_change_event[0x1]; 1928 u8 reserved_at_21[0x1a]; 1929 u8 event_on_mtu[0x1]; 1930 u8 event_on_promisc_change[0x1]; 1931 u8 event_on_vlan_change[0x1]; 1932 u8 event_on_mc_address_change[0x1]; 1933 u8 event_on_uc_address_change[0x1]; 1934 u8 reserved_at_40[0xc]; 1935 u8 affiliation_criteria[0x4]; 1936 u8 affiliated_vhca_id[0x10]; 1937 u8 reserved_at_60[0xd0]; 1938 u8 mtu[0x10]; 1939 u8 system_image_guid[0x40]; 1940 u8 port_guid[0x40]; 1941 u8 node_guid[0x40]; 1942 u8 reserved_at_200[0x140]; 1943 u8 qkey_violation_counter[0x10]; 1944 u8 reserved_at_350[0x430]; 1945 u8 promisc_uc[0x1]; 1946 u8 promisc_mc[0x1]; 1947 u8 promisc_all[0x1]; 1948 u8 reserved_at_783[0x2]; 1949 u8 allowed_list_type[0x3]; 1950 u8 reserved_at_788[0xc]; 1951 u8 allowed_list_size[0xc]; 1952 struct mlx5_ifc_mac_address_layout_bits permanent_address; 1953 u8 reserved_at_7e0[0x20]; 1954 }; 1955 1956 struct mlx5_ifc_query_nic_vport_context_out_bits { 1957 u8 status[0x8]; 1958 u8 reserved_at_8[0x18]; 1959 u8 syndrome[0x20]; 1960 u8 reserved_at_40[0x40]; 1961 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 1962 }; 1963 1964 struct mlx5_ifc_query_nic_vport_context_in_bits { 1965 u8 opcode[0x10]; 1966 u8 reserved_at_10[0x10]; 1967 u8 reserved_at_20[0x10]; 1968 u8 op_mod[0x10]; 1969 u8 other_vport[0x1]; 1970 u8 reserved_at_41[0xf]; 1971 u8 vport_number[0x10]; 1972 u8 reserved_at_60[0x5]; 1973 u8 allowed_list_type[0x3]; 1974 u8 reserved_at_68[0x18]; 1975 }; 1976 1977 struct mlx5_ifc_tisc_bits { 1978 u8 strict_lag_tx_port_affinity[0x1]; 1979 u8 reserved_at_1[0x3]; 1980 u8 lag_tx_port_affinity[0x04]; 1981 u8 reserved_at_8[0x4]; 1982 u8 prio[0x4]; 1983 u8 reserved_at_10[0x10]; 1984 u8 reserved_at_20[0x100]; 1985 u8 reserved_at_120[0x8]; 1986 u8 transport_domain[0x18]; 1987 u8 reserved_at_140[0x8]; 1988 u8 underlay_qpn[0x18]; 1989 u8 reserved_at_160[0x3a0]; 1990 }; 1991 1992 struct mlx5_ifc_query_tis_out_bits { 1993 u8 status[0x8]; 1994 u8 reserved_at_8[0x18]; 1995 u8 syndrome[0x20]; 1996 u8 reserved_at_40[0x40]; 1997 struct mlx5_ifc_tisc_bits tis_context; 1998 }; 1999 2000 struct mlx5_ifc_query_tis_in_bits { 2001 u8 opcode[0x10]; 2002 u8 reserved_at_10[0x10]; 2003 u8 reserved_at_20[0x10]; 2004 u8 op_mod[0x10]; 2005 u8 reserved_at_40[0x8]; 2006 u8 tisn[0x18]; 2007 u8 reserved_at_60[0x20]; 2008 }; 2009 2010 struct mlx5_ifc_alloc_transport_domain_out_bits { 2011 u8 status[0x8]; 2012 u8 reserved_at_8[0x18]; 2013 u8 syndrome[0x20]; 2014 u8 reserved_at_40[0x8]; 2015 u8 transport_domain[0x18]; 2016 u8 reserved_at_60[0x20]; 2017 }; 2018 2019 struct mlx5_ifc_alloc_transport_domain_in_bits { 2020 u8 opcode[0x10]; 2021 u8 reserved_at_10[0x10]; 2022 u8 reserved_at_20[0x10]; 2023 u8 op_mod[0x10]; 2024 u8 reserved_at_40[0x40]; 2025 }; 2026 2027 enum { 2028 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 2029 MLX5_WQ_TYPE_CYCLIC = 0x1, 2030 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 2031 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 2032 }; 2033 2034 enum { 2035 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 2036 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 2037 }; 2038 2039 struct mlx5_ifc_wq_bits { 2040 u8 wq_type[0x4]; 2041 u8 wq_signature[0x1]; 2042 u8 end_padding_mode[0x2]; 2043 u8 cd_slave[0x1]; 2044 u8 reserved_at_8[0x18]; 2045 u8 hds_skip_first_sge[0x1]; 2046 u8 log2_hds_buf_size[0x3]; 2047 u8 reserved_at_24[0x7]; 2048 u8 page_offset[0x5]; 2049 u8 lwm[0x10]; 2050 u8 reserved_at_40[0x8]; 2051 u8 pd[0x18]; 2052 u8 reserved_at_60[0x8]; 2053 u8 uar_page[0x18]; 2054 u8 dbr_addr[0x40]; 2055 u8 hw_counter[0x20]; 2056 u8 sw_counter[0x20]; 2057 u8 reserved_at_100[0xc]; 2058 u8 log_wq_stride[0x4]; 2059 u8 reserved_at_110[0x3]; 2060 u8 log_wq_pg_sz[0x5]; 2061 u8 reserved_at_118[0x3]; 2062 u8 log_wq_sz[0x5]; 2063 u8 dbr_umem_valid[0x1]; 2064 u8 wq_umem_valid[0x1]; 2065 u8 reserved_at_122[0x1]; 2066 u8 log_hairpin_num_packets[0x5]; 2067 u8 reserved_at_128[0x3]; 2068 u8 log_hairpin_data_sz[0x5]; 2069 u8 reserved_at_130[0x4]; 2070 u8 single_wqe_log_num_of_strides[0x4]; 2071 u8 two_byte_shift_en[0x1]; 2072 u8 reserved_at_139[0x4]; 2073 u8 single_stride_log_num_of_bytes[0x3]; 2074 u8 dbr_umem_id[0x20]; 2075 u8 wq_umem_id[0x20]; 2076 u8 wq_umem_offset[0x40]; 2077 u8 reserved_at_1c0[0x440]; 2078 }; 2079 2080 enum { 2081 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2082 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2083 }; 2084 2085 enum { 2086 MLX5_RQC_STATE_RST = 0x0, 2087 MLX5_RQC_STATE_RDY = 0x1, 2088 MLX5_RQC_STATE_ERR = 0x3, 2089 }; 2090 2091 struct mlx5_ifc_rqc_bits { 2092 u8 rlky[0x1]; 2093 u8 delay_drop_en[0x1]; 2094 u8 scatter_fcs[0x1]; 2095 u8 vsd[0x1]; 2096 u8 mem_rq_type[0x4]; 2097 u8 state[0x4]; 2098 u8 reserved_at_c[0x1]; 2099 u8 flush_in_error_en[0x1]; 2100 u8 hairpin[0x1]; 2101 u8 reserved_at_f[0xB]; 2102 u8 ts_format[0x02]; 2103 u8 reserved_at_1c[0x4]; 2104 u8 reserved_at_20[0x8]; 2105 u8 user_index[0x18]; 2106 u8 reserved_at_40[0x8]; 2107 u8 cqn[0x18]; 2108 u8 counter_set_id[0x8]; 2109 u8 reserved_at_68[0x18]; 2110 u8 reserved_at_80[0x8]; 2111 u8 rmpn[0x18]; 2112 u8 reserved_at_a0[0x8]; 2113 u8 hairpin_peer_sq[0x18]; 2114 u8 reserved_at_c0[0x10]; 2115 u8 hairpin_peer_vhca[0x10]; 2116 u8 reserved_at_e0[0xa0]; 2117 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */ 2118 }; 2119 2120 struct mlx5_ifc_create_rq_out_bits { 2121 u8 status[0x8]; 2122 u8 reserved_at_8[0x18]; 2123 u8 syndrome[0x20]; 2124 u8 reserved_at_40[0x8]; 2125 u8 rqn[0x18]; 2126 u8 reserved_at_60[0x20]; 2127 }; 2128 2129 struct mlx5_ifc_create_rq_in_bits { 2130 u8 opcode[0x10]; 2131 u8 uid[0x10]; 2132 u8 reserved_at_20[0x10]; 2133 u8 op_mod[0x10]; 2134 u8 reserved_at_40[0xc0]; 2135 struct mlx5_ifc_rqc_bits ctx; 2136 }; 2137 2138 struct mlx5_ifc_modify_rq_out_bits { 2139 u8 status[0x8]; 2140 u8 reserved_at_8[0x18]; 2141 u8 syndrome[0x20]; 2142 u8 reserved_at_40[0x40]; 2143 }; 2144 2145 struct mlx5_ifc_query_rq_out_bits { 2146 u8 status[0x8]; 2147 u8 reserved_at_8[0x18]; 2148 u8 syndrome[0x20]; 2149 u8 reserved_at_40[0xc0]; 2150 struct mlx5_ifc_rqc_bits rq_context; 2151 }; 2152 2153 struct mlx5_ifc_query_rq_in_bits { 2154 u8 opcode[0x10]; 2155 u8 reserved_at_10[0x10]; 2156 u8 reserved_at_20[0x10]; 2157 u8 op_mod[0x10]; 2158 u8 reserved_at_40[0x8]; 2159 u8 rqn[0x18]; 2160 u8 reserved_at_60[0x20]; 2161 }; 2162 2163 struct mlx5_ifc_create_tis_out_bits { 2164 u8 status[0x8]; 2165 u8 reserved_at_8[0x18]; 2166 u8 syndrome[0x20]; 2167 u8 reserved_at_40[0x8]; 2168 u8 tisn[0x18]; 2169 u8 reserved_at_60[0x20]; 2170 }; 2171 2172 struct mlx5_ifc_create_tis_in_bits { 2173 u8 opcode[0x10]; 2174 u8 uid[0x10]; 2175 u8 reserved_at_20[0x10]; 2176 u8 op_mod[0x10]; 2177 u8 reserved_at_40[0xc0]; 2178 struct mlx5_ifc_tisc_bits ctx; 2179 }; 2180 2181 enum { 2182 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0, 2183 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 2184 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 2185 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 2186 }; 2187 2188 struct mlx5_ifc_modify_rq_in_bits { 2189 u8 opcode[0x10]; 2190 u8 uid[0x10]; 2191 u8 reserved_at_20[0x10]; 2192 u8 op_mod[0x10]; 2193 u8 rq_state[0x4]; 2194 u8 reserved_at_44[0x4]; 2195 u8 rqn[0x18]; 2196 u8 reserved_at_60[0x20]; 2197 u8 modify_bitmask[0x40]; 2198 u8 reserved_at_c0[0x40]; 2199 struct mlx5_ifc_rqc_bits ctx; 2200 }; 2201 2202 enum { 2203 MLX5_L3_PROT_TYPE_IPV4 = 0, 2204 MLX5_L3_PROT_TYPE_IPV6 = 1, 2205 }; 2206 2207 enum { 2208 MLX5_L4_PROT_TYPE_TCP = 0, 2209 MLX5_L4_PROT_TYPE_UDP = 1, 2210 }; 2211 2212 enum { 2213 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 2214 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 2215 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 2216 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 2217 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 2218 }; 2219 2220 struct mlx5_ifc_rx_hash_field_select_bits { 2221 u8 l3_prot_type[0x1]; 2222 u8 l4_prot_type[0x1]; 2223 u8 selected_fields[0x1e]; 2224 }; 2225 2226 enum { 2227 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2228 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2229 }; 2230 2231 enum { 2232 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2233 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2234 }; 2235 2236 enum { 2237 MLX5_RX_HASH_FN_NONE = 0x0, 2238 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2239 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2240 }; 2241 2242 enum { 2243 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 2244 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 2245 }; 2246 2247 enum { 2248 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0, 2249 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1, 2250 }; 2251 2252 struct mlx5_ifc_tirc_bits { 2253 u8 reserved_at_0[0x20]; 2254 u8 disp_type[0x4]; 2255 u8 reserved_at_24[0x1c]; 2256 u8 reserved_at_40[0x40]; 2257 u8 reserved_at_80[0x4]; 2258 u8 lro_timeout_period_usecs[0x10]; 2259 u8 lro_enable_mask[0x4]; 2260 u8 lro_max_msg_sz[0x8]; 2261 u8 reserved_at_a0[0x40]; 2262 u8 reserved_at_e0[0x8]; 2263 u8 inline_rqn[0x18]; 2264 u8 rx_hash_symmetric[0x1]; 2265 u8 reserved_at_101[0x1]; 2266 u8 tunneled_offload_en[0x1]; 2267 u8 reserved_at_103[0x5]; 2268 u8 indirect_table[0x18]; 2269 u8 rx_hash_fn[0x4]; 2270 u8 reserved_at_124[0x2]; 2271 u8 self_lb_block[0x2]; 2272 u8 transport_domain[0x18]; 2273 u8 rx_hash_toeplitz_key[10][0x20]; 2274 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2275 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2276 u8 reserved_at_2c0[0x4c0]; 2277 }; 2278 2279 struct mlx5_ifc_create_tir_out_bits { 2280 u8 status[0x8]; 2281 u8 reserved_at_8[0x18]; 2282 u8 syndrome[0x20]; 2283 u8 reserved_at_40[0x8]; 2284 u8 tirn[0x18]; 2285 u8 reserved_at_60[0x20]; 2286 }; 2287 2288 struct mlx5_ifc_create_tir_in_bits { 2289 u8 opcode[0x10]; 2290 u8 uid[0x10]; 2291 u8 reserved_at_20[0x10]; 2292 u8 op_mod[0x10]; 2293 u8 reserved_at_40[0xc0]; 2294 struct mlx5_ifc_tirc_bits ctx; 2295 }; 2296 2297 enum { 2298 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0, 2299 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1, 2300 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2, 2301 /* bit 3 - tunneled_offload_en modify not supported. */ 2302 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4, 2303 }; 2304 2305 struct mlx5_ifc_modify_tir_out_bits { 2306 u8 status[0x8]; 2307 u8 reserved_at_8[0x18]; 2308 u8 syndrome[0x20]; 2309 u8 reserved_at_40[0x40]; 2310 }; 2311 2312 struct mlx5_ifc_modify_tir_in_bits { 2313 u8 opcode[0x10]; 2314 u8 uid[0x10]; 2315 u8 reserved_at_20[0x10]; 2316 u8 op_mod[0x10]; 2317 u8 reserved_at_40[0x8]; 2318 u8 tirn[0x18]; 2319 u8 reserved_at_60[0x20]; 2320 u8 modify_bitmask[0x40]; 2321 u8 reserved_at_c0[0x40]; 2322 struct mlx5_ifc_tirc_bits ctx; 2323 }; 2324 2325 enum { 2326 MLX5_INLINE_Q_TYPE_RQ = 0x0, 2327 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1, 2328 }; 2329 2330 struct mlx5_ifc_rq_num_bits { 2331 u8 reserved_at_0[0x8]; 2332 u8 rq_num[0x18]; 2333 }; 2334 2335 struct mlx5_ifc_rqtc_bits { 2336 u8 reserved_at_0[0xa5]; 2337 u8 list_q_type[0x3]; 2338 u8 reserved_at_a8[0x8]; 2339 u8 rqt_max_size[0x10]; 2340 u8 reserved_at_c0[0x10]; 2341 u8 rqt_actual_size[0x10]; 2342 u8 reserved_at_e0[0x6a0]; 2343 struct mlx5_ifc_rq_num_bits rq_num[]; 2344 }; 2345 2346 struct mlx5_ifc_create_rqt_out_bits { 2347 u8 status[0x8]; 2348 u8 reserved_at_8[0x18]; 2349 u8 syndrome[0x20]; 2350 u8 reserved_at_40[0x8]; 2351 u8 rqtn[0x18]; 2352 u8 reserved_at_60[0x20]; 2353 }; 2354 2355 #ifdef PEDANTIC 2356 #pragma GCC diagnostic ignored "-Wpedantic" 2357 #endif 2358 struct mlx5_ifc_create_rqt_in_bits { 2359 u8 opcode[0x10]; 2360 u8 uid[0x10]; 2361 u8 reserved_at_20[0x10]; 2362 u8 op_mod[0x10]; 2363 u8 reserved_at_40[0xc0]; 2364 struct mlx5_ifc_rqtc_bits rqt_context; 2365 }; 2366 2367 struct mlx5_ifc_modify_rqt_in_bits { 2368 u8 opcode[0x10]; 2369 u8 uid[0x10]; 2370 u8 reserved_at_20[0x10]; 2371 u8 op_mod[0x10]; 2372 u8 reserved_at_40[0x8]; 2373 u8 rqtn[0x18]; 2374 u8 reserved_at_60[0x20]; 2375 u8 modify_bitmask[0x40]; 2376 u8 reserved_at_c0[0x40]; 2377 struct mlx5_ifc_rqtc_bits rqt_context; 2378 }; 2379 #ifdef PEDANTIC 2380 #pragma GCC diagnostic error "-Wpedantic" 2381 #endif 2382 2383 struct mlx5_ifc_modify_rqt_out_bits { 2384 u8 status[0x8]; 2385 u8 reserved_at_8[0x18]; 2386 u8 syndrome[0x20]; 2387 u8 reserved_at_40[0x40]; 2388 }; 2389 2390 enum { 2391 MLX5_SQC_STATE_RST = 0x0, 2392 MLX5_SQC_STATE_RDY = 0x1, 2393 MLX5_SQC_STATE_ERR = 0x3, 2394 }; 2395 2396 struct mlx5_ifc_sqc_bits { 2397 u8 rlky[0x1]; 2398 u8 cd_master[0x1]; 2399 u8 fre[0x1]; 2400 u8 flush_in_error_en[0x1]; 2401 u8 allow_multi_pkt_send_wqe[0x1]; 2402 u8 min_wqe_inline_mode[0x3]; 2403 u8 state[0x4]; 2404 u8 reg_umr[0x1]; 2405 u8 allow_swp[0x1]; 2406 u8 hairpin[0x1]; 2407 u8 non_wire[0x1]; 2408 u8 static_sq_wq[0x1]; 2409 u8 reserved_at_11[0x9]; 2410 u8 ts_format[0x02]; 2411 u8 reserved_at_1c[0x4]; 2412 u8 reserved_at_20[0x8]; 2413 u8 user_index[0x18]; 2414 u8 reserved_at_40[0x8]; 2415 u8 cqn[0x18]; 2416 u8 reserved_at_60[0x8]; 2417 u8 hairpin_peer_rq[0x18]; 2418 u8 reserved_at_80[0x10]; 2419 u8 hairpin_peer_vhca[0x10]; 2420 u8 reserved_at_a0[0x50]; 2421 u8 packet_pacing_rate_limit_index[0x10]; 2422 u8 tis_lst_sz[0x10]; 2423 u8 reserved_at_110[0x10]; 2424 u8 reserved_at_120[0x40]; 2425 u8 reserved_at_160[0x8]; 2426 u8 tis_num_0[0x18]; 2427 struct mlx5_ifc_wq_bits wq; 2428 }; 2429 2430 struct mlx5_ifc_query_sq_in_bits { 2431 u8 opcode[0x10]; 2432 u8 reserved_at_10[0x10]; 2433 u8 reserved_at_20[0x10]; 2434 u8 op_mod[0x10]; 2435 u8 reserved_at_40[0x8]; 2436 u8 sqn[0x18]; 2437 u8 reserved_at_60[0x20]; 2438 }; 2439 2440 struct mlx5_ifc_modify_sq_out_bits { 2441 u8 status[0x8]; 2442 u8 reserved_at_8[0x18]; 2443 u8 syndrome[0x20]; 2444 u8 reserved_at_40[0x40]; 2445 }; 2446 2447 struct mlx5_ifc_modify_sq_in_bits { 2448 u8 opcode[0x10]; 2449 u8 uid[0x10]; 2450 u8 reserved_at_20[0x10]; 2451 u8 op_mod[0x10]; 2452 u8 sq_state[0x4]; 2453 u8 reserved_at_44[0x4]; 2454 u8 sqn[0x18]; 2455 u8 reserved_at_60[0x20]; 2456 u8 modify_bitmask[0x40]; 2457 u8 reserved_at_c0[0x40]; 2458 struct mlx5_ifc_sqc_bits ctx; 2459 }; 2460 2461 struct mlx5_ifc_create_sq_out_bits { 2462 u8 status[0x8]; 2463 u8 reserved_at_8[0x18]; 2464 u8 syndrome[0x20]; 2465 u8 reserved_at_40[0x8]; 2466 u8 sqn[0x18]; 2467 u8 reserved_at_60[0x20]; 2468 }; 2469 2470 struct mlx5_ifc_create_sq_in_bits { 2471 u8 opcode[0x10]; 2472 u8 uid[0x10]; 2473 u8 reserved_at_20[0x10]; 2474 u8 op_mod[0x10]; 2475 u8 reserved_at_40[0xc0]; 2476 struct mlx5_ifc_sqc_bits ctx; 2477 }; 2478 2479 enum { 2480 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0), 2481 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1), 2482 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2), 2483 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3), 2484 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4), 2485 }; 2486 2487 struct mlx5_ifc_flow_meter_parameters_bits { 2488 u8 valid[0x1]; 2489 u8 bucket_overflow[0x1]; 2490 u8 start_color[0x2]; 2491 u8 both_buckets_on_green[0x1]; 2492 u8 meter_mode[0x2]; 2493 u8 reserved_at_1[0x19]; 2494 u8 reserved_at_2[0x20]; 2495 u8 reserved_at_3[0x3]; 2496 u8 cbs_exponent[0x5]; 2497 u8 cbs_mantissa[0x8]; 2498 u8 reserved_at_4[0x3]; 2499 u8 cir_exponent[0x5]; 2500 u8 cir_mantissa[0x8]; 2501 u8 reserved_at_5[0x20]; 2502 u8 reserved_at_6[0x3]; 2503 u8 ebs_exponent[0x5]; 2504 u8 ebs_mantissa[0x8]; 2505 u8 reserved_at_7[0x3]; 2506 u8 eir_exponent[0x5]; 2507 u8 eir_mantissa[0x8]; 2508 u8 reserved_at_8[0x60]; 2509 }; 2510 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF) 2511 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8 2512 2513 enum { 2514 MLX5_METER_MODE_IP_LEN = 0x0, 2515 MLX5_METER_MODE_L2_LEN = 0x1, 2516 MLX5_METER_MODE_L2_IPG_LEN = 0x2, 2517 MLX5_METER_MODE_PKT = 0x3, 2518 }; 2519 2520 enum { 2521 MLX5_CQE_SIZE_64B = 0x0, 2522 MLX5_CQE_SIZE_128B = 0x1, 2523 }; 2524 2525 struct mlx5_ifc_cqc_bits { 2526 u8 status[0x4]; 2527 u8 as_notify[0x1]; 2528 u8 initiator_src_dct[0x1]; 2529 u8 dbr_umem_valid[0x1]; 2530 u8 reserved_at_7[0x1]; 2531 u8 cqe_sz[0x3]; 2532 u8 cc[0x1]; 2533 u8 reserved_at_c[0x1]; 2534 u8 scqe_break_moderation_en[0x1]; 2535 u8 oi[0x1]; 2536 u8 cq_period_mode[0x2]; 2537 u8 cqe_comp_en[0x1]; 2538 u8 mini_cqe_res_format[0x2]; 2539 u8 st[0x4]; 2540 u8 reserved_at_18[0x1]; 2541 u8 cqe_comp_layout[0x7]; 2542 u8 dbr_umem_id[0x20]; 2543 u8 reserved_at_40[0x14]; 2544 u8 page_offset[0x6]; 2545 u8 reserved_at_5a[0x2]; 2546 u8 mini_cqe_res_format_ext[0x2]; 2547 u8 cq_timestamp_format[0x2]; 2548 u8 reserved_at_60[0x3]; 2549 u8 log_cq_size[0x5]; 2550 u8 uar_page[0x18]; 2551 u8 reserved_at_80[0x4]; 2552 u8 cq_period[0xc]; 2553 u8 cq_max_count[0x10]; 2554 u8 reserved_at_a0[0x18]; 2555 u8 c_eqn[0x8]; 2556 u8 reserved_at_c0[0x3]; 2557 u8 log_page_size[0x5]; 2558 u8 reserved_at_c8[0x18]; 2559 u8 reserved_at_e0[0x20]; 2560 u8 reserved_at_100[0x8]; 2561 u8 last_notified_index[0x18]; 2562 u8 reserved_at_120[0x8]; 2563 u8 last_solicit_index[0x18]; 2564 u8 reserved_at_140[0x8]; 2565 u8 consumer_counter[0x18]; 2566 u8 reserved_at_160[0x8]; 2567 u8 producer_counter[0x18]; 2568 u8 local_partition_id[0xc]; 2569 u8 process_id[0x14]; 2570 u8 reserved_at_1A0[0x20]; 2571 u8 dbr_addr[0x40]; 2572 }; 2573 2574 struct mlx5_ifc_health_buffer_bits { 2575 u8 reserved_0[0x100]; 2576 u8 assert_existptr[0x20]; 2577 u8 assert_callra[0x20]; 2578 u8 reserved_1[0x40]; 2579 u8 fw_version[0x20]; 2580 u8 hw_id[0x20]; 2581 u8 reserved_2[0x20]; 2582 u8 irisc_index[0x8]; 2583 u8 synd[0x8]; 2584 u8 ext_synd[0x10]; 2585 }; 2586 2587 struct mlx5_ifc_initial_seg_bits { 2588 u8 fw_rev_minor[0x10]; 2589 u8 fw_rev_major[0x10]; 2590 u8 cmd_interface_rev[0x10]; 2591 u8 fw_rev_subminor[0x10]; 2592 u8 reserved_0[0x40]; 2593 u8 cmdq_phy_addr_63_32[0x20]; 2594 u8 cmdq_phy_addr_31_12[0x14]; 2595 u8 reserved_1[0x2]; 2596 u8 nic_interface[0x2]; 2597 u8 log_cmdq_size[0x4]; 2598 u8 log_cmdq_stride[0x4]; 2599 u8 command_doorbell_vector[0x20]; 2600 u8 reserved_2[0xf00]; 2601 u8 initializing[0x1]; 2602 u8 nic_interface_supported[0x7]; 2603 u8 reserved_4[0x18]; 2604 struct mlx5_ifc_health_buffer_bits health_buffer; 2605 u8 no_dram_nic_offset[0x20]; 2606 u8 reserved_5[0x6de0]; 2607 u8 internal_timer_h[0x20]; 2608 u8 internal_timer_l[0x20]; 2609 u8 reserved_6[0x20]; 2610 u8 reserved_7[0x1f]; 2611 u8 clear_int[0x1]; 2612 u8 health_syndrome[0x8]; 2613 u8 health_counter[0x18]; 2614 u8 reserved_8[0x17fc0]; 2615 }; 2616 2617 struct mlx5_ifc_create_cq_out_bits { 2618 u8 status[0x8]; 2619 u8 reserved_at_8[0x18]; 2620 u8 syndrome[0x20]; 2621 u8 reserved_at_40[0x8]; 2622 u8 cqn[0x18]; 2623 u8 reserved_at_60[0x20]; 2624 }; 2625 2626 struct mlx5_ifc_create_cq_in_bits { 2627 u8 opcode[0x10]; 2628 u8 uid[0x10]; 2629 u8 reserved_at_20[0x10]; 2630 u8 op_mod[0x10]; 2631 u8 reserved_at_40[0x40]; 2632 struct mlx5_ifc_cqc_bits cq_context; 2633 u8 cq_umem_offset[0x40]; 2634 u8 cq_umem_id[0x20]; 2635 u8 cq_umem_valid[0x1]; 2636 u8 reserved_at_2e1[0x1f]; 2637 u8 reserved_at_300[0x580]; 2638 u8 pas[]; 2639 }; 2640 2641 enum { 2642 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 2643 MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c, 2644 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d, 2645 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 2646 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d, 2647 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e, 2648 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f, 2649 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, 2650 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, 2651 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, 2652 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031, 2653 }; 2654 2655 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 2656 u8 opcode[0x10]; 2657 u8 reserved_at_10[0x20]; 2658 u8 obj_type[0x10]; 2659 u8 obj_id[0x20]; 2660 u8 reserved_at_60[0x3]; 2661 u8 log_obj_range[0x5]; 2662 u8 reserved_at_58[0x18]; 2663 }; 2664 2665 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 2666 u8 status[0x8]; 2667 u8 reserved_at_8[0x18]; 2668 u8 syndrome[0x20]; 2669 u8 obj_id[0x20]; 2670 u8 reserved_at_60[0x20]; 2671 }; 2672 2673 struct mlx5_ifc_virtio_q_counters_bits { 2674 u8 modify_field_select[0x40]; 2675 u8 reserved_at_40[0x40]; 2676 u8 received_desc[0x40]; 2677 u8 completed_desc[0x40]; 2678 u8 error_cqes[0x20]; 2679 u8 bad_desc_errors[0x20]; 2680 u8 exceed_max_chain[0x20]; 2681 u8 invalid_buffer[0x20]; 2682 u8 reserved_at_180[0x50]; 2683 }; 2684 2685 struct mlx5_ifc_geneve_tlv_option_bits { 2686 u8 modify_field_select[0x40]; 2687 u8 reserved_at_40[0x18]; 2688 u8 geneve_option_fte_index[0x8]; 2689 u8 option_class[0x10]; 2690 u8 option_type[0x8]; 2691 u8 reserved_at_78[0x3]; 2692 u8 option_data_length[0x5]; 2693 u8 reserved_at_80[0x180]; 2694 }; 2695 2696 struct mlx5_ifc_create_virtio_q_counters_in_bits { 2697 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2698 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 2699 }; 2700 2701 struct mlx5_ifc_query_virtio_q_counters_out_bits { 2702 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2703 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters; 2704 }; 2705 2706 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 2707 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2708 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 2709 }; 2710 2711 enum { 2712 MLX5_CRYPTO_KEY_SIZE_128b = 0x0, 2713 MLX5_CRYPTO_KEY_SIZE_256b = 0x1, 2714 }; 2715 2716 enum { 2717 MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1, 2718 MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2, 2719 MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3, 2720 MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4, 2721 MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5, 2722 MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6, 2723 }; 2724 2725 struct mlx5_ifc_dek_bits { 2726 u8 modify_field_select[0x40]; 2727 u8 state[0x8]; 2728 u8 reserved_at_48[0xc]; 2729 u8 key_size[0x4]; 2730 u8 has_keytag[0x1]; 2731 u8 reserved_at_59[0x3]; 2732 u8 key_purpose[0x4]; 2733 u8 reserved_at_60[0x8]; 2734 u8 pd[0x18]; 2735 u8 reserved_at_80[0x100]; 2736 u8 opaque[0x40]; 2737 u8 reserved_at_1c0[0x40]; 2738 u8 key[0x400]; 2739 u8 reserved_at_600[0x200]; 2740 }; 2741 2742 struct mlx5_ifc_create_dek_in_bits { 2743 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2744 struct mlx5_ifc_dek_bits dek; 2745 }; 2746 2747 struct mlx5_ifc_import_kek_bits { 2748 u8 modify_field_select[0x40]; 2749 u8 state[0x8]; 2750 u8 reserved_at_48[0xc]; 2751 u8 key_size[0x4]; 2752 u8 reserved_at_58[0x1a8]; 2753 u8 key[0x400]; 2754 u8 reserved_at_600[0x200]; 2755 }; 2756 2757 struct mlx5_ifc_create_import_kek_in_bits { 2758 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2759 struct mlx5_ifc_import_kek_bits import_kek; 2760 }; 2761 2762 enum { 2763 MLX5_CREDENTIAL_ROLE_OFFICER = 0x0, 2764 MLX5_CREDENTIAL_ROLE_USER = 0x1, 2765 }; 2766 2767 struct mlx5_ifc_credential_bits { 2768 u8 modify_field_select[0x40]; 2769 u8 state[0x8]; 2770 u8 reserved_at_48[0x10]; 2771 u8 credential_role[0x8]; 2772 u8 reserved_at_60[0x1a0]; 2773 u8 credential[0x180]; 2774 u8 reserved_at_380[0x480]; 2775 }; 2776 2777 struct mlx5_ifc_create_credential_in_bits { 2778 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2779 struct mlx5_ifc_credential_bits credential; 2780 }; 2781 2782 struct mlx5_ifc_crypto_login_bits { 2783 u8 modify_field_select[0x40]; 2784 u8 reserved_at_40[0x48]; 2785 u8 credential_pointer[0x18]; 2786 u8 reserved_at_a0[0x8]; 2787 u8 session_import_kek_ptr[0x18]; 2788 u8 reserved_at_c0[0x140]; 2789 u8 credential[0x180]; 2790 u8 reserved_at_380[0x480]; 2791 }; 2792 2793 struct mlx5_ifc_create_crypto_login_in_bits { 2794 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2795 struct mlx5_ifc_crypto_login_bits crypto_login; 2796 }; 2797 2798 enum { 2799 MLX5_VIRTQ_STATE_INIT = 0, 2800 MLX5_VIRTQ_STATE_RDY = 1, 2801 MLX5_VIRTQ_STATE_SUSPEND = 2, 2802 MLX5_VIRTQ_STATE_ERROR = 3, 2803 }; 2804 2805 enum { 2806 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0), 2807 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3), 2808 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4), 2809 }; 2810 2811 struct mlx5_ifc_virtio_q_bits { 2812 u8 virtio_q_type[0x8]; 2813 u8 reserved_at_8[0x5]; 2814 u8 event_mode[0x3]; 2815 u8 queue_index[0x10]; 2816 u8 full_emulation[0x1]; 2817 u8 virtio_version_1_0[0x1]; 2818 u8 reserved_at_22[0x2]; 2819 u8 offload_type[0x4]; 2820 u8 event_qpn_or_msix[0x18]; 2821 u8 doorbell_stride_idx[0x10]; 2822 u8 queue_size[0x10]; 2823 u8 device_emulation_id[0x20]; 2824 u8 desc_addr[0x40]; 2825 u8 used_addr[0x40]; 2826 u8 available_addr[0x40]; 2827 u8 virtio_q_mkey[0x20]; 2828 u8 reserved_at_160[0x18]; 2829 u8 error_type[0x8]; 2830 u8 umem_1_id[0x20]; 2831 u8 umem_1_size[0x20]; 2832 u8 umem_1_offset[0x40]; 2833 u8 umem_2_id[0x20]; 2834 u8 umem_2_size[0x20]; 2835 u8 umem_2_offset[0x40]; 2836 u8 umem_3_id[0x20]; 2837 u8 umem_3_size[0x20]; 2838 u8 umem_3_offset[0x40]; 2839 u8 counter_set_id[0x20]; 2840 u8 reserved_at_320[0x8]; 2841 u8 pd[0x18]; 2842 u8 reserved_at_340[0x2]; 2843 u8 queue_period_mode[0x2]; 2844 u8 queue_period_us[0xc]; 2845 u8 queue_max_count[0x10]; 2846 u8 reserved_at_360[0xa0]; 2847 }; 2848 2849 struct mlx5_ifc_virtio_net_q_bits { 2850 u8 modify_field_select[0x40]; 2851 u8 reserved_at_40[0x40]; 2852 u8 tso_ipv4[0x1]; 2853 u8 tso_ipv6[0x1]; 2854 u8 tx_csum[0x1]; 2855 u8 rx_csum[0x1]; 2856 u8 reserved_at_84[0x6]; 2857 u8 dirty_bitmap_dump_enable[0x1]; 2858 u8 vhost_log_page[0x5]; 2859 u8 reserved_at_90[0xc]; 2860 u8 state[0x4]; 2861 u8 reserved_at_a0[0x8]; 2862 u8 tisn_or_qpn[0x18]; 2863 u8 dirty_bitmap_mkey[0x20]; 2864 u8 dirty_bitmap_size[0x20]; 2865 u8 dirty_bitmap_addr[0x40]; 2866 u8 hw_available_index[0x10]; 2867 u8 hw_used_index[0x10]; 2868 u8 reserved_at_160[0xa0]; 2869 struct mlx5_ifc_virtio_q_bits virtio_q_context; 2870 }; 2871 2872 struct mlx5_ifc_create_virtq_in_bits { 2873 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2874 struct mlx5_ifc_virtio_net_q_bits virtq; 2875 }; 2876 2877 struct mlx5_ifc_query_virtq_out_bits { 2878 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2879 struct mlx5_ifc_virtio_net_q_bits virtq; 2880 }; 2881 2882 struct mlx5_ifc_flow_hit_aso_bits { 2883 u8 modify_field_select[0x40]; 2884 u8 reserved_at_40[0x48]; 2885 u8 access_pd[0x18]; 2886 u8 reserved_at_a0[0x160]; 2887 u8 flag[0x200]; 2888 }; 2889 2890 struct mlx5_ifc_create_flow_hit_aso_in_bits { 2891 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2892 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso; 2893 }; 2894 2895 struct mlx5_ifc_flow_meter_aso_bits { 2896 u8 modify_field_select[0x40]; 2897 u8 reserved_at_40[0x48]; 2898 u8 access_pd[0x18]; 2899 u8 reserved_at_a0[0x160]; 2900 u8 parameters[0x200]; 2901 }; 2902 2903 struct mlx5_ifc_create_flow_meter_aso_in_bits { 2904 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2905 struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso; 2906 }; 2907 2908 struct mlx5_ifc_tcp_window_params_bits { 2909 u8 max_ack[0x20]; 2910 u8 max_win[0x20]; 2911 u8 reply_end[0x20]; 2912 u8 sent_end[0x20]; 2913 }; 2914 2915 struct mlx5_ifc_conn_track_aso_bits { 2916 struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */ 2917 struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */ 2918 u8 last_end[0x20]; /* End of DW8. */ 2919 u8 last_ack[0x20]; /* End of DW9. */ 2920 u8 last_seq[0x20]; /* End of DW10. */ 2921 u8 last_win[0x10]; 2922 u8 reserved_at_170[0xa]; 2923 u8 last_dir[0x1]; 2924 u8 last_index[0x5]; /* End of DW11. */ 2925 u8 reserved_at_180[0x40]; /* End of DW13. */ 2926 u8 reply_direction_tcp_scale[0x4]; 2927 u8 reply_direction_tcp_close_initiated[0x1]; 2928 u8 reply_direction_tcp_liberal_enabled[0x1]; 2929 u8 reply_direction_tcp_data_unacked[0x1]; 2930 u8 reply_direction_tcp_max_ack[0x1]; 2931 u8 reserved_at_1c8[0x8]; 2932 u8 original_direction_tcp_scale[0x4]; 2933 u8 original_direction_tcp_close_initiated[0x1]; 2934 u8 original_direction_tcp_liberal_enabled[0x1]; 2935 u8 original_direction_tcp_data_unacked[0x1]; 2936 u8 original_direction_tcp_max_ack[0x1]; 2937 u8 reserved_at_1d8[0x8]; /* End of DW14. */ 2938 u8 valid[0x1]; 2939 u8 state[0x3]; 2940 u8 freeze_track[0x1]; 2941 u8 reserved_at_1e5[0xb]; 2942 u8 reserved_at_1f0[0x1]; 2943 u8 connection_assured[0x1]; 2944 u8 sack_permitted[0x1]; 2945 u8 challenged_acked[0x1]; 2946 u8 heartbeat[0x1]; 2947 u8 max_ack_window[0x3]; 2948 u8 reserved_at_1f8[0x1]; 2949 u8 retransmission_counter[0x3]; 2950 u8 retranmission_limit_exceeded[0x1]; 2951 u8 retranmission_limit[0x3]; /* End of DW15. */ 2952 }; 2953 2954 struct mlx5_ifc_conn_track_offload_bits { 2955 u8 modify_field_select[0x40]; 2956 u8 reserved_at_40[0x40]; 2957 u8 reserved_at_80[0x8]; 2958 u8 conn_track_aso_access_pd[0x18]; 2959 u8 reserved_at_a0[0x160]; 2960 struct mlx5_ifc_conn_track_aso_bits conn_track_aso; 2961 }; 2962 2963 struct mlx5_ifc_create_conn_track_aso_in_bits { 2964 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 2965 struct mlx5_ifc_conn_track_offload_bits conn_track_offload; 2966 }; 2967 2968 enum mlx5_access_aso_opc_mod { 2969 ASO_OPC_MOD_IPSEC = 0x0, 2970 ASO_OPC_MOD_CONNECTION_TRACKING = 0x1, 2971 ASO_OPC_MOD_POLICER = 0x2, 2972 ASO_OPC_MOD_RACE_AVOIDANCE = 0x3, 2973 ASO_OPC_MOD_FLOW_HIT = 0x4, 2974 }; 2975 2976 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30 2977 2978 enum mlx5_aso_data_mask_mode { 2979 BITWISE_64BIT = 0x0, 2980 BYTEWISE_64BYTE = 0x1, 2981 CALCULATED_64BYTE = 0x2, 2982 }; 2983 2984 #define ASO_CSEG_COND_0_OPER_OFFSET 20 2985 #define ASO_CSEG_COND_1_OPER_OFFSET 16 2986 2987 enum mlx5_aso_pre_cond_op { 2988 ASO_OP_ALWAYS_FALSE = 0x0, 2989 ASO_OP_ALWAYS_TRUE = 0x1, 2990 ASO_OP_EQUAL = 0x2, 2991 ASO_OP_NOT_EQUAL = 0x3, 2992 ASO_OP_GREATER_OR_EQUAL = 0x4, 2993 ASO_OP_LESSER_OR_EQUAL = 0x5, 2994 ASO_OP_LESSER = 0x6, 2995 ASO_OP_GREATER = 0x7, 2996 ASO_OP_CYCLIC_GREATER = 0x8, 2997 ASO_OP_CYCLIC_LESSER = 0x9, 2998 }; 2999 3000 #define ASO_CSEG_COND_OPER_OFFSET 6 3001 3002 enum mlx5_aso_op { 3003 ASO_OPER_LOGICAL_AND = 0x0, 3004 ASO_OPER_LOGICAL_OR = 0x1, 3005 }; 3006 3007 /* ASO WQE CTRL segment. */ 3008 struct mlx5_aso_cseg { 3009 uint32_t va_h; 3010 uint32_t va_l_r; 3011 uint32_t lkey; 3012 uint32_t operand_masks; 3013 uint32_t condition_0_data; 3014 uint32_t condition_0_mask; 3015 uint32_t condition_1_data; 3016 uint32_t condition_1_mask; 3017 uint64_t bitwise_data; 3018 uint64_t data_mask; 3019 } __rte_packed; 3020 3021 /* A meter data segment - 2 per ASO WQE. */ 3022 struct mlx5_aso_mtr_dseg { 3023 uint32_t v_bo_sc_bbog_mm; 3024 /* 3025 * bit 31: valid, 30: bucket overflow, 28-29: start color, 3026 * 27: both buckets on green, 24-25: meter mode. 3027 */ 3028 uint32_t reserved; 3029 uint32_t cbs_cir; 3030 /* 3031 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 3032 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 3033 */ 3034 uint32_t c_tokens; 3035 uint32_t ebs_eir; 3036 /* 3037 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 3038 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 3039 */ 3040 uint32_t e_tokens; 3041 uint64_t timestamp; 3042 } __rte_packed; 3043 3044 #define ASO_DSEG_VALID_OFFSET 31 3045 #define ASO_DSEG_BO_OFFSET 30 3046 #define ASO_DSEG_SC_OFFSET 28 3047 #define ASO_DSEG_BBOG_OFFSET 27 3048 #define ASO_DSEG_MTR_MODE 24 3049 #define ASO_DSEG_CBS_EXP_OFFSET 24 3050 #define ASO_DSEG_CBS_MAN_OFFSET 16 3051 #define ASO_DSEG_XIR_EXP_MASK 0x1F 3052 #define ASO_DSEG_XIR_EXP_OFFSET 8 3053 #define ASO_DSEG_EBS_EXP_OFFSET 24 3054 #define ASO_DSEG_EBS_MAN_OFFSET 16 3055 #define ASO_DSEG_EXP_MASK 0x1F 3056 #define ASO_DSEG_MAN_MASK 0xFF 3057 3058 #define MLX5_ASO_WQE_DSEG_SIZE 0x40 3059 #define MLX5_ASO_METERS_PER_WQE 2 3060 #define MLX5_ASO_MTRS_PER_POOL 128 3061 3062 /* ASO WQE data segment. */ 3063 struct mlx5_aso_dseg { 3064 union { 3065 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE]; 3066 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE]; 3067 }; 3068 } __rte_packed; 3069 3070 /* ASO WQE. */ 3071 struct mlx5_aso_wqe { 3072 struct mlx5_wqe_cseg general_cseg; 3073 struct mlx5_aso_cseg aso_cseg; 3074 struct mlx5_aso_dseg aso_dseg; 3075 } __rte_packed; 3076 3077 enum { 3078 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, 3079 }; 3080 3081 enum { 3082 MLX5_QP_ST_RC = 0x0, 3083 }; 3084 3085 enum { 3086 MLX5_QP_PM_MIGRATED = 0x3, 3087 }; 3088 3089 enum { 3090 MLX5_NON_ZERO_RQ = 0x0, 3091 MLX5_SRQ_RQ = 0x1, 3092 MLX5_CRQ_RQ = 0x2, 3093 MLX5_ZERO_LEN_RQ = 0x3, 3094 }; 3095 3096 struct mlx5_ifc_ads_bits { 3097 u8 fl[0x1]; 3098 u8 free_ar[0x1]; 3099 u8 reserved_at_2[0xe]; 3100 u8 pkey_index[0x10]; 3101 u8 reserved_at_20[0x8]; 3102 u8 grh[0x1]; 3103 u8 mlid[0x7]; 3104 u8 rlid[0x10]; 3105 u8 ack_timeout[0x5]; 3106 u8 reserved_at_45[0x3]; 3107 u8 src_addr_index[0x8]; 3108 u8 reserved_at_50[0x4]; 3109 u8 stat_rate[0x4]; 3110 u8 hop_limit[0x8]; 3111 u8 reserved_at_60[0x4]; 3112 u8 tclass[0x8]; 3113 u8 flow_label[0x14]; 3114 u8 rgid_rip[16][0x8]; 3115 u8 reserved_at_100[0x4]; 3116 u8 f_dscp[0x1]; 3117 u8 f_ecn[0x1]; 3118 u8 reserved_at_106[0x1]; 3119 u8 f_eth_prio[0x1]; 3120 u8 ecn[0x2]; 3121 u8 dscp[0x6]; 3122 u8 udp_sport[0x10]; 3123 u8 dei_cfi[0x1]; 3124 u8 eth_prio[0x3]; 3125 u8 sl[0x4]; 3126 u8 vhca_port_num[0x8]; 3127 u8 rmac_47_32[0x10]; 3128 u8 rmac_31_0[0x20]; 3129 }; 3130 3131 struct mlx5_ifc_qpc_bits { 3132 u8 state[0x4]; 3133 u8 lag_tx_port_affinity[0x4]; 3134 u8 st[0x8]; 3135 u8 reserved_at_10[0x3]; 3136 u8 pm_state[0x2]; 3137 u8 reserved_at_15[0x1]; 3138 u8 req_e2e_credit_mode[0x2]; 3139 u8 offload_type[0x4]; 3140 u8 end_padding_mode[0x2]; 3141 u8 reserved_at_1e[0x2]; 3142 u8 wq_signature[0x1]; 3143 u8 block_lb_mc[0x1]; 3144 u8 atomic_like_write_en[0x1]; 3145 u8 latency_sensitive[0x1]; 3146 u8 reserved_at_24[0x1]; 3147 u8 drain_sigerr[0x1]; 3148 u8 reserved_at_26[0x2]; 3149 u8 pd[0x18]; 3150 u8 mtu[0x3]; 3151 u8 log_msg_max[0x5]; 3152 u8 reserved_at_48[0x1]; 3153 u8 log_rq_size[0x4]; 3154 u8 log_rq_stride[0x3]; 3155 u8 no_sq[0x1]; 3156 u8 log_sq_size[0x4]; 3157 u8 reserved_at_55[0x3]; 3158 u8 ts_format[0x2]; 3159 u8 reserved_at_5a[0x1]; 3160 u8 rlky[0x1]; 3161 u8 ulp_stateless_offload_mode[0x4]; 3162 u8 counter_set_id[0x8]; 3163 u8 uar_page[0x18]; 3164 u8 reserved_at_80[0x8]; 3165 u8 user_index[0x18]; 3166 u8 reserved_at_a0[0x3]; 3167 u8 log_page_size[0x5]; 3168 u8 remote_qpn[0x18]; 3169 struct mlx5_ifc_ads_bits primary_address_path; 3170 struct mlx5_ifc_ads_bits secondary_address_path; 3171 u8 log_ack_req_freq[0x4]; 3172 u8 reserved_at_384[0x4]; 3173 u8 log_sra_max[0x3]; 3174 u8 reserved_at_38b[0x2]; 3175 u8 retry_count[0x3]; 3176 u8 rnr_retry[0x3]; 3177 u8 reserved_at_393[0x1]; 3178 u8 fre[0x1]; 3179 u8 cur_rnr_retry[0x3]; 3180 u8 cur_retry_count[0x3]; 3181 u8 reserved_at_39b[0x5]; 3182 u8 reserved_at_3a0[0x20]; 3183 u8 reserved_at_3c0[0x8]; 3184 u8 next_send_psn[0x18]; 3185 u8 reserved_at_3e0[0x8]; 3186 u8 cqn_snd[0x18]; 3187 u8 reserved_at_400[0x8]; 3188 u8 deth_sqpn[0x18]; 3189 u8 reserved_at_420[0x20]; 3190 u8 reserved_at_440[0x8]; 3191 u8 last_acked_psn[0x18]; 3192 u8 reserved_at_460[0x8]; 3193 u8 ssn[0x18]; 3194 u8 reserved_at_480[0x8]; 3195 u8 log_rra_max[0x3]; 3196 u8 reserved_at_48b[0x1]; 3197 u8 atomic_mode[0x4]; 3198 u8 rre[0x1]; 3199 u8 rwe[0x1]; 3200 u8 rae[0x1]; 3201 u8 reserved_at_493[0x1]; 3202 u8 page_offset[0x6]; 3203 u8 reserved_at_49a[0x3]; 3204 u8 cd_slave_receive[0x1]; 3205 u8 cd_slave_send[0x1]; 3206 u8 cd_master[0x1]; 3207 u8 reserved_at_4a0[0x3]; 3208 u8 min_rnr_nak[0x5]; 3209 u8 next_rcv_psn[0x18]; 3210 u8 reserved_at_4c0[0x8]; 3211 u8 xrcd[0x18]; 3212 u8 reserved_at_4e0[0x8]; 3213 u8 cqn_rcv[0x18]; 3214 u8 dbr_addr[0x40]; 3215 u8 q_key[0x20]; 3216 u8 reserved_at_560[0x5]; 3217 u8 rq_type[0x3]; 3218 u8 srqn_rmpn_xrqn[0x18]; 3219 u8 reserved_at_580[0x8]; 3220 u8 rmsn[0x18]; 3221 u8 hw_sq_wqebb_counter[0x10]; 3222 u8 sw_sq_wqebb_counter[0x10]; 3223 u8 hw_rq_counter[0x20]; 3224 u8 sw_rq_counter[0x20]; 3225 u8 reserved_at_600[0x20]; 3226 u8 reserved_at_620[0xf]; 3227 u8 cgs[0x1]; 3228 u8 cs_req[0x8]; 3229 u8 cs_res[0x8]; 3230 u8 dc_access_key[0x40]; 3231 u8 reserved_at_680[0x3]; 3232 u8 dbr_umem_valid[0x1]; 3233 u8 reserved_at_684[0x9c]; 3234 u8 dbr_umem_id[0x20]; 3235 }; 3236 3237 struct mlx5_ifc_create_qp_out_bits { 3238 u8 status[0x8]; 3239 u8 reserved_at_8[0x18]; 3240 u8 syndrome[0x20]; 3241 u8 reserved_at_40[0x8]; 3242 u8 qpn[0x18]; 3243 u8 reserved_at_60[0x20]; 3244 }; 3245 3246 struct mlx5_ifc_qpc_extension_bits { 3247 u8 reserved_at_0[0x2]; 3248 u8 mmo[0x1]; 3249 u8 reserved_at_3[0x5fd]; 3250 }; 3251 3252 #ifdef PEDANTIC 3253 #pragma GCC diagnostic ignored "-Wpedantic" 3254 #endif 3255 struct mlx5_ifc_qpc_pas_list_bits { 3256 u8 pas[0][0x40]; 3257 }; 3258 3259 #ifdef PEDANTIC 3260 #pragma GCC diagnostic ignored "-Wpedantic" 3261 #endif 3262 struct mlx5_ifc_qpc_extension_and_pas_list_bits { 3263 struct mlx5_ifc_qpc_extension_bits qpc_data_extension; 3264 u8 pas[0][0x40]; 3265 }; 3266 3267 3268 #ifdef PEDANTIC 3269 #pragma GCC diagnostic ignored "-Wpedantic" 3270 #endif 3271 struct mlx5_ifc_create_qp_in_bits { 3272 u8 opcode[0x10]; 3273 u8 uid[0x10]; 3274 u8 reserved_at_20[0x10]; 3275 u8 op_mod[0x10]; 3276 u8 qpc_ext[0x1]; 3277 u8 reserved_at_41[0x3f]; 3278 u8 opt_param_mask[0x20]; 3279 u8 reserved_at_a0[0x20]; 3280 struct mlx5_ifc_qpc_bits qpc; 3281 u8 wq_umem_offset[0x40]; 3282 u8 wq_umem_id[0x20]; 3283 u8 wq_umem_valid[0x1]; 3284 u8 reserved_at_861[0x1f]; 3285 union { 3286 struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list; 3287 struct mlx5_ifc_qpc_extension_and_pas_list_bits 3288 qpc_extension_and_pas_list; 3289 }; 3290 }; 3291 #ifdef PEDANTIC 3292 #pragma GCC diagnostic error "-Wpedantic" 3293 #endif 3294 3295 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3296 u8 status[0x8]; 3297 u8 reserved_at_8[0x18]; 3298 u8 syndrome[0x20]; 3299 u8 reserved_at_40[0x40]; 3300 }; 3301 3302 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3303 u8 opcode[0x10]; 3304 u8 uid[0x10]; 3305 u8 reserved_at_20[0x10]; 3306 u8 op_mod[0x10]; 3307 u8 reserved_at_40[0x8]; 3308 u8 qpn[0x18]; 3309 u8 reserved_at_60[0x20]; 3310 u8 opt_param_mask[0x20]; 3311 u8 reserved_at_a0[0x20]; 3312 struct mlx5_ifc_qpc_bits qpc; 3313 u8 reserved_at_800[0x80]; 3314 }; 3315 3316 struct mlx5_ifc_sqd2rts_qp_out_bits { 3317 u8 status[0x8]; 3318 u8 reserved_at_8[0x18]; 3319 u8 syndrome[0x20]; 3320 u8 reserved_at_40[0x40]; 3321 }; 3322 3323 struct mlx5_ifc_sqd2rts_qp_in_bits { 3324 u8 opcode[0x10]; 3325 u8 uid[0x10]; 3326 u8 reserved_at_20[0x10]; 3327 u8 op_mod[0x10]; 3328 u8 reserved_at_40[0x8]; 3329 u8 qpn[0x18]; 3330 u8 reserved_at_60[0x20]; 3331 u8 opt_param_mask[0x20]; 3332 u8 reserved_at_a0[0x20]; 3333 struct mlx5_ifc_qpc_bits qpc; 3334 u8 reserved_at_800[0x80]; 3335 }; 3336 3337 struct mlx5_ifc_rts2rts_qp_out_bits { 3338 u8 status[0x8]; 3339 u8 reserved_at_8[0x18]; 3340 u8 syndrome[0x20]; 3341 u8 reserved_at_40[0x40]; 3342 }; 3343 3344 struct mlx5_ifc_rts2rts_qp_in_bits { 3345 u8 opcode[0x10]; 3346 u8 uid[0x10]; 3347 u8 reserved_at_20[0x10]; 3348 u8 op_mod[0x10]; 3349 u8 reserved_at_40[0x8]; 3350 u8 qpn[0x18]; 3351 u8 reserved_at_60[0x20]; 3352 u8 opt_param_mask[0x20]; 3353 u8 reserved_at_a0[0x20]; 3354 struct mlx5_ifc_qpc_bits qpc; 3355 u8 reserved_at_800[0x80]; 3356 }; 3357 3358 struct mlx5_ifc_rtr2rts_qp_out_bits { 3359 u8 status[0x8]; 3360 u8 reserved_at_8[0x18]; 3361 u8 syndrome[0x20]; 3362 u8 reserved_at_40[0x40]; 3363 }; 3364 3365 struct mlx5_ifc_rtr2rts_qp_in_bits { 3366 u8 opcode[0x10]; 3367 u8 uid[0x10]; 3368 u8 reserved_at_20[0x10]; 3369 u8 op_mod[0x10]; 3370 u8 reserved_at_40[0x8]; 3371 u8 qpn[0x18]; 3372 u8 reserved_at_60[0x20]; 3373 u8 opt_param_mask[0x20]; 3374 u8 reserved_at_a0[0x20]; 3375 struct mlx5_ifc_qpc_bits qpc; 3376 u8 reserved_at_800[0x80]; 3377 }; 3378 3379 struct mlx5_ifc_rst2init_qp_out_bits { 3380 u8 status[0x8]; 3381 u8 reserved_at_8[0x18]; 3382 u8 syndrome[0x20]; 3383 u8 reserved_at_40[0x40]; 3384 }; 3385 3386 struct mlx5_ifc_rst2init_qp_in_bits { 3387 u8 opcode[0x10]; 3388 u8 uid[0x10]; 3389 u8 reserved_at_20[0x10]; 3390 u8 op_mod[0x10]; 3391 u8 reserved_at_40[0x8]; 3392 u8 qpn[0x18]; 3393 u8 reserved_at_60[0x20]; 3394 u8 opt_param_mask[0x20]; 3395 u8 reserved_at_a0[0x20]; 3396 struct mlx5_ifc_qpc_bits qpc; 3397 u8 reserved_at_800[0x80]; 3398 }; 3399 3400 struct mlx5_ifc_init2rtr_qp_out_bits { 3401 u8 status[0x8]; 3402 u8 reserved_at_8[0x18]; 3403 u8 syndrome[0x20]; 3404 u8 reserved_at_40[0x40]; 3405 }; 3406 3407 struct mlx5_ifc_init2rtr_qp_in_bits { 3408 u8 opcode[0x10]; 3409 u8 uid[0x10]; 3410 u8 reserved_at_20[0x10]; 3411 u8 op_mod[0x10]; 3412 u8 reserved_at_40[0x8]; 3413 u8 qpn[0x18]; 3414 u8 reserved_at_60[0x20]; 3415 u8 opt_param_mask[0x20]; 3416 u8 reserved_at_a0[0x20]; 3417 struct mlx5_ifc_qpc_bits qpc; 3418 u8 reserved_at_800[0x80]; 3419 }; 3420 3421 struct mlx5_ifc_init2init_qp_out_bits { 3422 u8 status[0x8]; 3423 u8 reserved_at_8[0x18]; 3424 u8 syndrome[0x20]; 3425 u8 reserved_at_40[0x40]; 3426 }; 3427 3428 struct mlx5_ifc_init2init_qp_in_bits { 3429 u8 opcode[0x10]; 3430 u8 uid[0x10]; 3431 u8 reserved_at_20[0x10]; 3432 u8 op_mod[0x10]; 3433 u8 reserved_at_40[0x8]; 3434 u8 qpn[0x18]; 3435 u8 reserved_at_60[0x20]; 3436 u8 opt_param_mask[0x20]; 3437 u8 reserved_at_a0[0x20]; 3438 struct mlx5_ifc_qpc_bits qpc; 3439 u8 reserved_at_800[0x80]; 3440 }; 3441 3442 struct mlx5_ifc_dealloc_pd_out_bits { 3443 u8 status[0x8]; 3444 u8 reserved_0[0x18]; 3445 u8 syndrome[0x20]; 3446 u8 reserved_1[0x40]; 3447 }; 3448 3449 struct mlx5_ifc_dealloc_pd_in_bits { 3450 u8 opcode[0x10]; 3451 u8 reserved_0[0x10]; 3452 u8 reserved_1[0x10]; 3453 u8 op_mod[0x10]; 3454 u8 reserved_2[0x8]; 3455 u8 pd[0x18]; 3456 u8 reserved_3[0x20]; 3457 }; 3458 3459 struct mlx5_ifc_alloc_pd_out_bits { 3460 u8 status[0x8]; 3461 u8 reserved_0[0x18]; 3462 u8 syndrome[0x20]; 3463 u8 reserved_1[0x8]; 3464 u8 pd[0x18]; 3465 u8 reserved_2[0x20]; 3466 }; 3467 3468 struct mlx5_ifc_alloc_pd_in_bits { 3469 u8 opcode[0x10]; 3470 u8 reserved_0[0x10]; 3471 u8 reserved_1[0x10]; 3472 u8 op_mod[0x10]; 3473 u8 reserved_2[0x40]; 3474 }; 3475 3476 #ifdef PEDANTIC 3477 #pragma GCC diagnostic ignored "-Wpedantic" 3478 #endif 3479 struct mlx5_ifc_query_qp_out_bits { 3480 u8 status[0x8]; 3481 u8 reserved_at_8[0x18]; 3482 u8 syndrome[0x20]; 3483 u8 reserved_at_40[0x40]; 3484 u8 opt_param_mask[0x20]; 3485 u8 reserved_at_a0[0x20]; 3486 struct mlx5_ifc_qpc_bits qpc; 3487 u8 reserved_at_800[0x80]; 3488 u8 pas[0][0x40]; 3489 }; 3490 #ifdef PEDANTIC 3491 #pragma GCC diagnostic error "-Wpedantic" 3492 #endif 3493 3494 struct mlx5_ifc_query_qp_in_bits { 3495 u8 opcode[0x10]; 3496 u8 reserved_at_10[0x10]; 3497 u8 reserved_at_20[0x10]; 3498 u8 op_mod[0x10]; 3499 u8 reserved_at_40[0x8]; 3500 u8 qpn[0x18]; 3501 u8 reserved_at_60[0x20]; 3502 }; 3503 3504 enum { 3505 MLX5_DATA_RATE = 0x0, 3506 MLX5_WQE_RATE = 0x1, 3507 }; 3508 3509 struct mlx5_ifc_set_pp_rate_limit_context_bits { 3510 u8 rate_limit[0x20]; 3511 u8 burst_upper_bound[0x20]; 3512 u8 reserved_at_40[0xC]; 3513 u8 rate_mode[0x4]; 3514 u8 typical_packet_size[0x10]; 3515 u8 reserved_at_60[0x120]; 3516 }; 3517 3518 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u 3519 3520 #ifdef PEDANTIC 3521 #pragma GCC diagnostic ignored "-Wpedantic" 3522 #endif 3523 struct mlx5_ifc_access_register_out_bits { 3524 u8 status[0x8]; 3525 u8 reserved_at_8[0x18]; 3526 u8 syndrome[0x20]; 3527 u8 reserved_at_40[0x40]; 3528 u8 register_data[0][0x20]; 3529 }; 3530 3531 struct mlx5_ifc_access_register_in_bits { 3532 u8 opcode[0x10]; 3533 u8 reserved_at_10[0x10]; 3534 u8 reserved_at_20[0x10]; 3535 u8 op_mod[0x10]; 3536 u8 reserved_at_40[0x10]; 3537 u8 register_id[0x10]; 3538 u8 argument[0x20]; 3539 u8 register_data[0][0x20]; 3540 }; 3541 #ifdef PEDANTIC 3542 #pragma GCC diagnostic error "-Wpedantic" 3543 #endif 3544 3545 enum { 3546 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 3547 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 3548 }; 3549 3550 enum { 3551 MLX5_REGISTER_ID_MTUTC = 0x9055, 3552 MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002, 3553 MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003, 3554 MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004, 3555 MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005, 3556 }; 3557 3558 struct mlx5_ifc_register_mtutc_bits { 3559 u8 time_stamp_mode[0x2]; 3560 u8 time_stamp_state[0x2]; 3561 u8 reserved_at_4[0x18]; 3562 u8 operation[0x4]; 3563 u8 freq_adjustment[0x20]; 3564 u8 reserved_at_40[0x40]; 3565 u8 utc_sec[0x20]; 3566 u8 utc_nsec[0x20]; 3567 u8 time_adjustment[0x20]; 3568 }; 3569 3570 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0 3571 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1 3572 3573 struct mlx5_ifc_crypto_operational_register_bits { 3574 u8 wrapped_crypto_operational[0x1]; 3575 u8 reserved_at_1[0x1b]; 3576 u8 kek_size[0x4]; 3577 u8 reserved_at_20[0x20]; 3578 u8 credential[0x140]; 3579 u8 kek[0x100]; 3580 u8 reserved_at_280[0x180]; 3581 }; 3582 3583 struct mlx5_ifc_crypto_commissioning_register_bits { 3584 u8 token[0x1]; /* TODO: add size after PRM update */ 3585 }; 3586 3587 struct mlx5_ifc_import_kek_handle_register_bits { 3588 struct mlx5_ifc_crypto_login_bits crypto_login_object; 3589 struct mlx5_ifc_import_kek_bits import_kek_object; 3590 u8 reserved_at_200[0x4]; 3591 u8 write_operation[0x4]; 3592 u8 import_kek_id[0x18]; 3593 u8 reserved_at_220[0xe0]; 3594 }; 3595 3596 struct mlx5_ifc_credential_handle_register_bits { 3597 struct mlx5_ifc_crypto_login_bits crypto_login_object; 3598 struct mlx5_ifc_credential_bits credential_object; 3599 u8 reserved_at_200[0x4]; 3600 u8 write_operation[0x4]; 3601 u8 credential_id[0x18]; 3602 u8 reserved_at_220[0xe0]; 3603 }; 3604 3605 enum { 3606 MLX5_REGISTER_ADD_OPERATION = 0x1, 3607 MLX5_REGISTER_DELETE_OPERATION = 0x2, 3608 }; 3609 3610 struct mlx5_ifc_parse_graph_arc_bits { 3611 u8 start_inner_tunnel[0x1]; 3612 u8 reserved_at_1[0x7]; 3613 u8 arc_parse_graph_node[0x8]; 3614 u8 compare_condition_value[0x10]; 3615 u8 parse_graph_node_handle[0x20]; 3616 u8 reserved_at_40[0x40]; 3617 }; 3618 3619 struct mlx5_ifc_parse_graph_flow_match_sample_bits { 3620 u8 flow_match_sample_en[0x1]; 3621 u8 reserved_at_1[0x3]; 3622 u8 flow_match_sample_offset_mode[0x4]; 3623 u8 reserved_at_5[0x8]; 3624 u8 flow_match_sample_field_offset[0x10]; 3625 u8 reserved_at_32[0x4]; 3626 u8 flow_match_sample_field_offset_shift[0x4]; 3627 u8 flow_match_sample_field_base_offset[0x8]; 3628 u8 reserved_at_48[0xd]; 3629 u8 flow_match_sample_tunnel_mode[0x3]; 3630 u8 flow_match_sample_field_offset_mask[0x20]; 3631 u8 flow_match_sample_field_id[0x20]; 3632 }; 3633 3634 struct mlx5_ifc_parse_graph_flex_bits { 3635 u8 modify_field_select[0x40]; 3636 u8 reserved_at_64[0x20]; 3637 u8 header_length_base_value[0x10]; 3638 u8 reserved_at_112[0x4]; 3639 u8 header_length_field_shift[0x4]; 3640 u8 reserved_at_120[0x4]; 3641 u8 header_length_mode[0x4]; 3642 u8 header_length_field_offset[0x10]; 3643 u8 next_header_field_offset[0x10]; 3644 u8 reserved_at_160[0x1b]; 3645 u8 next_header_field_size[0x5]; 3646 u8 header_length_field_mask[0x20]; 3647 u8 reserved_at_224[0x20]; 3648 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8]; 3649 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8]; 3650 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8]; 3651 }; 3652 3653 struct mlx5_ifc_create_flex_parser_in_bits { 3654 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3655 struct mlx5_ifc_parse_graph_flex_bits flex; 3656 }; 3657 3658 struct mlx5_ifc_create_flex_parser_out_bits { 3659 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 3660 struct mlx5_ifc_parse_graph_flex_bits flex; 3661 }; 3662 3663 struct mlx5_ifc_parse_graph_flex_out_bits { 3664 u8 status[0x8]; 3665 u8 reserved_at_8[0x18]; 3666 u8 syndrome[0x20]; 3667 u8 reserved_at_40[0x40]; 3668 struct mlx5_ifc_parse_graph_flex_bits capability; 3669 }; 3670 3671 struct regexp_params_field_select_bits { 3672 u8 reserved_at_0[0x1e]; 3673 u8 stop_engine[0x1]; 3674 u8 db_umem_id[0x1]; 3675 }; 3676 3677 struct mlx5_ifc_regexp_params_bits { 3678 u8 reserved_at_0[0x1f]; 3679 u8 stop_engine[0x1]; 3680 u8 db_umem_id[0x20]; 3681 u8 db_umem_offset[0x40]; 3682 u8 reserved_at_80[0x100]; 3683 }; 3684 3685 struct mlx5_ifc_set_regexp_params_in_bits { 3686 u8 opcode[0x10]; 3687 u8 uid[0x10]; 3688 u8 reserved_at_20[0x10]; 3689 u8 op_mod[0x10]; 3690 u8 reserved_at_40[0x18]; 3691 u8 engine_id[0x8]; 3692 struct regexp_params_field_select_bits field_select; 3693 struct mlx5_ifc_regexp_params_bits regexp_params; 3694 }; 3695 3696 struct mlx5_ifc_set_regexp_params_out_bits { 3697 u8 status[0x8]; 3698 u8 reserved_at_8[0x18]; 3699 u8 syndrome[0x20]; 3700 u8 reserved_at_18[0x40]; 3701 }; 3702 3703 struct mlx5_ifc_query_regexp_params_in_bits { 3704 u8 opcode[0x10]; 3705 u8 uid[0x10]; 3706 u8 reserved_at_20[0x10]; 3707 u8 op_mod[0x10]; 3708 u8 reserved_at_40[0x18]; 3709 u8 engine_id[0x8]; 3710 u8 reserved[0x20]; 3711 }; 3712 3713 struct mlx5_ifc_query_regexp_params_out_bits { 3714 u8 status[0x8]; 3715 u8 reserved_at_8[0x18]; 3716 u8 syndrome[0x20]; 3717 u8 reserved[0x40]; 3718 struct mlx5_ifc_regexp_params_bits regexp_params; 3719 }; 3720 3721 struct mlx5_ifc_set_regexp_register_in_bits { 3722 u8 opcode[0x10]; 3723 u8 uid[0x10]; 3724 u8 reserved_at_20[0x10]; 3725 u8 op_mod[0x10]; 3726 u8 reserved_at_40[0x18]; 3727 u8 engine_id[0x8]; 3728 u8 register_address[0x20]; 3729 u8 register_data[0x20]; 3730 u8 reserved[0x60]; 3731 }; 3732 3733 struct mlx5_ifc_set_regexp_register_out_bits { 3734 u8 status[0x8]; 3735 u8 reserved_at_8[0x18]; 3736 u8 syndrome[0x20]; 3737 u8 reserved[0x40]; 3738 }; 3739 3740 struct mlx5_ifc_query_regexp_register_in_bits { 3741 u8 opcode[0x10]; 3742 u8 uid[0x10]; 3743 u8 reserved_at_20[0x10]; 3744 u8 op_mod[0x10]; 3745 u8 reserved_at_40[0x18]; 3746 u8 engine_id[0x8]; 3747 u8 register_address[0x20]; 3748 }; 3749 3750 struct mlx5_ifc_query_regexp_register_out_bits { 3751 u8 status[0x8]; 3752 u8 reserved_at_8[0x18]; 3753 u8 syndrome[0x20]; 3754 u8 reserved[0x20]; 3755 u8 register_data[0x20]; 3756 }; 3757 3758 /* Queue counters. */ 3759 struct mlx5_ifc_alloc_q_counter_out_bits { 3760 u8 status[0x8]; 3761 u8 reserved_at_8[0x18]; 3762 u8 syndrome[0x20]; 3763 u8 reserved_at_40[0x18]; 3764 u8 counter_set_id[0x8]; 3765 u8 reserved_at_60[0x20]; 3766 }; 3767 3768 struct mlx5_ifc_alloc_q_counter_in_bits { 3769 u8 opcode[0x10]; 3770 u8 uid[0x10]; 3771 u8 reserved_at_20[0x10]; 3772 u8 op_mod[0x10]; 3773 u8 reserved_at_40[0x40]; 3774 }; 3775 3776 struct mlx5_ifc_query_q_counter_out_bits { 3777 u8 status[0x8]; 3778 u8 reserved_at_8[0x18]; 3779 u8 syndrome[0x20]; 3780 u8 reserved_at_40[0x40]; 3781 u8 rx_write_requests[0x20]; 3782 u8 reserved_at_a0[0x20]; 3783 u8 rx_read_requests[0x20]; 3784 u8 reserved_at_e0[0x20]; 3785 u8 rx_atomic_requests[0x20]; 3786 u8 reserved_at_120[0x20]; 3787 u8 rx_dct_connect[0x20]; 3788 u8 reserved_at_160[0x20]; 3789 u8 out_of_buffer[0x20]; 3790 u8 reserved_at_1a0[0x20]; 3791 u8 out_of_sequence[0x20]; 3792 u8 reserved_at_1e0[0x20]; 3793 u8 duplicate_request[0x20]; 3794 u8 reserved_at_220[0x20]; 3795 u8 rnr_nak_retry_err[0x20]; 3796 u8 reserved_at_260[0x20]; 3797 u8 packet_seq_err[0x20]; 3798 u8 reserved_at_2a0[0x20]; 3799 u8 implied_nak_seq_err[0x20]; 3800 u8 reserved_at_2e0[0x20]; 3801 u8 local_ack_timeout_err[0x20]; 3802 u8 reserved_at_320[0xa0]; 3803 u8 resp_local_length_error[0x20]; 3804 u8 req_local_length_error[0x20]; 3805 u8 resp_local_qp_error[0x20]; 3806 u8 local_operation_error[0x20]; 3807 u8 resp_local_protection[0x20]; 3808 u8 req_local_protection[0x20]; 3809 u8 resp_cqe_error[0x20]; 3810 u8 req_cqe_error[0x20]; 3811 u8 req_mw_binding[0x20]; 3812 u8 req_bad_response[0x20]; 3813 u8 req_remote_invalid_request[0x20]; 3814 u8 resp_remote_invalid_request[0x20]; 3815 u8 req_remote_access_errors[0x20]; 3816 u8 resp_remote_access_errors[0x20]; 3817 u8 req_remote_operation_errors[0x20]; 3818 u8 req_transport_retries_exceeded[0x20]; 3819 u8 cq_overflow[0x20]; 3820 u8 resp_cqe_flush_error[0x20]; 3821 u8 req_cqe_flush_error[0x20]; 3822 u8 reserved_at_620[0x1e0]; 3823 }; 3824 3825 struct mlx5_ifc_query_q_counter_in_bits { 3826 u8 opcode[0x10]; 3827 u8 uid[0x10]; 3828 u8 reserved_at_20[0x10]; 3829 u8 op_mod[0x10]; 3830 u8 reserved_at_40[0x80]; 3831 u8 clear[0x1]; 3832 u8 reserved_at_c1[0x1f]; 3833 u8 reserved_at_e0[0x18]; 3834 u8 counter_set_id[0x8]; 3835 }; 3836 3837 /* CQE format mask. */ 3838 #define MLX5E_CQE_FORMAT_MASK 0xc 3839 3840 /* MPW opcode. */ 3841 #define MLX5_OPC_MOD_MPW 0x01 3842 3843 /* Compressed Rx CQE structure. */ 3844 struct mlx5_mini_cqe8 { 3845 union { 3846 uint32_t rx_hash_result; 3847 struct { 3848 union { 3849 uint16_t checksum; 3850 uint16_t flow_tag_high; 3851 struct { 3852 uint8_t reserved; 3853 uint8_t hdr_type; 3854 }; 3855 }; 3856 uint16_t stride_idx; 3857 }; 3858 struct { 3859 uint16_t wqe_counter; 3860 uint8_t s_wqe_opcode; 3861 uint8_t reserved; 3862 } s_wqe_info; 3863 }; 3864 union { 3865 uint32_t byte_cnt_flow; 3866 uint32_t byte_cnt; 3867 }; 3868 }; 3869 3870 /* Mini CQE responder format. */ 3871 enum { 3872 MLX5_CQE_RESP_FORMAT_HASH = 0x0, 3873 MLX5_CQE_RESP_FORMAT_CSUM = 0x1, 3874 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2, 3875 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3, 3876 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4, 3877 }; 3878 3879 /* srTCM PRM flow meter parameters. */ 3880 enum { 3881 MLX5_FLOW_COLOR_RED = 0, 3882 MLX5_FLOW_COLOR_YELLOW, 3883 MLX5_FLOW_COLOR_GREEN, 3884 MLX5_FLOW_COLOR_UNDEFINED, 3885 }; 3886 3887 /* Maximum value of srTCM & trTCM metering parameters. */ 3888 #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F)) 3889 #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF) 3890 3891 /* The bits meter color use. */ 3892 #define MLX5_MTR_COLOR_BITS 8 3893 3894 /* The bit size of one register. */ 3895 #define MLX5_REG_BITS 32 3896 3897 /* Idle bits for non-color usage in color register. */ 3898 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS) 3899 3900 /* Length mode of dynamic flex parser graph node. */ 3901 enum mlx5_parse_graph_node_len_mode { 3902 MLX5_GRAPH_NODE_LEN_FIXED = 0x0, 3903 MLX5_GRAPH_NODE_LEN_FIELD = 0x1, 3904 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2, 3905 }; 3906 3907 /* Offset mode of the samples of flex parser. */ 3908 enum mlx5_parse_graph_flow_match_sample_offset_mode { 3909 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0, 3910 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1, 3911 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2, 3912 }; 3913 3914 /* Node index for an input / output arc of the flex parser graph. */ 3915 enum mlx5_parse_graph_arc_node_index { 3916 MLX5_GRAPH_ARC_NODE_NULL = 0x0, 3917 MLX5_GRAPH_ARC_NODE_HEAD = 0x1, 3918 MLX5_GRAPH_ARC_NODE_MAC = 0x2, 3919 MLX5_GRAPH_ARC_NODE_IP = 0x3, 3920 MLX5_GRAPH_ARC_NODE_GRE = 0x4, 3921 MLX5_GRAPH_ARC_NODE_UDP = 0x5, 3922 MLX5_GRAPH_ARC_NODE_MPLS = 0x6, 3923 MLX5_GRAPH_ARC_NODE_TCP = 0x7, 3924 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8, 3925 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9, 3926 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa, 3927 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f, 3928 }; 3929 3930 /** 3931 * Convert a user mark to flow mark. 3932 * 3933 * @param val 3934 * Mark value to convert. 3935 * 3936 * @return 3937 * Converted mark value. 3938 */ 3939 static inline uint32_t 3940 mlx5_flow_mark_set(uint32_t val) 3941 { 3942 uint32_t ret; 3943 3944 /* 3945 * Add one to the user value to differentiate un-marked flows from 3946 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it 3947 * remains untouched. 3948 */ 3949 if (val != MLX5_FLOW_MARK_DEFAULT) 3950 ++val; 3951 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 3952 /* 3953 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit 3954 * word, byte-swapped by the kernel on little-endian systems. In this 3955 * case, left-shifting the resulting big-endian value ensures the 3956 * least significant 24 bits are retained when converting it back. 3957 */ 3958 ret = rte_cpu_to_be_32(val) >> 8; 3959 #else 3960 ret = val; 3961 #endif 3962 return ret; 3963 } 3964 3965 /** 3966 * Convert a mark to user mark. 3967 * 3968 * @param val 3969 * Mark value to convert. 3970 * 3971 * @return 3972 * Converted mark value. 3973 */ 3974 static inline uint32_t 3975 mlx5_flow_mark_get(uint32_t val) 3976 { 3977 /* 3978 * Subtract one from the retrieved value. It was added by 3979 * mlx5_flow_mark_set() to distinguish unmarked flows. 3980 */ 3981 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 3982 return (val >> 8) - 1; 3983 #else 3984 return val - 1; 3985 #endif 3986 } 3987 3988 /** 3989 * Convert a timestamp format to configure settings in the queue context. 3990 * 3991 * @param val 3992 * timestamp format supported by the queue. 3993 * 3994 * @return 3995 * Converted timstamp format settings. 3996 */ 3997 static inline uint32_t 3998 mlx5_ts_format_conv(uint32_t ts_format) 3999 { 4000 return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ? 4001 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : 4002 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; 4003 } 4004 4005 #endif /* RTE_PMD_MLX5_PRM_H_ */ 4006