1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_BYTES(access_register_out) + 57 sizeof(uint32_t) * dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Perform write access to the registers. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param[in] reg_id 83 * Register identifier according to the PRM. 84 * @param[in] arg 85 * Register access auxiliary parameter according to the PRM. 86 * @param[out] data 87 * Pointer to the buffer containing data to write. 88 * @param[in] dw_cnt 89 * Buffer size in double words (32bit units). 90 * 91 * @return 92 * 0 on success, a negative value otherwise. 93 */ 94 int 95 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 96 uint32_t *data, uint32_t dw_cnt) 97 { 98 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 99 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 100 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 101 int status, rc; 102 void *ptr; 103 104 MLX5_ASSERT(data && dw_cnt); 105 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 106 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 107 DRV_LOG(ERR, "Data to write exceeds max size"); 108 return -1; 109 } 110 MLX5_SET(access_register_in, in, opcode, 111 MLX5_CMD_OP_ACCESS_REGISTER_USER); 112 MLX5_SET(access_register_in, in, op_mod, 113 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 114 MLX5_SET(access_register_in, in, register_id, reg_id); 115 MLX5_SET(access_register_in, in, argument, arg); 116 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 117 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 118 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 119 120 rc = mlx5_glue->devx_general_cmd(ctx, in, 121 MLX5_ST_SZ_BYTES(access_register_in) + 122 dw_cnt * sizeof(uint32_t), 123 out, sizeof(out)); 124 if (rc) 125 goto error; 126 status = MLX5_GET(access_register_out, out, status); 127 if (status) { 128 int syndrome = MLX5_GET(access_register_out, out, syndrome); 129 130 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " 131 "status %x, syndrome = %x", 132 reg_id, status, syndrome); 133 return -1; 134 } 135 return 0; 136 error: 137 rc = (rc > 0) ? -rc : rc; 138 return rc; 139 } 140 141 /** 142 * Allocate flow counters via devx interface. 143 * 144 * @param[in] ctx 145 * Context returned from mlx5 open_device() glue function. 146 * @param dcs 147 * Pointer to counters properties structure to be filled by the routine. 148 * @param bulk_n_128 149 * Bulk counter numbers in 128 counters units. 150 * 151 * @return 152 * Pointer to counter object on success, a negative value otherwise and 153 * rte_errno is set. 154 */ 155 struct mlx5_devx_obj * 156 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 157 { 158 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 159 0, SOCKET_ID_ANY); 160 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 161 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 162 163 if (!dcs) { 164 rte_errno = ENOMEM; 165 return NULL; 166 } 167 MLX5_SET(alloc_flow_counter_in, in, opcode, 168 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 169 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 170 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 171 sizeof(in), out, sizeof(out)); 172 if (!dcs->obj) { 173 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 174 rte_errno = errno; 175 mlx5_free(dcs); 176 return NULL; 177 } 178 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 179 return dcs; 180 } 181 182 /** 183 * Query flow counters values. 184 * 185 * @param[in] dcs 186 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 187 * @param[in] clear 188 * Whether hardware should clear the counters after the query or not. 189 * @param[in] n_counters 190 * 0 in case of 1 counter to read, otherwise the counter number to read. 191 * @param pkts 192 * The number of packets that matched the flow. 193 * @param bytes 194 * The number of bytes that matched the flow. 195 * @param mkey 196 * The mkey key for batch query. 197 * @param addr 198 * The address in the mkey range for batch query. 199 * @param cmd_comp 200 * The completion object for asynchronous batch query. 201 * @param async_id 202 * The ID to be returned in the asynchronous batch query response. 203 * 204 * @return 205 * 0 on success, a negative value otherwise. 206 */ 207 int 208 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 209 int clear, uint32_t n_counters, 210 uint64_t *pkts, uint64_t *bytes, 211 uint32_t mkey, void *addr, 212 void *cmd_comp, 213 uint64_t async_id) 214 { 215 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 216 MLX5_ST_SZ_BYTES(traffic_counter); 217 uint32_t out[out_len]; 218 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 219 void *stats; 220 int rc; 221 222 MLX5_SET(query_flow_counter_in, in, opcode, 223 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 224 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 225 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 226 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 227 228 if (n_counters) { 229 MLX5_SET(query_flow_counter_in, in, num_of_counters, 230 n_counters); 231 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 232 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 233 MLX5_SET64(query_flow_counter_in, in, address, 234 (uint64_t)(uintptr_t)addr); 235 } 236 if (!cmd_comp) 237 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 238 out_len); 239 else 240 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 241 out_len, async_id, 242 cmd_comp); 243 if (rc) { 244 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 245 rte_errno = rc; 246 return -rc; 247 } 248 if (!n_counters) { 249 stats = MLX5_ADDR_OF(query_flow_counter_out, 250 out, flow_statistics); 251 *pkts = MLX5_GET64(traffic_counter, stats, packets); 252 *bytes = MLX5_GET64(traffic_counter, stats, octets); 253 } 254 return 0; 255 } 256 257 /** 258 * Create a new mkey. 259 * 260 * @param[in] ctx 261 * Context returned from mlx5 open_device() glue function. 262 * @param[in] attr 263 * Attributes of the requested mkey. 264 * 265 * @return 266 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 267 * is set. 268 */ 269 struct mlx5_devx_obj * 270 mlx5_devx_cmd_mkey_create(void *ctx, 271 struct mlx5_devx_mkey_attr *attr) 272 { 273 struct mlx5_klm *klm_array = attr->klm_array; 274 int klm_num = attr->klm_num; 275 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 276 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 277 uint32_t in[in_size_dw]; 278 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 279 void *mkc; 280 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 281 0, SOCKET_ID_ANY); 282 size_t pgsize; 283 uint32_t translation_size; 284 285 if (!mkey) { 286 rte_errno = ENOMEM; 287 return NULL; 288 } 289 memset(in, 0, in_size_dw * 4); 290 pgsize = rte_mem_page_size(); 291 if (pgsize == (size_t)-1) { 292 mlx5_free(mkey); 293 DRV_LOG(ERR, "Failed to get page size"); 294 rte_errno = ENOMEM; 295 return NULL; 296 } 297 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 298 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 299 if (klm_num > 0) { 300 int i; 301 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 302 klm_pas_mtt); 303 translation_size = RTE_ALIGN(klm_num, 4); 304 for (i = 0; i < klm_num; i++) { 305 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 306 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 307 MLX5_SET64(klm, klm, address, klm_array[i].address); 308 klm += MLX5_ST_SZ_BYTES(klm); 309 } 310 for (; i < (int)translation_size; i++) { 311 MLX5_SET(klm, klm, mkey, 0x0); 312 MLX5_SET64(klm, klm, address, 0x0); 313 klm += MLX5_ST_SZ_BYTES(klm); 314 } 315 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 316 MLX5_MKC_ACCESS_MODE_KLM_FBS : 317 MLX5_MKC_ACCESS_MODE_KLM); 318 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 319 } else { 320 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 321 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 322 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 323 } 324 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 325 translation_size); 326 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 327 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 328 MLX5_SET(mkc, mkc, lw, 0x1); 329 MLX5_SET(mkc, mkc, lr, 0x1); 330 if (attr->set_remote_rw) { 331 MLX5_SET(mkc, mkc, rw, 0x1); 332 MLX5_SET(mkc, mkc, rr, 0x1); 333 } 334 MLX5_SET(mkc, mkc, qpn, 0xffffff); 335 MLX5_SET(mkc, mkc, pd, attr->pd); 336 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 337 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 338 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 339 MLX5_SET(mkc, mkc, relaxed_ordering_write, 340 attr->relaxed_ordering_write); 341 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 342 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 343 MLX5_SET64(mkc, mkc, len, attr->size); 344 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 345 if (attr->crypto_en) { 346 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 347 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 348 } 349 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 350 sizeof(out)); 351 if (!mkey->obj) { 352 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 353 klm_num ? "an in" : "a ", errno); 354 rte_errno = errno; 355 mlx5_free(mkey); 356 return NULL; 357 } 358 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 359 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 360 return mkey; 361 } 362 363 /** 364 * Get status of devx command response. 365 * Mainly used for asynchronous commands. 366 * 367 * @param[in] out 368 * The out response buffer. 369 * 370 * @return 371 * 0 on success, non-zero value otherwise. 372 */ 373 int 374 mlx5_devx_get_out_command_status(void *out) 375 { 376 int status; 377 378 if (!out) 379 return -EINVAL; 380 status = MLX5_GET(query_flow_counter_out, out, status); 381 if (status) { 382 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 383 384 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 385 syndrome); 386 } 387 return status; 388 } 389 390 /** 391 * Destroy any object allocated by a Devx API. 392 * 393 * @param[in] obj 394 * Pointer to a general object. 395 * 396 * @return 397 * 0 on success, a negative value otherwise. 398 */ 399 int 400 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 401 { 402 int ret; 403 404 if (!obj) 405 return 0; 406 ret = mlx5_glue->devx_obj_destroy(obj->obj); 407 mlx5_free(obj); 408 return ret; 409 } 410 411 /** 412 * Query NIC vport context. 413 * Fills minimal inline attribute. 414 * 415 * @param[in] ctx 416 * ibv contexts returned from mlx5dv_open_device. 417 * @param[in] vport 418 * vport index 419 * @param[out] attr 420 * Attributes device values. 421 * 422 * @return 423 * 0 on success, a negative value otherwise. 424 */ 425 static int 426 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 427 unsigned int vport, 428 struct mlx5_hca_attr *attr) 429 { 430 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 431 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 432 void *vctx; 433 int status, syndrome, rc; 434 435 /* Query NIC vport context to determine inline mode. */ 436 MLX5_SET(query_nic_vport_context_in, in, opcode, 437 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 438 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 439 if (vport) 440 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 441 rc = mlx5_glue->devx_general_cmd(ctx, 442 in, sizeof(in), 443 out, sizeof(out)); 444 if (rc) 445 goto error; 446 status = MLX5_GET(query_nic_vport_context_out, out, status); 447 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 448 if (status) { 449 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 450 "status %x, syndrome = %x", status, syndrome); 451 return -1; 452 } 453 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 454 nic_vport_context); 455 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 456 min_wqe_inline_mode); 457 return 0; 458 error: 459 rc = (rc > 0) ? -rc : rc; 460 return rc; 461 } 462 463 /** 464 * Query NIC vDPA attributes. 465 * 466 * @param[in] ctx 467 * Context returned from mlx5 open_device() glue function. 468 * @param[out] vdpa_attr 469 * vDPA Attributes structure to fill. 470 */ 471 static void 472 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 473 struct mlx5_hca_vdpa_attr *vdpa_attr) 474 { 475 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 476 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 477 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 478 int status, syndrome, rc; 479 480 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 481 MLX5_SET(query_hca_cap_in, in, op_mod, 482 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 483 MLX5_HCA_CAP_OPMOD_GET_CUR); 484 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 485 status = MLX5_GET(query_hca_cap_out, out, status); 486 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 487 if (rc || status) { 488 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 489 " status %x, syndrome = %x", status, syndrome); 490 vdpa_attr->valid = 0; 491 } else { 492 vdpa_attr->valid = 1; 493 vdpa_attr->desc_tunnel_offload_type = 494 MLX5_GET(virtio_emulation_cap, hcattr, 495 desc_tunnel_offload_type); 496 vdpa_attr->eth_frame_offload_type = 497 MLX5_GET(virtio_emulation_cap, hcattr, 498 eth_frame_offload_type); 499 vdpa_attr->virtio_version_1_0 = 500 MLX5_GET(virtio_emulation_cap, hcattr, 501 virtio_version_1_0); 502 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 503 tso_ipv4); 504 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 505 tso_ipv6); 506 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 507 tx_csum); 508 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 509 rx_csum); 510 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 511 event_mode); 512 vdpa_attr->virtio_queue_type = 513 MLX5_GET(virtio_emulation_cap, hcattr, 514 virtio_queue_type); 515 vdpa_attr->log_doorbell_stride = 516 MLX5_GET(virtio_emulation_cap, hcattr, 517 log_doorbell_stride); 518 vdpa_attr->log_doorbell_bar_size = 519 MLX5_GET(virtio_emulation_cap, hcattr, 520 log_doorbell_bar_size); 521 vdpa_attr->doorbell_bar_offset = 522 MLX5_GET64(virtio_emulation_cap, hcattr, 523 doorbell_bar_offset); 524 vdpa_attr->max_num_virtio_queues = 525 MLX5_GET(virtio_emulation_cap, hcattr, 526 max_num_virtio_queues); 527 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 528 umem_1_buffer_param_a); 529 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 530 umem_1_buffer_param_b); 531 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 532 umem_2_buffer_param_a); 533 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 534 umem_2_buffer_param_b); 535 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 536 umem_3_buffer_param_a); 537 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 538 umem_3_buffer_param_b); 539 } 540 } 541 542 int 543 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 544 uint32_t ids[], uint32_t num) 545 { 546 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 547 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 548 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 549 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 550 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 551 int ret; 552 uint32_t idx = 0; 553 uint32_t i; 554 555 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 556 rte_errno = EINVAL; 557 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 558 return -rte_errno; 559 } 560 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 561 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 562 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 563 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 564 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 565 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 566 out, sizeof(out)); 567 if (ret) { 568 rte_errno = ret; 569 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 570 (void *)flex_obj); 571 return -rte_errno; 572 } 573 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 574 void *s_off = (void *)((char *)sample + i * 575 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 576 uint32_t en; 577 578 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 579 flow_match_sample_en); 580 if (!en) 581 continue; 582 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 583 flow_match_sample_field_id); 584 } 585 if (num != idx) { 586 rte_errno = EINVAL; 587 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 588 return -rte_errno; 589 } 590 return ret; 591 } 592 593 594 struct mlx5_devx_obj * 595 mlx5_devx_cmd_create_flex_parser(void *ctx, 596 struct mlx5_devx_graph_node_attr *data) 597 { 598 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 599 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 600 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 601 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 602 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 603 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 604 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 605 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 606 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 607 uint32_t i; 608 609 if (!parse_flex_obj) { 610 DRV_LOG(ERR, "Failed to allocate flex parser data."); 611 rte_errno = ENOMEM; 612 return NULL; 613 } 614 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 615 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 616 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 617 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 618 MLX5_SET(parse_graph_flex, flex, header_length_mode, 619 data->header_length_mode); 620 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 621 data->header_length_base_value); 622 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 623 data->header_length_field_offset); 624 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 625 data->header_length_field_shift); 626 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 627 data->header_length_field_mask); 628 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 629 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 630 void *s_off = (void *)((char *)sample + i * 631 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 632 633 if (!s->flow_match_sample_en) 634 continue; 635 MLX5_SET(parse_graph_flow_match_sample, s_off, 636 flow_match_sample_en, !!s->flow_match_sample_en); 637 MLX5_SET(parse_graph_flow_match_sample, s_off, 638 flow_match_sample_field_offset, 639 s->flow_match_sample_field_offset); 640 MLX5_SET(parse_graph_flow_match_sample, s_off, 641 flow_match_sample_offset_mode, 642 s->flow_match_sample_offset_mode); 643 MLX5_SET(parse_graph_flow_match_sample, s_off, 644 flow_match_sample_field_offset_mask, 645 s->flow_match_sample_field_offset_mask); 646 MLX5_SET(parse_graph_flow_match_sample, s_off, 647 flow_match_sample_field_offset_shift, 648 s->flow_match_sample_field_offset_shift); 649 MLX5_SET(parse_graph_flow_match_sample, s_off, 650 flow_match_sample_field_base_offset, 651 s->flow_match_sample_field_base_offset); 652 MLX5_SET(parse_graph_flow_match_sample, s_off, 653 flow_match_sample_tunnel_mode, 654 s->flow_match_sample_tunnel_mode); 655 } 656 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 657 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 658 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 659 void *in_off = (void *)((char *)in_arc + i * 660 MLX5_ST_SZ_BYTES(parse_graph_arc)); 661 void *out_off = (void *)((char *)out_arc + i * 662 MLX5_ST_SZ_BYTES(parse_graph_arc)); 663 664 if (ia->arc_parse_graph_node != 0) { 665 MLX5_SET(parse_graph_arc, in_off, 666 compare_condition_value, 667 ia->compare_condition_value); 668 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 669 ia->start_inner_tunnel); 670 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 671 ia->arc_parse_graph_node); 672 MLX5_SET(parse_graph_arc, in_off, 673 parse_graph_node_handle, 674 ia->parse_graph_node_handle); 675 } 676 if (oa->arc_parse_graph_node != 0) { 677 MLX5_SET(parse_graph_arc, out_off, 678 compare_condition_value, 679 oa->compare_condition_value); 680 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 681 oa->start_inner_tunnel); 682 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 683 oa->arc_parse_graph_node); 684 MLX5_SET(parse_graph_arc, out_off, 685 parse_graph_node_handle, 686 oa->parse_graph_node_handle); 687 } 688 } 689 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 690 out, sizeof(out)); 691 if (!parse_flex_obj->obj) { 692 rte_errno = errno; 693 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 694 "by using DevX."); 695 mlx5_free(parse_flex_obj); 696 return NULL; 697 } 698 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 699 return parse_flex_obj; 700 } 701 702 static int 703 mlx5_devx_query_pkt_integrity_match(void *hcattr) 704 { 705 return MLX5_GET(flow_table_nic_cap, hcattr, 706 ft_field_support_2_nic_receive.inner_l3_ok) && 707 MLX5_GET(flow_table_nic_cap, hcattr, 708 ft_field_support_2_nic_receive.inner_l4_ok) && 709 MLX5_GET(flow_table_nic_cap, hcattr, 710 ft_field_support_2_nic_receive.outer_l3_ok) && 711 MLX5_GET(flow_table_nic_cap, hcattr, 712 ft_field_support_2_nic_receive.outer_l4_ok) && 713 MLX5_GET(flow_table_nic_cap, hcattr, 714 ft_field_support_2_nic_receive 715 .inner_ipv4_checksum_ok) && 716 MLX5_GET(flow_table_nic_cap, hcattr, 717 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 718 MLX5_GET(flow_table_nic_cap, hcattr, 719 ft_field_support_2_nic_receive 720 .outer_ipv4_checksum_ok) && 721 MLX5_GET(flow_table_nic_cap, hcattr, 722 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 723 } 724 725 /** 726 * Query HCA attributes. 727 * Using those attributes we can check on run time if the device 728 * is having the required capabilities. 729 * 730 * @param[in] ctx 731 * Context returned from mlx5 open_device() glue function. 732 * @param[out] attr 733 * Attributes device values. 734 * 735 * @return 736 * 0 on success, a negative value otherwise. 737 */ 738 int 739 mlx5_devx_cmd_query_hca_attr(void *ctx, 740 struct mlx5_hca_attr *attr) 741 { 742 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 743 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 744 void *hcattr; 745 int status, syndrome, rc, i; 746 uint64_t general_obj_types_supported = 0; 747 748 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 749 MLX5_SET(query_hca_cap_in, in, op_mod, 750 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 751 MLX5_HCA_CAP_OPMOD_GET_CUR); 752 753 rc = mlx5_glue->devx_general_cmd(ctx, 754 in, sizeof(in), out, sizeof(out)); 755 if (rc) 756 goto error; 757 status = MLX5_GET(query_hca_cap_out, out, status); 758 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 759 if (status) { 760 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 761 "status %x, syndrome = %x", status, syndrome); 762 return -1; 763 } 764 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 765 attr->flow_counter_bulk_alloc_bitmap = 766 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 767 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 768 flow_counters_dump); 769 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 770 log_max_rqt_size); 771 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 772 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 773 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 774 log_max_hairpin_queues); 775 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 776 log_max_hairpin_wq_data_sz); 777 attr->log_max_hairpin_num_packets = MLX5_GET 778 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 779 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 780 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 781 relaxed_ordering_write); 782 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 783 relaxed_ordering_read); 784 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 785 access_register_user); 786 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 787 eth_net_offloads); 788 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 789 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 790 flex_parser_protocols); 791 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 792 max_geneve_tlv_options); 793 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 794 max_geneve_tlv_option_data_len); 795 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 796 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 797 general_obj_types) & 798 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 799 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 800 general_obj_types) & 801 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 802 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 803 general_obj_types) & 804 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 805 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 806 general_obj_types) & 807 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 808 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 809 wqe_index_ignore_cap); 810 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 811 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 812 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 813 log_max_static_sq_wq); 814 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 815 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 816 device_frequency_khz); 817 attr->scatter_fcs_w_decap_disable = 818 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 819 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 820 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 821 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 822 attr->steering_format_version = 823 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 824 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 825 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 826 regexp_num_of_engines); 827 /* Read the general_obj_types bitmap and extract the relevant bits. */ 828 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 829 general_obj_types); 830 attr->vdpa.valid = !!(general_obj_types_supported & 831 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 832 attr->vdpa.queue_counters_valid = 833 !!(general_obj_types_supported & 834 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 835 attr->parse_graph_flex_node = 836 !!(general_obj_types_supported & 837 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 838 attr->flow_hit_aso = !!(general_obj_types_supported & 839 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 840 attr->geneve_tlv_opt = !!(general_obj_types_supported & 841 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 842 attr->dek = !!(general_obj_types_supported & 843 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 844 attr->import_kek = !!(general_obj_types_supported & 845 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 846 attr->credential = !!(general_obj_types_supported & 847 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 848 attr->crypto_login = !!(general_obj_types_supported & 849 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 850 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 851 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 852 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 853 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 854 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 855 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 856 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 857 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 858 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 859 attr->reg_c_preserve = 860 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 861 attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo); 862 attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress); 863 attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress); 864 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 865 compress_min_block_size); 866 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 867 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 868 log_compress_mmo_size); 869 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 870 log_decompress_mmo_size); 871 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 872 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 873 mini_cqe_resp_flow_tag); 874 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 875 mini_cqe_resp_l3_l4_tag); 876 attr->umr_indirect_mkey_disabled = 877 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 878 attr->umr_modify_entity_size_disabled = 879 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 880 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 881 if (attr->crypto) 882 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 883 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 884 general_obj_types) & 885 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 886 if (attr->qos.sup) { 887 MLX5_SET(query_hca_cap_in, in, op_mod, 888 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 889 MLX5_HCA_CAP_OPMOD_GET_CUR); 890 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 891 out, sizeof(out)); 892 if (rc) 893 goto error; 894 if (status) { 895 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 896 " status %x, syndrome = %x", status, syndrome); 897 return -1; 898 } 899 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 900 attr->qos.flow_meter_old = 901 MLX5_GET(qos_cap, hcattr, flow_meter_old); 902 attr->qos.log_max_flow_meter = 903 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 904 attr->qos.flow_meter_reg_c_ids = 905 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 906 attr->qos.flow_meter = 907 MLX5_GET(qos_cap, hcattr, flow_meter); 908 attr->qos.packet_pacing = 909 MLX5_GET(qos_cap, hcattr, packet_pacing); 910 attr->qos.wqe_rate_pp = 911 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 912 if (attr->qos.flow_meter_aso_sup) { 913 attr->qos.log_meter_aso_granularity = 914 MLX5_GET(qos_cap, hcattr, 915 log_meter_aso_granularity); 916 attr->qos.log_meter_aso_max_alloc = 917 MLX5_GET(qos_cap, hcattr, 918 log_meter_aso_max_alloc); 919 attr->qos.log_max_num_meter_aso = 920 MLX5_GET(qos_cap, hcattr, 921 log_max_num_meter_aso); 922 } 923 } 924 if (attr->vdpa.valid) 925 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 926 if (!attr->eth_net_offloads) 927 return 0; 928 929 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 930 memset(in, 0, sizeof(in)); 931 memset(out, 0, sizeof(out)); 932 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 933 MLX5_SET(query_hca_cap_in, in, op_mod, 934 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 935 MLX5_HCA_CAP_OPMOD_GET_CUR); 936 937 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 938 if (rc) 939 goto error; 940 status = MLX5_GET(query_hca_cap_out, out, status); 941 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 942 if (status) { 943 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 944 "status %x, syndrome = %x", status, syndrome); 945 attr->log_max_ft_sampler_num = 0; 946 return -1; 947 } 948 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 949 attr->log_max_ft_sampler_num = MLX5_GET 950 (flow_table_nic_cap, hcattr, 951 flow_table_properties_nic_receive.log_max_ft_sampler_num); 952 attr->flow.tunnel_header_0_1 = MLX5_GET 953 (flow_table_nic_cap, hcattr, 954 ft_field_support_2_nic_receive.tunnel_header_0_1); 955 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 956 attr->inner_ipv4_ihl = MLX5_GET 957 (flow_table_nic_cap, hcattr, 958 ft_field_support_2_nic_receive.inner_ipv4_ihl); 959 attr->outer_ipv4_ihl = MLX5_GET 960 (flow_table_nic_cap, hcattr, 961 ft_field_support_2_nic_receive.outer_ipv4_ihl); 962 /* Query HCA offloads for Ethernet protocol. */ 963 memset(in, 0, sizeof(in)); 964 memset(out, 0, sizeof(out)); 965 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 966 MLX5_SET(query_hca_cap_in, in, op_mod, 967 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 968 MLX5_HCA_CAP_OPMOD_GET_CUR); 969 970 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 971 if (rc) { 972 attr->eth_net_offloads = 0; 973 goto error; 974 } 975 status = MLX5_GET(query_hca_cap_out, out, status); 976 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 977 if (status) { 978 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 979 "status %x, syndrome = %x", status, syndrome); 980 attr->eth_net_offloads = 0; 981 return -1; 982 } 983 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 984 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 985 hcattr, wqe_vlan_insert); 986 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 987 hcattr, csum_cap); 988 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 989 lro_cap); 990 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 991 hcattr, tunnel_lro_gre); 992 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 993 hcattr, tunnel_lro_vxlan); 994 attr->lro_max_msg_sz_mode = MLX5_GET 995 (per_protocol_networking_offload_caps, 996 hcattr, lro_max_msg_sz_mode); 997 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 998 attr->lro_timer_supported_periods[i] = 999 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1000 lro_timer_supported_periods[i]); 1001 } 1002 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1003 hcattr, lro_min_mss_size); 1004 attr->tunnel_stateless_geneve_rx = 1005 MLX5_GET(per_protocol_networking_offload_caps, 1006 hcattr, tunnel_stateless_geneve_rx); 1007 attr->geneve_max_opt_len = 1008 MLX5_GET(per_protocol_networking_offload_caps, 1009 hcattr, max_geneve_opt_len); 1010 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1011 hcattr, wqe_inline_mode); 1012 attr->tunnel_stateless_gtp = MLX5_GET 1013 (per_protocol_networking_offload_caps, 1014 hcattr, tunnel_stateless_gtp); 1015 attr->rss_ind_tbl_cap = MLX5_GET 1016 (per_protocol_networking_offload_caps, 1017 hcattr, rss_ind_tbl_cap); 1018 /* Query HCA attribute for ROCE. */ 1019 if (attr->roce) { 1020 memset(in, 0, sizeof(in)); 1021 memset(out, 0, sizeof(out)); 1022 MLX5_SET(query_hca_cap_in, in, opcode, 1023 MLX5_CMD_OP_QUERY_HCA_CAP); 1024 MLX5_SET(query_hca_cap_in, in, op_mod, 1025 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1026 MLX5_HCA_CAP_OPMOD_GET_CUR); 1027 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 1028 out, sizeof(out)); 1029 if (rc) 1030 goto error; 1031 status = MLX5_GET(query_hca_cap_out, out, status); 1032 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 1033 if (status) { 1034 DRV_LOG(DEBUG, 1035 "Failed to query devx HCA ROCE capabilities, " 1036 "status %x, syndrome = %x", status, syndrome); 1037 return -1; 1038 } 1039 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 1040 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1041 } 1042 if (attr->eth_virt && 1043 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1044 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1045 if (rc) { 1046 attr->eth_virt = 0; 1047 goto error; 1048 } 1049 } 1050 return 0; 1051 error: 1052 rc = (rc > 0) ? -rc : rc; 1053 return rc; 1054 } 1055 1056 /** 1057 * Query TIS transport domain from QP verbs object using DevX API. 1058 * 1059 * @param[in] qp 1060 * Pointer to verbs QP returned by ibv_create_qp . 1061 * @param[in] tis_num 1062 * TIS number of TIS to query. 1063 * @param[out] tis_td 1064 * Pointer to TIS transport domain variable, to be set by the routine. 1065 * 1066 * @return 1067 * 0 on success, a negative value otherwise. 1068 */ 1069 int 1070 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1071 uint32_t *tis_td) 1072 { 1073 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1074 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1075 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1076 int rc; 1077 void *tis_ctx; 1078 1079 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1080 MLX5_SET(query_tis_in, in, tisn, tis_num); 1081 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1082 if (rc) { 1083 DRV_LOG(ERR, "Failed to query QP using DevX"); 1084 return -rc; 1085 }; 1086 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1087 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1088 return 0; 1089 #else 1090 (void)qp; 1091 (void)tis_num; 1092 (void)tis_td; 1093 return -ENOTSUP; 1094 #endif 1095 } 1096 1097 /** 1098 * Fill WQ data for DevX API command. 1099 * Utility function for use when creating DevX objects containing a WQ. 1100 * 1101 * @param[in] wq_ctx 1102 * Pointer to WQ context to fill with data. 1103 * @param [in] wq_attr 1104 * Pointer to WQ attributes structure to fill in WQ context. 1105 */ 1106 static void 1107 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1108 { 1109 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1110 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1111 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1112 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1113 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1114 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1115 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1116 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1117 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1118 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1119 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1120 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1121 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1122 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1123 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1124 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1125 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1126 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1127 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1128 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1129 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1130 wq_attr->log_hairpin_num_packets); 1131 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1132 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1133 wq_attr->single_wqe_log_num_of_strides); 1134 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1135 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1136 wq_attr->single_stride_log_num_of_bytes); 1137 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1138 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1139 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1140 } 1141 1142 /** 1143 * Create RQ using DevX API. 1144 * 1145 * @param[in] ctx 1146 * Context returned from mlx5 open_device() glue function. 1147 * @param [in] rq_attr 1148 * Pointer to create RQ attributes structure. 1149 * @param [in] socket 1150 * CPU socket ID for allocations. 1151 * 1152 * @return 1153 * The DevX object created, NULL otherwise and rte_errno is set. 1154 */ 1155 struct mlx5_devx_obj * 1156 mlx5_devx_cmd_create_rq(void *ctx, 1157 struct mlx5_devx_create_rq_attr *rq_attr, 1158 int socket) 1159 { 1160 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1161 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1162 void *rq_ctx, *wq_ctx; 1163 struct mlx5_devx_wq_attr *wq_attr; 1164 struct mlx5_devx_obj *rq = NULL; 1165 1166 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1167 if (!rq) { 1168 DRV_LOG(ERR, "Failed to allocate RQ data"); 1169 rte_errno = ENOMEM; 1170 return NULL; 1171 } 1172 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1173 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1174 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1175 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1176 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1177 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1178 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1179 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1180 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1181 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1182 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1183 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1184 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1185 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1186 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1187 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1188 wq_attr = &rq_attr->wq_attr; 1189 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1190 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1191 out, sizeof(out)); 1192 if (!rq->obj) { 1193 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1194 rte_errno = errno; 1195 mlx5_free(rq); 1196 return NULL; 1197 } 1198 rq->id = MLX5_GET(create_rq_out, out, rqn); 1199 return rq; 1200 } 1201 1202 /** 1203 * Modify RQ using DevX API. 1204 * 1205 * @param[in] rq 1206 * Pointer to RQ object structure. 1207 * @param [in] rq_attr 1208 * Pointer to modify RQ attributes structure. 1209 * 1210 * @return 1211 * 0 on success, a negative errno value otherwise and rte_errno is set. 1212 */ 1213 int 1214 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1215 struct mlx5_devx_modify_rq_attr *rq_attr) 1216 { 1217 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1218 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1219 void *rq_ctx, *wq_ctx; 1220 int ret; 1221 1222 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1223 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1224 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1225 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1226 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1227 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1228 if (rq_attr->modify_bitmask & 1229 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1230 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1231 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1232 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1233 if (rq_attr->modify_bitmask & 1234 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1235 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1236 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1237 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1238 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1239 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1240 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1241 } 1242 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1243 out, sizeof(out)); 1244 if (ret) { 1245 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1246 rte_errno = errno; 1247 return -errno; 1248 } 1249 return ret; 1250 } 1251 1252 /** 1253 * Create TIR using DevX API. 1254 * 1255 * @param[in] ctx 1256 * Context returned from mlx5 open_device() glue function. 1257 * @param [in] tir_attr 1258 * Pointer to TIR attributes structure. 1259 * 1260 * @return 1261 * The DevX object created, NULL otherwise and rte_errno is set. 1262 */ 1263 struct mlx5_devx_obj * 1264 mlx5_devx_cmd_create_tir(void *ctx, 1265 struct mlx5_devx_tir_attr *tir_attr) 1266 { 1267 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1268 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1269 void *tir_ctx, *outer, *inner, *rss_key; 1270 struct mlx5_devx_obj *tir = NULL; 1271 1272 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1273 if (!tir) { 1274 DRV_LOG(ERR, "Failed to allocate TIR data"); 1275 rte_errno = ENOMEM; 1276 return NULL; 1277 } 1278 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1279 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1280 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1281 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1282 tir_attr->lro_timeout_period_usecs); 1283 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1284 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1285 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1286 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1287 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1288 tir_attr->tunneled_offload_en); 1289 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1290 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1291 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1292 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1293 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1294 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1295 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1296 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1297 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1298 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1299 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1300 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1301 tir_attr->rx_hash_field_selector_outer.selected_fields); 1302 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1303 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1304 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1305 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1306 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1307 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1308 tir_attr->rx_hash_field_selector_inner.selected_fields); 1309 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1310 out, sizeof(out)); 1311 if (!tir->obj) { 1312 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1313 rte_errno = errno; 1314 mlx5_free(tir); 1315 return NULL; 1316 } 1317 tir->id = MLX5_GET(create_tir_out, out, tirn); 1318 return tir; 1319 } 1320 1321 /** 1322 * Modify TIR using DevX API. 1323 * 1324 * @param[in] tir 1325 * Pointer to TIR DevX object structure. 1326 * @param [in] modify_tir_attr 1327 * Pointer to TIR modification attributes structure. 1328 * 1329 * @return 1330 * 0 on success, a negative errno value otherwise and rte_errno is set. 1331 */ 1332 int 1333 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1334 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1335 { 1336 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1337 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1338 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1339 void *tir_ctx; 1340 int ret; 1341 1342 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1343 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1344 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1345 modify_tir_attr->modify_bitmask); 1346 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1347 if (modify_tir_attr->modify_bitmask & 1348 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1349 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1350 tir_attr->lro_timeout_period_usecs); 1351 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1352 tir_attr->lro_enable_mask); 1353 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1354 tir_attr->lro_max_msg_sz); 1355 } 1356 if (modify_tir_attr->modify_bitmask & 1357 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1358 MLX5_SET(tirc, tir_ctx, indirect_table, 1359 tir_attr->indirect_table); 1360 if (modify_tir_attr->modify_bitmask & 1361 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1362 int i; 1363 void *outer, *inner; 1364 1365 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1366 tir_attr->rx_hash_symmetric); 1367 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1368 for (i = 0; i < 10; i++) { 1369 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1370 tir_attr->rx_hash_toeplitz_key[i]); 1371 } 1372 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1373 rx_hash_field_selector_outer); 1374 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1375 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1376 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1377 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1378 MLX5_SET 1379 (rx_hash_field_select, outer, selected_fields, 1380 tir_attr->rx_hash_field_selector_outer.selected_fields); 1381 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1382 rx_hash_field_selector_inner); 1383 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1384 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1385 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1386 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1387 MLX5_SET 1388 (rx_hash_field_select, inner, selected_fields, 1389 tir_attr->rx_hash_field_selector_inner.selected_fields); 1390 } 1391 if (modify_tir_attr->modify_bitmask & 1392 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1393 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1394 } 1395 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1396 out, sizeof(out)); 1397 if (ret) { 1398 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1399 rte_errno = errno; 1400 return -errno; 1401 } 1402 return ret; 1403 } 1404 1405 /** 1406 * Create RQT using DevX API. 1407 * 1408 * @param[in] ctx 1409 * Context returned from mlx5 open_device() glue function. 1410 * @param [in] rqt_attr 1411 * Pointer to RQT attributes structure. 1412 * 1413 * @return 1414 * The DevX object created, NULL otherwise and rte_errno is set. 1415 */ 1416 struct mlx5_devx_obj * 1417 mlx5_devx_cmd_create_rqt(void *ctx, 1418 struct mlx5_devx_rqt_attr *rqt_attr) 1419 { 1420 uint32_t *in = NULL; 1421 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1422 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1423 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1424 void *rqt_ctx; 1425 struct mlx5_devx_obj *rqt = NULL; 1426 int i; 1427 1428 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1429 if (!in) { 1430 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1431 rte_errno = ENOMEM; 1432 return NULL; 1433 } 1434 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1435 if (!rqt) { 1436 DRV_LOG(ERR, "Failed to allocate RQT data"); 1437 rte_errno = ENOMEM; 1438 mlx5_free(in); 1439 return NULL; 1440 } 1441 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1442 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1443 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1444 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1445 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1446 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1447 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1448 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1449 mlx5_free(in); 1450 if (!rqt->obj) { 1451 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1452 rte_errno = errno; 1453 mlx5_free(rqt); 1454 return NULL; 1455 } 1456 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1457 return rqt; 1458 } 1459 1460 /** 1461 * Modify RQT using DevX API. 1462 * 1463 * @param[in] rqt 1464 * Pointer to RQT DevX object structure. 1465 * @param [in] rqt_attr 1466 * Pointer to RQT attributes structure. 1467 * 1468 * @return 1469 * 0 on success, a negative errno value otherwise and rte_errno is set. 1470 */ 1471 int 1472 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1473 struct mlx5_devx_rqt_attr *rqt_attr) 1474 { 1475 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1476 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1477 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1478 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1479 void *rqt_ctx; 1480 int i; 1481 int ret; 1482 1483 if (!in) { 1484 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1485 rte_errno = ENOMEM; 1486 return -ENOMEM; 1487 } 1488 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1489 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1490 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1491 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1492 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1493 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1494 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1495 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1496 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1497 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1498 mlx5_free(in); 1499 if (ret) { 1500 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1501 rte_errno = errno; 1502 return -rte_errno; 1503 } 1504 return ret; 1505 } 1506 1507 /** 1508 * Create SQ using DevX API. 1509 * 1510 * @param[in] ctx 1511 * Context returned from mlx5 open_device() glue function. 1512 * @param [in] sq_attr 1513 * Pointer to SQ attributes structure. 1514 * @param [in] socket 1515 * CPU socket ID for allocations. 1516 * 1517 * @return 1518 * The DevX object created, NULL otherwise and rte_errno is set. 1519 **/ 1520 struct mlx5_devx_obj * 1521 mlx5_devx_cmd_create_sq(void *ctx, 1522 struct mlx5_devx_create_sq_attr *sq_attr) 1523 { 1524 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1525 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1526 void *sq_ctx; 1527 void *wq_ctx; 1528 struct mlx5_devx_wq_attr *wq_attr; 1529 struct mlx5_devx_obj *sq = NULL; 1530 1531 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1532 if (!sq) { 1533 DRV_LOG(ERR, "Failed to allocate SQ data"); 1534 rte_errno = ENOMEM; 1535 return NULL; 1536 } 1537 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1538 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1539 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1540 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1541 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1542 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1543 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1544 sq_attr->allow_multi_pkt_send_wqe); 1545 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1546 sq_attr->min_wqe_inline_mode); 1547 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1548 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1549 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1550 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1551 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1552 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1553 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1554 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1555 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1556 sq_attr->packet_pacing_rate_limit_index); 1557 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1558 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1559 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1560 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1561 wq_attr = &sq_attr->wq_attr; 1562 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1563 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1564 out, sizeof(out)); 1565 if (!sq->obj) { 1566 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1567 rte_errno = errno; 1568 mlx5_free(sq); 1569 return NULL; 1570 } 1571 sq->id = MLX5_GET(create_sq_out, out, sqn); 1572 return sq; 1573 } 1574 1575 /** 1576 * Modify SQ using DevX API. 1577 * 1578 * @param[in] sq 1579 * Pointer to SQ object structure. 1580 * @param [in] sq_attr 1581 * Pointer to SQ attributes structure. 1582 * 1583 * @return 1584 * 0 on success, a negative errno value otherwise and rte_errno is set. 1585 */ 1586 int 1587 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1588 struct mlx5_devx_modify_sq_attr *sq_attr) 1589 { 1590 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1591 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1592 void *sq_ctx; 1593 int ret; 1594 1595 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1596 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1597 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1598 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1599 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1600 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1601 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1602 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1603 out, sizeof(out)); 1604 if (ret) { 1605 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1606 rte_errno = errno; 1607 return -rte_errno; 1608 } 1609 return ret; 1610 } 1611 1612 /** 1613 * Create TIS using DevX API. 1614 * 1615 * @param[in] ctx 1616 * Context returned from mlx5 open_device() glue function. 1617 * @param [in] tis_attr 1618 * Pointer to TIS attributes structure. 1619 * 1620 * @return 1621 * The DevX object created, NULL otherwise and rte_errno is set. 1622 */ 1623 struct mlx5_devx_obj * 1624 mlx5_devx_cmd_create_tis(void *ctx, 1625 struct mlx5_devx_tis_attr *tis_attr) 1626 { 1627 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1628 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1629 struct mlx5_devx_obj *tis = NULL; 1630 void *tis_ctx; 1631 1632 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1633 if (!tis) { 1634 DRV_LOG(ERR, "Failed to allocate TIS object"); 1635 rte_errno = ENOMEM; 1636 return NULL; 1637 } 1638 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1639 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1640 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1641 tis_attr->strict_lag_tx_port_affinity); 1642 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1643 tis_attr->lag_tx_port_affinity); 1644 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1645 MLX5_SET(tisc, tis_ctx, transport_domain, 1646 tis_attr->transport_domain); 1647 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1648 out, sizeof(out)); 1649 if (!tis->obj) { 1650 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1651 rte_errno = errno; 1652 mlx5_free(tis); 1653 return NULL; 1654 } 1655 tis->id = MLX5_GET(create_tis_out, out, tisn); 1656 return tis; 1657 } 1658 1659 /** 1660 * Create transport domain using DevX API. 1661 * 1662 * @param[in] ctx 1663 * Context returned from mlx5 open_device() glue function. 1664 * @return 1665 * The DevX object created, NULL otherwise and rte_errno is set. 1666 */ 1667 struct mlx5_devx_obj * 1668 mlx5_devx_cmd_create_td(void *ctx) 1669 { 1670 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1671 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1672 struct mlx5_devx_obj *td = NULL; 1673 1674 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1675 if (!td) { 1676 DRV_LOG(ERR, "Failed to allocate TD object"); 1677 rte_errno = ENOMEM; 1678 return NULL; 1679 } 1680 MLX5_SET(alloc_transport_domain_in, in, opcode, 1681 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1682 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1683 out, sizeof(out)); 1684 if (!td->obj) { 1685 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1686 rte_errno = errno; 1687 mlx5_free(td); 1688 return NULL; 1689 } 1690 td->id = MLX5_GET(alloc_transport_domain_out, out, 1691 transport_domain); 1692 return td; 1693 } 1694 1695 /** 1696 * Dump all flows to file. 1697 * 1698 * @param[in] fdb_domain 1699 * FDB domain. 1700 * @param[in] rx_domain 1701 * RX domain. 1702 * @param[in] tx_domain 1703 * TX domain. 1704 * @param[out] file 1705 * Pointer to file stream. 1706 * 1707 * @return 1708 * 0 on success, a nagative value otherwise. 1709 */ 1710 int 1711 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1712 void *rx_domain __rte_unused, 1713 void *tx_domain __rte_unused, FILE *file __rte_unused) 1714 { 1715 int ret = 0; 1716 1717 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1718 if (fdb_domain) { 1719 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1720 if (ret) 1721 return ret; 1722 } 1723 MLX5_ASSERT(rx_domain); 1724 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1725 if (ret) 1726 return ret; 1727 MLX5_ASSERT(tx_domain); 1728 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1729 #else 1730 ret = ENOTSUP; 1731 #endif 1732 return -ret; 1733 } 1734 1735 int 1736 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1737 FILE *file __rte_unused) 1738 { 1739 int ret = 0; 1740 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1741 if (rule_info) 1742 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1743 #else 1744 ret = ENOTSUP; 1745 #endif 1746 return -ret; 1747 } 1748 1749 /* 1750 * Create CQ using DevX API. 1751 * 1752 * @param[in] ctx 1753 * Context returned from mlx5 open_device() glue function. 1754 * @param [in] attr 1755 * Pointer to CQ attributes structure. 1756 * 1757 * @return 1758 * The DevX object created, NULL otherwise and rte_errno is set. 1759 */ 1760 struct mlx5_devx_obj * 1761 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1762 { 1763 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1764 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1765 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1766 sizeof(*cq_obj), 1767 0, SOCKET_ID_ANY); 1768 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1769 1770 if (!cq_obj) { 1771 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1772 rte_errno = ENOMEM; 1773 return NULL; 1774 } 1775 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1776 if (attr->db_umem_valid) { 1777 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1778 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1779 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1780 } else { 1781 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1782 } 1783 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1784 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1785 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1786 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1787 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1788 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1789 MLX5_SET(cqc, cqctx, log_page_size, 1790 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1791 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1792 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1793 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1794 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1795 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1796 attr->mini_cqe_res_format_ext); 1797 if (attr->q_umem_valid) { 1798 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1799 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1800 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1801 attr->q_umem_offset); 1802 } 1803 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1804 sizeof(out)); 1805 if (!cq_obj->obj) { 1806 rte_errno = errno; 1807 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1808 mlx5_free(cq_obj); 1809 return NULL; 1810 } 1811 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1812 return cq_obj; 1813 } 1814 1815 /** 1816 * Create VIRTQ using DevX API. 1817 * 1818 * @param[in] ctx 1819 * Context returned from mlx5 open_device() glue function. 1820 * @param [in] attr 1821 * Pointer to VIRTQ attributes structure. 1822 * 1823 * @return 1824 * The DevX object created, NULL otherwise and rte_errno is set. 1825 */ 1826 struct mlx5_devx_obj * 1827 mlx5_devx_cmd_create_virtq(void *ctx, 1828 struct mlx5_devx_virtq_attr *attr) 1829 { 1830 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1831 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1832 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1833 sizeof(*virtq_obj), 1834 0, SOCKET_ID_ANY); 1835 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1836 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1837 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1838 1839 if (!virtq_obj) { 1840 DRV_LOG(ERR, "Failed to allocate virtq data."); 1841 rte_errno = ENOMEM; 1842 return NULL; 1843 } 1844 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1845 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1846 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1847 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1848 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1849 attr->hw_available_index); 1850 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1851 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1852 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1853 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1854 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1855 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1856 attr->virtio_version_1_0); 1857 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1858 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1859 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1860 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1861 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1862 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1863 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1864 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1865 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1866 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1867 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1868 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1869 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1870 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1871 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1872 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1873 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1874 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1875 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1876 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1877 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1878 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1879 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1880 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1881 sizeof(out)); 1882 if (!virtq_obj->obj) { 1883 rte_errno = errno; 1884 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1885 mlx5_free(virtq_obj); 1886 return NULL; 1887 } 1888 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1889 return virtq_obj; 1890 } 1891 1892 /** 1893 * Modify VIRTQ using DevX API. 1894 * 1895 * @param[in] virtq_obj 1896 * Pointer to virtq object structure. 1897 * @param [in] attr 1898 * Pointer to modify virtq attributes structure. 1899 * 1900 * @return 1901 * 0 on success, a negative errno value otherwise and rte_errno is set. 1902 */ 1903 int 1904 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1905 struct mlx5_devx_virtq_attr *attr) 1906 { 1907 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1908 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1909 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1910 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1911 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1912 int ret; 1913 1914 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1915 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1916 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1917 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1918 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1919 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1920 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1921 switch (attr->type) { 1922 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1923 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1924 break; 1925 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1926 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1927 attr->dirty_bitmap_mkey); 1928 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1929 attr->dirty_bitmap_addr); 1930 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1931 attr->dirty_bitmap_size); 1932 break; 1933 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1934 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1935 attr->dirty_bitmap_dump_enable); 1936 break; 1937 default: 1938 rte_errno = EINVAL; 1939 return -rte_errno; 1940 } 1941 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1942 out, sizeof(out)); 1943 if (ret) { 1944 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1945 rte_errno = errno; 1946 return -rte_errno; 1947 } 1948 return ret; 1949 } 1950 1951 /** 1952 * Query VIRTQ using DevX API. 1953 * 1954 * @param[in] virtq_obj 1955 * Pointer to virtq object structure. 1956 * @param [in/out] attr 1957 * Pointer to virtq attributes structure. 1958 * 1959 * @return 1960 * 0 on success, a negative errno value otherwise and rte_errno is set. 1961 */ 1962 int 1963 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1964 struct mlx5_devx_virtq_attr *attr) 1965 { 1966 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1967 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1968 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1969 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1970 int ret; 1971 1972 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1973 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1974 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1975 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1976 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1977 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1978 out, sizeof(out)); 1979 if (ret) { 1980 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1981 rte_errno = errno; 1982 return -errno; 1983 } 1984 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1985 hw_available_index); 1986 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1987 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1988 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1989 virtio_q_context.error_type); 1990 return ret; 1991 } 1992 1993 /** 1994 * Create QP using DevX API. 1995 * 1996 * @param[in] ctx 1997 * Context returned from mlx5 open_device() glue function. 1998 * @param [in] attr 1999 * Pointer to QP attributes structure. 2000 * 2001 * @return 2002 * The DevX object created, NULL otherwise and rte_errno is set. 2003 */ 2004 struct mlx5_devx_obj * 2005 mlx5_devx_cmd_create_qp(void *ctx, 2006 struct mlx5_devx_qp_attr *attr) 2007 { 2008 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2009 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2010 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2011 sizeof(*qp_obj), 2012 0, SOCKET_ID_ANY); 2013 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2014 2015 if (!qp_obj) { 2016 DRV_LOG(ERR, "Failed to allocate QP data."); 2017 rte_errno = ENOMEM; 2018 return NULL; 2019 } 2020 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2021 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2022 MLX5_SET(qpc, qpc, pd, attr->pd); 2023 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2024 if (attr->uar_index) { 2025 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2026 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2027 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2028 MLX5_SET(qpc, qpc, log_page_size, 2029 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2030 if (attr->sq_size) { 2031 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 2032 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2033 MLX5_SET(qpc, qpc, log_sq_size, 2034 rte_log2_u32(attr->sq_size)); 2035 } else { 2036 MLX5_SET(qpc, qpc, no_sq, 1); 2037 } 2038 if (attr->rq_size) { 2039 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 2040 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2041 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2042 MLX5_LOG_RQ_STRIDE_SHIFT); 2043 MLX5_SET(qpc, qpc, log_rq_size, 2044 rte_log2_u32(attr->rq_size)); 2045 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2046 } else { 2047 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2048 } 2049 if (attr->dbr_umem_valid) { 2050 MLX5_SET(qpc, qpc, dbr_umem_valid, 2051 attr->dbr_umem_valid); 2052 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2053 } 2054 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2055 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2056 attr->wq_umem_offset); 2057 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2058 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2059 } else { 2060 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2061 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2062 MLX5_SET(qpc, qpc, no_sq, 1); 2063 } 2064 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2065 sizeof(out)); 2066 if (!qp_obj->obj) { 2067 rte_errno = errno; 2068 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 2069 mlx5_free(qp_obj); 2070 return NULL; 2071 } 2072 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2073 return qp_obj; 2074 } 2075 2076 /** 2077 * Modify QP using DevX API. 2078 * Currently supports only force loop-back QP. 2079 * 2080 * @param[in] qp 2081 * Pointer to QP object structure. 2082 * @param [in] qp_st_mod_op 2083 * The QP state modification operation. 2084 * @param [in] remote_qp_id 2085 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2086 * 2087 * @return 2088 * 0 on success, a negative errno value otherwise and rte_errno is set. 2089 */ 2090 int 2091 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2092 uint32_t remote_qp_id) 2093 { 2094 union { 2095 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2096 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2097 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2098 } in; 2099 union { 2100 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2101 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2102 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2103 } out; 2104 void *qpc; 2105 int ret; 2106 unsigned int inlen; 2107 unsigned int outlen; 2108 2109 memset(&in, 0, sizeof(in)); 2110 memset(&out, 0, sizeof(out)); 2111 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2112 switch (qp_st_mod_op) { 2113 case MLX5_CMD_OP_RST2INIT_QP: 2114 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2115 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2116 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2117 MLX5_SET(qpc, qpc, rre, 1); 2118 MLX5_SET(qpc, qpc, rwe, 1); 2119 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2120 inlen = sizeof(in.rst2init); 2121 outlen = sizeof(out.rst2init); 2122 break; 2123 case MLX5_CMD_OP_INIT2RTR_QP: 2124 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2125 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2126 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2127 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2128 MLX5_SET(qpc, qpc, mtu, 1); 2129 MLX5_SET(qpc, qpc, log_msg_max, 30); 2130 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2131 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2132 inlen = sizeof(in.init2rtr); 2133 outlen = sizeof(out.init2rtr); 2134 break; 2135 case MLX5_CMD_OP_RTR2RTS_QP: 2136 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2137 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2138 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 2139 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2140 MLX5_SET(qpc, qpc, retry_count, 7); 2141 MLX5_SET(qpc, qpc, rnr_retry, 7); 2142 inlen = sizeof(in.rtr2rts); 2143 outlen = sizeof(out.rtr2rts); 2144 break; 2145 default: 2146 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2147 qp_st_mod_op); 2148 rte_errno = EINVAL; 2149 return -rte_errno; 2150 } 2151 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2152 if (ret) { 2153 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2154 rte_errno = errno; 2155 return -rte_errno; 2156 } 2157 return ret; 2158 } 2159 2160 struct mlx5_devx_obj * 2161 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2162 { 2163 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2164 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2165 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2166 sizeof(*couners_obj), 0, 2167 SOCKET_ID_ANY); 2168 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2169 2170 if (!couners_obj) { 2171 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2172 rte_errno = ENOMEM; 2173 return NULL; 2174 } 2175 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2176 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2177 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2178 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2179 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2180 sizeof(out)); 2181 if (!couners_obj->obj) { 2182 rte_errno = errno; 2183 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2184 " DevX."); 2185 mlx5_free(couners_obj); 2186 return NULL; 2187 } 2188 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2189 return couners_obj; 2190 } 2191 2192 int 2193 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2194 struct mlx5_devx_virtio_q_couners_attr *attr) 2195 { 2196 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2197 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2198 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2199 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2200 virtio_q_counters); 2201 int ret; 2202 2203 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2204 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2205 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2206 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2207 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2208 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2209 sizeof(out)); 2210 if (ret) { 2211 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2212 rte_errno = errno; 2213 return -errno; 2214 } 2215 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2216 received_desc); 2217 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2218 completed_desc); 2219 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2220 error_cqes); 2221 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2222 bad_desc_errors); 2223 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2224 exceed_max_chain); 2225 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2226 invalid_buffer); 2227 return ret; 2228 } 2229 2230 /** 2231 * Create general object of type FLOW_HIT_ASO using DevX API. 2232 * 2233 * @param[in] ctx 2234 * Context returned from mlx5 open_device() glue function. 2235 * @param [in] pd 2236 * PD value to associate the FLOW_HIT_ASO object with. 2237 * 2238 * @return 2239 * The DevX object created, NULL otherwise and rte_errno is set. 2240 */ 2241 struct mlx5_devx_obj * 2242 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2243 { 2244 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2245 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2246 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2247 void *ptr = NULL; 2248 2249 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2250 0, SOCKET_ID_ANY); 2251 if (!flow_hit_aso_obj) { 2252 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2253 rte_errno = ENOMEM; 2254 return NULL; 2255 } 2256 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2257 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2258 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2259 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2260 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2261 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2262 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2263 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2264 out, sizeof(out)); 2265 if (!flow_hit_aso_obj->obj) { 2266 rte_errno = errno; 2267 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2268 mlx5_free(flow_hit_aso_obj); 2269 return NULL; 2270 } 2271 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2272 return flow_hit_aso_obj; 2273 } 2274 2275 /* 2276 * Create PD using DevX API. 2277 * 2278 * @param[in] ctx 2279 * Context returned from mlx5 open_device() glue function. 2280 * 2281 * @return 2282 * The DevX object created, NULL otherwise and rte_errno is set. 2283 */ 2284 struct mlx5_devx_obj * 2285 mlx5_devx_cmd_alloc_pd(void *ctx) 2286 { 2287 struct mlx5_devx_obj *ppd = 2288 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2289 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2290 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2291 2292 if (!ppd) { 2293 DRV_LOG(ERR, "Failed to allocate PD data."); 2294 rte_errno = ENOMEM; 2295 return NULL; 2296 } 2297 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2298 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2299 out, sizeof(out)); 2300 if (!ppd->obj) { 2301 mlx5_free(ppd); 2302 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2303 rte_errno = errno; 2304 return NULL; 2305 } 2306 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2307 return ppd; 2308 } 2309 2310 /** 2311 * Create general object of type FLOW_METER_ASO using DevX API. 2312 * 2313 * @param[in] ctx 2314 * Context returned from mlx5 open_device() glue function. 2315 * @param [in] pd 2316 * PD value to associate the FLOW_METER_ASO object with. 2317 * @param [in] log_obj_size 2318 * log_obj_size define to allocate number of 2 * meters 2319 * in one FLOW_METER_ASO object. 2320 * 2321 * @return 2322 * The DevX object created, NULL otherwise and rte_errno is set. 2323 */ 2324 struct mlx5_devx_obj * 2325 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2326 uint32_t log_obj_size) 2327 { 2328 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2329 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2330 struct mlx5_devx_obj *flow_meter_aso_obj; 2331 void *ptr; 2332 2333 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2334 sizeof(*flow_meter_aso_obj), 2335 0, SOCKET_ID_ANY); 2336 if (!flow_meter_aso_obj) { 2337 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2338 rte_errno = ENOMEM; 2339 return NULL; 2340 } 2341 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2342 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2343 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2344 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2345 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2346 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2347 log_obj_size); 2348 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2349 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2350 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2351 ctx, in, sizeof(in), 2352 out, sizeof(out)); 2353 if (!flow_meter_aso_obj->obj) { 2354 rte_errno = errno; 2355 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2356 mlx5_free(flow_meter_aso_obj); 2357 return NULL; 2358 } 2359 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2360 out, obj_id); 2361 return flow_meter_aso_obj; 2362 } 2363 2364 /* 2365 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2366 * 2367 * @param[in] ctx 2368 * Context returned from mlx5 open_device() glue function. 2369 * @param [in] pd 2370 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2371 * @param [in] log_obj_size 2372 * log_obj_size to allocate its power of 2 * objects 2373 * in one CONN_TRACK_OFFLOAD bulk allocation. 2374 * 2375 * @return 2376 * The DevX object created, NULL otherwise and rte_errno is set. 2377 */ 2378 struct mlx5_devx_obj * 2379 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2380 uint32_t log_obj_size) 2381 { 2382 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2383 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2384 struct mlx5_devx_obj *ct_aso_obj; 2385 void *ptr; 2386 2387 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2388 0, SOCKET_ID_ANY); 2389 if (!ct_aso_obj) { 2390 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2391 rte_errno = ENOMEM; 2392 return NULL; 2393 } 2394 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2395 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2396 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2397 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2398 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2399 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2400 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2401 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2402 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2403 out, sizeof(out)); 2404 if (!ct_aso_obj->obj) { 2405 rte_errno = errno; 2406 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX."); 2407 mlx5_free(ct_aso_obj); 2408 return NULL; 2409 } 2410 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2411 return ct_aso_obj; 2412 } 2413 2414 /** 2415 * Create general object of type GENEVE TLV option using DevX API. 2416 * 2417 * @param[in] ctx 2418 * Context returned from mlx5 open_device() glue function. 2419 * @param [in] class 2420 * TLV option variable value of class 2421 * @param [in] type 2422 * TLV option variable value of type 2423 * @param [in] len 2424 * TLV option variable value of len 2425 * 2426 * @return 2427 * The DevX object created, NULL otherwise and rte_errno is set. 2428 */ 2429 struct mlx5_devx_obj * 2430 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2431 uint16_t class, uint8_t type, uint8_t len) 2432 { 2433 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2434 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2435 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2436 sizeof(*geneve_tlv_opt_obj), 2437 0, SOCKET_ID_ANY); 2438 2439 if (!geneve_tlv_opt_obj) { 2440 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2441 rte_errno = ENOMEM; 2442 return NULL; 2443 } 2444 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2445 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2446 geneve_tlv_opt); 2447 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2448 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2449 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2450 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2451 MLX5_SET(geneve_tlv_option, opt, option_class, 2452 rte_be_to_cpu_16(class)); 2453 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2454 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2455 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2456 sizeof(in), out, sizeof(out)); 2457 if (!geneve_tlv_opt_obj->obj) { 2458 rte_errno = errno; 2459 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2460 "Obj using DevX."); 2461 mlx5_free(geneve_tlv_opt_obj); 2462 return NULL; 2463 } 2464 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2465 return geneve_tlv_opt_obj; 2466 } 2467 2468 int 2469 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2470 { 2471 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2472 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2473 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2474 int rc; 2475 void *rq_ctx; 2476 2477 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2478 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2479 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2480 if (rc) { 2481 rte_errno = errno; 2482 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2483 "rc = %d, errno = %d.", rc, errno); 2484 return -rc; 2485 }; 2486 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2487 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2488 return 0; 2489 #else 2490 (void)wq; 2491 (void)counter_set_id; 2492 return -ENOTSUP; 2493 #endif 2494 } 2495 2496 /* 2497 * Allocate queue counters via devx interface. 2498 * 2499 * @param[in] ctx 2500 * Context returned from mlx5 open_device() glue function. 2501 * 2502 * @return 2503 * Pointer to counter object on success, a NULL value otherwise and 2504 * rte_errno is set. 2505 */ 2506 struct mlx5_devx_obj * 2507 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2508 { 2509 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2510 SOCKET_ID_ANY); 2511 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2512 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2513 2514 if (!dcs) { 2515 rte_errno = ENOMEM; 2516 return NULL; 2517 } 2518 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2519 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2520 sizeof(out)); 2521 if (!dcs->obj) { 2522 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2523 "%d.", errno); 2524 rte_errno = errno; 2525 mlx5_free(dcs); 2526 return NULL; 2527 } 2528 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2529 return dcs; 2530 } 2531 2532 /** 2533 * Query queue counters values. 2534 * 2535 * @param[in] dcs 2536 * devx object of the queue counter set. 2537 * @param[in] clear 2538 * Whether hardware should clear the counters after the query or not. 2539 * @param[out] out_of_buffers 2540 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2541 * 2542 * @return 2543 * 0 on success, a negative value otherwise. 2544 */ 2545 int 2546 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2547 uint32_t *out_of_buffers) 2548 { 2549 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2550 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2551 int rc; 2552 2553 MLX5_SET(query_q_counter_in, in, opcode, 2554 MLX5_CMD_OP_QUERY_Q_COUNTER); 2555 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2556 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2557 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2558 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2559 sizeof(out)); 2560 if (rc) { 2561 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2562 rte_errno = rc; 2563 return -rc; 2564 } 2565 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2566 return 0; 2567 } 2568 2569 /** 2570 * Create general object of type DEK using DevX API. 2571 * 2572 * @param[in] ctx 2573 * Context returned from mlx5 open_device() glue function. 2574 * @param [in] attr 2575 * Pointer to DEK attributes structure. 2576 * 2577 * @return 2578 * The DevX object created, NULL otherwise and rte_errno is set. 2579 */ 2580 struct mlx5_devx_obj * 2581 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2582 { 2583 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2584 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2585 struct mlx5_devx_obj *dek_obj = NULL; 2586 void *ptr = NULL, *key_addr = NULL; 2587 2588 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2589 0, SOCKET_ID_ANY); 2590 if (dek_obj == NULL) { 2591 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2592 rte_errno = ENOMEM; 2593 return NULL; 2594 } 2595 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2596 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2597 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2598 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2599 MLX5_GENERAL_OBJ_TYPE_DEK); 2600 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2601 MLX5_SET(dek, ptr, key_size, attr->key_size); 2602 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2603 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2604 MLX5_SET(dek, ptr, pd, attr->pd); 2605 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2606 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2607 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2608 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2609 out, sizeof(out)); 2610 if (dek_obj->obj == NULL) { 2611 rte_errno = errno; 2612 DRV_LOG(ERR, "Failed to create DEK obj using DevX."); 2613 mlx5_free(dek_obj); 2614 return NULL; 2615 } 2616 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2617 return dek_obj; 2618 } 2619 2620 /** 2621 * Create general object of type IMPORT_KEK using DevX API. 2622 * 2623 * @param[in] ctx 2624 * Context returned from mlx5 open_device() glue function. 2625 * @param [in] attr 2626 * Pointer to IMPORT_KEK attributes structure. 2627 * 2628 * @return 2629 * The DevX object created, NULL otherwise and rte_errno is set. 2630 */ 2631 struct mlx5_devx_obj * 2632 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2633 struct mlx5_devx_import_kek_attr *attr) 2634 { 2635 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2636 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2637 struct mlx5_devx_obj *import_kek_obj = NULL; 2638 void *ptr = NULL, *key_addr = NULL; 2639 2640 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2641 0, SOCKET_ID_ANY); 2642 if (import_kek_obj == NULL) { 2643 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2644 rte_errno = ENOMEM; 2645 return NULL; 2646 } 2647 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2648 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2649 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2650 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2651 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2652 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2653 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2654 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2655 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2656 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2657 out, sizeof(out)); 2658 if (import_kek_obj->obj == NULL) { 2659 rte_errno = errno; 2660 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); 2661 mlx5_free(import_kek_obj); 2662 return NULL; 2663 } 2664 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2665 return import_kek_obj; 2666 } 2667 2668 /** 2669 * Create general object of type CREDENTIAL using DevX API. 2670 * 2671 * @param[in] ctx 2672 * Context returned from mlx5 open_device() glue function. 2673 * @param [in] attr 2674 * Pointer to CREDENTIAL attributes structure. 2675 * 2676 * @return 2677 * The DevX object created, NULL otherwise and rte_errno is set. 2678 */ 2679 struct mlx5_devx_obj * 2680 mlx5_devx_cmd_create_credential_obj(void *ctx, 2681 struct mlx5_devx_credential_attr *attr) 2682 { 2683 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2684 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2685 struct mlx5_devx_obj *credential_obj = NULL; 2686 void *ptr = NULL, *credential_addr = NULL; 2687 2688 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2689 0, SOCKET_ID_ANY); 2690 if (credential_obj == NULL) { 2691 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2692 rte_errno = ENOMEM; 2693 return NULL; 2694 } 2695 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2696 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2697 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2698 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2699 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2700 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2701 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2702 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2703 memcpy(credential_addr, (void *)(attr->credential), 2704 MLX5_CRYPTO_CREDENTIAL_SIZE); 2705 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2706 out, sizeof(out)); 2707 if (credential_obj->obj == NULL) { 2708 rte_errno = errno; 2709 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); 2710 mlx5_free(credential_obj); 2711 return NULL; 2712 } 2713 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2714 return credential_obj; 2715 } 2716 2717 /** 2718 * Create general object of type CRYPTO_LOGIN using DevX API. 2719 * 2720 * @param[in] ctx 2721 * Context returned from mlx5 open_device() glue function. 2722 * @param [in] attr 2723 * Pointer to CRYPTO_LOGIN attributes structure. 2724 * 2725 * @return 2726 * The DevX object created, NULL otherwise and rte_errno is set. 2727 */ 2728 struct mlx5_devx_obj * 2729 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2730 struct mlx5_devx_crypto_login_attr *attr) 2731 { 2732 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2733 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2734 struct mlx5_devx_obj *crypto_login_obj = NULL; 2735 void *ptr = NULL, *credential_addr = NULL; 2736 2737 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2738 0, SOCKET_ID_ANY); 2739 if (crypto_login_obj == NULL) { 2740 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2741 rte_errno = ENOMEM; 2742 return NULL; 2743 } 2744 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2745 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2746 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2747 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2748 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2749 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2750 MLX5_SET(crypto_login, ptr, credential_pointer, 2751 attr->credential_pointer); 2752 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2753 attr->session_import_kek_ptr); 2754 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2755 memcpy(credential_addr, (void *)(attr->credential), 2756 MLX5_CRYPTO_CREDENTIAL_SIZE); 2757 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2758 out, sizeof(out)); 2759 if (crypto_login_obj->obj == NULL) { 2760 rte_errno = errno; 2761 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); 2762 mlx5_free(crypto_login_obj); 2763 return NULL; 2764 } 2765 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2766 return crypto_login_obj; 2767 } 2768