1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright 2018 Mellanox Technologies, Ltd */ 3 4 #include <unistd.h> 5 6 #include <rte_errno.h> 7 #include <rte_malloc.h> 8 #include <rte_eal_paging.h> 9 10 #include "mlx5_prm.h" 11 #include "mlx5_devx_cmds.h" 12 #include "mlx5_common_utils.h" 13 #include "mlx5_malloc.h" 14 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_DW(access_register_out) * 57 sizeof(uint32_t) + dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Allocate flow counters via devx interface. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param dcs 83 * Pointer to counters properties structure to be filled by the routine. 84 * @param bulk_n_128 85 * Bulk counter numbers in 128 counters units. 86 * 87 * @return 88 * Pointer to counter object on success, a negative value otherwise and 89 * rte_errno is set. 90 */ 91 struct mlx5_devx_obj * 92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 93 { 94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 95 0, SOCKET_ID_ANY); 96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 98 99 if (!dcs) { 100 rte_errno = ENOMEM; 101 return NULL; 102 } 103 MLX5_SET(alloc_flow_counter_in, in, opcode, 104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 107 sizeof(in), out, sizeof(out)); 108 if (!dcs->obj) { 109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 110 rte_errno = errno; 111 mlx5_free(dcs); 112 return NULL; 113 } 114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 115 return dcs; 116 } 117 118 /** 119 * Query flow counters values. 120 * 121 * @param[in] dcs 122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 123 * @param[in] clear 124 * Whether hardware should clear the counters after the query or not. 125 * @param[in] n_counters 126 * 0 in case of 1 counter to read, otherwise the counter number to read. 127 * @param pkts 128 * The number of packets that matched the flow. 129 * @param bytes 130 * The number of bytes that matched the flow. 131 * @param mkey 132 * The mkey key for batch query. 133 * @param addr 134 * The address in the mkey range for batch query. 135 * @param cmd_comp 136 * The completion object for asynchronous batch query. 137 * @param async_id 138 * The ID to be returned in the asynchronous batch query response. 139 * 140 * @return 141 * 0 on success, a negative value otherwise. 142 */ 143 int 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 145 int clear, uint32_t n_counters, 146 uint64_t *pkts, uint64_t *bytes, 147 uint32_t mkey, void *addr, 148 void *cmd_comp, 149 uint64_t async_id) 150 { 151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 152 MLX5_ST_SZ_BYTES(traffic_counter); 153 uint32_t out[out_len]; 154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 155 void *stats; 156 int rc; 157 158 MLX5_SET(query_flow_counter_in, in, opcode, 159 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 160 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 162 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 163 164 if (n_counters) { 165 MLX5_SET(query_flow_counter_in, in, num_of_counters, 166 n_counters); 167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 168 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 169 MLX5_SET64(query_flow_counter_in, in, address, 170 (uint64_t)(uintptr_t)addr); 171 } 172 if (!cmd_comp) 173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 174 out_len); 175 else 176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 177 out_len, async_id, 178 cmd_comp); 179 if (rc) { 180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 181 rte_errno = rc; 182 return -rc; 183 } 184 if (!n_counters) { 185 stats = MLX5_ADDR_OF(query_flow_counter_out, 186 out, flow_statistics); 187 *pkts = MLX5_GET64(traffic_counter, stats, packets); 188 *bytes = MLX5_GET64(traffic_counter, stats, octets); 189 } 190 return 0; 191 } 192 193 /** 194 * Create a new mkey. 195 * 196 * @param[in] ctx 197 * Context returned from mlx5 open_device() glue function. 198 * @param[in] attr 199 * Attributes of the requested mkey. 200 * 201 * @return 202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 203 * is set. 204 */ 205 struct mlx5_devx_obj * 206 mlx5_devx_cmd_mkey_create(void *ctx, 207 struct mlx5_devx_mkey_attr *attr) 208 { 209 struct mlx5_klm *klm_array = attr->klm_array; 210 int klm_num = attr->klm_num; 211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 213 uint32_t in[in_size_dw]; 214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 215 void *mkc; 216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 217 0, SOCKET_ID_ANY); 218 size_t pgsize; 219 uint32_t translation_size; 220 221 if (!mkey) { 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 memset(in, 0, in_size_dw * 4); 226 pgsize = rte_mem_page_size(); 227 if (pgsize == (size_t)-1) { 228 mlx5_free(mkey); 229 DRV_LOG(ERR, "Failed to get page size"); 230 rte_errno = ENOMEM; 231 return NULL; 232 } 233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 235 if (klm_num > 0) { 236 int i; 237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 238 klm_pas_mtt); 239 translation_size = RTE_ALIGN(klm_num, 4); 240 for (i = 0; i < klm_num; i++) { 241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 243 MLX5_SET64(klm, klm, address, klm_array[i].address); 244 klm += MLX5_ST_SZ_BYTES(klm); 245 } 246 for (; i < (int)translation_size; i++) { 247 MLX5_SET(klm, klm, mkey, 0x0); 248 MLX5_SET64(klm, klm, address, 0x0); 249 klm += MLX5_ST_SZ_BYTES(klm); 250 } 251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 252 MLX5_MKC_ACCESS_MODE_KLM_FBS : 253 MLX5_MKC_ACCESS_MODE_KLM); 254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 255 } else { 256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 259 } 260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 261 translation_size); 262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 264 MLX5_SET(mkc, mkc, lw, 0x1); 265 MLX5_SET(mkc, mkc, lr, 0x1); 266 MLX5_SET(mkc, mkc, qpn, 0xffffff); 267 MLX5_SET(mkc, mkc, pd, attr->pd); 268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 269 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 270 if (attr->relaxed_ordering == 1) { 271 MLX5_SET(mkc, mkc, relaxed_ordering_write, 0x1); 272 MLX5_SET(mkc, mkc, relaxed_ordering_read, 0x1); 273 } 274 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 275 MLX5_SET64(mkc, mkc, len, attr->size); 276 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 277 sizeof(out)); 278 if (!mkey->obj) { 279 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n", 280 klm_num ? "an in" : "a ", errno); 281 rte_errno = errno; 282 mlx5_free(mkey); 283 return NULL; 284 } 285 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 286 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 287 return mkey; 288 } 289 290 /** 291 * Get status of devx command response. 292 * Mainly used for asynchronous commands. 293 * 294 * @param[in] out 295 * The out response buffer. 296 * 297 * @return 298 * 0 on success, non-zero value otherwise. 299 */ 300 int 301 mlx5_devx_get_out_command_status(void *out) 302 { 303 int status; 304 305 if (!out) 306 return -EINVAL; 307 status = MLX5_GET(query_flow_counter_out, out, status); 308 if (status) { 309 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 310 311 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status, 312 syndrome); 313 } 314 return status; 315 } 316 317 /** 318 * Destroy any object allocated by a Devx API. 319 * 320 * @param[in] obj 321 * Pointer to a general object. 322 * 323 * @return 324 * 0 on success, a negative value otherwise. 325 */ 326 int 327 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 328 { 329 int ret; 330 331 if (!obj) 332 return 0; 333 ret = mlx5_glue->devx_obj_destroy(obj->obj); 334 mlx5_free(obj); 335 return ret; 336 } 337 338 /** 339 * Query NIC vport context. 340 * Fills minimal inline attribute. 341 * 342 * @param[in] ctx 343 * ibv contexts returned from mlx5dv_open_device. 344 * @param[in] vport 345 * vport index 346 * @param[out] attr 347 * Attributes device values. 348 * 349 * @return 350 * 0 on success, a negative value otherwise. 351 */ 352 static int 353 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 354 unsigned int vport, 355 struct mlx5_hca_attr *attr) 356 { 357 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 358 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 359 void *vctx; 360 int status, syndrome, rc; 361 362 /* Query NIC vport context to determine inline mode. */ 363 MLX5_SET(query_nic_vport_context_in, in, opcode, 364 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 365 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 366 if (vport) 367 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 368 rc = mlx5_glue->devx_general_cmd(ctx, 369 in, sizeof(in), 370 out, sizeof(out)); 371 if (rc) 372 goto error; 373 status = MLX5_GET(query_nic_vport_context_out, out, status); 374 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 375 if (status) { 376 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 377 "status %x, syndrome = %x", 378 status, syndrome); 379 return -1; 380 } 381 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 382 nic_vport_context); 383 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 384 min_wqe_inline_mode); 385 return 0; 386 error: 387 rc = (rc > 0) ? -rc : rc; 388 return rc; 389 } 390 391 /** 392 * Query NIC vDPA attributes. 393 * 394 * @param[in] ctx 395 * Context returned from mlx5 open_device() glue function. 396 * @param[out] vdpa_attr 397 * vDPA Attributes structure to fill. 398 */ 399 static void 400 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 401 struct mlx5_hca_vdpa_attr *vdpa_attr) 402 { 403 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 404 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 405 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 406 int status, syndrome, rc; 407 408 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 409 MLX5_SET(query_hca_cap_in, in, op_mod, 410 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 411 MLX5_HCA_CAP_OPMOD_GET_CUR); 412 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 413 status = MLX5_GET(query_hca_cap_out, out, status); 414 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 415 if (rc || status) { 416 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 417 " status %x, syndrome = %x", status, syndrome); 418 vdpa_attr->valid = 0; 419 } else { 420 vdpa_attr->valid = 1; 421 vdpa_attr->desc_tunnel_offload_type = 422 MLX5_GET(virtio_emulation_cap, hcattr, 423 desc_tunnel_offload_type); 424 vdpa_attr->eth_frame_offload_type = 425 MLX5_GET(virtio_emulation_cap, hcattr, 426 eth_frame_offload_type); 427 vdpa_attr->virtio_version_1_0 = 428 MLX5_GET(virtio_emulation_cap, hcattr, 429 virtio_version_1_0); 430 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 431 tso_ipv4); 432 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 433 tso_ipv6); 434 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 435 tx_csum); 436 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 437 rx_csum); 438 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 439 event_mode); 440 vdpa_attr->virtio_queue_type = 441 MLX5_GET(virtio_emulation_cap, hcattr, 442 virtio_queue_type); 443 vdpa_attr->log_doorbell_stride = 444 MLX5_GET(virtio_emulation_cap, hcattr, 445 log_doorbell_stride); 446 vdpa_attr->log_doorbell_bar_size = 447 MLX5_GET(virtio_emulation_cap, hcattr, 448 log_doorbell_bar_size); 449 vdpa_attr->doorbell_bar_offset = 450 MLX5_GET64(virtio_emulation_cap, hcattr, 451 doorbell_bar_offset); 452 vdpa_attr->max_num_virtio_queues = 453 MLX5_GET(virtio_emulation_cap, hcattr, 454 max_num_virtio_queues); 455 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 456 umem_1_buffer_param_a); 457 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 458 umem_1_buffer_param_b); 459 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 460 umem_2_buffer_param_a); 461 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 462 umem_2_buffer_param_b); 463 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 464 umem_3_buffer_param_a); 465 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 466 umem_3_buffer_param_b); 467 } 468 } 469 470 int 471 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 472 uint32_t ids[], uint32_t num) 473 { 474 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 475 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 476 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 477 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 478 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 479 int ret; 480 uint32_t idx = 0; 481 uint32_t i; 482 483 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 484 rte_errno = EINVAL; 485 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 486 return -rte_errno; 487 } 488 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 489 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 490 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 491 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 492 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 493 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 494 out, sizeof(out)); 495 if (ret) { 496 rte_errno = ret; 497 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 498 (void *)flex_obj); 499 return -rte_errno; 500 } 501 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 502 void *s_off = (void *)((char *)sample + i * 503 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 504 uint32_t en; 505 506 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 507 flow_match_sample_en); 508 if (!en) 509 continue; 510 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 511 flow_match_sample_field_id); 512 } 513 if (num != idx) { 514 rte_errno = EINVAL; 515 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 516 return -rte_errno; 517 } 518 return ret; 519 } 520 521 522 struct mlx5_devx_obj * 523 mlx5_devx_cmd_create_flex_parser(void *ctx, 524 struct mlx5_devx_graph_node_attr *data) 525 { 526 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 527 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 528 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 529 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 530 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 531 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 532 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 533 struct mlx5_devx_obj *parse_flex_obj = NULL; 534 uint32_t i; 535 536 parse_flex_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, 537 SOCKET_ID_ANY); 538 if (!parse_flex_obj) { 539 DRV_LOG(ERR, "Failed to allocate flex parser data"); 540 rte_errno = ENOMEM; 541 mlx5_free(in); 542 return NULL; 543 } 544 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 545 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 546 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 547 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 548 MLX5_SET(parse_graph_flex, flex, header_length_mode, 549 data->header_length_mode); 550 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 551 data->header_length_base_value); 552 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 553 data->header_length_field_offset); 554 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 555 data->header_length_field_shift); 556 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 557 data->header_length_field_mask); 558 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 559 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 560 void *s_off = (void *)((char *)sample + i * 561 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 562 563 if (!s->flow_match_sample_en) 564 continue; 565 MLX5_SET(parse_graph_flow_match_sample, s_off, 566 flow_match_sample_en, !!s->flow_match_sample_en); 567 MLX5_SET(parse_graph_flow_match_sample, s_off, 568 flow_match_sample_field_offset, 569 s->flow_match_sample_field_offset); 570 MLX5_SET(parse_graph_flow_match_sample, s_off, 571 flow_match_sample_offset_mode, 572 s->flow_match_sample_offset_mode); 573 MLX5_SET(parse_graph_flow_match_sample, s_off, 574 flow_match_sample_field_offset_mask, 575 s->flow_match_sample_field_offset_mask); 576 MLX5_SET(parse_graph_flow_match_sample, s_off, 577 flow_match_sample_field_offset_shift, 578 s->flow_match_sample_field_offset_shift); 579 MLX5_SET(parse_graph_flow_match_sample, s_off, 580 flow_match_sample_field_base_offset, 581 s->flow_match_sample_field_base_offset); 582 MLX5_SET(parse_graph_flow_match_sample, s_off, 583 flow_match_sample_tunnel_mode, 584 s->flow_match_sample_tunnel_mode); 585 } 586 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 587 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 588 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 589 void *in_off = (void *)((char *)in_arc + i * 590 MLX5_ST_SZ_BYTES(parse_graph_arc)); 591 void *out_off = (void *)((char *)out_arc + i * 592 MLX5_ST_SZ_BYTES(parse_graph_arc)); 593 594 if (ia->arc_parse_graph_node != 0) { 595 MLX5_SET(parse_graph_arc, in_off, 596 compare_condition_value, 597 ia->compare_condition_value); 598 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 599 ia->start_inner_tunnel); 600 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 601 ia->arc_parse_graph_node); 602 MLX5_SET(parse_graph_arc, in_off, 603 parse_graph_node_handle, 604 ia->parse_graph_node_handle); 605 } 606 if (oa->arc_parse_graph_node != 0) { 607 MLX5_SET(parse_graph_arc, out_off, 608 compare_condition_value, 609 oa->compare_condition_value); 610 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 611 oa->start_inner_tunnel); 612 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 613 oa->arc_parse_graph_node); 614 MLX5_SET(parse_graph_arc, out_off, 615 parse_graph_node_handle, 616 oa->parse_graph_node_handle); 617 } 618 } 619 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 620 out, sizeof(out)); 621 if (!parse_flex_obj->obj) { 622 rte_errno = errno; 623 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 624 "by using DevX."); 625 mlx5_free(parse_flex_obj); 626 return NULL; 627 } 628 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 629 return parse_flex_obj; 630 } 631 632 /** 633 * Query HCA attributes. 634 * Using those attributes we can check on run time if the device 635 * is having the required capabilities. 636 * 637 * @param[in] ctx 638 * Context returned from mlx5 open_device() glue function. 639 * @param[out] attr 640 * Attributes device values. 641 * 642 * @return 643 * 0 on success, a negative value otherwise. 644 */ 645 int 646 mlx5_devx_cmd_query_hca_attr(void *ctx, 647 struct mlx5_hca_attr *attr) 648 { 649 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 650 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 651 void *hcattr; 652 int status, syndrome, rc, i; 653 654 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 655 MLX5_SET(query_hca_cap_in, in, op_mod, 656 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 657 MLX5_HCA_CAP_OPMOD_GET_CUR); 658 659 rc = mlx5_glue->devx_general_cmd(ctx, 660 in, sizeof(in), out, sizeof(out)); 661 if (rc) 662 goto error; 663 status = MLX5_GET(query_hca_cap_out, out, status); 664 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 665 if (status) { 666 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 667 "status %x, syndrome = %x", 668 status, syndrome); 669 return -1; 670 } 671 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 672 attr->flow_counter_bulk_alloc_bitmap = 673 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 674 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 675 flow_counters_dump); 676 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 677 log_max_rqt_size); 678 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 679 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 680 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 681 log_max_hairpin_queues); 682 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 683 log_max_hairpin_wq_data_sz); 684 attr->log_max_hairpin_num_packets = MLX5_GET 685 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 686 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 687 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 688 relaxed_ordering_write); 689 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 690 relaxed_ordering_read); 691 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 692 access_register_user); 693 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 694 eth_net_offloads); 695 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 696 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 697 flex_parser_protocols); 698 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 699 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 700 general_obj_types) & 701 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 702 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 703 general_obj_types) & 704 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 705 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 706 general_obj_types) & 707 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 708 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 709 wqe_index_ignore_cap); 710 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 711 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 712 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 713 log_max_static_sq_wq); 714 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 715 device_frequency_khz); 716 attr->scatter_fcs_w_decap_disable = 717 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 718 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 719 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 720 regexp_num_of_engines); 721 if (attr->qos.sup) { 722 MLX5_SET(query_hca_cap_in, in, op_mod, 723 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 724 MLX5_HCA_CAP_OPMOD_GET_CUR); 725 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 726 out, sizeof(out)); 727 if (rc) 728 goto error; 729 if (status) { 730 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 731 " status %x, syndrome = %x", 732 status, syndrome); 733 return -1; 734 } 735 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 736 attr->qos.srtcm_sup = 737 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm); 738 attr->qos.log_max_flow_meter = 739 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 740 attr->qos.flow_meter_reg_c_ids = 741 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 742 attr->qos.flow_meter_reg_share = 743 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share); 744 attr->qos.packet_pacing = 745 MLX5_GET(qos_cap, hcattr, packet_pacing); 746 attr->qos.wqe_rate_pp = 747 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 748 } 749 if (attr->vdpa.valid) 750 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 751 if (!attr->eth_net_offloads) 752 return 0; 753 754 /* Query HCA offloads for Ethernet protocol. */ 755 memset(in, 0, sizeof(in)); 756 memset(out, 0, sizeof(out)); 757 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 758 MLX5_SET(query_hca_cap_in, in, op_mod, 759 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 760 MLX5_HCA_CAP_OPMOD_GET_CUR); 761 762 rc = mlx5_glue->devx_general_cmd(ctx, 763 in, sizeof(in), 764 out, sizeof(out)); 765 if (rc) { 766 attr->eth_net_offloads = 0; 767 goto error; 768 } 769 status = MLX5_GET(query_hca_cap_out, out, status); 770 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 771 if (status) { 772 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 773 "status %x, syndrome = %x", 774 status, syndrome); 775 attr->eth_net_offloads = 0; 776 return -1; 777 } 778 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 779 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 780 hcattr, wqe_vlan_insert); 781 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 782 lro_cap); 783 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 784 hcattr, tunnel_lro_gre); 785 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 786 hcattr, tunnel_lro_vxlan); 787 attr->lro_max_msg_sz_mode = MLX5_GET 788 (per_protocol_networking_offload_caps, 789 hcattr, lro_max_msg_sz_mode); 790 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 791 attr->lro_timer_supported_periods[i] = 792 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 793 lro_timer_supported_periods[i]); 794 } 795 attr->tunnel_stateless_geneve_rx = 796 MLX5_GET(per_protocol_networking_offload_caps, 797 hcattr, tunnel_stateless_geneve_rx); 798 attr->geneve_max_opt_len = 799 MLX5_GET(per_protocol_networking_offload_caps, 800 hcattr, max_geneve_opt_len); 801 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 802 hcattr, wqe_inline_mode); 803 attr->tunnel_stateless_gtp = MLX5_GET 804 (per_protocol_networking_offload_caps, 805 hcattr, tunnel_stateless_gtp); 806 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 807 return 0; 808 if (attr->eth_virt) { 809 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 810 if (rc) { 811 attr->eth_virt = 0; 812 goto error; 813 } 814 } 815 return 0; 816 error: 817 rc = (rc > 0) ? -rc : rc; 818 return rc; 819 } 820 821 /** 822 * Query TIS transport domain from QP verbs object using DevX API. 823 * 824 * @param[in] qp 825 * Pointer to verbs QP returned by ibv_create_qp . 826 * @param[in] tis_num 827 * TIS number of TIS to query. 828 * @param[out] tis_td 829 * Pointer to TIS transport domain variable, to be set by the routine. 830 * 831 * @return 832 * 0 on success, a negative value otherwise. 833 */ 834 int 835 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 836 uint32_t *tis_td) 837 { 838 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 839 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 840 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 841 int rc; 842 void *tis_ctx; 843 844 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 845 MLX5_SET(query_tis_in, in, tisn, tis_num); 846 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 847 if (rc) { 848 DRV_LOG(ERR, "Failed to query QP using DevX"); 849 return -rc; 850 }; 851 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 852 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 853 return 0; 854 #else 855 (void)qp; 856 (void)tis_num; 857 (void)tis_td; 858 return -ENOTSUP; 859 #endif 860 } 861 862 /** 863 * Fill WQ data for DevX API command. 864 * Utility function for use when creating DevX objects containing a WQ. 865 * 866 * @param[in] wq_ctx 867 * Pointer to WQ context to fill with data. 868 * @param [in] wq_attr 869 * Pointer to WQ attributes structure to fill in WQ context. 870 */ 871 static void 872 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 873 { 874 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 875 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 876 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 877 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 878 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 879 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 880 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 881 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 882 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 883 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 884 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 885 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 886 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 887 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 888 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz); 889 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 890 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 891 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 892 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 893 wq_attr->log_hairpin_num_packets); 894 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 895 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 896 wq_attr->single_wqe_log_num_of_strides); 897 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 898 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 899 wq_attr->single_stride_log_num_of_bytes); 900 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 901 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 902 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 903 } 904 905 /** 906 * Create RQ using DevX API. 907 * 908 * @param[in] ctx 909 * Context returned from mlx5 open_device() glue function. 910 * @param [in] rq_attr 911 * Pointer to create RQ attributes structure. 912 * @param [in] socket 913 * CPU socket ID for allocations. 914 * 915 * @return 916 * The DevX object created, NULL otherwise and rte_errno is set. 917 */ 918 struct mlx5_devx_obj * 919 mlx5_devx_cmd_create_rq(void *ctx, 920 struct mlx5_devx_create_rq_attr *rq_attr, 921 int socket) 922 { 923 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 924 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 925 void *rq_ctx, *wq_ctx; 926 struct mlx5_devx_wq_attr *wq_attr; 927 struct mlx5_devx_obj *rq = NULL; 928 929 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 930 if (!rq) { 931 DRV_LOG(ERR, "Failed to allocate RQ data"); 932 rte_errno = ENOMEM; 933 return NULL; 934 } 935 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 936 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 937 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 938 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 939 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 940 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 941 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 942 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 943 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 944 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 945 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 946 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 947 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 948 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 949 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 950 wq_attr = &rq_attr->wq_attr; 951 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 952 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 953 out, sizeof(out)); 954 if (!rq->obj) { 955 DRV_LOG(ERR, "Failed to create RQ using DevX"); 956 rte_errno = errno; 957 mlx5_free(rq); 958 return NULL; 959 } 960 rq->id = MLX5_GET(create_rq_out, out, rqn); 961 return rq; 962 } 963 964 /** 965 * Modify RQ using DevX API. 966 * 967 * @param[in] rq 968 * Pointer to RQ object structure. 969 * @param [in] rq_attr 970 * Pointer to modify RQ attributes structure. 971 * 972 * @return 973 * 0 on success, a negative errno value otherwise and rte_errno is set. 974 */ 975 int 976 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 977 struct mlx5_devx_modify_rq_attr *rq_attr) 978 { 979 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 980 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 981 void *rq_ctx, *wq_ctx; 982 int ret; 983 984 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 985 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 986 MLX5_SET(modify_rq_in, in, rqn, rq->id); 987 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 988 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 989 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 990 if (rq_attr->modify_bitmask & 991 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 992 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 993 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 994 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 995 if (rq_attr->modify_bitmask & 996 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 997 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 998 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 999 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1000 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1001 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1002 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1003 } 1004 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1005 out, sizeof(out)); 1006 if (ret) { 1007 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1008 rte_errno = errno; 1009 return -errno; 1010 } 1011 return ret; 1012 } 1013 1014 /** 1015 * Create TIR using DevX API. 1016 * 1017 * @param[in] ctx 1018 * Context returned from mlx5 open_device() glue function. 1019 * @param [in] tir_attr 1020 * Pointer to TIR attributes structure. 1021 * 1022 * @return 1023 * The DevX object created, NULL otherwise and rte_errno is set. 1024 */ 1025 struct mlx5_devx_obj * 1026 mlx5_devx_cmd_create_tir(void *ctx, 1027 struct mlx5_devx_tir_attr *tir_attr) 1028 { 1029 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1030 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1031 void *tir_ctx, *outer, *inner, *rss_key; 1032 struct mlx5_devx_obj *tir = NULL; 1033 1034 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1035 if (!tir) { 1036 DRV_LOG(ERR, "Failed to allocate TIR data"); 1037 rte_errno = ENOMEM; 1038 return NULL; 1039 } 1040 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1041 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1042 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1043 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1044 tir_attr->lro_timeout_period_usecs); 1045 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1046 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1047 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1048 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1049 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1050 tir_attr->tunneled_offload_en); 1051 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1052 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1053 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1054 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1055 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1056 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1057 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1058 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1059 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1060 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1061 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1062 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1063 tir_attr->rx_hash_field_selector_outer.selected_fields); 1064 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1065 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1066 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1067 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1068 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1069 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1070 tir_attr->rx_hash_field_selector_inner.selected_fields); 1071 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1072 out, sizeof(out)); 1073 if (!tir->obj) { 1074 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1075 rte_errno = errno; 1076 mlx5_free(tir); 1077 return NULL; 1078 } 1079 tir->id = MLX5_GET(create_tir_out, out, tirn); 1080 return tir; 1081 } 1082 1083 /** 1084 * Create RQT using DevX API. 1085 * 1086 * @param[in] ctx 1087 * Context returned from mlx5 open_device() glue function. 1088 * @param [in] rqt_attr 1089 * Pointer to RQT attributes structure. 1090 * 1091 * @return 1092 * The DevX object created, NULL otherwise and rte_errno is set. 1093 */ 1094 struct mlx5_devx_obj * 1095 mlx5_devx_cmd_create_rqt(void *ctx, 1096 struct mlx5_devx_rqt_attr *rqt_attr) 1097 { 1098 uint32_t *in = NULL; 1099 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1100 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1101 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1102 void *rqt_ctx; 1103 struct mlx5_devx_obj *rqt = NULL; 1104 int i; 1105 1106 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1107 if (!in) { 1108 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1109 rte_errno = ENOMEM; 1110 return NULL; 1111 } 1112 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1113 if (!rqt) { 1114 DRV_LOG(ERR, "Failed to allocate RQT data"); 1115 rte_errno = ENOMEM; 1116 mlx5_free(in); 1117 return NULL; 1118 } 1119 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1120 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1121 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1122 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1123 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1124 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1125 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1126 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1127 mlx5_free(in); 1128 if (!rqt->obj) { 1129 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1130 rte_errno = errno; 1131 mlx5_free(rqt); 1132 return NULL; 1133 } 1134 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1135 return rqt; 1136 } 1137 1138 /** 1139 * Modify RQT using DevX API. 1140 * 1141 * @param[in] rqt 1142 * Pointer to RQT DevX object structure. 1143 * @param [in] rqt_attr 1144 * Pointer to RQT attributes structure. 1145 * 1146 * @return 1147 * 0 on success, a negative errno value otherwise and rte_errno is set. 1148 */ 1149 int 1150 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1151 struct mlx5_devx_rqt_attr *rqt_attr) 1152 { 1153 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1154 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1155 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1156 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1157 void *rqt_ctx; 1158 int i; 1159 int ret; 1160 1161 if (!in) { 1162 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1163 rte_errno = ENOMEM; 1164 return -ENOMEM; 1165 } 1166 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1167 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1168 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1169 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1170 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1171 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1172 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1173 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1174 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1175 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1176 mlx5_free(in); 1177 if (ret) { 1178 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1179 rte_errno = errno; 1180 return -rte_errno; 1181 } 1182 return ret; 1183 } 1184 1185 /** 1186 * Create SQ using DevX API. 1187 * 1188 * @param[in] ctx 1189 * Context returned from mlx5 open_device() glue function. 1190 * @param [in] sq_attr 1191 * Pointer to SQ attributes structure. 1192 * @param [in] socket 1193 * CPU socket ID for allocations. 1194 * 1195 * @return 1196 * The DevX object created, NULL otherwise and rte_errno is set. 1197 **/ 1198 struct mlx5_devx_obj * 1199 mlx5_devx_cmd_create_sq(void *ctx, 1200 struct mlx5_devx_create_sq_attr *sq_attr) 1201 { 1202 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1203 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1204 void *sq_ctx; 1205 void *wq_ctx; 1206 struct mlx5_devx_wq_attr *wq_attr; 1207 struct mlx5_devx_obj *sq = NULL; 1208 1209 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1210 if (!sq) { 1211 DRV_LOG(ERR, "Failed to allocate SQ data"); 1212 rte_errno = ENOMEM; 1213 return NULL; 1214 } 1215 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1216 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1217 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1218 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1219 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1220 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1221 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1222 sq_attr->flush_in_error_en); 1223 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1224 sq_attr->min_wqe_inline_mode); 1225 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1226 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1227 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1228 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1229 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1230 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1231 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1232 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1233 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1234 sq_attr->packet_pacing_rate_limit_index); 1235 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1236 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1237 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1238 wq_attr = &sq_attr->wq_attr; 1239 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1240 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1241 out, sizeof(out)); 1242 if (!sq->obj) { 1243 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1244 rte_errno = errno; 1245 mlx5_free(sq); 1246 return NULL; 1247 } 1248 sq->id = MLX5_GET(create_sq_out, out, sqn); 1249 return sq; 1250 } 1251 1252 /** 1253 * Modify SQ using DevX API. 1254 * 1255 * @param[in] sq 1256 * Pointer to SQ object structure. 1257 * @param [in] sq_attr 1258 * Pointer to SQ attributes structure. 1259 * 1260 * @return 1261 * 0 on success, a negative errno value otherwise and rte_errno is set. 1262 */ 1263 int 1264 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1265 struct mlx5_devx_modify_sq_attr *sq_attr) 1266 { 1267 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1268 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1269 void *sq_ctx; 1270 int ret; 1271 1272 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1273 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1274 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1275 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1276 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1277 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1278 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1279 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1280 out, sizeof(out)); 1281 if (ret) { 1282 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1283 rte_errno = errno; 1284 return -rte_errno; 1285 } 1286 return ret; 1287 } 1288 1289 /** 1290 * Create TIS using DevX API. 1291 * 1292 * @param[in] ctx 1293 * Context returned from mlx5 open_device() glue function. 1294 * @param [in] tis_attr 1295 * Pointer to TIS attributes structure. 1296 * 1297 * @return 1298 * The DevX object created, NULL otherwise and rte_errno is set. 1299 */ 1300 struct mlx5_devx_obj * 1301 mlx5_devx_cmd_create_tis(void *ctx, 1302 struct mlx5_devx_tis_attr *tis_attr) 1303 { 1304 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1305 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1306 struct mlx5_devx_obj *tis = NULL; 1307 void *tis_ctx; 1308 1309 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1310 if (!tis) { 1311 DRV_LOG(ERR, "Failed to allocate TIS object"); 1312 rte_errno = ENOMEM; 1313 return NULL; 1314 } 1315 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1316 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1317 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1318 tis_attr->strict_lag_tx_port_affinity); 1319 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1320 tis_attr->strict_lag_tx_port_affinity); 1321 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1322 MLX5_SET(tisc, tis_ctx, transport_domain, 1323 tis_attr->transport_domain); 1324 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1325 out, sizeof(out)); 1326 if (!tis->obj) { 1327 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1328 rte_errno = errno; 1329 mlx5_free(tis); 1330 return NULL; 1331 } 1332 tis->id = MLX5_GET(create_tis_out, out, tisn); 1333 return tis; 1334 } 1335 1336 /** 1337 * Create transport domain using DevX API. 1338 * 1339 * @param[in] ctx 1340 * Context returned from mlx5 open_device() glue function. 1341 * @return 1342 * The DevX object created, NULL otherwise and rte_errno is set. 1343 */ 1344 struct mlx5_devx_obj * 1345 mlx5_devx_cmd_create_td(void *ctx) 1346 { 1347 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1348 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1349 struct mlx5_devx_obj *td = NULL; 1350 1351 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1352 if (!td) { 1353 DRV_LOG(ERR, "Failed to allocate TD object"); 1354 rte_errno = ENOMEM; 1355 return NULL; 1356 } 1357 MLX5_SET(alloc_transport_domain_in, in, opcode, 1358 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1359 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1360 out, sizeof(out)); 1361 if (!td->obj) { 1362 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1363 rte_errno = errno; 1364 mlx5_free(td); 1365 return NULL; 1366 } 1367 td->id = MLX5_GET(alloc_transport_domain_out, out, 1368 transport_domain); 1369 return td; 1370 } 1371 1372 /** 1373 * Dump all flows to file. 1374 * 1375 * @param[in] fdb_domain 1376 * FDB domain. 1377 * @param[in] rx_domain 1378 * RX domain. 1379 * @param[in] tx_domain 1380 * TX domain. 1381 * @param[out] file 1382 * Pointer to file stream. 1383 * 1384 * @return 1385 * 0 on success, a nagative value otherwise. 1386 */ 1387 int 1388 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1389 void *rx_domain __rte_unused, 1390 void *tx_domain __rte_unused, FILE *file __rte_unused) 1391 { 1392 int ret = 0; 1393 1394 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1395 if (fdb_domain) { 1396 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1397 if (ret) 1398 return ret; 1399 } 1400 MLX5_ASSERT(rx_domain); 1401 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1402 if (ret) 1403 return ret; 1404 MLX5_ASSERT(tx_domain); 1405 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1406 #else 1407 ret = ENOTSUP; 1408 #endif 1409 return -ret; 1410 } 1411 1412 /* 1413 * Create CQ using DevX API. 1414 * 1415 * @param[in] ctx 1416 * Context returned from mlx5 open_device() glue function. 1417 * @param [in] attr 1418 * Pointer to CQ attributes structure. 1419 * 1420 * @return 1421 * The DevX object created, NULL otherwise and rte_errno is set. 1422 */ 1423 struct mlx5_devx_obj * 1424 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1425 { 1426 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1427 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1428 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1429 sizeof(*cq_obj), 1430 0, SOCKET_ID_ANY); 1431 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1432 1433 if (!cq_obj) { 1434 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1435 rte_errno = ENOMEM; 1436 return NULL; 1437 } 1438 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1439 if (attr->db_umem_valid) { 1440 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1441 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1442 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1443 } else { 1444 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1445 } 1446 MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size); 1447 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1448 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1449 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1450 MLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size - 1451 MLX5_ADAPTER_PAGE_SHIFT); 1452 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1453 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1454 MLX5_SET(cqc, cqctx, cqe_comp_en, attr->cqe_comp_en); 1455 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1456 MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size); 1457 if (attr->q_umem_valid) { 1458 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1459 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1460 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1461 attr->q_umem_offset); 1462 } 1463 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1464 sizeof(out)); 1465 if (!cq_obj->obj) { 1466 rte_errno = errno; 1467 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1468 mlx5_free(cq_obj); 1469 return NULL; 1470 } 1471 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1472 return cq_obj; 1473 } 1474 1475 /** 1476 * Create VIRTQ using DevX API. 1477 * 1478 * @param[in] ctx 1479 * Context returned from mlx5 open_device() glue function. 1480 * @param [in] attr 1481 * Pointer to VIRTQ attributes structure. 1482 * 1483 * @return 1484 * The DevX object created, NULL otherwise and rte_errno is set. 1485 */ 1486 struct mlx5_devx_obj * 1487 mlx5_devx_cmd_create_virtq(void *ctx, 1488 struct mlx5_devx_virtq_attr *attr) 1489 { 1490 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1491 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1492 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1493 sizeof(*virtq_obj), 1494 0, SOCKET_ID_ANY); 1495 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1496 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1497 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1498 1499 if (!virtq_obj) { 1500 DRV_LOG(ERR, "Failed to allocate virtq data."); 1501 rte_errno = ENOMEM; 1502 return NULL; 1503 } 1504 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1505 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1506 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1507 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1508 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1509 attr->hw_available_index); 1510 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1511 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1512 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1513 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1514 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1515 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1516 attr->virtio_version_1_0); 1517 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1518 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1519 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1520 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1521 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1522 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1523 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1524 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1525 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1526 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1527 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1528 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1529 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1530 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1531 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1532 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1533 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1534 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1535 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1536 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1537 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1538 sizeof(out)); 1539 if (!virtq_obj->obj) { 1540 rte_errno = errno; 1541 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1542 mlx5_free(virtq_obj); 1543 return NULL; 1544 } 1545 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1546 return virtq_obj; 1547 } 1548 1549 /** 1550 * Modify VIRTQ using DevX API. 1551 * 1552 * @param[in] virtq_obj 1553 * Pointer to virtq object structure. 1554 * @param [in] attr 1555 * Pointer to modify virtq attributes structure. 1556 * 1557 * @return 1558 * 0 on success, a negative errno value otherwise and rte_errno is set. 1559 */ 1560 int 1561 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1562 struct mlx5_devx_virtq_attr *attr) 1563 { 1564 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1565 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1566 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1567 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1568 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1569 int ret; 1570 1571 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1572 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1573 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1574 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1575 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1576 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1577 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1578 switch (attr->type) { 1579 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1580 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1581 break; 1582 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1583 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1584 attr->dirty_bitmap_mkey); 1585 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1586 attr->dirty_bitmap_addr); 1587 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1588 attr->dirty_bitmap_size); 1589 break; 1590 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1591 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1592 attr->dirty_bitmap_dump_enable); 1593 break; 1594 default: 1595 rte_errno = EINVAL; 1596 return -rte_errno; 1597 } 1598 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1599 out, sizeof(out)); 1600 if (ret) { 1601 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1602 rte_errno = errno; 1603 return -rte_errno; 1604 } 1605 return ret; 1606 } 1607 1608 /** 1609 * Query VIRTQ using DevX API. 1610 * 1611 * @param[in] virtq_obj 1612 * Pointer to virtq object structure. 1613 * @param [in/out] attr 1614 * Pointer to virtq attributes structure. 1615 * 1616 * @return 1617 * 0 on success, a negative errno value otherwise and rte_errno is set. 1618 */ 1619 int 1620 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1621 struct mlx5_devx_virtq_attr *attr) 1622 { 1623 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1624 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1625 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1626 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1627 int ret; 1628 1629 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1630 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1631 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1632 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1633 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1634 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1635 out, sizeof(out)); 1636 if (ret) { 1637 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1638 rte_errno = errno; 1639 return -errno; 1640 } 1641 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1642 hw_available_index); 1643 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1644 return ret; 1645 } 1646 1647 /** 1648 * Create QP using DevX API. 1649 * 1650 * @param[in] ctx 1651 * Context returned from mlx5 open_device() glue function. 1652 * @param [in] attr 1653 * Pointer to QP attributes structure. 1654 * 1655 * @return 1656 * The DevX object created, NULL otherwise and rte_errno is set. 1657 */ 1658 struct mlx5_devx_obj * 1659 mlx5_devx_cmd_create_qp(void *ctx, 1660 struct mlx5_devx_qp_attr *attr) 1661 { 1662 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1663 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1664 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1665 sizeof(*qp_obj), 1666 0, SOCKET_ID_ANY); 1667 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1668 1669 if (!qp_obj) { 1670 DRV_LOG(ERR, "Failed to allocate QP data."); 1671 rte_errno = ENOMEM; 1672 return NULL; 1673 } 1674 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 1675 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 1676 MLX5_SET(qpc, qpc, pd, attr->pd); 1677 if (attr->uar_index) { 1678 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1679 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 1680 MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size - 1681 MLX5_ADAPTER_PAGE_SHIFT); 1682 if (attr->sq_size) { 1683 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 1684 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 1685 MLX5_SET(qpc, qpc, log_sq_size, 1686 rte_log2_u32(attr->sq_size)); 1687 } else { 1688 MLX5_SET(qpc, qpc, no_sq, 1); 1689 } 1690 if (attr->rq_size) { 1691 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 1692 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 1693 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 1694 MLX5_LOG_RQ_STRIDE_SHIFT); 1695 MLX5_SET(qpc, qpc, log_rq_size, 1696 rte_log2_u32(attr->rq_size)); 1697 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 1698 } else { 1699 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1700 } 1701 if (attr->dbr_umem_valid) { 1702 MLX5_SET(qpc, qpc, dbr_umem_valid, 1703 attr->dbr_umem_valid); 1704 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 1705 } 1706 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 1707 MLX5_SET64(create_qp_in, in, wq_umem_offset, 1708 attr->wq_umem_offset); 1709 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 1710 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 1711 } else { 1712 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 1713 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1714 MLX5_SET(qpc, qpc, no_sq, 1); 1715 } 1716 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1717 sizeof(out)); 1718 if (!qp_obj->obj) { 1719 rte_errno = errno; 1720 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 1721 mlx5_free(qp_obj); 1722 return NULL; 1723 } 1724 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 1725 return qp_obj; 1726 } 1727 1728 /** 1729 * Modify QP using DevX API. 1730 * Currently supports only force loop-back QP. 1731 * 1732 * @param[in] qp 1733 * Pointer to QP object structure. 1734 * @param [in] qp_st_mod_op 1735 * The QP state modification operation. 1736 * @param [in] remote_qp_id 1737 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 1738 * 1739 * @return 1740 * 0 on success, a negative errno value otherwise and rte_errno is set. 1741 */ 1742 int 1743 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 1744 uint32_t remote_qp_id) 1745 { 1746 union { 1747 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 1748 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 1749 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 1750 } in; 1751 union { 1752 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 1753 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 1754 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 1755 } out; 1756 void *qpc; 1757 int ret; 1758 unsigned int inlen; 1759 unsigned int outlen; 1760 1761 memset(&in, 0, sizeof(in)); 1762 memset(&out, 0, sizeof(out)); 1763 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 1764 switch (qp_st_mod_op) { 1765 case MLX5_CMD_OP_RST2INIT_QP: 1766 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 1767 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 1768 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1769 MLX5_SET(qpc, qpc, rre, 1); 1770 MLX5_SET(qpc, qpc, rwe, 1); 1771 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1772 inlen = sizeof(in.rst2init); 1773 outlen = sizeof(out.rst2init); 1774 break; 1775 case MLX5_CMD_OP_INIT2RTR_QP: 1776 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 1777 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 1778 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 1779 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1780 MLX5_SET(qpc, qpc, mtu, 1); 1781 MLX5_SET(qpc, qpc, log_msg_max, 30); 1782 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 1783 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 1784 inlen = sizeof(in.init2rtr); 1785 outlen = sizeof(out.init2rtr); 1786 break; 1787 case MLX5_CMD_OP_RTR2RTS_QP: 1788 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 1789 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 1790 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 1791 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 1792 MLX5_SET(qpc, qpc, retry_count, 7); 1793 MLX5_SET(qpc, qpc, rnr_retry, 7); 1794 inlen = sizeof(in.rtr2rts); 1795 outlen = sizeof(out.rtr2rts); 1796 break; 1797 default: 1798 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 1799 qp_st_mod_op); 1800 rte_errno = EINVAL; 1801 return -rte_errno; 1802 } 1803 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 1804 if (ret) { 1805 DRV_LOG(ERR, "Failed to modify QP using DevX."); 1806 rte_errno = errno; 1807 return -rte_errno; 1808 } 1809 return ret; 1810 } 1811 1812 struct mlx5_devx_obj * 1813 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 1814 { 1815 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 1816 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1817 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 1818 sizeof(*couners_obj), 0, 1819 SOCKET_ID_ANY); 1820 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 1821 1822 if (!couners_obj) { 1823 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 1824 rte_errno = ENOMEM; 1825 return NULL; 1826 } 1827 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1828 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1829 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1830 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1831 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1832 sizeof(out)); 1833 if (!couners_obj->obj) { 1834 rte_errno = errno; 1835 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 1836 " DevX."); 1837 mlx5_free(couners_obj); 1838 return NULL; 1839 } 1840 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1841 return couners_obj; 1842 } 1843 1844 int 1845 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 1846 struct mlx5_devx_virtio_q_couners_attr *attr) 1847 { 1848 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1849 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 1850 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 1851 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 1852 virtio_q_counters); 1853 int ret; 1854 1855 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1856 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1857 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1858 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1859 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 1860 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 1861 sizeof(out)); 1862 if (ret) { 1863 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 1864 rte_errno = errno; 1865 return -errno; 1866 } 1867 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 1868 received_desc); 1869 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 1870 completed_desc); 1871 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 1872 error_cqes); 1873 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 1874 bad_desc_errors); 1875 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 1876 exceed_max_chain); 1877 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 1878 invalid_buffer); 1879 return ret; 1880 } 1881