1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 static void * 17 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, 18 int *err, uint32_t flags) 19 { 20 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); 21 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); 22 int status, syndrome, rc; 23 24 if (err) 25 *err = 0; 26 memset(in, 0, size_in); 27 memset(out, 0, size_out); 28 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 29 MLX5_SET(query_hca_cap_in, in, op_mod, flags); 30 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); 31 if (rc) { 32 DRV_LOG(ERR, 33 "Failed to query devx HCA capabilities func %#02x", 34 flags >> 1); 35 if (err) 36 *err = rc > 0 ? -rc : rc; 37 return NULL; 38 } 39 status = MLX5_GET(query_hca_cap_out, out, status); 40 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 41 if (status) { 42 DRV_LOG(ERR, 43 "Failed to query devx HCA capabilities func %#02x status %x, syndrome = %x", 44 flags >> 1, status, syndrome); 45 if (err) 46 *err = -1; 47 return NULL; 48 } 49 return MLX5_ADDR_OF(query_hca_cap_out, out, capability); 50 } 51 52 /** 53 * Perform read access to the registers. Reads data from register 54 * and writes ones to the specified buffer. 55 * 56 * @param[in] ctx 57 * Context returned from mlx5 open_device() glue function. 58 * @param[in] reg_id 59 * Register identifier according to the PRM. 60 * @param[in] arg 61 * Register access auxiliary parameter according to the PRM. 62 * @param[out] data 63 * Pointer to the buffer to store read data. 64 * @param[in] dw_cnt 65 * Buffer size in double words. 66 * 67 * @return 68 * 0 on success, a negative value otherwise. 69 */ 70 int 71 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 72 uint32_t *data, uint32_t dw_cnt) 73 { 74 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 75 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 76 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 77 int status, rc; 78 79 MLX5_ASSERT(data && dw_cnt); 80 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 81 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 82 DRV_LOG(ERR, "Not enough buffer for register read data"); 83 return -1; 84 } 85 MLX5_SET(access_register_in, in, opcode, 86 MLX5_CMD_OP_ACCESS_REGISTER_USER); 87 MLX5_SET(access_register_in, in, op_mod, 88 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 89 MLX5_SET(access_register_in, in, register_id, reg_id); 90 MLX5_SET(access_register_in, in, argument, arg); 91 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 92 MLX5_ST_SZ_BYTES(access_register_out) + 93 sizeof(uint32_t) * dw_cnt); 94 if (rc) 95 goto error; 96 status = MLX5_GET(access_register_out, out, status); 97 if (status) { 98 int syndrome = MLX5_GET(access_register_out, out, syndrome); 99 100 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " 101 "status %x, syndrome = %x", 102 reg_id, status, syndrome); 103 return -1; 104 } 105 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 106 dw_cnt * sizeof(uint32_t)); 107 return 0; 108 error: 109 rc = (rc > 0) ? -rc : rc; 110 return rc; 111 } 112 113 /** 114 * Perform write access to the registers. 115 * 116 * @param[in] ctx 117 * Context returned from mlx5 open_device() glue function. 118 * @param[in] reg_id 119 * Register identifier according to the PRM. 120 * @param[in] arg 121 * Register access auxiliary parameter according to the PRM. 122 * @param[out] data 123 * Pointer to the buffer containing data to write. 124 * @param[in] dw_cnt 125 * Buffer size in double words (32bit units). 126 * 127 * @return 128 * 0 on success, a negative value otherwise. 129 */ 130 int 131 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 132 uint32_t *data, uint32_t dw_cnt) 133 { 134 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 135 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 136 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 137 int status, rc; 138 void *ptr; 139 140 MLX5_ASSERT(data && dw_cnt); 141 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 142 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 143 DRV_LOG(ERR, "Data to write exceeds max size"); 144 return -1; 145 } 146 MLX5_SET(access_register_in, in, opcode, 147 MLX5_CMD_OP_ACCESS_REGISTER_USER); 148 MLX5_SET(access_register_in, in, op_mod, 149 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 150 MLX5_SET(access_register_in, in, register_id, reg_id); 151 MLX5_SET(access_register_in, in, argument, arg); 152 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 153 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 154 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 155 156 rc = mlx5_glue->devx_general_cmd(ctx, in, 157 MLX5_ST_SZ_BYTES(access_register_in) + 158 dw_cnt * sizeof(uint32_t), 159 out, sizeof(out)); 160 if (rc) 161 goto error; 162 status = MLX5_GET(access_register_out, out, status); 163 if (status) { 164 int syndrome = MLX5_GET(access_register_out, out, syndrome); 165 166 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " 167 "status %x, syndrome = %x", 168 reg_id, status, syndrome); 169 return -1; 170 } 171 return 0; 172 error: 173 rc = (rc > 0) ? -rc : rc; 174 return rc; 175 } 176 177 /** 178 * Allocate flow counters via devx interface. 179 * 180 * @param[in] ctx 181 * Context returned from mlx5 open_device() glue function. 182 * @param dcs 183 * Pointer to counters properties structure to be filled by the routine. 184 * @param bulk_n_128 185 * Bulk counter numbers in 128 counters units. 186 * 187 * @return 188 * Pointer to counter object on success, a negative value otherwise and 189 * rte_errno is set. 190 */ 191 struct mlx5_devx_obj * 192 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 193 { 194 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 195 0, SOCKET_ID_ANY); 196 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 197 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 198 199 if (!dcs) { 200 rte_errno = ENOMEM; 201 return NULL; 202 } 203 MLX5_SET(alloc_flow_counter_in, in, opcode, 204 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 205 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 206 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 207 sizeof(in), out, sizeof(out)); 208 if (!dcs->obj) { 209 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 210 rte_errno = errno; 211 mlx5_free(dcs); 212 return NULL; 213 } 214 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 215 return dcs; 216 } 217 218 /** 219 * Query flow counters values. 220 * 221 * @param[in] dcs 222 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 223 * @param[in] clear 224 * Whether hardware should clear the counters after the query or not. 225 * @param[in] n_counters 226 * 0 in case of 1 counter to read, otherwise the counter number to read. 227 * @param pkts 228 * The number of packets that matched the flow. 229 * @param bytes 230 * The number of bytes that matched the flow. 231 * @param mkey 232 * The mkey key for batch query. 233 * @param addr 234 * The address in the mkey range for batch query. 235 * @param cmd_comp 236 * The completion object for asynchronous batch query. 237 * @param async_id 238 * The ID to be returned in the asynchronous batch query response. 239 * 240 * @return 241 * 0 on success, a negative value otherwise. 242 */ 243 int 244 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 245 int clear, uint32_t n_counters, 246 uint64_t *pkts, uint64_t *bytes, 247 uint32_t mkey, void *addr, 248 void *cmd_comp, 249 uint64_t async_id) 250 { 251 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 252 MLX5_ST_SZ_BYTES(traffic_counter); 253 uint32_t out[out_len]; 254 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 255 void *stats; 256 int rc; 257 258 MLX5_SET(query_flow_counter_in, in, opcode, 259 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 260 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 261 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 262 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 263 264 if (n_counters) { 265 MLX5_SET(query_flow_counter_in, in, num_of_counters, 266 n_counters); 267 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 268 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 269 MLX5_SET64(query_flow_counter_in, in, address, 270 (uint64_t)(uintptr_t)addr); 271 } 272 if (!cmd_comp) 273 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 274 out_len); 275 else 276 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 277 out_len, async_id, 278 cmd_comp); 279 if (rc) { 280 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 281 rte_errno = rc; 282 return -rc; 283 } 284 if (!n_counters) { 285 stats = MLX5_ADDR_OF(query_flow_counter_out, 286 out, flow_statistics); 287 *pkts = MLX5_GET64(traffic_counter, stats, packets); 288 *bytes = MLX5_GET64(traffic_counter, stats, octets); 289 } 290 return 0; 291 } 292 293 /** 294 * Create a new mkey. 295 * 296 * @param[in] ctx 297 * Context returned from mlx5 open_device() glue function. 298 * @param[in] attr 299 * Attributes of the requested mkey. 300 * 301 * @return 302 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 303 * is set. 304 */ 305 struct mlx5_devx_obj * 306 mlx5_devx_cmd_mkey_create(void *ctx, 307 struct mlx5_devx_mkey_attr *attr) 308 { 309 struct mlx5_klm *klm_array = attr->klm_array; 310 int klm_num = attr->klm_num; 311 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 312 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 313 uint32_t in[in_size_dw]; 314 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 315 void *mkc; 316 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 317 0, SOCKET_ID_ANY); 318 size_t pgsize; 319 uint32_t translation_size; 320 321 if (!mkey) { 322 rte_errno = ENOMEM; 323 return NULL; 324 } 325 memset(in, 0, in_size_dw * 4); 326 pgsize = rte_mem_page_size(); 327 if (pgsize == (size_t)-1) { 328 mlx5_free(mkey); 329 DRV_LOG(ERR, "Failed to get page size"); 330 rte_errno = ENOMEM; 331 return NULL; 332 } 333 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 334 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 335 if (klm_num > 0) { 336 int i; 337 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 338 klm_pas_mtt); 339 translation_size = RTE_ALIGN(klm_num, 4); 340 for (i = 0; i < klm_num; i++) { 341 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 342 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 343 MLX5_SET64(klm, klm, address, klm_array[i].address); 344 klm += MLX5_ST_SZ_BYTES(klm); 345 } 346 for (; i < (int)translation_size; i++) { 347 MLX5_SET(klm, klm, mkey, 0x0); 348 MLX5_SET64(klm, klm, address, 0x0); 349 klm += MLX5_ST_SZ_BYTES(klm); 350 } 351 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 352 MLX5_MKC_ACCESS_MODE_KLM_FBS : 353 MLX5_MKC_ACCESS_MODE_KLM); 354 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 355 } else { 356 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 357 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 358 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 359 } 360 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 361 translation_size); 362 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 363 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 364 MLX5_SET(mkc, mkc, lw, 0x1); 365 MLX5_SET(mkc, mkc, lr, 0x1); 366 if (attr->set_remote_rw) { 367 MLX5_SET(mkc, mkc, rw, 0x1); 368 MLX5_SET(mkc, mkc, rr, 0x1); 369 } 370 MLX5_SET(mkc, mkc, qpn, 0xffffff); 371 MLX5_SET(mkc, mkc, pd, attr->pd); 372 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 373 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 374 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 375 MLX5_SET(mkc, mkc, relaxed_ordering_write, 376 attr->relaxed_ordering_write); 377 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 378 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 379 MLX5_SET64(mkc, mkc, len, attr->size); 380 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 381 if (attr->crypto_en) { 382 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 383 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 384 } 385 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 386 sizeof(out)); 387 if (!mkey->obj) { 388 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 389 klm_num ? "an in" : "a ", errno); 390 rte_errno = errno; 391 mlx5_free(mkey); 392 return NULL; 393 } 394 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 395 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 396 return mkey; 397 } 398 399 /** 400 * Get status of devx command response. 401 * Mainly used for asynchronous commands. 402 * 403 * @param[in] out 404 * The out response buffer. 405 * 406 * @return 407 * 0 on success, non-zero value otherwise. 408 */ 409 int 410 mlx5_devx_get_out_command_status(void *out) 411 { 412 int status; 413 414 if (!out) 415 return -EINVAL; 416 status = MLX5_GET(query_flow_counter_out, out, status); 417 if (status) { 418 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 419 420 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 421 syndrome); 422 } 423 return status; 424 } 425 426 /** 427 * Destroy any object allocated by a Devx API. 428 * 429 * @param[in] obj 430 * Pointer to a general object. 431 * 432 * @return 433 * 0 on success, a negative value otherwise. 434 */ 435 int 436 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 437 { 438 int ret; 439 440 if (!obj) 441 return 0; 442 ret = mlx5_glue->devx_obj_destroy(obj->obj); 443 mlx5_free(obj); 444 return ret; 445 } 446 447 /** 448 * Query NIC vport context. 449 * Fills minimal inline attribute. 450 * 451 * @param[in] ctx 452 * ibv contexts returned from mlx5dv_open_device. 453 * @param[in] vport 454 * vport index 455 * @param[out] attr 456 * Attributes device values. 457 * 458 * @return 459 * 0 on success, a negative value otherwise. 460 */ 461 static int 462 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 463 unsigned int vport, 464 struct mlx5_hca_attr *attr) 465 { 466 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 467 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 468 void *vctx; 469 int status, syndrome, rc; 470 471 /* Query NIC vport context to determine inline mode. */ 472 MLX5_SET(query_nic_vport_context_in, in, opcode, 473 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 474 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 475 if (vport) 476 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 477 rc = mlx5_glue->devx_general_cmd(ctx, 478 in, sizeof(in), 479 out, sizeof(out)); 480 if (rc) 481 goto error; 482 status = MLX5_GET(query_nic_vport_context_out, out, status); 483 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 484 if (status) { 485 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 486 "status %x, syndrome = %x", status, syndrome); 487 return -1; 488 } 489 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 490 nic_vport_context); 491 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 492 min_wqe_inline_mode); 493 return 0; 494 error: 495 rc = (rc > 0) ? -rc : rc; 496 return rc; 497 } 498 499 /** 500 * Query NIC vDPA attributes. 501 * 502 * @param[in] ctx 503 * Context returned from mlx5 open_device() glue function. 504 * @param[out] vdpa_attr 505 * vDPA Attributes structure to fill. 506 */ 507 static void 508 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 509 struct mlx5_hca_vdpa_attr *vdpa_attr) 510 { 511 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 512 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 513 void *hcattr; 514 515 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, 516 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 517 MLX5_HCA_CAP_OPMOD_GET_CUR); 518 if (!hcattr) { 519 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); 520 vdpa_attr->valid = 0; 521 } else { 522 vdpa_attr->valid = 1; 523 vdpa_attr->desc_tunnel_offload_type = 524 MLX5_GET(virtio_emulation_cap, hcattr, 525 desc_tunnel_offload_type); 526 vdpa_attr->eth_frame_offload_type = 527 MLX5_GET(virtio_emulation_cap, hcattr, 528 eth_frame_offload_type); 529 vdpa_attr->virtio_version_1_0 = 530 MLX5_GET(virtio_emulation_cap, hcattr, 531 virtio_version_1_0); 532 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 533 tso_ipv4); 534 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 535 tso_ipv6); 536 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 537 tx_csum); 538 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 539 rx_csum); 540 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 541 event_mode); 542 vdpa_attr->virtio_queue_type = 543 MLX5_GET(virtio_emulation_cap, hcattr, 544 virtio_queue_type); 545 vdpa_attr->log_doorbell_stride = 546 MLX5_GET(virtio_emulation_cap, hcattr, 547 log_doorbell_stride); 548 vdpa_attr->log_doorbell_bar_size = 549 MLX5_GET(virtio_emulation_cap, hcattr, 550 log_doorbell_bar_size); 551 vdpa_attr->doorbell_bar_offset = 552 MLX5_GET64(virtio_emulation_cap, hcattr, 553 doorbell_bar_offset); 554 vdpa_attr->max_num_virtio_queues = 555 MLX5_GET(virtio_emulation_cap, hcattr, 556 max_num_virtio_queues); 557 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 558 umem_1_buffer_param_a); 559 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 560 umem_1_buffer_param_b); 561 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 562 umem_2_buffer_param_a); 563 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 564 umem_2_buffer_param_b); 565 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 566 umem_3_buffer_param_a); 567 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 568 umem_3_buffer_param_b); 569 } 570 } 571 572 int 573 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 574 uint32_t ids[], uint32_t num) 575 { 576 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 577 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 578 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 579 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 580 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 581 int ret; 582 uint32_t idx = 0; 583 uint32_t i; 584 585 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 586 rte_errno = EINVAL; 587 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 588 return -rte_errno; 589 } 590 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 591 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 592 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 593 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 594 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 595 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 596 out, sizeof(out)); 597 if (ret) { 598 rte_errno = ret; 599 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 600 (void *)flex_obj); 601 return -rte_errno; 602 } 603 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 604 void *s_off = (void *)((char *)sample + i * 605 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 606 uint32_t en; 607 608 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 609 flow_match_sample_en); 610 if (!en) 611 continue; 612 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 613 flow_match_sample_field_id); 614 } 615 if (num != idx) { 616 rte_errno = EINVAL; 617 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 618 return -rte_errno; 619 } 620 return ret; 621 } 622 623 struct mlx5_devx_obj * 624 mlx5_devx_cmd_create_flex_parser(void *ctx, 625 struct mlx5_devx_graph_node_attr *data) 626 { 627 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 628 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 629 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 630 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 631 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 632 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 633 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 634 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 635 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 636 uint32_t i; 637 638 if (!parse_flex_obj) { 639 DRV_LOG(ERR, "Failed to allocate flex parser data."); 640 rte_errno = ENOMEM; 641 return NULL; 642 } 643 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 644 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 645 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 646 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 647 MLX5_SET(parse_graph_flex, flex, header_length_mode, 648 data->header_length_mode); 649 MLX5_SET64(parse_graph_flex, flex, modify_field_select, 650 data->modify_field_select); 651 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 652 data->header_length_base_value); 653 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 654 data->header_length_field_offset); 655 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 656 data->header_length_field_shift); 657 MLX5_SET(parse_graph_flex, flex, next_header_field_offset, 658 data->next_header_field_offset); 659 MLX5_SET(parse_graph_flex, flex, next_header_field_size, 660 data->next_header_field_size); 661 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 662 data->header_length_field_mask); 663 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 664 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 665 void *s_off = (void *)((char *)sample + i * 666 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 667 668 if (!s->flow_match_sample_en) 669 continue; 670 MLX5_SET(parse_graph_flow_match_sample, s_off, 671 flow_match_sample_en, !!s->flow_match_sample_en); 672 MLX5_SET(parse_graph_flow_match_sample, s_off, 673 flow_match_sample_field_offset, 674 s->flow_match_sample_field_offset); 675 MLX5_SET(parse_graph_flow_match_sample, s_off, 676 flow_match_sample_offset_mode, 677 s->flow_match_sample_offset_mode); 678 MLX5_SET(parse_graph_flow_match_sample, s_off, 679 flow_match_sample_field_offset_mask, 680 s->flow_match_sample_field_offset_mask); 681 MLX5_SET(parse_graph_flow_match_sample, s_off, 682 flow_match_sample_field_offset_shift, 683 s->flow_match_sample_field_offset_shift); 684 MLX5_SET(parse_graph_flow_match_sample, s_off, 685 flow_match_sample_field_base_offset, 686 s->flow_match_sample_field_base_offset); 687 MLX5_SET(parse_graph_flow_match_sample, s_off, 688 flow_match_sample_tunnel_mode, 689 s->flow_match_sample_tunnel_mode); 690 } 691 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 692 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 693 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 694 void *in_off = (void *)((char *)in_arc + i * 695 MLX5_ST_SZ_BYTES(parse_graph_arc)); 696 void *out_off = (void *)((char *)out_arc + i * 697 MLX5_ST_SZ_BYTES(parse_graph_arc)); 698 699 if (ia->arc_parse_graph_node != 0) { 700 MLX5_SET(parse_graph_arc, in_off, 701 compare_condition_value, 702 ia->compare_condition_value); 703 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 704 ia->start_inner_tunnel); 705 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 706 ia->arc_parse_graph_node); 707 MLX5_SET(parse_graph_arc, in_off, 708 parse_graph_node_handle, 709 ia->parse_graph_node_handle); 710 } 711 if (oa->arc_parse_graph_node != 0) { 712 MLX5_SET(parse_graph_arc, out_off, 713 compare_condition_value, 714 oa->compare_condition_value); 715 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 716 oa->start_inner_tunnel); 717 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 718 oa->arc_parse_graph_node); 719 MLX5_SET(parse_graph_arc, out_off, 720 parse_graph_node_handle, 721 oa->parse_graph_node_handle); 722 } 723 } 724 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 725 out, sizeof(out)); 726 if (!parse_flex_obj->obj) { 727 rte_errno = errno; 728 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 729 "by using DevX."); 730 mlx5_free(parse_flex_obj); 731 return NULL; 732 } 733 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 734 return parse_flex_obj; 735 } 736 737 static int 738 mlx5_devx_cmd_query_hca_parse_graph_node_cap 739 (void *ctx, struct mlx5_hca_flex_attr *attr) 740 { 741 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; 742 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; 743 void *hcattr; 744 int rc; 745 746 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 747 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP | 748 MLX5_HCA_CAP_OPMOD_GET_CUR); 749 if (!hcattr) 750 return rc; 751 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in); 752 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out); 753 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr, 754 header_length_mode); 755 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr, 756 sample_offset_mode); 757 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr, 758 max_num_arc_in); 759 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr, 760 max_num_arc_out); 761 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, 762 max_num_sample); 763 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, 764 sample_id_in_out); 765 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, 766 max_base_header_length); 767 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr, 768 max_sample_base_offset); 769 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr, 770 max_next_header_offset); 771 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr, 772 header_length_mask_width); 773 /* Get the max supported samples from HCA CAP 2 */ 774 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 775 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 776 MLX5_HCA_CAP_OPMOD_GET_CUR); 777 if (!hcattr) 778 return rc; 779 attr->max_num_prog_sample = 780 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field); 781 return 0; 782 } 783 784 static int 785 mlx5_devx_query_pkt_integrity_match(void *hcattr) 786 { 787 return MLX5_GET(flow_table_nic_cap, hcattr, 788 ft_field_support_2_nic_receive.inner_l3_ok) && 789 MLX5_GET(flow_table_nic_cap, hcattr, 790 ft_field_support_2_nic_receive.inner_l4_ok) && 791 MLX5_GET(flow_table_nic_cap, hcattr, 792 ft_field_support_2_nic_receive.outer_l3_ok) && 793 MLX5_GET(flow_table_nic_cap, hcattr, 794 ft_field_support_2_nic_receive.outer_l4_ok) && 795 MLX5_GET(flow_table_nic_cap, hcattr, 796 ft_field_support_2_nic_receive 797 .inner_ipv4_checksum_ok) && 798 MLX5_GET(flow_table_nic_cap, hcattr, 799 ft_field_support_2_nic_receive.inner_l4_checksum_ok) && 800 MLX5_GET(flow_table_nic_cap, hcattr, 801 ft_field_support_2_nic_receive 802 .outer_ipv4_checksum_ok) && 803 MLX5_GET(flow_table_nic_cap, hcattr, 804 ft_field_support_2_nic_receive.outer_l4_checksum_ok); 805 } 806 807 /** 808 * Query HCA attributes. 809 * Using those attributes we can check on run time if the device 810 * is having the required capabilities. 811 * 812 * @param[in] ctx 813 * Context returned from mlx5 open_device() glue function. 814 * @param[out] attr 815 * Attributes device values. 816 * 817 * @return 818 * 0 on success, a negative value otherwise. 819 */ 820 int 821 mlx5_devx_cmd_query_hca_attr(void *ctx, 822 struct mlx5_hca_attr *attr) 823 { 824 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 825 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 826 bool hca_cap_2_sup; 827 uint64_t general_obj_types_supported = 0; 828 void *hcattr; 829 int rc, i; 830 831 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 832 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 833 MLX5_HCA_CAP_OPMOD_GET_CUR); 834 if (!hcattr) 835 return rc; 836 hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2); 837 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq); 838 attr->flow_counter_bulk_alloc_bitmap = 839 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 840 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 841 flow_counters_dump); 842 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp); 843 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp); 844 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 845 log_max_rqt_size); 846 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 847 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 848 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 849 log_max_hairpin_queues); 850 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 851 log_max_hairpin_wq_data_sz); 852 attr->log_max_hairpin_num_packets = MLX5_GET 853 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 854 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 855 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 856 relaxed_ordering_write); 857 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 858 relaxed_ordering_read); 859 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 860 access_register_user); 861 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 862 eth_net_offloads); 863 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 864 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 865 flex_parser_protocols); 866 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 867 max_geneve_tlv_options); 868 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 869 max_geneve_tlv_option_data_len); 870 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 871 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 872 general_obj_types) & 873 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 874 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 875 general_obj_types) & 876 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 877 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 878 general_obj_types) & 879 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 880 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 881 general_obj_types) & 882 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 883 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 884 wqe_index_ignore_cap); 885 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 886 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 887 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 888 log_max_static_sq_wq); 889 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 890 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 891 device_frequency_khz); 892 attr->scatter_fcs_w_decap_disable = 893 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 894 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 895 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 896 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 897 attr->steering_format_version = 898 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version); 899 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params); 900 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version); 901 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 902 regexp_num_of_engines); 903 /* Read the general_obj_types bitmap and extract the relevant bits. */ 904 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 905 general_obj_types); 906 attr->vdpa.valid = !!(general_obj_types_supported & 907 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 908 attr->vdpa.queue_counters_valid = 909 !!(general_obj_types_supported & 910 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 911 attr->parse_graph_flex_node = 912 !!(general_obj_types_supported & 913 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 914 attr->flow_hit_aso = !!(general_obj_types_supported & 915 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 916 attr->geneve_tlv_opt = !!(general_obj_types_supported & 917 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 918 attr->dek = !!(general_obj_types_supported & 919 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 920 attr->import_kek = !!(general_obj_types_supported & 921 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 922 attr->credential = !!(general_obj_types_supported & 923 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 924 attr->crypto_login = !!(general_obj_types_supported & 925 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 926 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 927 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 928 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 929 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 930 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 931 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 932 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 933 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 934 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 935 attr->reg_c_preserve = 936 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 937 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp); 938 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq); 939 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq); 940 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 941 compress_mmo_sq); 942 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, 943 decompress_mmo_sq); 944 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp); 945 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 946 compress_mmo_qp); 947 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, 948 decompress_mmo_qp); 949 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 950 compress_min_block_size); 951 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 952 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 953 log_compress_mmo_size); 954 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 955 log_decompress_mmo_size); 956 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 957 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 958 mini_cqe_resp_flow_tag); 959 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 960 mini_cqe_resp_l3_l4_tag); 961 attr->umr_indirect_mkey_disabled = 962 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 963 attr->umr_modify_entity_size_disabled = 964 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 965 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 966 if (attr->crypto) 967 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 968 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, 969 general_obj_types) & 970 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); 971 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); 972 if (hca_cap_2_sup) { 973 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 974 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 | 975 MLX5_HCA_CAP_OPMOD_GET_CUR); 976 if (!hcattr) { 977 DRV_LOG(DEBUG, 978 "Failed to query DevX HCA capabilities 2."); 979 return rc; 980 } 981 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr, 982 log_min_stride_wqe_sz); 983 } 984 if (attr->log_min_stride_wqe_sz == 0) 985 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE; 986 if (attr->qos.sup) { 987 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 988 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 989 MLX5_HCA_CAP_OPMOD_GET_CUR); 990 if (!hcattr) { 991 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); 992 return rc; 993 } 994 attr->qos.flow_meter_old = 995 MLX5_GET(qos_cap, hcattr, flow_meter_old); 996 attr->qos.log_max_flow_meter = 997 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 998 attr->qos.flow_meter_reg_c_ids = 999 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 1000 attr->qos.flow_meter = 1001 MLX5_GET(qos_cap, hcattr, flow_meter); 1002 attr->qos.packet_pacing = 1003 MLX5_GET(qos_cap, hcattr, packet_pacing); 1004 attr->qos.wqe_rate_pp = 1005 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 1006 if (attr->qos.flow_meter_aso_sup) { 1007 attr->qos.log_meter_aso_granularity = 1008 MLX5_GET(qos_cap, hcattr, 1009 log_meter_aso_granularity); 1010 attr->qos.log_meter_aso_max_alloc = 1011 MLX5_GET(qos_cap, hcattr, 1012 log_meter_aso_max_alloc); 1013 attr->qos.log_max_num_meter_aso = 1014 MLX5_GET(qos_cap, hcattr, 1015 log_max_num_meter_aso); 1016 } 1017 } 1018 /* 1019 * Flex item support needs max_num_prog_sample_field 1020 * from the Capabilities 2 table for PARSE_GRAPH_NODE 1021 */ 1022 if (attr->parse_graph_flex_node) { 1023 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap 1024 (ctx, &attr->flex); 1025 if (rc) 1026 return -1; 1027 } 1028 if (attr->vdpa.valid) 1029 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 1030 if (!attr->eth_net_offloads) 1031 return 0; 1032 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 1033 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1034 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 1035 MLX5_HCA_CAP_OPMOD_GET_CUR); 1036 if (!hcattr) { 1037 attr->log_max_ft_sampler_num = 0; 1038 return rc; 1039 } 1040 attr->log_max_ft_sampler_num = MLX5_GET 1041 (flow_table_nic_cap, hcattr, 1042 flow_table_properties_nic_receive.log_max_ft_sampler_num); 1043 attr->flow.tunnel_header_0_1 = MLX5_GET 1044 (flow_table_nic_cap, hcattr, 1045 ft_field_support_2_nic_receive.tunnel_header_0_1); 1046 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr); 1047 attr->inner_ipv4_ihl = MLX5_GET 1048 (flow_table_nic_cap, hcattr, 1049 ft_field_support_2_nic_receive.inner_ipv4_ihl); 1050 attr->outer_ipv4_ihl = MLX5_GET 1051 (flow_table_nic_cap, hcattr, 1052 ft_field_support_2_nic_receive.outer_ipv4_ihl); 1053 /* Query HCA offloads for Ethernet protocol. */ 1054 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1055 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 1056 MLX5_HCA_CAP_OPMOD_GET_CUR); 1057 if (!hcattr) { 1058 attr->eth_net_offloads = 0; 1059 return rc; 1060 } 1061 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 1062 hcattr, wqe_vlan_insert); 1063 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, 1064 hcattr, csum_cap); 1065 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps, 1066 hcattr, vlan_cap); 1067 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1068 lro_cap); 1069 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps, 1070 hcattr, max_lso_cap); 1071 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps, 1072 hcattr, scatter_fcs); 1073 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 1074 hcattr, tunnel_lro_gre); 1075 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 1076 hcattr, tunnel_lro_vxlan); 1077 attr->swp = MLX5_GET(per_protocol_networking_offload_caps, 1078 hcattr, swp); 1079 attr->tunnel_stateless_gre = 1080 MLX5_GET(per_protocol_networking_offload_caps, 1081 hcattr, tunnel_stateless_gre); 1082 attr->tunnel_stateless_vxlan = 1083 MLX5_GET(per_protocol_networking_offload_caps, 1084 hcattr, tunnel_stateless_vxlan); 1085 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps, 1086 hcattr, swp_csum); 1087 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps, 1088 hcattr, swp_lso); 1089 attr->lro_max_msg_sz_mode = MLX5_GET 1090 (per_protocol_networking_offload_caps, 1091 hcattr, lro_max_msg_sz_mode); 1092 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 1093 attr->lro_timer_supported_periods[i] = 1094 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 1095 lro_timer_supported_periods[i]); 1096 } 1097 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 1098 hcattr, lro_min_mss_size); 1099 attr->tunnel_stateless_geneve_rx = 1100 MLX5_GET(per_protocol_networking_offload_caps, 1101 hcattr, tunnel_stateless_geneve_rx); 1102 attr->geneve_max_opt_len = 1103 MLX5_GET(per_protocol_networking_offload_caps, 1104 hcattr, max_geneve_opt_len); 1105 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 1106 hcattr, wqe_inline_mode); 1107 attr->tunnel_stateless_gtp = MLX5_GET 1108 (per_protocol_networking_offload_caps, 1109 hcattr, tunnel_stateless_gtp); 1110 attr->rss_ind_tbl_cap = MLX5_GET 1111 (per_protocol_networking_offload_caps, 1112 hcattr, rss_ind_tbl_cap); 1113 /* Query HCA attribute for ROCE. */ 1114 if (attr->roce) { 1115 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, 1116 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 1117 MLX5_HCA_CAP_OPMOD_GET_CUR); 1118 if (!hcattr) { 1119 DRV_LOG(DEBUG, 1120 "Failed to query devx HCA ROCE capabilities"); 1121 return rc; 1122 } 1123 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1124 } 1125 if (attr->eth_virt && 1126 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1127 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1128 if (rc) { 1129 attr->eth_virt = 0; 1130 goto error; 1131 } 1132 } 1133 return 0; 1134 error: 1135 rc = (rc > 0) ? -rc : rc; 1136 return rc; 1137 } 1138 1139 /** 1140 * Query TIS transport domain from QP verbs object using DevX API. 1141 * 1142 * @param[in] qp 1143 * Pointer to verbs QP returned by ibv_create_qp . 1144 * @param[in] tis_num 1145 * TIS number of TIS to query. 1146 * @param[out] tis_td 1147 * Pointer to TIS transport domain variable, to be set by the routine. 1148 * 1149 * @return 1150 * 0 on success, a negative value otherwise. 1151 */ 1152 int 1153 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1154 uint32_t *tis_td) 1155 { 1156 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1157 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1158 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1159 int rc; 1160 void *tis_ctx; 1161 1162 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1163 MLX5_SET(query_tis_in, in, tisn, tis_num); 1164 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1165 if (rc) { 1166 DRV_LOG(ERR, "Failed to query QP using DevX"); 1167 return -rc; 1168 }; 1169 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1170 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1171 return 0; 1172 #else 1173 (void)qp; 1174 (void)tis_num; 1175 (void)tis_td; 1176 return -ENOTSUP; 1177 #endif 1178 } 1179 1180 /** 1181 * Fill WQ data for DevX API command. 1182 * Utility function for use when creating DevX objects containing a WQ. 1183 * 1184 * @param[in] wq_ctx 1185 * Pointer to WQ context to fill with data. 1186 * @param [in] wq_attr 1187 * Pointer to WQ attributes structure to fill in WQ context. 1188 */ 1189 static void 1190 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1191 { 1192 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1193 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1194 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1195 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1196 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1197 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1198 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1199 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1200 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1201 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1202 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1203 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1204 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1205 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1206 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1207 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1208 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1209 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1210 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1211 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1212 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1213 wq_attr->log_hairpin_num_packets); 1214 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1215 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1216 wq_attr->single_wqe_log_num_of_strides); 1217 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1218 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1219 wq_attr->single_stride_log_num_of_bytes); 1220 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1221 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1222 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1223 } 1224 1225 /** 1226 * Create RQ using DevX API. 1227 * 1228 * @param[in] ctx 1229 * Context returned from mlx5 open_device() glue function. 1230 * @param [in] rq_attr 1231 * Pointer to create RQ attributes structure. 1232 * @param [in] socket 1233 * CPU socket ID for allocations. 1234 * 1235 * @return 1236 * The DevX object created, NULL otherwise and rte_errno is set. 1237 */ 1238 struct mlx5_devx_obj * 1239 mlx5_devx_cmd_create_rq(void *ctx, 1240 struct mlx5_devx_create_rq_attr *rq_attr, 1241 int socket) 1242 { 1243 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1244 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1245 void *rq_ctx, *wq_ctx; 1246 struct mlx5_devx_wq_attr *wq_attr; 1247 struct mlx5_devx_obj *rq = NULL; 1248 1249 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1250 if (!rq) { 1251 DRV_LOG(ERR, "Failed to allocate RQ data"); 1252 rte_errno = ENOMEM; 1253 return NULL; 1254 } 1255 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1256 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1257 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1258 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1259 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1260 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1261 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1262 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1263 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1264 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1265 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1266 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1267 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1268 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1269 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1270 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1271 wq_attr = &rq_attr->wq_attr; 1272 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1273 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1274 out, sizeof(out)); 1275 if (!rq->obj) { 1276 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1277 rte_errno = errno; 1278 mlx5_free(rq); 1279 return NULL; 1280 } 1281 rq->id = MLX5_GET(create_rq_out, out, rqn); 1282 return rq; 1283 } 1284 1285 /** 1286 * Modify RQ using DevX API. 1287 * 1288 * @param[in] rq 1289 * Pointer to RQ object structure. 1290 * @param [in] rq_attr 1291 * Pointer to modify RQ attributes structure. 1292 * 1293 * @return 1294 * 0 on success, a negative errno value otherwise and rte_errno is set. 1295 */ 1296 int 1297 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1298 struct mlx5_devx_modify_rq_attr *rq_attr) 1299 { 1300 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1301 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1302 void *rq_ctx, *wq_ctx; 1303 int ret; 1304 1305 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1306 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1307 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1308 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1309 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1310 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1311 if (rq_attr->modify_bitmask & 1312 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1313 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1314 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1315 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1316 if (rq_attr->modify_bitmask & 1317 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1318 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1319 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1320 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1321 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1322 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1323 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1324 } 1325 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1326 out, sizeof(out)); 1327 if (ret) { 1328 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1329 rte_errno = errno; 1330 return -errno; 1331 } 1332 return ret; 1333 } 1334 1335 /** 1336 * Create RMP using DevX API. 1337 * 1338 * @param[in] ctx 1339 * Context returned from mlx5 open_device() glue function. 1340 * @param [in] rmp_attr 1341 * Pointer to create RMP attributes structure. 1342 * @param [in] socket 1343 * CPU socket ID for allocations. 1344 * 1345 * @return 1346 * The DevX object created, NULL otherwise and rte_errno is set. 1347 */ 1348 struct mlx5_devx_obj * 1349 mlx5_devx_cmd_create_rmp(void *ctx, 1350 struct mlx5_devx_create_rmp_attr *rmp_attr, 1351 int socket) 1352 { 1353 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0}; 1354 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0}; 1355 void *rmp_ctx, *wq_ctx; 1356 struct mlx5_devx_wq_attr *wq_attr; 1357 struct mlx5_devx_obj *rmp = NULL; 1358 1359 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket); 1360 if (!rmp) { 1361 DRV_LOG(ERR, "Failed to allocate RMP data"); 1362 rte_errno = ENOMEM; 1363 return NULL; 1364 } 1365 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP); 1366 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx); 1367 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state); 1368 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe, 1369 rmp_attr->basic_cyclic_rcv_wqe); 1370 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq); 1371 wq_attr = &rmp_attr->wq_attr; 1372 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1373 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1374 sizeof(out)); 1375 if (!rmp->obj) { 1376 DRV_LOG(ERR, "Failed to create RMP using DevX"); 1377 rte_errno = errno; 1378 mlx5_free(rmp); 1379 return NULL; 1380 } 1381 rmp->id = MLX5_GET(create_rmp_out, out, rmpn); 1382 return rmp; 1383 } 1384 1385 /* 1386 * Create TIR using DevX API. 1387 * 1388 * @param[in] ctx 1389 * Context returned from mlx5 open_device() glue function. 1390 * @param [in] tir_attr 1391 * Pointer to TIR attributes structure. 1392 * 1393 * @return 1394 * The DevX object created, NULL otherwise and rte_errno is set. 1395 */ 1396 struct mlx5_devx_obj * 1397 mlx5_devx_cmd_create_tir(void *ctx, 1398 struct mlx5_devx_tir_attr *tir_attr) 1399 { 1400 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1401 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1402 void *tir_ctx, *outer, *inner, *rss_key; 1403 struct mlx5_devx_obj *tir = NULL; 1404 1405 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1406 if (!tir) { 1407 DRV_LOG(ERR, "Failed to allocate TIR data"); 1408 rte_errno = ENOMEM; 1409 return NULL; 1410 } 1411 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1412 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1413 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1414 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1415 tir_attr->lro_timeout_period_usecs); 1416 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1417 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1418 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1419 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1420 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1421 tir_attr->tunneled_offload_en); 1422 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1423 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1424 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1425 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1426 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1427 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1428 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1429 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1430 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1431 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1432 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1433 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1434 tir_attr->rx_hash_field_selector_outer.selected_fields); 1435 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1436 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1437 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1438 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1439 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1440 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1441 tir_attr->rx_hash_field_selector_inner.selected_fields); 1442 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1443 out, sizeof(out)); 1444 if (!tir->obj) { 1445 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1446 rte_errno = errno; 1447 mlx5_free(tir); 1448 return NULL; 1449 } 1450 tir->id = MLX5_GET(create_tir_out, out, tirn); 1451 return tir; 1452 } 1453 1454 /** 1455 * Modify TIR using DevX API. 1456 * 1457 * @param[in] tir 1458 * Pointer to TIR DevX object structure. 1459 * @param [in] modify_tir_attr 1460 * Pointer to TIR modification attributes structure. 1461 * 1462 * @return 1463 * 0 on success, a negative errno value otherwise and rte_errno is set. 1464 */ 1465 int 1466 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1467 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1468 { 1469 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1470 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1471 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1472 void *tir_ctx; 1473 int ret; 1474 1475 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1476 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1477 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1478 modify_tir_attr->modify_bitmask); 1479 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1480 if (modify_tir_attr->modify_bitmask & 1481 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1482 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1483 tir_attr->lro_timeout_period_usecs); 1484 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1485 tir_attr->lro_enable_mask); 1486 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1487 tir_attr->lro_max_msg_sz); 1488 } 1489 if (modify_tir_attr->modify_bitmask & 1490 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1491 MLX5_SET(tirc, tir_ctx, indirect_table, 1492 tir_attr->indirect_table); 1493 if (modify_tir_attr->modify_bitmask & 1494 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1495 int i; 1496 void *outer, *inner; 1497 1498 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1499 tir_attr->rx_hash_symmetric); 1500 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1501 for (i = 0; i < 10; i++) { 1502 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1503 tir_attr->rx_hash_toeplitz_key[i]); 1504 } 1505 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1506 rx_hash_field_selector_outer); 1507 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1508 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1509 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1510 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1511 MLX5_SET 1512 (rx_hash_field_select, outer, selected_fields, 1513 tir_attr->rx_hash_field_selector_outer.selected_fields); 1514 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1515 rx_hash_field_selector_inner); 1516 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1517 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1518 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1519 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1520 MLX5_SET 1521 (rx_hash_field_select, inner, selected_fields, 1522 tir_attr->rx_hash_field_selector_inner.selected_fields); 1523 } 1524 if (modify_tir_attr->modify_bitmask & 1525 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1526 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1527 } 1528 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1529 out, sizeof(out)); 1530 if (ret) { 1531 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1532 rte_errno = errno; 1533 return -errno; 1534 } 1535 return ret; 1536 } 1537 1538 /** 1539 * Create RQT using DevX API. 1540 * 1541 * @param[in] ctx 1542 * Context returned from mlx5 open_device() glue function. 1543 * @param [in] rqt_attr 1544 * Pointer to RQT attributes structure. 1545 * 1546 * @return 1547 * The DevX object created, NULL otherwise and rte_errno is set. 1548 */ 1549 struct mlx5_devx_obj * 1550 mlx5_devx_cmd_create_rqt(void *ctx, 1551 struct mlx5_devx_rqt_attr *rqt_attr) 1552 { 1553 uint32_t *in = NULL; 1554 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1555 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1556 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1557 void *rqt_ctx; 1558 struct mlx5_devx_obj *rqt = NULL; 1559 int i; 1560 1561 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1562 if (!in) { 1563 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1564 rte_errno = ENOMEM; 1565 return NULL; 1566 } 1567 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1568 if (!rqt) { 1569 DRV_LOG(ERR, "Failed to allocate RQT data"); 1570 rte_errno = ENOMEM; 1571 mlx5_free(in); 1572 return NULL; 1573 } 1574 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1575 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1576 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1577 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1578 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1579 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1580 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1581 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1582 mlx5_free(in); 1583 if (!rqt->obj) { 1584 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1585 rte_errno = errno; 1586 mlx5_free(rqt); 1587 return NULL; 1588 } 1589 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1590 return rqt; 1591 } 1592 1593 /** 1594 * Modify RQT using DevX API. 1595 * 1596 * @param[in] rqt 1597 * Pointer to RQT DevX object structure. 1598 * @param [in] rqt_attr 1599 * Pointer to RQT attributes structure. 1600 * 1601 * @return 1602 * 0 on success, a negative errno value otherwise and rte_errno is set. 1603 */ 1604 int 1605 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1606 struct mlx5_devx_rqt_attr *rqt_attr) 1607 { 1608 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1609 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1610 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1611 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1612 void *rqt_ctx; 1613 int i; 1614 int ret; 1615 1616 if (!in) { 1617 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1618 rte_errno = ENOMEM; 1619 return -ENOMEM; 1620 } 1621 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1622 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1623 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1624 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1625 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1626 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1627 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1628 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1629 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1630 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1631 mlx5_free(in); 1632 if (ret) { 1633 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1634 rte_errno = errno; 1635 return -rte_errno; 1636 } 1637 return ret; 1638 } 1639 1640 /** 1641 * Create SQ using DevX API. 1642 * 1643 * @param[in] ctx 1644 * Context returned from mlx5 open_device() glue function. 1645 * @param [in] sq_attr 1646 * Pointer to SQ attributes structure. 1647 * @param [in] socket 1648 * CPU socket ID for allocations. 1649 * 1650 * @return 1651 * The DevX object created, NULL otherwise and rte_errno is set. 1652 **/ 1653 struct mlx5_devx_obj * 1654 mlx5_devx_cmd_create_sq(void *ctx, 1655 struct mlx5_devx_create_sq_attr *sq_attr) 1656 { 1657 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1658 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1659 void *sq_ctx; 1660 void *wq_ctx; 1661 struct mlx5_devx_wq_attr *wq_attr; 1662 struct mlx5_devx_obj *sq = NULL; 1663 1664 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1665 if (!sq) { 1666 DRV_LOG(ERR, "Failed to allocate SQ data"); 1667 rte_errno = ENOMEM; 1668 return NULL; 1669 } 1670 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1671 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1672 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1673 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1674 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1675 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1676 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1677 sq_attr->allow_multi_pkt_send_wqe); 1678 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1679 sq_attr->min_wqe_inline_mode); 1680 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1681 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1682 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1683 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1684 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1685 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1686 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1687 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1688 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1689 sq_attr->packet_pacing_rate_limit_index); 1690 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1691 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1692 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1693 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1694 wq_attr = &sq_attr->wq_attr; 1695 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1696 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1697 out, sizeof(out)); 1698 if (!sq->obj) { 1699 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1700 rte_errno = errno; 1701 mlx5_free(sq); 1702 return NULL; 1703 } 1704 sq->id = MLX5_GET(create_sq_out, out, sqn); 1705 return sq; 1706 } 1707 1708 /** 1709 * Modify SQ using DevX API. 1710 * 1711 * @param[in] sq 1712 * Pointer to SQ object structure. 1713 * @param [in] sq_attr 1714 * Pointer to SQ attributes structure. 1715 * 1716 * @return 1717 * 0 on success, a negative errno value otherwise and rte_errno is set. 1718 */ 1719 int 1720 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1721 struct mlx5_devx_modify_sq_attr *sq_attr) 1722 { 1723 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1724 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1725 void *sq_ctx; 1726 int ret; 1727 1728 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1729 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1730 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1731 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1732 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1733 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1734 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1735 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1736 out, sizeof(out)); 1737 if (ret) { 1738 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1739 rte_errno = errno; 1740 return -rte_errno; 1741 } 1742 return ret; 1743 } 1744 1745 /** 1746 * Create TIS using DevX API. 1747 * 1748 * @param[in] ctx 1749 * Context returned from mlx5 open_device() glue function. 1750 * @param [in] tis_attr 1751 * Pointer to TIS attributes structure. 1752 * 1753 * @return 1754 * The DevX object created, NULL otherwise and rte_errno is set. 1755 */ 1756 struct mlx5_devx_obj * 1757 mlx5_devx_cmd_create_tis(void *ctx, 1758 struct mlx5_devx_tis_attr *tis_attr) 1759 { 1760 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1761 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1762 struct mlx5_devx_obj *tis = NULL; 1763 void *tis_ctx; 1764 1765 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1766 if (!tis) { 1767 DRV_LOG(ERR, "Failed to allocate TIS object"); 1768 rte_errno = ENOMEM; 1769 return NULL; 1770 } 1771 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1772 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1773 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1774 tis_attr->strict_lag_tx_port_affinity); 1775 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1776 tis_attr->lag_tx_port_affinity); 1777 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1778 MLX5_SET(tisc, tis_ctx, transport_domain, 1779 tis_attr->transport_domain); 1780 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1781 out, sizeof(out)); 1782 if (!tis->obj) { 1783 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1784 rte_errno = errno; 1785 mlx5_free(tis); 1786 return NULL; 1787 } 1788 tis->id = MLX5_GET(create_tis_out, out, tisn); 1789 return tis; 1790 } 1791 1792 /** 1793 * Create transport domain using DevX API. 1794 * 1795 * @param[in] ctx 1796 * Context returned from mlx5 open_device() glue function. 1797 * @return 1798 * The DevX object created, NULL otherwise and rte_errno is set. 1799 */ 1800 struct mlx5_devx_obj * 1801 mlx5_devx_cmd_create_td(void *ctx) 1802 { 1803 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1804 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1805 struct mlx5_devx_obj *td = NULL; 1806 1807 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1808 if (!td) { 1809 DRV_LOG(ERR, "Failed to allocate TD object"); 1810 rte_errno = ENOMEM; 1811 return NULL; 1812 } 1813 MLX5_SET(alloc_transport_domain_in, in, opcode, 1814 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1815 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1816 out, sizeof(out)); 1817 if (!td->obj) { 1818 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1819 rte_errno = errno; 1820 mlx5_free(td); 1821 return NULL; 1822 } 1823 td->id = MLX5_GET(alloc_transport_domain_out, out, 1824 transport_domain); 1825 return td; 1826 } 1827 1828 /** 1829 * Dump all flows to file. 1830 * 1831 * @param[in] fdb_domain 1832 * FDB domain. 1833 * @param[in] rx_domain 1834 * RX domain. 1835 * @param[in] tx_domain 1836 * TX domain. 1837 * @param[out] file 1838 * Pointer to file stream. 1839 * 1840 * @return 1841 * 0 on success, a negative value otherwise. 1842 */ 1843 int 1844 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1845 void *rx_domain __rte_unused, 1846 void *tx_domain __rte_unused, FILE *file __rte_unused) 1847 { 1848 int ret = 0; 1849 1850 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1851 if (fdb_domain) { 1852 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1853 if (ret) 1854 return ret; 1855 } 1856 MLX5_ASSERT(rx_domain); 1857 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1858 if (ret) 1859 return ret; 1860 MLX5_ASSERT(tx_domain); 1861 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1862 #else 1863 ret = ENOTSUP; 1864 #endif 1865 return -ret; 1866 } 1867 1868 int 1869 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1870 FILE *file __rte_unused) 1871 { 1872 int ret = 0; 1873 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1874 if (rule_info) 1875 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1876 #else 1877 ret = ENOTSUP; 1878 #endif 1879 return -ret; 1880 } 1881 1882 /* 1883 * Create CQ using DevX API. 1884 * 1885 * @param[in] ctx 1886 * Context returned from mlx5 open_device() glue function. 1887 * @param [in] attr 1888 * Pointer to CQ attributes structure. 1889 * 1890 * @return 1891 * The DevX object created, NULL otherwise and rte_errno is set. 1892 */ 1893 struct mlx5_devx_obj * 1894 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1895 { 1896 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1897 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1898 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1899 sizeof(*cq_obj), 1900 0, SOCKET_ID_ANY); 1901 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1902 1903 if (!cq_obj) { 1904 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1905 rte_errno = ENOMEM; 1906 return NULL; 1907 } 1908 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1909 if (attr->db_umem_valid) { 1910 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1911 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1912 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1913 } else { 1914 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1915 } 1916 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1917 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1918 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1919 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1920 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1921 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1922 MLX5_SET(cqc, cqctx, log_page_size, 1923 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1924 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1925 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1926 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1927 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1928 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1929 attr->mini_cqe_res_format_ext); 1930 if (attr->q_umem_valid) { 1931 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1932 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1933 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1934 attr->q_umem_offset); 1935 } 1936 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1937 sizeof(out)); 1938 if (!cq_obj->obj) { 1939 rte_errno = errno; 1940 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1941 mlx5_free(cq_obj); 1942 return NULL; 1943 } 1944 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1945 return cq_obj; 1946 } 1947 1948 /** 1949 * Create VIRTQ using DevX API. 1950 * 1951 * @param[in] ctx 1952 * Context returned from mlx5 open_device() glue function. 1953 * @param [in] attr 1954 * Pointer to VIRTQ attributes structure. 1955 * 1956 * @return 1957 * The DevX object created, NULL otherwise and rte_errno is set. 1958 */ 1959 struct mlx5_devx_obj * 1960 mlx5_devx_cmd_create_virtq(void *ctx, 1961 struct mlx5_devx_virtq_attr *attr) 1962 { 1963 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1964 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1965 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1966 sizeof(*virtq_obj), 1967 0, SOCKET_ID_ANY); 1968 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1969 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1970 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1971 1972 if (!virtq_obj) { 1973 DRV_LOG(ERR, "Failed to allocate virtq data."); 1974 rte_errno = ENOMEM; 1975 return NULL; 1976 } 1977 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1978 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1979 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1980 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1981 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1982 attr->hw_available_index); 1983 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1984 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1985 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1986 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1987 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1988 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1989 attr->virtio_version_1_0); 1990 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1991 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1992 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1993 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1994 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1995 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1996 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1997 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1998 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1999 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 2000 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 2001 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 2002 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 2003 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 2004 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 2005 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 2006 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 2007 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 2008 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 2009 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 2010 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 2011 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 2012 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 2013 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2014 sizeof(out)); 2015 if (!virtq_obj->obj) { 2016 rte_errno = errno; 2017 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 2018 mlx5_free(virtq_obj); 2019 return NULL; 2020 } 2021 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2022 return virtq_obj; 2023 } 2024 2025 /** 2026 * Modify VIRTQ using DevX API. 2027 * 2028 * @param[in] virtq_obj 2029 * Pointer to virtq object structure. 2030 * @param [in] attr 2031 * Pointer to modify virtq attributes structure. 2032 * 2033 * @return 2034 * 0 on success, a negative errno value otherwise and rte_errno is set. 2035 */ 2036 int 2037 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 2038 struct mlx5_devx_virtq_attr *attr) 2039 { 2040 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 2041 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2042 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 2043 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 2044 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 2045 int ret; 2046 2047 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2048 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 2049 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2050 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2051 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2052 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 2053 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 2054 switch (attr->type) { 2055 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 2056 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 2057 break; 2058 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 2059 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 2060 attr->dirty_bitmap_mkey); 2061 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 2062 attr->dirty_bitmap_addr); 2063 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 2064 attr->dirty_bitmap_size); 2065 break; 2066 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 2067 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 2068 attr->dirty_bitmap_dump_enable); 2069 break; 2070 default: 2071 rte_errno = EINVAL; 2072 return -rte_errno; 2073 } 2074 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 2075 out, sizeof(out)); 2076 if (ret) { 2077 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2078 rte_errno = errno; 2079 return -rte_errno; 2080 } 2081 return ret; 2082 } 2083 2084 /** 2085 * Query VIRTQ using DevX API. 2086 * 2087 * @param[in] virtq_obj 2088 * Pointer to virtq object structure. 2089 * @param [in/out] attr 2090 * Pointer to virtq attributes structure. 2091 * 2092 * @return 2093 * 0 on success, a negative errno value otherwise and rte_errno is set. 2094 */ 2095 int 2096 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 2097 struct mlx5_devx_virtq_attr *attr) 2098 { 2099 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2100 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 2101 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 2102 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 2103 int ret; 2104 2105 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2106 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2107 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2108 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 2109 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 2110 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 2111 out, sizeof(out)); 2112 if (ret) { 2113 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 2114 rte_errno = errno; 2115 return -errno; 2116 } 2117 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 2118 hw_available_index); 2119 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 2120 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 2121 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 2122 virtio_q_context.error_type); 2123 return ret; 2124 } 2125 2126 /** 2127 * Create QP using DevX API. 2128 * 2129 * @param[in] ctx 2130 * Context returned from mlx5 open_device() glue function. 2131 * @param [in] attr 2132 * Pointer to QP attributes structure. 2133 * 2134 * @return 2135 * The DevX object created, NULL otherwise and rte_errno is set. 2136 */ 2137 struct mlx5_devx_obj * 2138 mlx5_devx_cmd_create_qp(void *ctx, 2139 struct mlx5_devx_qp_attr *attr) 2140 { 2141 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 2142 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 2143 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 2144 sizeof(*qp_obj), 2145 0, SOCKET_ID_ANY); 2146 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 2147 2148 if (!qp_obj) { 2149 DRV_LOG(ERR, "Failed to allocate QP data."); 2150 rte_errno = ENOMEM; 2151 return NULL; 2152 } 2153 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 2154 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 2155 MLX5_SET(qpc, qpc, pd, attr->pd); 2156 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 2157 MLX5_SET(qpc, qpc, user_index, attr->user_index); 2158 if (attr->uar_index) { 2159 if (attr->mmo) { 2160 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, 2161 in, qpc_extension_and_pas_list); 2162 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, 2163 qpc_ext_and_pas_list, qpc_data_extension); 2164 2165 MLX5_SET(create_qp_in, in, qpc_ext, 1); 2166 MLX5_SET(qpc_extension, qpc_ext, mmo, 1); 2167 } 2168 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2169 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 2170 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 2171 MLX5_SET(qpc, qpc, log_page_size, 2172 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 2173 if (attr->num_of_send_wqbbs) { 2174 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs)); 2175 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 2176 MLX5_SET(qpc, qpc, log_sq_size, 2177 rte_log2_u32(attr->num_of_send_wqbbs)); 2178 } else { 2179 MLX5_SET(qpc, qpc, no_sq, 1); 2180 } 2181 if (attr->num_of_receive_wqes) { 2182 MLX5_ASSERT(RTE_IS_POWER_OF_2( 2183 attr->num_of_receive_wqes)); 2184 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2185 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2186 MLX5_LOG_RQ_STRIDE_SHIFT); 2187 MLX5_SET(qpc, qpc, log_rq_size, 2188 rte_log2_u32(attr->num_of_receive_wqes)); 2189 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2190 } else { 2191 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2192 } 2193 if (attr->dbr_umem_valid) { 2194 MLX5_SET(qpc, qpc, dbr_umem_valid, 2195 attr->dbr_umem_valid); 2196 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2197 } 2198 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2199 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2200 attr->wq_umem_offset); 2201 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2202 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2203 } else { 2204 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2205 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2206 MLX5_SET(qpc, qpc, no_sq, 1); 2207 } 2208 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2209 sizeof(out)); 2210 if (!qp_obj->obj) { 2211 rte_errno = errno; 2212 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 2213 mlx5_free(qp_obj); 2214 return NULL; 2215 } 2216 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2217 return qp_obj; 2218 } 2219 2220 /** 2221 * Modify QP using DevX API. 2222 * Currently supports only force loop-back QP. 2223 * 2224 * @param[in] qp 2225 * Pointer to QP object structure. 2226 * @param [in] qp_st_mod_op 2227 * The QP state modification operation. 2228 * @param [in] remote_qp_id 2229 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2230 * 2231 * @return 2232 * 0 on success, a negative errno value otherwise and rte_errno is set. 2233 */ 2234 int 2235 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2236 uint32_t remote_qp_id) 2237 { 2238 union { 2239 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2240 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2241 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2242 } in; 2243 union { 2244 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2245 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2246 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2247 } out; 2248 void *qpc; 2249 int ret; 2250 unsigned int inlen; 2251 unsigned int outlen; 2252 2253 memset(&in, 0, sizeof(in)); 2254 memset(&out, 0, sizeof(out)); 2255 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2256 switch (qp_st_mod_op) { 2257 case MLX5_CMD_OP_RST2INIT_QP: 2258 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2259 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2260 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2261 MLX5_SET(qpc, qpc, rre, 1); 2262 MLX5_SET(qpc, qpc, rwe, 1); 2263 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2264 inlen = sizeof(in.rst2init); 2265 outlen = sizeof(out.rst2init); 2266 break; 2267 case MLX5_CMD_OP_INIT2RTR_QP: 2268 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2269 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2270 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2271 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2272 MLX5_SET(qpc, qpc, mtu, 1); 2273 MLX5_SET(qpc, qpc, log_msg_max, 30); 2274 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2275 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2276 inlen = sizeof(in.init2rtr); 2277 outlen = sizeof(out.init2rtr); 2278 break; 2279 case MLX5_CMD_OP_RTR2RTS_QP: 2280 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2281 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2282 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 2283 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2284 MLX5_SET(qpc, qpc, retry_count, 7); 2285 MLX5_SET(qpc, qpc, rnr_retry, 7); 2286 inlen = sizeof(in.rtr2rts); 2287 outlen = sizeof(out.rtr2rts); 2288 break; 2289 default: 2290 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2291 qp_st_mod_op); 2292 rte_errno = EINVAL; 2293 return -rte_errno; 2294 } 2295 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2296 if (ret) { 2297 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2298 rte_errno = errno; 2299 return -rte_errno; 2300 } 2301 return ret; 2302 } 2303 2304 struct mlx5_devx_obj * 2305 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2306 { 2307 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2308 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2309 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2310 sizeof(*couners_obj), 0, 2311 SOCKET_ID_ANY); 2312 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2313 2314 if (!couners_obj) { 2315 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2316 rte_errno = ENOMEM; 2317 return NULL; 2318 } 2319 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2320 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2321 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2322 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2323 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2324 sizeof(out)); 2325 if (!couners_obj->obj) { 2326 rte_errno = errno; 2327 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2328 " DevX."); 2329 mlx5_free(couners_obj); 2330 return NULL; 2331 } 2332 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2333 return couners_obj; 2334 } 2335 2336 int 2337 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2338 struct mlx5_devx_virtio_q_couners_attr *attr) 2339 { 2340 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2341 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2342 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2343 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2344 virtio_q_counters); 2345 int ret; 2346 2347 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2348 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2349 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2350 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2351 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2352 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2353 sizeof(out)); 2354 if (ret) { 2355 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2356 rte_errno = errno; 2357 return -errno; 2358 } 2359 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2360 received_desc); 2361 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2362 completed_desc); 2363 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2364 error_cqes); 2365 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2366 bad_desc_errors); 2367 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2368 exceed_max_chain); 2369 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2370 invalid_buffer); 2371 return ret; 2372 } 2373 2374 /** 2375 * Create general object of type FLOW_HIT_ASO using DevX API. 2376 * 2377 * @param[in] ctx 2378 * Context returned from mlx5 open_device() glue function. 2379 * @param [in] pd 2380 * PD value to associate the FLOW_HIT_ASO object with. 2381 * 2382 * @return 2383 * The DevX object created, NULL otherwise and rte_errno is set. 2384 */ 2385 struct mlx5_devx_obj * 2386 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2387 { 2388 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2389 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2390 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2391 void *ptr = NULL; 2392 2393 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2394 0, SOCKET_ID_ANY); 2395 if (!flow_hit_aso_obj) { 2396 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2397 rte_errno = ENOMEM; 2398 return NULL; 2399 } 2400 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2401 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2402 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2403 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2404 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2405 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2406 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2407 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2408 out, sizeof(out)); 2409 if (!flow_hit_aso_obj->obj) { 2410 rte_errno = errno; 2411 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2412 mlx5_free(flow_hit_aso_obj); 2413 return NULL; 2414 } 2415 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2416 return flow_hit_aso_obj; 2417 } 2418 2419 /* 2420 * Create PD using DevX API. 2421 * 2422 * @param[in] ctx 2423 * Context returned from mlx5 open_device() glue function. 2424 * 2425 * @return 2426 * The DevX object created, NULL otherwise and rte_errno is set. 2427 */ 2428 struct mlx5_devx_obj * 2429 mlx5_devx_cmd_alloc_pd(void *ctx) 2430 { 2431 struct mlx5_devx_obj *ppd = 2432 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2433 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2434 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2435 2436 if (!ppd) { 2437 DRV_LOG(ERR, "Failed to allocate PD data."); 2438 rte_errno = ENOMEM; 2439 return NULL; 2440 } 2441 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2442 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2443 out, sizeof(out)); 2444 if (!ppd->obj) { 2445 mlx5_free(ppd); 2446 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2447 rte_errno = errno; 2448 return NULL; 2449 } 2450 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2451 return ppd; 2452 } 2453 2454 /** 2455 * Create general object of type FLOW_METER_ASO using DevX API. 2456 * 2457 * @param[in] ctx 2458 * Context returned from mlx5 open_device() glue function. 2459 * @param [in] pd 2460 * PD value to associate the FLOW_METER_ASO object with. 2461 * @param [in] log_obj_size 2462 * log_obj_size define to allocate number of 2 * meters 2463 * in one FLOW_METER_ASO object. 2464 * 2465 * @return 2466 * The DevX object created, NULL otherwise and rte_errno is set. 2467 */ 2468 struct mlx5_devx_obj * 2469 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2470 uint32_t log_obj_size) 2471 { 2472 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2473 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2474 struct mlx5_devx_obj *flow_meter_aso_obj; 2475 void *ptr; 2476 2477 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2478 sizeof(*flow_meter_aso_obj), 2479 0, SOCKET_ID_ANY); 2480 if (!flow_meter_aso_obj) { 2481 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2482 rte_errno = ENOMEM; 2483 return NULL; 2484 } 2485 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2486 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2487 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2488 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2489 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2490 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2491 log_obj_size); 2492 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2493 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2494 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2495 ctx, in, sizeof(in), 2496 out, sizeof(out)); 2497 if (!flow_meter_aso_obj->obj) { 2498 rte_errno = errno; 2499 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2500 mlx5_free(flow_meter_aso_obj); 2501 return NULL; 2502 } 2503 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2504 out, obj_id); 2505 return flow_meter_aso_obj; 2506 } 2507 2508 /* 2509 * Create general object of type CONN_TRACK_OFFLOAD using DevX API. 2510 * 2511 * @param[in] ctx 2512 * Context returned from mlx5 open_device() glue function. 2513 * @param [in] pd 2514 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with. 2515 * @param [in] log_obj_size 2516 * log_obj_size to allocate its power of 2 * objects 2517 * in one CONN_TRACK_OFFLOAD bulk allocation. 2518 * 2519 * @return 2520 * The DevX object created, NULL otherwise and rte_errno is set. 2521 */ 2522 struct mlx5_devx_obj * 2523 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd, 2524 uint32_t log_obj_size) 2525 { 2526 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0}; 2527 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2528 struct mlx5_devx_obj *ct_aso_obj; 2529 void *ptr; 2530 2531 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj), 2532 0, SOCKET_ID_ANY); 2533 if (!ct_aso_obj) { 2534 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object."); 2535 rte_errno = ENOMEM; 2536 return NULL; 2537 } 2538 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr); 2539 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2540 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2541 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2542 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD); 2543 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size); 2544 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload); 2545 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd); 2546 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2547 out, sizeof(out)); 2548 if (!ct_aso_obj->obj) { 2549 rte_errno = errno; 2550 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX."); 2551 mlx5_free(ct_aso_obj); 2552 return NULL; 2553 } 2554 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2555 return ct_aso_obj; 2556 } 2557 2558 /** 2559 * Create general object of type GENEVE TLV option using DevX API. 2560 * 2561 * @param[in] ctx 2562 * Context returned from mlx5 open_device() glue function. 2563 * @param [in] class 2564 * TLV option variable value of class 2565 * @param [in] type 2566 * TLV option variable value of type 2567 * @param [in] len 2568 * TLV option variable value of len 2569 * 2570 * @return 2571 * The DevX object created, NULL otherwise and rte_errno is set. 2572 */ 2573 struct mlx5_devx_obj * 2574 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2575 uint16_t class, uint8_t type, uint8_t len) 2576 { 2577 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2578 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2579 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2580 sizeof(*geneve_tlv_opt_obj), 2581 0, SOCKET_ID_ANY); 2582 2583 if (!geneve_tlv_opt_obj) { 2584 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2585 rte_errno = ENOMEM; 2586 return NULL; 2587 } 2588 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2589 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2590 geneve_tlv_opt); 2591 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2592 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2593 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2594 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2595 MLX5_SET(geneve_tlv_option, opt, option_class, 2596 rte_be_to_cpu_16(class)); 2597 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2598 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2599 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2600 sizeof(in), out, sizeof(out)); 2601 if (!geneve_tlv_opt_obj->obj) { 2602 rte_errno = errno; 2603 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2604 "Obj using DevX."); 2605 mlx5_free(geneve_tlv_opt_obj); 2606 return NULL; 2607 } 2608 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2609 return geneve_tlv_opt_obj; 2610 } 2611 2612 int 2613 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2614 { 2615 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2616 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2617 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2618 int rc; 2619 void *rq_ctx; 2620 2621 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2622 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2623 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2624 if (rc) { 2625 rte_errno = errno; 2626 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2627 "rc = %d, errno = %d.", rc, errno); 2628 return -rc; 2629 }; 2630 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2631 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2632 return 0; 2633 #else 2634 (void)wq; 2635 (void)counter_set_id; 2636 return -ENOTSUP; 2637 #endif 2638 } 2639 2640 /* 2641 * Allocate queue counters via devx interface. 2642 * 2643 * @param[in] ctx 2644 * Context returned from mlx5 open_device() glue function. 2645 * 2646 * @return 2647 * Pointer to counter object on success, a NULL value otherwise and 2648 * rte_errno is set. 2649 */ 2650 struct mlx5_devx_obj * 2651 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2652 { 2653 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2654 SOCKET_ID_ANY); 2655 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2656 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2657 2658 if (!dcs) { 2659 rte_errno = ENOMEM; 2660 return NULL; 2661 } 2662 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2663 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2664 sizeof(out)); 2665 if (!dcs->obj) { 2666 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2667 "%d.", errno); 2668 rte_errno = errno; 2669 mlx5_free(dcs); 2670 return NULL; 2671 } 2672 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2673 return dcs; 2674 } 2675 2676 /** 2677 * Query queue counters values. 2678 * 2679 * @param[in] dcs 2680 * devx object of the queue counter set. 2681 * @param[in] clear 2682 * Whether hardware should clear the counters after the query or not. 2683 * @param[out] out_of_buffers 2684 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2685 * 2686 * @return 2687 * 0 on success, a negative value otherwise. 2688 */ 2689 int 2690 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2691 uint32_t *out_of_buffers) 2692 { 2693 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2694 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2695 int rc; 2696 2697 MLX5_SET(query_q_counter_in, in, opcode, 2698 MLX5_CMD_OP_QUERY_Q_COUNTER); 2699 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2700 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2701 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2702 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2703 sizeof(out)); 2704 if (rc) { 2705 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2706 rte_errno = rc; 2707 return -rc; 2708 } 2709 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2710 return 0; 2711 } 2712 2713 /** 2714 * Create general object of type DEK using DevX API. 2715 * 2716 * @param[in] ctx 2717 * Context returned from mlx5 open_device() glue function. 2718 * @param [in] attr 2719 * Pointer to DEK attributes structure. 2720 * 2721 * @return 2722 * The DevX object created, NULL otherwise and rte_errno is set. 2723 */ 2724 struct mlx5_devx_obj * 2725 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2726 { 2727 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2728 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2729 struct mlx5_devx_obj *dek_obj = NULL; 2730 void *ptr = NULL, *key_addr = NULL; 2731 2732 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2733 0, SOCKET_ID_ANY); 2734 if (dek_obj == NULL) { 2735 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2736 rte_errno = ENOMEM; 2737 return NULL; 2738 } 2739 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2740 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2741 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2742 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2743 MLX5_GENERAL_OBJ_TYPE_DEK); 2744 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2745 MLX5_SET(dek, ptr, key_size, attr->key_size); 2746 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2747 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2748 MLX5_SET(dek, ptr, pd, attr->pd); 2749 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2750 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2751 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2752 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2753 out, sizeof(out)); 2754 if (dek_obj->obj == NULL) { 2755 rte_errno = errno; 2756 DRV_LOG(ERR, "Failed to create DEK obj using DevX."); 2757 mlx5_free(dek_obj); 2758 return NULL; 2759 } 2760 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2761 return dek_obj; 2762 } 2763 2764 /** 2765 * Create general object of type IMPORT_KEK using DevX API. 2766 * 2767 * @param[in] ctx 2768 * Context returned from mlx5 open_device() glue function. 2769 * @param [in] attr 2770 * Pointer to IMPORT_KEK attributes structure. 2771 * 2772 * @return 2773 * The DevX object created, NULL otherwise and rte_errno is set. 2774 */ 2775 struct mlx5_devx_obj * 2776 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2777 struct mlx5_devx_import_kek_attr *attr) 2778 { 2779 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2780 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2781 struct mlx5_devx_obj *import_kek_obj = NULL; 2782 void *ptr = NULL, *key_addr = NULL; 2783 2784 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2785 0, SOCKET_ID_ANY); 2786 if (import_kek_obj == NULL) { 2787 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2788 rte_errno = ENOMEM; 2789 return NULL; 2790 } 2791 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2792 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2793 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2794 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2795 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2796 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2797 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2798 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2799 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2800 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2801 out, sizeof(out)); 2802 if (import_kek_obj->obj == NULL) { 2803 rte_errno = errno; 2804 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); 2805 mlx5_free(import_kek_obj); 2806 return NULL; 2807 } 2808 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2809 return import_kek_obj; 2810 } 2811 2812 /** 2813 * Create general object of type CREDENTIAL using DevX API. 2814 * 2815 * @param[in] ctx 2816 * Context returned from mlx5 open_device() glue function. 2817 * @param [in] attr 2818 * Pointer to CREDENTIAL attributes structure. 2819 * 2820 * @return 2821 * The DevX object created, NULL otherwise and rte_errno is set. 2822 */ 2823 struct mlx5_devx_obj * 2824 mlx5_devx_cmd_create_credential_obj(void *ctx, 2825 struct mlx5_devx_credential_attr *attr) 2826 { 2827 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2828 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2829 struct mlx5_devx_obj *credential_obj = NULL; 2830 void *ptr = NULL, *credential_addr = NULL; 2831 2832 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2833 0, SOCKET_ID_ANY); 2834 if (credential_obj == NULL) { 2835 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2836 rte_errno = ENOMEM; 2837 return NULL; 2838 } 2839 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2840 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2841 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2842 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2843 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2844 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2845 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2846 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2847 memcpy(credential_addr, (void *)(attr->credential), 2848 MLX5_CRYPTO_CREDENTIAL_SIZE); 2849 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2850 out, sizeof(out)); 2851 if (credential_obj->obj == NULL) { 2852 rte_errno = errno; 2853 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); 2854 mlx5_free(credential_obj); 2855 return NULL; 2856 } 2857 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2858 return credential_obj; 2859 } 2860 2861 /** 2862 * Create general object of type CRYPTO_LOGIN using DevX API. 2863 * 2864 * @param[in] ctx 2865 * Context returned from mlx5 open_device() glue function. 2866 * @param [in] attr 2867 * Pointer to CRYPTO_LOGIN attributes structure. 2868 * 2869 * @return 2870 * The DevX object created, NULL otherwise and rte_errno is set. 2871 */ 2872 struct mlx5_devx_obj * 2873 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2874 struct mlx5_devx_crypto_login_attr *attr) 2875 { 2876 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2877 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2878 struct mlx5_devx_obj *crypto_login_obj = NULL; 2879 void *ptr = NULL, *credential_addr = NULL; 2880 2881 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2882 0, SOCKET_ID_ANY); 2883 if (crypto_login_obj == NULL) { 2884 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2885 rte_errno = ENOMEM; 2886 return NULL; 2887 } 2888 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2889 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2890 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2891 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2892 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2893 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2894 MLX5_SET(crypto_login, ptr, credential_pointer, 2895 attr->credential_pointer); 2896 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2897 attr->session_import_kek_ptr); 2898 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2899 memcpy(credential_addr, (void *)(attr->credential), 2900 MLX5_CRYPTO_CREDENTIAL_SIZE); 2901 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2902 out, sizeof(out)); 2903 if (crypto_login_obj->obj == NULL) { 2904 rte_errno = errno; 2905 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); 2906 mlx5_free(crypto_login_obj); 2907 return NULL; 2908 } 2909 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2910 return crypto_login_obj; 2911 } 2912 2913 /** 2914 * Query LAG context. 2915 * 2916 * @param[in] ctx 2917 * Pointer to ibv_context, returned from mlx5dv_open_device. 2918 * @param[out] lag_ctx 2919 * Pointer to struct mlx5_devx_lag_context, to be set by the routine. 2920 * 2921 * @return 2922 * 0 on success, a negative value otherwise. 2923 */ 2924 int 2925 mlx5_devx_cmd_query_lag(void *ctx, 2926 struct mlx5_devx_lag_context *lag_ctx) 2927 { 2928 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0}; 2929 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0}; 2930 void *lctx; 2931 int rc; 2932 2933 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG); 2934 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 2935 if (rc) 2936 goto error; 2937 lctx = MLX5_ADDR_OF(query_lag_out, out, context); 2938 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx, 2939 fdb_selection_mode); 2940 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx, 2941 port_select_mode); 2942 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state); 2943 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx, 2944 tx_remap_affinity_2); 2945 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx, 2946 tx_remap_affinity_1); 2947 return 0; 2948 error: 2949 rc = (rc > 0) ? -rc : rc; 2950 return rc; 2951 } 2952