1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 7 #include <rte_errno.h> 8 #include <rte_malloc.h> 9 #include <rte_eal_paging.h> 10 11 #include "mlx5_prm.h" 12 #include "mlx5_devx_cmds.h" 13 #include "mlx5_common_log.h" 14 #include "mlx5_malloc.h" 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_BYTES(access_register_out) + 57 sizeof(uint32_t) * dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Perform write access to the registers. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param[in] reg_id 83 * Register identifier according to the PRM. 84 * @param[in] arg 85 * Register access auxiliary parameter according to the PRM. 86 * @param[out] data 87 * Pointer to the buffer containing data to write. 88 * @param[in] dw_cnt 89 * Buffer size in double words (32bit units). 90 * 91 * @return 92 * 0 on success, a negative value otherwise. 93 */ 94 int 95 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg, 96 uint32_t *data, uint32_t dw_cnt) 97 { 98 uint32_t in[MLX5_ST_SZ_DW(access_register_in) + 99 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 100 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0}; 101 int status, rc; 102 void *ptr; 103 104 MLX5_ASSERT(data && dw_cnt); 105 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 106 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 107 DRV_LOG(ERR, "Data to write exceeds max size"); 108 return -1; 109 } 110 MLX5_SET(access_register_in, in, opcode, 111 MLX5_CMD_OP_ACCESS_REGISTER_USER); 112 MLX5_SET(access_register_in, in, op_mod, 113 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE); 114 MLX5_SET(access_register_in, in, register_id, reg_id); 115 MLX5_SET(access_register_in, in, argument, arg); 116 ptr = MLX5_ADDR_OF(access_register_in, in, register_data); 117 memcpy(ptr, data, dw_cnt * sizeof(uint32_t)); 118 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 119 120 rc = mlx5_glue->devx_general_cmd(ctx, in, 121 MLX5_ST_SZ_BYTES(access_register_in) + 122 dw_cnt * sizeof(uint32_t), 123 out, sizeof(out)); 124 if (rc) 125 goto error; 126 status = MLX5_GET(access_register_out, out, status); 127 if (status) { 128 int syndrome = MLX5_GET(access_register_out, out, syndrome); 129 130 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, " 131 "status %x, syndrome = %x", 132 reg_id, status, syndrome); 133 return -1; 134 } 135 return 0; 136 error: 137 rc = (rc > 0) ? -rc : rc; 138 return rc; 139 } 140 141 /** 142 * Allocate flow counters via devx interface. 143 * 144 * @param[in] ctx 145 * Context returned from mlx5 open_device() glue function. 146 * @param dcs 147 * Pointer to counters properties structure to be filled by the routine. 148 * @param bulk_n_128 149 * Bulk counter numbers in 128 counters units. 150 * 151 * @return 152 * Pointer to counter object on success, a negative value otherwise and 153 * rte_errno is set. 154 */ 155 struct mlx5_devx_obj * 156 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 157 { 158 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 159 0, SOCKET_ID_ANY); 160 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 161 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 162 163 if (!dcs) { 164 rte_errno = ENOMEM; 165 return NULL; 166 } 167 MLX5_SET(alloc_flow_counter_in, in, opcode, 168 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 169 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 170 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 171 sizeof(in), out, sizeof(out)); 172 if (!dcs->obj) { 173 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 174 rte_errno = errno; 175 mlx5_free(dcs); 176 return NULL; 177 } 178 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 179 return dcs; 180 } 181 182 /** 183 * Query flow counters values. 184 * 185 * @param[in] dcs 186 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 187 * @param[in] clear 188 * Whether hardware should clear the counters after the query or not. 189 * @param[in] n_counters 190 * 0 in case of 1 counter to read, otherwise the counter number to read. 191 * @param pkts 192 * The number of packets that matched the flow. 193 * @param bytes 194 * The number of bytes that matched the flow. 195 * @param mkey 196 * The mkey key for batch query. 197 * @param addr 198 * The address in the mkey range for batch query. 199 * @param cmd_comp 200 * The completion object for asynchronous batch query. 201 * @param async_id 202 * The ID to be returned in the asynchronous batch query response. 203 * 204 * @return 205 * 0 on success, a negative value otherwise. 206 */ 207 int 208 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 209 int clear, uint32_t n_counters, 210 uint64_t *pkts, uint64_t *bytes, 211 uint32_t mkey, void *addr, 212 void *cmd_comp, 213 uint64_t async_id) 214 { 215 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 216 MLX5_ST_SZ_BYTES(traffic_counter); 217 uint32_t out[out_len]; 218 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 219 void *stats; 220 int rc; 221 222 MLX5_SET(query_flow_counter_in, in, opcode, 223 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 224 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 225 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 226 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 227 228 if (n_counters) { 229 MLX5_SET(query_flow_counter_in, in, num_of_counters, 230 n_counters); 231 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 232 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 233 MLX5_SET64(query_flow_counter_in, in, address, 234 (uint64_t)(uintptr_t)addr); 235 } 236 if (!cmd_comp) 237 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 238 out_len); 239 else 240 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 241 out_len, async_id, 242 cmd_comp); 243 if (rc) { 244 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 245 rte_errno = rc; 246 return -rc; 247 } 248 if (!n_counters) { 249 stats = MLX5_ADDR_OF(query_flow_counter_out, 250 out, flow_statistics); 251 *pkts = MLX5_GET64(traffic_counter, stats, packets); 252 *bytes = MLX5_GET64(traffic_counter, stats, octets); 253 } 254 return 0; 255 } 256 257 /** 258 * Create a new mkey. 259 * 260 * @param[in] ctx 261 * Context returned from mlx5 open_device() glue function. 262 * @param[in] attr 263 * Attributes of the requested mkey. 264 * 265 * @return 266 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 267 * is set. 268 */ 269 struct mlx5_devx_obj * 270 mlx5_devx_cmd_mkey_create(void *ctx, 271 struct mlx5_devx_mkey_attr *attr) 272 { 273 struct mlx5_klm *klm_array = attr->klm_array; 274 int klm_num = attr->klm_num; 275 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 276 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 277 uint32_t in[in_size_dw]; 278 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 279 void *mkc; 280 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 281 0, SOCKET_ID_ANY); 282 size_t pgsize; 283 uint32_t translation_size; 284 285 if (!mkey) { 286 rte_errno = ENOMEM; 287 return NULL; 288 } 289 memset(in, 0, in_size_dw * 4); 290 pgsize = rte_mem_page_size(); 291 if (pgsize == (size_t)-1) { 292 mlx5_free(mkey); 293 DRV_LOG(ERR, "Failed to get page size"); 294 rte_errno = ENOMEM; 295 return NULL; 296 } 297 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 298 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 299 if (klm_num > 0) { 300 int i; 301 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 302 klm_pas_mtt); 303 translation_size = RTE_ALIGN(klm_num, 4); 304 for (i = 0; i < klm_num; i++) { 305 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 306 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 307 MLX5_SET64(klm, klm, address, klm_array[i].address); 308 klm += MLX5_ST_SZ_BYTES(klm); 309 } 310 for (; i < (int)translation_size; i++) { 311 MLX5_SET(klm, klm, mkey, 0x0); 312 MLX5_SET64(klm, klm, address, 0x0); 313 klm += MLX5_ST_SZ_BYTES(klm); 314 } 315 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 316 MLX5_MKC_ACCESS_MODE_KLM_FBS : 317 MLX5_MKC_ACCESS_MODE_KLM); 318 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 319 } else { 320 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 321 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 322 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 323 } 324 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 325 translation_size); 326 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 327 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 328 MLX5_SET(mkc, mkc, lw, 0x1); 329 MLX5_SET(mkc, mkc, lr, 0x1); 330 if (attr->set_remote_rw) { 331 MLX5_SET(mkc, mkc, rw, 0x1); 332 MLX5_SET(mkc, mkc, rr, 0x1); 333 } 334 MLX5_SET(mkc, mkc, qpn, 0xffffff); 335 MLX5_SET(mkc, mkc, pd, attr->pd); 336 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 337 MLX5_SET(mkc, mkc, umr_en, attr->umr_en); 338 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 339 MLX5_SET(mkc, mkc, relaxed_ordering_write, 340 attr->relaxed_ordering_write); 341 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 342 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 343 MLX5_SET64(mkc, mkc, len, attr->size); 344 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en); 345 if (attr->crypto_en) { 346 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en); 347 MLX5_SET(mkc, mkc, bsf_octword_size, 4); 348 } 349 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 350 sizeof(out)); 351 if (!mkey->obj) { 352 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d", 353 klm_num ? "an in" : "a ", errno); 354 rte_errno = errno; 355 mlx5_free(mkey); 356 return NULL; 357 } 358 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 359 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 360 return mkey; 361 } 362 363 /** 364 * Get status of devx command response. 365 * Mainly used for asynchronous commands. 366 * 367 * @param[in] out 368 * The out response buffer. 369 * 370 * @return 371 * 0 on success, non-zero value otherwise. 372 */ 373 int 374 mlx5_devx_get_out_command_status(void *out) 375 { 376 int status; 377 378 if (!out) 379 return -EINVAL; 380 status = MLX5_GET(query_flow_counter_out, out, status); 381 if (status) { 382 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 383 384 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 385 syndrome); 386 } 387 return status; 388 } 389 390 /** 391 * Destroy any object allocated by a Devx API. 392 * 393 * @param[in] obj 394 * Pointer to a general object. 395 * 396 * @return 397 * 0 on success, a negative value otherwise. 398 */ 399 int 400 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 401 { 402 int ret; 403 404 if (!obj) 405 return 0; 406 ret = mlx5_glue->devx_obj_destroy(obj->obj); 407 mlx5_free(obj); 408 return ret; 409 } 410 411 /** 412 * Query NIC vport context. 413 * Fills minimal inline attribute. 414 * 415 * @param[in] ctx 416 * ibv contexts returned from mlx5dv_open_device. 417 * @param[in] vport 418 * vport index 419 * @param[out] attr 420 * Attributes device values. 421 * 422 * @return 423 * 0 on success, a negative value otherwise. 424 */ 425 static int 426 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 427 unsigned int vport, 428 struct mlx5_hca_attr *attr) 429 { 430 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 431 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 432 void *vctx; 433 int status, syndrome, rc; 434 435 /* Query NIC vport context to determine inline mode. */ 436 MLX5_SET(query_nic_vport_context_in, in, opcode, 437 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 438 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 439 if (vport) 440 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 441 rc = mlx5_glue->devx_general_cmd(ctx, 442 in, sizeof(in), 443 out, sizeof(out)); 444 if (rc) 445 goto error; 446 status = MLX5_GET(query_nic_vport_context_out, out, status); 447 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 448 if (status) { 449 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 450 "status %x, syndrome = %x", status, syndrome); 451 return -1; 452 } 453 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 454 nic_vport_context); 455 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 456 min_wqe_inline_mode); 457 return 0; 458 error: 459 rc = (rc > 0) ? -rc : rc; 460 return rc; 461 } 462 463 /** 464 * Query NIC vDPA attributes. 465 * 466 * @param[in] ctx 467 * Context returned from mlx5 open_device() glue function. 468 * @param[out] vdpa_attr 469 * vDPA Attributes structure to fill. 470 */ 471 static void 472 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 473 struct mlx5_hca_vdpa_attr *vdpa_attr) 474 { 475 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 476 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 477 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 478 int status, syndrome, rc; 479 480 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 481 MLX5_SET(query_hca_cap_in, in, op_mod, 482 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 483 MLX5_HCA_CAP_OPMOD_GET_CUR); 484 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 485 status = MLX5_GET(query_hca_cap_out, out, status); 486 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 487 if (rc || status) { 488 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 489 " status %x, syndrome = %x", status, syndrome); 490 vdpa_attr->valid = 0; 491 } else { 492 vdpa_attr->valid = 1; 493 vdpa_attr->desc_tunnel_offload_type = 494 MLX5_GET(virtio_emulation_cap, hcattr, 495 desc_tunnel_offload_type); 496 vdpa_attr->eth_frame_offload_type = 497 MLX5_GET(virtio_emulation_cap, hcattr, 498 eth_frame_offload_type); 499 vdpa_attr->virtio_version_1_0 = 500 MLX5_GET(virtio_emulation_cap, hcattr, 501 virtio_version_1_0); 502 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 503 tso_ipv4); 504 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 505 tso_ipv6); 506 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 507 tx_csum); 508 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 509 rx_csum); 510 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 511 event_mode); 512 vdpa_attr->virtio_queue_type = 513 MLX5_GET(virtio_emulation_cap, hcattr, 514 virtio_queue_type); 515 vdpa_attr->log_doorbell_stride = 516 MLX5_GET(virtio_emulation_cap, hcattr, 517 log_doorbell_stride); 518 vdpa_attr->log_doorbell_bar_size = 519 MLX5_GET(virtio_emulation_cap, hcattr, 520 log_doorbell_bar_size); 521 vdpa_attr->doorbell_bar_offset = 522 MLX5_GET64(virtio_emulation_cap, hcattr, 523 doorbell_bar_offset); 524 vdpa_attr->max_num_virtio_queues = 525 MLX5_GET(virtio_emulation_cap, hcattr, 526 max_num_virtio_queues); 527 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 528 umem_1_buffer_param_a); 529 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 530 umem_1_buffer_param_b); 531 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 532 umem_2_buffer_param_a); 533 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 534 umem_2_buffer_param_b); 535 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 536 umem_3_buffer_param_a); 537 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 538 umem_3_buffer_param_b); 539 } 540 } 541 542 int 543 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 544 uint32_t ids[], uint32_t num) 545 { 546 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 547 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 548 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 549 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 550 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 551 int ret; 552 uint32_t idx = 0; 553 uint32_t i; 554 555 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 556 rte_errno = EINVAL; 557 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 558 return -rte_errno; 559 } 560 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 561 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 562 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 563 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 564 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 565 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 566 out, sizeof(out)); 567 if (ret) { 568 rte_errno = ret; 569 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 570 (void *)flex_obj); 571 return -rte_errno; 572 } 573 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 574 void *s_off = (void *)((char *)sample + i * 575 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 576 uint32_t en; 577 578 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 579 flow_match_sample_en); 580 if (!en) 581 continue; 582 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 583 flow_match_sample_field_id); 584 } 585 if (num != idx) { 586 rte_errno = EINVAL; 587 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 588 return -rte_errno; 589 } 590 return ret; 591 } 592 593 594 struct mlx5_devx_obj * 595 mlx5_devx_cmd_create_flex_parser(void *ctx, 596 struct mlx5_devx_graph_node_attr *data) 597 { 598 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 599 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 600 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 601 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 602 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 603 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 604 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 605 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 606 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 607 uint32_t i; 608 609 if (!parse_flex_obj) { 610 DRV_LOG(ERR, "Failed to allocate flex parser data."); 611 rte_errno = ENOMEM; 612 return NULL; 613 } 614 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 615 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 616 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 617 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 618 MLX5_SET(parse_graph_flex, flex, header_length_mode, 619 data->header_length_mode); 620 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 621 data->header_length_base_value); 622 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 623 data->header_length_field_offset); 624 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 625 data->header_length_field_shift); 626 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 627 data->header_length_field_mask); 628 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 629 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 630 void *s_off = (void *)((char *)sample + i * 631 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 632 633 if (!s->flow_match_sample_en) 634 continue; 635 MLX5_SET(parse_graph_flow_match_sample, s_off, 636 flow_match_sample_en, !!s->flow_match_sample_en); 637 MLX5_SET(parse_graph_flow_match_sample, s_off, 638 flow_match_sample_field_offset, 639 s->flow_match_sample_field_offset); 640 MLX5_SET(parse_graph_flow_match_sample, s_off, 641 flow_match_sample_offset_mode, 642 s->flow_match_sample_offset_mode); 643 MLX5_SET(parse_graph_flow_match_sample, s_off, 644 flow_match_sample_field_offset_mask, 645 s->flow_match_sample_field_offset_mask); 646 MLX5_SET(parse_graph_flow_match_sample, s_off, 647 flow_match_sample_field_offset_shift, 648 s->flow_match_sample_field_offset_shift); 649 MLX5_SET(parse_graph_flow_match_sample, s_off, 650 flow_match_sample_field_base_offset, 651 s->flow_match_sample_field_base_offset); 652 MLX5_SET(parse_graph_flow_match_sample, s_off, 653 flow_match_sample_tunnel_mode, 654 s->flow_match_sample_tunnel_mode); 655 } 656 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 657 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 658 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 659 void *in_off = (void *)((char *)in_arc + i * 660 MLX5_ST_SZ_BYTES(parse_graph_arc)); 661 void *out_off = (void *)((char *)out_arc + i * 662 MLX5_ST_SZ_BYTES(parse_graph_arc)); 663 664 if (ia->arc_parse_graph_node != 0) { 665 MLX5_SET(parse_graph_arc, in_off, 666 compare_condition_value, 667 ia->compare_condition_value); 668 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 669 ia->start_inner_tunnel); 670 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 671 ia->arc_parse_graph_node); 672 MLX5_SET(parse_graph_arc, in_off, 673 parse_graph_node_handle, 674 ia->parse_graph_node_handle); 675 } 676 if (oa->arc_parse_graph_node != 0) { 677 MLX5_SET(parse_graph_arc, out_off, 678 compare_condition_value, 679 oa->compare_condition_value); 680 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 681 oa->start_inner_tunnel); 682 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 683 oa->arc_parse_graph_node); 684 MLX5_SET(parse_graph_arc, out_off, 685 parse_graph_node_handle, 686 oa->parse_graph_node_handle); 687 } 688 } 689 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 690 out, sizeof(out)); 691 if (!parse_flex_obj->obj) { 692 rte_errno = errno; 693 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 694 "by using DevX."); 695 mlx5_free(parse_flex_obj); 696 return NULL; 697 } 698 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 699 return parse_flex_obj; 700 } 701 702 /** 703 * Query HCA attributes. 704 * Using those attributes we can check on run time if the device 705 * is having the required capabilities. 706 * 707 * @param[in] ctx 708 * Context returned from mlx5 open_device() glue function. 709 * @param[out] attr 710 * Attributes device values. 711 * 712 * @return 713 * 0 on success, a negative value otherwise. 714 */ 715 int 716 mlx5_devx_cmd_query_hca_attr(void *ctx, 717 struct mlx5_hca_attr *attr) 718 { 719 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 720 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 721 void *hcattr; 722 int status, syndrome, rc, i; 723 uint64_t general_obj_types_supported = 0; 724 725 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 726 MLX5_SET(query_hca_cap_in, in, op_mod, 727 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 728 MLX5_HCA_CAP_OPMOD_GET_CUR); 729 730 rc = mlx5_glue->devx_general_cmd(ctx, 731 in, sizeof(in), out, sizeof(out)); 732 if (rc) 733 goto error; 734 status = MLX5_GET(query_hca_cap_out, out, status); 735 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 736 if (status) { 737 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 738 "status %x, syndrome = %x", status, syndrome); 739 return -1; 740 } 741 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 742 attr->flow_counter_bulk_alloc_bitmap = 743 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 744 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 745 flow_counters_dump); 746 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 747 log_max_rqt_size); 748 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 749 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 750 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 751 log_max_hairpin_queues); 752 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 753 log_max_hairpin_wq_data_sz); 754 attr->log_max_hairpin_num_packets = MLX5_GET 755 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 756 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 757 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 758 relaxed_ordering_write); 759 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 760 relaxed_ordering_read); 761 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 762 access_register_user); 763 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 764 eth_net_offloads); 765 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 766 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 767 flex_parser_protocols); 768 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 769 max_geneve_tlv_options); 770 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 771 max_geneve_tlv_option_data_len); 772 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 773 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr, 774 general_obj_types) & 775 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO); 776 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 777 general_obj_types) & 778 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 779 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 780 general_obj_types) & 781 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 782 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 783 general_obj_types) & 784 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 785 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 786 wqe_index_ignore_cap); 787 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 788 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 789 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 790 log_max_static_sq_wq); 791 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 792 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 793 device_frequency_khz); 794 attr->scatter_fcs_w_decap_disable = 795 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 796 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce); 797 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format); 798 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format); 799 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 800 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 801 regexp_num_of_engines); 802 /* Read the general_obj_types bitmap and extract the relevant bits. */ 803 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr, 804 general_obj_types); 805 attr->vdpa.valid = !!(general_obj_types_supported & 806 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 807 attr->vdpa.queue_counters_valid = 808 !!(general_obj_types_supported & 809 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 810 attr->parse_graph_flex_node = 811 !!(general_obj_types_supported & 812 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 813 attr->flow_hit_aso = !!(general_obj_types_supported & 814 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 815 attr->geneve_tlv_opt = !!(general_obj_types_supported & 816 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 817 attr->dek = !!(general_obj_types_supported & 818 MLX5_GENERAL_OBJ_TYPES_CAP_DEK); 819 attr->import_kek = !!(general_obj_types_supported & 820 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK); 821 attr->credential = !!(general_obj_types_supported & 822 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL); 823 attr->crypto_login = !!(general_obj_types_supported & 824 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN); 825 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */ 826 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 827 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 828 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 829 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 830 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 831 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 832 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 833 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 834 attr->reg_c_preserve = 835 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 836 attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo); 837 attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress); 838 attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress); 839 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 840 compress_min_block_size); 841 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 842 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 843 log_compress_mmo_size); 844 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 845 log_decompress_mmo_size); 846 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); 847 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, 848 mini_cqe_resp_flow_tag); 849 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, 850 mini_cqe_resp_l3_l4_tag); 851 attr->umr_indirect_mkey_disabled = 852 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); 853 attr->umr_modify_entity_size_disabled = 854 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); 855 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto); 856 if (attr->crypto) 857 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts); 858 if (attr->qos.sup) { 859 MLX5_SET(query_hca_cap_in, in, op_mod, 860 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 861 MLX5_HCA_CAP_OPMOD_GET_CUR); 862 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 863 out, sizeof(out)); 864 if (rc) 865 goto error; 866 if (status) { 867 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 868 " status %x, syndrome = %x", status, syndrome); 869 return -1; 870 } 871 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 872 attr->qos.flow_meter_old = 873 MLX5_GET(qos_cap, hcattr, flow_meter_old); 874 attr->qos.log_max_flow_meter = 875 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 876 attr->qos.flow_meter_reg_c_ids = 877 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 878 attr->qos.flow_meter = 879 MLX5_GET(qos_cap, hcattr, flow_meter); 880 attr->qos.packet_pacing = 881 MLX5_GET(qos_cap, hcattr, packet_pacing); 882 attr->qos.wqe_rate_pp = 883 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 884 if (attr->qos.flow_meter_aso_sup) { 885 attr->qos.log_meter_aso_granularity = 886 MLX5_GET(qos_cap, hcattr, 887 log_meter_aso_granularity); 888 attr->qos.log_meter_aso_max_alloc = 889 MLX5_GET(qos_cap, hcattr, 890 log_meter_aso_max_alloc); 891 attr->qos.log_max_num_meter_aso = 892 MLX5_GET(qos_cap, hcattr, 893 log_max_num_meter_aso); 894 } 895 } 896 if (attr->vdpa.valid) 897 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 898 if (!attr->eth_net_offloads) 899 return 0; 900 901 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 902 memset(in, 0, sizeof(in)); 903 memset(out, 0, sizeof(out)); 904 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 905 MLX5_SET(query_hca_cap_in, in, op_mod, 906 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 907 MLX5_HCA_CAP_OPMOD_GET_CUR); 908 909 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 910 if (rc) 911 goto error; 912 status = MLX5_GET(query_hca_cap_out, out, status); 913 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 914 if (status) { 915 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 916 "status %x, syndrome = %x", status, syndrome); 917 attr->log_max_ft_sampler_num = 0; 918 return -1; 919 } 920 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 921 attr->log_max_ft_sampler_num = 922 MLX5_GET(flow_table_nic_cap, 923 hcattr, flow_table_properties.log_max_ft_sampler_num); 924 925 /* Query HCA offloads for Ethernet protocol. */ 926 memset(in, 0, sizeof(in)); 927 memset(out, 0, sizeof(out)); 928 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 929 MLX5_SET(query_hca_cap_in, in, op_mod, 930 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 931 MLX5_HCA_CAP_OPMOD_GET_CUR); 932 933 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 934 if (rc) { 935 attr->eth_net_offloads = 0; 936 goto error; 937 } 938 status = MLX5_GET(query_hca_cap_out, out, status); 939 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 940 if (status) { 941 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 942 "status %x, syndrome = %x", status, syndrome); 943 attr->eth_net_offloads = 0; 944 return -1; 945 } 946 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 947 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 948 hcattr, wqe_vlan_insert); 949 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 950 lro_cap); 951 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 952 hcattr, tunnel_lro_gre); 953 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 954 hcattr, tunnel_lro_vxlan); 955 attr->lro_max_msg_sz_mode = MLX5_GET 956 (per_protocol_networking_offload_caps, 957 hcattr, lro_max_msg_sz_mode); 958 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 959 attr->lro_timer_supported_periods[i] = 960 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 961 lro_timer_supported_periods[i]); 962 } 963 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 964 hcattr, lro_min_mss_size); 965 attr->tunnel_stateless_geneve_rx = 966 MLX5_GET(per_protocol_networking_offload_caps, 967 hcattr, tunnel_stateless_geneve_rx); 968 attr->geneve_max_opt_len = 969 MLX5_GET(per_protocol_networking_offload_caps, 970 hcattr, max_geneve_opt_len); 971 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 972 hcattr, wqe_inline_mode); 973 attr->tunnel_stateless_gtp = MLX5_GET 974 (per_protocol_networking_offload_caps, 975 hcattr, tunnel_stateless_gtp); 976 attr->rss_ind_tbl_cap = MLX5_GET 977 (per_protocol_networking_offload_caps, 978 hcattr, rss_ind_tbl_cap); 979 /* Query HCA attribute for ROCE. */ 980 if (attr->roce) { 981 memset(in, 0, sizeof(in)); 982 memset(out, 0, sizeof(out)); 983 MLX5_SET(query_hca_cap_in, in, opcode, 984 MLX5_CMD_OP_QUERY_HCA_CAP); 985 MLX5_SET(query_hca_cap_in, in, op_mod, 986 MLX5_GET_HCA_CAP_OP_MOD_ROCE | 987 MLX5_HCA_CAP_OPMOD_GET_CUR); 988 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 989 out, sizeof(out)); 990 if (rc) 991 goto error; 992 status = MLX5_GET(query_hca_cap_out, out, status); 993 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 994 if (status) { 995 DRV_LOG(DEBUG, 996 "Failed to query devx HCA ROCE capabilities, " 997 "status %x, syndrome = %x", status, syndrome); 998 return -1; 999 } 1000 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 1001 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); 1002 } 1003 if (attr->eth_virt && 1004 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) { 1005 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 1006 if (rc) { 1007 attr->eth_virt = 0; 1008 goto error; 1009 } 1010 } 1011 return 0; 1012 error: 1013 rc = (rc > 0) ? -rc : rc; 1014 return rc; 1015 } 1016 1017 /** 1018 * Query TIS transport domain from QP verbs object using DevX API. 1019 * 1020 * @param[in] qp 1021 * Pointer to verbs QP returned by ibv_create_qp . 1022 * @param[in] tis_num 1023 * TIS number of TIS to query. 1024 * @param[out] tis_td 1025 * Pointer to TIS transport domain variable, to be set by the routine. 1026 * 1027 * @return 1028 * 0 on success, a negative value otherwise. 1029 */ 1030 int 1031 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 1032 uint32_t *tis_td) 1033 { 1034 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1035 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 1036 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 1037 int rc; 1038 void *tis_ctx; 1039 1040 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 1041 MLX5_SET(query_tis_in, in, tisn, tis_num); 1042 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 1043 if (rc) { 1044 DRV_LOG(ERR, "Failed to query QP using DevX"); 1045 return -rc; 1046 }; 1047 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 1048 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 1049 return 0; 1050 #else 1051 (void)qp; 1052 (void)tis_num; 1053 (void)tis_td; 1054 return -ENOTSUP; 1055 #endif 1056 } 1057 1058 /** 1059 * Fill WQ data for DevX API command. 1060 * Utility function for use when creating DevX objects containing a WQ. 1061 * 1062 * @param[in] wq_ctx 1063 * Pointer to WQ context to fill with data. 1064 * @param [in] wq_attr 1065 * Pointer to WQ attributes structure to fill in WQ context. 1066 */ 1067 static void 1068 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 1069 { 1070 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 1071 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 1072 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 1073 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 1074 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 1075 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 1076 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 1077 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 1078 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 1079 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 1080 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 1081 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 1082 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 1083 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 1084 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 1085 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 1086 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 1087 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 1088 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 1089 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 1090 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 1091 wq_attr->log_hairpin_num_packets); 1092 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 1093 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 1094 wq_attr->single_wqe_log_num_of_strides); 1095 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 1096 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 1097 wq_attr->single_stride_log_num_of_bytes); 1098 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 1099 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 1100 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 1101 } 1102 1103 /** 1104 * Create RQ using DevX API. 1105 * 1106 * @param[in] ctx 1107 * Context returned from mlx5 open_device() glue function. 1108 * @param [in] rq_attr 1109 * Pointer to create RQ attributes structure. 1110 * @param [in] socket 1111 * CPU socket ID for allocations. 1112 * 1113 * @return 1114 * The DevX object created, NULL otherwise and rte_errno is set. 1115 */ 1116 struct mlx5_devx_obj * 1117 mlx5_devx_cmd_create_rq(void *ctx, 1118 struct mlx5_devx_create_rq_attr *rq_attr, 1119 int socket) 1120 { 1121 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 1122 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 1123 void *rq_ctx, *wq_ctx; 1124 struct mlx5_devx_wq_attr *wq_attr; 1125 struct mlx5_devx_obj *rq = NULL; 1126 1127 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 1128 if (!rq) { 1129 DRV_LOG(ERR, "Failed to allocate RQ data"); 1130 rte_errno = ENOMEM; 1131 return NULL; 1132 } 1133 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 1134 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 1135 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 1136 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 1137 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1138 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1139 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 1140 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1141 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 1142 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 1143 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 1144 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1145 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1146 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1147 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format); 1148 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1149 wq_attr = &rq_attr->wq_attr; 1150 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1151 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1152 out, sizeof(out)); 1153 if (!rq->obj) { 1154 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1155 rte_errno = errno; 1156 mlx5_free(rq); 1157 return NULL; 1158 } 1159 rq->id = MLX5_GET(create_rq_out, out, rqn); 1160 return rq; 1161 } 1162 1163 /** 1164 * Modify RQ using DevX API. 1165 * 1166 * @param[in] rq 1167 * Pointer to RQ object structure. 1168 * @param [in] rq_attr 1169 * Pointer to modify RQ attributes structure. 1170 * 1171 * @return 1172 * 0 on success, a negative errno value otherwise and rte_errno is set. 1173 */ 1174 int 1175 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1176 struct mlx5_devx_modify_rq_attr *rq_attr) 1177 { 1178 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1179 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1180 void *rq_ctx, *wq_ctx; 1181 int ret; 1182 1183 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1184 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1185 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1186 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1187 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1188 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1189 if (rq_attr->modify_bitmask & 1190 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1191 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1192 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1193 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1194 if (rq_attr->modify_bitmask & 1195 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1196 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1197 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1198 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1199 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1200 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1201 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1202 } 1203 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1204 out, sizeof(out)); 1205 if (ret) { 1206 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1207 rte_errno = errno; 1208 return -errno; 1209 } 1210 return ret; 1211 } 1212 1213 /** 1214 * Create TIR using DevX API. 1215 * 1216 * @param[in] ctx 1217 * Context returned from mlx5 open_device() glue function. 1218 * @param [in] tir_attr 1219 * Pointer to TIR attributes structure. 1220 * 1221 * @return 1222 * The DevX object created, NULL otherwise and rte_errno is set. 1223 */ 1224 struct mlx5_devx_obj * 1225 mlx5_devx_cmd_create_tir(void *ctx, 1226 struct mlx5_devx_tir_attr *tir_attr) 1227 { 1228 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1229 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1230 void *tir_ctx, *outer, *inner, *rss_key; 1231 struct mlx5_devx_obj *tir = NULL; 1232 1233 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1234 if (!tir) { 1235 DRV_LOG(ERR, "Failed to allocate TIR data"); 1236 rte_errno = ENOMEM; 1237 return NULL; 1238 } 1239 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1240 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1241 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1242 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1243 tir_attr->lro_timeout_period_usecs); 1244 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1245 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1246 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1247 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1248 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1249 tir_attr->tunneled_offload_en); 1250 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1251 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1252 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1253 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1254 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1255 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1256 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1257 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1258 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1259 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1260 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1261 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1262 tir_attr->rx_hash_field_selector_outer.selected_fields); 1263 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1264 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1265 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1266 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1267 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1268 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1269 tir_attr->rx_hash_field_selector_inner.selected_fields); 1270 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1271 out, sizeof(out)); 1272 if (!tir->obj) { 1273 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1274 rte_errno = errno; 1275 mlx5_free(tir); 1276 return NULL; 1277 } 1278 tir->id = MLX5_GET(create_tir_out, out, tirn); 1279 return tir; 1280 } 1281 1282 /** 1283 * Modify TIR using DevX API. 1284 * 1285 * @param[in] tir 1286 * Pointer to TIR DevX object structure. 1287 * @param [in] modify_tir_attr 1288 * Pointer to TIR modification attributes structure. 1289 * 1290 * @return 1291 * 0 on success, a negative errno value otherwise and rte_errno is set. 1292 */ 1293 int 1294 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1295 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1296 { 1297 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1298 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1299 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1300 void *tir_ctx; 1301 int ret; 1302 1303 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1304 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1305 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1306 modify_tir_attr->modify_bitmask); 1307 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1308 if (modify_tir_attr->modify_bitmask & 1309 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1310 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1311 tir_attr->lro_timeout_period_usecs); 1312 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1313 tir_attr->lro_enable_mask); 1314 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1315 tir_attr->lro_max_msg_sz); 1316 } 1317 if (modify_tir_attr->modify_bitmask & 1318 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1319 MLX5_SET(tirc, tir_ctx, indirect_table, 1320 tir_attr->indirect_table); 1321 if (modify_tir_attr->modify_bitmask & 1322 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1323 int i; 1324 void *outer, *inner; 1325 1326 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1327 tir_attr->rx_hash_symmetric); 1328 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1329 for (i = 0; i < 10; i++) { 1330 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1331 tir_attr->rx_hash_toeplitz_key[i]); 1332 } 1333 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1334 rx_hash_field_selector_outer); 1335 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1336 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1337 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1338 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1339 MLX5_SET 1340 (rx_hash_field_select, outer, selected_fields, 1341 tir_attr->rx_hash_field_selector_outer.selected_fields); 1342 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1343 rx_hash_field_selector_inner); 1344 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1345 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1346 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1347 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1348 MLX5_SET 1349 (rx_hash_field_select, inner, selected_fields, 1350 tir_attr->rx_hash_field_selector_inner.selected_fields); 1351 } 1352 if (modify_tir_attr->modify_bitmask & 1353 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1354 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1355 } 1356 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1357 out, sizeof(out)); 1358 if (ret) { 1359 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1360 rte_errno = errno; 1361 return -errno; 1362 } 1363 return ret; 1364 } 1365 1366 /** 1367 * Create RQT using DevX API. 1368 * 1369 * @param[in] ctx 1370 * Context returned from mlx5 open_device() glue function. 1371 * @param [in] rqt_attr 1372 * Pointer to RQT attributes structure. 1373 * 1374 * @return 1375 * The DevX object created, NULL otherwise and rte_errno is set. 1376 */ 1377 struct mlx5_devx_obj * 1378 mlx5_devx_cmd_create_rqt(void *ctx, 1379 struct mlx5_devx_rqt_attr *rqt_attr) 1380 { 1381 uint32_t *in = NULL; 1382 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1383 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1384 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1385 void *rqt_ctx; 1386 struct mlx5_devx_obj *rqt = NULL; 1387 int i; 1388 1389 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1390 if (!in) { 1391 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1392 rte_errno = ENOMEM; 1393 return NULL; 1394 } 1395 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1396 if (!rqt) { 1397 DRV_LOG(ERR, "Failed to allocate RQT data"); 1398 rte_errno = ENOMEM; 1399 mlx5_free(in); 1400 return NULL; 1401 } 1402 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1403 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1404 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1405 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1406 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1407 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1408 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1409 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1410 mlx5_free(in); 1411 if (!rqt->obj) { 1412 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1413 rte_errno = errno; 1414 mlx5_free(rqt); 1415 return NULL; 1416 } 1417 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1418 return rqt; 1419 } 1420 1421 /** 1422 * Modify RQT using DevX API. 1423 * 1424 * @param[in] rqt 1425 * Pointer to RQT DevX object structure. 1426 * @param [in] rqt_attr 1427 * Pointer to RQT attributes structure. 1428 * 1429 * @return 1430 * 0 on success, a negative errno value otherwise and rte_errno is set. 1431 */ 1432 int 1433 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1434 struct mlx5_devx_rqt_attr *rqt_attr) 1435 { 1436 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1437 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1438 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1439 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1440 void *rqt_ctx; 1441 int i; 1442 int ret; 1443 1444 if (!in) { 1445 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1446 rte_errno = ENOMEM; 1447 return -ENOMEM; 1448 } 1449 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1450 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1451 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1452 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1453 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1454 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1455 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1456 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1457 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1458 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1459 mlx5_free(in); 1460 if (ret) { 1461 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1462 rte_errno = errno; 1463 return -rte_errno; 1464 } 1465 return ret; 1466 } 1467 1468 /** 1469 * Create SQ using DevX API. 1470 * 1471 * @param[in] ctx 1472 * Context returned from mlx5 open_device() glue function. 1473 * @param [in] sq_attr 1474 * Pointer to SQ attributes structure. 1475 * @param [in] socket 1476 * CPU socket ID for allocations. 1477 * 1478 * @return 1479 * The DevX object created, NULL otherwise and rte_errno is set. 1480 **/ 1481 struct mlx5_devx_obj * 1482 mlx5_devx_cmd_create_sq(void *ctx, 1483 struct mlx5_devx_create_sq_attr *sq_attr) 1484 { 1485 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1486 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1487 void *sq_ctx; 1488 void *wq_ctx; 1489 struct mlx5_devx_wq_attr *wq_attr; 1490 struct mlx5_devx_obj *sq = NULL; 1491 1492 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1493 if (!sq) { 1494 DRV_LOG(ERR, "Failed to allocate SQ data"); 1495 rte_errno = ENOMEM; 1496 return NULL; 1497 } 1498 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1499 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1500 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1501 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1502 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1503 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1504 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1505 sq_attr->allow_multi_pkt_send_wqe); 1506 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1507 sq_attr->min_wqe_inline_mode); 1508 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1509 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1510 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1511 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1512 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1513 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1514 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1515 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1516 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1517 sq_attr->packet_pacing_rate_limit_index); 1518 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1519 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1520 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format); 1521 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1522 wq_attr = &sq_attr->wq_attr; 1523 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1524 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1525 out, sizeof(out)); 1526 if (!sq->obj) { 1527 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1528 rte_errno = errno; 1529 mlx5_free(sq); 1530 return NULL; 1531 } 1532 sq->id = MLX5_GET(create_sq_out, out, sqn); 1533 return sq; 1534 } 1535 1536 /** 1537 * Modify SQ using DevX API. 1538 * 1539 * @param[in] sq 1540 * Pointer to SQ object structure. 1541 * @param [in] sq_attr 1542 * Pointer to SQ attributes structure. 1543 * 1544 * @return 1545 * 0 on success, a negative errno value otherwise and rte_errno is set. 1546 */ 1547 int 1548 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1549 struct mlx5_devx_modify_sq_attr *sq_attr) 1550 { 1551 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1552 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1553 void *sq_ctx; 1554 int ret; 1555 1556 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1557 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1558 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1559 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1560 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1561 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1562 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1563 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1564 out, sizeof(out)); 1565 if (ret) { 1566 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1567 rte_errno = errno; 1568 return -rte_errno; 1569 } 1570 return ret; 1571 } 1572 1573 /** 1574 * Create TIS using DevX API. 1575 * 1576 * @param[in] ctx 1577 * Context returned from mlx5 open_device() glue function. 1578 * @param [in] tis_attr 1579 * Pointer to TIS attributes structure. 1580 * 1581 * @return 1582 * The DevX object created, NULL otherwise and rte_errno is set. 1583 */ 1584 struct mlx5_devx_obj * 1585 mlx5_devx_cmd_create_tis(void *ctx, 1586 struct mlx5_devx_tis_attr *tis_attr) 1587 { 1588 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1589 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1590 struct mlx5_devx_obj *tis = NULL; 1591 void *tis_ctx; 1592 1593 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1594 if (!tis) { 1595 DRV_LOG(ERR, "Failed to allocate TIS object"); 1596 rte_errno = ENOMEM; 1597 return NULL; 1598 } 1599 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1600 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1601 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1602 tis_attr->strict_lag_tx_port_affinity); 1603 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1604 tis_attr->lag_tx_port_affinity); 1605 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1606 MLX5_SET(tisc, tis_ctx, transport_domain, 1607 tis_attr->transport_domain); 1608 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1609 out, sizeof(out)); 1610 if (!tis->obj) { 1611 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1612 rte_errno = errno; 1613 mlx5_free(tis); 1614 return NULL; 1615 } 1616 tis->id = MLX5_GET(create_tis_out, out, tisn); 1617 return tis; 1618 } 1619 1620 /** 1621 * Create transport domain using DevX API. 1622 * 1623 * @param[in] ctx 1624 * Context returned from mlx5 open_device() glue function. 1625 * @return 1626 * The DevX object created, NULL otherwise and rte_errno is set. 1627 */ 1628 struct mlx5_devx_obj * 1629 mlx5_devx_cmd_create_td(void *ctx) 1630 { 1631 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1632 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1633 struct mlx5_devx_obj *td = NULL; 1634 1635 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1636 if (!td) { 1637 DRV_LOG(ERR, "Failed to allocate TD object"); 1638 rte_errno = ENOMEM; 1639 return NULL; 1640 } 1641 MLX5_SET(alloc_transport_domain_in, in, opcode, 1642 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1643 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1644 out, sizeof(out)); 1645 if (!td->obj) { 1646 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1647 rte_errno = errno; 1648 mlx5_free(td); 1649 return NULL; 1650 } 1651 td->id = MLX5_GET(alloc_transport_domain_out, out, 1652 transport_domain); 1653 return td; 1654 } 1655 1656 /** 1657 * Dump all flows to file. 1658 * 1659 * @param[in] fdb_domain 1660 * FDB domain. 1661 * @param[in] rx_domain 1662 * RX domain. 1663 * @param[in] tx_domain 1664 * TX domain. 1665 * @param[out] file 1666 * Pointer to file stream. 1667 * 1668 * @return 1669 * 0 on success, a nagative value otherwise. 1670 */ 1671 int 1672 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1673 void *rx_domain __rte_unused, 1674 void *tx_domain __rte_unused, FILE *file __rte_unused) 1675 { 1676 int ret = 0; 1677 1678 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1679 if (fdb_domain) { 1680 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1681 if (ret) 1682 return ret; 1683 } 1684 MLX5_ASSERT(rx_domain); 1685 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1686 if (ret) 1687 return ret; 1688 MLX5_ASSERT(tx_domain); 1689 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1690 #else 1691 ret = ENOTSUP; 1692 #endif 1693 return -ret; 1694 } 1695 1696 int 1697 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused, 1698 FILE *file __rte_unused) 1699 { 1700 int ret = 0; 1701 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE 1702 if (rule_info) 1703 ret = mlx5_glue->dr_dump_rule(file, rule_info); 1704 #else 1705 ret = ENOTSUP; 1706 #endif 1707 return -ret; 1708 } 1709 1710 /* 1711 * Create CQ using DevX API. 1712 * 1713 * @param[in] ctx 1714 * Context returned from mlx5 open_device() glue function. 1715 * @param [in] attr 1716 * Pointer to CQ attributes structure. 1717 * 1718 * @return 1719 * The DevX object created, NULL otherwise and rte_errno is set. 1720 */ 1721 struct mlx5_devx_obj * 1722 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1723 { 1724 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1725 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1726 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1727 sizeof(*cq_obj), 1728 0, SOCKET_ID_ANY); 1729 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1730 1731 if (!cq_obj) { 1732 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1733 rte_errno = ENOMEM; 1734 return NULL; 1735 } 1736 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1737 if (attr->db_umem_valid) { 1738 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1739 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1740 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1741 } else { 1742 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1743 } 1744 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1745 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1746 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1747 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1748 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1749 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1750 MLX5_SET(cqc, cqctx, log_page_size, 1751 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1752 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1753 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1754 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1755 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1756 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1757 attr->mini_cqe_res_format_ext); 1758 if (attr->q_umem_valid) { 1759 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1760 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1761 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1762 attr->q_umem_offset); 1763 } 1764 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1765 sizeof(out)); 1766 if (!cq_obj->obj) { 1767 rte_errno = errno; 1768 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1769 mlx5_free(cq_obj); 1770 return NULL; 1771 } 1772 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1773 return cq_obj; 1774 } 1775 1776 /** 1777 * Create VIRTQ using DevX API. 1778 * 1779 * @param[in] ctx 1780 * Context returned from mlx5 open_device() glue function. 1781 * @param [in] attr 1782 * Pointer to VIRTQ attributes structure. 1783 * 1784 * @return 1785 * The DevX object created, NULL otherwise and rte_errno is set. 1786 */ 1787 struct mlx5_devx_obj * 1788 mlx5_devx_cmd_create_virtq(void *ctx, 1789 struct mlx5_devx_virtq_attr *attr) 1790 { 1791 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1792 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1793 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1794 sizeof(*virtq_obj), 1795 0, SOCKET_ID_ANY); 1796 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1797 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1798 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1799 1800 if (!virtq_obj) { 1801 DRV_LOG(ERR, "Failed to allocate virtq data."); 1802 rte_errno = ENOMEM; 1803 return NULL; 1804 } 1805 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1806 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1807 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1808 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1809 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1810 attr->hw_available_index); 1811 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1812 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1813 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1814 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1815 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1816 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1817 attr->virtio_version_1_0); 1818 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1819 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1820 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1821 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1822 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1823 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1824 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1825 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1826 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1827 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1828 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1829 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1830 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1831 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1832 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1833 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1834 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1835 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1836 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1837 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1838 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1839 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1840 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1841 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1842 sizeof(out)); 1843 if (!virtq_obj->obj) { 1844 rte_errno = errno; 1845 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1846 mlx5_free(virtq_obj); 1847 return NULL; 1848 } 1849 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1850 return virtq_obj; 1851 } 1852 1853 /** 1854 * Modify VIRTQ using DevX API. 1855 * 1856 * @param[in] virtq_obj 1857 * Pointer to virtq object structure. 1858 * @param [in] attr 1859 * Pointer to modify virtq attributes structure. 1860 * 1861 * @return 1862 * 0 on success, a negative errno value otherwise and rte_errno is set. 1863 */ 1864 int 1865 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1866 struct mlx5_devx_virtq_attr *attr) 1867 { 1868 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1869 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1870 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1871 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1872 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1873 int ret; 1874 1875 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1876 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1877 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1878 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1879 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1880 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1881 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1882 switch (attr->type) { 1883 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1884 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1885 break; 1886 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1887 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1888 attr->dirty_bitmap_mkey); 1889 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1890 attr->dirty_bitmap_addr); 1891 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1892 attr->dirty_bitmap_size); 1893 break; 1894 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1895 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1896 attr->dirty_bitmap_dump_enable); 1897 break; 1898 default: 1899 rte_errno = EINVAL; 1900 return -rte_errno; 1901 } 1902 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1903 out, sizeof(out)); 1904 if (ret) { 1905 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1906 rte_errno = errno; 1907 return -rte_errno; 1908 } 1909 return ret; 1910 } 1911 1912 /** 1913 * Query VIRTQ using DevX API. 1914 * 1915 * @param[in] virtq_obj 1916 * Pointer to virtq object structure. 1917 * @param [in/out] attr 1918 * Pointer to virtq attributes structure. 1919 * 1920 * @return 1921 * 0 on success, a negative errno value otherwise and rte_errno is set. 1922 */ 1923 int 1924 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1925 struct mlx5_devx_virtq_attr *attr) 1926 { 1927 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1928 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1929 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1930 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1931 int ret; 1932 1933 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1934 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1935 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1936 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1937 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1938 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1939 out, sizeof(out)); 1940 if (ret) { 1941 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1942 rte_errno = errno; 1943 return -errno; 1944 } 1945 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1946 hw_available_index); 1947 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1948 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1949 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1950 virtio_q_context.error_type); 1951 return ret; 1952 } 1953 1954 /** 1955 * Create QP using DevX API. 1956 * 1957 * @param[in] ctx 1958 * Context returned from mlx5 open_device() glue function. 1959 * @param [in] attr 1960 * Pointer to QP attributes structure. 1961 * 1962 * @return 1963 * The DevX object created, NULL otherwise and rte_errno is set. 1964 */ 1965 struct mlx5_devx_obj * 1966 mlx5_devx_cmd_create_qp(void *ctx, 1967 struct mlx5_devx_qp_attr *attr) 1968 { 1969 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1970 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1971 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1972 sizeof(*qp_obj), 1973 0, SOCKET_ID_ANY); 1974 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1975 1976 if (!qp_obj) { 1977 DRV_LOG(ERR, "Failed to allocate QP data."); 1978 rte_errno = ENOMEM; 1979 return NULL; 1980 } 1981 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 1982 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 1983 MLX5_SET(qpc, qpc, pd, attr->pd); 1984 MLX5_SET(qpc, qpc, ts_format, attr->ts_format); 1985 if (attr->uar_index) { 1986 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1987 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 1988 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1989 MLX5_SET(qpc, qpc, log_page_size, 1990 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1991 if (attr->sq_size) { 1992 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 1993 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 1994 MLX5_SET(qpc, qpc, log_sq_size, 1995 rte_log2_u32(attr->sq_size)); 1996 } else { 1997 MLX5_SET(qpc, qpc, no_sq, 1); 1998 } 1999 if (attr->rq_size) { 2000 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 2001 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 2002 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 2003 MLX5_LOG_RQ_STRIDE_SHIFT); 2004 MLX5_SET(qpc, qpc, log_rq_size, 2005 rte_log2_u32(attr->rq_size)); 2006 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 2007 } else { 2008 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2009 } 2010 if (attr->dbr_umem_valid) { 2011 MLX5_SET(qpc, qpc, dbr_umem_valid, 2012 attr->dbr_umem_valid); 2013 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 2014 } 2015 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 2016 MLX5_SET64(create_qp_in, in, wq_umem_offset, 2017 attr->wq_umem_offset); 2018 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 2019 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 2020 } else { 2021 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 2022 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 2023 MLX5_SET(qpc, qpc, no_sq, 1); 2024 } 2025 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2026 sizeof(out)); 2027 if (!qp_obj->obj) { 2028 rte_errno = errno; 2029 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 2030 mlx5_free(qp_obj); 2031 return NULL; 2032 } 2033 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 2034 return qp_obj; 2035 } 2036 2037 /** 2038 * Modify QP using DevX API. 2039 * Currently supports only force loop-back QP. 2040 * 2041 * @param[in] qp 2042 * Pointer to QP object structure. 2043 * @param [in] qp_st_mod_op 2044 * The QP state modification operation. 2045 * @param [in] remote_qp_id 2046 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 2047 * 2048 * @return 2049 * 0 on success, a negative errno value otherwise and rte_errno is set. 2050 */ 2051 int 2052 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 2053 uint32_t remote_qp_id) 2054 { 2055 union { 2056 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 2057 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 2058 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 2059 } in; 2060 union { 2061 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 2062 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 2063 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 2064 } out; 2065 void *qpc; 2066 int ret; 2067 unsigned int inlen; 2068 unsigned int outlen; 2069 2070 memset(&in, 0, sizeof(in)); 2071 memset(&out, 0, sizeof(out)); 2072 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 2073 switch (qp_st_mod_op) { 2074 case MLX5_CMD_OP_RST2INIT_QP: 2075 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 2076 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 2077 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2078 MLX5_SET(qpc, qpc, rre, 1); 2079 MLX5_SET(qpc, qpc, rwe, 1); 2080 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 2081 inlen = sizeof(in.rst2init); 2082 outlen = sizeof(out.rst2init); 2083 break; 2084 case MLX5_CMD_OP_INIT2RTR_QP: 2085 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 2086 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 2087 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 2088 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 2089 MLX5_SET(qpc, qpc, mtu, 1); 2090 MLX5_SET(qpc, qpc, log_msg_max, 30); 2091 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 2092 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 2093 inlen = sizeof(in.init2rtr); 2094 outlen = sizeof(out.init2rtr); 2095 break; 2096 case MLX5_CMD_OP_RTR2RTS_QP: 2097 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 2098 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 2099 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 2100 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 2101 MLX5_SET(qpc, qpc, retry_count, 7); 2102 MLX5_SET(qpc, qpc, rnr_retry, 7); 2103 inlen = sizeof(in.rtr2rts); 2104 outlen = sizeof(out.rtr2rts); 2105 break; 2106 default: 2107 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 2108 qp_st_mod_op); 2109 rte_errno = EINVAL; 2110 return -rte_errno; 2111 } 2112 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 2113 if (ret) { 2114 DRV_LOG(ERR, "Failed to modify QP using DevX."); 2115 rte_errno = errno; 2116 return -rte_errno; 2117 } 2118 return ret; 2119 } 2120 2121 struct mlx5_devx_obj * 2122 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 2123 { 2124 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 2125 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2126 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 2127 sizeof(*couners_obj), 0, 2128 SOCKET_ID_ANY); 2129 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 2130 2131 if (!couners_obj) { 2132 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 2133 rte_errno = ENOMEM; 2134 return NULL; 2135 } 2136 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2137 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2138 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2139 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2140 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2141 sizeof(out)); 2142 if (!couners_obj->obj) { 2143 rte_errno = errno; 2144 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 2145 " DevX."); 2146 mlx5_free(couners_obj); 2147 return NULL; 2148 } 2149 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2150 return couners_obj; 2151 } 2152 2153 int 2154 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 2155 struct mlx5_devx_virtio_q_couners_attr *attr) 2156 { 2157 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 2158 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 2159 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 2160 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 2161 virtio_q_counters); 2162 int ret; 2163 2164 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2165 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2166 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2167 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2168 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2169 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2170 sizeof(out)); 2171 if (ret) { 2172 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2173 rte_errno = errno; 2174 return -errno; 2175 } 2176 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2177 received_desc); 2178 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2179 completed_desc); 2180 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2181 error_cqes); 2182 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2183 bad_desc_errors); 2184 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2185 exceed_max_chain); 2186 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2187 invalid_buffer); 2188 return ret; 2189 } 2190 2191 /** 2192 * Create general object of type FLOW_HIT_ASO using DevX API. 2193 * 2194 * @param[in] ctx 2195 * Context returned from mlx5 open_device() glue function. 2196 * @param [in] pd 2197 * PD value to associate the FLOW_HIT_ASO object with. 2198 * 2199 * @return 2200 * The DevX object created, NULL otherwise and rte_errno is set. 2201 */ 2202 struct mlx5_devx_obj * 2203 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2204 { 2205 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2206 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2207 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2208 void *ptr = NULL; 2209 2210 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2211 0, SOCKET_ID_ANY); 2212 if (!flow_hit_aso_obj) { 2213 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2214 rte_errno = ENOMEM; 2215 return NULL; 2216 } 2217 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2218 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2219 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2220 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2221 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2222 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2223 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2224 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2225 out, sizeof(out)); 2226 if (!flow_hit_aso_obj->obj) { 2227 rte_errno = errno; 2228 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2229 mlx5_free(flow_hit_aso_obj); 2230 return NULL; 2231 } 2232 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2233 return flow_hit_aso_obj; 2234 } 2235 2236 /* 2237 * Create PD using DevX API. 2238 * 2239 * @param[in] ctx 2240 * Context returned from mlx5 open_device() glue function. 2241 * 2242 * @return 2243 * The DevX object created, NULL otherwise and rte_errno is set. 2244 */ 2245 struct mlx5_devx_obj * 2246 mlx5_devx_cmd_alloc_pd(void *ctx) 2247 { 2248 struct mlx5_devx_obj *ppd = 2249 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2250 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2251 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2252 2253 if (!ppd) { 2254 DRV_LOG(ERR, "Failed to allocate PD data."); 2255 rte_errno = ENOMEM; 2256 return NULL; 2257 } 2258 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2259 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2260 out, sizeof(out)); 2261 if (!ppd->obj) { 2262 mlx5_free(ppd); 2263 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2264 rte_errno = errno; 2265 return NULL; 2266 } 2267 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2268 return ppd; 2269 } 2270 2271 /** 2272 * Create general object of type FLOW_METER_ASO using DevX API. 2273 * 2274 * @param[in] ctx 2275 * Context returned from mlx5 open_device() glue function. 2276 * @param [in] pd 2277 * PD value to associate the FLOW_METER_ASO object with. 2278 * @param [in] log_obj_size 2279 * log_obj_size define to allocate number of 2 * meters 2280 * in one FLOW_METER_ASO object. 2281 * 2282 * @return 2283 * The DevX object created, NULL otherwise and rte_errno is set. 2284 */ 2285 struct mlx5_devx_obj * 2286 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd, 2287 uint32_t log_obj_size) 2288 { 2289 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0}; 2290 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; 2291 struct mlx5_devx_obj *flow_meter_aso_obj; 2292 void *ptr; 2293 2294 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, 2295 sizeof(*flow_meter_aso_obj), 2296 0, SOCKET_ID_ANY); 2297 if (!flow_meter_aso_obj) { 2298 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data"); 2299 rte_errno = ENOMEM; 2300 return NULL; 2301 } 2302 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr); 2303 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2304 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2305 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2306 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO); 2307 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, 2308 log_obj_size); 2309 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso); 2310 MLX5_SET(flow_meter_aso, ptr, access_pd, pd); 2311 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create( 2312 ctx, in, sizeof(in), 2313 out, sizeof(out)); 2314 if (!flow_meter_aso_obj->obj) { 2315 rte_errno = errno; 2316 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX."); 2317 mlx5_free(flow_meter_aso_obj); 2318 return NULL; 2319 } 2320 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, 2321 out, obj_id); 2322 return flow_meter_aso_obj; 2323 } 2324 2325 /** 2326 * Create general object of type GENEVE TLV option using DevX API. 2327 * 2328 * @param[in] ctx 2329 * Context returned from mlx5 open_device() glue function. 2330 * @param [in] class 2331 * TLV option variable value of class 2332 * @param [in] type 2333 * TLV option variable value of type 2334 * @param [in] len 2335 * TLV option variable value of len 2336 * 2337 * @return 2338 * The DevX object created, NULL otherwise and rte_errno is set. 2339 */ 2340 struct mlx5_devx_obj * 2341 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2342 uint16_t class, uint8_t type, uint8_t len) 2343 { 2344 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2345 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2346 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2347 sizeof(*geneve_tlv_opt_obj), 2348 0, SOCKET_ID_ANY); 2349 2350 if (!geneve_tlv_opt_obj) { 2351 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2352 rte_errno = ENOMEM; 2353 return NULL; 2354 } 2355 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2356 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2357 geneve_tlv_opt); 2358 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2359 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2360 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2361 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT); 2362 MLX5_SET(geneve_tlv_option, opt, option_class, 2363 rte_be_to_cpu_16(class)); 2364 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2365 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2366 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2367 sizeof(in), out, sizeof(out)); 2368 if (!geneve_tlv_opt_obj->obj) { 2369 rte_errno = errno; 2370 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2371 "Obj using DevX."); 2372 mlx5_free(geneve_tlv_opt_obj); 2373 return NULL; 2374 } 2375 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2376 return geneve_tlv_opt_obj; 2377 } 2378 2379 int 2380 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id) 2381 { 2382 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2383 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; 2384 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0}; 2385 int rc; 2386 void *rq_ctx; 2387 2388 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ); 2389 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num); 2390 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out)); 2391 if (rc) { 2392 rte_errno = errno; 2393 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - " 2394 "rc = %d, errno = %d.", rc, errno); 2395 return -rc; 2396 }; 2397 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context); 2398 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id); 2399 return 0; 2400 #else 2401 (void)wq; 2402 (void)counter_set_id; 2403 return -ENOTSUP; 2404 #endif 2405 } 2406 2407 /* 2408 * Allocate queue counters via devx interface. 2409 * 2410 * @param[in] ctx 2411 * Context returned from mlx5 open_device() glue function. 2412 * 2413 * @return 2414 * Pointer to counter object on success, a NULL value otherwise and 2415 * rte_errno is set. 2416 */ 2417 struct mlx5_devx_obj * 2418 mlx5_devx_cmd_queue_counter_alloc(void *ctx) 2419 { 2420 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0, 2421 SOCKET_ID_ANY); 2422 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0}; 2423 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0}; 2424 2425 if (!dcs) { 2426 rte_errno = ENOMEM; 2427 return NULL; 2428 } 2429 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER); 2430 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 2431 sizeof(out)); 2432 if (!dcs->obj) { 2433 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error " 2434 "%d.", errno); 2435 rte_errno = errno; 2436 mlx5_free(dcs); 2437 return NULL; 2438 } 2439 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id); 2440 return dcs; 2441 } 2442 2443 /** 2444 * Query queue counters values. 2445 * 2446 * @param[in] dcs 2447 * devx object of the queue counter set. 2448 * @param[in] clear 2449 * Whether hardware should clear the counters after the query or not. 2450 * @param[out] out_of_buffers 2451 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs. 2452 * 2453 * @return 2454 * 0 on success, a negative value otherwise. 2455 */ 2456 int 2457 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, 2458 uint32_t *out_of_buffers) 2459 { 2460 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0}; 2461 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0}; 2462 int rc; 2463 2464 MLX5_SET(query_q_counter_in, in, opcode, 2465 MLX5_CMD_OP_QUERY_Q_COUNTER); 2466 MLX5_SET(query_q_counter_in, in, op_mod, 0); 2467 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id); 2468 MLX5_SET(query_q_counter_in, in, clear, !!clear); 2469 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 2470 sizeof(out)); 2471 if (rc) { 2472 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc); 2473 rte_errno = rc; 2474 return -rc; 2475 } 2476 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer); 2477 return 0; 2478 } 2479 2480 /** 2481 * Create general object of type DEK using DevX API. 2482 * 2483 * @param[in] ctx 2484 * Context returned from mlx5 open_device() glue function. 2485 * @param [in] attr 2486 * Pointer to DEK attributes structure. 2487 * 2488 * @return 2489 * The DevX object created, NULL otherwise and rte_errno is set. 2490 */ 2491 struct mlx5_devx_obj * 2492 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr) 2493 { 2494 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0}; 2495 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2496 struct mlx5_devx_obj *dek_obj = NULL; 2497 void *ptr = NULL, *key_addr = NULL; 2498 2499 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj), 2500 0, SOCKET_ID_ANY); 2501 if (dek_obj == NULL) { 2502 DRV_LOG(ERR, "Failed to allocate DEK object data"); 2503 rte_errno = ENOMEM; 2504 return NULL; 2505 } 2506 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr); 2507 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2508 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2509 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2510 MLX5_GENERAL_OBJ_TYPE_DEK); 2511 ptr = MLX5_ADDR_OF(create_dek_in, in, dek); 2512 MLX5_SET(dek, ptr, key_size, attr->key_size); 2513 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag); 2514 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose); 2515 MLX5_SET(dek, ptr, pd, attr->pd); 2516 MLX5_SET64(dek, ptr, opaque, attr->opaque); 2517 key_addr = MLX5_ADDR_OF(dek, ptr, key); 2518 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2519 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2520 out, sizeof(out)); 2521 if (dek_obj->obj == NULL) { 2522 rte_errno = errno; 2523 DRV_LOG(ERR, "Failed to create DEK obj using DevX."); 2524 mlx5_free(dek_obj); 2525 return NULL; 2526 } 2527 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2528 return dek_obj; 2529 } 2530 2531 /** 2532 * Create general object of type IMPORT_KEK using DevX API. 2533 * 2534 * @param[in] ctx 2535 * Context returned from mlx5 open_device() glue function. 2536 * @param [in] attr 2537 * Pointer to IMPORT_KEK attributes structure. 2538 * 2539 * @return 2540 * The DevX object created, NULL otherwise and rte_errno is set. 2541 */ 2542 struct mlx5_devx_obj * 2543 mlx5_devx_cmd_create_import_kek_obj(void *ctx, 2544 struct mlx5_devx_import_kek_attr *attr) 2545 { 2546 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0}; 2547 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2548 struct mlx5_devx_obj *import_kek_obj = NULL; 2549 void *ptr = NULL, *key_addr = NULL; 2550 2551 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj), 2552 0, SOCKET_ID_ANY); 2553 if (import_kek_obj == NULL) { 2554 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data"); 2555 rte_errno = ENOMEM; 2556 return NULL; 2557 } 2558 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr); 2559 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2560 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2561 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2562 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK); 2563 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek); 2564 MLX5_SET(import_kek, ptr, key_size, attr->key_size); 2565 key_addr = MLX5_ADDR_OF(import_kek, ptr, key); 2566 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE); 2567 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2568 out, sizeof(out)); 2569 if (import_kek_obj->obj == NULL) { 2570 rte_errno = errno; 2571 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX."); 2572 mlx5_free(import_kek_obj); 2573 return NULL; 2574 } 2575 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2576 return import_kek_obj; 2577 } 2578 2579 /** 2580 * Create general object of type CREDENTIAL using DevX API. 2581 * 2582 * @param[in] ctx 2583 * Context returned from mlx5 open_device() glue function. 2584 * @param [in] attr 2585 * Pointer to CREDENTIAL attributes structure. 2586 * 2587 * @return 2588 * The DevX object created, NULL otherwise and rte_errno is set. 2589 */ 2590 struct mlx5_devx_obj * 2591 mlx5_devx_cmd_create_credential_obj(void *ctx, 2592 struct mlx5_devx_credential_attr *attr) 2593 { 2594 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0}; 2595 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2596 struct mlx5_devx_obj *credential_obj = NULL; 2597 void *ptr = NULL, *credential_addr = NULL; 2598 2599 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj), 2600 0, SOCKET_ID_ANY); 2601 if (credential_obj == NULL) { 2602 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data"); 2603 rte_errno = ENOMEM; 2604 return NULL; 2605 } 2606 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr); 2607 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2608 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2609 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2610 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL); 2611 ptr = MLX5_ADDR_OF(create_credential_in, in, credential); 2612 MLX5_SET(credential, ptr, credential_role, attr->credential_role); 2613 credential_addr = MLX5_ADDR_OF(credential, ptr, credential); 2614 memcpy(credential_addr, (void *)(attr->credential), 2615 MLX5_CRYPTO_CREDENTIAL_SIZE); 2616 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2617 out, sizeof(out)); 2618 if (credential_obj->obj == NULL) { 2619 rte_errno = errno; 2620 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX."); 2621 mlx5_free(credential_obj); 2622 return NULL; 2623 } 2624 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2625 return credential_obj; 2626 } 2627 2628 /** 2629 * Create general object of type CRYPTO_LOGIN using DevX API. 2630 * 2631 * @param[in] ctx 2632 * Context returned from mlx5 open_device() glue function. 2633 * @param [in] attr 2634 * Pointer to CRYPTO_LOGIN attributes structure. 2635 * 2636 * @return 2637 * The DevX object created, NULL otherwise and rte_errno is set. 2638 */ 2639 struct mlx5_devx_obj * 2640 mlx5_devx_cmd_create_crypto_login_obj(void *ctx, 2641 struct mlx5_devx_crypto_login_attr *attr) 2642 { 2643 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0}; 2644 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2645 struct mlx5_devx_obj *crypto_login_obj = NULL; 2646 void *ptr = NULL, *credential_addr = NULL; 2647 2648 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj), 2649 0, SOCKET_ID_ANY); 2650 if (crypto_login_obj == NULL) { 2651 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data"); 2652 rte_errno = ENOMEM; 2653 return NULL; 2654 } 2655 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr); 2656 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2657 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2658 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2659 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN); 2660 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login); 2661 MLX5_SET(crypto_login, ptr, credential_pointer, 2662 attr->credential_pointer); 2663 MLX5_SET(crypto_login, ptr, session_import_kek_ptr, 2664 attr->session_import_kek_ptr); 2665 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential); 2666 memcpy(credential_addr, (void *)(attr->credential), 2667 MLX5_CRYPTO_CREDENTIAL_SIZE); 2668 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2669 out, sizeof(out)); 2670 if (crypto_login_obj->obj == NULL) { 2671 rte_errno = errno; 2672 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX."); 2673 mlx5_free(crypto_login_obj); 2674 return NULL; 2675 } 2676 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2677 return crypto_login_obj; 2678 } 2679