1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright 2018 Mellanox Technologies, Ltd */ 3 4 #include <unistd.h> 5 6 #include <rte_errno.h> 7 #include <rte_malloc.h> 8 #include <rte_eal_paging.h> 9 10 #include "mlx5_prm.h" 11 #include "mlx5_devx_cmds.h" 12 #include "mlx5_common_utils.h" 13 #include "mlx5_malloc.h" 14 15 16 /** 17 * Perform read access to the registers. Reads data from register 18 * and writes ones to the specified buffer. 19 * 20 * @param[in] ctx 21 * Context returned from mlx5 open_device() glue function. 22 * @param[in] reg_id 23 * Register identifier according to the PRM. 24 * @param[in] arg 25 * Register access auxiliary parameter according to the PRM. 26 * @param[out] data 27 * Pointer to the buffer to store read data. 28 * @param[in] dw_cnt 29 * Buffer size in double words. 30 * 31 * @return 32 * 0 on success, a negative value otherwise. 33 */ 34 int 35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg, 36 uint32_t *data, uint32_t dw_cnt) 37 { 38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0}; 39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) + 40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0}; 41 int status, rc; 42 43 MLX5_ASSERT(data && dw_cnt); 44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX); 45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) { 46 DRV_LOG(ERR, "Not enough buffer for register read data"); 47 return -1; 48 } 49 MLX5_SET(access_register_in, in, opcode, 50 MLX5_CMD_OP_ACCESS_REGISTER_USER); 51 MLX5_SET(access_register_in, in, op_mod, 52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ); 53 MLX5_SET(access_register_in, in, register_id, reg_id); 54 MLX5_SET(access_register_in, in, argument, arg); 55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, 56 MLX5_ST_SZ_DW(access_register_out) * 57 sizeof(uint32_t) + dw_cnt); 58 if (rc) 59 goto error; 60 status = MLX5_GET(access_register_out, out, status); 61 if (status) { 62 int syndrome = MLX5_GET(access_register_out, out, syndrome); 63 64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, " 65 "status %x, syndrome = %x", 66 reg_id, status, syndrome); 67 return -1; 68 } 69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)], 70 dw_cnt * sizeof(uint32_t)); 71 return 0; 72 error: 73 rc = (rc > 0) ? -rc : rc; 74 return rc; 75 } 76 77 /** 78 * Allocate flow counters via devx interface. 79 * 80 * @param[in] ctx 81 * Context returned from mlx5 open_device() glue function. 82 * @param dcs 83 * Pointer to counters properties structure to be filled by the routine. 84 * @param bulk_n_128 85 * Bulk counter numbers in 128 counters units. 86 * 87 * @return 88 * Pointer to counter object on success, a negative value otherwise and 89 * rte_errno is set. 90 */ 91 struct mlx5_devx_obj * 92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128) 93 { 94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 95 0, SOCKET_ID_ANY); 96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0}; 97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0}; 98 99 if (!dcs) { 100 rte_errno = ENOMEM; 101 return NULL; 102 } 103 MLX5_SET(alloc_flow_counter_in, in, opcode, 104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER); 105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128); 106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, 107 sizeof(in), out, sizeof(out)); 108 if (!dcs->obj) { 109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno); 110 rte_errno = errno; 111 mlx5_free(dcs); 112 return NULL; 113 } 114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id); 115 return dcs; 116 } 117 118 /** 119 * Query flow counters values. 120 * 121 * @param[in] dcs 122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc. 123 * @param[in] clear 124 * Whether hardware should clear the counters after the query or not. 125 * @param[in] n_counters 126 * 0 in case of 1 counter to read, otherwise the counter number to read. 127 * @param pkts 128 * The number of packets that matched the flow. 129 * @param bytes 130 * The number of bytes that matched the flow. 131 * @param mkey 132 * The mkey key for batch query. 133 * @param addr 134 * The address in the mkey range for batch query. 135 * @param cmd_comp 136 * The completion object for asynchronous batch query. 137 * @param async_id 138 * The ID to be returned in the asynchronous batch query response. 139 * 140 * @return 141 * 0 on success, a negative value otherwise. 142 */ 143 int 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs, 145 int clear, uint32_t n_counters, 146 uint64_t *pkts, uint64_t *bytes, 147 uint32_t mkey, void *addr, 148 void *cmd_comp, 149 uint64_t async_id) 150 { 151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) + 152 MLX5_ST_SZ_BYTES(traffic_counter); 153 uint32_t out[out_len]; 154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0}; 155 void *stats; 156 int rc; 157 158 MLX5_SET(query_flow_counter_in, in, opcode, 159 MLX5_CMD_OP_QUERY_FLOW_COUNTER); 160 MLX5_SET(query_flow_counter_in, in, op_mod, 0); 161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id); 162 MLX5_SET(query_flow_counter_in, in, clear, !!clear); 163 164 if (n_counters) { 165 MLX5_SET(query_flow_counter_in, in, num_of_counters, 166 n_counters); 167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1); 168 MLX5_SET(query_flow_counter_in, in, mkey, mkey); 169 MLX5_SET64(query_flow_counter_in, in, address, 170 (uint64_t)(uintptr_t)addr); 171 } 172 if (!cmd_comp) 173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out, 174 out_len); 175 else 176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in), 177 out_len, async_id, 178 cmd_comp); 179 if (rc) { 180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc); 181 rte_errno = rc; 182 return -rc; 183 } 184 if (!n_counters) { 185 stats = MLX5_ADDR_OF(query_flow_counter_out, 186 out, flow_statistics); 187 *pkts = MLX5_GET64(traffic_counter, stats, packets); 188 *bytes = MLX5_GET64(traffic_counter, stats, octets); 189 } 190 return 0; 191 } 192 193 /** 194 * Create a new mkey. 195 * 196 * @param[in] ctx 197 * Context returned from mlx5 open_device() glue function. 198 * @param[in] attr 199 * Attributes of the requested mkey. 200 * 201 * @return 202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno 203 * is set. 204 */ 205 struct mlx5_devx_obj * 206 mlx5_devx_cmd_mkey_create(void *ctx, 207 struct mlx5_devx_mkey_attr *attr) 208 { 209 struct mlx5_klm *klm_array = attr->klm_array; 210 int klm_num = attr->klm_num; 211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) + 212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm); 213 uint32_t in[in_size_dw]; 214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; 215 void *mkc; 216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey), 217 0, SOCKET_ID_ANY); 218 size_t pgsize; 219 uint32_t translation_size; 220 221 if (!mkey) { 222 rte_errno = ENOMEM; 223 return NULL; 224 } 225 memset(in, 0, in_size_dw * 4); 226 pgsize = rte_mem_page_size(); 227 if (pgsize == (size_t)-1) { 228 mlx5_free(mkey); 229 DRV_LOG(ERR, "Failed to get page size"); 230 rte_errno = ENOMEM; 231 return NULL; 232 } 233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); 234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 235 if (klm_num > 0) { 236 int i; 237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in, 238 klm_pas_mtt); 239 translation_size = RTE_ALIGN(klm_num, 4); 240 for (i = 0; i < klm_num; i++) { 241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count); 242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey); 243 MLX5_SET64(klm, klm, address, klm_array[i].address); 244 klm += MLX5_ST_SZ_BYTES(klm); 245 } 246 for (; i < (int)translation_size; i++) { 247 MLX5_SET(klm, klm, mkey, 0x0); 248 MLX5_SET64(klm, klm, address, 0x0); 249 klm += MLX5_ST_SZ_BYTES(klm); 250 } 251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ? 252 MLX5_MKC_ACCESS_MODE_KLM_FBS : 253 MLX5_MKC_ACCESS_MODE_KLM); 254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size); 255 } else { 256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16; 257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT); 258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize)); 259 } 260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size, 261 translation_size); 262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id); 263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access); 264 MLX5_SET(mkc, mkc, lw, 0x1); 265 MLX5_SET(mkc, mkc, lr, 0x1); 266 MLX5_SET(mkc, mkc, qpn, 0xffffff); 267 MLX5_SET(mkc, mkc, pd, attr->pd); 268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF); 269 MLX5_SET(mkc, mkc, translations_octword_size, translation_size); 270 MLX5_SET(mkc, mkc, relaxed_ordering_write, 271 attr->relaxed_ordering_write); 272 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read); 273 MLX5_SET64(mkc, mkc, start_addr, attr->addr); 274 MLX5_SET64(mkc, mkc, len, attr->size); 275 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out, 276 sizeof(out)); 277 if (!mkey->obj) { 278 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n", 279 klm_num ? "an in" : "a ", errno); 280 rte_errno = errno; 281 mlx5_free(mkey); 282 return NULL; 283 } 284 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index); 285 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF); 286 return mkey; 287 } 288 289 /** 290 * Get status of devx command response. 291 * Mainly used for asynchronous commands. 292 * 293 * @param[in] out 294 * The out response buffer. 295 * 296 * @return 297 * 0 on success, non-zero value otherwise. 298 */ 299 int 300 mlx5_devx_get_out_command_status(void *out) 301 { 302 int status; 303 304 if (!out) 305 return -EINVAL; 306 status = MLX5_GET(query_flow_counter_out, out, status); 307 if (status) { 308 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome); 309 310 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status, 311 syndrome); 312 } 313 return status; 314 } 315 316 /** 317 * Destroy any object allocated by a Devx API. 318 * 319 * @param[in] obj 320 * Pointer to a general object. 321 * 322 * @return 323 * 0 on success, a negative value otherwise. 324 */ 325 int 326 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj) 327 { 328 int ret; 329 330 if (!obj) 331 return 0; 332 ret = mlx5_glue->devx_obj_destroy(obj->obj); 333 mlx5_free(obj); 334 return ret; 335 } 336 337 /** 338 * Query NIC vport context. 339 * Fills minimal inline attribute. 340 * 341 * @param[in] ctx 342 * ibv contexts returned from mlx5dv_open_device. 343 * @param[in] vport 344 * vport index 345 * @param[out] attr 346 * Attributes device values. 347 * 348 * @return 349 * 0 on success, a negative value otherwise. 350 */ 351 static int 352 mlx5_devx_cmd_query_nic_vport_context(void *ctx, 353 unsigned int vport, 354 struct mlx5_hca_attr *attr) 355 { 356 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; 357 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0}; 358 void *vctx; 359 int status, syndrome, rc; 360 361 /* Query NIC vport context to determine inline mode. */ 362 MLX5_SET(query_nic_vport_context_in, in, opcode, 363 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT); 364 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport); 365 if (vport) 366 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1); 367 rc = mlx5_glue->devx_general_cmd(ctx, 368 in, sizeof(in), 369 out, sizeof(out)); 370 if (rc) 371 goto error; 372 status = MLX5_GET(query_nic_vport_context_out, out, status); 373 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome); 374 if (status) { 375 DRV_LOG(DEBUG, "Failed to query NIC vport context, " 376 "status %x, syndrome = %x", status, syndrome); 377 return -1; 378 } 379 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out, 380 nic_vport_context); 381 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx, 382 min_wqe_inline_mode); 383 return 0; 384 error: 385 rc = (rc > 0) ? -rc : rc; 386 return rc; 387 } 388 389 /** 390 * Query NIC vDPA attributes. 391 * 392 * @param[in] ctx 393 * Context returned from mlx5 open_device() glue function. 394 * @param[out] vdpa_attr 395 * vDPA Attributes structure to fill. 396 */ 397 static void 398 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, 399 struct mlx5_hca_vdpa_attr *vdpa_attr) 400 { 401 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 402 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 403 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 404 int status, syndrome, rc; 405 406 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 407 MLX5_SET(query_hca_cap_in, in, op_mod, 408 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | 409 MLX5_HCA_CAP_OPMOD_GET_CUR); 410 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 411 status = MLX5_GET(query_hca_cap_out, out, status); 412 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 413 if (rc || status) { 414 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," 415 " status %x, syndrome = %x", status, syndrome); 416 vdpa_attr->valid = 0; 417 } else { 418 vdpa_attr->valid = 1; 419 vdpa_attr->desc_tunnel_offload_type = 420 MLX5_GET(virtio_emulation_cap, hcattr, 421 desc_tunnel_offload_type); 422 vdpa_attr->eth_frame_offload_type = 423 MLX5_GET(virtio_emulation_cap, hcattr, 424 eth_frame_offload_type); 425 vdpa_attr->virtio_version_1_0 = 426 MLX5_GET(virtio_emulation_cap, hcattr, 427 virtio_version_1_0); 428 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr, 429 tso_ipv4); 430 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr, 431 tso_ipv6); 432 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 433 tx_csum); 434 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr, 435 rx_csum); 436 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr, 437 event_mode); 438 vdpa_attr->virtio_queue_type = 439 MLX5_GET(virtio_emulation_cap, hcattr, 440 virtio_queue_type); 441 vdpa_attr->log_doorbell_stride = 442 MLX5_GET(virtio_emulation_cap, hcattr, 443 log_doorbell_stride); 444 vdpa_attr->log_doorbell_bar_size = 445 MLX5_GET(virtio_emulation_cap, hcattr, 446 log_doorbell_bar_size); 447 vdpa_attr->doorbell_bar_offset = 448 MLX5_GET64(virtio_emulation_cap, hcattr, 449 doorbell_bar_offset); 450 vdpa_attr->max_num_virtio_queues = 451 MLX5_GET(virtio_emulation_cap, hcattr, 452 max_num_virtio_queues); 453 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr, 454 umem_1_buffer_param_a); 455 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr, 456 umem_1_buffer_param_b); 457 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr, 458 umem_2_buffer_param_a); 459 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr, 460 umem_2_buffer_param_b); 461 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr, 462 umem_3_buffer_param_a); 463 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr, 464 umem_3_buffer_param_b); 465 } 466 } 467 468 int 469 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, 470 uint32_t ids[], uint32_t num) 471 { 472 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 473 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; 474 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr); 475 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex); 476 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 477 int ret; 478 uint32_t idx = 0; 479 uint32_t i; 480 481 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) { 482 rte_errno = EINVAL; 483 DRV_LOG(ERR, "Too many sample IDs to be fetched."); 484 return -rte_errno; 485 } 486 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 487 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 488 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 489 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 490 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id); 491 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in), 492 out, sizeof(out)); 493 if (ret) { 494 rte_errno = ret; 495 DRV_LOG(ERR, "Failed to query sample IDs with object %p.", 496 (void *)flex_obj); 497 return -rte_errno; 498 } 499 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 500 void *s_off = (void *)((char *)sample + i * 501 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 502 uint32_t en; 503 504 en = MLX5_GET(parse_graph_flow_match_sample, s_off, 505 flow_match_sample_en); 506 if (!en) 507 continue; 508 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, 509 flow_match_sample_field_id); 510 } 511 if (num != idx) { 512 rte_errno = EINVAL; 513 DRV_LOG(ERR, "Number of sample IDs are not as expected."); 514 return -rte_errno; 515 } 516 return ret; 517 } 518 519 520 struct mlx5_devx_obj * 521 mlx5_devx_cmd_create_flex_parser(void *ctx, 522 struct mlx5_devx_graph_node_attr *data) 523 { 524 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0}; 525 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 526 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr); 527 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex); 528 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table); 529 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc); 530 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc); 531 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc 532 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY); 533 uint32_t i; 534 535 if (!parse_flex_obj) { 536 DRV_LOG(ERR, "Failed to allocate flex parser data."); 537 rte_errno = ENOMEM; 538 return NULL; 539 } 540 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 541 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 542 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 543 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH); 544 MLX5_SET(parse_graph_flex, flex, header_length_mode, 545 data->header_length_mode); 546 MLX5_SET(parse_graph_flex, flex, header_length_base_value, 547 data->header_length_base_value); 548 MLX5_SET(parse_graph_flex, flex, header_length_field_offset, 549 data->header_length_field_offset); 550 MLX5_SET(parse_graph_flex, flex, header_length_field_shift, 551 data->header_length_field_shift); 552 MLX5_SET(parse_graph_flex, flex, header_length_field_mask, 553 data->header_length_field_mask); 554 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 555 struct mlx5_devx_match_sample_attr *s = &data->sample[i]; 556 void *s_off = (void *)((char *)sample + i * 557 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); 558 559 if (!s->flow_match_sample_en) 560 continue; 561 MLX5_SET(parse_graph_flow_match_sample, s_off, 562 flow_match_sample_en, !!s->flow_match_sample_en); 563 MLX5_SET(parse_graph_flow_match_sample, s_off, 564 flow_match_sample_field_offset, 565 s->flow_match_sample_field_offset); 566 MLX5_SET(parse_graph_flow_match_sample, s_off, 567 flow_match_sample_offset_mode, 568 s->flow_match_sample_offset_mode); 569 MLX5_SET(parse_graph_flow_match_sample, s_off, 570 flow_match_sample_field_offset_mask, 571 s->flow_match_sample_field_offset_mask); 572 MLX5_SET(parse_graph_flow_match_sample, s_off, 573 flow_match_sample_field_offset_shift, 574 s->flow_match_sample_field_offset_shift); 575 MLX5_SET(parse_graph_flow_match_sample, s_off, 576 flow_match_sample_field_base_offset, 577 s->flow_match_sample_field_base_offset); 578 MLX5_SET(parse_graph_flow_match_sample, s_off, 579 flow_match_sample_tunnel_mode, 580 s->flow_match_sample_tunnel_mode); 581 } 582 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) { 583 struct mlx5_devx_graph_arc_attr *ia = &data->in[i]; 584 struct mlx5_devx_graph_arc_attr *oa = &data->out[i]; 585 void *in_off = (void *)((char *)in_arc + i * 586 MLX5_ST_SZ_BYTES(parse_graph_arc)); 587 void *out_off = (void *)((char *)out_arc + i * 588 MLX5_ST_SZ_BYTES(parse_graph_arc)); 589 590 if (ia->arc_parse_graph_node != 0) { 591 MLX5_SET(parse_graph_arc, in_off, 592 compare_condition_value, 593 ia->compare_condition_value); 594 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel, 595 ia->start_inner_tunnel); 596 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node, 597 ia->arc_parse_graph_node); 598 MLX5_SET(parse_graph_arc, in_off, 599 parse_graph_node_handle, 600 ia->parse_graph_node_handle); 601 } 602 if (oa->arc_parse_graph_node != 0) { 603 MLX5_SET(parse_graph_arc, out_off, 604 compare_condition_value, 605 oa->compare_condition_value); 606 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel, 607 oa->start_inner_tunnel); 608 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node, 609 oa->arc_parse_graph_node); 610 MLX5_SET(parse_graph_arc, out_off, 611 parse_graph_node_handle, 612 oa->parse_graph_node_handle); 613 } 614 } 615 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 616 out, sizeof(out)); 617 if (!parse_flex_obj->obj) { 618 rte_errno = errno; 619 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object " 620 "by using DevX."); 621 mlx5_free(parse_flex_obj); 622 return NULL; 623 } 624 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 625 return parse_flex_obj; 626 } 627 628 /** 629 * Query HCA attributes. 630 * Using those attributes we can check on run time if the device 631 * is having the required capabilities. 632 * 633 * @param[in] ctx 634 * Context returned from mlx5 open_device() glue function. 635 * @param[out] attr 636 * Attributes device values. 637 * 638 * @return 639 * 0 on success, a negative value otherwise. 640 */ 641 int 642 mlx5_devx_cmd_query_hca_attr(void *ctx, 643 struct mlx5_hca_attr *attr) 644 { 645 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; 646 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; 647 void *hcattr; 648 int status, syndrome, rc, i; 649 650 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 651 MLX5_SET(query_hca_cap_in, in, op_mod, 652 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | 653 MLX5_HCA_CAP_OPMOD_GET_CUR); 654 655 rc = mlx5_glue->devx_general_cmd(ctx, 656 in, sizeof(in), out, sizeof(out)); 657 if (rc) 658 goto error; 659 status = MLX5_GET(query_hca_cap_out, out, status); 660 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 661 if (status) { 662 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 663 "status %x, syndrome = %x", status, syndrome); 664 return -1; 665 } 666 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 667 attr->flow_counter_bulk_alloc_bitmap = 668 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); 669 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, 670 flow_counters_dump); 671 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr, 672 log_max_rqt_size); 673 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager); 674 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin); 675 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr, 676 log_max_hairpin_queues); 677 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr, 678 log_max_hairpin_wq_data_sz); 679 attr->log_max_hairpin_num_packets = MLX5_GET 680 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz); 681 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id); 682 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr, 683 relaxed_ordering_write); 684 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr, 685 relaxed_ordering_read); 686 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr, 687 access_register_user); 688 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr, 689 eth_net_offloads); 690 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt); 691 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr, 692 flex_parser_protocols); 693 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr, 694 max_geneve_tlv_options); 695 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr, 696 max_geneve_tlv_option_data_len); 697 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos); 698 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 699 general_obj_types) & 700 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q); 701 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr, 702 general_obj_types) & 703 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS); 704 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr, 705 general_obj_types) & 706 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE); 707 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr, 708 wqe_index_ignore_cap); 709 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd); 710 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq); 711 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr, 712 log_max_static_sq_wq); 713 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports); 714 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr, 715 device_frequency_khz); 716 attr->scatter_fcs_w_decap_disable = 717 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable); 718 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp); 719 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr, 720 regexp_num_of_engines); 721 attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr, 722 general_obj_types) & 723 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); 724 attr->geneve_tlv_opt = !!(MLX5_GET64(cmd_hca_cap, hcattr, 725 general_obj_types) & 726 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT); 727 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq); 728 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); 729 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); 730 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); 731 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); 732 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); 733 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); 734 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz); 735 attr->reg_c_preserve = 736 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve); 737 attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo); 738 attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress); 739 attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress); 740 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr, 741 compress_min_block_size); 742 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size); 743 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr, 744 log_compress_mmo_size); 745 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, 746 log_decompress_mmo_size); 747 if (attr->qos.sup) { 748 MLX5_SET(query_hca_cap_in, in, op_mod, 749 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | 750 MLX5_HCA_CAP_OPMOD_GET_CUR); 751 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), 752 out, sizeof(out)); 753 if (rc) 754 goto error; 755 if (status) { 756 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," 757 " status %x, syndrome = %x", status, syndrome); 758 return -1; 759 } 760 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 761 attr->qos.srtcm_sup = 762 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm); 763 attr->qos.log_max_flow_meter = 764 MLX5_GET(qos_cap, hcattr, log_max_flow_meter); 765 attr->qos.flow_meter_reg_c_ids = 766 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id); 767 attr->qos.flow_meter_reg_share = 768 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share); 769 attr->qos.packet_pacing = 770 MLX5_GET(qos_cap, hcattr, packet_pacing); 771 attr->qos.wqe_rate_pp = 772 MLX5_GET(qos_cap, hcattr, wqe_rate_pp); 773 } 774 if (attr->vdpa.valid) 775 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); 776 if (!attr->eth_net_offloads) 777 return 0; 778 779 /* Query Flow Sampler Capability From FLow Table Properties Layout. */ 780 memset(in, 0, sizeof(in)); 781 memset(out, 0, sizeof(out)); 782 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 783 MLX5_SET(query_hca_cap_in, in, op_mod, 784 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | 785 MLX5_HCA_CAP_OPMOD_GET_CUR); 786 787 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 788 if (rc) 789 goto error; 790 status = MLX5_GET(query_hca_cap_out, out, status); 791 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 792 if (status) { 793 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 794 "status %x, syndrome = %x", status, syndrome); 795 attr->log_max_ft_sampler_num = 0; 796 return -1; 797 } 798 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 799 attr->log_max_ft_sampler_num = 800 MLX5_GET(flow_table_nic_cap, 801 hcattr, flow_table_properties.log_max_ft_sampler_num); 802 803 /* Query HCA offloads for Ethernet protocol. */ 804 memset(in, 0, sizeof(in)); 805 memset(out, 0, sizeof(out)); 806 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 807 MLX5_SET(query_hca_cap_in, in, op_mod, 808 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | 809 MLX5_HCA_CAP_OPMOD_GET_CUR); 810 811 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); 812 if (rc) { 813 attr->eth_net_offloads = 0; 814 goto error; 815 } 816 status = MLX5_GET(query_hca_cap_out, out, status); 817 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); 818 if (status) { 819 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " 820 "status %x, syndrome = %x", status, syndrome); 821 attr->eth_net_offloads = 0; 822 return -1; 823 } 824 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 825 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, 826 hcattr, wqe_vlan_insert); 827 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr, 828 lro_cap); 829 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps, 830 hcattr, tunnel_lro_gre); 831 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps, 832 hcattr, tunnel_lro_vxlan); 833 attr->lro_max_msg_sz_mode = MLX5_GET 834 (per_protocol_networking_offload_caps, 835 hcattr, lro_max_msg_sz_mode); 836 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) { 837 attr->lro_timer_supported_periods[i] = 838 MLX5_GET(per_protocol_networking_offload_caps, hcattr, 839 lro_timer_supported_periods[i]); 840 } 841 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps, 842 hcattr, lro_min_mss_size); 843 attr->tunnel_stateless_geneve_rx = 844 MLX5_GET(per_protocol_networking_offload_caps, 845 hcattr, tunnel_stateless_geneve_rx); 846 attr->geneve_max_opt_len = 847 MLX5_GET(per_protocol_networking_offload_caps, 848 hcattr, max_geneve_opt_len); 849 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps, 850 hcattr, wqe_inline_mode); 851 attr->tunnel_stateless_gtp = MLX5_GET 852 (per_protocol_networking_offload_caps, 853 hcattr, tunnel_stateless_gtp); 854 attr->rss_ind_tbl_cap = MLX5_GET 855 (per_protocol_networking_offload_caps, 856 hcattr, rss_ind_tbl_cap); 857 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) 858 return 0; 859 if (attr->eth_virt) { 860 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr); 861 if (rc) { 862 attr->eth_virt = 0; 863 goto error; 864 } 865 } 866 return 0; 867 error: 868 rc = (rc > 0) ? -rc : rc; 869 return rc; 870 } 871 872 /** 873 * Query TIS transport domain from QP verbs object using DevX API. 874 * 875 * @param[in] qp 876 * Pointer to verbs QP returned by ibv_create_qp . 877 * @param[in] tis_num 878 * TIS number of TIS to query. 879 * @param[out] tis_td 880 * Pointer to TIS transport domain variable, to be set by the routine. 881 * 882 * @return 883 * 0 on success, a negative value otherwise. 884 */ 885 int 886 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num, 887 uint32_t *tis_td) 888 { 889 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 890 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0}; 891 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0}; 892 int rc; 893 void *tis_ctx; 894 895 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS); 896 MLX5_SET(query_tis_in, in, tisn, tis_num); 897 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out)); 898 if (rc) { 899 DRV_LOG(ERR, "Failed to query QP using DevX"); 900 return -rc; 901 }; 902 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context); 903 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain); 904 return 0; 905 #else 906 (void)qp; 907 (void)tis_num; 908 (void)tis_td; 909 return -ENOTSUP; 910 #endif 911 } 912 913 /** 914 * Fill WQ data for DevX API command. 915 * Utility function for use when creating DevX objects containing a WQ. 916 * 917 * @param[in] wq_ctx 918 * Pointer to WQ context to fill with data. 919 * @param [in] wq_attr 920 * Pointer to WQ attributes structure to fill in WQ context. 921 */ 922 static void 923 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr) 924 { 925 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type); 926 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature); 927 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode); 928 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave); 929 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge); 930 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size); 931 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset); 932 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm); 933 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd); 934 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page); 935 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr); 936 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter); 937 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter); 938 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride); 939 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT) 940 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, 941 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT); 942 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz); 943 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid); 944 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid); 945 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets, 946 wq_attr->log_hairpin_num_packets); 947 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz); 948 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides, 949 wq_attr->single_wqe_log_num_of_strides); 950 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en); 951 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes, 952 wq_attr->single_stride_log_num_of_bytes); 953 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id); 954 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id); 955 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset); 956 } 957 958 /** 959 * Create RQ using DevX API. 960 * 961 * @param[in] ctx 962 * Context returned from mlx5 open_device() glue function. 963 * @param [in] rq_attr 964 * Pointer to create RQ attributes structure. 965 * @param [in] socket 966 * CPU socket ID for allocations. 967 * 968 * @return 969 * The DevX object created, NULL otherwise and rte_errno is set. 970 */ 971 struct mlx5_devx_obj * 972 mlx5_devx_cmd_create_rq(void *ctx, 973 struct mlx5_devx_create_rq_attr *rq_attr, 974 int socket) 975 { 976 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0}; 977 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; 978 void *rq_ctx, *wq_ctx; 979 struct mlx5_devx_wq_attr *wq_attr; 980 struct mlx5_devx_obj *rq = NULL; 981 982 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket); 983 if (!rq) { 984 DRV_LOG(ERR, "Failed to allocate RQ data"); 985 rte_errno = ENOMEM; 986 return NULL; 987 } 988 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ); 989 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx); 990 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky); 991 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en); 992 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 993 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 994 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type); 995 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 996 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en); 997 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin); 998 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index); 999 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn); 1000 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1001 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn); 1002 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1003 wq_attr = &rq_attr->wq_attr; 1004 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1005 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1006 out, sizeof(out)); 1007 if (!rq->obj) { 1008 DRV_LOG(ERR, "Failed to create RQ using DevX"); 1009 rte_errno = errno; 1010 mlx5_free(rq); 1011 return NULL; 1012 } 1013 rq->id = MLX5_GET(create_rq_out, out, rqn); 1014 return rq; 1015 } 1016 1017 /** 1018 * Modify RQ using DevX API. 1019 * 1020 * @param[in] rq 1021 * Pointer to RQ object structure. 1022 * @param [in] rq_attr 1023 * Pointer to modify RQ attributes structure. 1024 * 1025 * @return 1026 * 0 on success, a negative errno value otherwise and rte_errno is set. 1027 */ 1028 int 1029 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq, 1030 struct mlx5_devx_modify_rq_attr *rq_attr) 1031 { 1032 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0}; 1033 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0}; 1034 void *rq_ctx, *wq_ctx; 1035 int ret; 1036 1037 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ); 1038 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state); 1039 MLX5_SET(modify_rq_in, in, rqn, rq->id); 1040 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask); 1041 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1042 MLX5_SET(rqc, rq_ctx, state, rq_attr->state); 1043 if (rq_attr->modify_bitmask & 1044 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS) 1045 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs); 1046 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD) 1047 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd); 1048 if (rq_attr->modify_bitmask & 1049 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID) 1050 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id); 1051 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq); 1052 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca); 1053 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) { 1054 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq); 1055 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm); 1056 } 1057 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in), 1058 out, sizeof(out)); 1059 if (ret) { 1060 DRV_LOG(ERR, "Failed to modify RQ using DevX"); 1061 rte_errno = errno; 1062 return -errno; 1063 } 1064 return ret; 1065 } 1066 1067 /** 1068 * Create TIR using DevX API. 1069 * 1070 * @param[in] ctx 1071 * Context returned from mlx5 open_device() glue function. 1072 * @param [in] tir_attr 1073 * Pointer to TIR attributes structure. 1074 * 1075 * @return 1076 * The DevX object created, NULL otherwise and rte_errno is set. 1077 */ 1078 struct mlx5_devx_obj * 1079 mlx5_devx_cmd_create_tir(void *ctx, 1080 struct mlx5_devx_tir_attr *tir_attr) 1081 { 1082 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; 1083 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0}; 1084 void *tir_ctx, *outer, *inner, *rss_key; 1085 struct mlx5_devx_obj *tir = NULL; 1086 1087 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY); 1088 if (!tir) { 1089 DRV_LOG(ERR, "Failed to allocate TIR data"); 1090 rte_errno = ENOMEM; 1091 return NULL; 1092 } 1093 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR); 1094 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx); 1095 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type); 1096 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1097 tir_attr->lro_timeout_period_usecs); 1098 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask); 1099 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz); 1100 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn); 1101 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric); 1102 MLX5_SET(tirc, tir_ctx, tunneled_offload_en, 1103 tir_attr->tunneled_offload_en); 1104 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table); 1105 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1106 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1107 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain); 1108 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key); 1109 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN); 1110 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer); 1111 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1112 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1113 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1114 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1115 MLX5_SET(rx_hash_field_select, outer, selected_fields, 1116 tir_attr->rx_hash_field_selector_outer.selected_fields); 1117 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner); 1118 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1119 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1120 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1121 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1122 MLX5_SET(rx_hash_field_select, inner, selected_fields, 1123 tir_attr->rx_hash_field_selector_inner.selected_fields); 1124 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1125 out, sizeof(out)); 1126 if (!tir->obj) { 1127 DRV_LOG(ERR, "Failed to create TIR using DevX"); 1128 rte_errno = errno; 1129 mlx5_free(tir); 1130 return NULL; 1131 } 1132 tir->id = MLX5_GET(create_tir_out, out, tirn); 1133 return tir; 1134 } 1135 1136 /** 1137 * Modify TIR using DevX API. 1138 * 1139 * @param[in] tir 1140 * Pointer to TIR DevX object structure. 1141 * @param [in] modify_tir_attr 1142 * Pointer to TIR modification attributes structure. 1143 * 1144 * @return 1145 * 0 on success, a negative errno value otherwise and rte_errno is set. 1146 */ 1147 int 1148 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, 1149 struct mlx5_devx_modify_tir_attr *modify_tir_attr) 1150 { 1151 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir; 1152 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0}; 1153 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0}; 1154 void *tir_ctx; 1155 int ret; 1156 1157 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR); 1158 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn); 1159 MLX5_SET64(modify_tir_in, in, modify_bitmask, 1160 modify_tir_attr->modify_bitmask); 1161 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx); 1162 if (modify_tir_attr->modify_bitmask & 1163 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) { 1164 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs, 1165 tir_attr->lro_timeout_period_usecs); 1166 MLX5_SET(tirc, tir_ctx, lro_enable_mask, 1167 tir_attr->lro_enable_mask); 1168 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, 1169 tir_attr->lro_max_msg_sz); 1170 } 1171 if (modify_tir_attr->modify_bitmask & 1172 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE) 1173 MLX5_SET(tirc, tir_ctx, indirect_table, 1174 tir_attr->indirect_table); 1175 if (modify_tir_attr->modify_bitmask & 1176 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) { 1177 int i; 1178 void *outer, *inner; 1179 1180 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, 1181 tir_attr->rx_hash_symmetric); 1182 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn); 1183 for (i = 0; i < 10; i++) { 1184 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i], 1185 tir_attr->rx_hash_toeplitz_key[i]); 1186 } 1187 outer = MLX5_ADDR_OF(tirc, tir_ctx, 1188 rx_hash_field_selector_outer); 1189 MLX5_SET(rx_hash_field_select, outer, l3_prot_type, 1190 tir_attr->rx_hash_field_selector_outer.l3_prot_type); 1191 MLX5_SET(rx_hash_field_select, outer, l4_prot_type, 1192 tir_attr->rx_hash_field_selector_outer.l4_prot_type); 1193 MLX5_SET 1194 (rx_hash_field_select, outer, selected_fields, 1195 tir_attr->rx_hash_field_selector_outer.selected_fields); 1196 inner = MLX5_ADDR_OF(tirc, tir_ctx, 1197 rx_hash_field_selector_inner); 1198 MLX5_SET(rx_hash_field_select, inner, l3_prot_type, 1199 tir_attr->rx_hash_field_selector_inner.l3_prot_type); 1200 MLX5_SET(rx_hash_field_select, inner, l4_prot_type, 1201 tir_attr->rx_hash_field_selector_inner.l4_prot_type); 1202 MLX5_SET 1203 (rx_hash_field_select, inner, selected_fields, 1204 tir_attr->rx_hash_field_selector_inner.selected_fields); 1205 } 1206 if (modify_tir_attr->modify_bitmask & 1207 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) { 1208 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block); 1209 } 1210 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in), 1211 out, sizeof(out)); 1212 if (ret) { 1213 DRV_LOG(ERR, "Failed to modify TIR using DevX"); 1214 rte_errno = errno; 1215 return -errno; 1216 } 1217 return ret; 1218 } 1219 1220 /** 1221 * Create RQT using DevX API. 1222 * 1223 * @param[in] ctx 1224 * Context returned from mlx5 open_device() glue function. 1225 * @param [in] rqt_attr 1226 * Pointer to RQT attributes structure. 1227 * 1228 * @return 1229 * The DevX object created, NULL otherwise and rte_errno is set. 1230 */ 1231 struct mlx5_devx_obj * 1232 mlx5_devx_cmd_create_rqt(void *ctx, 1233 struct mlx5_devx_rqt_attr *rqt_attr) 1234 { 1235 uint32_t *in = NULL; 1236 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + 1237 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1238 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0}; 1239 void *rqt_ctx; 1240 struct mlx5_devx_obj *rqt = NULL; 1241 int i; 1242 1243 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1244 if (!in) { 1245 DRV_LOG(ERR, "Failed to allocate RQT IN data"); 1246 rte_errno = ENOMEM; 1247 return NULL; 1248 } 1249 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY); 1250 if (!rqt) { 1251 DRV_LOG(ERR, "Failed to allocate RQT data"); 1252 rte_errno = ENOMEM; 1253 mlx5_free(in); 1254 return NULL; 1255 } 1256 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT); 1257 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); 1258 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1259 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1260 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1261 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1262 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1263 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out)); 1264 mlx5_free(in); 1265 if (!rqt->obj) { 1266 DRV_LOG(ERR, "Failed to create RQT using DevX"); 1267 rte_errno = errno; 1268 mlx5_free(rqt); 1269 return NULL; 1270 } 1271 rqt->id = MLX5_GET(create_rqt_out, out, rqtn); 1272 return rqt; 1273 } 1274 1275 /** 1276 * Modify RQT using DevX API. 1277 * 1278 * @param[in] rqt 1279 * Pointer to RQT DevX object structure. 1280 * @param [in] rqt_attr 1281 * Pointer to RQT attributes structure. 1282 * 1283 * @return 1284 * 0 on success, a negative errno value otherwise and rte_errno is set. 1285 */ 1286 int 1287 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt, 1288 struct mlx5_devx_rqt_attr *rqt_attr) 1289 { 1290 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + 1291 rqt_attr->rqt_actual_size * sizeof(uint32_t); 1292 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0}; 1293 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY); 1294 void *rqt_ctx; 1295 int i; 1296 int ret; 1297 1298 if (!in) { 1299 DRV_LOG(ERR, "Failed to allocate RQT modify IN data."); 1300 rte_errno = ENOMEM; 1301 return -ENOMEM; 1302 } 1303 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT); 1304 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id); 1305 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1); 1306 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context); 1307 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type); 1308 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size); 1309 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size); 1310 for (i = 0; i < rqt_attr->rqt_actual_size; i++) 1311 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]); 1312 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out)); 1313 mlx5_free(in); 1314 if (ret) { 1315 DRV_LOG(ERR, "Failed to modify RQT using DevX."); 1316 rte_errno = errno; 1317 return -rte_errno; 1318 } 1319 return ret; 1320 } 1321 1322 /** 1323 * Create SQ using DevX API. 1324 * 1325 * @param[in] ctx 1326 * Context returned from mlx5 open_device() glue function. 1327 * @param [in] sq_attr 1328 * Pointer to SQ attributes structure. 1329 * @param [in] socket 1330 * CPU socket ID for allocations. 1331 * 1332 * @return 1333 * The DevX object created, NULL otherwise and rte_errno is set. 1334 **/ 1335 struct mlx5_devx_obj * 1336 mlx5_devx_cmd_create_sq(void *ctx, 1337 struct mlx5_devx_create_sq_attr *sq_attr) 1338 { 1339 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0}; 1340 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; 1341 void *sq_ctx; 1342 void *wq_ctx; 1343 struct mlx5_devx_wq_attr *wq_attr; 1344 struct mlx5_devx_obj *sq = NULL; 1345 1346 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY); 1347 if (!sq) { 1348 DRV_LOG(ERR, "Failed to allocate SQ data"); 1349 rte_errno = ENOMEM; 1350 return NULL; 1351 } 1352 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ); 1353 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx); 1354 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky); 1355 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master); 1356 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre); 1357 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en); 1358 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe, 1359 sq_attr->allow_multi_pkt_send_wqe); 1360 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode, 1361 sq_attr->min_wqe_inline_mode); 1362 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1363 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr); 1364 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp); 1365 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin); 1366 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire); 1367 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq); 1368 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index); 1369 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn); 1370 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index, 1371 sq_attr->packet_pacing_rate_limit_index); 1372 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz); 1373 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num); 1374 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq); 1375 wq_attr = &sq_attr->wq_attr; 1376 devx_cmd_fill_wq_data(wq_ctx, wq_attr); 1377 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1378 out, sizeof(out)); 1379 if (!sq->obj) { 1380 DRV_LOG(ERR, "Failed to create SQ using DevX"); 1381 rte_errno = errno; 1382 mlx5_free(sq); 1383 return NULL; 1384 } 1385 sq->id = MLX5_GET(create_sq_out, out, sqn); 1386 return sq; 1387 } 1388 1389 /** 1390 * Modify SQ using DevX API. 1391 * 1392 * @param[in] sq 1393 * Pointer to SQ object structure. 1394 * @param [in] sq_attr 1395 * Pointer to SQ attributes structure. 1396 * 1397 * @return 1398 * 0 on success, a negative errno value otherwise and rte_errno is set. 1399 */ 1400 int 1401 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq, 1402 struct mlx5_devx_modify_sq_attr *sq_attr) 1403 { 1404 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0}; 1405 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0}; 1406 void *sq_ctx; 1407 int ret; 1408 1409 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ); 1410 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state); 1411 MLX5_SET(modify_sq_in, in, sqn, sq->id); 1412 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx); 1413 MLX5_SET(sqc, sq_ctx, state, sq_attr->state); 1414 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq); 1415 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca); 1416 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in), 1417 out, sizeof(out)); 1418 if (ret) { 1419 DRV_LOG(ERR, "Failed to modify SQ using DevX"); 1420 rte_errno = errno; 1421 return -rte_errno; 1422 } 1423 return ret; 1424 } 1425 1426 /** 1427 * Create TIS using DevX API. 1428 * 1429 * @param[in] ctx 1430 * Context returned from mlx5 open_device() glue function. 1431 * @param [in] tis_attr 1432 * Pointer to TIS attributes structure. 1433 * 1434 * @return 1435 * The DevX object created, NULL otherwise and rte_errno is set. 1436 */ 1437 struct mlx5_devx_obj * 1438 mlx5_devx_cmd_create_tis(void *ctx, 1439 struct mlx5_devx_tis_attr *tis_attr) 1440 { 1441 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; 1442 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0}; 1443 struct mlx5_devx_obj *tis = NULL; 1444 void *tis_ctx; 1445 1446 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY); 1447 if (!tis) { 1448 DRV_LOG(ERR, "Failed to allocate TIS object"); 1449 rte_errno = ENOMEM; 1450 return NULL; 1451 } 1452 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS); 1453 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx); 1454 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity, 1455 tis_attr->strict_lag_tx_port_affinity); 1456 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity, 1457 tis_attr->lag_tx_port_affinity); 1458 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio); 1459 MLX5_SET(tisc, tis_ctx, transport_domain, 1460 tis_attr->transport_domain); 1461 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1462 out, sizeof(out)); 1463 if (!tis->obj) { 1464 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1465 rte_errno = errno; 1466 mlx5_free(tis); 1467 return NULL; 1468 } 1469 tis->id = MLX5_GET(create_tis_out, out, tisn); 1470 return tis; 1471 } 1472 1473 /** 1474 * Create transport domain using DevX API. 1475 * 1476 * @param[in] ctx 1477 * Context returned from mlx5 open_device() glue function. 1478 * @return 1479 * The DevX object created, NULL otherwise and rte_errno is set. 1480 */ 1481 struct mlx5_devx_obj * 1482 mlx5_devx_cmd_create_td(void *ctx) 1483 { 1484 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; 1485 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; 1486 struct mlx5_devx_obj *td = NULL; 1487 1488 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY); 1489 if (!td) { 1490 DRV_LOG(ERR, "Failed to allocate TD object"); 1491 rte_errno = ENOMEM; 1492 return NULL; 1493 } 1494 MLX5_SET(alloc_transport_domain_in, in, opcode, 1495 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN); 1496 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 1497 out, sizeof(out)); 1498 if (!td->obj) { 1499 DRV_LOG(ERR, "Failed to create TIS using DevX"); 1500 rte_errno = errno; 1501 mlx5_free(td); 1502 return NULL; 1503 } 1504 td->id = MLX5_GET(alloc_transport_domain_out, out, 1505 transport_domain); 1506 return td; 1507 } 1508 1509 /** 1510 * Dump all flows to file. 1511 * 1512 * @param[in] fdb_domain 1513 * FDB domain. 1514 * @param[in] rx_domain 1515 * RX domain. 1516 * @param[in] tx_domain 1517 * TX domain. 1518 * @param[out] file 1519 * Pointer to file stream. 1520 * 1521 * @return 1522 * 0 on success, a nagative value otherwise. 1523 */ 1524 int 1525 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused, 1526 void *rx_domain __rte_unused, 1527 void *tx_domain __rte_unused, FILE *file __rte_unused) 1528 { 1529 int ret = 0; 1530 1531 #ifdef HAVE_MLX5_DR_FLOW_DUMP 1532 if (fdb_domain) { 1533 ret = mlx5_glue->dr_dump_domain(file, fdb_domain); 1534 if (ret) 1535 return ret; 1536 } 1537 MLX5_ASSERT(rx_domain); 1538 ret = mlx5_glue->dr_dump_domain(file, rx_domain); 1539 if (ret) 1540 return ret; 1541 MLX5_ASSERT(tx_domain); 1542 ret = mlx5_glue->dr_dump_domain(file, tx_domain); 1543 #else 1544 ret = ENOTSUP; 1545 #endif 1546 return -ret; 1547 } 1548 1549 /* 1550 * Create CQ using DevX API. 1551 * 1552 * @param[in] ctx 1553 * Context returned from mlx5 open_device() glue function. 1554 * @param [in] attr 1555 * Pointer to CQ attributes structure. 1556 * 1557 * @return 1558 * The DevX object created, NULL otherwise and rte_errno is set. 1559 */ 1560 struct mlx5_devx_obj * 1561 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr) 1562 { 1563 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0}; 1564 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0}; 1565 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1566 sizeof(*cq_obj), 1567 0, SOCKET_ID_ANY); 1568 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context); 1569 1570 if (!cq_obj) { 1571 DRV_LOG(ERR, "Failed to allocate CQ object memory."); 1572 rte_errno = ENOMEM; 1573 return NULL; 1574 } 1575 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ); 1576 if (attr->db_umem_valid) { 1577 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid); 1578 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id); 1579 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset); 1580 } else { 1581 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr); 1582 } 1583 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ? 1584 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B); 1585 MLX5_SET(cqc, cqctx, cc, attr->use_first_only); 1586 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore); 1587 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size); 1588 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1589 MLX5_SET(cqc, cqctx, log_page_size, 1590 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1591 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn); 1592 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id); 1593 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en); 1594 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format); 1595 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext, 1596 attr->mini_cqe_res_format_ext); 1597 if (attr->q_umem_valid) { 1598 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid); 1599 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id); 1600 MLX5_SET64(create_cq_in, in, cq_umem_offset, 1601 attr->q_umem_offset); 1602 } 1603 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1604 sizeof(out)); 1605 if (!cq_obj->obj) { 1606 rte_errno = errno; 1607 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno); 1608 mlx5_free(cq_obj); 1609 return NULL; 1610 } 1611 cq_obj->id = MLX5_GET(create_cq_out, out, cqn); 1612 return cq_obj; 1613 } 1614 1615 /** 1616 * Create VIRTQ using DevX API. 1617 * 1618 * @param[in] ctx 1619 * Context returned from mlx5 open_device() glue function. 1620 * @param [in] attr 1621 * Pointer to VIRTQ attributes structure. 1622 * 1623 * @return 1624 * The DevX object created, NULL otherwise and rte_errno is set. 1625 */ 1626 struct mlx5_devx_obj * 1627 mlx5_devx_cmd_create_virtq(void *ctx, 1628 struct mlx5_devx_virtq_attr *attr) 1629 { 1630 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1631 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1632 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO, 1633 sizeof(*virtq_obj), 1634 0, SOCKET_ID_ANY); 1635 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1636 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1637 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1638 1639 if (!virtq_obj) { 1640 DRV_LOG(ERR, "Failed to allocate virtq data."); 1641 rte_errno = ENOMEM; 1642 return NULL; 1643 } 1644 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1645 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1646 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1647 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1648 MLX5_SET16(virtio_net_q, virtq, hw_available_index, 1649 attr->hw_available_index); 1650 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index); 1651 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4); 1652 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6); 1653 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum); 1654 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum); 1655 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0, 1656 attr->virtio_version_1_0); 1657 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode); 1658 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id); 1659 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr); 1660 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr); 1661 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr); 1662 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1663 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size); 1664 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey); 1665 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id); 1666 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size); 1667 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset); 1668 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id); 1669 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size); 1670 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset); 1671 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id); 1672 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size); 1673 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset); 1674 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id); 1675 MLX5_SET(virtio_q, virtctx, pd, attr->pd); 1676 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode); 1677 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us); 1678 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp); 1679 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id); 1680 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1681 sizeof(out)); 1682 if (!virtq_obj->obj) { 1683 rte_errno = errno; 1684 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX."); 1685 mlx5_free(virtq_obj); 1686 return NULL; 1687 } 1688 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1689 return virtq_obj; 1690 } 1691 1692 /** 1693 * Modify VIRTQ using DevX API. 1694 * 1695 * @param[in] virtq_obj 1696 * Pointer to virtq object structure. 1697 * @param [in] attr 1698 * Pointer to modify virtq attributes structure. 1699 * 1700 * @return 1701 * 0 on success, a negative errno value otherwise and rte_errno is set. 1702 */ 1703 int 1704 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj, 1705 struct mlx5_devx_virtq_attr *attr) 1706 { 1707 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0}; 1708 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1709 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq); 1710 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr); 1711 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context); 1712 int ret; 1713 1714 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1715 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT); 1716 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1717 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1718 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1719 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type); 1720 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index); 1721 switch (attr->type) { 1722 case MLX5_VIRTQ_MODIFY_TYPE_STATE: 1723 MLX5_SET16(virtio_net_q, virtq, state, attr->state); 1724 break; 1725 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS: 1726 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey, 1727 attr->dirty_bitmap_mkey); 1728 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr, 1729 attr->dirty_bitmap_addr); 1730 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size, 1731 attr->dirty_bitmap_size); 1732 break; 1733 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE: 1734 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable, 1735 attr->dirty_bitmap_dump_enable); 1736 break; 1737 default: 1738 rte_errno = EINVAL; 1739 return -rte_errno; 1740 } 1741 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in), 1742 out, sizeof(out)); 1743 if (ret) { 1744 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1745 rte_errno = errno; 1746 return -rte_errno; 1747 } 1748 return ret; 1749 } 1750 1751 /** 1752 * Query VIRTQ using DevX API. 1753 * 1754 * @param[in] virtq_obj 1755 * Pointer to virtq object structure. 1756 * @param [in/out] attr 1757 * Pointer to virtq attributes structure. 1758 * 1759 * @return 1760 * 0 on success, a negative errno value otherwise and rte_errno is set. 1761 */ 1762 int 1763 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj, 1764 struct mlx5_devx_virtq_attr *attr) 1765 { 1766 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1767 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0}; 1768 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr); 1769 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq); 1770 int ret; 1771 1772 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1773 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 1774 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1775 MLX5_GENERAL_OBJ_TYPE_VIRTQ); 1776 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id); 1777 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in), 1778 out, sizeof(out)); 1779 if (ret) { 1780 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX."); 1781 rte_errno = errno; 1782 return -errno; 1783 } 1784 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq, 1785 hw_available_index); 1786 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index); 1787 attr->state = MLX5_GET16(virtio_net_q, virtq, state); 1788 attr->error_type = MLX5_GET16(virtio_net_q, virtq, 1789 virtio_q_context.error_type); 1790 return ret; 1791 } 1792 1793 /** 1794 * Create QP using DevX API. 1795 * 1796 * @param[in] ctx 1797 * Context returned from mlx5 open_device() glue function. 1798 * @param [in] attr 1799 * Pointer to QP attributes structure. 1800 * 1801 * @return 1802 * The DevX object created, NULL otherwise and rte_errno is set. 1803 */ 1804 struct mlx5_devx_obj * 1805 mlx5_devx_cmd_create_qp(void *ctx, 1806 struct mlx5_devx_qp_attr *attr) 1807 { 1808 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0}; 1809 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; 1810 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO, 1811 sizeof(*qp_obj), 1812 0, SOCKET_ID_ANY); 1813 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); 1814 1815 if (!qp_obj) { 1816 DRV_LOG(ERR, "Failed to allocate QP data."); 1817 rte_errno = ENOMEM; 1818 return NULL; 1819 } 1820 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); 1821 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); 1822 MLX5_SET(qpc, qpc, pd, attr->pd); 1823 if (attr->uar_index) { 1824 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1825 MLX5_SET(qpc, qpc, uar_page, attr->uar_index); 1826 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT) 1827 MLX5_SET(qpc, qpc, log_page_size, 1828 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT); 1829 if (attr->sq_size) { 1830 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size)); 1831 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn); 1832 MLX5_SET(qpc, qpc, log_sq_size, 1833 rte_log2_u32(attr->sq_size)); 1834 } else { 1835 MLX5_SET(qpc, qpc, no_sq, 1); 1836 } 1837 if (attr->rq_size) { 1838 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size)); 1839 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn); 1840 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride - 1841 MLX5_LOG_RQ_STRIDE_SHIFT); 1842 MLX5_SET(qpc, qpc, log_rq_size, 1843 rte_log2_u32(attr->rq_size)); 1844 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ); 1845 } else { 1846 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1847 } 1848 if (attr->dbr_umem_valid) { 1849 MLX5_SET(qpc, qpc, dbr_umem_valid, 1850 attr->dbr_umem_valid); 1851 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id); 1852 } 1853 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address); 1854 MLX5_SET64(create_qp_in, in, wq_umem_offset, 1855 attr->wq_umem_offset); 1856 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id); 1857 MLX5_SET(create_qp_in, in, wq_umem_valid, 1); 1858 } else { 1859 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */ 1860 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ); 1861 MLX5_SET(qpc, qpc, no_sq, 1); 1862 } 1863 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1864 sizeof(out)); 1865 if (!qp_obj->obj) { 1866 rte_errno = errno; 1867 DRV_LOG(ERR, "Failed to create QP Obj using DevX."); 1868 mlx5_free(qp_obj); 1869 return NULL; 1870 } 1871 qp_obj->id = MLX5_GET(create_qp_out, out, qpn); 1872 return qp_obj; 1873 } 1874 1875 /** 1876 * Modify QP using DevX API. 1877 * Currently supports only force loop-back QP. 1878 * 1879 * @param[in] qp 1880 * Pointer to QP object structure. 1881 * @param [in] qp_st_mod_op 1882 * The QP state modification operation. 1883 * @param [in] remote_qp_id 1884 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation. 1885 * 1886 * @return 1887 * 0 on success, a negative errno value otherwise and rte_errno is set. 1888 */ 1889 int 1890 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op, 1891 uint32_t remote_qp_id) 1892 { 1893 union { 1894 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)]; 1895 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)]; 1896 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)]; 1897 } in; 1898 union { 1899 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)]; 1900 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)]; 1901 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)]; 1902 } out; 1903 void *qpc; 1904 int ret; 1905 unsigned int inlen; 1906 unsigned int outlen; 1907 1908 memset(&in, 0, sizeof(in)); 1909 memset(&out, 0, sizeof(out)); 1910 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op); 1911 switch (qp_st_mod_op) { 1912 case MLX5_CMD_OP_RST2INIT_QP: 1913 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id); 1914 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc); 1915 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1916 MLX5_SET(qpc, qpc, rre, 1); 1917 MLX5_SET(qpc, qpc, rwe, 1); 1918 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); 1919 inlen = sizeof(in.rst2init); 1920 outlen = sizeof(out.rst2init); 1921 break; 1922 case MLX5_CMD_OP_INIT2RTR_QP: 1923 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id); 1924 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc); 1925 MLX5_SET(qpc, qpc, primary_address_path.fl, 1); 1926 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1); 1927 MLX5_SET(qpc, qpc, mtu, 1); 1928 MLX5_SET(qpc, qpc, log_msg_max, 30); 1929 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id); 1930 MLX5_SET(qpc, qpc, min_rnr_nak, 0); 1931 inlen = sizeof(in.init2rtr); 1932 outlen = sizeof(out.init2rtr); 1933 break; 1934 case MLX5_CMD_OP_RTR2RTS_QP: 1935 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc); 1936 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id); 1937 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14); 1938 MLX5_SET(qpc, qpc, log_ack_req_freq, 0); 1939 MLX5_SET(qpc, qpc, retry_count, 7); 1940 MLX5_SET(qpc, qpc, rnr_retry, 7); 1941 inlen = sizeof(in.rtr2rts); 1942 outlen = sizeof(out.rtr2rts); 1943 break; 1944 default: 1945 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.", 1946 qp_st_mod_op); 1947 rte_errno = EINVAL; 1948 return -rte_errno; 1949 } 1950 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen); 1951 if (ret) { 1952 DRV_LOG(ERR, "Failed to modify QP using DevX."); 1953 rte_errno = errno; 1954 return -rte_errno; 1955 } 1956 return ret; 1957 } 1958 1959 struct mlx5_devx_obj * 1960 mlx5_devx_cmd_create_virtio_q_counters(void *ctx) 1961 { 1962 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0}; 1963 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 1964 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO, 1965 sizeof(*couners_obj), 0, 1966 SOCKET_ID_ANY); 1967 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr); 1968 1969 if (!couners_obj) { 1970 DRV_LOG(ERR, "Failed to allocate virtio queue counters data."); 1971 rte_errno = ENOMEM; 1972 return NULL; 1973 } 1974 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 1975 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 1976 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 1977 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 1978 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out, 1979 sizeof(out)); 1980 if (!couners_obj->obj) { 1981 rte_errno = errno; 1982 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using" 1983 " DevX."); 1984 mlx5_free(couners_obj); 1985 return NULL; 1986 } 1987 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 1988 return couners_obj; 1989 } 1990 1991 int 1992 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj, 1993 struct mlx5_devx_virtio_q_couners_attr *attr) 1994 { 1995 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; 1996 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0}; 1997 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr); 1998 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out, 1999 virtio_q_counters); 2000 int ret; 2001 2002 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2003 MLX5_CMD_OP_QUERY_GENERAL_OBJECT); 2004 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2005 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS); 2006 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id); 2007 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out, 2008 sizeof(out)); 2009 if (ret) { 2010 DRV_LOG(ERR, "Failed to query virtio q counters using DevX."); 2011 rte_errno = errno; 2012 return -errno; 2013 } 2014 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2015 received_desc); 2016 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters, 2017 completed_desc); 2018 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters, 2019 error_cqes); 2020 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters, 2021 bad_desc_errors); 2022 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters, 2023 exceed_max_chain); 2024 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters, 2025 invalid_buffer); 2026 return ret; 2027 } 2028 2029 /** 2030 * Create general object of type FLOW_HIT_ASO using DevX API. 2031 * 2032 * @param[in] ctx 2033 * Context returned from mlx5 open_device() glue function. 2034 * @param [in] pd 2035 * PD value to associate the FLOW_HIT_ASO object with. 2036 * 2037 * @return 2038 * The DevX object created, NULL otherwise and rte_errno is set. 2039 */ 2040 struct mlx5_devx_obj * 2041 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd) 2042 { 2043 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0}; 2044 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2045 struct mlx5_devx_obj *flow_hit_aso_obj = NULL; 2046 void *ptr = NULL; 2047 2048 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj), 2049 0, SOCKET_ID_ANY); 2050 if (!flow_hit_aso_obj) { 2051 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data"); 2052 rte_errno = ENOMEM; 2053 return NULL; 2054 } 2055 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr); 2056 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode, 2057 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2058 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type, 2059 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO); 2060 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso); 2061 MLX5_SET(flow_hit_aso, ptr, access_pd, pd); 2062 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2063 out, sizeof(out)); 2064 if (!flow_hit_aso_obj->obj) { 2065 rte_errno = errno; 2066 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX."); 2067 mlx5_free(flow_hit_aso_obj); 2068 return NULL; 2069 } 2070 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2071 return flow_hit_aso_obj; 2072 } 2073 2074 /* 2075 * Create PD using DevX API. 2076 * 2077 * @param[in] ctx 2078 * Context returned from mlx5 open_device() glue function. 2079 * 2080 * @return 2081 * The DevX object created, NULL otherwise and rte_errno is set. 2082 */ 2083 struct mlx5_devx_obj * 2084 mlx5_devx_cmd_alloc_pd(void *ctx) 2085 { 2086 struct mlx5_devx_obj *ppd = 2087 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY); 2088 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; 2089 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; 2090 2091 if (!ppd) { 2092 DRV_LOG(ERR, "Failed to allocate PD data."); 2093 rte_errno = ENOMEM; 2094 return NULL; 2095 } 2096 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2097 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), 2098 out, sizeof(out)); 2099 if (!ppd->obj) { 2100 mlx5_free(ppd); 2101 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX."); 2102 rte_errno = errno; 2103 return NULL; 2104 } 2105 ppd->id = MLX5_GET(alloc_pd_out, out, pd); 2106 return ppd; 2107 } 2108 2109 /** 2110 * Create general object of type GENEVE TLV option using DevX API. 2111 * 2112 * @param[in] ctx 2113 * Context returned from mlx5 open_device() glue function. 2114 * @param [in] class 2115 * TLV option variable value of class 2116 * @param [in] type 2117 * TLV option variable value of type 2118 * @param [in] len 2119 * TLV option variable value of len 2120 * 2121 * @return 2122 * The DevX object created, NULL otherwise and rte_errno is set. 2123 */ 2124 struct mlx5_devx_obj * 2125 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx, 2126 uint16_t class, uint8_t type, uint8_t len) 2127 { 2128 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0}; 2129 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0}; 2130 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO, 2131 sizeof(*geneve_tlv_opt_obj), 2132 0, SOCKET_ID_ANY); 2133 2134 if (!geneve_tlv_opt_obj) { 2135 DRV_LOG(ERR, "Failed to allocate geneve tlv option object."); 2136 rte_errno = ENOMEM; 2137 return NULL; 2138 } 2139 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr); 2140 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, 2141 geneve_tlv_opt); 2142 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode, 2143 MLX5_CMD_OP_CREATE_GENERAL_OBJECT); 2144 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type, 2145 MLX5_OBJ_TYPE_GENEVE_TLV_OPT); 2146 MLX5_SET(geneve_tlv_option, opt, option_class, 2147 rte_be_to_cpu_16(class)); 2148 MLX5_SET(geneve_tlv_option, opt, option_type, type); 2149 MLX5_SET(geneve_tlv_option, opt, option_data_length, len); 2150 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in, 2151 sizeof(in), out, sizeof(out)); 2152 if (!geneve_tlv_opt_obj->obj) { 2153 rte_errno = errno; 2154 DRV_LOG(ERR, "Failed to create Geneve tlv option " 2155 "Obj using DevX."); 2156 mlx5_free(geneve_tlv_opt_obj); 2157 return NULL; 2158 } 2159 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id); 2160 return geneve_tlv_opt_obj; 2161 } 2162 2163